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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.60 96.97 93.02 97.88 100.00 98.37 97.89 99.07


Total test records in report: 471
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T304 /workspace/coverage/default/41.rom_ctrl_smoke.4249272507 May 26 02:00:34 PM PDT 24 May 26 02:01:24 PM PDT 24 59130337573 ps
T305 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.63135785 May 26 01:59:23 PM PDT 24 May 26 01:59:38 PM PDT 24 674050091 ps
T306 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2802615123 May 26 01:59:57 PM PDT 24 May 26 02:05:05 PM PDT 24 65389685842 ps
T307 /workspace/coverage/default/24.rom_ctrl_stress_all.3997103330 May 26 01:59:56 PM PDT 24 May 26 02:00:16 PM PDT 24 2455255860 ps
T308 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2026170348 May 26 02:00:16 PM PDT 24 May 26 02:00:46 PM PDT 24 697450726 ps
T309 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3881497447 May 26 02:00:16 PM PDT 24 May 26 02:03:01 PM PDT 24 3464337546 ps
T310 /workspace/coverage/default/26.rom_ctrl_alert_test.1259075494 May 26 02:00:03 PM PDT 24 May 26 02:00:25 PM PDT 24 2471211692 ps
T311 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2799887711 May 26 02:00:24 PM PDT 24 May 26 02:26:01 PM PDT 24 38331952945 ps
T312 /workspace/coverage/default/21.rom_ctrl_alert_test.413643578 May 26 01:59:57 PM PDT 24 May 26 02:00:19 PM PDT 24 7952828042 ps
T313 /workspace/coverage/default/14.rom_ctrl_smoke.1154995457 May 26 01:59:39 PM PDT 24 May 26 02:00:21 PM PDT 24 41025585132 ps
T314 /workspace/coverage/default/49.rom_ctrl_smoke.1766498644 May 26 02:00:49 PM PDT 24 May 26 02:01:11 PM PDT 24 186162237 ps
T315 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2510766512 May 26 01:59:42 PM PDT 24 May 26 01:59:54 PM PDT 24 7319317915 ps
T316 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4167288601 May 26 01:59:41 PM PDT 24 May 26 02:06:42 PM PDT 24 44033913525 ps
T317 /workspace/coverage/default/40.rom_ctrl_smoke.3924960428 May 26 02:00:29 PM PDT 24 May 26 02:01:17 PM PDT 24 6125417466 ps
T318 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2935921610 May 26 02:00:32 PM PDT 24 May 26 02:01:08 PM PDT 24 822116460 ps
T319 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2044237691 May 26 01:59:25 PM PDT 24 May 26 02:04:09 PM PDT 24 168940226690 ps
T320 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1415012475 May 26 01:59:25 PM PDT 24 May 26 01:59:40 PM PDT 24 1654314754 ps
T321 /workspace/coverage/default/19.rom_ctrl_alert_test.98316567 May 26 01:59:55 PM PDT 24 May 26 02:00:18 PM PDT 24 4225846518 ps
T322 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.82298255 May 26 01:59:57 PM PDT 24 May 26 02:05:01 PM PDT 24 482150756152 ps
T323 /workspace/coverage/default/12.rom_ctrl_stress_all.148468341 May 26 01:59:39 PM PDT 24 May 26 02:00:40 PM PDT 24 5323758476 ps
T324 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2798783525 May 26 02:00:19 PM PDT 24 May 26 02:48:40 PM PDT 24 46762590094 ps
T325 /workspace/coverage/default/23.rom_ctrl_smoke.819765434 May 26 01:59:55 PM PDT 24 May 26 02:00:25 PM PDT 24 25988873072 ps
T326 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3062829569 May 26 01:59:39 PM PDT 24 May 26 02:00:12 PM PDT 24 3782086046 ps
T327 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2601059949 May 26 02:00:08 PM PDT 24 May 26 02:00:35 PM PDT 24 2003464360 ps
T328 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2767257724 May 26 01:59:48 PM PDT 24 May 26 02:06:03 PM PDT 24 80334332120 ps
T329 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2262718637 May 26 01:59:40 PM PDT 24 May 26 02:04:25 PM PDT 24 89100358474 ps
T330 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3229587350 May 26 01:59:15 PM PDT 24 May 26 01:59:31 PM PDT 24 3310714287 ps
T331 /workspace/coverage/default/25.rom_ctrl_stress_all.3913686078 May 26 02:00:05 PM PDT 24 May 26 02:00:34 PM PDT 24 310882043 ps
T332 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1627201506 May 26 02:00:25 PM PDT 24 May 26 02:00:56 PM PDT 24 2584057637 ps
T333 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1514248477 May 26 02:00:35 PM PDT 24 May 26 02:04:29 PM PDT 24 74565206643 ps
T334 /workspace/coverage/default/41.rom_ctrl_alert_test.645673524 May 26 02:00:32 PM PDT 24 May 26 02:00:57 PM PDT 24 86549522 ps
T335 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.258678336 May 26 02:00:40 PM PDT 24 May 26 02:03:13 PM PDT 24 13949367005 ps
T336 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2766887118 May 26 02:00:04 PM PDT 24 May 26 02:00:27 PM PDT 24 168708925 ps
T337 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2820597595 May 26 01:59:56 PM PDT 24 May 26 03:38:18 PM PDT 24 45858415850 ps
T338 /workspace/coverage/default/47.rom_ctrl_stress_all.3647278898 May 26 02:00:43 PM PDT 24 May 26 02:01:25 PM PDT 24 8510222963 ps
T339 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.93369924 May 26 01:59:23 PM PDT 24 May 26 01:59:44 PM PDT 24 3299678732 ps
T340 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1748119548 May 26 01:59:48 PM PDT 24 May 26 02:00:10 PM PDT 24 1833827172 ps
T341 /workspace/coverage/default/23.rom_ctrl_stress_all.1222668447 May 26 01:59:57 PM PDT 24 May 26 02:01:15 PM PDT 24 45856437718 ps
T342 /workspace/coverage/default/45.rom_ctrl_smoke.424410696 May 26 02:00:37 PM PDT 24 May 26 02:01:11 PM PDT 24 3483321374 ps
T343 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1382975932 May 26 02:00:08 PM PDT 24 May 26 04:32:00 PM PDT 24 133968722293 ps
T344 /workspace/coverage/default/3.rom_ctrl_stress_all.2588513496 May 26 01:59:25 PM PDT 24 May 26 02:00:18 PM PDT 24 66616413384 ps
T345 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3873190130 May 26 02:00:05 PM PDT 24 May 26 02:00:35 PM PDT 24 984668862 ps
T346 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3322939060 May 26 01:59:32 PM PDT 24 May 26 02:00:04 PM PDT 24 7654036283 ps
T347 /workspace/coverage/default/28.rom_ctrl_smoke.1100967019 May 26 02:00:03 PM PDT 24 May 26 02:00:31 PM PDT 24 2363100850 ps
T348 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1756020343 May 26 02:00:04 PM PDT 24 May 26 02:02:49 PM PDT 24 2453050278 ps
T349 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2291075238 May 26 02:00:09 PM PDT 24 May 26 02:00:41 PM PDT 24 7518931314 ps
T32 /workspace/coverage/default/0.rom_ctrl_sec_cm.73916781 May 26 01:59:15 PM PDT 24 May 26 02:01:01 PM PDT 24 7305097858 ps
T350 /workspace/coverage/default/36.rom_ctrl_stress_all.2717363750 May 26 02:00:25 PM PDT 24 May 26 02:01:45 PM PDT 24 4778479004 ps
T351 /workspace/coverage/default/36.rom_ctrl_smoke.2681211015 May 26 02:00:29 PM PDT 24 May 26 02:01:00 PM PDT 24 388279413 ps
T352 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3665647522 May 26 01:59:55 PM PDT 24 May 26 02:11:33 PM PDT 24 73366290114 ps
T353 /workspace/coverage/default/38.rom_ctrl_stress_all.3827024324 May 26 02:00:24 PM PDT 24 May 26 02:01:02 PM PDT 24 3997939234 ps
T354 /workspace/coverage/default/15.rom_ctrl_alert_test.2258700552 May 26 01:59:50 PM PDT 24 May 26 02:00:07 PM PDT 24 8034761188 ps
T355 /workspace/coverage/default/5.rom_ctrl_smoke.1622488776 May 26 01:59:23 PM PDT 24 May 26 01:59:44 PM PDT 24 3114920940 ps
T17 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3421650460 May 26 01:59:44 PM PDT 24 May 26 03:34:39 PM PDT 24 519292950372 ps
T356 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1443212082 May 26 02:00:41 PM PDT 24 May 26 02:01:30 PM PDT 24 14686739952 ps
T357 /workspace/coverage/default/2.rom_ctrl_stress_all.2421943198 May 26 01:59:18 PM PDT 24 May 26 01:59:52 PM PDT 24 5561178968 ps
T358 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2347604143 May 26 02:00:26 PM PDT 24 May 26 02:00:55 PM PDT 24 735746631 ps
T359 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1496432647 May 26 02:00:35 PM PDT 24 May 26 02:07:58 PM PDT 24 48349239166 ps
T360 /workspace/coverage/default/49.rom_ctrl_alert_test.16320176 May 26 02:00:49 PM PDT 24 May 26 02:01:17 PM PDT 24 2766112287 ps
T361 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2452498919 May 26 02:00:41 PM PDT 24 May 26 02:01:08 PM PDT 24 790423049 ps
T362 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2425744272 May 26 02:00:31 PM PDT 24 May 26 02:01:01 PM PDT 24 1037484151 ps
T363 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.541349100 May 26 01:59:47 PM PDT 24 May 26 02:03:02 PM PDT 24 35919427920 ps
T364 /workspace/coverage/default/21.rom_ctrl_smoke.352511109 May 26 01:59:59 PM PDT 24 May 26 02:00:48 PM PDT 24 58996776777 ps
T365 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3335768942 May 26 02:00:04 PM PDT 24 May 26 02:04:38 PM PDT 24 12867138438 ps
T366 /workspace/coverage/default/25.rom_ctrl_smoke.3733848116 May 26 02:00:08 PM PDT 24 May 26 02:00:35 PM PDT 24 756107725 ps
T367 /workspace/coverage/default/34.rom_ctrl_smoke.1458107746 May 26 02:00:28 PM PDT 24 May 26 02:01:23 PM PDT 24 8213747009 ps
T368 /workspace/coverage/default/47.rom_ctrl_smoke.2535940793 May 26 02:00:39 PM PDT 24 May 26 02:01:15 PM PDT 24 953037961 ps
T369 /workspace/coverage/default/22.rom_ctrl_stress_all.502423427 May 26 01:59:56 PM PDT 24 May 26 02:01:03 PM PDT 24 29008742619 ps
T370 /workspace/coverage/default/5.rom_ctrl_alert_test.551414750 May 26 01:59:25 PM PDT 24 May 26 01:59:31 PM PDT 24 333646409 ps
T371 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2934569201 May 26 02:00:05 PM PDT 24 May 26 02:19:24 PM PDT 24 59522558094 ps
T372 /workspace/coverage/default/3.rom_ctrl_smoke.3752520634 May 26 01:59:24 PM PDT 24 May 26 01:59:34 PM PDT 24 192232929 ps
T373 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.339401146 May 26 01:59:23 PM PDT 24 May 26 02:01:55 PM PDT 24 15107768126 ps
T33 /workspace/coverage/default/4.rom_ctrl_sec_cm.1760782894 May 26 01:59:24 PM PDT 24 May 26 02:01:06 PM PDT 24 505945986 ps
T374 /workspace/coverage/default/27.rom_ctrl_smoke.2436097879 May 26 02:00:04 PM PDT 24 May 26 02:00:28 PM PDT 24 190497215 ps
T375 /workspace/coverage/default/30.rom_ctrl_stress_all.2891132156 May 26 02:00:17 PM PDT 24 May 26 02:00:56 PM PDT 24 1068108349 ps
T376 /workspace/coverage/default/37.rom_ctrl_smoke.2727921112 May 26 02:00:23 PM PDT 24 May 26 02:01:09 PM PDT 24 14049679431 ps
T57 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1262156394 May 26 01:02:25 PM PDT 24 May 26 01:03:15 PM PDT 24 10559538327 ps
T58 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2540767542 May 26 01:02:26 PM PDT 24 May 26 01:02:31 PM PDT 24 333091692 ps
T377 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1676099911 May 26 01:02:06 PM PDT 24 May 26 01:02:22 PM PDT 24 4623234459 ps
T59 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1014203289 May 26 01:02:26 PM PDT 24 May 26 01:02:43 PM PDT 24 38730899595 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1200146896 May 26 01:02:05 PM PDT 24 May 26 01:02:24 PM PDT 24 7552261221 ps
T379 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4236605646 May 26 01:02:16 PM PDT 24 May 26 01:02:24 PM PDT 24 133345984 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1925901379 May 26 01:02:08 PM PDT 24 May 26 01:02:26 PM PDT 24 7837302818 ps
T65 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.76960227 May 26 01:02:16 PM PDT 24 May 26 01:03:39 PM PDT 24 8918916939 ps
T66 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1362624808 May 26 01:02:02 PM PDT 24 May 26 01:02:19 PM PDT 24 11107036724 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.375345519 May 26 01:02:17 PM PDT 24 May 26 01:02:24 PM PDT 24 540617458 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2238859272 May 26 01:02:04 PM PDT 24 May 26 01:02:13 PM PDT 24 259181344 ps
T67 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2677558691 May 26 01:02:06 PM PDT 24 May 26 01:02:13 PM PDT 24 168265813 ps
T97 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.285188294 May 26 01:02:26 PM PDT 24 May 26 01:02:33 PM PDT 24 1148570792 ps
T91 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2648984295 May 26 01:02:16 PM PDT 24 May 26 01:02:36 PM PDT 24 1493524076 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1528928482 May 26 01:01:58 PM PDT 24 May 26 01:02:21 PM PDT 24 2143601427 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1041987132 May 26 01:02:15 PM PDT 24 May 26 01:02:20 PM PDT 24 368048251 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1194970055 May 26 01:02:09 PM PDT 24 May 26 01:02:26 PM PDT 24 6484670247 ps
T385 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1200400912 May 26 01:02:25 PM PDT 24 May 26 01:02:41 PM PDT 24 6217077914 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2213494432 May 26 01:02:26 PM PDT 24 May 26 01:02:44 PM PDT 24 3587151417 ps
T99 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4021259749 May 26 01:02:25 PM PDT 24 May 26 01:03:20 PM PDT 24 54362683417 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.681097837 May 26 01:02:01 PM PDT 24 May 26 01:02:11 PM PDT 24 92860460 ps
T388 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.602357051 May 26 01:02:24 PM PDT 24 May 26 01:02:44 PM PDT 24 2001656485 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3334463736 May 26 01:02:07 PM PDT 24 May 26 01:02:14 PM PDT 24 592958227 ps
T54 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.819748954 May 26 01:02:27 PM PDT 24 May 26 01:03:11 PM PDT 24 2776677966 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2621404130 May 26 01:02:14 PM PDT 24 May 26 01:02:29 PM PDT 24 3423217778 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1540585454 May 26 01:02:05 PM PDT 24 May 26 01:02:16 PM PDT 24 618496084 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1988077857 May 26 01:01:58 PM PDT 24 May 26 01:02:06 PM PDT 24 293487103 ps
T55 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1646391880 May 26 01:02:03 PM PDT 24 May 26 01:03:20 PM PDT 24 3171935450 ps
T68 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3458443347 May 26 01:02:19 PM PDT 24 May 26 01:03:15 PM PDT 24 104551256395 ps
T69 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3092765157 May 26 01:02:17 PM PDT 24 May 26 01:02:22 PM PDT 24 347043634 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2978029432 May 26 01:02:22 PM PDT 24 May 26 01:02:37 PM PDT 24 1868151592 ps
T392 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2764741869 May 26 01:02:19 PM PDT 24 May 26 01:02:38 PM PDT 24 2195122238 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4294012940 May 26 01:02:07 PM PDT 24 May 26 01:02:23 PM PDT 24 1597610425 ps
T394 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3359913327 May 26 01:02:24 PM PDT 24 May 26 01:03:20 PM PDT 24 9070304770 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1403244054 May 26 01:02:10 PM PDT 24 May 26 01:02:20 PM PDT 24 89835839 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.822684643 May 26 01:02:09 PM PDT 24 May 26 01:02:19 PM PDT 24 881442336 ps
T56 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1205986692 May 26 01:02:27 PM PDT 24 May 26 01:03:42 PM PDT 24 10524066098 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4154177131 May 26 01:02:08 PM PDT 24 May 26 01:02:19 PM PDT 24 209872044 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.792364739 May 26 01:02:05 PM PDT 24 May 26 01:02:23 PM PDT 24 6901063893 ps
T94 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3385042677 May 26 01:02:08 PM PDT 24 May 26 01:02:17 PM PDT 24 3011651380 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.504503393 May 26 01:02:06 PM PDT 24 May 26 01:02:14 PM PDT 24 128087176 ps
T109 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3588324884 May 26 01:02:11 PM PDT 24 May 26 01:03:21 PM PDT 24 753458867 ps
T70 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3493502990 May 26 01:02:15 PM PDT 24 May 26 01:02:24 PM PDT 24 1647022652 ps
T95 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3022812718 May 26 01:02:26 PM PDT 24 May 26 01:02:42 PM PDT 24 5815124170 ps
T71 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1193466634 May 26 01:02:09 PM PDT 24 May 26 01:02:52 PM PDT 24 26810435624 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.34459450 May 26 01:02:14 PM PDT 24 May 26 01:02:31 PM PDT 24 2122272308 ps
T72 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.210133464 May 26 01:01:59 PM PDT 24 May 26 01:02:12 PM PDT 24 4134082642 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1206207114 May 26 01:02:01 PM PDT 24 May 26 01:02:14 PM PDT 24 12397023691 ps
T401 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3794067324 May 26 01:02:28 PM PDT 24 May 26 01:02:34 PM PDT 24 144797023 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3120371585 May 26 01:02:09 PM PDT 24 May 26 01:02:21 PM PDT 24 7315573382 ps
T403 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.28711054 May 26 01:02:28 PM PDT 24 May 26 01:02:36 PM PDT 24 168660766 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.645853158 May 26 01:02:17 PM PDT 24 May 26 01:02:35 PM PDT 24 5881924417 ps
T405 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2710886676 May 26 01:02:26 PM PDT 24 May 26 01:02:44 PM PDT 24 17440504948 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3330817751 May 26 01:02:24 PM PDT 24 May 26 01:02:32 PM PDT 24 346901471 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4155308964 May 26 01:01:56 PM PDT 24 May 26 01:02:04 PM PDT 24 348809838 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2759293084 May 26 01:02:06 PM PDT 24 May 26 01:02:23 PM PDT 24 3064010860 ps
T110 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1385928111 May 26 01:02:08 PM PDT 24 May 26 01:03:19 PM PDT 24 230282797 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.254539247 May 26 01:02:08 PM PDT 24 May 26 01:02:15 PM PDT 24 214813347 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1727078793 May 26 01:02:27 PM PDT 24 May 26 01:02:35 PM PDT 24 416160665 ps
T410 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2801989592 May 26 01:02:18 PM PDT 24 May 26 01:02:32 PM PDT 24 7640663696 ps
T116 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2520334989 May 26 01:02:16 PM PDT 24 May 26 01:03:02 PM PDT 24 6368974895 ps
T80 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3210213889 May 26 01:02:17 PM PDT 24 May 26 01:02:22 PM PDT 24 333157716 ps
T411 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3677412531 May 26 01:02:04 PM PDT 24 May 26 01:02:21 PM PDT 24 1543702887 ps
T81 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1723966981 May 26 01:02:09 PM PDT 24 May 26 01:03:18 PM PDT 24 16386049106 ps
T85 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3431754011 May 26 01:02:07 PM PDT 24 May 26 01:02:14 PM PDT 24 178442793 ps
T412 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1492627732 May 26 01:02:06 PM PDT 24 May 26 01:02:19 PM PDT 24 2235530218 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.116707265 May 26 01:02:17 PM PDT 24 May 26 01:03:02 PM PDT 24 1451709866 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3978589679 May 26 01:02:03 PM PDT 24 May 26 01:02:17 PM PDT 24 2152868948 ps
T115 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3313272100 May 26 01:02:17 PM PDT 24 May 26 01:03:31 PM PDT 24 597359145 ps
T414 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2486597129 May 26 01:02:15 PM PDT 24 May 26 01:02:23 PM PDT 24 98842230 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4027201558 May 26 01:02:14 PM PDT 24 May 26 01:02:24 PM PDT 24 833300332 ps
T416 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2717341722 May 26 01:02:28 PM PDT 24 May 26 01:02:42 PM PDT 24 5194153257 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2172064531 May 26 01:02:04 PM PDT 24 May 26 01:02:20 PM PDT 24 5410599405 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2574483218 May 26 01:02:07 PM PDT 24 May 26 01:02:16 PM PDT 24 305814543 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1332818414 May 26 01:02:05 PM PDT 24 May 26 01:02:16 PM PDT 24 757146081 ps
T420 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2416182475 May 26 01:02:24 PM PDT 24 May 26 01:02:36 PM PDT 24 4455556044 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1056483137 May 26 01:02:14 PM PDT 24 May 26 01:02:33 PM PDT 24 5011220865 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4263662889 May 26 01:02:13 PM PDT 24 May 26 01:02:46 PM PDT 24 2082446240 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.572818067 May 26 01:02:06 PM PDT 24 May 26 01:02:23 PM PDT 24 1735966796 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2895273561 May 26 01:02:05 PM PDT 24 May 26 01:02:22 PM PDT 24 2031627615 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.778706890 May 26 01:01:59 PM PDT 24 May 26 01:02:09 PM PDT 24 516686216 ps
T114 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2452215877 May 26 01:02:14 PM PDT 24 May 26 01:03:28 PM PDT 24 1021374787 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1139977007 May 26 01:02:04 PM PDT 24 May 26 01:02:25 PM PDT 24 4501327125 ps
T425 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1900258205 May 26 01:02:15 PM PDT 24 May 26 01:02:31 PM PDT 24 3812612315 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.728440055 May 26 01:02:25 PM PDT 24 May 26 01:02:41 PM PDT 24 22440001410 ps
T427 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4249960092 May 26 01:02:19 PM PDT 24 May 26 01:02:36 PM PDT 24 4100844254 ps
T428 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1402684798 May 26 01:02:06 PM PDT 24 May 26 01:02:21 PM PDT 24 1818939529 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1308546185 May 26 01:02:05 PM PDT 24 May 26 01:02:14 PM PDT 24 241914853 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3445491491 May 26 01:02:08 PM PDT 24 May 26 01:02:17 PM PDT 24 1488494677 ps
T431 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.15821222 May 26 01:02:24 PM PDT 24 May 26 01:02:36 PM PDT 24 1102161200 ps
T107 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.854399374 May 26 01:02:26 PM PDT 24 May 26 01:03:27 PM PDT 24 7184347133 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.523070254 May 26 01:02:07 PM PDT 24 May 26 01:02:38 PM PDT 24 543396363 ps
T433 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1588292980 May 26 01:02:24 PM PDT 24 May 26 01:02:36 PM PDT 24 4584654414 ps
T434 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1502579680 May 26 01:02:16 PM PDT 24 May 26 01:02:33 PM PDT 24 4049656036 ps
T118 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2005946382 May 26 01:02:08 PM PDT 24 May 26 01:02:47 PM PDT 24 153750369 ps
T83 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.688121582 May 26 01:02:19 PM PDT 24 May 26 01:03:37 PM PDT 24 19494577633 ps
T435 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1990022627 May 26 01:02:08 PM PDT 24 May 26 01:02:25 PM PDT 24 10947959441 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3774990160 May 26 01:02:05 PM PDT 24 May 26 01:02:24 PM PDT 24 3566536147 ps
T437 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2803549849 May 26 01:02:25 PM PDT 24 May 26 01:02:39 PM PDT 24 2630202039 ps
T117 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3237332836 May 26 01:02:09 PM PDT 24 May 26 01:03:25 PM PDT 24 2523891179 ps
T438 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.815468654 May 26 01:02:26 PM PDT 24 May 26 01:02:38 PM PDT 24 21867958738 ps
T439 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1696550509 May 26 01:02:23 PM PDT 24 May 26 01:03:20 PM PDT 24 24410575517 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3963898218 May 26 01:02:04 PM PDT 24 May 26 01:02:55 PM PDT 24 35154332513 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.184605351 May 26 01:01:59 PM PDT 24 May 26 01:02:11 PM PDT 24 2302894079 ps
T441 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4214413037 May 26 01:02:14 PM PDT 24 May 26 01:02:32 PM PDT 24 4348674742 ps
T119 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4180547978 May 26 01:02:26 PM PDT 24 May 26 01:03:41 PM PDT 24 20921582836 ps
T442 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1137697984 May 26 01:02:24 PM PDT 24 May 26 01:02:31 PM PDT 24 176720310 ps
T89 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4081237481 May 26 01:02:05 PM PDT 24 May 26 01:03:12 PM PDT 24 12434540390 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4135176197 May 26 01:02:09 PM PDT 24 May 26 01:02:25 PM PDT 24 6181597304 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.72476180 May 26 01:02:25 PM PDT 24 May 26 01:02:39 PM PDT 24 1418944561 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2861887704 May 26 01:02:00 PM PDT 24 May 26 01:03:05 PM PDT 24 5917681961 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3647143848 May 26 01:02:06 PM PDT 24 May 26 01:03:29 PM PDT 24 89159190227 ps
T120 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2525687219 May 26 01:02:07 PM PDT 24 May 26 01:02:49 PM PDT 24 3043804434 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3239219650 May 26 01:02:10 PM PDT 24 May 26 01:02:29 PM PDT 24 5535781399 ps
T448 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3184431025 May 26 01:02:27 PM PDT 24 May 26 01:02:38 PM PDT 24 798654427 ps
T449 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.401124482 May 26 01:02:09 PM PDT 24 May 26 01:02:30 PM PDT 24 2013086466 ps
T450 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2882633894 May 26 01:02:25 PM PDT 24 May 26 01:02:46 PM PDT 24 4955519851 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.849352244 May 26 01:02:09 PM PDT 24 May 26 01:02:22 PM PDT 24 1751872141 ps
T451 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4084924011 May 26 01:02:14 PM PDT 24 May 26 01:02:27 PM PDT 24 2364824847 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2755513973 May 26 01:02:05 PM PDT 24 May 26 01:02:22 PM PDT 24 2728109299 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1776657020 May 26 01:02:08 PM PDT 24 May 26 01:02:18 PM PDT 24 85545366 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3608676599 May 26 01:02:04 PM PDT 24 May 26 01:02:11 PM PDT 24 827077208 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.299289289 May 26 01:02:05 PM PDT 24 May 26 01:02:19 PM PDT 24 1363148007 ps
T455 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.313029950 May 26 01:02:27 PM PDT 24 May 26 01:03:14 PM PDT 24 4971122512 ps
T456 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3593069412 May 26 01:02:14 PM PDT 24 May 26 01:02:27 PM PDT 24 2511251797 ps
T457 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2177114789 May 26 01:02:26 PM PDT 24 May 26 01:02:34 PM PDT 24 1875537459 ps
T458 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3755917552 May 26 01:02:09 PM PDT 24 May 26 01:02:28 PM PDT 24 3667407463 ps
T459 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3068327237 May 26 01:02:04 PM PDT 24 May 26 01:02:21 PM PDT 24 1034753760 ps
T460 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3359731689 May 26 01:02:24 PM PDT 24 May 26 01:02:37 PM PDT 24 2768782888 ps
T121 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2703541569 May 26 01:02:07 PM PDT 24 May 26 01:03:20 PM PDT 24 524993728 ps
T461 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2646377473 May 26 01:02:25 PM PDT 24 May 26 01:02:40 PM PDT 24 1450661422 ps
T462 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.152101117 May 26 01:02:16 PM PDT 24 May 26 01:02:33 PM PDT 24 1110180114 ps
T463 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.91680879 May 26 01:02:26 PM PDT 24 May 26 01:03:46 PM PDT 24 9761527033 ps
T464 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.768910148 May 26 01:02:06 PM PDT 24 May 26 01:02:58 PM PDT 24 2449018975 ps
T111 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.534427254 May 26 01:02:24 PM PDT 24 May 26 01:03:35 PM PDT 24 4121763327 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1148476629 May 26 01:02:07 PM PDT 24 May 26 01:03:09 PM PDT 24 30912140664 ps
T465 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.572546153 May 26 01:02:14 PM PDT 24 May 26 01:02:28 PM PDT 24 4417606449 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1380256989 May 26 01:02:01 PM PDT 24 May 26 01:03:20 PM PDT 24 1598338737 ps
T466 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3378792385 May 26 01:02:25 PM PDT 24 May 26 01:02:31 PM PDT 24 344369675 ps
T108 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3860776858 May 26 01:02:24 PM PDT 24 May 26 01:04:05 PM PDT 24 48041191433 ps
T467 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.788841616 May 26 01:02:24 PM PDT 24 May 26 01:03:07 PM PDT 24 1030674721 ps
T468 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.458195146 May 26 01:02:08 PM PDT 24 May 26 01:03:04 PM PDT 24 6031492003 ps
T469 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1795461159 May 26 01:02:06 PM PDT 24 May 26 01:02:18 PM PDT 24 6906401812 ps
T470 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4048655773 May 26 01:02:07 PM PDT 24 May 26 01:02:27 PM PDT 24 7134317413 ps
T471 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2391991766 May 26 01:02:17 PM PDT 24 May 26 01:02:32 PM PDT 24 5691100448 ps

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2324318488
Short name T9
Test name
Test status
Simulation time 26804893759 ps
CPU time 2553.9 seconds
Started May 26 02:00:34 PM PDT 24
Finished May 26 02:43:28 PM PDT 24
Peak memory 227872 kb
Host smart-e0c555ab-7486-4827-a41d-f3613768f673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324318488 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2324318488
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1072773243
Short name T1
Test name
Test status
Simulation time 355355507640 ps
CPU time 415.58 seconds
Started May 26 01:59:48 PM PDT 24
Finished May 26 02:06:45 PM PDT 24
Peak memory 224436 kb
Host smart-6668f917-162d-4a0b-841f-09ed11a76c86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072773243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1072773243
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.80860238
Short name T285
Test name
Test status
Simulation time 137680922407 ps
CPU time 373.36 seconds
Started May 26 02:00:42 PM PDT 24
Finished May 26 02:07:12 PM PDT 24
Peak memory 233440 kb
Host smart-377ead1b-c72a-474a-b5f4-9ee5b2cf1a26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80860238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_co
rrupt_sig_fatal_chk.80860238
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.698628982
Short name T16
Test name
Test status
Simulation time 143658968037 ps
CPU time 10361.8 seconds
Started May 26 01:59:49 PM PDT 24
Finished May 26 04:52:33 PM PDT 24
Peak memory 235732 kb
Host smart-8544e3fa-795a-49d0-b2f8-abac3b1b63be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698628982 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.698628982
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1205986692
Short name T56
Test name
Test status
Simulation time 10524066098 ps
CPU time 74.34 seconds
Started May 26 01:02:27 PM PDT 24
Finished May 26 01:03:42 PM PDT 24
Peak memory 219716 kb
Host smart-41e787be-8e18-40ed-adda-e61877c0e84d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205986692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1205986692
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1660792240
Short name T11
Test name
Test status
Simulation time 10094565938 ps
CPU time 43.75 seconds
Started May 26 01:59:35 PM PDT 24
Finished May 26 02:00:19 PM PDT 24
Peak memory 217528 kb
Host smart-a297f4c0-fa9c-4389-b4fa-74dfb2f32a90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660792240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1660792240
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1826744815
Short name T29
Test name
Test status
Simulation time 9381915143 ps
CPU time 110.89 seconds
Started May 26 01:59:16 PM PDT 24
Finished May 26 02:01:08 PM PDT 24
Peak memory 230624 kb
Host smart-61bdb253-57f9-40ca-86c2-79d2ccda8f5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826744815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1826744815
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2540767542
Short name T58
Test name
Test status
Simulation time 333091692 ps
CPU time 4.18 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:02:31 PM PDT 24
Peak memory 211164 kb
Host smart-8e39f480-560f-4ce7-a031-a04cbd7349fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540767542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2540767542
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4180547978
Short name T119
Test name
Test status
Simulation time 20921582836 ps
CPU time 74.56 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:03:41 PM PDT 24
Peak memory 219396 kb
Host smart-2e5b0d92-0090-41b2-aa5c-4dc6284202eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180547978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4180547978
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2991145820
Short name T15
Test name
Test status
Simulation time 64958363383 ps
CPU time 1331.14 seconds
Started May 26 02:00:34 PM PDT 24
Finished May 26 02:23:06 PM PDT 24
Peak memory 233968 kb
Host smart-144405c3-5a58-4aac-b840-e9fbf777caca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991145820 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2991145820
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.357930682
Short name T60
Test name
Test status
Simulation time 15212979781 ps
CPU time 11.19 seconds
Started May 26 01:59:47 PM PDT 24
Finished May 26 01:59:59 PM PDT 24
Peak memory 211084 kb
Host smart-e3888719-0a63-44a6-b5eb-b12d875a94dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357930682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.357930682
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1873785839
Short name T124
Test name
Test status
Simulation time 4571082529 ps
CPU time 14.86 seconds
Started May 26 01:59:43 PM PDT 24
Finished May 26 01:59:59 PM PDT 24
Peak memory 212676 kb
Host smart-99b6e8c3-0a07-4ccc-8038-2e99b84d2e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873785839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1873785839
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.748638101
Short name T294
Test name
Test status
Simulation time 692857389 ps
CPU time 9.72 seconds
Started May 26 01:59:16 PM PDT 24
Finished May 26 01:59:27 PM PDT 24
Peak memory 211736 kb
Host smart-cd416d49-9718-49b9-bd6b-a72b16eb7c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748638101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.748638101
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1646391880
Short name T55
Test name
Test status
Simulation time 3171935450 ps
CPU time 74.18 seconds
Started May 26 01:02:03 PM PDT 24
Finished May 26 01:03:20 PM PDT 24
Peak memory 212184 kb
Host smart-bdcca8f5-bc68-4016-9a51-60a0b9d9ee8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646391880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1646391880
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4081237481
Short name T89
Test name
Test status
Simulation time 12434540390 ps
CPU time 63.38 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:03:12 PM PDT 24
Peak memory 211264 kb
Host smart-114d3824-077a-437e-a5a4-976f2daa7bbd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081237481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4081237481
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1380256989
Short name T112
Test name
Test status
Simulation time 1598338737 ps
CPU time 75.9 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:03:20 PM PDT 24
Peak memory 211952 kb
Host smart-98cd7722-d550-468b-bcf3-5f4277142e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380256989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1380256989
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3210213889
Short name T80
Test name
Test status
Simulation time 333157716 ps
CPU time 4.27 seconds
Started May 26 01:02:17 PM PDT 24
Finished May 26 01:02:22 PM PDT 24
Peak memory 211280 kb
Host smart-e709e999-9444-4df6-9918-05595dc53793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210213889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3210213889
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3421650460
Short name T17
Test name
Test status
Simulation time 519292950372 ps
CPU time 5693.52 seconds
Started May 26 01:59:44 PM PDT 24
Finished May 26 03:34:39 PM PDT 24
Peak memory 230712 kb
Host smart-5aafcc97-f487-48be-ab73-0d67d6d6ee58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421650460 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3421650460
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.299289289
Short name T454
Test name
Test status
Simulation time 1363148007 ps
CPU time 11.82 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:19 PM PDT 24
Peak memory 211160 kb
Host smart-3920fbe2-8a50-4ef9-8fd9-a98c2fa728cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299289289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.299289289
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2238859272
Short name T382
Test name
Test status
Simulation time 259181344 ps
CPU time 6.17 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:13 PM PDT 24
Peak memory 211140 kb
Host smart-32636158-6f82-47f7-9521-3fdb0ae83979
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238859272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2238859272
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.681097837
Short name T387
Test name
Test status
Simulation time 92860460 ps
CPU time 7.46 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:11 PM PDT 24
Peak memory 211176 kb
Host smart-b97ed00c-e172-4ec3-8027-a116bb0f8ac5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681097837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.681097837
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1200146896
Short name T378
Test name
Test status
Simulation time 7552261221 ps
CPU time 16.09 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:24 PM PDT 24
Peak memory 213000 kb
Host smart-21dd942d-132c-41f4-b21b-fbb5a88b2116
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200146896 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1200146896
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3978589679
Short name T413
Test name
Test status
Simulation time 2152868948 ps
CPU time 10.4 seconds
Started May 26 01:02:03 PM PDT 24
Finished May 26 01:02:17 PM PDT 24
Peak memory 211228 kb
Host smart-14f2d352-7325-49f4-b1f3-c844eeb57671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978589679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3978589679
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1540585454
Short name T390
Test name
Test status
Simulation time 618496084 ps
CPU time 8.01 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:16 PM PDT 24
Peak memory 210996 kb
Host smart-9972f28c-9be4-4899-8581-c10f7d285e4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540585454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1540585454
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2172064531
Short name T417
Test name
Test status
Simulation time 5410599405 ps
CPU time 13.15 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:20 PM PDT 24
Peak memory 211120 kb
Host smart-3b3d1b67-7b4f-4fc6-975e-e07fc844a939
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172064531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2172064531
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3963898218
Short name T88
Test name
Test status
Simulation time 35154332513 ps
CPU time 49.03 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:55 PM PDT 24
Peak memory 211356 kb
Host smart-89bfc43e-f70b-49c8-af95-447c9674fddf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963898218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3963898218
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.184605351
Short name T440
Test name
Test status
Simulation time 2302894079 ps
CPU time 8.11 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:11 PM PDT 24
Peak memory 211196 kb
Host smart-96381e6a-2dbb-4788-9491-98edc4cf6f93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184605351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.184605351
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1139977007
Short name T424
Test name
Test status
Simulation time 4501327125 ps
CPU time 18.47 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:25 PM PDT 24
Peak memory 219468 kb
Host smart-62256075-45c2-4dc0-8bc6-2ac5ce43a646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139977007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1139977007
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.210133464
Short name T72
Test name
Test status
Simulation time 4134082642 ps
CPU time 10.72 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:12 PM PDT 24
Peak memory 211260 kb
Host smart-9083bee3-60bb-4b0b-a6ba-3941a5f7370b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210133464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.210133464
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4155308964
Short name T407
Test name
Test status
Simulation time 348809838 ps
CPU time 6.53 seconds
Started May 26 01:01:56 PM PDT 24
Finished May 26 01:02:04 PM PDT 24
Peak memory 211256 kb
Host smart-20af446f-2414-415d-b8ed-57a66da5cbc2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155308964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4155308964
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1362624808
Short name T66
Test name
Test status
Simulation time 11107036724 ps
CPU time 14.78 seconds
Started May 26 01:02:02 PM PDT 24
Finished May 26 01:02:19 PM PDT 24
Peak memory 211220 kb
Host smart-73c5f305-7c61-4450-9579-ef6c18bb6005
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362624808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1362624808
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3774990160
Short name T436
Test name
Test status
Simulation time 3566536147 ps
CPU time 15.94 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:24 PM PDT 24
Peak memory 219440 kb
Host smart-9c97005f-4fec-407f-a9a0-abde88b6f2df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774990160 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3774990160
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.778706890
Short name T86
Test name
Test status
Simulation time 516686216 ps
CPU time 7.07 seconds
Started May 26 01:01:59 PM PDT 24
Finished May 26 01:02:09 PM PDT 24
Peak memory 211148 kb
Host smart-0d86c1e4-0beb-486e-b10e-e51ef55ecbdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778706890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.778706890
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1206207114
Short name T400
Test name
Test status
Simulation time 12397023691 ps
CPU time 9.62 seconds
Started May 26 01:02:01 PM PDT 24
Finished May 26 01:02:14 PM PDT 24
Peak memory 211052 kb
Host smart-78fa37b7-222e-4447-94dd-af011ea05e46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206207114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1206207114
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1988077857
Short name T391
Test name
Test status
Simulation time 293487103 ps
CPU time 6.16 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:06 PM PDT 24
Peak memory 211200 kb
Host smart-47f8f25b-7207-4c14-9048-e2c24b1e729c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988077857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1988077857
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2861887704
Short name T445
Test name
Test status
Simulation time 5917681961 ps
CPU time 61.96 seconds
Started May 26 01:02:00 PM PDT 24
Finished May 26 01:03:05 PM PDT 24
Peak memory 211248 kb
Host smart-f07d2440-afa7-4eb3-a65b-e4a8dd1f99e4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861887704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2861887704
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3608676599
Short name T453
Test name
Test status
Simulation time 827077208 ps
CPU time 4.37 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:11 PM PDT 24
Peak memory 211128 kb
Host smart-8288cec3-9c18-4b1d-9d77-0046ccafb623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608676599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3608676599
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1528928482
Short name T383
Test name
Test status
Simulation time 2143601427 ps
CPU time 20.08 seconds
Started May 26 01:01:58 PM PDT 24
Finished May 26 01:02:21 PM PDT 24
Peak memory 219416 kb
Host smart-1558fd10-31f0-4852-9105-85e89f90e586
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528928482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1528928482
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.572546153
Short name T465
Test name
Test status
Simulation time 4417606449 ps
CPU time 12.45 seconds
Started May 26 01:02:14 PM PDT 24
Finished May 26 01:02:28 PM PDT 24
Peak memory 219584 kb
Host smart-ec38d23a-f8fa-45bc-a2fc-449ea9ce6e5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572546153 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.572546153
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2648984295
Short name T91
Test name
Test status
Simulation time 1493524076 ps
CPU time 19.2 seconds
Started May 26 01:02:16 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 211208 kb
Host smart-0421f209-e3cc-461f-b89c-51b69a881f13
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648984295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2648984295
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3593069412
Short name T456
Test name
Test status
Simulation time 2511251797 ps
CPU time 12.56 seconds
Started May 26 01:02:14 PM PDT 24
Finished May 26 01:02:27 PM PDT 24
Peak memory 211188 kb
Host smart-fa2183ea-c3b0-4f50-98d4-6fe84b228231
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593069412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3593069412
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4236605646
Short name T379
Test name
Test status
Simulation time 133345984 ps
CPU time 7.2 seconds
Started May 26 01:02:16 PM PDT 24
Finished May 26 01:02:24 PM PDT 24
Peak memory 215452 kb
Host smart-d1b21a5a-0fb5-4d00-9440-cef4c0b43164
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236605646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4236605646
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3313272100
Short name T115
Test name
Test status
Simulation time 597359145 ps
CPU time 73.04 seconds
Started May 26 01:02:17 PM PDT 24
Finished May 26 01:03:31 PM PDT 24
Peak memory 212152 kb
Host smart-d0caeb74-7ef2-4898-8cf3-8393ac3d75cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313272100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3313272100
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4214413037
Short name T441
Test name
Test status
Simulation time 4348674742 ps
CPU time 17.3 seconds
Started May 26 01:02:14 PM PDT 24
Finished May 26 01:02:32 PM PDT 24
Peak memory 219468 kb
Host smart-40485dbf-7d33-4cd2-a7dc-2e08f36d9fb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214413037 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4214413037
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2391991766
Short name T471
Test name
Test status
Simulation time 5691100448 ps
CPU time 14.17 seconds
Started May 26 01:02:17 PM PDT 24
Finished May 26 01:02:32 PM PDT 24
Peak memory 211344 kb
Host smart-11d166e0-a95b-40b2-87a7-e8a651f9b8a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391991766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2391991766
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.688121582
Short name T83
Test name
Test status
Simulation time 19494577633 ps
CPU time 77.24 seconds
Started May 26 01:02:19 PM PDT 24
Finished May 26 01:03:37 PM PDT 24
Peak memory 211184 kb
Host smart-76a32dc4-5bcb-417a-9b3b-4a36ef68d7dd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688121582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.688121582
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3092765157
Short name T69
Test name
Test status
Simulation time 347043634 ps
CPU time 4.33 seconds
Started May 26 01:02:17 PM PDT 24
Finished May 26 01:02:22 PM PDT 24
Peak memory 211132 kb
Host smart-eb3a1a92-c9f4-4b50-81bd-d332516acf01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092765157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3092765157
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2764741869
Short name T392
Test name
Test status
Simulation time 2195122238 ps
CPU time 18.2 seconds
Started May 26 01:02:19 PM PDT 24
Finished May 26 01:02:38 PM PDT 24
Peak memory 219584 kb
Host smart-cc465756-a2cb-400b-8ac2-82a9d795d214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764741869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2764741869
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2452215877
Short name T114
Test name
Test status
Simulation time 1021374787 ps
CPU time 73.41 seconds
Started May 26 01:02:14 PM PDT 24
Finished May 26 01:03:28 PM PDT 24
Peak memory 211888 kb
Host smart-6798354a-e7de-4d8c-a180-3933315baec1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452215877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2452215877
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2801989592
Short name T410
Test name
Test status
Simulation time 7640663696 ps
CPU time 14.04 seconds
Started May 26 01:02:18 PM PDT 24
Finished May 26 01:02:32 PM PDT 24
Peak memory 219544 kb
Host smart-ae081430-d00f-44fa-8176-97ac121dbe1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801989592 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2801989592
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3493502990
Short name T70
Test name
Test status
Simulation time 1647022652 ps
CPU time 7.18 seconds
Started May 26 01:02:15 PM PDT 24
Finished May 26 01:02:24 PM PDT 24
Peak memory 211220 kb
Host smart-703a8439-457e-45a3-a299-ce1395c82111
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493502990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3493502990
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3458443347
Short name T68
Test name
Test status
Simulation time 104551256395 ps
CPU time 55.45 seconds
Started May 26 01:02:19 PM PDT 24
Finished May 26 01:03:15 PM PDT 24
Peak memory 211152 kb
Host smart-1ea9aa1f-184c-4d1e-8aae-1a419e279a06
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458443347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3458443347
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2486597129
Short name T414
Test name
Test status
Simulation time 98842230 ps
CPU time 6.21 seconds
Started May 26 01:02:15 PM PDT 24
Finished May 26 01:02:23 PM PDT 24
Peak memory 211428 kb
Host smart-b54cc48b-ea04-4e63-91d9-2739a1ecb31d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486597129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2486597129
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.152101117
Short name T462
Test name
Test status
Simulation time 1110180114 ps
CPU time 15.3 seconds
Started May 26 01:02:16 PM PDT 24
Finished May 26 01:02:33 PM PDT 24
Peak memory 219332 kb
Host smart-13cca203-2c93-4667-ae9a-896d561f1cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152101117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.152101117
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2520334989
Short name T116
Test name
Test status
Simulation time 6368974895 ps
CPU time 44.79 seconds
Started May 26 01:02:16 PM PDT 24
Finished May 26 01:03:02 PM PDT 24
Peak memory 219480 kb
Host smart-cd8b3d4d-c330-4169-92dd-79413c027b46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520334989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2520334989
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2710886676
Short name T405
Test name
Test status
Simulation time 17440504948 ps
CPU time 16.8 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:02:44 PM PDT 24
Peak memory 219468 kb
Host smart-6f4dafab-1da3-4fe9-895e-ff313aca4a19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710886676 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2710886676
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.815468654
Short name T438
Test name
Test status
Simulation time 21867958738 ps
CPU time 10.83 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:02:38 PM PDT 24
Peak memory 211164 kb
Host smart-5dfe3732-bf9a-4e71-8ac5-e1fcf690f95c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815468654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.815468654
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.76960227
Short name T65
Test name
Test status
Simulation time 8918916939 ps
CPU time 81.73 seconds
Started May 26 01:02:16 PM PDT 24
Finished May 26 01:03:39 PM PDT 24
Peak memory 211228 kb
Host smart-6ded7c01-1c77-42a4-b626-ec7e573f4248
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76960227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pas
sthru_mem_tl_intg_err.76960227
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1588292980
Short name T433
Test name
Test status
Simulation time 4584654414 ps
CPU time 11.04 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 211252 kb
Host smart-d3472167-8eb2-4f7c-8539-f7975d053ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588292980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1588292980
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.602357051
Short name T388
Test name
Test status
Simulation time 2001656485 ps
CPU time 19.39 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:02:44 PM PDT 24
Peak memory 219500 kb
Host smart-6879ae3a-4d55-4487-b42b-76c695a976c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602357051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.602357051
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3184431025
Short name T448
Test name
Test status
Simulation time 798654427 ps
CPU time 10.14 seconds
Started May 26 01:02:27 PM PDT 24
Finished May 26 01:02:38 PM PDT 24
Peak memory 219396 kb
Host smart-e466216b-805a-427c-8d41-481fd9617215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184431025 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3184431025
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2177114789
Short name T457
Test name
Test status
Simulation time 1875537459 ps
CPU time 7.33 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:02:34 PM PDT 24
Peak memory 211168 kb
Host smart-93065e3e-98f1-4f0f-bc24-75ab9c2b796f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177114789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2177114789
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3860776858
Short name T108
Test name
Test status
Simulation time 48041191433 ps
CPU time 99.32 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:04:05 PM PDT 24
Peak memory 211220 kb
Host smart-7c585a42-ce39-4637-8453-5e111fe98458
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860776858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3860776858
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.72476180
Short name T444
Test name
Test status
Simulation time 1418944561 ps
CPU time 12.82 seconds
Started May 26 01:02:25 PM PDT 24
Finished May 26 01:02:39 PM PDT 24
Peak memory 211476 kb
Host smart-f4b1f1e4-a030-4183-a255-76eb27822c7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72476180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ct
rl_same_csr_outstanding.72476180
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2646377473
Short name T461
Test name
Test status
Simulation time 1450661422 ps
CPU time 14.41 seconds
Started May 26 01:02:25 PM PDT 24
Finished May 26 01:02:40 PM PDT 24
Peak memory 219512 kb
Host smart-bdd7d992-d8cc-4bd4-aa97-dd440fc8a5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646377473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2646377473
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.728440055
Short name T426
Test name
Test status
Simulation time 22440001410 ps
CPU time 15.17 seconds
Started May 26 01:02:25 PM PDT 24
Finished May 26 01:02:41 PM PDT 24
Peak memory 219480 kb
Host smart-2c24bbde-898d-40f1-8591-1b96993a8bff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728440055 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.728440055
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1696550509
Short name T439
Test name
Test status
Simulation time 24410575517 ps
CPU time 56.45 seconds
Started May 26 01:02:23 PM PDT 24
Finished May 26 01:03:20 PM PDT 24
Peak memory 211388 kb
Host smart-46c040cf-023f-4566-ad46-98639cc8de37
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696550509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1696550509
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2803549849
Short name T437
Test name
Test status
Simulation time 2630202039 ps
CPU time 13.77 seconds
Started May 26 01:02:25 PM PDT 24
Finished May 26 01:02:39 PM PDT 24
Peak memory 211296 kb
Host smart-1acafd4a-83d7-42bd-89f2-a056c0d5bbe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803549849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2803549849
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.28711054
Short name T403
Test name
Test status
Simulation time 168660766 ps
CPU time 7.09 seconds
Started May 26 01:02:28 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 219384 kb
Host smart-667181b1-2591-48be-99fb-c68840422c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28711054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.28711054
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.534427254
Short name T111
Test name
Test status
Simulation time 4121763327 ps
CPU time 70.26 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:03:35 PM PDT 24
Peak memory 211524 kb
Host smart-bde2755d-c1c6-43eb-b13f-bd1d2f4d6b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534427254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.534427254
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3359731689
Short name T460
Test name
Test status
Simulation time 2768782888 ps
CPU time 12.78 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:02:37 PM PDT 24
Peak memory 219472 kb
Host smart-6ce6c1c3-193a-4081-811e-b5b28b058436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359731689 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3359731689
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.15821222
Short name T431
Test name
Test status
Simulation time 1102161200 ps
CPU time 10.6 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 211280 kb
Host smart-50a90ff2-8055-4a8a-ad7f-dcee8f1783c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15821222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.15821222
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3359913327
Short name T394
Test name
Test status
Simulation time 9070304770 ps
CPU time 55.33 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:03:20 PM PDT 24
Peak memory 211244 kb
Host smart-eb6b7f63-a88a-4570-b707-a506e56cf0fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359913327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3359913327
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3022812718
Short name T95
Test name
Test status
Simulation time 5815124170 ps
CPU time 13.9 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:02:42 PM PDT 24
Peak memory 211260 kb
Host smart-26ba52bf-e052-49a5-a708-e23a3b222b16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022812718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3022812718
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2882633894
Short name T450
Test name
Test status
Simulation time 4955519851 ps
CPU time 19.58 seconds
Started May 26 01:02:25 PM PDT 24
Finished May 26 01:02:46 PM PDT 24
Peak memory 219460 kb
Host smart-3606bce9-db49-457c-8a2a-ae05271e6853
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882633894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2882633894
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.788841616
Short name T467
Test name
Test status
Simulation time 1030674721 ps
CPU time 42.21 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:03:07 PM PDT 24
Peak memory 211980 kb
Host smart-cd82eb74-0172-47e7-a6dd-ae6cb0d47704
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788841616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.788841616
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1200400912
Short name T385
Test name
Test status
Simulation time 6217077914 ps
CPU time 14.67 seconds
Started May 26 01:02:25 PM PDT 24
Finished May 26 01:02:41 PM PDT 24
Peak memory 219448 kb
Host smart-7324105c-02c7-4fd7-81ae-b5d102814403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200400912 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1200400912
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1014203289
Short name T59
Test name
Test status
Simulation time 38730899595 ps
CPU time 15.77 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:02:43 PM PDT 24
Peak memory 211340 kb
Host smart-7b59d023-5cfc-4db0-90d7-03cad878b990
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014203289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1014203289
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1262156394
Short name T57
Test name
Test status
Simulation time 10559538327 ps
CPU time 48.94 seconds
Started May 26 01:02:25 PM PDT 24
Finished May 26 01:03:15 PM PDT 24
Peak memory 211308 kb
Host smart-20375840-5ae7-41e4-8831-dad23ef9f29c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262156394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1262156394
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1137697984
Short name T442
Test name
Test status
Simulation time 176720310 ps
CPU time 5.47 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:02:31 PM PDT 24
Peak memory 211132 kb
Host smart-65ebff32-892c-4432-a053-80d2017c6c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137697984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1137697984
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1727078793
Short name T409
Test name
Test status
Simulation time 416160665 ps
CPU time 7.48 seconds
Started May 26 01:02:27 PM PDT 24
Finished May 26 01:02:35 PM PDT 24
Peak memory 219412 kb
Host smart-b9fb734c-2df2-4e3a-ab2e-f7f1362a6e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727078793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1727078793
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.819748954
Short name T54
Test name
Test status
Simulation time 2776677966 ps
CPU time 43.49 seconds
Started May 26 01:02:27 PM PDT 24
Finished May 26 01:03:11 PM PDT 24
Peak memory 211688 kb
Host smart-019d67ea-2094-484e-a2b4-896e98c52d49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819748954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.819748954
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3794067324
Short name T401
Test name
Test status
Simulation time 144797023 ps
CPU time 5.38 seconds
Started May 26 01:02:28 PM PDT 24
Finished May 26 01:02:34 PM PDT 24
Peak memory 219352 kb
Host smart-f77b036f-cb9c-4ff7-ac2e-e36cfceb7416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794067324 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3794067324
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.285188294
Short name T97
Test name
Test status
Simulation time 1148570792 ps
CPU time 6.33 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:02:33 PM PDT 24
Peak memory 211192 kb
Host smart-326744f2-14f5-4941-89fc-8dabf0f2b0f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285188294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.285188294
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4021259749
Short name T99
Test name
Test status
Simulation time 54362683417 ps
CPU time 53.72 seconds
Started May 26 01:02:25 PM PDT 24
Finished May 26 01:03:20 PM PDT 24
Peak memory 211568 kb
Host smart-489ca81a-a62e-492d-892e-9353121c9436
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021259749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4021259749
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2978029432
Short name T93
Test name
Test status
Simulation time 1868151592 ps
CPU time 14.4 seconds
Started May 26 01:02:22 PM PDT 24
Finished May 26 01:02:37 PM PDT 24
Peak memory 211156 kb
Host smart-8802e711-e0b0-4d50-8c2b-093a8d7c04dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978029432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2978029432
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3330817751
Short name T406
Test name
Test status
Simulation time 346901471 ps
CPU time 6.63 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:02:32 PM PDT 24
Peak memory 219496 kb
Host smart-74d1496d-4ddb-4aab-ab09-9b6d904e578c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330817751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3330817751
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.91680879
Short name T463
Test name
Test status
Simulation time 9761527033 ps
CPU time 78.86 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:03:46 PM PDT 24
Peak memory 219512 kb
Host smart-7ff3d219-e04d-4f0a-9894-bee298c67253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91680879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_int
g_err.91680879
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2717341722
Short name T416
Test name
Test status
Simulation time 5194153257 ps
CPU time 12.99 seconds
Started May 26 01:02:28 PM PDT 24
Finished May 26 01:02:42 PM PDT 24
Peak memory 219472 kb
Host smart-d10b4b4a-fb5e-413c-a188-d768db16fb30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717341722 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2717341722
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2416182475
Short name T420
Test name
Test status
Simulation time 4455556044 ps
CPU time 10.89 seconds
Started May 26 01:02:24 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 211260 kb
Host smart-ba3a8248-ca0c-4538-9197-abdda8bd631c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416182475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2416182475
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.854399374
Short name T107
Test name
Test status
Simulation time 7184347133 ps
CPU time 60.25 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:03:27 PM PDT 24
Peak memory 212252 kb
Host smart-e8b09087-ab43-4e30-8a9f-b9c5b7659d73
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854399374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.854399374
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3378792385
Short name T466
Test name
Test status
Simulation time 344369675 ps
CPU time 5.42 seconds
Started May 26 01:02:25 PM PDT 24
Finished May 26 01:02:31 PM PDT 24
Peak memory 211180 kb
Host smart-1ed1d087-9da0-4ca6-8096-a9198c0a539d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378792385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3378792385
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2213494432
Short name T386
Test name
Test status
Simulation time 3587151417 ps
CPU time 16.6 seconds
Started May 26 01:02:26 PM PDT 24
Finished May 26 01:02:44 PM PDT 24
Peak memory 219480 kb
Host smart-622ccefb-3f89-460f-9873-833cc8c7e4b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213494432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2213494432
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.313029950
Short name T455
Test name
Test status
Simulation time 4971122512 ps
CPU time 46.22 seconds
Started May 26 01:02:27 PM PDT 24
Finished May 26 01:03:14 PM PDT 24
Peak memory 219368 kb
Host smart-cff0b9bb-3845-451b-abf6-5c7414a68b96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313029950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.313029950
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2759293084
Short name T79
Test name
Test status
Simulation time 3064010860 ps
CPU time 14.1 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:02:23 PM PDT 24
Peak memory 211208 kb
Host smart-a4c99652-e8ba-4d68-b78d-5fb8866559bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759293084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2759293084
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2677558691
Short name T67
Test name
Test status
Simulation time 168265813 ps
CPU time 4.53 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:02:13 PM PDT 24
Peak memory 211200 kb
Host smart-9e14ecae-35ed-4a02-87cf-999b49d2ca7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677558691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2677558691
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2895273561
Short name T82
Test name
Test status
Simulation time 2031627615 ps
CPU time 13.82 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:22 PM PDT 24
Peak memory 211288 kb
Host smart-cd097b57-f14e-402a-beb2-ede95704cc89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895273561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2895273561
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1402684798
Short name T428
Test name
Test status
Simulation time 1818939529 ps
CPU time 12.34 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:02:21 PM PDT 24
Peak memory 219492 kb
Host smart-f11b2f6b-6ea0-4286-baa1-efdcabda3989
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402684798 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1402684798
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.34459450
Short name T96
Test name
Test status
Simulation time 2122272308 ps
CPU time 15.38 seconds
Started May 26 01:02:14 PM PDT 24
Finished May 26 01:02:31 PM PDT 24
Peak memory 211136 kb
Host smart-a66ff591-baf0-4363-ba96-a436099a4c11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34459450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.34459450
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1925901379
Short name T380
Test name
Test status
Simulation time 7837302818 ps
CPU time 15.17 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:02:26 PM PDT 24
Peak memory 211128 kb
Host smart-038d383e-d290-4ce6-9f16-a753f0b6e58c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925901379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1925901379
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1332818414
Short name T419
Test name
Test status
Simulation time 757146081 ps
CPU time 8.49 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:16 PM PDT 24
Peak memory 211044 kb
Host smart-430ad21c-f460-4f57-b241-0ff8d4bb6fcd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332818414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1332818414
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3647143848
Short name T446
Test name
Test status
Simulation time 89159190227 ps
CPU time 80.59 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:03:29 PM PDT 24
Peak memory 211348 kb
Host smart-4a56e01c-0913-481e-8b90-9b60e1b53aa3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647143848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3647143848
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.572818067
Short name T423
Test name
Test status
Simulation time 1735966796 ps
CPU time 13.83 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:02:23 PM PDT 24
Peak memory 211268 kb
Host smart-573f7996-9aaf-4d4a-8d14-fe56d75cd6a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572818067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.572818067
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3068327237
Short name T459
Test name
Test status
Simulation time 1034753760 ps
CPU time 14.38 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:21 PM PDT 24
Peak memory 219512 kb
Host smart-53e80e43-021b-4a38-b70a-8f2d10b4b309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068327237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3068327237
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3237332836
Short name T117
Test name
Test status
Simulation time 2523891179 ps
CPU time 72.83 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:03:25 PM PDT 24
Peak memory 211144 kb
Host smart-d63dfa49-62a7-404c-b753-80d1f35ec603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237332836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3237332836
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4294012940
Short name T393
Test name
Test status
Simulation time 1597610425 ps
CPU time 13.5 seconds
Started May 26 01:02:07 PM PDT 24
Finished May 26 01:02:23 PM PDT 24
Peak memory 211260 kb
Host smart-37a2fd2d-f8e1-4630-88a9-84e01a55b3b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294012940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4294012940
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3120371585
Short name T402
Test name
Test status
Simulation time 7315573382 ps
CPU time 9.35 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:02:21 PM PDT 24
Peak memory 211108 kb
Host smart-4bedcf98-8fc6-4ba0-9b3b-2199cd311bb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120371585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3120371585
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2755513973
Short name T90
Test name
Test status
Simulation time 2728109299 ps
CPU time 15.07 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:22 PM PDT 24
Peak memory 211360 kb
Host smart-42c58ba4-890a-4018-86ad-834838daae17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755513973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2755513973
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.822684643
Short name T396
Test name
Test status
Simulation time 881442336 ps
CPU time 7.49 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:02:19 PM PDT 24
Peak memory 219388 kb
Host smart-72a9528b-1171-444e-a7d4-9c9e80a3add0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822684643 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.822684643
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.849352244
Short name T84
Test name
Test status
Simulation time 1751872141 ps
CPU time 9.79 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:02:22 PM PDT 24
Peak memory 211180 kb
Host smart-935ddeef-c63a-407e-a669-198e4ec8d0c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849352244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.849352244
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2574483218
Short name T418
Test name
Test status
Simulation time 305814543 ps
CPU time 6.14 seconds
Started May 26 01:02:07 PM PDT 24
Finished May 26 01:02:16 PM PDT 24
Peak memory 211124 kb
Host smart-28f1f7df-1dc2-436d-9507-63119b54d168
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574483218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2574483218
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.792364739
Short name T398
Test name
Test status
Simulation time 6901063893 ps
CPU time 14.78 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:23 PM PDT 24
Peak memory 211188 kb
Host smart-c09893cd-2ed8-46cf-9d84-b762b4c863b9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792364739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
792364739
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1148476629
Short name T87
Test name
Test status
Simulation time 30912140664 ps
CPU time 58.75 seconds
Started May 26 01:02:07 PM PDT 24
Finished May 26 01:03:09 PM PDT 24
Peak memory 211352 kb
Host smart-0ea4da26-0c63-4d48-b889-c7f9d67c7c4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148476629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1148476629
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1308546185
Short name T429
Test name
Test status
Simulation time 241914853 ps
CPU time 5.89 seconds
Started May 26 01:02:05 PM PDT 24
Finished May 26 01:02:14 PM PDT 24
Peak memory 211132 kb
Host smart-9c286b6d-f13b-415f-ada9-d993915fbe24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308546185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1308546185
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1056483137
Short name T421
Test name
Test status
Simulation time 5011220865 ps
CPU time 18.06 seconds
Started May 26 01:02:14 PM PDT 24
Finished May 26 01:02:33 PM PDT 24
Peak memory 219444 kb
Host smart-2793e67a-263a-466a-a393-eda132be2967
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056483137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1056483137
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2005946382
Short name T118
Test name
Test status
Simulation time 153750369 ps
CPU time 36.84 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:02:47 PM PDT 24
Peak memory 212096 kb
Host smart-1fbe6c58-74f6-47b3-be65-5503ee7e4c33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005946382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2005946382
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1194970055
Short name T98
Test name
Test status
Simulation time 6484670247 ps
CPU time 14.29 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:02:26 PM PDT 24
Peak memory 211248 kb
Host smart-40e9e2cb-c7c7-4552-9dba-84bee1f8bb11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194970055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1194970055
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2621404130
Short name T389
Test name
Test status
Simulation time 3423217778 ps
CPU time 14.11 seconds
Started May 26 01:02:14 PM PDT 24
Finished May 26 01:02:29 PM PDT 24
Peak memory 211236 kb
Host smart-0bcc8a7d-a42e-401b-a5d0-3c146df341da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621404130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2621404130
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4048655773
Short name T470
Test name
Test status
Simulation time 7134317413 ps
CPU time 16.77 seconds
Started May 26 01:02:07 PM PDT 24
Finished May 26 01:02:27 PM PDT 24
Peak memory 211200 kb
Host smart-e27b94ab-1444-4588-b039-441b6858140d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048655773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4048655773
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3239219650
Short name T447
Test name
Test status
Simulation time 5535781399 ps
CPU time 16.33 seconds
Started May 26 01:02:10 PM PDT 24
Finished May 26 01:02:29 PM PDT 24
Peak memory 219468 kb
Host smart-35f72685-31a0-425c-84ac-d35647d27974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239219650 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3239219650
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3334463736
Short name T92
Test name
Test status
Simulation time 592958227 ps
CPU time 4.48 seconds
Started May 26 01:02:07 PM PDT 24
Finished May 26 01:02:14 PM PDT 24
Peak memory 211144 kb
Host smart-456ee8a9-8231-4dec-8edd-ddbc68be8939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334463736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3334463736
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3445491491
Short name T430
Test name
Test status
Simulation time 1488494677 ps
CPU time 6.61 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:02:17 PM PDT 24
Peak memory 211004 kb
Host smart-9bb3432e-7cfa-4788-be98-1cae7eaa7c2a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445491491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3445491491
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.254539247
Short name T408
Test name
Test status
Simulation time 214813347 ps
CPU time 4.16 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:02:15 PM PDT 24
Peak memory 211064 kb
Host smart-dd59e305-db29-455e-ae1c-219df395b90d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254539247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
254539247
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.523070254
Short name T432
Test name
Test status
Simulation time 543396363 ps
CPU time 27.92 seconds
Started May 26 01:02:07 PM PDT 24
Finished May 26 01:02:38 PM PDT 24
Peak memory 211184 kb
Host smart-fe98bd4a-2002-427a-a020-2f1720d3e841
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523070254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.523070254
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4135176197
Short name T443
Test name
Test status
Simulation time 6181597304 ps
CPU time 13.44 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:02:25 PM PDT 24
Peak memory 211216 kb
Host smart-c394cc14-ebf0-4ae6-aa14-9b2a196d3e1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135176197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4135176197
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1776657020
Short name T452
Test name
Test status
Simulation time 85545366 ps
CPU time 7.42 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:02:18 PM PDT 24
Peak memory 219644 kb
Host smart-c9359358-fdc9-4de8-b87c-56532e48e477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776657020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1776657020
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3588324884
Short name T109
Test name
Test status
Simulation time 753458867 ps
CPU time 67.96 seconds
Started May 26 01:02:11 PM PDT 24
Finished May 26 01:03:21 PM PDT 24
Peak memory 212100 kb
Host smart-08b7ac5f-97f8-4996-ad5e-17a8a6914ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588324884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3588324884
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1795461159
Short name T469
Test name
Test status
Simulation time 6906401812 ps
CPU time 9.56 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:02:18 PM PDT 24
Peak memory 213636 kb
Host smart-4ff18eb9-db3f-4a3a-8ed0-f8c842fd06e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795461159 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1795461159
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3431754011
Short name T85
Test name
Test status
Simulation time 178442793 ps
CPU time 4.25 seconds
Started May 26 01:02:07 PM PDT 24
Finished May 26 01:02:14 PM PDT 24
Peak memory 211132 kb
Host smart-a14b8f7b-c98e-4fcb-b290-ee9665ba5175
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431754011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3431754011
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3755917552
Short name T458
Test name
Test status
Simulation time 3667407463 ps
CPU time 16.34 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:02:28 PM PDT 24
Peak memory 211240 kb
Host smart-7b718499-c54a-4c82-afe8-dc1000253593
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755917552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3755917552
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1403244054
Short name T395
Test name
Test status
Simulation time 89835839 ps
CPU time 7.18 seconds
Started May 26 01:02:10 PM PDT 24
Finished May 26 01:02:20 PM PDT 24
Peak memory 219432 kb
Host smart-006aaadf-d1b4-4798-a305-82f72d30c1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403244054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1403244054
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2703541569
Short name T121
Test name
Test status
Simulation time 524993728 ps
CPU time 69.92 seconds
Started May 26 01:02:07 PM PDT 24
Finished May 26 01:03:20 PM PDT 24
Peak memory 212284 kb
Host smart-bc2ac913-7d40-4b7a-8218-0a5445f2cd53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703541569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2703541569
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1990022627
Short name T435
Test name
Test status
Simulation time 10947959441 ps
CPU time 14.79 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:02:25 PM PDT 24
Peak memory 213568 kb
Host smart-cae5d08b-69fe-4b3b-b602-67c87797cf18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990022627 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1990022627
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3677412531
Short name T411
Test name
Test status
Simulation time 1543702887 ps
CPU time 13.48 seconds
Started May 26 01:02:04 PM PDT 24
Finished May 26 01:02:21 PM PDT 24
Peak memory 211248 kb
Host smart-9ffbc858-4163-4199-911f-21f6944b9b85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677412531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3677412531
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.458195146
Short name T468
Test name
Test status
Simulation time 6031492003 ps
CPU time 53.64 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:03:04 PM PDT 24
Peak memory 211240 kb
Host smart-f9437cb7-e491-4180-8a31-f99eb9ad0229
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458195146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.458195146
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3385042677
Short name T94
Test name
Test status
Simulation time 3011651380 ps
CPU time 6.46 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:02:17 PM PDT 24
Peak memory 211164 kb
Host smart-16523be6-0492-47c1-b188-7e88fb4a220c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385042677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3385042677
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.401124482
Short name T449
Test name
Test status
Simulation time 2013086466 ps
CPU time 18.22 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:02:30 PM PDT 24
Peak memory 219348 kb
Host smart-7958c3a9-e770-4089-93f3-5413a9c104ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401124482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.401124482
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.768910148
Short name T464
Test name
Test status
Simulation time 2449018975 ps
CPU time 48.96 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:02:58 PM PDT 24
Peak memory 212096 kb
Host smart-eb9e5e5b-c817-4089-9e3a-c9312346576f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768910148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.768910148
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4084924011
Short name T451
Test name
Test status
Simulation time 2364824847 ps
CPU time 11.39 seconds
Started May 26 01:02:14 PM PDT 24
Finished May 26 01:02:27 PM PDT 24
Peak memory 219464 kb
Host smart-8ef06a2f-e831-44c4-806a-2f02d3a319c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084924011 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4084924011
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.504503393
Short name T399
Test name
Test status
Simulation time 128087176 ps
CPU time 5.11 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:02:14 PM PDT 24
Peak memory 211184 kb
Host smart-878f4f55-6b05-427f-bbe9-d0ced0250368
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504503393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.504503393
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1193466634
Short name T71
Test name
Test status
Simulation time 26810435624 ps
CPU time 40.15 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:02:52 PM PDT 24
Peak memory 211212 kb
Host smart-51447a82-0ddc-474c-b919-644e8dfc1234
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193466634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1193466634
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1492627732
Short name T412
Test name
Test status
Simulation time 2235530218 ps
CPU time 9.49 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:02:19 PM PDT 24
Peak memory 211260 kb
Host smart-216f95c8-b91f-4e9a-a231-d938ed4cbadc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492627732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1492627732
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1676099911
Short name T377
Test name
Test status
Simulation time 4623234459 ps
CPU time 13.11 seconds
Started May 26 01:02:06 PM PDT 24
Finished May 26 01:02:22 PM PDT 24
Peak memory 219536 kb
Host smart-e0d84f4a-7204-4ea3-9f63-fc6438e64120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676099911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1676099911
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2525687219
Short name T120
Test name
Test status
Simulation time 3043804434 ps
CPU time 39.39 seconds
Started May 26 01:02:07 PM PDT 24
Finished May 26 01:02:49 PM PDT 24
Peak memory 211748 kb
Host smart-b6c47f07-309f-4471-a3e3-d935aa052c25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525687219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2525687219
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4027201558
Short name T415
Test name
Test status
Simulation time 833300332 ps
CPU time 9.65 seconds
Started May 26 01:02:14 PM PDT 24
Finished May 26 01:02:24 PM PDT 24
Peak memory 219444 kb
Host smart-746ccc0e-88b4-4933-823d-96f6cb0eb741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027201558 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4027201558
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4249960092
Short name T427
Test name
Test status
Simulation time 4100844254 ps
CPU time 16.21 seconds
Started May 26 01:02:19 PM PDT 24
Finished May 26 01:02:36 PM PDT 24
Peak memory 211164 kb
Host smart-4bafa416-2d1e-462d-8487-22cfa51ce941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249960092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4249960092
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1723966981
Short name T81
Test name
Test status
Simulation time 16386049106 ps
CPU time 66.29 seconds
Started May 26 01:02:09 PM PDT 24
Finished May 26 01:03:18 PM PDT 24
Peak memory 211184 kb
Host smart-780b9bc4-b52b-4428-99c3-5a04b34603ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723966981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1723966981
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1900258205
Short name T425
Test name
Test status
Simulation time 3812612315 ps
CPU time 15.39 seconds
Started May 26 01:02:15 PM PDT 24
Finished May 26 01:02:31 PM PDT 24
Peak memory 211232 kb
Host smart-68892fa3-7957-444e-9af8-76d703051b89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900258205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1900258205
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.4154177131
Short name T397
Test name
Test status
Simulation time 209872044 ps
CPU time 8.04 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:02:19 PM PDT 24
Peak memory 219408 kb
Host smart-2b24c8cb-933f-46c8-907e-3732153852c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154177131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.4154177131
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1385928111
Short name T110
Test name
Test status
Simulation time 230282797 ps
CPU time 68.21 seconds
Started May 26 01:02:08 PM PDT 24
Finished May 26 01:03:19 PM PDT 24
Peak memory 211344 kb
Host smart-6b7a9f66-bf3d-4f8e-84bd-90091ec99bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385928111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1385928111
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1041987132
Short name T384
Test name
Test status
Simulation time 368048251 ps
CPU time 4.48 seconds
Started May 26 01:02:15 PM PDT 24
Finished May 26 01:02:20 PM PDT 24
Peak memory 212268 kb
Host smart-1d720fcc-ed24-41f5-bd16-58aa9a85c618
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041987132 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1041987132
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.375345519
Short name T381
Test name
Test status
Simulation time 540617458 ps
CPU time 6.21 seconds
Started May 26 01:02:17 PM PDT 24
Finished May 26 01:02:24 PM PDT 24
Peak memory 211136 kb
Host smart-ae086dcc-2044-427d-85ba-dca205887fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375345519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.375345519
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4263662889
Short name T422
Test name
Test status
Simulation time 2082446240 ps
CPU time 31.46 seconds
Started May 26 01:02:13 PM PDT 24
Finished May 26 01:02:46 PM PDT 24
Peak memory 211184 kb
Host smart-58b5a0d5-101a-4995-9b1d-59cb0c399558
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263662889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.4263662889
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1502579680
Short name T434
Test name
Test status
Simulation time 4049656036 ps
CPU time 16.17 seconds
Started May 26 01:02:16 PM PDT 24
Finished May 26 01:02:33 PM PDT 24
Peak memory 211208 kb
Host smart-80f5629a-902b-4af6-8555-7733d225369d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502579680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1502579680
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.645853158
Short name T404
Test name
Test status
Simulation time 5881924417 ps
CPU time 16.97 seconds
Started May 26 01:02:17 PM PDT 24
Finished May 26 01:02:35 PM PDT 24
Peak memory 219540 kb
Host smart-b9699240-96ac-4f48-9f40-4d027b674eae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645853158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.645853158
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.116707265
Short name T113
Test name
Test status
Simulation time 1451709866 ps
CPU time 44.17 seconds
Started May 26 01:02:17 PM PDT 24
Finished May 26 01:03:02 PM PDT 24
Peak memory 211840 kb
Host smart-4d48d47b-7767-4c0d-90fd-c09045d8b780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116707265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.116707265
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1332933744
Short name T21
Test name
Test status
Simulation time 11682018255 ps
CPU time 9.13 seconds
Started May 26 01:59:17 PM PDT 24
Finished May 26 01:59:27 PM PDT 24
Peak memory 211084 kb
Host smart-364face3-19dd-4017-b172-1829e2cd8c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332933744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1332933744
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2101398944
Short name T251
Test name
Test status
Simulation time 229878297070 ps
CPU time 562.53 seconds
Started May 26 01:59:16 PM PDT 24
Finished May 26 02:08:39 PM PDT 24
Peak memory 224464 kb
Host smart-858cc64e-97eb-4a7a-ab3c-f4e3d0a4dadc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101398944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2101398944
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3229587350
Short name T330
Test name
Test status
Simulation time 3310714287 ps
CPU time 14.73 seconds
Started May 26 01:59:15 PM PDT 24
Finished May 26 01:59:31 PM PDT 24
Peak memory 211000 kb
Host smart-fda18993-2dc4-4a01-b10c-3854cca12d2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229587350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3229587350
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.73916781
Short name T32
Test name
Test status
Simulation time 7305097858 ps
CPU time 105.42 seconds
Started May 26 01:59:15 PM PDT 24
Finished May 26 02:01:01 PM PDT 24
Peak memory 230500 kb
Host smart-0f535394-bc3c-44b9-af88-9a51b28f9c32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73916781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.73916781
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.30146842
Short name T282
Test name
Test status
Simulation time 368433355 ps
CPU time 10.5 seconds
Started May 26 01:59:18 PM PDT 24
Finished May 26 01:59:29 PM PDT 24
Peak memory 219148 kb
Host smart-1ea65f23-e993-4eff-8c99-c1a9acf8e60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30146842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.30146842
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1219248316
Short name T292
Test name
Test status
Simulation time 24743226145 ps
CPU time 77.93 seconds
Started May 26 01:59:17 PM PDT 24
Finished May 26 02:00:36 PM PDT 24
Peak memory 219196 kb
Host smart-dbcd083e-4953-443a-a48d-c398efc6f9c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219248316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1219248316
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.197713843
Short name T148
Test name
Test status
Simulation time 510961826 ps
CPU time 7.56 seconds
Started May 26 01:59:18 PM PDT 24
Finished May 26 01:59:26 PM PDT 24
Peak memory 211048 kb
Host smart-2ea0bfdb-f60a-444d-abf1-d7880068f9e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197713843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.197713843
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4033097611
Short name T146
Test name
Test status
Simulation time 29157740279 ps
CPU time 328.33 seconds
Started May 26 01:59:15 PM PDT 24
Finished May 26 02:04:44 PM PDT 24
Peak memory 236484 kb
Host smart-4665c77e-922d-4b48-b0d4-7126d9bd2c31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033097611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4033097611
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3009717072
Short name T247
Test name
Test status
Simulation time 9667034947 ps
CPU time 23.2 seconds
Started May 26 01:59:17 PM PDT 24
Finished May 26 01:59:41 PM PDT 24
Peak memory 211932 kb
Host smart-2c8374dc-57c3-48c6-9d51-870643ea6100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009717072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3009717072
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3711137979
Short name T215
Test name
Test status
Simulation time 669180318 ps
CPU time 9.85 seconds
Started May 26 01:59:18 PM PDT 24
Finished May 26 01:59:28 PM PDT 24
Peak memory 211012 kb
Host smart-d7b4ee37-55cf-4ccd-864a-406a156e05c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3711137979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3711137979
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3291916153
Short name T30
Test name
Test status
Simulation time 407956609 ps
CPU time 69.42 seconds
Started May 26 01:59:18 PM PDT 24
Finished May 26 02:00:28 PM PDT 24
Peak memory 240564 kb
Host smart-5deffb76-283a-4727-9448-02f88dc90ade
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291916153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3291916153
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4213087401
Short name T219
Test name
Test status
Simulation time 1987259820 ps
CPU time 22.53 seconds
Started May 26 01:59:15 PM PDT 24
Finished May 26 01:59:38 PM PDT 24
Peak memory 219144 kb
Host smart-25276417-0ff1-4830-af30-a3a53673563d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213087401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4213087401
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1963265388
Short name T7
Test name
Test status
Simulation time 3621103935 ps
CPU time 44.14 seconds
Started May 26 01:59:17 PM PDT 24
Finished May 26 02:00:02 PM PDT 24
Peak memory 215020 kb
Host smart-403cc187-03c9-4bee-adfc-dc0bad9d1b8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963265388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1963265388
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4080530439
Short name T37
Test name
Test status
Simulation time 347460903 ps
CPU time 4.34 seconds
Started May 26 01:59:41 PM PDT 24
Finished May 26 01:59:47 PM PDT 24
Peak memory 211056 kb
Host smart-33bd19ff-88e6-4a8e-9ef1-405a8578e4fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080530439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4080530439
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1781332388
Short name T143
Test name
Test status
Simulation time 42705462588 ps
CPU time 370.8 seconds
Started May 26 01:59:44 PM PDT 24
Finished May 26 02:05:56 PM PDT 24
Peak memory 236496 kb
Host smart-d5b65baf-1365-4671-a198-b40567815ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781332388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1781332388
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1065377597
Short name T171
Test name
Test status
Simulation time 4991606614 ps
CPU time 17.47 seconds
Started May 26 01:59:40 PM PDT 24
Finished May 26 01:59:59 PM PDT 24
Peak memory 211904 kb
Host smart-c9e623ba-6ef0-4106-a7b6-c8b906ceae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065377597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1065377597
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.972192045
Short name T149
Test name
Test status
Simulation time 1495018837 ps
CPU time 5.75 seconds
Started May 26 01:59:33 PM PDT 24
Finished May 26 01:59:40 PM PDT 24
Peak memory 211004 kb
Host smart-44669eb2-567b-4429-a81f-c77fad555959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972192045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.972192045
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3543680753
Short name T168
Test name
Test status
Simulation time 1683911043 ps
CPU time 15.52 seconds
Started May 26 01:59:35 PM PDT 24
Finished May 26 01:59:51 PM PDT 24
Peak memory 219144 kb
Host smart-5b15cb91-de78-4388-9c5d-07856bd7d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543680753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3543680753
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2233894084
Short name T106
Test name
Test status
Simulation time 16948845445 ps
CPU time 34.99 seconds
Started May 26 01:59:35 PM PDT 24
Finished May 26 02:00:11 PM PDT 24
Peak memory 219240 kb
Host smart-d817fd9c-ae75-47b3-a411-149181d9c278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233894084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2233894084
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1553331633
Short name T210
Test name
Test status
Simulation time 1657168218 ps
CPU time 7.07 seconds
Started May 26 01:59:44 PM PDT 24
Finished May 26 01:59:52 PM PDT 24
Peak memory 211028 kb
Host smart-e5a53c99-ee21-49c8-97db-7ed143685f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553331633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1553331633
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3531070053
Short name T263
Test name
Test status
Simulation time 10489653562 ps
CPU time 166.34 seconds
Started May 26 01:59:41 PM PDT 24
Finished May 26 02:02:28 PM PDT 24
Peak memory 232788 kb
Host smart-34f3bc48-2dd6-48d2-9d32-cdab0ca8c670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531070053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3531070053
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1307729337
Short name T241
Test name
Test status
Simulation time 850291629 ps
CPU time 10.45 seconds
Started May 26 01:59:40 PM PDT 24
Finished May 26 01:59:52 PM PDT 24
Peak memory 211004 kb
Host smart-0a6e8f06-aec0-4251-bd34-23670640b975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307729337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1307729337
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1836653291
Short name T262
Test name
Test status
Simulation time 9139396047 ps
CPU time 37.09 seconds
Started May 26 01:59:41 PM PDT 24
Finished May 26 02:00:19 PM PDT 24
Peak memory 213880 kb
Host smart-76699161-56af-4c3f-b239-6058eea6d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836653291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1836653291
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1744044952
Short name T259
Test name
Test status
Simulation time 1738360926 ps
CPU time 11.05 seconds
Started May 26 01:59:40 PM PDT 24
Finished May 26 01:59:52 PM PDT 24
Peak memory 211844 kb
Host smart-b98badf3-2be9-4070-80a6-054afc29ebbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744044952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1744044952
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2706487379
Short name T275
Test name
Test status
Simulation time 7853327713 ps
CPU time 15.42 seconds
Started May 26 01:59:39 PM PDT 24
Finished May 26 01:59:56 PM PDT 24
Peak memory 211116 kb
Host smart-89b9849b-1f9b-481a-8597-a2463abc4c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706487379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2706487379
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3208103362
Short name T296
Test name
Test status
Simulation time 75290664724 ps
CPU time 188.4 seconds
Started May 26 01:59:40 PM PDT 24
Finished May 26 02:02:49 PM PDT 24
Peak memory 236452 kb
Host smart-1de473f7-c8d5-48b4-893d-33906c287ef9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208103362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3208103362
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3062829569
Short name T326
Test name
Test status
Simulation time 3782086046 ps
CPU time 31.57 seconds
Started May 26 01:59:39 PM PDT 24
Finished May 26 02:00:12 PM PDT 24
Peak memory 211700 kb
Host smart-7395d45f-5514-46cc-97d2-f277fdc7073c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062829569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3062829569
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.736519093
Short name T230
Test name
Test status
Simulation time 2684038502 ps
CPU time 13.51 seconds
Started May 26 01:59:43 PM PDT 24
Finished May 26 01:59:58 PM PDT 24
Peak memory 211080 kb
Host smart-f7bb71d0-e1a9-4b54-965c-f13d96794924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=736519093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.736519093
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.700593773
Short name T129
Test name
Test status
Simulation time 4831701592 ps
CPU time 22.03 seconds
Started May 26 01:59:40 PM PDT 24
Finished May 26 02:00:03 PM PDT 24
Peak memory 219236 kb
Host smart-be086173-78d6-4dbe-aefc-27d87842c44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700593773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.700593773
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.148468341
Short name T323
Test name
Test status
Simulation time 5323758476 ps
CPU time 59.55 seconds
Started May 26 01:59:39 PM PDT 24
Finished May 26 02:00:40 PM PDT 24
Peak memory 216448 kb
Host smart-103e51f3-e02d-4c06-957b-efdb551f02b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148468341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.148468341
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.601434864
Short name T238
Test name
Test status
Simulation time 10034988539 ps
CPU time 16.03 seconds
Started May 26 01:59:38 PM PDT 24
Finished May 26 01:59:55 PM PDT 24
Peak memory 211120 kb
Host smart-f8c9635b-5062-460f-9d98-1eb39c7a211c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601434864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.601434864
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2262718637
Short name T329
Test name
Test status
Simulation time 89100358474 ps
CPU time 283.61 seconds
Started May 26 01:59:40 PM PDT 24
Finished May 26 02:04:25 PM PDT 24
Peak memory 212308 kb
Host smart-b9227f9d-71a1-41a4-8a1c-9c68c8602fc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262718637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2262718637
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.436859726
Short name T221
Test name
Test status
Simulation time 1279757938 ps
CPU time 9.61 seconds
Started May 26 01:59:40 PM PDT 24
Finished May 26 01:59:51 PM PDT 24
Peak memory 211676 kb
Host smart-d444894d-e50b-4c10-87bf-583a976917c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436859726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.436859726
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3227379544
Short name T130
Test name
Test status
Simulation time 8562711230 ps
CPU time 17.16 seconds
Started May 26 01:59:43 PM PDT 24
Finished May 26 02:00:00 PM PDT 24
Peak memory 211068 kb
Host smart-81650ae9-4965-41af-a16c-ce42542c539b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227379544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3227379544
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3479647117
Short name T268
Test name
Test status
Simulation time 187253280 ps
CPU time 10.5 seconds
Started May 26 01:59:43 PM PDT 24
Finished May 26 01:59:55 PM PDT 24
Peak memory 219184 kb
Host smart-733c461f-4894-4b02-a392-a01acc6aa49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479647117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3479647117
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1354584845
Short name T196
Test name
Test status
Simulation time 13571152722 ps
CPU time 55.58 seconds
Started May 26 01:59:44 PM PDT 24
Finished May 26 02:00:40 PM PDT 24
Peak memory 216288 kb
Host smart-124c93b2-1017-4d1f-bcc3-2f3848fcead2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354584845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1354584845
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4167288601
Short name T316
Test name
Test status
Simulation time 44033913525 ps
CPU time 419.45 seconds
Started May 26 01:59:41 PM PDT 24
Finished May 26 02:06:42 PM PDT 24
Peak memory 225620 kb
Host smart-e8543940-6721-48d2-a4fb-394f4243db12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167288601 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.4167288601
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3143603052
Short name T191
Test name
Test status
Simulation time 954088388 ps
CPU time 6.24 seconds
Started May 26 01:59:45 PM PDT 24
Finished May 26 01:59:52 PM PDT 24
Peak memory 211064 kb
Host smart-f4cca105-f5cd-4f07-bdb9-b0f62a757e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143603052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3143603052
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1096492269
Short name T44
Test name
Test status
Simulation time 145595889472 ps
CPU time 334.93 seconds
Started May 26 01:59:43 PM PDT 24
Finished May 26 02:05:19 PM PDT 24
Peak memory 237492 kb
Host smart-e97b4d71-1c95-488b-975a-ae1b26d1da7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096492269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1096492269
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4043134450
Short name T264
Test name
Test status
Simulation time 3937130434 ps
CPU time 31.41 seconds
Started May 26 01:59:40 PM PDT 24
Finished May 26 02:00:12 PM PDT 24
Peak memory 211736 kb
Host smart-7e026e4c-013f-4814-a87a-20716147b7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043134450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4043134450
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2510766512
Short name T315
Test name
Test status
Simulation time 7319317915 ps
CPU time 11.08 seconds
Started May 26 01:59:42 PM PDT 24
Finished May 26 01:59:54 PM PDT 24
Peak memory 211036 kb
Host smart-ab1f8653-b56d-43e5-9923-a18c5aad6429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510766512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2510766512
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1154995457
Short name T313
Test name
Test status
Simulation time 41025585132 ps
CPU time 41.28 seconds
Started May 26 01:59:39 PM PDT 24
Finished May 26 02:00:21 PM PDT 24
Peak memory 219204 kb
Host smart-d7b422cb-9875-4338-9066-4fc42f1b0909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154995457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1154995457
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3616088996
Short name T240
Test name
Test status
Simulation time 12652780789 ps
CPU time 18.02 seconds
Started May 26 01:59:38 PM PDT 24
Finished May 26 01:59:57 PM PDT 24
Peak memory 210968 kb
Host smart-ef36811a-dbd9-4c8f-855e-62e0c01c0cd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616088996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3616088996
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2258700552
Short name T354
Test name
Test status
Simulation time 8034761188 ps
CPU time 14.99 seconds
Started May 26 01:59:50 PM PDT 24
Finished May 26 02:00:07 PM PDT 24
Peak memory 211068 kb
Host smart-251501fb-7b8b-4ad3-92e2-d09c5931a5f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258700552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2258700552
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2767257724
Short name T328
Test name
Test status
Simulation time 80334332120 ps
CPU time 373.86 seconds
Started May 26 01:59:48 PM PDT 24
Finished May 26 02:06:03 PM PDT 24
Peak memory 233936 kb
Host smart-2016e059-9797-49af-84db-99bc509bfec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767257724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2767257724
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1940026256
Short name T198
Test name
Test status
Simulation time 747930204 ps
CPU time 14.52 seconds
Started May 26 01:59:47 PM PDT 24
Finished May 26 02:00:02 PM PDT 24
Peak memory 211532 kb
Host smart-76e41efa-01f6-4d65-ae71-b62023ecd677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940026256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1940026256
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3719237457
Short name T225
Test name
Test status
Simulation time 100602326 ps
CPU time 5.75 seconds
Started May 26 01:59:48 PM PDT 24
Finished May 26 01:59:55 PM PDT 24
Peak memory 210968 kb
Host smart-340f8805-8436-4fea-b65f-22b5d67f6e2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719237457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3719237457
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2977384668
Short name T257
Test name
Test status
Simulation time 1757252857 ps
CPU time 20.43 seconds
Started May 26 01:59:46 PM PDT 24
Finished May 26 02:00:07 PM PDT 24
Peak memory 213228 kb
Host smart-98be8c5c-770e-4870-81d1-6bf69e1372ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977384668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2977384668
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.646090913
Short name T77
Test name
Test status
Simulation time 1033901012 ps
CPU time 17.31 seconds
Started May 26 01:59:47 PM PDT 24
Finished May 26 02:00:05 PM PDT 24
Peak memory 219148 kb
Host smart-54e97085-fe7f-442a-adb3-9fc8a7a1a8ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646090913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.646090913
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3607457932
Short name T297
Test name
Test status
Simulation time 26597621840 ps
CPU time 2850.62 seconds
Started May 26 01:59:50 PM PDT 24
Finished May 26 02:47:23 PM PDT 24
Peak memory 227488 kb
Host smart-29e98e1a-4c7d-4d77-ae74-eb15bc786b55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607457932 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3607457932
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.276468750
Short name T173
Test name
Test status
Simulation time 58835838397 ps
CPU time 152.47 seconds
Started May 26 01:59:48 PM PDT 24
Finished May 26 02:02:22 PM PDT 24
Peak memory 230492 kb
Host smart-a3dc4c25-d0cb-412e-8ff3-55132f1cc0f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276468750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.276468750
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2120865175
Short name T153
Test name
Test status
Simulation time 5719641760 ps
CPU time 18.95 seconds
Started May 26 01:59:47 PM PDT 24
Finished May 26 02:00:08 PM PDT 24
Peak memory 212100 kb
Host smart-a102fc78-afd8-41a2-ac51-74ef30dc6802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120865175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2120865175
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.103231698
Short name T273
Test name
Test status
Simulation time 101089868 ps
CPU time 5.89 seconds
Started May 26 01:59:49 PM PDT 24
Finished May 26 01:59:56 PM PDT 24
Peak memory 210988 kb
Host smart-2f524613-370a-4f59-82d8-93ced054dd8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103231698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.103231698
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2618602891
Short name T5
Test name
Test status
Simulation time 2882317131 ps
CPU time 20.52 seconds
Started May 26 01:59:48 PM PDT 24
Finished May 26 02:00:11 PM PDT 24
Peak memory 219200 kb
Host smart-e94efbe7-e5da-4ba9-8d53-179b488ef90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618602891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2618602891
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.833976638
Short name T261
Test name
Test status
Simulation time 11441683493 ps
CPU time 76.64 seconds
Started May 26 01:59:47 PM PDT 24
Finished May 26 02:01:05 PM PDT 24
Peak memory 217488 kb
Host smart-6ef54c68-2d32-48d8-9194-504bcae437ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833976638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.833976638
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3379795637
Short name T61
Test name
Test status
Simulation time 1940630932 ps
CPU time 10.07 seconds
Started May 26 01:59:47 PM PDT 24
Finished May 26 01:59:59 PM PDT 24
Peak memory 211028 kb
Host smart-881d7d4c-73be-42d2-b168-f74b910d4acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379795637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3379795637
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1734773974
Short name T213
Test name
Test status
Simulation time 6256794984 ps
CPU time 124.56 seconds
Started May 26 01:59:48 PM PDT 24
Finished May 26 02:01:54 PM PDT 24
Peak memory 233472 kb
Host smart-fa48a2e5-dddb-4578-b692-ae0374396d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734773974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1734773974
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1748119548
Short name T340
Test name
Test status
Simulation time 1833827172 ps
CPU time 20.43 seconds
Started May 26 01:59:48 PM PDT 24
Finished May 26 02:00:10 PM PDT 24
Peak memory 219204 kb
Host smart-1a345065-78ff-491e-a922-2bb8b81df4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748119548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1748119548
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.258076637
Short name T164
Test name
Test status
Simulation time 1300393753 ps
CPU time 5.64 seconds
Started May 26 01:59:46 PM PDT 24
Finished May 26 01:59:53 PM PDT 24
Peak memory 210992 kb
Host smart-a04a8327-3179-4e1b-8156-c73bf2d2ce69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258076637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.258076637
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1115011785
Short name T174
Test name
Test status
Simulation time 3305758531 ps
CPU time 32.34 seconds
Started May 26 01:59:49 PM PDT 24
Finished May 26 02:00:23 PM PDT 24
Peak memory 219200 kb
Host smart-51bfc9b1-6188-4b37-ba1d-d2ce8083db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115011785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1115011785
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1788804811
Short name T139
Test name
Test status
Simulation time 795807060 ps
CPU time 14.07 seconds
Started May 26 01:59:49 PM PDT 24
Finished May 26 02:00:05 PM PDT 24
Peak memory 210936 kb
Host smart-813eb48f-35ef-4c2e-936a-dc3095de94cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788804811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1788804811
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1390429685
Short name T180
Test name
Test status
Simulation time 2265456563 ps
CPU time 12.73 seconds
Started May 26 01:59:49 PM PDT 24
Finished May 26 02:00:03 PM PDT 24
Peak memory 211116 kb
Host smart-2b73d5ad-3eb1-498a-a5de-6f0b004b562b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390429685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1390429685
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.234048140
Short name T40
Test name
Test status
Simulation time 1477406906 ps
CPU time 19.29 seconds
Started May 26 01:59:49 PM PDT 24
Finished May 26 02:00:10 PM PDT 24
Peak memory 211608 kb
Host smart-7a20fb02-f23f-4039-9ecd-40e7040fd589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234048140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.234048140
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.366471945
Short name T254
Test name
Test status
Simulation time 353159792 ps
CPU time 5.47 seconds
Started May 26 01:59:51 PM PDT 24
Finished May 26 01:59:58 PM PDT 24
Peak memory 210960 kb
Host smart-c1ae5cb4-d4da-4a9f-b29c-8e24aebc30c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366471945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.366471945
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.985746160
Short name T291
Test name
Test status
Simulation time 11278165909 ps
CPU time 31.45 seconds
Started May 26 01:59:46 PM PDT 24
Finished May 26 02:00:18 PM PDT 24
Peak memory 214052 kb
Host smart-35ab537b-2c4e-4eeb-a355-7abb46fcdf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985746160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.985746160
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.75402251
Short name T157
Test name
Test status
Simulation time 1689468717 ps
CPU time 17.77 seconds
Started May 26 01:59:46 PM PDT 24
Finished May 26 02:00:04 PM PDT 24
Peak memory 210912 kb
Host smart-d1321ece-e62d-4d52-9625-4d543cefd677
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75402251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.rom_ctrl_stress_all.75402251
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1836197690
Short name T23
Test name
Test status
Simulation time 116473203878 ps
CPU time 1821 seconds
Started May 26 01:59:47 PM PDT 24
Finished May 26 02:30:10 PM PDT 24
Peak memory 235692 kb
Host smart-515a82dd-8994-4f6b-a2b5-078822902d86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836197690 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1836197690
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.98316567
Short name T321
Test name
Test status
Simulation time 4225846518 ps
CPU time 16.64 seconds
Started May 26 01:59:55 PM PDT 24
Finished May 26 02:00:18 PM PDT 24
Peak memory 211128 kb
Host smart-2dbb5985-1d44-4d2a-b48e-21069e8638a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98316567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.98316567
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.541349100
Short name T363
Test name
Test status
Simulation time 35919427920 ps
CPU time 194.42 seconds
Started May 26 01:59:47 PM PDT 24
Finished May 26 02:03:02 PM PDT 24
Peak memory 228128 kb
Host smart-cf00b4f0-d8fa-4a7f-8f51-f9a09e59736b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541349100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.541349100
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2593879112
Short name T128
Test name
Test status
Simulation time 2103462557 ps
CPU time 23.29 seconds
Started May 26 01:59:48 PM PDT 24
Finished May 26 02:00:13 PM PDT 24
Peak memory 211060 kb
Host smart-bf8a7a52-8245-4f78-b75f-b83d0aa249eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593879112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2593879112
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3481596959
Short name T122
Test name
Test status
Simulation time 378548865 ps
CPU time 5.54 seconds
Started May 26 01:59:51 PM PDT 24
Finished May 26 01:59:58 PM PDT 24
Peak memory 211012 kb
Host smart-30639d91-7f46-4d37-a2f4-cf542116c64d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481596959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3481596959
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.236594558
Short name T175
Test name
Test status
Simulation time 17889786773 ps
CPU time 42.03 seconds
Started May 26 01:59:47 PM PDT 24
Finished May 26 02:00:30 PM PDT 24
Peak memory 219188 kb
Host smart-0b49b04b-61eb-4c7a-8549-56d89c49b66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236594558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.236594558
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.642469678
Short name T3
Test name
Test status
Simulation time 2555798756 ps
CPU time 19.14 seconds
Started May 26 01:59:48 PM PDT 24
Finished May 26 02:00:09 PM PDT 24
Peak memory 213608 kb
Host smart-5561dafd-0995-4244-9b4d-ce10c3df55cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642469678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.642469678
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3844523559
Short name T287
Test name
Test status
Simulation time 439093356 ps
CPU time 4.29 seconds
Started May 26 01:59:16 PM PDT 24
Finished May 26 01:59:21 PM PDT 24
Peak memory 211028 kb
Host smart-5949ee73-9fbd-48b9-bbc4-c50dc36d9755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844523559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3844523559
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3743968540
Short name T41
Test name
Test status
Simulation time 39776366702 ps
CPU time 224.42 seconds
Started May 26 01:59:18 PM PDT 24
Finished May 26 02:03:03 PM PDT 24
Peak memory 233472 kb
Host smart-0cd978be-83f7-4a12-94d7-8873c0f93828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743968540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3743968540
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.7744601
Short name T299
Test name
Test status
Simulation time 5411317852 ps
CPU time 26.3 seconds
Started May 26 01:59:18 PM PDT 24
Finished May 26 01:59:45 PM PDT 24
Peak memory 211952 kb
Host smart-59f25d59-8c58-4717-ab6f-5235d606f844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7744601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.7744601
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4026947201
Short name T135
Test name
Test status
Simulation time 3705399788 ps
CPU time 16.72 seconds
Started May 26 01:59:18 PM PDT 24
Finished May 26 01:59:35 PM PDT 24
Peak memory 211072 kb
Host smart-cafea588-3266-4c61-867d-d30d4c347480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026947201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4026947201
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1536827136
Short name T295
Test name
Test status
Simulation time 389869898 ps
CPU time 10.05 seconds
Started May 26 01:59:16 PM PDT 24
Finished May 26 01:59:27 PM PDT 24
Peak memory 212908 kb
Host smart-9c2df19c-9f1d-4d50-aa2e-2d16cd54866d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536827136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1536827136
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2421943198
Short name T357
Test name
Test status
Simulation time 5561178968 ps
CPU time 33.04 seconds
Started May 26 01:59:18 PM PDT 24
Finished May 26 01:59:52 PM PDT 24
Peak memory 219244 kb
Host smart-3bf7f109-4436-4222-951c-1ec995cd9117
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421943198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2421943198
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1594450603
Short name T266
Test name
Test status
Simulation time 18707580951 ps
CPU time 2219.4 seconds
Started May 26 01:59:20 PM PDT 24
Finished May 26 02:36:19 PM PDT 24
Peak memory 232844 kb
Host smart-142bef0b-fe10-4d42-8342-90d4d3004358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594450603 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1594450603
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.839778076
Short name T228
Test name
Test status
Simulation time 5450973949 ps
CPU time 12.5 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 02:00:15 PM PDT 24
Peak memory 211312 kb
Host smart-7481d5e1-903c-4f94-9d1d-0776657fbb3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839778076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.839778076
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.146865426
Short name T22
Test name
Test status
Simulation time 77542126951 ps
CPU time 392.47 seconds
Started May 26 01:59:55 PM PDT 24
Finished May 26 02:06:33 PM PDT 24
Peak memory 213352 kb
Host smart-307577fb-be90-455a-8ff2-4e7fa94714a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146865426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.146865426
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.389134781
Short name T170
Test name
Test status
Simulation time 13502878419 ps
CPU time 28.95 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 02:00:31 PM PDT 24
Peak memory 212160 kb
Host smart-60ed5ac7-9720-446c-b0b0-19037206d04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389134781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.389134781
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2770185620
Short name T204
Test name
Test status
Simulation time 1684777320 ps
CPU time 15.24 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 02:00:17 PM PDT 24
Peak memory 211008 kb
Host smart-e7c9cf6b-b539-42f1-9259-180680e26a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770185620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2770185620
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2839066647
Short name T193
Test name
Test status
Simulation time 15699125364 ps
CPU time 37.51 seconds
Started May 26 01:59:57 PM PDT 24
Finished May 26 02:00:43 PM PDT 24
Peak memory 214356 kb
Host smart-67a80d44-dd39-4c7c-b1f6-dde6395728a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839066647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2839066647
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2727542593
Short name T272
Test name
Test status
Simulation time 22589257864 ps
CPU time 70.93 seconds
Started May 26 01:59:57 PM PDT 24
Finished May 26 02:01:16 PM PDT 24
Peak memory 219212 kb
Host smart-3d3f866f-8fdd-406d-b6df-4c30d3f2f747
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727542593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2727542593
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3665647522
Short name T352
Test name
Test status
Simulation time 73366290114 ps
CPU time 692.67 seconds
Started May 26 01:59:55 PM PDT 24
Finished May 26 02:11:33 PM PDT 24
Peak memory 235728 kb
Host smart-244921d0-0906-4c7c-b900-d8ab19f5f513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665647522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3665647522
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.413643578
Short name T312
Test name
Test status
Simulation time 7952828042 ps
CPU time 14.34 seconds
Started May 26 01:59:57 PM PDT 24
Finished May 26 02:00:19 PM PDT 24
Peak memory 211100 kb
Host smart-57ad8826-6338-47fa-8dd6-5108a37c9b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413643578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.413643578
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3836641943
Short name T212
Test name
Test status
Simulation time 2027082978 ps
CPU time 133.93 seconds
Started May 26 01:59:59 PM PDT 24
Finished May 26 02:02:23 PM PDT 24
Peak memory 239520 kb
Host smart-cc1ed7a0-b6fc-4101-9541-626cf31319ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836641943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3836641943
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1653946010
Short name T19
Test name
Test status
Simulation time 175243769 ps
CPU time 9.38 seconds
Started May 26 01:59:57 PM PDT 24
Finished May 26 02:00:14 PM PDT 24
Peak memory 211532 kb
Host smart-2a57d30e-999f-421f-906e-c742badcad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653946010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1653946010
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4107804011
Short name T13
Test name
Test status
Simulation time 9481142941 ps
CPU time 13.21 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 02:00:15 PM PDT 24
Peak memory 211060 kb
Host smart-a9c432ca-402f-4e18-805b-7f5934189d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107804011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4107804011
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.352511109
Short name T364
Test name
Test status
Simulation time 58996776777 ps
CPU time 38.65 seconds
Started May 26 01:59:59 PM PDT 24
Finished May 26 02:00:48 PM PDT 24
Peak memory 219244 kb
Host smart-9ddc193d-d600-41d8-9b3a-919ae329bee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352511109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.352511109
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2988912537
Short name T276
Test name
Test status
Simulation time 1030372185 ps
CPU time 10.88 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 02:00:15 PM PDT 24
Peak memory 210944 kb
Host smart-9bf5da05-0888-4ea2-9752-1630dbf24193
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988912537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2988912537
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2820597595
Short name T337
Test name
Test status
Simulation time 45858415850 ps
CPU time 5895.59 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 03:38:18 PM PDT 24
Peak memory 236228 kb
Host smart-fa9d28ec-b57e-44bf-9419-8ebfbe89c9d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820597595 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2820597595
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4203757379
Short name T279
Test name
Test status
Simulation time 4550714540 ps
CPU time 11.11 seconds
Started May 26 01:59:59 PM PDT 24
Finished May 26 02:00:21 PM PDT 24
Peak memory 211104 kb
Host smart-124eb4c8-b5a6-4989-abb2-d3cb7248a65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203757379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4203757379
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.82298255
Short name T322
Test name
Test status
Simulation time 482150756152 ps
CPU time 296.54 seconds
Started May 26 01:59:57 PM PDT 24
Finished May 26 02:05:01 PM PDT 24
Peak memory 236824 kb
Host smart-5977b5a0-3c62-4c93-910a-d05be34339d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82298255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_co
rrupt_sig_fatal_chk.82298255
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2545369952
Short name T20
Test name
Test status
Simulation time 724568852 ps
CPU time 9.55 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 02:00:13 PM PDT 24
Peak memory 212156 kb
Host smart-e6f84a09-b70b-47f0-933b-3500a58874d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545369952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2545369952
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3005968268
Short name T181
Test name
Test status
Simulation time 10063860785 ps
CPU time 12.7 seconds
Started May 26 01:59:54 PM PDT 24
Finished May 26 02:00:12 PM PDT 24
Peak memory 211040 kb
Host smart-f0fa3d50-f13f-44b3-9061-faf7c1802d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3005968268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3005968268
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1942563486
Short name T162
Test name
Test status
Simulation time 746941277 ps
CPU time 10.33 seconds
Started May 26 01:59:55 PM PDT 24
Finished May 26 02:00:10 PM PDT 24
Peak memory 219140 kb
Host smart-cdcca0b0-6b91-4793-83ff-c2bb17546f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942563486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1942563486
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.502423427
Short name T369
Test name
Test status
Simulation time 29008742619 ps
CPU time 60.96 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 02:01:03 PM PDT 24
Peak memory 217836 kb
Host smart-bd687757-20c8-448b-8e18-01b891eb6b34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502423427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.502423427
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3730104026
Short name T207
Test name
Test status
Simulation time 3545486965 ps
CPU time 8.95 seconds
Started May 26 01:59:59 PM PDT 24
Finished May 26 02:00:17 PM PDT 24
Peak memory 211104 kb
Host smart-a3da930b-9e0c-45cb-a4f4-eb007430e529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730104026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3730104026
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2528118915
Short name T182
Test name
Test status
Simulation time 46942598399 ps
CPU time 283.13 seconds
Started May 26 01:59:55 PM PDT 24
Finished May 26 02:04:45 PM PDT 24
Peak memory 237480 kb
Host smart-2ab09852-938c-4dca-bf84-242142919620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528118915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2528118915
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1873789534
Short name T166
Test name
Test status
Simulation time 3452273418 ps
CPU time 27.84 seconds
Started May 26 02:00:00 PM PDT 24
Finished May 26 02:00:38 PM PDT 24
Peak memory 211808 kb
Host smart-2768069f-a945-4068-b12f-00573a9ad522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873789534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1873789534
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.41198233
Short name T189
Test name
Test status
Simulation time 1425893269 ps
CPU time 14.18 seconds
Started May 26 01:59:55 PM PDT 24
Finished May 26 02:00:14 PM PDT 24
Peak memory 210988 kb
Host smart-a1142833-6486-4171-98c2-90a230da146d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41198233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.41198233
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.819765434
Short name T325
Test name
Test status
Simulation time 25988873072 ps
CPU time 24.02 seconds
Started May 26 01:59:55 PM PDT 24
Finished May 26 02:00:25 PM PDT 24
Peak memory 219192 kb
Host smart-2502195f-d938-474b-9ee7-d05f5362e6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819765434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.819765434
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1222668447
Short name T341
Test name
Test status
Simulation time 45856437718 ps
CPU time 70.44 seconds
Started May 26 01:59:57 PM PDT 24
Finished May 26 02:01:15 PM PDT 24
Peak memory 219372 kb
Host smart-d17cef34-e521-419f-98a2-65601a4ea942
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222668447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1222668447
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.937271766
Short name T271
Test name
Test status
Simulation time 130618837 ps
CPU time 5.2 seconds
Started May 26 02:00:05 PM PDT 24
Finished May 26 02:00:25 PM PDT 24
Peak memory 210820 kb
Host smart-f3329389-ddfd-4280-8aca-ef1efb7dc07d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937271766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.937271766
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2802615123
Short name T306
Test name
Test status
Simulation time 65389685842 ps
CPU time 300.34 seconds
Started May 26 01:59:57 PM PDT 24
Finished May 26 02:05:05 PM PDT 24
Peak memory 212396 kb
Host smart-e8d30738-4592-416c-b0c1-6332c0b9d9fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802615123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2802615123
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3276238909
Short name T123
Test name
Test status
Simulation time 8013500765 ps
CPU time 32.38 seconds
Started May 26 01:59:58 PM PDT 24
Finished May 26 02:00:40 PM PDT 24
Peak memory 212156 kb
Host smart-559cb673-23d7-4038-b325-d66ca2392fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276238909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3276238909
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1183359451
Short name T244
Test name
Test status
Simulation time 101156526 ps
CPU time 5.63 seconds
Started May 26 01:59:55 PM PDT 24
Finished May 26 02:00:07 PM PDT 24
Peak memory 211000 kb
Host smart-abbd8fab-6143-46ac-9138-a3aff849e890
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183359451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1183359451
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.351857508
Short name T205
Test name
Test status
Simulation time 3229288433 ps
CPU time 32.46 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 02:00:35 PM PDT 24
Peak memory 219232 kb
Host smart-c6c0f450-23e0-42f4-bbed-a12c403027aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351857508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.351857508
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3997103330
Short name T307
Test name
Test status
Simulation time 2455255860 ps
CPU time 14.32 seconds
Started May 26 01:59:56 PM PDT 24
Finished May 26 02:00:16 PM PDT 24
Peak memory 213160 kb
Host smart-2a73ef42-238b-4117-a492-46c482b43c57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997103330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3997103330
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1382975932
Short name T343
Test name
Test status
Simulation time 133968722293 ps
CPU time 9094.54 seconds
Started May 26 02:00:08 PM PDT 24
Finished May 26 04:32:00 PM PDT 24
Peak memory 235712 kb
Host smart-302a0a66-f112-4c4d-9f6a-127e0318860a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382975932 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1382975932
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3106489501
Short name T63
Test name
Test status
Simulation time 6015037637 ps
CPU time 13.82 seconds
Started May 26 02:00:04 PM PDT 24
Finished May 26 02:00:31 PM PDT 24
Peak memory 211120 kb
Host smart-15f8a943-24e6-4bb7-bfdb-af8c5071730e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106489501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3106489501
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1763064157
Short name T252
Test name
Test status
Simulation time 32337983976 ps
CPU time 349.24 seconds
Started May 26 02:00:03 PM PDT 24
Finished May 26 02:06:06 PM PDT 24
Peak memory 238740 kb
Host smart-eb99c6b7-bc73-4fdf-b63e-0a7c43b52308
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763064157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1763064157
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2766887118
Short name T336
Test name
Test status
Simulation time 168708925 ps
CPU time 9.77 seconds
Started May 26 02:00:04 PM PDT 24
Finished May 26 02:00:27 PM PDT 24
Peak memory 211952 kb
Host smart-985099c6-15b7-466e-9067-03115f5720c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766887118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2766887118
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.850052187
Short name T265
Test name
Test status
Simulation time 7056267953 ps
CPU time 15.45 seconds
Started May 26 02:00:05 PM PDT 24
Finished May 26 02:00:35 PM PDT 24
Peak memory 210964 kb
Host smart-0d4b7e4e-3a9a-4b36-b528-2b525bfe7fd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850052187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.850052187
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3733848116
Short name T366
Test name
Test status
Simulation time 756107725 ps
CPU time 10 seconds
Started May 26 02:00:08 PM PDT 24
Finished May 26 02:00:35 PM PDT 24
Peak memory 213628 kb
Host smart-b8bb34c0-c91a-463e-a8a1-0c24e8f21c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733848116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3733848116
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3913686078
Short name T331
Test name
Test status
Simulation time 310882043 ps
CPU time 15.49 seconds
Started May 26 02:00:05 PM PDT 24
Finished May 26 02:00:34 PM PDT 24
Peak memory 213752 kb
Host smart-4839ee3a-41de-4fd1-bb36-d34049e929f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913686078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3913686078
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2934569201
Short name T371
Test name
Test status
Simulation time 59522558094 ps
CPU time 1144.61 seconds
Started May 26 02:00:05 PM PDT 24
Finished May 26 02:19:24 PM PDT 24
Peak memory 235712 kb
Host smart-fc9cdb36-622c-4203-b9e8-92fb226f1578
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934569201 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2934569201
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1259075494
Short name T310
Test name
Test status
Simulation time 2471211692 ps
CPU time 7.87 seconds
Started May 26 02:00:03 PM PDT 24
Finished May 26 02:00:25 PM PDT 24
Peak memory 211060 kb
Host smart-90e56024-7608-47fa-9a62-0da52adbbe7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259075494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1259075494
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3335768942
Short name T365
Test name
Test status
Simulation time 12867138438 ps
CPU time 260.39 seconds
Started May 26 02:00:04 PM PDT 24
Finished May 26 02:04:38 PM PDT 24
Peak memory 237524 kb
Host smart-14a48f9d-1c55-4f7b-a994-947d7c8ffbc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335768942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3335768942
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2834293574
Short name T38
Test name
Test status
Simulation time 7427434682 ps
CPU time 31.08 seconds
Started May 26 02:00:04 PM PDT 24
Finished May 26 02:00:49 PM PDT 24
Peak memory 212100 kb
Host smart-91a3ed71-ad7d-4bf0-8058-a573ee2be0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834293574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2834293574
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3383097708
Short name T105
Test name
Test status
Simulation time 1575285034 ps
CPU time 14.29 seconds
Started May 26 02:00:08 PM PDT 24
Finished May 26 02:00:38 PM PDT 24
Peak memory 211004 kb
Host smart-048982fc-75bb-4e30-b907-79a4695f00e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383097708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3383097708
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3185275655
Short name T102
Test name
Test status
Simulation time 3767143685 ps
CPU time 20.96 seconds
Started May 26 02:00:09 PM PDT 24
Finished May 26 02:00:46 PM PDT 24
Peak memory 219156 kb
Host smart-7285a247-6467-4ae0-aeb6-5bce9f955204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185275655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3185275655
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.95841694
Short name T280
Test name
Test status
Simulation time 27622304929 ps
CPU time 65.59 seconds
Started May 26 02:00:04 PM PDT 24
Finished May 26 02:01:23 PM PDT 24
Peak memory 216732 kb
Host smart-bf8e8a41-7577-4d44-8539-3a540f73f3ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95841694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.rom_ctrl_stress_all.95841694
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2024275249
Short name T184
Test name
Test status
Simulation time 1584353122 ps
CPU time 10.82 seconds
Started May 26 02:00:06 PM PDT 24
Finished May 26 02:00:33 PM PDT 24
Peak memory 211068 kb
Host smart-4971f686-453b-4ce1-8bc6-3833e8febd43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024275249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2024275249
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3042679454
Short name T35
Test name
Test status
Simulation time 2447021347 ps
CPU time 70.79 seconds
Started May 26 02:00:09 PM PDT 24
Finished May 26 02:01:36 PM PDT 24
Peak memory 228472 kb
Host smart-19b2824d-7331-46bb-a4b8-0b823c9f5357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042679454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3042679454
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3873190130
Short name T345
Test name
Test status
Simulation time 984668862 ps
CPU time 16.14 seconds
Started May 26 02:00:05 PM PDT 24
Finished May 26 02:00:35 PM PDT 24
Peak memory 211728 kb
Host smart-8a94d2ac-3d2c-40d4-8673-586b1235af61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873190130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3873190130
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2601059949
Short name T327
Test name
Test status
Simulation time 2003464360 ps
CPU time 11.3 seconds
Started May 26 02:00:08 PM PDT 24
Finished May 26 02:00:35 PM PDT 24
Peak memory 211004 kb
Host smart-1938b8ba-4d48-44a5-afa5-c0d794b27776
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601059949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2601059949
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2436097879
Short name T374
Test name
Test status
Simulation time 190497215 ps
CPU time 10.03 seconds
Started May 26 02:00:04 PM PDT 24
Finished May 26 02:00:28 PM PDT 24
Peak memory 213148 kb
Host smart-e75b7e07-d22f-4371-8ae0-496b6fea955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436097879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2436097879
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2413150541
Short name T142
Test name
Test status
Simulation time 12915865271 ps
CPU time 34.47 seconds
Started May 26 02:00:04 PM PDT 24
Finished May 26 02:00:52 PM PDT 24
Peak memory 215904 kb
Host smart-e7ac3b1b-8292-4987-a638-e218b5699aa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413150541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2413150541
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3935062564
Short name T195
Test name
Test status
Simulation time 1715737966 ps
CPU time 14.67 seconds
Started May 26 02:00:05 PM PDT 24
Finished May 26 02:00:34 PM PDT 24
Peak memory 210732 kb
Host smart-1800b8ad-c557-40a9-9ec2-59d3c7f550c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935062564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3935062564
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1291141552
Short name T216
Test name
Test status
Simulation time 100926640484 ps
CPU time 235.28 seconds
Started May 26 02:00:03 PM PDT 24
Finished May 26 02:04:12 PM PDT 24
Peak memory 212336 kb
Host smart-b28624be-8498-4e45-a024-5d61d8c51e63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291141552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1291141552
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.489167551
Short name T233
Test name
Test status
Simulation time 6098678656 ps
CPU time 27.55 seconds
Started May 26 02:00:05 PM PDT 24
Finished May 26 02:00:46 PM PDT 24
Peak memory 212284 kb
Host smart-90c30cf8-d82d-4307-822a-219d4fc5fc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489167551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.489167551
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.130554659
Short name T260
Test name
Test status
Simulation time 2588138065 ps
CPU time 12.9 seconds
Started May 26 02:00:05 PM PDT 24
Finished May 26 02:00:32 PM PDT 24
Peak memory 211076 kb
Host smart-42b8643e-5f5b-402f-82e8-98cd8fa053df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130554659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.130554659
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1100967019
Short name T347
Test name
Test status
Simulation time 2363100850 ps
CPU time 14.43 seconds
Started May 26 02:00:03 PM PDT 24
Finished May 26 02:00:31 PM PDT 24
Peak memory 219240 kb
Host smart-2b486a46-4c95-4bb8-9543-8a8016dfc264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100967019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1100967019
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3385969419
Short name T73
Test name
Test status
Simulation time 3990343830 ps
CPU time 44.85 seconds
Started May 26 02:00:05 PM PDT 24
Finished May 26 02:01:04 PM PDT 24
Peak memory 219200 kb
Host smart-8f07f203-f150-4f48-9843-ec20f1918b89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385969419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3385969419
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2057207590
Short name T197
Test name
Test status
Simulation time 3483553799 ps
CPU time 14.83 seconds
Started May 26 02:00:17 PM PDT 24
Finished May 26 02:00:52 PM PDT 24
Peak memory 211096 kb
Host smart-f84eebfd-a016-4036-86e5-8e2da85546b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057207590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2057207590
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1756020343
Short name T348
Test name
Test status
Simulation time 2453050278 ps
CPU time 151.74 seconds
Started May 26 02:00:04 PM PDT 24
Finished May 26 02:02:49 PM PDT 24
Peak memory 235660 kb
Host smart-e496d36e-49d3-4670-a359-a70144e29afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756020343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1756020343
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.200952846
Short name T249
Test name
Test status
Simulation time 753866120 ps
CPU time 9.16 seconds
Started May 26 02:00:07 PM PDT 24
Finished May 26 02:00:32 PM PDT 24
Peak memory 211700 kb
Host smart-dce1e222-61b7-4b33-9d14-9ee890116f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200952846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.200952846
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2291075238
Short name T349
Test name
Test status
Simulation time 7518931314 ps
CPU time 16.04 seconds
Started May 26 02:00:09 PM PDT 24
Finished May 26 02:00:41 PM PDT 24
Peak memory 211008 kb
Host smart-fcc0e9b0-0c58-40c2-baac-bb5a198f5f3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291075238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2291075238
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2889141128
Short name T220
Test name
Test status
Simulation time 4058750597 ps
CPU time 32.54 seconds
Started May 26 02:00:09 PM PDT 24
Finished May 26 02:00:59 PM PDT 24
Peak memory 219232 kb
Host smart-b9338120-8677-4964-8400-180e832910d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889141128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2889141128
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1287333419
Short name T150
Test name
Test status
Simulation time 450631815 ps
CPU time 19.01 seconds
Started May 26 02:00:09 PM PDT 24
Finished May 26 02:00:45 PM PDT 24
Peak memory 219184 kb
Host smart-9a20d9dc-3092-485d-898d-43da9d201c58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287333419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1287333419
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3614720107
Short name T64
Test name
Test status
Simulation time 1517584893 ps
CPU time 7.26 seconds
Started May 26 01:59:25 PM PDT 24
Finished May 26 01:59:33 PM PDT 24
Peak memory 211016 kb
Host smart-9710cccf-c44c-47c1-a09b-ebc76fbe98c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614720107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3614720107
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.339401146
Short name T373
Test name
Test status
Simulation time 15107768126 ps
CPU time 150.97 seconds
Started May 26 01:59:23 PM PDT 24
Finished May 26 02:01:55 PM PDT 24
Peak memory 227680 kb
Host smart-b3e77f7b-f1fb-44fc-8e03-878f3977ea5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339401146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.339401146
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.63135785
Short name T305
Test name
Test status
Simulation time 674050091 ps
CPU time 14.82 seconds
Started May 26 01:59:23 PM PDT 24
Finished May 26 01:59:38 PM PDT 24
Peak memory 211776 kb
Host smart-4d51cfd9-50f1-4b94-bf4b-dd5d79b9d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63135785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.63135785
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.558666693
Short name T140
Test name
Test status
Simulation time 3479522510 ps
CPU time 15.9 seconds
Started May 26 01:59:26 PM PDT 24
Finished May 26 01:59:42 PM PDT 24
Peak memory 211008 kb
Host smart-8a958d3b-23e1-4951-86f0-69b21024ec2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558666693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.558666693
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3176917236
Short name T31
Test name
Test status
Simulation time 275585570 ps
CPU time 52.81 seconds
Started May 26 01:59:27 PM PDT 24
Finished May 26 02:00:20 PM PDT 24
Peak memory 233228 kb
Host smart-c05e2ee6-0bde-4ddb-9f97-10025882863e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176917236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3176917236
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3752520634
Short name T372
Test name
Test status
Simulation time 192232929 ps
CPU time 9.92 seconds
Started May 26 01:59:24 PM PDT 24
Finished May 26 01:59:34 PM PDT 24
Peak memory 212864 kb
Host smart-df34405a-e67a-4c60-b964-75ccbd210fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752520634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3752520634
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2588513496
Short name T344
Test name
Test status
Simulation time 66616413384 ps
CPU time 51.89 seconds
Started May 26 01:59:25 PM PDT 24
Finished May 26 02:00:18 PM PDT 24
Peak memory 213284 kb
Host smart-e1d47ef0-a0d5-489d-bc05-047995626e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588513496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2588513496
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3422530001
Short name T194
Test name
Test status
Simulation time 7691032055 ps
CPU time 11.69 seconds
Started May 26 02:00:17 PM PDT 24
Finished May 26 02:00:49 PM PDT 24
Peak memory 211124 kb
Host smart-01c531b7-c1a5-417d-8d47-dce599e439b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422530001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3422530001
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1964550231
Short name T137
Test name
Test status
Simulation time 51524982294 ps
CPU time 239.61 seconds
Started May 26 02:00:17 PM PDT 24
Finished May 26 02:04:36 PM PDT 24
Peak memory 236112 kb
Host smart-49d16867-b6dd-482e-b08c-871843bf9f02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964550231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1964550231
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1969118459
Short name T211
Test name
Test status
Simulation time 3770161292 ps
CPU time 15.53 seconds
Started May 26 02:00:15 PM PDT 24
Finished May 26 02:00:49 PM PDT 24
Peak memory 211972 kb
Host smart-d7d3be37-742c-433b-b91b-b4fab7108828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969118459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1969118459
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1429273512
Short name T177
Test name
Test status
Simulation time 2200143800 ps
CPU time 18.84 seconds
Started May 26 02:00:17 PM PDT 24
Finished May 26 02:00:56 PM PDT 24
Peak memory 211020 kb
Host smart-095280d2-b9ea-432e-b179-9967f2113793
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429273512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1429273512
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2968055307
Short name T288
Test name
Test status
Simulation time 1372589704 ps
CPU time 15.21 seconds
Started May 26 02:00:18 PM PDT 24
Finished May 26 02:00:54 PM PDT 24
Peak memory 219184 kb
Host smart-7e869989-af8e-4604-b6d1-48719c956600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968055307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2968055307
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2891132156
Short name T375
Test name
Test status
Simulation time 1068108349 ps
CPU time 18.13 seconds
Started May 26 02:00:17 PM PDT 24
Finished May 26 02:00:56 PM PDT 24
Peak memory 213096 kb
Host smart-99ec4860-0f95-4454-a71d-0be33f395880
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891132156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2891132156
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3881497447
Short name T309
Test name
Test status
Simulation time 3464337546 ps
CPU time 144 seconds
Started May 26 02:00:16 PM PDT 24
Finished May 26 02:03:01 PM PDT 24
Peak memory 221200 kb
Host smart-35507561-7c1c-4f28-8798-e5495c88cb5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881497447 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3881497447
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2032015799
Short name T160
Test name
Test status
Simulation time 2002223801 ps
CPU time 16.09 seconds
Started May 26 02:00:15 PM PDT 24
Finished May 26 02:00:50 PM PDT 24
Peak memory 211040 kb
Host smart-5ec0ae06-397c-4de8-8906-273ea353229e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032015799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2032015799
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.697162561
Short name T27
Test name
Test status
Simulation time 6948395501 ps
CPU time 112.06 seconds
Started May 26 02:00:15 PM PDT 24
Finished May 26 02:02:26 PM PDT 24
Peak memory 236460 kb
Host smart-65409ba7-eda4-4276-a652-bec5aea42c01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697162561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.697162561
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3675323293
Short name T24
Test name
Test status
Simulation time 8794702409 ps
CPU time 17.43 seconds
Started May 26 02:00:16 PM PDT 24
Finished May 26 02:00:52 PM PDT 24
Peak memory 212044 kb
Host smart-1b003de5-0fbb-472b-b382-ce7897cb88f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675323293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3675323293
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.602612894
Short name T267
Test name
Test status
Simulation time 1523966013 ps
CPU time 10.06 seconds
Started May 26 02:00:15 PM PDT 24
Finished May 26 02:00:44 PM PDT 24
Peak memory 210944 kb
Host smart-d4bffeb3-a40d-472d-a4fb-7aa75a72179f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=602612894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.602612894
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1640531000
Short name T290
Test name
Test status
Simulation time 7268709534 ps
CPU time 25.7 seconds
Started May 26 02:00:15 PM PDT 24
Finished May 26 02:00:59 PM PDT 24
Peak memory 213760 kb
Host smart-1d8a49ea-0158-430f-9148-a779d7d25ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640531000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1640531000
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2800943233
Short name T42
Test name
Test status
Simulation time 26425156804 ps
CPU time 67.03 seconds
Started May 26 02:00:16 PM PDT 24
Finished May 26 02:01:43 PM PDT 24
Peak memory 219220 kb
Host smart-a500ed93-1d62-4ac6-8a1e-a6f6f1244056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800943233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2800943233
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2798783525
Short name T324
Test name
Test status
Simulation time 46762590094 ps
CPU time 2879.03 seconds
Started May 26 02:00:19 PM PDT 24
Finished May 26 02:48:40 PM PDT 24
Peak memory 235652 kb
Host smart-1103a2ca-03d6-4fae-b15f-3c75aa6316d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798783525 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2798783525
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2892694314
Short name T152
Test name
Test status
Simulation time 717473172 ps
CPU time 8.76 seconds
Started May 26 02:00:17 PM PDT 24
Finished May 26 02:00:45 PM PDT 24
Peak memory 210956 kb
Host smart-377d589c-8041-4790-a8d8-8065c58da65e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892694314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2892694314
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3323410282
Short name T246
Test name
Test status
Simulation time 16795195322 ps
CPU time 228.32 seconds
Started May 26 02:00:16 PM PDT 24
Finished May 26 02:04:24 PM PDT 24
Peak memory 221416 kb
Host smart-6576f095-7842-4b4b-9ac7-260f87fb8b68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323410282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3323410282
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2026170348
Short name T308
Test name
Test status
Simulation time 697450726 ps
CPU time 9.46 seconds
Started May 26 02:00:16 PM PDT 24
Finished May 26 02:00:46 PM PDT 24
Peak memory 211448 kb
Host smart-97675eef-183f-4b7a-958f-63acc19c1002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026170348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2026170348
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3302653158
Short name T163
Test name
Test status
Simulation time 1416676846 ps
CPU time 13.03 seconds
Started May 26 02:00:18 PM PDT 24
Finished May 26 02:00:52 PM PDT 24
Peak memory 210972 kb
Host smart-4a7686a2-31e9-4f72-9044-51b7c18a5aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302653158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3302653158
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4233266955
Short name T103
Test name
Test status
Simulation time 38649975387 ps
CPU time 32.77 seconds
Started May 26 02:00:18 PM PDT 24
Finished May 26 02:01:11 PM PDT 24
Peak memory 219196 kb
Host smart-5251d866-ade9-435b-a9b4-2ed5abe8481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233266955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4233266955
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3806358353
Short name T74
Test name
Test status
Simulation time 12939823552 ps
CPU time 41.09 seconds
Started May 26 02:00:15 PM PDT 24
Finished May 26 02:01:15 PM PDT 24
Peak memory 214052 kb
Host smart-48530f94-fe08-48d0-a9b9-8f404d405692
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806358353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3806358353
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.220068922
Short name T8
Test name
Test status
Simulation time 6260877910 ps
CPU time 13.28 seconds
Started May 26 02:00:28 PM PDT 24
Finished May 26 02:01:03 PM PDT 24
Peak memory 211080 kb
Host smart-e6f496ae-1b3a-4375-9357-3af024d990a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220068922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.220068922
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3533686540
Short name T226
Test name
Test status
Simulation time 62921221454 ps
CPU time 263.56 seconds
Started May 26 02:00:27 PM PDT 24
Finished May 26 02:05:12 PM PDT 24
Peak memory 237436 kb
Host smart-b7532f07-b76b-4bb8-832b-936037d1c3df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533686540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3533686540
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2677575861
Short name T127
Test name
Test status
Simulation time 7931394576 ps
CPU time 22.05 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:01:10 PM PDT 24
Peak memory 211080 kb
Host smart-90638b01-8cdb-4a12-8a54-d5ecb646cb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677575861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2677575861
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1650513391
Short name T229
Test name
Test status
Simulation time 373256874 ps
CPU time 5.57 seconds
Started May 26 02:00:16 PM PDT 24
Finished May 26 02:00:41 PM PDT 24
Peak memory 210968 kb
Host smart-7621af52-3db7-4fe4-bd3c-3f6707c4c411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650513391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1650513391
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.314871008
Short name T256
Test name
Test status
Simulation time 2658629349 ps
CPU time 25.26 seconds
Started May 26 02:00:15 PM PDT 24
Finished May 26 02:01:00 PM PDT 24
Peak memory 213600 kb
Host smart-2b518b8c-60f4-4c03-8c84-6d1367ba5dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314871008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.314871008
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3941729347
Short name T303
Test name
Test status
Simulation time 300170040 ps
CPU time 17.27 seconds
Started May 26 02:00:17 PM PDT 24
Finished May 26 02:00:54 PM PDT 24
Peak memory 219184 kb
Host smart-b50de974-2855-4dac-a0ae-ccd8f87eb521
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941729347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3941729347
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.11705026
Short name T136
Test name
Test status
Simulation time 89243969 ps
CPU time 4.31 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:00:55 PM PDT 24
Peak memory 211040 kb
Host smart-d9e78817-06ed-42a9-8ca2-4ba9e05a340c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11705026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.11705026
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1638691098
Short name T47
Test name
Test status
Simulation time 19880919385 ps
CPU time 278.23 seconds
Started May 26 02:00:27 PM PDT 24
Finished May 26 02:05:27 PM PDT 24
Peak memory 228136 kb
Host smart-2354957f-6f94-4309-a2ef-a9ff9607efc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638691098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1638691098
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4151248253
Short name T227
Test name
Test status
Simulation time 3858447521 ps
CPU time 32.53 seconds
Started May 26 02:00:25 PM PDT 24
Finished May 26 02:01:19 PM PDT 24
Peak memory 211696 kb
Host smart-2319fd6b-57db-4836-ad80-d0d759bfe8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151248253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4151248253
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3658476675
Short name T199
Test name
Test status
Simulation time 8838124296 ps
CPU time 17.98 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:01:05 PM PDT 24
Peak memory 211044 kb
Host smart-07bc8aec-3d61-474f-bdd3-ea39b282bf3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658476675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3658476675
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1458107746
Short name T367
Test name
Test status
Simulation time 8213747009 ps
CPU time 33.92 seconds
Started May 26 02:00:28 PM PDT 24
Finished May 26 02:01:23 PM PDT 24
Peak memory 213696 kb
Host smart-c34397ef-7615-4880-a8a9-0cb6cd97f71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458107746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1458107746
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2662310108
Short name T206
Test name
Test status
Simulation time 19212389138 ps
CPU time 64.13 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:01:52 PM PDT 24
Peak memory 217172 kb
Host smart-84d33c4e-5a97-4aff-a735-6e6f0c71f80e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662310108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2662310108
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.336872496
Short name T49
Test name
Test status
Simulation time 40724979674 ps
CPU time 1657.8 seconds
Started May 26 02:00:25 PM PDT 24
Finished May 26 02:28:25 PM PDT 24
Peak memory 236340 kb
Host smart-0942cb0f-3600-44be-a9eb-b6eecebdda14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336872496 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.336872496
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.258996670
Short name T155
Test name
Test status
Simulation time 1957133852 ps
CPU time 9.86 seconds
Started May 26 02:00:25 PM PDT 24
Finished May 26 02:00:56 PM PDT 24
Peak memory 211004 kb
Host smart-c90194fc-5204-45bc-b5ac-0398498a88a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258996670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.258996670
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3458941612
Short name T43
Test name
Test status
Simulation time 60000369751 ps
CPU time 293.11 seconds
Started May 26 02:00:27 PM PDT 24
Finished May 26 02:05:41 PM PDT 24
Peak memory 240776 kb
Host smart-6d12a077-b0df-4902-92cb-44df4b5461b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458941612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3458941612
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4055454745
Short name T161
Test name
Test status
Simulation time 14088747131 ps
CPU time 31.55 seconds
Started May 26 02:00:27 PM PDT 24
Finished May 26 02:01:20 PM PDT 24
Peak memory 211096 kb
Host smart-b6a37a15-a023-469f-809d-e2c1c8e40fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055454745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4055454745
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3277581169
Short name T154
Test name
Test status
Simulation time 359888192 ps
CPU time 7.72 seconds
Started May 26 02:00:25 PM PDT 24
Finished May 26 02:00:54 PM PDT 24
Peak memory 211020 kb
Host smart-1d170175-b29b-4491-b718-5874af41aeea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277581169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3277581169
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1294295829
Short name T36
Test name
Test status
Simulation time 3420876813 ps
CPU time 35.39 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:01:26 PM PDT 24
Peak memory 212692 kb
Host smart-4ca13820-810f-4574-9ab9-321db41127b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294295829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1294295829
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.165281152
Short name T277
Test name
Test status
Simulation time 549934319 ps
CPU time 32.39 seconds
Started May 26 02:00:25 PM PDT 24
Finished May 26 02:01:19 PM PDT 24
Peak memory 216656 kb
Host smart-d3f8a2cc-1910-4933-8ec5-c3d9c6585c80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165281152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.165281152
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2157300409
Short name T2
Test name
Test status
Simulation time 415117140 ps
CPU time 5.04 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:00:52 PM PDT 24
Peak memory 211036 kb
Host smart-982ccab3-e5eb-4751-aabd-9b23729915d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157300409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2157300409
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.582884716
Short name T141
Test name
Test status
Simulation time 8191926049 ps
CPU time 149.34 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:03:16 PM PDT 24
Peak memory 228488 kb
Host smart-b03a4911-fb61-4981-9bd9-133ad19868cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582884716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.582884716
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1491019487
Short name T201
Test name
Test status
Simulation time 748935424 ps
CPU time 14.73 seconds
Started May 26 02:00:27 PM PDT 24
Finished May 26 02:01:03 PM PDT 24
Peak memory 211060 kb
Host smart-775dedfc-c687-484e-aeff-73fb989be170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491019487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1491019487
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1627201506
Short name T332
Test name
Test status
Simulation time 2584057637 ps
CPU time 10.08 seconds
Started May 26 02:00:25 PM PDT 24
Finished May 26 02:00:56 PM PDT 24
Peak memory 211032 kb
Host smart-d3eb35bd-bfdc-45a9-8419-5ec863e89af0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627201506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1627201506
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2681211015
Short name T351
Test name
Test status
Simulation time 388279413 ps
CPU time 10.11 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:01:00 PM PDT 24
Peak memory 213792 kb
Host smart-1c74dc61-d489-4be7-8144-abcc39af0998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681211015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2681211015
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2717363750
Short name T350
Test name
Test status
Simulation time 4778479004 ps
CPU time 57.79 seconds
Started May 26 02:00:25 PM PDT 24
Finished May 26 02:01:45 PM PDT 24
Peak memory 219204 kb
Host smart-29169dab-9435-489c-9bd5-f69eb99c0749
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717363750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2717363750
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2431310324
Short name T223
Test name
Test status
Simulation time 1634009068 ps
CPU time 7.35 seconds
Started May 26 02:00:25 PM PDT 24
Finished May 26 02:00:54 PM PDT 24
Peak memory 211016 kb
Host smart-26c2201f-46d1-4919-b49b-feee14adc4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431310324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2431310324
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1491715255
Short name T293
Test name
Test status
Simulation time 32240001601 ps
CPU time 377.65 seconds
Started May 26 02:00:25 PM PDT 24
Finished May 26 02:07:05 PM PDT 24
Peak memory 235008 kb
Host smart-7c53cd7f-d73b-4281-9a2d-9269c2e1ec21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491715255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1491715255
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2439951818
Short name T176
Test name
Test status
Simulation time 341596975 ps
CPU time 9.25 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:01:00 PM PDT 24
Peak memory 211972 kb
Host smart-c649c29f-e430-4ef8-819e-2126cb19170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439951818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2439951818
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2980043416
Short name T224
Test name
Test status
Simulation time 3607725134 ps
CPU time 17.57 seconds
Started May 26 02:00:30 PM PDT 24
Finished May 26 02:01:09 PM PDT 24
Peak memory 211072 kb
Host smart-594e9acc-a3cd-4ae2-9586-d9950e631c1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980043416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2980043416
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2727921112
Short name T376
Test name
Test status
Simulation time 14049679431 ps
CPU time 24.4 seconds
Started May 26 02:00:23 PM PDT 24
Finished May 26 02:01:09 PM PDT 24
Peak memory 219228 kb
Host smart-461d5c15-b8df-4e5f-bf72-fe5a59547617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727921112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2727921112
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3743470735
Short name T101
Test name
Test status
Simulation time 3821786230 ps
CPU time 27.46 seconds
Started May 26 02:00:24 PM PDT 24
Finished May 26 02:01:13 PM PDT 24
Peak memory 215568 kb
Host smart-40dadba4-6dce-4980-ab24-cdf06f1bb826
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743470735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3743470735
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.664288632
Short name T289
Test name
Test status
Simulation time 1379421865 ps
CPU time 4.16 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:00:51 PM PDT 24
Peak memory 211008 kb
Host smart-acb67c43-a172-4b40-b63d-4475b1fe0c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664288632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.664288632
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3974019213
Short name T235
Test name
Test status
Simulation time 28647845857 ps
CPU time 146.8 seconds
Started May 26 02:00:27 PM PDT 24
Finished May 26 02:03:15 PM PDT 24
Peak memory 235836 kb
Host smart-e6c9666f-8154-4bb3-9006-cb39f1ace00d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974019213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3974019213
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3143795909
Short name T248
Test name
Test status
Simulation time 505025430 ps
CPU time 13.02 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:01:01 PM PDT 24
Peak memory 213164 kb
Host smart-2463f11a-e5cc-44c9-a731-a62ff9d85539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143795909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3143795909
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3551528224
Short name T185
Test name
Test status
Simulation time 180355946 ps
CPU time 6.84 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:00:55 PM PDT 24
Peak memory 210980 kb
Host smart-a2042095-9b0e-4507-929f-30644e4d2c44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551528224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3551528224
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3619303397
Short name T218
Test name
Test status
Simulation time 8388387297 ps
CPU time 40.83 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:01:31 PM PDT 24
Peak memory 212392 kb
Host smart-ac3540d5-964d-4f13-b2c1-97c845fcbeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619303397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3619303397
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3827024324
Short name T353
Test name
Test status
Simulation time 3997939234 ps
CPU time 16.64 seconds
Started May 26 02:00:24 PM PDT 24
Finished May 26 02:01:02 PM PDT 24
Peak memory 210952 kb
Host smart-22ff28e7-2956-4d5d-91f4-4622df734ec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827024324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3827024324
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.946935747
Short name T131
Test name
Test status
Simulation time 2115900260 ps
CPU time 15.76 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:01:06 PM PDT 24
Peak memory 211044 kb
Host smart-e4903738-9887-4fc5-88e3-01b7947f5bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946935747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.946935747
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.381566779
Short name T45
Test name
Test status
Simulation time 258306946935 ps
CPU time 527.72 seconds
Started May 26 02:00:24 PM PDT 24
Finished May 26 02:09:33 PM PDT 24
Peak memory 236948 kb
Host smart-a3858a39-21d5-4cad-a3fc-66ada39ce810
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381566779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.381566779
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3467360323
Short name T203
Test name
Test status
Simulation time 9194807559 ps
CPU time 23.56 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:01:14 PM PDT 24
Peak memory 212108 kb
Host smart-59c5e486-5c0c-4be4-b031-bee56bdb828c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467360323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3467360323
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4218397719
Short name T232
Test name
Test status
Simulation time 102471457 ps
CPU time 5.66 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:00:56 PM PDT 24
Peak memory 211012 kb
Host smart-4a0cf47f-b059-47fa-a80a-28ea9229c805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4218397719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4218397719
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2622860918
Short name T169
Test name
Test status
Simulation time 3047571260 ps
CPU time 30.93 seconds
Started May 26 02:00:27 PM PDT 24
Finished May 26 02:01:20 PM PDT 24
Peak memory 213032 kb
Host smart-bf1f6d19-cb07-4c14-bc4d-5c79cf1757c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622860918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2622860918
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3491503444
Short name T253
Test name
Test status
Simulation time 2259539578 ps
CPU time 34.92 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:01:26 PM PDT 24
Peak memory 219216 kb
Host smart-d4697cbf-d388-41c4-958f-3924df83ff75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491503444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3491503444
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2799887711
Short name T311
Test name
Test status
Simulation time 38331952945 ps
CPU time 1515.23 seconds
Started May 26 02:00:24 PM PDT 24
Finished May 26 02:26:01 PM PDT 24
Peak memory 232472 kb
Host smart-087bde0c-a324-4c8d-a8f6-12f0128ef19d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799887711 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2799887711
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1787352877
Short name T6
Test name
Test status
Simulation time 5606714885 ps
CPU time 14.72 seconds
Started May 26 01:59:28 PM PDT 24
Finished May 26 01:59:44 PM PDT 24
Peak memory 211060 kb
Host smart-3dd5d251-814c-42f2-9bd8-42768a97f7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787352877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1787352877
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2044237691
Short name T319
Test name
Test status
Simulation time 168940226690 ps
CPU time 282.78 seconds
Started May 26 01:59:25 PM PDT 24
Finished May 26 02:04:09 PM PDT 24
Peak memory 241276 kb
Host smart-bbbcfb22-4512-4dd9-9883-271d0cb801cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044237691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2044237691
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.976289943
Short name T18
Test name
Test status
Simulation time 5526216676 ps
CPU time 30.62 seconds
Started May 26 01:59:24 PM PDT 24
Finished May 26 01:59:55 PM PDT 24
Peak memory 211928 kb
Host smart-0e8717e7-1c1c-4e51-bee3-0cca30f410b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976289943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.976289943
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4258050626
Short name T183
Test name
Test status
Simulation time 4787303042 ps
CPU time 11.5 seconds
Started May 26 01:59:24 PM PDT 24
Finished May 26 01:59:36 PM PDT 24
Peak memory 211020 kb
Host smart-83533de5-86a8-4c7b-b240-0a2889e5a34d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4258050626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4258050626
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1760782894
Short name T33
Test name
Test status
Simulation time 505945986 ps
CPU time 101.8 seconds
Started May 26 01:59:24 PM PDT 24
Finished May 26 02:01:06 PM PDT 24
Peak memory 235580 kb
Host smart-2ef613b4-928b-4395-a5d3-4c1ede1db393
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760782894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1760782894
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.631736518
Short name T39
Test name
Test status
Simulation time 1901948472 ps
CPU time 16.03 seconds
Started May 26 01:59:24 PM PDT 24
Finished May 26 01:59:41 PM PDT 24
Peak memory 212524 kb
Host smart-75f67b97-e44c-49e3-ac4d-7020eccc1a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631736518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.631736518
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3012083474
Short name T202
Test name
Test status
Simulation time 582995496 ps
CPU time 6.62 seconds
Started May 26 01:59:23 PM PDT 24
Finished May 26 01:59:31 PM PDT 24
Peak memory 211016 kb
Host smart-91a71e77-bdf7-4bce-b689-6530e84db4fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012083474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3012083474
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.988276184
Short name T51
Test name
Test status
Simulation time 32482453011 ps
CPU time 4280.53 seconds
Started May 26 01:59:27 PM PDT 24
Finished May 26 03:10:48 PM PDT 24
Peak memory 235716 kb
Host smart-ef126a0e-b90c-4e2f-b64f-771fa2de1b68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988276184 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.988276184
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3518552493
Short name T214
Test name
Test status
Simulation time 6068879840 ps
CPU time 13.35 seconds
Started May 26 02:00:40 PM PDT 24
Finished May 26 02:01:11 PM PDT 24
Peak memory 211184 kb
Host smart-19203148-3b01-4ff8-b314-bdfa6bad4d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518552493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3518552493
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1077428777
Short name T222
Test name
Test status
Simulation time 31661222721 ps
CPU time 151.32 seconds
Started May 26 02:00:32 PM PDT 24
Finished May 26 02:03:24 PM PDT 24
Peak memory 230480 kb
Host smart-33eaefc3-ff94-4a01-a1a3-a5aff7d9cbf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077428777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1077428777
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2935921610
Short name T318
Test name
Test status
Simulation time 822116460 ps
CPU time 15.38 seconds
Started May 26 02:00:32 PM PDT 24
Finished May 26 02:01:08 PM PDT 24
Peak memory 211660 kb
Host smart-56540776-b673-413c-beae-26150ba44027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935921610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2935921610
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2347604143
Short name T358
Test name
Test status
Simulation time 735746631 ps
CPU time 7.96 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:00:55 PM PDT 24
Peak memory 210976 kb
Host smart-e7e1863c-9cad-49ca-9281-d8e98bfce994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347604143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2347604143
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3924960428
Short name T317
Test name
Test status
Simulation time 6125417466 ps
CPU time 26.16 seconds
Started May 26 02:00:29 PM PDT 24
Finished May 26 02:01:17 PM PDT 24
Peak memory 213796 kb
Host smart-9e89e9e6-ba7c-48db-8867-f338c5995a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924960428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3924960428
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1842680936
Short name T190
Test name
Test status
Simulation time 2417894942 ps
CPU time 31.81 seconds
Started May 26 02:00:26 PM PDT 24
Finished May 26 02:01:19 PM PDT 24
Peak memory 215912 kb
Host smart-83030903-3d64-4dfe-9da5-32e4a7b7886b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842680936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1842680936
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.645673524
Short name T334
Test name
Test status
Simulation time 86549522 ps
CPU time 4.34 seconds
Started May 26 02:00:32 PM PDT 24
Finished May 26 02:00:57 PM PDT 24
Peak memory 211068 kb
Host smart-2bb796e4-ff17-4319-bc0a-dd7f56cd6df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645673524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.645673524
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.228489129
Short name T28
Test name
Test status
Simulation time 270504795878 ps
CPU time 437.28 seconds
Started May 26 02:00:36 PM PDT 24
Finished May 26 02:08:13 PM PDT 24
Peak memory 237508 kb
Host smart-7b5ebcb2-eb43-4175-bb4e-8e8e1dd02f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228489129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.228489129
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1689718558
Short name T236
Test name
Test status
Simulation time 11794042907 ps
CPU time 28.3 seconds
Started May 26 02:00:33 PM PDT 24
Finished May 26 02:01:22 PM PDT 24
Peak memory 211920 kb
Host smart-65ef1606-5181-4160-9139-a8bda5c05910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689718558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1689718558
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.359961079
Short name T234
Test name
Test status
Simulation time 204457962 ps
CPU time 5.49 seconds
Started May 26 02:00:34 PM PDT 24
Finished May 26 02:01:00 PM PDT 24
Peak memory 210948 kb
Host smart-91d490fb-4927-4f13-90af-5b9860608215
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359961079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.359961079
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4249272507
Short name T304
Test name
Test status
Simulation time 59130337573 ps
CPU time 29.43 seconds
Started May 26 02:00:34 PM PDT 24
Finished May 26 02:01:24 PM PDT 24
Peak memory 213180 kb
Host smart-5d57067b-d514-494a-b0c0-e3ba571f5572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249272507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4249272507
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2906827960
Short name T284
Test name
Test status
Simulation time 421501276 ps
CPU time 6.2 seconds
Started May 26 02:00:33 PM PDT 24
Finished May 26 02:01:00 PM PDT 24
Peak memory 211008 kb
Host smart-0cad092b-2e10-40a6-8dc0-a9783f010cb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906827960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2906827960
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2332487737
Short name T255
Test name
Test status
Simulation time 3812552920 ps
CPU time 15.81 seconds
Started May 26 02:00:33 PM PDT 24
Finished May 26 02:01:10 PM PDT 24
Peak memory 211284 kb
Host smart-ea45d0a2-ec22-41b3-acc1-b79a7db5c9be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332487737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2332487737
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4255393577
Short name T158
Test name
Test status
Simulation time 4500602958 ps
CPU time 90.87 seconds
Started May 26 02:00:32 PM PDT 24
Finished May 26 02:02:23 PM PDT 24
Peak memory 237484 kb
Host smart-7a1ec357-452a-4c24-a63d-244281f3d19a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255393577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4255393577
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4152363976
Short name T144
Test name
Test status
Simulation time 1229286319 ps
CPU time 18.14 seconds
Started May 26 02:00:37 PM PDT 24
Finished May 26 02:01:14 PM PDT 24
Peak memory 211688 kb
Host smart-3c77489c-fd82-40d6-afc4-5757003ffcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152363976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4152363976
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2425744272
Short name T362
Test name
Test status
Simulation time 1037484151 ps
CPU time 8.83 seconds
Started May 26 02:00:31 PM PDT 24
Finished May 26 02:01:01 PM PDT 24
Peak memory 210968 kb
Host smart-9083a0d6-1016-4294-aea7-5d07a2f4392e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425744272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2425744272
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2698801756
Short name T250
Test name
Test status
Simulation time 824886551 ps
CPU time 10.33 seconds
Started May 26 02:00:31 PM PDT 24
Finished May 26 02:01:02 PM PDT 24
Peak memory 213356 kb
Host smart-03d619a7-bece-48ad-8fdc-7db5e113ad10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698801756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2698801756
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2105995552
Short name T301
Test name
Test status
Simulation time 3206146699 ps
CPU time 18.97 seconds
Started May 26 02:00:35 PM PDT 24
Finished May 26 02:01:14 PM PDT 24
Peak memory 211648 kb
Host smart-fcdb1f68-56dd-4ddc-9135-6323cd7274f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105995552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2105995552
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.32259352
Short name T50
Test name
Test status
Simulation time 10690266972 ps
CPU time 460.29 seconds
Started May 26 02:00:33 PM PDT 24
Finished May 26 02:08:34 PM PDT 24
Peak memory 227880 kb
Host smart-552985bb-3046-48a4-868e-55c56e058f86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259352 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.32259352
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1913946507
Short name T186
Test name
Test status
Simulation time 1378007335 ps
CPU time 4.27 seconds
Started May 26 02:00:40 PM PDT 24
Finished May 26 02:01:02 PM PDT 24
Peak memory 210892 kb
Host smart-7453f6c0-2a2a-4dfd-8232-ca9aafc94302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913946507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1913946507
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4158942234
Short name T286
Test name
Test status
Simulation time 23107226557 ps
CPU time 155.48 seconds
Started May 26 02:00:32 PM PDT 24
Finished May 26 02:03:29 PM PDT 24
Peak memory 237580 kb
Host smart-45936165-19b4-46fc-b652-be76de4e0adf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158942234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4158942234
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3756980598
Short name T34
Test name
Test status
Simulation time 175407969 ps
CPU time 9.63 seconds
Started May 26 02:00:39 PM PDT 24
Finished May 26 02:01:07 PM PDT 24
Peak memory 211604 kb
Host smart-94dd4dbb-d8fd-49c6-9f38-779260c22633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756980598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3756980598
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2764103084
Short name T270
Test name
Test status
Simulation time 7768854683 ps
CPU time 17.3 seconds
Started May 26 02:00:31 PM PDT 24
Finished May 26 02:01:09 PM PDT 24
Peak memory 211068 kb
Host smart-f82fb0e0-def3-4173-8073-c69c9f0d6af1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2764103084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2764103084
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3777364369
Short name T78
Test name
Test status
Simulation time 4614931347 ps
CPU time 20.58 seconds
Started May 26 02:00:32 PM PDT 24
Finished May 26 02:01:13 PM PDT 24
Peak memory 214020 kb
Host smart-f22f8bc3-214b-48c0-bb92-b6ac93c0e588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777364369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3777364369
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3604593810
Short name T76
Test name
Test status
Simulation time 2084036975 ps
CPU time 47.39 seconds
Started May 26 02:00:36 PM PDT 24
Finished May 26 02:01:43 PM PDT 24
Peak memory 217324 kb
Host smart-f825cd9c-ee28-4371-93f0-a52499e40bd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604593810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3604593810
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.985395904
Short name T138
Test name
Test status
Simulation time 765152476 ps
CPU time 8.79 seconds
Started May 26 02:00:32 PM PDT 24
Finished May 26 02:01:02 PM PDT 24
Peak memory 211056 kb
Host smart-9c152c96-7ce3-450f-b874-76132ec0a732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985395904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.985395904
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1514248477
Short name T333
Test name
Test status
Simulation time 74565206643 ps
CPU time 213.38 seconds
Started May 26 02:00:35 PM PDT 24
Finished May 26 02:04:29 PM PDT 24
Peak memory 236448 kb
Host smart-d826615d-0c61-41b1-a881-5157b37411f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514248477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1514248477
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3183465955
Short name T300
Test name
Test status
Simulation time 791694800 ps
CPU time 9.61 seconds
Started May 26 02:00:33 PM PDT 24
Finished May 26 02:01:04 PM PDT 24
Peak memory 211708 kb
Host smart-82d0aa47-8a28-4c12-b29f-f300b40dd3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183465955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3183465955
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1372082549
Short name T159
Test name
Test status
Simulation time 2224188175 ps
CPU time 18.17 seconds
Started May 26 02:00:40 PM PDT 24
Finished May 26 02:01:16 PM PDT 24
Peak memory 210908 kb
Host smart-731bc48c-af6e-40e5-b335-0d20b21cd574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372082549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1372082549
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1739747497
Short name T239
Test name
Test status
Simulation time 188197259 ps
CPU time 10.33 seconds
Started May 26 02:00:31 PM PDT 24
Finished May 26 02:01:02 PM PDT 24
Peak memory 213228 kb
Host smart-bb4bb494-cd7d-4f12-8b89-37406a255972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739747497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1739747497
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.843465063
Short name T237
Test name
Test status
Simulation time 2651201501 ps
CPU time 39.04 seconds
Started May 26 02:00:32 PM PDT 24
Finished May 26 02:01:32 PM PDT 24
Peak memory 213712 kb
Host smart-ad055d92-0347-4cc5-9830-1ccd78e02224
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843465063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.843465063
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3589256146
Short name T283
Test name
Test status
Simulation time 5194978954 ps
CPU time 16.01 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:01:14 PM PDT 24
Peak memory 211124 kb
Host smart-b8e7ad81-250d-4523-ac31-21cc6088189d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589256146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3589256146
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1496432647
Short name T359
Test name
Test status
Simulation time 48349239166 ps
CPU time 422.45 seconds
Started May 26 02:00:35 PM PDT 24
Finished May 26 02:07:58 PM PDT 24
Peak memory 236192 kb
Host smart-0310db0d-7027-44ab-9939-5ea8937998a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496432647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1496432647
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2452498919
Short name T361
Test name
Test status
Simulation time 790423049 ps
CPU time 9.57 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:01:08 PM PDT 24
Peak memory 211712 kb
Host smart-80dcad79-05f7-44fc-b884-7d759b635fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452498919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2452498919
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3962722302
Short name T167
Test name
Test status
Simulation time 1673727592 ps
CPU time 15.72 seconds
Started May 26 02:00:32 PM PDT 24
Finished May 26 02:01:09 PM PDT 24
Peak memory 210984 kb
Host smart-0e02fa6f-d37e-4666-a622-115f9f77e7ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962722302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3962722302
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.424410696
Short name T342
Test name
Test status
Simulation time 3483321374 ps
CPU time 15.8 seconds
Started May 26 02:00:37 PM PDT 24
Finished May 26 02:01:11 PM PDT 24
Peak memory 212932 kb
Host smart-ac523c8b-43d1-4f4c-aa73-80b2fef04b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424410696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.424410696
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1350761857
Short name T274
Test name
Test status
Simulation time 11774877464 ps
CPU time 37.55 seconds
Started May 26 02:00:33 PM PDT 24
Finished May 26 02:01:32 PM PDT 24
Peak memory 216580 kb
Host smart-f47d9ea5-7573-4c32-a422-f275fbe5f69c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350761857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1350761857
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1147242453
Short name T133
Test name
Test status
Simulation time 1960951501 ps
CPU time 16.12 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:01:14 PM PDT 24
Peak memory 211060 kb
Host smart-4dbcd2a1-f19a-4d43-9417-eaa75e28143d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147242453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1147242453
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3105752644
Short name T178
Test name
Test status
Simulation time 34228027766 ps
CPU time 334.17 seconds
Started May 26 02:00:40 PM PDT 24
Finished May 26 02:06:32 PM PDT 24
Peak memory 234572 kb
Host smart-65df10a9-a9c8-4936-9947-5f5d1fe88aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105752644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3105752644
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4289402665
Short name T126
Test name
Test status
Simulation time 7802213226 ps
CPU time 21.91 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:01:20 PM PDT 24
Peak memory 211228 kb
Host smart-cf3c1b7d-33e2-44a9-9093-59223809a045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289402665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4289402665
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.984705032
Short name T192
Test name
Test status
Simulation time 7020200269 ps
CPU time 15.42 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:01:14 PM PDT 24
Peak memory 211064 kb
Host smart-eed1b88a-304b-491a-8de9-01f6d8157154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984705032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.984705032
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.953815684
Short name T231
Test name
Test status
Simulation time 2703917210 ps
CPU time 24.81 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:01:23 PM PDT 24
Peak memory 212816 kb
Host smart-251f5dd5-f2ae-4266-8058-3064504b7ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953815684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.953815684
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2669719368
Short name T179
Test name
Test status
Simulation time 4971070282 ps
CPU time 28.11 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:01:26 PM PDT 24
Peak memory 219208 kb
Host smart-9c398100-8a7d-48f6-9c14-0c4ce3829e23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669719368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2669719368
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4252507422
Short name T53
Test name
Test status
Simulation time 23496594624 ps
CPU time 4339.41 seconds
Started May 26 02:00:40 PM PDT 24
Finished May 26 03:13:18 PM PDT 24
Peak memory 235712 kb
Host smart-eccb639e-642c-498b-8e7f-dafa71c5ce93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252507422 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4252507422
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2558289547
Short name T145
Test name
Test status
Simulation time 8648089667 ps
CPU time 16.73 seconds
Started May 26 02:00:40 PM PDT 24
Finished May 26 02:01:15 PM PDT 24
Peak memory 211084 kb
Host smart-3790da34-462b-42ad-b1da-aefbabaafb27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558289547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2558289547
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4051935319
Short name T243
Test name
Test status
Simulation time 1650122909 ps
CPU time 20.58 seconds
Started May 26 02:00:40 PM PDT 24
Finished May 26 02:01:18 PM PDT 24
Peak memory 211648 kb
Host smart-75053fb4-2e54-4fa2-a759-ea065a722e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051935319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4051935319
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1249317512
Short name T217
Test name
Test status
Simulation time 433119418 ps
CPU time 5.23 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:01:04 PM PDT 24
Peak memory 210936 kb
Host smart-9d55182a-56c2-44fb-88fa-3beca2fd8321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249317512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1249317512
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2535940793
Short name T368
Test name
Test status
Simulation time 953037961 ps
CPU time 17.45 seconds
Started May 26 02:00:39 PM PDT 24
Finished May 26 02:01:15 PM PDT 24
Peak memory 219128 kb
Host smart-23c6f9b5-1860-48c7-8e82-f03b3612092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535940793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2535940793
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3647278898
Short name T338
Test name
Test status
Simulation time 8510222963 ps
CPU time 26.3 seconds
Started May 26 02:00:43 PM PDT 24
Finished May 26 02:01:25 PM PDT 24
Peak memory 214972 kb
Host smart-5c150737-cc4c-4526-8eee-c335cd1a5fd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647278898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3647278898
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4245016195
Short name T151
Test name
Test status
Simulation time 1538685393 ps
CPU time 6.72 seconds
Started May 26 02:00:42 PM PDT 24
Finished May 26 02:01:05 PM PDT 24
Peak memory 211052 kb
Host smart-73468d7d-d049-477c-acb4-11a9e472582d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245016195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4245016195
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.258678336
Short name T335
Test name
Test status
Simulation time 13949367005 ps
CPU time 135.07 seconds
Started May 26 02:00:40 PM PDT 24
Finished May 26 02:03:13 PM PDT 24
Peak memory 211276 kb
Host smart-d423d35f-e77a-485d-b1fa-0bbf56f51e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258678336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.258678336
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1443212082
Short name T356
Test name
Test status
Simulation time 14686739952 ps
CPU time 32.03 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:01:30 PM PDT 24
Peak memory 211896 kb
Host smart-eb7a8932-122d-48f5-998d-a8e1ff38aa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443212082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1443212082
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1709983495
Short name T100
Test name
Test status
Simulation time 98065370 ps
CPU time 5.66 seconds
Started May 26 02:00:40 PM PDT 24
Finished May 26 02:01:04 PM PDT 24
Peak memory 211016 kb
Host smart-616dfdfe-6b47-4184-8aaf-e83273a72088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709983495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1709983495
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.217782890
Short name T269
Test name
Test status
Simulation time 3136438277 ps
CPU time 31.71 seconds
Started May 26 02:00:42 PM PDT 24
Finished May 26 02:01:30 PM PDT 24
Peak memory 211700 kb
Host smart-a5ed87ce-f530-4dab-bea7-617e3bba3837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217782890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.217782890
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4116185767
Short name T258
Test name
Test status
Simulation time 14854725100 ps
CPU time 69.84 seconds
Started May 26 02:00:41 PM PDT 24
Finished May 26 02:02:08 PM PDT 24
Peak memory 216684 kb
Host smart-48a01094-7157-4c99-b469-1ea5be328cd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116185767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4116185767
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.16320176
Short name T360
Test name
Test status
Simulation time 2766112287 ps
CPU time 16.56 seconds
Started May 26 02:00:49 PM PDT 24
Finished May 26 02:01:17 PM PDT 24
Peak memory 211092 kb
Host smart-b83df50e-234b-4e09-afea-b2d1f0897153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16320176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.16320176
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3646286987
Short name T278
Test name
Test status
Simulation time 78550085320 ps
CPU time 300.6 seconds
Started May 26 02:00:48 PM PDT 24
Finished May 26 02:06:01 PM PDT 24
Peak memory 233540 kb
Host smart-e7a46e4e-b825-4e4e-bd52-bd2cb98c4042
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646286987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3646286987
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.750829342
Short name T281
Test name
Test status
Simulation time 8538143301 ps
CPU time 21.88 seconds
Started May 26 02:00:50 PM PDT 24
Finished May 26 02:01:23 PM PDT 24
Peak memory 212164 kb
Host smart-22ccbbc0-ad55-4064-b8dc-39be52275a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750829342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.750829342
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3711799467
Short name T134
Test name
Test status
Simulation time 1353809870 ps
CPU time 8.17 seconds
Started May 26 02:00:49 PM PDT 24
Finished May 26 02:01:09 PM PDT 24
Peak memory 210972 kb
Host smart-a3cfa5df-5fc1-4911-8c82-a00d3665458a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3711799467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3711799467
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1766498644
Short name T314
Test name
Test status
Simulation time 186162237 ps
CPU time 10.24 seconds
Started May 26 02:00:49 PM PDT 24
Finished May 26 02:01:11 PM PDT 24
Peak memory 213028 kb
Host smart-90f96cb1-9db8-4710-b6bf-d09a4ba69bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766498644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1766498644
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2091515069
Short name T208
Test name
Test status
Simulation time 8653561701 ps
CPU time 54.81 seconds
Started May 26 02:00:50 PM PDT 24
Finished May 26 02:01:56 PM PDT 24
Peak memory 219216 kb
Host smart-537f5316-46f7-4bf2-92f0-b2e648f8be7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091515069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2091515069
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3644797732
Short name T52
Test name
Test status
Simulation time 73521137582 ps
CPU time 4395.69 seconds
Started May 26 02:00:49 PM PDT 24
Finished May 26 03:14:17 PM PDT 24
Peak memory 227800 kb
Host smart-99ff3d1e-153e-43f1-b078-248a145a3659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644797732 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3644797732
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.551414750
Short name T370
Test name
Test status
Simulation time 333646409 ps
CPU time 4.22 seconds
Started May 26 01:59:25 PM PDT 24
Finished May 26 01:59:31 PM PDT 24
Peak memory 211068 kb
Host smart-fc104974-b08a-420f-aaee-ce6e30f7fbb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551414750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.551414750
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1395291656
Short name T4
Test name
Test status
Simulation time 7266562232 ps
CPU time 82.76 seconds
Started May 26 01:59:23 PM PDT 24
Finished May 26 02:00:46 PM PDT 24
Peak memory 235884 kb
Host smart-8dd2d70e-4eb8-4235-9dca-9f7f94654b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395291656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1395291656
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.922288997
Short name T187
Test name
Test status
Simulation time 13761166604 ps
CPU time 28.38 seconds
Started May 26 01:59:28 PM PDT 24
Finished May 26 01:59:57 PM PDT 24
Peak memory 211072 kb
Host smart-01f27069-d19a-40b7-ae96-13c138ab23ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922288997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.922288997
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1415012475
Short name T320
Test name
Test status
Simulation time 1654314754 ps
CPU time 14.65 seconds
Started May 26 01:59:25 PM PDT 24
Finished May 26 01:59:40 PM PDT 24
Peak memory 210984 kb
Host smart-d4e3f879-7973-4089-bec6-667d3f80abfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415012475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1415012475
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1622488776
Short name T355
Test name
Test status
Simulation time 3114920940 ps
CPU time 19.98 seconds
Started May 26 01:59:23 PM PDT 24
Finished May 26 01:59:44 PM PDT 24
Peak memory 219228 kb
Host smart-ee605edc-b239-49d7-bf55-1dd7f7d035cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622488776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1622488776
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.631169374
Short name T298
Test name
Test status
Simulation time 7679318784 ps
CPU time 51.51 seconds
Started May 26 01:59:23 PM PDT 24
Finished May 26 02:00:16 PM PDT 24
Peak memory 219220 kb
Host smart-4df3684d-161e-4803-ac4b-4ac2db30ecc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631169374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.631169374
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2919342328
Short name T188
Test name
Test status
Simulation time 1020346332 ps
CPU time 10.74 seconds
Started May 26 01:59:23 PM PDT 24
Finished May 26 01:59:35 PM PDT 24
Peak memory 211068 kb
Host smart-4d9c52fc-ef65-4594-b1b1-739898fa7f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919342328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2919342328
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.319712354
Short name T26
Test name
Test status
Simulation time 6321895728 ps
CPU time 85.47 seconds
Started May 26 01:59:28 PM PDT 24
Finished May 26 02:00:54 PM PDT 24
Peak memory 213296 kb
Host smart-30f71e32-68f9-446a-8c5b-51adbcbeb8a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319712354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.319712354
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.93369924
Short name T339
Test name
Test status
Simulation time 3299678732 ps
CPU time 20.16 seconds
Started May 26 01:59:23 PM PDT 24
Finished May 26 01:59:44 PM PDT 24
Peak memory 211096 kb
Host smart-681c23c5-ab0c-4a69-8179-0c5c66cfa4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93369924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.93369924
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2381215396
Short name T104
Test name
Test status
Simulation time 184582728 ps
CPU time 7.06 seconds
Started May 26 01:59:23 PM PDT 24
Finished May 26 01:59:30 PM PDT 24
Peak memory 211136 kb
Host smart-a7c00436-ba4a-4372-a6e0-25d29472d76a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2381215396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2381215396
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.941613238
Short name T132
Test name
Test status
Simulation time 3297341181 ps
CPU time 20.05 seconds
Started May 26 01:59:24 PM PDT 24
Finished May 26 01:59:45 PM PDT 24
Peak memory 213292 kb
Host smart-47e08c95-ccf0-40b7-b2d5-f97001658a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941613238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.941613238
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4030047336
Short name T165
Test name
Test status
Simulation time 753710719 ps
CPU time 21.51 seconds
Started May 26 01:59:24 PM PDT 24
Finished May 26 01:59:46 PM PDT 24
Peak memory 219144 kb
Host smart-5a563e16-aa28-40cf-bd6d-fc1ca6e3c8d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030047336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4030047336
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2893905751
Short name T62
Test name
Test status
Simulation time 1487889477 ps
CPU time 13.53 seconds
Started May 26 01:59:35 PM PDT 24
Finished May 26 01:59:49 PM PDT 24
Peak memory 210968 kb
Host smart-49e01876-7623-4713-99d4-a145028da181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893905751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2893905751
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2801979239
Short name T14
Test name
Test status
Simulation time 12699341694 ps
CPU time 120.24 seconds
Started May 26 01:59:33 PM PDT 24
Finished May 26 02:01:34 PM PDT 24
Peak memory 237776 kb
Host smart-9dea0913-eca7-45f8-9e4b-ba6ccfe30c75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801979239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2801979239
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.803286679
Short name T25
Test name
Test status
Simulation time 14612243551 ps
CPU time 29.96 seconds
Started May 26 01:59:32 PM PDT 24
Finished May 26 02:00:02 PM PDT 24
Peak memory 211872 kb
Host smart-489cfd12-a871-4e77-b1e6-13f0162047ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803286679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.803286679
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3045439725
Short name T242
Test name
Test status
Simulation time 1434584947 ps
CPU time 13.91 seconds
Started May 26 01:59:33 PM PDT 24
Finished May 26 01:59:47 PM PDT 24
Peak memory 210980 kb
Host smart-427381cc-4452-4a6e-91f0-681c356f4663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045439725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3045439725
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3482447389
Short name T200
Test name
Test status
Simulation time 3905789640 ps
CPU time 33.7 seconds
Started May 26 01:59:22 PM PDT 24
Finished May 26 01:59:57 PM PDT 24
Peak memory 219240 kb
Host smart-aadc2982-6eb4-4cbc-80a3-46adbc3aa431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482447389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3482447389
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1098514501
Short name T125
Test name
Test status
Simulation time 5602712749 ps
CPU time 16.79 seconds
Started May 26 01:59:32 PM PDT 24
Finished May 26 01:59:50 PM PDT 24
Peak memory 210956 kb
Host smart-3a18c670-51a8-4ce0-9b70-4e4ad1d4e74b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098514501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1098514501
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2722539707
Short name T147
Test name
Test status
Simulation time 9270378413 ps
CPU time 11.29 seconds
Started May 26 01:59:31 PM PDT 24
Finished May 26 01:59:43 PM PDT 24
Peak memory 211124 kb
Host smart-f9ab2f9a-18d3-4ef5-9e61-b1c90a750d33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722539707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2722539707
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.688293091
Short name T245
Test name
Test status
Simulation time 192310961264 ps
CPU time 449.02 seconds
Started May 26 01:59:33 PM PDT 24
Finished May 26 02:07:03 PM PDT 24
Peak memory 212252 kb
Host smart-b48200b3-44b7-4f08-bf71-fe92f5231483
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688293091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.688293091
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.666588685
Short name T10
Test name
Test status
Simulation time 3145120107 ps
CPU time 29.12 seconds
Started May 26 01:59:32 PM PDT 24
Finished May 26 02:00:01 PM PDT 24
Peak memory 211736 kb
Host smart-2d59c16b-bbb5-4d77-80c3-4b3985194dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666588685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.666588685
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1329168855
Short name T156
Test name
Test status
Simulation time 3184732564 ps
CPU time 15.34 seconds
Started May 26 01:59:34 PM PDT 24
Finished May 26 01:59:50 PM PDT 24
Peak memory 211048 kb
Host smart-43155d40-b338-4898-870d-024c2ef013de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329168855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1329168855
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1021320808
Short name T75
Test name
Test status
Simulation time 4593098332 ps
CPU time 19.68 seconds
Started May 26 01:59:32 PM PDT 24
Finished May 26 01:59:52 PM PDT 24
Peak memory 213104 kb
Host smart-9fe25618-bb92-4ed4-987c-5ce777cb5fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021320808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1021320808
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1569353090
Short name T172
Test name
Test status
Simulation time 4320544553 ps
CPU time 41.54 seconds
Started May 26 01:59:32 PM PDT 24
Finished May 26 02:00:15 PM PDT 24
Peak memory 219244 kb
Host smart-c8dfb22b-c34d-4f67-8167-f078ffb02110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569353090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1569353090
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.674753985
Short name T302
Test name
Test status
Simulation time 332732279 ps
CPU time 4.36 seconds
Started May 26 01:59:32 PM PDT 24
Finished May 26 01:59:37 PM PDT 24
Peak memory 211072 kb
Host smart-dcf768c9-f951-4a35-9b68-3b35d6f9844d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674753985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.674753985
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1393262971
Short name T46
Test name
Test status
Simulation time 69415307416 ps
CPU time 219 seconds
Started May 26 01:59:32 PM PDT 24
Finished May 26 02:03:12 PM PDT 24
Peak memory 240668 kb
Host smart-6da46ec8-f02b-45d9-aba8-a0396be346a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393262971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1393262971
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3322939060
Short name T346
Test name
Test status
Simulation time 7654036283 ps
CPU time 31.54 seconds
Started May 26 01:59:32 PM PDT 24
Finished May 26 02:00:04 PM PDT 24
Peak memory 212308 kb
Host smart-90958518-3c04-4615-9b94-53685599125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322939060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3322939060
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1288996920
Short name T209
Test name
Test status
Simulation time 1365716109 ps
CPU time 13.29 seconds
Started May 26 01:59:35 PM PDT 24
Finished May 26 01:59:49 PM PDT 24
Peak memory 211008 kb
Host smart-e67e6ed1-8699-4481-9a06-0a4b6977eb1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288996920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1288996920
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.227840618
Short name T12
Test name
Test status
Simulation time 4876447556 ps
CPU time 23.33 seconds
Started May 26 01:59:32 PM PDT 24
Finished May 26 01:59:56 PM PDT 24
Peak memory 219224 kb
Host smart-845b8cf5-5fb1-46ca-9995-611c05445713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227840618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.227840618
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3031144712
Short name T48
Test name
Test status
Simulation time 390954782460 ps
CPU time 4239.74 seconds
Started May 26 01:59:34 PM PDT 24
Finished May 26 03:10:14 PM PDT 24
Peak memory 254428 kb
Host smart-64b926d2-a925-4e72-980b-26f97e455ee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031144712 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3031144712
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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