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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 96.97 93.02 97.88 100.00 98.37 98.04 98.83


Total test records in report: 468
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T297 /workspace/coverage/default/34.rom_ctrl_alert_test.2239535736 May 28 01:08:36 PM PDT 24 May 28 01:08:49 PM PDT 24 981215054 ps
T298 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1948036226 May 28 01:08:38 PM PDT 24 May 28 01:08:49 PM PDT 24 452122959 ps
T299 /workspace/coverage/default/48.rom_ctrl_smoke.3896298404 May 28 01:08:36 PM PDT 24 May 28 01:09:06 PM PDT 24 1849096799 ps
T300 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2139800062 May 28 01:08:49 PM PDT 24 May 28 01:09:00 PM PDT 24 172098841 ps
T301 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.894548496 May 28 01:08:32 PM PDT 24 May 28 01:08:53 PM PDT 24 2094142825 ps
T302 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.681657004 May 28 01:08:14 PM PDT 24 May 28 01:08:48 PM PDT 24 72022283964 ps
T303 /workspace/coverage/default/1.rom_ctrl_smoke.3772928754 May 28 01:08:12 PM PDT 24 May 28 01:08:41 PM PDT 24 1716532885 ps
T304 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3670091613 May 28 01:08:48 PM PDT 24 May 28 01:09:03 PM PDT 24 691185832 ps
T305 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.389583076 May 28 01:08:22 PM PDT 24 May 28 01:09:23 PM PDT 24 1537116293 ps
T306 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1993326351 May 28 01:08:07 PM PDT 24 May 28 01:08:32 PM PDT 24 2377596908 ps
T307 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.31022108 May 28 01:08:19 PM PDT 24 May 28 01:12:13 PM PDT 24 376658144481 ps
T308 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1747728946 May 28 01:08:33 PM PDT 24 May 28 01:08:52 PM PDT 24 32971771297 ps
T309 /workspace/coverage/default/33.rom_ctrl_stress_all.2307947916 May 28 01:08:31 PM PDT 24 May 28 01:09:05 PM PDT 24 6340955787 ps
T310 /workspace/coverage/default/0.rom_ctrl_stress_all.2249059141 May 28 01:08:09 PM PDT 24 May 28 01:08:49 PM PDT 24 3730564394 ps
T311 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1308476704 May 28 01:08:26 PM PDT 24 May 28 01:08:57 PM PDT 24 24106758379 ps
T312 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3826178706 May 28 01:08:33 PM PDT 24 May 28 01:08:58 PM PDT 24 11600505811 ps
T313 /workspace/coverage/default/4.rom_ctrl_alert_test.1929583347 May 28 01:08:23 PM PDT 24 May 28 01:08:32 PM PDT 24 2819306081 ps
T314 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3333786716 May 28 01:08:15 PM PDT 24 May 28 01:08:33 PM PDT 24 11638082261 ps
T315 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2632519373 May 28 01:08:33 PM PDT 24 May 28 01:08:45 PM PDT 24 327597607 ps
T316 /workspace/coverage/default/3.rom_ctrl_smoke.3441751520 May 28 01:08:23 PM PDT 24 May 28 01:08:39 PM PDT 24 2562190102 ps
T317 /workspace/coverage/default/31.rom_ctrl_stress_all.476761163 May 28 01:08:25 PM PDT 24 May 28 01:08:56 PM PDT 24 2175794319 ps
T318 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.733278173 May 28 01:08:19 PM PDT 24 May 28 01:08:56 PM PDT 24 17123104862 ps
T319 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3905560164 May 28 01:08:28 PM PDT 24 May 28 01:08:35 PM PDT 24 100840067 ps
T320 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1552597152 May 28 01:08:21 PM PDT 24 May 28 01:08:37 PM PDT 24 2410195030 ps
T321 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3080208549 May 28 01:08:03 PM PDT 24 May 28 01:08:10 PM PDT 24 222067305 ps
T322 /workspace/coverage/default/37.rom_ctrl_alert_test.3531503329 May 28 01:08:39 PM PDT 24 May 28 01:08:46 PM PDT 24 155780248 ps
T323 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.319888259 May 28 01:08:20 PM PDT 24 May 28 01:11:16 PM PDT 24 54282953828 ps
T324 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2156948285 May 28 01:08:44 PM PDT 24 May 28 01:08:57 PM PDT 24 4516986549 ps
T325 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1407660028 May 28 01:08:45 PM PDT 24 May 28 01:14:41 PM PDT 24 59801319560 ps
T326 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3153656350 May 28 01:08:37 PM PDT 24 May 28 01:08:59 PM PDT 24 3074706320 ps
T327 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4054337772 May 28 01:08:17 PM PDT 24 May 28 01:08:50 PM PDT 24 39955767738 ps
T328 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.734596034 May 28 01:08:26 PM PDT 24 May 28 01:10:51 PM PDT 24 4322835824 ps
T329 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.584744358 May 28 01:08:00 PM PDT 24 May 28 01:08:30 PM PDT 24 6562535340 ps
T330 /workspace/coverage/default/35.rom_ctrl_smoke.211742932 May 28 01:08:38 PM PDT 24 May 28 01:09:10 PM PDT 24 12895906997 ps
T331 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2630456966 May 28 01:08:01 PM PDT 24 May 28 01:08:20 PM PDT 24 8594594104 ps
T332 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4225741391 May 28 01:08:35 PM PDT 24 May 28 01:11:50 PM PDT 24 41673629237 ps
T333 /workspace/coverage/default/19.rom_ctrl_smoke.3085236940 May 28 01:08:07 PM PDT 24 May 28 01:08:43 PM PDT 24 4216059811 ps
T334 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1168675005 May 28 01:08:14 PM PDT 24 May 28 01:08:24 PM PDT 24 1065045129 ps
T335 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2395223544 May 28 01:09:02 PM PDT 24 May 28 01:21:49 PM PDT 24 45745251689 ps
T336 /workspace/coverage/default/30.rom_ctrl_alert_test.3847525050 May 28 01:08:32 PM PDT 24 May 28 01:08:38 PM PDT 24 86584760 ps
T337 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2941134484 May 28 01:08:19 PM PDT 24 May 28 01:08:56 PM PDT 24 5715994185 ps
T338 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4252509815 May 28 01:08:28 PM PDT 24 May 28 01:08:43 PM PDT 24 1116274733 ps
T339 /workspace/coverage/default/7.rom_ctrl_stress_all.127127040 May 28 01:08:20 PM PDT 24 May 28 01:10:08 PM PDT 24 57134025122 ps
T340 /workspace/coverage/default/44.rom_ctrl_alert_test.2606184978 May 28 01:08:41 PM PDT 24 May 28 01:08:55 PM PDT 24 1462888724 ps
T341 /workspace/coverage/default/18.rom_ctrl_smoke.2952324700 May 28 01:08:37 PM PDT 24 May 28 01:09:15 PM PDT 24 16086956920 ps
T342 /workspace/coverage/default/41.rom_ctrl_stress_all.4209809871 May 28 01:08:39 PM PDT 24 May 28 01:09:11 PM PDT 24 6149417265 ps
T343 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2860705653 May 28 01:08:34 PM PDT 24 May 28 01:11:04 PM PDT 24 41129859670 ps
T344 /workspace/coverage/default/19.rom_ctrl_alert_test.789527312 May 28 01:08:20 PM PDT 24 May 28 01:08:35 PM PDT 24 2072964328 ps
T345 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.197025189 May 28 01:08:17 PM PDT 24 May 28 01:08:48 PM PDT 24 39889592509 ps
T346 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3194516903 May 28 01:08:20 PM PDT 24 May 28 01:08:28 PM PDT 24 223716870 ps
T347 /workspace/coverage/default/47.rom_ctrl_smoke.2998126574 May 28 01:08:45 PM PDT 24 May 28 01:09:23 PM PDT 24 15178571834 ps
T348 /workspace/coverage/default/46.rom_ctrl_stress_all.2897919052 May 28 01:08:48 PM PDT 24 May 28 01:09:02 PM PDT 24 2513014154 ps
T349 /workspace/coverage/default/15.rom_ctrl_stress_all.71108426 May 28 01:08:06 PM PDT 24 May 28 01:08:19 PM PDT 24 958123218 ps
T350 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2563584639 May 28 01:07:51 PM PDT 24 May 28 01:15:38 PM PDT 24 49507274862 ps
T351 /workspace/coverage/default/9.rom_ctrl_alert_test.1623178642 May 28 01:08:06 PM PDT 24 May 28 01:08:11 PM PDT 24 111406556 ps
T352 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2585947057 May 28 01:08:33 PM PDT 24 May 28 02:14:21 PM PDT 24 49253104151 ps
T353 /workspace/coverage/default/38.rom_ctrl_smoke.1211521865 May 28 01:08:31 PM PDT 24 May 28 01:08:54 PM PDT 24 1740737794 ps
T354 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2922812418 May 28 01:08:47 PM PDT 24 May 28 01:09:46 PM PDT 24 1585623692 ps
T355 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3933113578 May 28 01:08:06 PM PDT 24 May 28 01:08:22 PM PDT 24 257868930 ps
T356 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2375938151 May 28 01:08:15 PM PDT 24 May 28 01:08:23 PM PDT 24 392661981 ps
T357 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3180871435 May 28 01:08:04 PM PDT 24 May 28 01:08:15 PM PDT 24 747792858 ps
T358 /workspace/coverage/default/45.rom_ctrl_smoke.3178582126 May 28 01:08:48 PM PDT 24 May 28 01:08:59 PM PDT 24 1345305864 ps
T35 /workspace/coverage/default/3.rom_ctrl_sec_cm.3611641014 May 28 01:08:19 PM PDT 24 May 28 01:09:13 PM PDT 24 543151756 ps
T359 /workspace/coverage/default/9.rom_ctrl_stress_all.1216585006 May 28 01:08:18 PM PDT 24 May 28 01:09:35 PM PDT 24 25511069463 ps
T360 /workspace/coverage/default/17.rom_ctrl_alert_test.2304274088 May 28 01:08:18 PM PDT 24 May 28 01:08:24 PM PDT 24 88165012 ps
T361 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1095618597 May 28 01:08:05 PM PDT 24 May 28 01:11:11 PM PDT 24 8349661473 ps
T362 /workspace/coverage/default/46.rom_ctrl_smoke.1734965878 May 28 01:08:52 PM PDT 24 May 28 01:09:16 PM PDT 24 1812292077 ps
T363 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.673408169 May 28 01:08:10 PM PDT 24 May 28 01:08:46 PM PDT 24 50163032192 ps
T364 /workspace/coverage/default/21.rom_ctrl_stress_all.2215009086 May 28 01:08:18 PM PDT 24 May 28 01:09:29 PM PDT 24 26262464271 ps
T365 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3908268257 May 28 01:08:32 PM PDT 24 May 28 01:13:07 PM PDT 24 42246084883 ps
T366 /workspace/coverage/default/14.rom_ctrl_alert_test.2823245722 May 28 01:08:21 PM PDT 24 May 28 01:08:35 PM PDT 24 1139489557 ps
T367 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2067851238 May 28 01:08:31 PM PDT 24 May 28 01:13:48 PM PDT 24 58313397969 ps
T368 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.906438028 May 28 01:08:09 PM PDT 24 May 28 01:08:27 PM PDT 24 12668356625 ps
T61 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1443787985 May 28 01:11:30 PM PDT 24 May 28 01:11:51 PM PDT 24 5425633780 ps
T369 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2474305512 May 28 01:11:31 PM PDT 24 May 28 01:11:55 PM PDT 24 1240174702 ps
T370 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2186930637 May 28 01:11:40 PM PDT 24 May 28 01:12:00 PM PDT 24 1894018226 ps
T62 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1366189593 May 28 01:11:30 PM PDT 24 May 28 01:11:46 PM PDT 24 386892578 ps
T63 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.625682802 May 28 01:11:46 PM PDT 24 May 28 01:11:59 PM PDT 24 461580806 ps
T71 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4195022009 May 28 01:11:41 PM PDT 24 May 28 01:12:42 PM PDT 24 26035446588 ps
T58 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2099977012 May 28 01:11:33 PM PDT 24 May 28 01:12:56 PM PDT 24 2945669432 ps
T99 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2318656406 May 28 01:11:43 PM PDT 24 May 28 01:12:04 PM PDT 24 2019047693 ps
T72 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3230529577 May 28 01:11:43 PM PDT 24 May 28 01:12:07 PM PDT 24 379231699 ps
T371 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1236683989 May 28 01:11:29 PM PDT 24 May 28 01:11:50 PM PDT 24 4386657391 ps
T372 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3877502089 May 28 01:11:39 PM PDT 24 May 28 01:11:59 PM PDT 24 2025859603 ps
T59 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2206117771 May 28 01:11:30 PM PDT 24 May 28 01:12:55 PM PDT 24 1784938128 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2536968334 May 28 01:11:54 PM PDT 24 May 28 01:12:51 PM PDT 24 6975495573 ps
T100 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3117548711 May 28 01:11:38 PM PDT 24 May 28 01:11:52 PM PDT 24 1149849663 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2643502449 May 28 01:11:31 PM PDT 24 May 28 01:11:54 PM PDT 24 6594137735 ps
T106 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2718219205 May 28 01:11:29 PM PDT 24 May 28 01:11:53 PM PDT 24 7014079327 ps
T107 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2342459557 May 28 01:11:45 PM PDT 24 May 28 01:12:10 PM PDT 24 639901006 ps
T73 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2952665358 May 28 01:11:31 PM PDT 24 May 28 01:11:52 PM PDT 24 5100487685 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2669978152 May 28 01:11:26 PM PDT 24 May 28 01:11:41 PM PDT 24 920645058 ps
T74 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2592670829 May 28 01:11:42 PM PDT 24 May 28 01:12:01 PM PDT 24 1714334960 ps
T75 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.631408962 May 28 01:11:46 PM PDT 24 May 28 01:12:18 PM PDT 24 6535893629 ps
T76 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2675325265 May 28 01:11:26 PM PDT 24 May 28 01:13:00 PM PDT 24 20630886437 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3563743160 May 28 01:11:32 PM PDT 24 May 28 01:11:51 PM PDT 24 902995201 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3761658403 May 28 01:11:29 PM PDT 24 May 28 01:11:51 PM PDT 24 1135505229 ps
T77 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.554859746 May 28 01:11:33 PM PDT 24 May 28 01:12:47 PM PDT 24 16122415916 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4039504700 May 28 01:11:31 PM PDT 24 May 28 01:11:56 PM PDT 24 3999177626 ps
T60 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2233628314 May 28 01:11:31 PM PDT 24 May 28 01:12:53 PM PDT 24 4459405850 ps
T78 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1640523157 May 28 01:11:43 PM PDT 24 May 28 01:12:35 PM PDT 24 11553115055 ps
T378 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1310730004 May 28 01:11:53 PM PDT 24 May 28 01:12:06 PM PDT 24 293174427 ps
T101 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1772295038 May 28 01:11:43 PM PDT 24 May 28 01:11:55 PM PDT 24 1658895980 ps
T379 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1880241913 May 28 01:11:30 PM PDT 24 May 28 01:11:47 PM PDT 24 489063888 ps
T380 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1100673412 May 28 01:11:54 PM PDT 24 May 28 01:12:06 PM PDT 24 332980738 ps
T102 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.919529837 May 28 01:11:29 PM PDT 24 May 28 01:11:56 PM PDT 24 4020609661 ps
T381 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2711363192 May 28 01:11:42 PM PDT 24 May 28 01:12:00 PM PDT 24 5668655322 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1012649141 May 28 01:11:31 PM PDT 24 May 28 01:11:54 PM PDT 24 2207724483 ps
T79 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2617833042 May 28 01:11:46 PM PDT 24 May 28 01:12:05 PM PDT 24 15137747339 ps
T119 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.805509711 May 28 01:11:38 PM PDT 24 May 28 01:12:22 PM PDT 24 3208387931 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.382570201 May 28 01:11:52 PM PDT 24 May 28 01:12:12 PM PDT 24 5606233145 ps
T108 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.750432141 May 28 01:11:27 PM PDT 24 May 28 01:12:22 PM PDT 24 8070319412 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.236897607 May 28 01:11:26 PM PDT 24 May 28 01:11:42 PM PDT 24 298982791 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.375880445 May 28 01:11:29 PM PDT 24 May 28 01:11:57 PM PDT 24 1620275629 ps
T385 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3658781166 May 28 01:11:41 PM PDT 24 May 28 01:11:58 PM PDT 24 4808158108 ps
T120 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4086698605 May 28 01:11:39 PM PDT 24 May 28 01:12:27 PM PDT 24 4347701508 ps
T386 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1099574399 May 28 01:11:28 PM PDT 24 May 28 01:11:42 PM PDT 24 89086843 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3649122929 May 28 01:11:39 PM PDT 24 May 28 01:12:03 PM PDT 24 4863409192 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.961341372 May 28 01:11:24 PM PDT 24 May 28 01:12:34 PM PDT 24 6216182496 ps
T80 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4071133705 May 28 01:11:40 PM PDT 24 May 28 01:11:53 PM PDT 24 5115104263 ps
T389 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2545255960 May 28 01:11:41 PM PDT 24 May 28 01:11:56 PM PDT 24 1364500823 ps
T81 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1021085648 May 28 01:11:54 PM PDT 24 May 28 01:13:27 PM PDT 24 20066993323 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.140804451 May 28 01:11:29 PM PDT 24 May 28 01:11:50 PM PDT 24 321935262 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1656735359 May 28 01:11:31 PM PDT 24 May 28 01:11:59 PM PDT 24 2193338575 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.69305578 May 28 01:11:41 PM PDT 24 May 28 01:11:58 PM PDT 24 8996689733 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1663967546 May 28 01:11:24 PM PDT 24 May 28 01:12:47 PM PDT 24 6976115587 ps
T393 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2937229132 May 28 01:11:24 PM PDT 24 May 28 01:11:44 PM PDT 24 9826603272 ps
T394 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.683042377 May 28 01:11:57 PM PDT 24 May 28 01:12:18 PM PDT 24 1892064072 ps
T395 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3488695933 May 28 01:11:44 PM PDT 24 May 28 01:12:05 PM PDT 24 5089264855 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.193271478 May 28 01:11:25 PM PDT 24 May 28 01:11:42 PM PDT 24 5061817377 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.158729498 May 28 01:11:28 PM PDT 24 May 28 01:12:20 PM PDT 24 7267065766 ps
T111 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4198905285 May 28 01:11:53 PM PDT 24 May 28 01:13:11 PM PDT 24 734403995 ps
T397 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3032206439 May 28 01:11:41 PM PDT 24 May 28 01:11:51 PM PDT 24 499009813 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2326180870 May 28 01:11:31 PM PDT 24 May 28 01:12:23 PM PDT 24 1291199679 ps
T399 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2680887503 May 28 01:11:41 PM PDT 24 May 28 01:12:00 PM PDT 24 2100226272 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1871836911 May 28 01:11:29 PM PDT 24 May 28 01:11:54 PM PDT 24 3365971847 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1018780691 May 28 01:11:30 PM PDT 24 May 28 01:11:55 PM PDT 24 2053723236 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4216055043 May 28 01:11:33 PM PDT 24 May 28 01:13:18 PM PDT 24 11393953910 ps
T83 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2603328424 May 28 01:11:32 PM PDT 24 May 28 01:12:33 PM PDT 24 5714610376 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2311945540 May 28 01:11:29 PM PDT 24 May 28 01:11:50 PM PDT 24 7233180156 ps
T404 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2750077329 May 28 01:11:42 PM PDT 24 May 28 01:12:07 PM PDT 24 7803943092 ps
T405 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.200474206 May 28 01:11:32 PM PDT 24 May 28 01:11:59 PM PDT 24 7162627133 ps
T406 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2389360261 May 28 01:11:30 PM PDT 24 May 28 01:11:46 PM PDT 24 429487688 ps
T407 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1495295882 May 28 01:12:00 PM PDT 24 May 28 01:12:23 PM PDT 24 7785981169 ps
T408 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3205077197 May 28 01:11:48 PM PDT 24 May 28 01:12:02 PM PDT 24 388130935 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4150685917 May 28 01:11:29 PM PDT 24 May 28 01:11:50 PM PDT 24 11938885509 ps
T410 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3170897525 May 28 01:11:42 PM PDT 24 May 28 01:11:56 PM PDT 24 719013016 ps
T114 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4042916999 May 28 01:11:49 PM PDT 24 May 28 01:13:08 PM PDT 24 8581542735 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2383926319 May 28 01:11:26 PM PDT 24 May 28 01:11:49 PM PDT 24 2356150381 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1156169936 May 28 01:11:26 PM PDT 24 May 28 01:11:54 PM PDT 24 4513015258 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2294909113 May 28 01:11:23 PM PDT 24 May 28 01:11:32 PM PDT 24 164585850 ps
T414 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1411550155 May 28 01:11:30 PM PDT 24 May 28 01:12:14 PM PDT 24 1040685715 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1607917357 May 28 01:11:26 PM PDT 24 May 28 01:11:46 PM PDT 24 19070118554 ps
T416 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2911123658 May 28 01:11:48 PM PDT 24 May 28 01:12:09 PM PDT 24 30929232716 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3257738831 May 28 01:11:25 PM PDT 24 May 28 01:11:37 PM PDT 24 688313524 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2342917801 May 28 01:11:26 PM PDT 24 May 28 01:12:17 PM PDT 24 1083107287 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.376843181 May 28 01:11:28 PM PDT 24 May 28 01:11:42 PM PDT 24 88208402 ps
T418 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1637933617 May 28 01:11:29 PM PDT 24 May 28 01:11:46 PM PDT 24 1035435283 ps
T419 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3230994989 May 28 01:11:27 PM PDT 24 May 28 01:11:49 PM PDT 24 1630724655 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1197538785 May 28 01:11:29 PM PDT 24 May 28 01:11:54 PM PDT 24 3174096541 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3245705124 May 28 01:11:33 PM PDT 24 May 28 01:11:47 PM PDT 24 820263185 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4172960817 May 28 01:11:43 PM PDT 24 May 28 01:11:53 PM PDT 24 111891093 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.204120543 May 28 01:11:31 PM PDT 24 May 28 01:13:03 PM PDT 24 19562950212 ps
T424 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3052391573 May 28 01:11:31 PM PDT 24 May 28 01:11:54 PM PDT 24 1507294615 ps
T425 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1272882530 May 28 01:11:31 PM PDT 24 May 28 01:11:53 PM PDT 24 6319402680 ps
T426 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1799004910 May 28 01:11:41 PM PDT 24 May 28 01:12:05 PM PDT 24 376068985 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2789779752 May 28 01:11:24 PM PDT 24 May 28 01:11:35 PM PDT 24 287743470 ps
T109 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.688937761 May 28 01:11:33 PM PDT 24 May 28 01:13:12 PM PDT 24 44235482448 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.48696646 May 28 01:11:29 PM PDT 24 May 28 01:11:50 PM PDT 24 719120973 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2404637229 May 28 01:11:45 PM PDT 24 May 28 01:12:06 PM PDT 24 6351215368 ps
T118 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1815310482 May 28 01:11:40 PM PDT 24 May 28 01:12:24 PM PDT 24 267745862 ps
T430 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2132119021 May 28 01:11:29 PM PDT 24 May 28 01:11:53 PM PDT 24 1604976863 ps
T431 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3553748721 May 28 01:11:31 PM PDT 24 May 28 01:11:49 PM PDT 24 178013099 ps
T117 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3584776870 May 28 01:11:41 PM PDT 24 May 28 01:12:59 PM PDT 24 4135774844 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3339154891 May 28 01:11:30 PM PDT 24 May 28 01:11:46 PM PDT 24 296203503 ps
T433 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3461847349 May 28 01:11:33 PM PDT 24 May 28 01:11:50 PM PDT 24 1830865442 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1267109512 May 28 01:11:29 PM PDT 24 May 28 01:11:54 PM PDT 24 1884894638 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3208177814 May 28 01:11:31 PM PDT 24 May 28 01:11:52 PM PDT 24 4890649541 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3951868631 May 28 01:11:43 PM PDT 24 May 28 01:13:05 PM PDT 24 6954402285 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3632918254 May 28 01:11:29 PM PDT 24 May 28 01:11:51 PM PDT 24 1357428751 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1697655042 May 28 01:11:40 PM PDT 24 May 28 01:11:56 PM PDT 24 3950882056 ps
T437 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1254160494 May 28 01:11:45 PM PDT 24 May 28 01:12:00 PM PDT 24 904167799 ps
T438 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2233252894 May 28 01:11:41 PM PDT 24 May 28 01:12:00 PM PDT 24 3101345011 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3299209832 May 28 01:11:29 PM PDT 24 May 28 01:12:55 PM PDT 24 8843740333 ps
T440 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2965164481 May 28 01:11:31 PM PDT 24 May 28 01:11:55 PM PDT 24 1913298260 ps
T441 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3139446340 May 28 01:11:30 PM PDT 24 May 28 01:11:49 PM PDT 24 1578076751 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1929741568 May 28 01:11:33 PM PDT 24 May 28 01:11:46 PM PDT 24 347903543 ps
T86 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1229380356 May 28 01:11:26 PM PDT 24 May 28 01:13:04 PM PDT 24 54228266635 ps
T443 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1706947342 May 28 01:11:33 PM PDT 24 May 28 01:11:51 PM PDT 24 890574294 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3962580374 May 28 01:11:26 PM PDT 24 May 28 01:11:39 PM PDT 24 178634205 ps
T445 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.425389866 May 28 01:11:45 PM PDT 24 May 28 01:12:36 PM PDT 24 1646483311 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2891368204 May 28 01:11:29 PM PDT 24 May 28 01:11:50 PM PDT 24 1813460532 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3999287463 May 28 01:11:31 PM PDT 24 May 28 01:11:48 PM PDT 24 595045455 ps
T448 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1240629377 May 28 01:11:40 PM PDT 24 May 28 01:12:24 PM PDT 24 261515595 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4092772067 May 28 01:11:26 PM PDT 24 May 28 01:11:41 PM PDT 24 1139699987 ps
T82 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.159867592 May 28 01:11:28 PM PDT 24 May 28 01:11:56 PM PDT 24 2192523026 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2088647404 May 28 01:11:31 PM PDT 24 May 28 01:11:51 PM PDT 24 1088352874 ps
T450 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1072970472 May 28 01:11:54 PM PDT 24 May 28 01:12:54 PM PDT 24 20422263097 ps
T451 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3945016335 May 28 01:11:50 PM PDT 24 May 28 01:12:03 PM PDT 24 92724890 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1970362271 May 28 01:11:27 PM PDT 24 May 28 01:11:52 PM PDT 24 2008065395 ps
T453 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1549150846 May 28 01:11:49 PM PDT 24 May 28 01:12:01 PM PDT 24 96975921 ps
T454 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2629866267 May 28 01:11:47 PM PDT 24 May 28 01:11:58 PM PDT 24 249326179 ps
T88 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3806818428 May 28 01:11:30 PM PDT 24 May 28 01:11:53 PM PDT 24 1711520732 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2357135067 May 28 01:11:41 PM PDT 24 May 28 01:11:59 PM PDT 24 1389015724 ps
T456 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1824925310 May 28 01:11:27 PM PDT 24 May 28 01:11:52 PM PDT 24 3752582421 ps
T457 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3451460665 May 28 01:11:23 PM PDT 24 May 28 01:12:38 PM PDT 24 213963875 ps
T458 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3569364049 May 28 01:11:33 PM PDT 24 May 28 01:12:28 PM PDT 24 1800975884 ps
T459 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.996113880 May 28 01:11:49 PM PDT 24 May 28 01:12:08 PM PDT 24 1188765696 ps
T460 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.396860848 May 28 01:11:28 PM PDT 24 May 28 01:11:52 PM PDT 24 1809716437 ps
T116 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.757855520 May 28 01:11:52 PM PDT 24 May 28 01:13:16 PM PDT 24 1712654118 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1051864722 May 28 01:11:25 PM PDT 24 May 28 01:11:46 PM PDT 24 2988215372 ps
T462 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1107716659 May 28 01:11:50 PM PDT 24 May 28 01:12:07 PM PDT 24 474257174 ps
T463 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3115691039 May 28 01:11:33 PM PDT 24 May 28 01:11:56 PM PDT 24 7368214750 ps
T464 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3901435105 May 28 01:11:43 PM PDT 24 May 28 01:12:02 PM PDT 24 2352260064 ps
T465 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2448013022 May 28 01:11:29 PM PDT 24 May 28 01:11:52 PM PDT 24 6312010517 ps
T466 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.547834993 May 28 01:11:41 PM PDT 24 May 28 01:11:53 PM PDT 24 296115747 ps
T467 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3727662017 May 28 01:11:31 PM PDT 24 May 28 01:11:55 PM PDT 24 1876362498 ps
T468 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.135181501 May 28 01:11:29 PM PDT 24 May 28 01:12:20 PM PDT 24 2556527953 ps

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3607462733
Short name T9
Test name
Test status
Simulation time 19918809593 ps
CPU time 727.48 seconds
Started May 28 01:08:44 PM PDT 24
Finished May 28 01:20:53 PM PDT 24
Peak memory 227732 kb
Host smart-2710866c-167e-4033-9f10-86c2c565a3d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607462733 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3607462733
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1450582759
Short name T25
Test name
Test status
Simulation time 22397159032 ps
CPU time 213.71 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:12:03 PM PDT 24
Peak memory 237424 kb
Host smart-c1baaef6-4fb2-442a-a4b8-cb0f0e33769c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450582759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1450582759
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3975116386
Short name T11
Test name
Test status
Simulation time 17271037613 ps
CPU time 34.49 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:09:05 PM PDT 24
Peak memory 219052 kb
Host smart-541ea9f6-7b7c-4cd5-b215-acbaa87ef2c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975116386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3975116386
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.145875582
Short name T34
Test name
Test status
Simulation time 21779347295 ps
CPU time 65.4 seconds
Started May 28 01:08:22 PM PDT 24
Finished May 28 01:09:30 PM PDT 24
Peak memory 236488 kb
Host smart-e97816d2-f511-421b-b2f7-dcb8126f88d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145875582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.145875582
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4042916999
Short name T114
Test name
Test status
Simulation time 8581542735 ps
CPU time 73.12 seconds
Started May 28 01:11:49 PM PDT 24
Finished May 28 01:13:08 PM PDT 24
Peak memory 212480 kb
Host smart-542d1776-5921-46a0-be20-7b5d9287ec84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042916999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4042916999
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1325469518
Short name T1
Test name
Test status
Simulation time 7213399927 ps
CPU time 88.25 seconds
Started May 28 01:08:21 PM PDT 24
Finished May 28 01:09:52 PM PDT 24
Peak memory 219108 kb
Host smart-cd62ee02-77de-4d95-a2f4-83b0226f9c5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325469518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1325469518
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2675325265
Short name T76
Test name
Test status
Simulation time 20630886437 ps
CPU time 84.89 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:13:00 PM PDT 24
Peak memory 211352 kb
Host smart-0dec1a09-a69f-486f-b1ed-a8ab5ad8163d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675325265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2675325265
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3584776870
Short name T117
Test name
Test status
Simulation time 4135774844 ps
CPU time 71.91 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:12:59 PM PDT 24
Peak memory 211940 kb
Host smart-5b2e50fd-7723-4779-9f5b-c7a141778dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584776870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3584776870
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3024852489
Short name T14
Test name
Test status
Simulation time 40323421644 ps
CPU time 360.26 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:14:22 PM PDT 24
Peak memory 233884 kb
Host smart-6ad11124-b372-4a2c-8294-d96842c6e3ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024852489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3024852489
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3427825398
Short name T18
Test name
Test status
Simulation time 22789397548 ps
CPU time 3146.04 seconds
Started May 28 01:08:17 PM PDT 24
Finished May 28 02:00:45 PM PDT 24
Peak memory 226980 kb
Host smart-e025642b-f26f-44f4-8725-ad9aa43a6e6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427825398 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3427825398
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3480392201
Short name T32
Test name
Test status
Simulation time 7083282156 ps
CPU time 14.99 seconds
Started May 28 01:08:25 PM PDT 24
Finished May 28 01:08:42 PM PDT 24
Peak memory 211008 kb
Host smart-fe5b5bd2-4473-4e90-bcf1-17ab1b3e64f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480392201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3480392201
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3208344519
Short name T7
Test name
Test status
Simulation time 348172151 ps
CPU time 9.03 seconds
Started May 28 01:08:04 PM PDT 24
Finished May 28 01:08:14 PM PDT 24
Peak memory 211612 kb
Host smart-c0022e9e-a3d7-47c1-850f-6369fd8b5656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208344519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3208344519
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4100746568
Short name T144
Test name
Test status
Simulation time 10441388283 ps
CPU time 26.32 seconds
Started May 28 01:08:56 PM PDT 24
Finished May 28 01:09:25 PM PDT 24
Peak memory 211820 kb
Host smart-27f793f7-209a-49f1-b533-29623a8fe3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100746568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4100746568
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3230529577
Short name T72
Test name
Test status
Simulation time 379231699 ps
CPU time 18.54 seconds
Started May 28 01:11:43 PM PDT 24
Finished May 28 01:12:07 PM PDT 24
Peak memory 211172 kb
Host smart-1729e3a4-7a10-4b1c-98a2-e1527a54fa42
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230529577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3230529577
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2342917801
Short name T112
Test name
Test status
Simulation time 1083107287 ps
CPU time 41.76 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:12:17 PM PDT 24
Peak memory 211992 kb
Host smart-99a1f415-ef05-4172-b102-40682910869c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342917801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2342917801
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2233628314
Short name T60
Test name
Test status
Simulation time 4459405850 ps
CPU time 72.46 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:12:53 PM PDT 24
Peak memory 219496 kb
Host smart-26164a44-6c3a-4041-bf2a-14b9bfd4bd80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233628314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2233628314
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1291575389
Short name T48
Test name
Test status
Simulation time 733292985 ps
CPU time 7.66 seconds
Started May 28 01:08:06 PM PDT 24
Finished May 28 01:08:15 PM PDT 24
Peak memory 210960 kb
Host smart-6cf84399-2262-4c84-9c9e-b740a44f68c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291575389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1291575389
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1560725880
Short name T95
Test name
Test status
Simulation time 41234690598 ps
CPU time 67.72 seconds
Started May 28 01:08:38 PM PDT 24
Finished May 28 01:09:48 PM PDT 24
Peak memory 219448 kb
Host smart-64577af2-5d88-45a5-879a-b53cb0f82617
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560725880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1560725880
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.919529837
Short name T102
Test name
Test status
Simulation time 4020609661 ps
CPU time 16.91 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:56 PM PDT 24
Peak memory 211200 kb
Host smart-667935cb-d381-4cd3-b740-96b77e2c6059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919529837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.919529837
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1090297533
Short name T89
Test name
Test status
Simulation time 1067667993 ps
CPU time 12.01 seconds
Started May 28 01:08:09 PM PDT 24
Finished May 28 01:08:22 PM PDT 24
Peak memory 210880 kb
Host smart-7344e526-c267-4d7e-9804-4976d0bfe5ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090297533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1090297533
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2718219205
Short name T106
Test name
Test status
Simulation time 7014079327 ps
CPU time 14 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:53 PM PDT 24
Peak memory 211236 kb
Host smart-1c73f620-2394-4033-a08f-90693808f498
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718219205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2718219205
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3962580374
Short name T444
Test name
Test status
Simulation time 178634205 ps
CPU time 4.35 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:39 PM PDT 24
Peak memory 211000 kb
Host smart-4812a93d-f3f5-472c-b5ff-791f7b3e230f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962580374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3962580374
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.159867592
Short name T82
Test name
Test status
Simulation time 2192523026 ps
CPU time 18.37 seconds
Started May 28 01:11:28 PM PDT 24
Finished May 28 01:11:56 PM PDT 24
Peak memory 211232 kb
Host smart-9367ddc7-1b0e-4de7-9f54-8458dbfd68e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159867592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.159867592
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2132119021
Short name T430
Test name
Test status
Simulation time 1604976863 ps
CPU time 13.47 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:53 PM PDT 24
Peak memory 219360 kb
Host smart-7d6a0e7a-4d6c-4dd2-8107-b0ee6b398b35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132119021 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2132119021
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2891368204
Short name T446
Test name
Test status
Simulation time 1813460532 ps
CPU time 10.86 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 211272 kb
Host smart-353d388d-b620-455c-8e1d-73837a2746ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891368204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2891368204
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.193271478
Short name T396
Test name
Test status
Simulation time 5061817377 ps
CPU time 8.39 seconds
Started May 28 01:11:25 PM PDT 24
Finished May 28 01:11:42 PM PDT 24
Peak memory 211120 kb
Host smart-886b7935-0e83-4fda-a7ca-b002060182a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193271478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.193271478
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.396860848
Short name T460
Test name
Test status
Simulation time 1809716437 ps
CPU time 14.59 seconds
Started May 28 01:11:28 PM PDT 24
Finished May 28 01:11:52 PM PDT 24
Peak memory 211064 kb
Host smart-d07402cb-b9f2-4251-a75f-155f86249285
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396860848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
396860848
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.961341372
Short name T388
Test name
Test status
Simulation time 6216182496 ps
CPU time 63.86 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:12:34 PM PDT 24
Peak memory 211200 kb
Host smart-c15107d0-6f52-4b2b-b9da-c0cb320305f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961341372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.961341372
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4150685917
Short name T409
Test name
Test status
Simulation time 11938885509 ps
CPU time 11.32 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 211200 kb
Host smart-9058836a-9023-431d-aea4-10939b8532f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150685917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4150685917
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2383926319
Short name T411
Test name
Test status
Simulation time 2356150381 ps
CPU time 14.4 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:49 PM PDT 24
Peak memory 219540 kb
Host smart-02a8fd9c-166e-4af5-8bb4-1c49dcb78a23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383926319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2383926319
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1018780691
Short name T401
Test name
Test status
Simulation time 2053723236 ps
CPU time 15.34 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:11:55 PM PDT 24
Peak memory 211224 kb
Host smart-02b53336-1ea4-425e-9a54-811bddecaf54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018780691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1018780691
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2448013022
Short name T465
Test name
Test status
Simulation time 6312010517 ps
CPU time 13.29 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:52 PM PDT 24
Peak memory 211324 kb
Host smart-970f0878-c434-489f-95fd-871621546e9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448013022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2448013022
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1871836911
Short name T400
Test name
Test status
Simulation time 3365971847 ps
CPU time 15.71 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:54 PM PDT 24
Peak memory 211204 kb
Host smart-72eb1a34-40f8-47db-b927-1805aa6b0ba6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871836911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1871836911
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3257738831
Short name T417
Test name
Test status
Simulation time 688313524 ps
CPU time 5.01 seconds
Started May 28 01:11:25 PM PDT 24
Finished May 28 01:11:37 PM PDT 24
Peak memory 219744 kb
Host smart-f3325d66-e3a5-4d1b-afa3-70ad08a2cc18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257738831 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3257738831
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3632918254
Short name T85
Test name
Test status
Simulation time 1357428751 ps
CPU time 12.49 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:51 PM PDT 24
Peak memory 211260 kb
Host smart-6863cdd0-6a4a-4503-9da1-81dc9c4990d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632918254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3632918254
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1824925310
Short name T456
Test name
Test status
Simulation time 3752582421 ps
CPU time 14.41 seconds
Started May 28 01:11:27 PM PDT 24
Finished May 28 01:11:52 PM PDT 24
Peak memory 211100 kb
Host smart-ca21b365-6a85-4be3-b882-e93bdce66d24
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824925310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1824925310
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2088647404
Short name T449
Test name
Test status
Simulation time 1088352874 ps
CPU time 10.86 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:51 PM PDT 24
Peak memory 210396 kb
Host smart-5a08d3de-ec60-4a77-908c-4b34e8bf83a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088647404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2088647404
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3299209832
Short name T439
Test name
Test status
Simulation time 8843740333 ps
CPU time 76.5 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:12:55 PM PDT 24
Peak memory 211180 kb
Host smart-58079178-5bcb-4114-9190-839addab4f76
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299209832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3299209832
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.48696646
Short name T428
Test name
Test status
Simulation time 719120973 ps
CPU time 11.42 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 219372 kb
Host smart-05f40108-383b-49c2-9fcb-53745beff569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48696646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.48696646
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.135181501
Short name T468
Test name
Test status
Simulation time 2556527953 ps
CPU time 40.76 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:12:20 PM PDT 24
Peak memory 211780 kb
Host smart-a199f05d-898d-4a07-9043-71a0ebb9bea2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135181501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.135181501
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3901435105
Short name T464
Test name
Test status
Simulation time 2352260064 ps
CPU time 14.04 seconds
Started May 28 01:11:43 PM PDT 24
Finished May 28 01:12:02 PM PDT 24
Peak memory 219552 kb
Host smart-0216ba27-92b7-473a-8da6-8e9bc4a99242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901435105 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3901435105
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1697655042
Short name T436
Test name
Test status
Simulation time 3950882056 ps
CPU time 10.43 seconds
Started May 28 01:11:40 PM PDT 24
Finished May 28 01:11:56 PM PDT 24
Peak memory 211208 kb
Host smart-b4c7d2e4-bbef-4111-946e-ea6114d6a213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697655042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1697655042
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.750432141
Short name T108
Test name
Test status
Simulation time 8070319412 ps
CPU time 44.37 seconds
Started May 28 01:11:27 PM PDT 24
Finished May 28 01:12:22 PM PDT 24
Peak memory 218428 kb
Host smart-1a8d6d32-493f-4135-895c-2cb6672e82c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750432141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.750432141
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3945016335
Short name T451
Test name
Test status
Simulation time 92724890 ps
CPU time 6.14 seconds
Started May 28 01:11:50 PM PDT 24
Finished May 28 01:12:03 PM PDT 24
Peak memory 211208 kb
Host smart-798d78f8-d599-44fa-a267-2d26e461b86a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945016335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3945016335
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1880241913
Short name T379
Test name
Test status
Simulation time 489063888 ps
CPU time 7.83 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:11:47 PM PDT 24
Peak memory 219404 kb
Host smart-eeaae547-6631-43f1-914e-71fbb10836f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880241913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1880241913
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.805509711
Short name T119
Test name
Test status
Simulation time 3208387931 ps
CPU time 37.82 seconds
Started May 28 01:11:38 PM PDT 24
Finished May 28 01:12:22 PM PDT 24
Peak memory 211340 kb
Host smart-4c252581-6cc9-4f1f-afde-7904d9b90307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805509711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.805509711
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1254160494
Short name T437
Test name
Test status
Simulation time 904167799 ps
CPU time 9.46 seconds
Started May 28 01:11:45 PM PDT 24
Finished May 28 01:12:00 PM PDT 24
Peak memory 219404 kb
Host smart-d2ee8aa2-b1b2-457f-9f7a-a3bf3f99985b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254160494 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1254160494
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.547834993
Short name T466
Test name
Test status
Simulation time 296115747 ps
CPU time 6.5 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:11:53 PM PDT 24
Peak memory 211132 kb
Host smart-a5d78c5f-a1c5-41e5-b2a1-28a5ef11b229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547834993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.547834993
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4195022009
Short name T71
Test name
Test status
Simulation time 26035446588 ps
CPU time 55.83 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:12:42 PM PDT 24
Peak memory 211492 kb
Host smart-5caa4b87-5818-4457-94e3-21f7dcf155ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195022009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4195022009
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2592670829
Short name T74
Test name
Test status
Simulation time 1714334960 ps
CPU time 13.82 seconds
Started May 28 01:11:42 PM PDT 24
Finished May 28 01:12:01 PM PDT 24
Peak memory 211164 kb
Host smart-6fd8e1d3-c843-4344-a910-8ab44a94e8e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592670829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2592670829
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2750077329
Short name T404
Test name
Test status
Simulation time 7803943092 ps
CPU time 19.06 seconds
Started May 28 01:11:42 PM PDT 24
Finished May 28 01:12:07 PM PDT 24
Peak memory 219556 kb
Host smart-13283c64-84ea-4e82-91f3-18d47afeef64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750077329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2750077329
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4086698605
Short name T120
Test name
Test status
Simulation time 4347701508 ps
CPU time 41.54 seconds
Started May 28 01:11:39 PM PDT 24
Finished May 28 01:12:27 PM PDT 24
Peak memory 212396 kb
Host smart-b6117eb6-fa2e-495a-9861-18d69eb0df46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086698605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4086698605
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1549150846
Short name T453
Test name
Test status
Simulation time 96975921 ps
CPU time 5.08 seconds
Started May 28 01:11:49 PM PDT 24
Finished May 28 01:12:01 PM PDT 24
Peak memory 219316 kb
Host smart-08f9894d-c1c4-44a6-ae04-17c0991dc45b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549150846 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1549150846
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3170897525
Short name T410
Test name
Test status
Simulation time 719013016 ps
CPU time 8.53 seconds
Started May 28 01:11:42 PM PDT 24
Finished May 28 01:11:56 PM PDT 24
Peak memory 211232 kb
Host smart-c76570af-f5f5-44fc-9199-7fe9463b92ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170897525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3170897525
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3117548711
Short name T100
Test name
Test status
Simulation time 1149849663 ps
CPU time 7.7 seconds
Started May 28 01:11:38 PM PDT 24
Finished May 28 01:11:52 PM PDT 24
Peak memory 211224 kb
Host smart-3ae96ce7-0a0c-4324-9ec6-0c387572e8a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117548711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3117548711
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3877502089
Short name T372
Test name
Test status
Simulation time 2025859603 ps
CPU time 13.58 seconds
Started May 28 01:11:39 PM PDT 24
Finished May 28 01:11:59 PM PDT 24
Peak memory 219396 kb
Host smart-b3a7c709-3fc3-414b-bc47-2acc53369040
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877502089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3877502089
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1815310482
Short name T118
Test name
Test status
Simulation time 267745862 ps
CPU time 38.11 seconds
Started May 28 01:11:40 PM PDT 24
Finished May 28 01:12:24 PM PDT 24
Peak memory 211252 kb
Host smart-8f78b906-6e90-43d4-b196-285df3c19f82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815310482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1815310482
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2357135067
Short name T455
Test name
Test status
Simulation time 1389015724 ps
CPU time 12.61 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:11:59 PM PDT 24
Peak memory 219392 kb
Host smart-f9c6cf3b-c69d-440b-8a81-cae9308b29ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357135067 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2357135067
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4071133705
Short name T80
Test name
Test status
Simulation time 5115104263 ps
CPU time 7 seconds
Started May 28 01:11:40 PM PDT 24
Finished May 28 01:11:53 PM PDT 24
Peak memory 211340 kb
Host smart-cfd8cd50-7db9-4b0c-87dc-307f922ef846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071133705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4071133705
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1072970472
Short name T450
Test name
Test status
Simulation time 20422263097 ps
CPU time 53.45 seconds
Started May 28 01:11:54 PM PDT 24
Finished May 28 01:12:54 PM PDT 24
Peak memory 211244 kb
Host smart-68caf2c1-c1b3-4a85-9b0a-625c20d34fb4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072970472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1072970472
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4172960817
Short name T422
Test name
Test status
Simulation time 111891093 ps
CPU time 4.21 seconds
Started May 28 01:11:43 PM PDT 24
Finished May 28 01:11:53 PM PDT 24
Peak memory 211092 kb
Host smart-d2a5af32-de02-4dd0-97fc-19c0c8970d76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172960817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4172960817
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3649122929
Short name T387
Test name
Test status
Simulation time 4863409192 ps
CPU time 18.29 seconds
Started May 28 01:11:39 PM PDT 24
Finished May 28 01:12:03 PM PDT 24
Peak memory 219448 kb
Host smart-301c9d70-1bdf-40b2-98f5-69442bc00340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649122929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3649122929
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4198905285
Short name T111
Test name
Test status
Simulation time 734403995 ps
CPU time 71.48 seconds
Started May 28 01:11:53 PM PDT 24
Finished May 28 01:13:11 PM PDT 24
Peak memory 212128 kb
Host smart-1d009ba2-9c1f-4cf8-8950-2722a70291bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198905285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4198905285
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.996113880
Short name T459
Test name
Test status
Simulation time 1188765696 ps
CPU time 11.83 seconds
Started May 28 01:11:49 PM PDT 24
Finished May 28 01:12:08 PM PDT 24
Peak memory 219400 kb
Host smart-916cf2b8-6b4a-4143-8af8-d121ce59165c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996113880 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.996113880
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.625682802
Short name T63
Test name
Test status
Simulation time 461580806 ps
CPU time 7.24 seconds
Started May 28 01:11:46 PM PDT 24
Finished May 28 01:11:59 PM PDT 24
Peak memory 211120 kb
Host smart-57cb8957-62fc-4826-af9f-f165cff11451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625682802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.625682802
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1640523157
Short name T78
Test name
Test status
Simulation time 11553115055 ps
CPU time 47.02 seconds
Started May 28 01:11:43 PM PDT 24
Finished May 28 01:12:35 PM PDT 24
Peak memory 211248 kb
Host smart-15b1f737-4bde-4e3f-ba0b-c0ccce8c9d45
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640523157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1640523157
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3658781166
Short name T385
Test name
Test status
Simulation time 4808158108 ps
CPU time 11.27 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:11:58 PM PDT 24
Peak memory 211504 kb
Host smart-f0044246-cc90-4d06-b9dd-e324efe18243
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658781166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3658781166
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1107716659
Short name T462
Test name
Test status
Simulation time 474257174 ps
CPU time 9.91 seconds
Started May 28 01:11:50 PM PDT 24
Finished May 28 01:12:07 PM PDT 24
Peak memory 219436 kb
Host smart-e500d724-107f-4a9a-aea5-6d14a2cdfcfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107716659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1107716659
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1240629377
Short name T448
Test name
Test status
Simulation time 261515595 ps
CPU time 37.79 seconds
Started May 28 01:11:40 PM PDT 24
Finished May 28 01:12:24 PM PDT 24
Peak memory 211292 kb
Host smart-cb725aad-130e-4676-aec3-1f124073112d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240629377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1240629377
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3032206439
Short name T397
Test name
Test status
Simulation time 499009813 ps
CPU time 4.32 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:11:51 PM PDT 24
Peak memory 211940 kb
Host smart-e79122b8-da7c-4208-8f17-27fa7780044c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032206439 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3032206439
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2617833042
Short name T79
Test name
Test status
Simulation time 15137747339 ps
CPU time 13.17 seconds
Started May 28 01:11:46 PM PDT 24
Finished May 28 01:12:05 PM PDT 24
Peak memory 211232 kb
Host smart-17af0cc0-c3a5-4404-9122-fdbe2b81a4cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617833042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2617833042
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2342459557
Short name T107
Test name
Test status
Simulation time 639901006 ps
CPU time 19.13 seconds
Started May 28 01:11:45 PM PDT 24
Finished May 28 01:12:10 PM PDT 24
Peak memory 211092 kb
Host smart-42c04901-1a74-432b-97d8-a26a875916b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342459557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2342459557
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3488695933
Short name T395
Test name
Test status
Simulation time 5089264855 ps
CPU time 15.26 seconds
Started May 28 01:11:44 PM PDT 24
Finished May 28 01:12:05 PM PDT 24
Peak memory 211236 kb
Host smart-1d0566f5-526b-444c-b3bb-58c36edb1227
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488695933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3488695933
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2186930637
Short name T370
Test name
Test status
Simulation time 1894018226 ps
CPU time 13.89 seconds
Started May 28 01:11:40 PM PDT 24
Finished May 28 01:12:00 PM PDT 24
Peak memory 219488 kb
Host smart-d0800a15-1414-4eab-9bc3-17bde11abf7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186930637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2186930637
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.425389866
Short name T445
Test name
Test status
Simulation time 1646483311 ps
CPU time 44.3 seconds
Started May 28 01:11:45 PM PDT 24
Finished May 28 01:12:36 PM PDT 24
Peak memory 211856 kb
Host smart-6399a9b8-82bc-437f-8050-d4a255ab064e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425389866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.425389866
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2711363192
Short name T381
Test name
Test status
Simulation time 5668655322 ps
CPU time 12.42 seconds
Started May 28 01:11:42 PM PDT 24
Finished May 28 01:12:00 PM PDT 24
Peak memory 219564 kb
Host smart-a8c78d83-4580-41d5-ae61-549ae7791646
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711363192 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2711363192
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.69305578
Short name T392
Test name
Test status
Simulation time 8996689733 ps
CPU time 11.05 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:11:58 PM PDT 24
Peak memory 211364 kb
Host smart-6e535b60-c8b0-4804-9571-a4fbbd284437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69305578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.69305578
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1799004910
Short name T426
Test name
Test status
Simulation time 376068985 ps
CPU time 18.28 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:12:05 PM PDT 24
Peak memory 211284 kb
Host smart-ab62f155-eb13-4cb8-92c5-d5d1c196e8e7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799004910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1799004910
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2629866267
Short name T454
Test name
Test status
Simulation time 249326179 ps
CPU time 4.96 seconds
Started May 28 01:11:47 PM PDT 24
Finished May 28 01:11:58 PM PDT 24
Peak memory 211240 kb
Host smart-6a030bd4-98c0-4f1d-b17e-463972de64bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629866267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2629866267
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1495295882
Short name T407
Test name
Test status
Simulation time 7785981169 ps
CPU time 17.63 seconds
Started May 28 01:12:00 PM PDT 24
Finished May 28 01:12:23 PM PDT 24
Peak memory 219472 kb
Host smart-317ed0e4-dff8-4e5e-a5e6-d43af0d3bc01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495295882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1495295882
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.757855520
Short name T116
Test name
Test status
Simulation time 1712654118 ps
CPU time 77.49 seconds
Started May 28 01:11:52 PM PDT 24
Finished May 28 01:13:16 PM PDT 24
Peak memory 213040 kb
Host smart-4a449bb2-7d1e-466c-a88e-c70e6e5d975c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757855520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.757855520
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.683042377
Short name T394
Test name
Test status
Simulation time 1892064072 ps
CPU time 14.95 seconds
Started May 28 01:11:57 PM PDT 24
Finished May 28 01:12:18 PM PDT 24
Peak memory 219432 kb
Host smart-c8df883b-b514-4f4b-b46a-8432582ef1be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683042377 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.683042377
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2911123658
Short name T416
Test name
Test status
Simulation time 30929232716 ps
CPU time 14.94 seconds
Started May 28 01:11:48 PM PDT 24
Finished May 28 01:12:09 PM PDT 24
Peak memory 211188 kb
Host smart-4f612e26-f17e-4727-9b24-598e2f2b8ea2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911123658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2911123658
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2536968334
Short name T105
Test name
Test status
Simulation time 6975495573 ps
CPU time 49.55 seconds
Started May 28 01:11:54 PM PDT 24
Finished May 28 01:12:51 PM PDT 24
Peak memory 211248 kb
Host smart-a1cf639f-6fe1-4252-bd26-4e03defda702
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536968334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2536968334
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.382570201
Short name T103
Test name
Test status
Simulation time 5606233145 ps
CPU time 12.05 seconds
Started May 28 01:11:52 PM PDT 24
Finished May 28 01:12:12 PM PDT 24
Peak memory 211340 kb
Host smart-abced514-743f-4c98-849f-61c927a981df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382570201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.382570201
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2680887503
Short name T399
Test name
Test status
Simulation time 2100226272 ps
CPU time 13.56 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:12:00 PM PDT 24
Peak memory 215668 kb
Host smart-de55766f-7dca-4489-86fc-f6177064057c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680887503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2680887503
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3205077197
Short name T408
Test name
Test status
Simulation time 388130935 ps
CPU time 7.26 seconds
Started May 28 01:11:48 PM PDT 24
Finished May 28 01:12:02 PM PDT 24
Peak memory 219372 kb
Host smart-24b0d68d-43d5-4cab-b16f-2b3a2a59a9a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205077197 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3205077197
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2233252894
Short name T438
Test name
Test status
Simulation time 3101345011 ps
CPU time 12.77 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:12:00 PM PDT 24
Peak memory 211232 kb
Host smart-f01df915-9fae-4147-a606-61d0f2675d0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233252894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2233252894
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1021085648
Short name T81
Test name
Test status
Simulation time 20066993323 ps
CPU time 84.77 seconds
Started May 28 01:11:54 PM PDT 24
Finished May 28 01:13:27 PM PDT 24
Peak memory 211248 kb
Host smart-dc5a7f7a-d9ad-4104-af02-eb72efc814b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021085648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1021085648
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1772295038
Short name T101
Test name
Test status
Simulation time 1658895980 ps
CPU time 6 seconds
Started May 28 01:11:43 PM PDT 24
Finished May 28 01:11:55 PM PDT 24
Peak memory 211124 kb
Host smart-2a5f37aa-5333-42cf-89cf-f60f2bfc3554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772295038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1772295038
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2545255960
Short name T389
Test name
Test status
Simulation time 1364500823 ps
CPU time 9.29 seconds
Started May 28 01:11:41 PM PDT 24
Finished May 28 01:11:56 PM PDT 24
Peak memory 219444 kb
Host smart-753ffb70-966e-40fb-8b81-124e8fced7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545255960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2545255960
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3951868631
Short name T115
Test name
Test status
Simulation time 6954402285 ps
CPU time 76.65 seconds
Started May 28 01:11:43 PM PDT 24
Finished May 28 01:13:05 PM PDT 24
Peak memory 219420 kb
Host smart-fb95c9e6-cada-4047-b0e0-ba83ef6734ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951868631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3951868631
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1310730004
Short name T378
Test name
Test status
Simulation time 293174427 ps
CPU time 5.75 seconds
Started May 28 01:11:53 PM PDT 24
Finished May 28 01:12:06 PM PDT 24
Peak memory 219408 kb
Host smart-dd40c7c6-4e31-4900-b764-aad36cca082d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310730004 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1310730004
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1100673412
Short name T380
Test name
Test status
Simulation time 332980738 ps
CPU time 4.32 seconds
Started May 28 01:11:54 PM PDT 24
Finished May 28 01:12:06 PM PDT 24
Peak memory 211176 kb
Host smart-51d9c335-eb8e-4c1e-932b-28a309554e76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100673412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1100673412
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.631408962
Short name T75
Test name
Test status
Simulation time 6535893629 ps
CPU time 26.14 seconds
Started May 28 01:11:46 PM PDT 24
Finished May 28 01:12:18 PM PDT 24
Peak memory 211248 kb
Host smart-699d8995-5e21-4f79-9b63-77b170d03086
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631408962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.631408962
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2318656406
Short name T99
Test name
Test status
Simulation time 2019047693 ps
CPU time 15.54 seconds
Started May 28 01:11:43 PM PDT 24
Finished May 28 01:12:04 PM PDT 24
Peak memory 211180 kb
Host smart-74690c93-f3f1-4ca6-a573-17a91799ba94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318656406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2318656406
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2404637229
Short name T429
Test name
Test status
Simulation time 6351215368 ps
CPU time 15.56 seconds
Started May 28 01:11:45 PM PDT 24
Finished May 28 01:12:06 PM PDT 24
Peak memory 219584 kb
Host smart-a61111f8-dfb3-4ae1-b238-6e46db11c849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404637229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2404637229
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3999287463
Short name T447
Test name
Test status
Simulation time 595045455 ps
CPU time 8.08 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:48 PM PDT 24
Peak memory 211076 kb
Host smart-e67ee06b-6941-413e-943b-f1ca2058eb9b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999287463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3999287463
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3115691039
Short name T463
Test name
Test status
Simulation time 7368214750 ps
CPU time 14.85 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:11:56 PM PDT 24
Peak memory 210932 kb
Host smart-d091ab5e-0a58-4651-b777-c0fdcc81806a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115691039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3115691039
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1656735359
Short name T391
Test name
Test status
Simulation time 2193338575 ps
CPU time 18.45 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:59 PM PDT 24
Peak memory 211064 kb
Host smart-5d8067fa-4eb1-436b-99c9-477b59ae71a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656735359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1656735359
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2669978152
Short name T374
Test name
Test status
Simulation time 920645058 ps
CPU time 6.29 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:41 PM PDT 24
Peak memory 219456 kb
Host smart-7b3a6b26-31b7-4601-89ad-52ee114aadff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669978152 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2669978152
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3245705124
Short name T421
Test name
Test status
Simulation time 820263185 ps
CPU time 5.79 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:11:47 PM PDT 24
Peak memory 210992 kb
Host smart-520ddffd-3810-4fc7-b2c9-a286aa89abeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245705124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3245705124
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4039504700
Short name T377
Test name
Test status
Simulation time 3999177626 ps
CPU time 15.32 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:56 PM PDT 24
Peak memory 211092 kb
Host smart-eb4b48fc-a9d0-43b7-8a56-b15688578487
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039504700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4039504700
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1970362271
Short name T452
Test name
Test status
Simulation time 2008065395 ps
CPU time 15.22 seconds
Started May 28 01:11:27 PM PDT 24
Finished May 28 01:11:52 PM PDT 24
Peak memory 211104 kb
Host smart-90731b90-3703-4d85-ba17-16beead40bd5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970362271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1970362271
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4216055043
Short name T402
Test name
Test status
Simulation time 11393953910 ps
CPU time 96.51 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:13:18 PM PDT 24
Peak memory 211184 kb
Host smart-a06569cc-0a45-4172-9724-822c713c5caa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216055043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4216055043
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1929741568
Short name T442
Test name
Test status
Simulation time 347903543 ps
CPU time 4.4 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:11:46 PM PDT 24
Peak memory 211044 kb
Host smart-5abc425b-efdb-49d1-94ef-dd95cc0b07c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929741568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1929741568
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.140804451
Short name T390
Test name
Test status
Simulation time 321935262 ps
CPU time 10.46 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 219360 kb
Host smart-fa992c45-b54b-4709-bdb3-fe992edd7253
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140804451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.140804451
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2099977012
Short name T58
Test name
Test status
Simulation time 2945669432 ps
CPU time 74.2 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:12:56 PM PDT 24
Peak memory 212028 kb
Host smart-73a75f01-5d0f-4cc3-8505-cb8cfa0153a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099977012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2099977012
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.376843181
Short name T84
Test name
Test status
Simulation time 88208402 ps
CPU time 4.22 seconds
Started May 28 01:11:28 PM PDT 24
Finished May 28 01:11:42 PM PDT 24
Peak memory 211172 kb
Host smart-313cbdcd-bea1-4e3b-acf7-5939a720155c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376843181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.376843181
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3563743160
Short name T375
Test name
Test status
Simulation time 902995201 ps
CPU time 10.15 seconds
Started May 28 01:11:32 PM PDT 24
Finished May 28 01:11:51 PM PDT 24
Peak memory 211200 kb
Host smart-8ad1ad5b-c259-485b-bc98-c1f14d25a62e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563743160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3563743160
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.375880445
Short name T384
Test name
Test status
Simulation time 1620275629 ps
CPU time 17.39 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:57 PM PDT 24
Peak memory 211172 kb
Host smart-4ad79e01-e1ae-418a-aea7-01435c366842
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375880445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.375880445
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1267109512
Short name T434
Test name
Test status
Simulation time 1884894638 ps
CPU time 15.64 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:54 PM PDT 24
Peak memory 219052 kb
Host smart-ab9c5df3-4dd7-43be-957d-bf9844c18e65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267109512 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1267109512
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2965164481
Short name T440
Test name
Test status
Simulation time 1913298260 ps
CPU time 14.74 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:55 PM PDT 24
Peak memory 211272 kb
Host smart-4e654767-79aa-4af3-9983-cc72a1777382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965164481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2965164481
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3339154891
Short name T432
Test name
Test status
Simulation time 296203503 ps
CPU time 6.19 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:11:46 PM PDT 24
Peak memory 211032 kb
Host smart-efaf4ef8-f1aa-430d-91b0-91992f33dac6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339154891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3339154891
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1272882530
Short name T425
Test name
Test status
Simulation time 6319402680 ps
CPU time 13.07 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:53 PM PDT 24
Peak memory 211248 kb
Host smart-127bf5c6-d3e3-4a48-94ad-6d2ae3da786f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272882530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1272882530
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1197538785
Short name T420
Test name
Test status
Simulation time 3174096541 ps
CPU time 15.28 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:54 PM PDT 24
Peak memory 210924 kb
Host smart-76dd823f-ca0a-4643-bc28-11bb690bdbdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197538785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1197538785
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1012649141
Short name T382
Test name
Test status
Simulation time 2207724483 ps
CPU time 13.81 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:54 PM PDT 24
Peak memory 219524 kb
Host smart-6253454e-a9d4-47cb-8c42-e2dc3dbae97d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012649141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1012649141
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2326180870
Short name T398
Test name
Test status
Simulation time 1291199679 ps
CPU time 42.46 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:12:23 PM PDT 24
Peak memory 211416 kb
Host smart-ee6c3eed-1bd1-4b6d-9964-d58d0a6bb640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326180870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2326180870
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4092772067
Short name T87
Test name
Test status
Simulation time 1139699987 ps
CPU time 5.79 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:41 PM PDT 24
Peak memory 211064 kb
Host smart-d92220cd-b616-43c9-9a5a-08520520c131
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092772067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4092772067
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.236897607
Short name T383
Test name
Test status
Simulation time 298982791 ps
CPU time 6.55 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:42 PM PDT 24
Peak memory 211172 kb
Host smart-52f982df-7403-4e3f-9ff5-45c7d15189b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236897607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.236897607
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3761658403
Short name T376
Test name
Test status
Simulation time 1135505229 ps
CPU time 12.38 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:51 PM PDT 24
Peak memory 211100 kb
Host smart-64231a44-05f5-434a-9392-e4555f85732c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761658403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3761658403
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1607917357
Short name T415
Test name
Test status
Simulation time 19070118554 ps
CPU time 10.73 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:46 PM PDT 24
Peak memory 214160 kb
Host smart-b724bcc2-3413-43c4-8b26-77af6be1be1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607917357 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1607917357
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2789779752
Short name T427
Test name
Test status
Simulation time 287743470 ps
CPU time 4.12 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:35 PM PDT 24
Peak memory 211084 kb
Host smart-ec873d7f-5b56-4f86-9f85-9d4d149207c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789779752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2789779752
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1051864722
Short name T461
Test name
Test status
Simulation time 2988215372 ps
CPU time 12.68 seconds
Started May 28 01:11:25 PM PDT 24
Finished May 28 01:11:46 PM PDT 24
Peak memory 211208 kb
Host smart-9b86d9b4-98af-4f6b-a812-d4cc27c8cb2a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051864722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1051864722
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2294909113
Short name T413
Test name
Test status
Simulation time 164585850 ps
CPU time 4.22 seconds
Started May 28 01:11:23 PM PDT 24
Finished May 28 01:11:32 PM PDT 24
Peak memory 211060 kb
Host smart-c523408d-770f-4f8a-8b6a-44ffdb5fbc06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294909113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2294909113
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.204120543
Short name T423
Test name
Test status
Simulation time 19562950212 ps
CPU time 82.53 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:13:03 PM PDT 24
Peak memory 211304 kb
Host smart-a4ffe1c5-081f-4224-bdc4-9db75edec013
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204120543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.204120543
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2937229132
Short name T393
Test name
Test status
Simulation time 9826603272 ps
CPU time 12.18 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:11:44 PM PDT 24
Peak memory 211360 kb
Host smart-f99e0407-0239-44e6-8823-6ab952cf2de7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937229132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2937229132
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1156169936
Short name T412
Test name
Test status
Simulation time 4513015258 ps
CPU time 19.26 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:11:54 PM PDT 24
Peak memory 216000 kb
Host smart-03ad63f4-994f-438e-ba95-28d964ee29e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156169936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1156169936
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1663967546
Short name T110
Test name
Test status
Simulation time 6976115587 ps
CPU time 75.38 seconds
Started May 28 01:11:24 PM PDT 24
Finished May 28 01:12:47 PM PDT 24
Peak memory 219412 kb
Host smart-4cf4cdd1-af83-4439-aaaa-374ef709efe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663967546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1663967546
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2643502449
Short name T373
Test name
Test status
Simulation time 6594137735 ps
CPU time 14.31 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:54 PM PDT 24
Peak memory 218928 kb
Host smart-31387d62-3bf8-4578-99ff-5a8ac6cbbfd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643502449 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2643502449
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3806818428
Short name T88
Test name
Test status
Simulation time 1711520732 ps
CPU time 13.75 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:11:53 PM PDT 24
Peak memory 211232 kb
Host smart-6af88cfd-93e4-4606-a5e7-a6482e42105b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806818428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3806818428
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1411550155
Short name T414
Test name
Test status
Simulation time 1040685715 ps
CPU time 34.76 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:12:14 PM PDT 24
Peak memory 211248 kb
Host smart-602aaa10-ba55-47a7-a452-255d4541c40d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411550155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1411550155
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2952665358
Short name T73
Test name
Test status
Simulation time 5100487685 ps
CPU time 11.65 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:52 PM PDT 24
Peak memory 211320 kb
Host smart-66b25b38-7b33-4022-b3b1-6e4123bf4bee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952665358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2952665358
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2474305512
Short name T369
Test name
Test status
Simulation time 1240174702 ps
CPU time 15.16 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:55 PM PDT 24
Peak memory 219424 kb
Host smart-0410a263-c033-45fb-8cba-e3ff173d68ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474305512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2474305512
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3451460665
Short name T457
Test name
Test status
Simulation time 213963875 ps
CPU time 68.95 seconds
Started May 28 01:11:23 PM PDT 24
Finished May 28 01:12:38 PM PDT 24
Peak memory 211304 kb
Host smart-57e79d8e-42b4-471f-9868-810cb5ba0a34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451460665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3451460665
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1236683989
Short name T371
Test name
Test status
Simulation time 4386657391 ps
CPU time 11.07 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 219436 kb
Host smart-98de1cdb-3615-42e7-b5e2-333ab0cfde01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236683989 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1236683989
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1366189593
Short name T62
Test name
Test status
Simulation time 386892578 ps
CPU time 6.78 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:11:46 PM PDT 24
Peak memory 211240 kb
Host smart-d3fb9b2b-7b59-4a49-82e3-1f23b7ad6850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366189593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1366189593
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2603328424
Short name T83
Test name
Test status
Simulation time 5714610376 ps
CPU time 52.1 seconds
Started May 28 01:11:32 PM PDT 24
Finished May 28 01:12:33 PM PDT 24
Peak memory 211216 kb
Host smart-ae78bcfc-226a-4739-b03b-3b2cc6729dce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603328424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2603328424
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1706947342
Short name T443
Test name
Test status
Simulation time 890574294 ps
CPU time 9.34 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:11:51 PM PDT 24
Peak memory 211132 kb
Host smart-4fbbf47b-244a-4a82-964e-0609c23ffa03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706947342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1706947342
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.200474206
Short name T405
Test name
Test status
Simulation time 7162627133 ps
CPU time 17.76 seconds
Started May 28 01:11:32 PM PDT 24
Finished May 28 01:11:59 PM PDT 24
Peak memory 219548 kb
Host smart-102fce5a-63d8-492f-9ef0-b4987b799062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200474206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.200474206
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3569364049
Short name T458
Test name
Test status
Simulation time 1800975884 ps
CPU time 46.24 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:12:28 PM PDT 24
Peak memory 211800 kb
Host smart-c115416c-4c43-4e1f-9dac-aa0ea1484684
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569364049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3569364049
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3139446340
Short name T441
Test name
Test status
Simulation time 1578076751 ps
CPU time 9.16 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:11:49 PM PDT 24
Peak memory 219508 kb
Host smart-5a3b7cb3-090b-42dc-830e-2f61bb29e8bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139446340 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3139446340
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3727662017
Short name T467
Test name
Test status
Simulation time 1876362498 ps
CPU time 14.74 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:55 PM PDT 24
Peak memory 211164 kb
Host smart-be6a4f0a-b8ba-4c60-b6c8-1457fe598d73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727662017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3727662017
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1229380356
Short name T86
Test name
Test status
Simulation time 54228266635 ps
CPU time 88.91 seconds
Started May 28 01:11:26 PM PDT 24
Finished May 28 01:13:04 PM PDT 24
Peak memory 211244 kb
Host smart-c64b6ba1-8f35-4c92-9020-b9ed467c7cfb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229380356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1229380356
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1443787985
Short name T61
Test name
Test status
Simulation time 5425633780 ps
CPU time 11.66 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:11:51 PM PDT 24
Peak memory 211296 kb
Host smart-9af8e206-ae50-4bb0-a440-9348df58e29c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443787985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1443787985
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1637933617
Short name T418
Test name
Test status
Simulation time 1035435283 ps
CPU time 6.42 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:46 PM PDT 24
Peak memory 219512 kb
Host smart-e8c60808-5991-4740-96a1-88d924509860
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637933617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1637933617
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2206117771
Short name T59
Test name
Test status
Simulation time 1784938128 ps
CPU time 75.85 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:12:55 PM PDT 24
Peak memory 211276 kb
Host smart-79563dc3-db13-4805-a033-47a88fdb9d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206117771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2206117771
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2389360261
Short name T406
Test name
Test status
Simulation time 429487688 ps
CPU time 6.09 seconds
Started May 28 01:11:30 PM PDT 24
Finished May 28 01:11:46 PM PDT 24
Peak memory 213284 kb
Host smart-bd175466-27b0-49e8-aa5e-f82742a5d3ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389360261 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2389360261
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2311945540
Short name T403
Test name
Test status
Simulation time 7233180156 ps
CPU time 11.28 seconds
Started May 28 01:11:29 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 211228 kb
Host smart-40c4e8b7-e625-4b51-be7c-c6d61e1aaa4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311945540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2311945540
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.554859746
Short name T77
Test name
Test status
Simulation time 16122415916 ps
CPU time 65.25 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:12:47 PM PDT 24
Peak memory 210920 kb
Host smart-e228249d-225d-4dab-93ea-7a042e555e8f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554859746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.554859746
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3461847349
Short name T433
Test name
Test status
Simulation time 1830865442 ps
CPU time 9.04 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 210868 kb
Host smart-bb061c70-817b-4f10-adca-27cb8c1d21f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461847349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3461847349
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3230994989
Short name T419
Test name
Test status
Simulation time 1630724655 ps
CPU time 11.53 seconds
Started May 28 01:11:27 PM PDT 24
Finished May 28 01:11:49 PM PDT 24
Peak memory 215144 kb
Host smart-9f89643a-b8fe-40d7-b945-34eb470384d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230994989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3230994989
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3052391573
Short name T424
Test name
Test status
Simulation time 1507294615 ps
CPU time 13.52 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:54 PM PDT 24
Peak memory 219488 kb
Host smart-113a3792-ba30-432a-b3ba-bf196fd9667d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052391573 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3052391573
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3208177814
Short name T435
Test name
Test status
Simulation time 4890649541 ps
CPU time 11.64 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:52 PM PDT 24
Peak memory 211228 kb
Host smart-edcef6c3-c4e6-4c65-b0a8-587b2fddd189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208177814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3208177814
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.688937761
Short name T109
Test name
Test status
Simulation time 44235482448 ps
CPU time 90.9 seconds
Started May 28 01:11:33 PM PDT 24
Finished May 28 01:13:12 PM PDT 24
Peak memory 212252 kb
Host smart-422d5b5b-38e7-4d17-b8fc-6ae08c118c00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688937761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.688937761
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1099574399
Short name T386
Test name
Test status
Simulation time 89086843 ps
CPU time 4.35 seconds
Started May 28 01:11:28 PM PDT 24
Finished May 28 01:11:42 PM PDT 24
Peak memory 211132 kb
Host smart-80b72eb0-7f15-4632-bc4d-a7cc8379e1a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099574399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1099574399
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3553748721
Short name T431
Test name
Test status
Simulation time 178013099 ps
CPU time 9.53 seconds
Started May 28 01:11:31 PM PDT 24
Finished May 28 01:11:49 PM PDT 24
Peak memory 219404 kb
Host smart-ba4470fe-6e26-43bb-bccc-84a2e0ebbb51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553748721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3553748721
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.158729498
Short name T113
Test name
Test status
Simulation time 7267065766 ps
CPU time 42.29 seconds
Started May 28 01:11:28 PM PDT 24
Finished May 28 01:12:20 PM PDT 24
Peak memory 219512 kb
Host smart-74fa724b-b771-45f8-94d2-a77ce09e3d37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158729498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.158729498
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3894677662
Short name T40
Test name
Test status
Simulation time 2363629190 ps
CPU time 15.65 seconds
Started May 28 01:07:54 PM PDT 24
Finished May 28 01:08:11 PM PDT 24
Peak memory 210928 kb
Host smart-54df2b3a-1b6d-4b33-aa38-0f76f1980a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894677662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3894677662
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3257669473
Short name T121
Test name
Test status
Simulation time 1936797194 ps
CPU time 70.19 seconds
Started May 28 01:08:12 PM PDT 24
Finished May 28 01:09:24 PM PDT 24
Peak memory 211228 kb
Host smart-3284562c-e4ef-406a-98c7-de8e3593b507
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257669473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3257669473
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1552597152
Short name T320
Test name
Test status
Simulation time 2410195030 ps
CPU time 13.45 seconds
Started May 28 01:08:21 PM PDT 24
Finished May 28 01:08:37 PM PDT 24
Peak memory 211736 kb
Host smart-e9356b50-e111-4782-a208-f2486f590c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552597152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1552597152
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3108131099
Short name T30
Test name
Test status
Simulation time 4790871136 ps
CPU time 58 seconds
Started May 28 01:08:05 PM PDT 24
Finished May 28 01:09:03 PM PDT 24
Peak memory 233440 kb
Host smart-7a0addce-29e3-4272-afc3-5e577b84658d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108131099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3108131099
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2217991139
Short name T129
Test name
Test status
Simulation time 25783807774 ps
CPU time 25.42 seconds
Started May 28 01:08:12 PM PDT 24
Finished May 28 01:08:39 PM PDT 24
Peak memory 219216 kb
Host smart-0d724ca7-ba66-4e7b-9240-3151b836822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217991139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2217991139
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2249059141
Short name T310
Test name
Test status
Simulation time 3730564394 ps
CPU time 38.3 seconds
Started May 28 01:08:09 PM PDT 24
Finished May 28 01:08:49 PM PDT 24
Peak memory 212728 kb
Host smart-4a11a0b7-4ac5-408b-b119-629684ce1d41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249059141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2249059141
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1863600658
Short name T159
Test name
Test status
Simulation time 1412886049 ps
CPU time 12.78 seconds
Started May 28 01:08:46 PM PDT 24
Finished May 28 01:09:01 PM PDT 24
Peak memory 211232 kb
Host smart-d48a4a36-0e12-493d-8eec-bed6a80ef892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863600658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1863600658
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2604868223
Short name T214
Test name
Test status
Simulation time 100299979352 ps
CPU time 238.38 seconds
Started May 28 01:08:03 PM PDT 24
Finished May 28 01:12:03 PM PDT 24
Peak memory 218296 kb
Host smart-cc5f37c8-a5c7-455c-a5d3-3010b4f54ec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604868223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2604868223
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1913626960
Short name T190
Test name
Test status
Simulation time 3660918601 ps
CPU time 30.73 seconds
Started May 28 01:08:35 PM PDT 24
Finished May 28 01:09:09 PM PDT 24
Peak memory 211992 kb
Host smart-3b2f61ff-2955-4a8f-9bba-40feb83a545b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913626960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1913626960
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1979670845
Short name T134
Test name
Test status
Simulation time 5053227671 ps
CPU time 13.4 seconds
Started May 28 01:08:38 PM PDT 24
Finished May 28 01:08:55 PM PDT 24
Peak memory 211272 kb
Host smart-99f9d580-788a-4560-8602-91869eec4a3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979670845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1979670845
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.383355903
Short name T29
Test name
Test status
Simulation time 1280408194 ps
CPU time 112.15 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:10:13 PM PDT 24
Peak memory 239500 kb
Host smart-41c255e1-5351-47c4-879a-ff64fc52d308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383355903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.383355903
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3772928754
Short name T303
Test name
Test status
Simulation time 1716532885 ps
CPU time 21.88 seconds
Started May 28 01:08:12 PM PDT 24
Finished May 28 01:08:41 PM PDT 24
Peak memory 212988 kb
Host smart-9f794d8c-f599-4133-9557-bc3a0c5227fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772928754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3772928754
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.346742689
Short name T274
Test name
Test status
Simulation time 12122835620 ps
CPU time 35.46 seconds
Started May 28 01:08:03 PM PDT 24
Finished May 28 01:08:40 PM PDT 24
Peak memory 213652 kb
Host smart-5d3062d1-6e92-4bae-bb87-de4d0e4b12b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346742689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.346742689
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4177404212
Short name T198
Test name
Test status
Simulation time 85562964 ps
CPU time 4.53 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:08:39 PM PDT 24
Peak memory 210932 kb
Host smart-eee07ddd-7afa-4289-a319-cc55c9668eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177404212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4177404212
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2933649571
Short name T39
Test name
Test status
Simulation time 62892823655 ps
CPU time 231.36 seconds
Started May 28 01:08:09 PM PDT 24
Finished May 28 01:12:02 PM PDT 24
Peak memory 233976 kb
Host smart-ca69ef21-fe69-4ceb-9768-ca4348b92b4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933649571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2933649571
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2630456966
Short name T331
Test name
Test status
Simulation time 8594594104 ps
CPU time 17.39 seconds
Started May 28 01:08:01 PM PDT 24
Finished May 28 01:08:20 PM PDT 24
Peak memory 210588 kb
Host smart-4c7616ea-11cd-4d5b-918c-493bd13124fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630456966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2630456966
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1084019291
Short name T150
Test name
Test status
Simulation time 183078721 ps
CPU time 9.75 seconds
Started May 28 01:08:10 PM PDT 24
Finished May 28 01:08:21 PM PDT 24
Peak memory 211828 kb
Host smart-266622a6-cfd9-4be9-becd-5825fd040d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084019291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1084019291
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3440560424
Short name T184
Test name
Test status
Simulation time 2359298360 ps
CPU time 48.34 seconds
Started May 28 01:07:56 PM PDT 24
Finished May 28 01:08:45 PM PDT 24
Peak memory 215124 kb
Host smart-7d861010-75b5-40b5-9cdd-af5d94143071
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440560424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3440560424
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3226961796
Short name T211
Test name
Test status
Simulation time 1708859828 ps
CPU time 14.15 seconds
Started May 28 01:08:04 PM PDT 24
Finished May 28 01:08:19 PM PDT 24
Peak memory 210932 kb
Host smart-41f3d8ff-000a-4af9-99f7-7e4d166790fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226961796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3226961796
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.197025189
Short name T345
Test name
Test status
Simulation time 39889592509 ps
CPU time 28.66 seconds
Started May 28 01:08:17 PM PDT 24
Finished May 28 01:08:48 PM PDT 24
Peak memory 211916 kb
Host smart-255f0453-aea4-4cc3-9291-d631c0171e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197025189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.197025189
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1168675005
Short name T334
Test name
Test status
Simulation time 1065045129 ps
CPU time 8.66 seconds
Started May 28 01:08:14 PM PDT 24
Finished May 28 01:08:24 PM PDT 24
Peak memory 210960 kb
Host smart-3a374ebb-dacf-4ed6-9110-43f776bd26ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168675005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1168675005
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1644578269
Short name T96
Test name
Test status
Simulation time 694616606 ps
CPU time 16.83 seconds
Started May 28 01:07:58 PM PDT 24
Finished May 28 01:08:16 PM PDT 24
Peak memory 212888 kb
Host smart-69c4ea5f-5216-4861-8552-4d1299fb3dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644578269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1644578269
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2049092396
Short name T215
Test name
Test status
Simulation time 10865539224 ps
CPU time 91.84 seconds
Started May 28 01:08:10 PM PDT 24
Finished May 28 01:09:43 PM PDT 24
Peak memory 219116 kb
Host smart-eb6500ed-00b3-4230-b404-0a7463fe7db1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049092396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2049092396
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1188193024
Short name T209
Test name
Test status
Simulation time 8690915427 ps
CPU time 16.49 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:08:46 PM PDT 24
Peak memory 210988 kb
Host smart-542fc2dc-10d2-4324-9b95-0e3c21c3571f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188193024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1188193024
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1095618597
Short name T361
Test name
Test status
Simulation time 8349661473 ps
CPU time 185.21 seconds
Started May 28 01:08:05 PM PDT 24
Finished May 28 01:11:11 PM PDT 24
Peak memory 224316 kb
Host smart-a87a2a4b-a91f-4d99-ace1-27e25ae82c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095618597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1095618597
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.673408169
Short name T363
Test name
Test status
Simulation time 50163032192 ps
CPU time 35.17 seconds
Started May 28 01:08:10 PM PDT 24
Finished May 28 01:08:46 PM PDT 24
Peak memory 211748 kb
Host smart-eb9ce7bd-0983-429a-be94-819b2ec9a1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673408169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.673408169
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3180871435
Short name T357
Test name
Test status
Simulation time 747792858 ps
CPU time 9.85 seconds
Started May 28 01:08:04 PM PDT 24
Finished May 28 01:08:15 PM PDT 24
Peak memory 210840 kb
Host smart-3d2d4675-88f0-485d-a9ff-02e4986f10fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3180871435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3180871435
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.928023809
Short name T221
Test name
Test status
Simulation time 2027750959 ps
CPU time 13.71 seconds
Started May 28 01:08:16 PM PDT 24
Finished May 28 01:08:31 PM PDT 24
Peak memory 213632 kb
Host smart-8ecb0b96-1ebb-414c-8f9d-eb9b6680e937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928023809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.928023809
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4027360559
Short name T179
Test name
Test status
Simulation time 1344366207 ps
CPU time 15.13 seconds
Started May 28 01:08:12 PM PDT 24
Finished May 28 01:08:29 PM PDT 24
Peak memory 213968 kb
Host smart-f63540b8-655e-4480-b3fa-6ef91c84d4ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027360559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4027360559
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2198441527
Short name T177
Test name
Test status
Simulation time 1717378396 ps
CPU time 9.5 seconds
Started May 28 01:08:16 PM PDT 24
Finished May 28 01:08:27 PM PDT 24
Peak memory 210940 kb
Host smart-5baf788a-523f-40eb-9628-9b239ad3e6ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198441527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2198441527
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2780633914
Short name T219
Test name
Test status
Simulation time 70691580340 ps
CPU time 214.77 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:12:00 PM PDT 24
Peak memory 236996 kb
Host smart-a953ae17-9b85-4004-91cc-e1eea8d9e2d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780633914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2780633914
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1993326351
Short name T306
Test name
Test status
Simulation time 2377596908 ps
CPU time 23.85 seconds
Started May 28 01:08:07 PM PDT 24
Finished May 28 01:08:32 PM PDT 24
Peak memory 211784 kb
Host smart-7bc23619-a978-4d86-9fb7-cec4caa9cd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993326351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1993326351
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2375938151
Short name T356
Test name
Test status
Simulation time 392661981 ps
CPU time 5.83 seconds
Started May 28 01:08:15 PM PDT 24
Finished May 28 01:08:23 PM PDT 24
Peak memory 210872 kb
Host smart-90ff8f83-3f96-4a5d-b78a-d4b892d20962
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375938151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2375938151
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3510552284
Short name T263
Test name
Test status
Simulation time 371262896 ps
CPU time 9.79 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:08:32 PM PDT 24
Peak memory 213220 kb
Host smart-22640331-fee8-4c28-a6cf-a9cc6c2222c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510552284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3510552284
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4172618073
Short name T98
Test name
Test status
Simulation time 510806647 ps
CPU time 21.49 seconds
Started May 28 01:08:24 PM PDT 24
Finished May 28 01:08:48 PM PDT 24
Peak memory 214980 kb
Host smart-d8af4509-85d0-4ba2-b5fd-7cf532a572f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172618073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4172618073
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2823245722
Short name T366
Test name
Test status
Simulation time 1139489557 ps
CPU time 11.37 seconds
Started May 28 01:08:21 PM PDT 24
Finished May 28 01:08:35 PM PDT 24
Peak memory 210932 kb
Host smart-35219048-7a23-40d5-9af4-6b38c970bb15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823245722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2823245722
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.31022108
Short name T307
Test name
Test status
Simulation time 376658144481 ps
CPU time 231.74 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:12:13 PM PDT 24
Peak memory 234528 kb
Host smart-fe978f2a-ace4-4a70-b9f7-4dbaa66fd0ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31022108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_co
rrupt_sig_fatal_chk.31022108
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2512695944
Short name T230
Test name
Test status
Simulation time 1556647842 ps
CPU time 19.78 seconds
Started May 28 01:08:21 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 210928 kb
Host smart-642a17bc-19f5-4e5b-98dc-562c87f57ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512695944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2512695944
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1256011024
Short name T37
Test name
Test status
Simulation time 9946259978 ps
CPU time 27.41 seconds
Started May 28 01:08:14 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 219104 kb
Host smart-d3eae959-96f1-40b5-b33f-5bd406ab63c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256011024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1256011024
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2620966201
Short name T13
Test name
Test status
Simulation time 38170302230 ps
CPU time 32.98 seconds
Started May 28 01:08:45 PM PDT 24
Finished May 28 01:09:20 PM PDT 24
Peak memory 214112 kb
Host smart-1b24e868-b325-4914-a394-a3b68eacd7d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620966201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2620966201
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3237015060
Short name T53
Test name
Test status
Simulation time 225780501467 ps
CPU time 9822.04 seconds
Started May 28 01:08:18 PM PDT 24
Finished May 28 03:52:04 PM PDT 24
Peak memory 235616 kb
Host smart-3325b230-4796-4773-87f1-5a5b016188d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237015060 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3237015060
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3100823722
Short name T180
Test name
Test status
Simulation time 55260592670 ps
CPU time 273.4 seconds
Started May 28 01:08:34 PM PDT 24
Finished May 28 01:13:10 PM PDT 24
Peak memory 214256 kb
Host smart-0152c150-8c2a-48c7-af34-bf28b30705ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100823722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3100823722
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1857543745
Short name T157
Test name
Test status
Simulation time 347465564 ps
CPU time 9.65 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:08:31 PM PDT 24
Peak memory 211500 kb
Host smart-a3846aa5-ead3-4fc5-9140-c717d3385052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857543745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1857543745
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3276958577
Short name T46
Test name
Test status
Simulation time 6609727894 ps
CPU time 15.39 seconds
Started May 28 01:08:07 PM PDT 24
Finished May 28 01:08:24 PM PDT 24
Peak memory 210940 kb
Host smart-1b407f1d-2d39-4019-a542-70f2e7e6bf49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276958577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3276958577
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2764491643
Short name T225
Test name
Test status
Simulation time 1392110612 ps
CPU time 10.65 seconds
Started May 28 01:08:20 PM PDT 24
Finished May 28 01:08:34 PM PDT 24
Peak memory 213176 kb
Host smart-7719773b-2f9b-466a-8ef3-8a6e9d7a5e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764491643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2764491643
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.71108426
Short name T349
Test name
Test status
Simulation time 958123218 ps
CPU time 11.39 seconds
Started May 28 01:08:06 PM PDT 24
Finished May 28 01:08:19 PM PDT 24
Peak memory 213612 kb
Host smart-4c4c4102-9c2d-4d83-8118-2c49a0c99cbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71108426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 15.rom_ctrl_stress_all.71108426
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.961671996
Short name T6
Test name
Test status
Simulation time 171745473 ps
CPU time 4.27 seconds
Started May 28 01:08:08 PM PDT 24
Finished May 28 01:08:14 PM PDT 24
Peak memory 210956 kb
Host smart-a66b35a0-5bec-432f-87be-5282a4bf7894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961671996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.961671996
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2755427375
Short name T169
Test name
Test status
Simulation time 181822215434 ps
CPU time 298.04 seconds
Started May 28 01:08:25 PM PDT 24
Finished May 28 01:13:25 PM PDT 24
Peak memory 236920 kb
Host smart-849120ae-091f-4d8e-a3f1-46a89aecca83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755427375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2755427375
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3933113578
Short name T355
Test name
Test status
Simulation time 257868930 ps
CPU time 9.36 seconds
Started May 28 01:08:06 PM PDT 24
Finished May 28 01:08:22 PM PDT 24
Peak memory 211584 kb
Host smart-01f19d74-5184-4667-95e7-c417da057b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933113578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3933113578
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2817591600
Short name T16
Test name
Test status
Simulation time 780087061 ps
CPU time 10.3 seconds
Started May 28 01:08:18 PM PDT 24
Finished May 28 01:08:30 PM PDT 24
Peak memory 210864 kb
Host smart-e99a2b7b-0766-4df8-9884-7266c642ec00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817591600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2817591600
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.703674318
Short name T69
Test name
Test status
Simulation time 15374549582 ps
CPU time 36.1 seconds
Started May 28 01:08:35 PM PDT 24
Finished May 28 01:09:13 PM PDT 24
Peak memory 213136 kb
Host smart-0e0503ed-5f1a-44a2-b8af-36234a117263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703674318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.703674318
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2304274088
Short name T360
Test name
Test status
Simulation time 88165012 ps
CPU time 4.27 seconds
Started May 28 01:08:18 PM PDT 24
Finished May 28 01:08:24 PM PDT 24
Peak memory 210928 kb
Host smart-23ce92bc-fe2c-4fc1-a8a6-edb8cd338822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304274088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2304274088
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.729531146
Short name T178
Test name
Test status
Simulation time 6209951394 ps
CPU time 11.26 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:08:36 PM PDT 24
Peak memory 210940 kb
Host smart-6758a986-06a9-4a84-81fb-96619310b115
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729531146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.729531146
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2854854717
Short name T66
Test name
Test status
Simulation time 14088504168 ps
CPU time 29.82 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:09:00 PM PDT 24
Peak memory 213476 kb
Host smart-00401dee-64c2-4d26-a8c9-b09a3d49bdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854854717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2854854717
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2736997090
Short name T67
Test name
Test status
Simulation time 3598644526 ps
CPU time 43.74 seconds
Started May 28 01:08:24 PM PDT 24
Finished May 28 01:09:10 PM PDT 24
Peak memory 219124 kb
Host smart-57fe1aea-3ca5-41a4-bcbe-25873b58835d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736997090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2736997090
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.786259512
Short name T202
Test name
Test status
Simulation time 7728125167 ps
CPU time 16.07 seconds
Started May 28 01:08:25 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 211012 kb
Host smart-7c38cfcb-59a2-4646-8b72-f807debaf65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786259512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.786259512
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3860755427
Short name T41
Test name
Test status
Simulation time 159127425664 ps
CPU time 351.69 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:14:14 PM PDT 24
Peak memory 225344 kb
Host smart-b1801671-9be5-44c9-b106-c769027e2d48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860755427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3860755427
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3209472860
Short name T256
Test name
Test status
Simulation time 347837525 ps
CPU time 11.73 seconds
Started May 28 01:08:14 PM PDT 24
Finished May 28 01:08:27 PM PDT 24
Peak memory 211544 kb
Host smart-a458d741-9b5d-452c-ae8d-adf8cee8822b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209472860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3209472860
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3194516903
Short name T346
Test name
Test status
Simulation time 223716870 ps
CPU time 5.83 seconds
Started May 28 01:08:20 PM PDT 24
Finished May 28 01:08:28 PM PDT 24
Peak memory 210836 kb
Host smart-bc0ac70c-26da-4a7c-b335-3fb448a592c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194516903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3194516903
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2952324700
Short name T341
Test name
Test status
Simulation time 16086956920 ps
CPU time 35.49 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:09:15 PM PDT 24
Peak memory 219104 kb
Host smart-5645f67f-df2e-446e-a77e-f358817486cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952324700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2952324700
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.827688297
Short name T213
Test name
Test status
Simulation time 1120988601 ps
CPU time 16.31 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:08:46 PM PDT 24
Peak memory 210852 kb
Host smart-a21cb7b8-6580-42d5-8233-59c5fa8bc349
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827688297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.827688297
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3126882543
Short name T238
Test name
Test status
Simulation time 27185624597 ps
CPU time 513.13 seconds
Started May 28 01:08:20 PM PDT 24
Finished May 28 01:16:56 PM PDT 24
Peak memory 232772 kb
Host smart-1c79795a-9cea-4c14-b9f4-169812cb8b25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126882543 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3126882543
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.789527312
Short name T344
Test name
Test status
Simulation time 2072964328 ps
CPU time 12.03 seconds
Started May 28 01:08:20 PM PDT 24
Finished May 28 01:08:35 PM PDT 24
Peak memory 210944 kb
Host smart-dfe7ad0d-5302-4b2e-9c91-693b9043944a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789527312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.789527312
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4225741391
Short name T332
Test name
Test status
Simulation time 41673629237 ps
CPU time 193.08 seconds
Started May 28 01:08:35 PM PDT 24
Finished May 28 01:11:50 PM PDT 24
Peak memory 236512 kb
Host smart-a405e841-09b0-49e6-8b4c-747468e55f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225741391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4225741391
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2847455446
Short name T19
Test name
Test status
Simulation time 723932718 ps
CPU time 9.5 seconds
Started May 28 01:08:20 PM PDT 24
Finished May 28 01:08:32 PM PDT 24
Peak memory 211452 kb
Host smart-56e14a74-5eca-4610-81d4-c4d7792e319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847455446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2847455446
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.343015882
Short name T47
Test name
Test status
Simulation time 1564770371 ps
CPU time 14.34 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:08:40 PM PDT 24
Peak memory 210884 kb
Host smart-90ed0263-1e75-462e-8c81-cd4d15356e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343015882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.343015882
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3085236940
Short name T333
Test name
Test status
Simulation time 4216059811 ps
CPU time 34.67 seconds
Started May 28 01:08:07 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 212704 kb
Host smart-c61efbd6-f626-4814-a932-49d0fa972bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085236940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3085236940
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.106768407
Short name T160
Test name
Test status
Simulation time 1543278965 ps
CPU time 21.35 seconds
Started May 28 01:08:12 PM PDT 24
Finished May 28 01:08:34 PM PDT 24
Peak memory 213892 kb
Host smart-07677baa-f52d-4d85-a66d-bf7eb9463523
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106768407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.106768407
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1645198562
Short name T4
Test name
Test status
Simulation time 152286913520 ps
CPU time 7285.63 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 03:09:48 PM PDT 24
Peak memory 235688 kb
Host smart-7bf7570e-05da-4bbf-964b-2eb114004ed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645198562 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1645198562
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3243519863
Short name T217
Test name
Test status
Simulation time 378067701 ps
CPU time 4.26 seconds
Started May 28 01:08:08 PM PDT 24
Finished May 28 01:08:14 PM PDT 24
Peak memory 210932 kb
Host smart-b5524031-12e0-4ce4-8ddc-d91b66bfc680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243519863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3243519863
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.319888259
Short name T323
Test name
Test status
Simulation time 54282953828 ps
CPU time 173.33 seconds
Started May 28 01:08:20 PM PDT 24
Finished May 28 01:11:16 PM PDT 24
Peak memory 224600 kb
Host smart-dcf27e7e-ca82-4630-b836-ecb9864d6520
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319888259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.319888259
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.437916643
Short name T240
Test name
Test status
Simulation time 168924888 ps
CPU time 9.58 seconds
Started May 28 01:07:59 PM PDT 24
Finished May 28 01:08:09 PM PDT 24
Peak memory 211664 kb
Host smart-adc543a4-d636-410c-9703-18486743a2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437916643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.437916643
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1771936139
Short name T250
Test name
Test status
Simulation time 374710344 ps
CPU time 5.62 seconds
Started May 28 01:08:43 PM PDT 24
Finished May 28 01:08:51 PM PDT 24
Peak memory 211212 kb
Host smart-ea8ec305-b2f7-474f-bec2-a725f585c5f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771936139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1771936139
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4025232910
Short name T280
Test name
Test status
Simulation time 721065461 ps
CPU time 9.99 seconds
Started May 28 01:07:57 PM PDT 24
Finished May 28 01:08:08 PM PDT 24
Peak memory 219052 kb
Host smart-d7892b32-5399-48e5-b257-b5d2829138c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025232910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4025232910
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4139857808
Short name T232
Test name
Test status
Simulation time 1941996602 ps
CPU time 16.01 seconds
Started May 28 01:08:15 PM PDT 24
Finished May 28 01:08:33 PM PDT 24
Peak memory 210920 kb
Host smart-3c9a135a-785c-45eb-ad67-1894d3dfbabe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139857808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4139857808
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2564264830
Short name T92
Test name
Test status
Simulation time 1211862594 ps
CPU time 63.64 seconds
Started May 28 01:08:12 PM PDT 24
Finished May 28 01:09:17 PM PDT 24
Peak memory 212128 kb
Host smart-2122e0ed-9425-45d7-be9e-88910f6a50ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564264830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2564264830
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4054337772
Short name T327
Test name
Test status
Simulation time 39955767738 ps
CPU time 31.62 seconds
Started May 28 01:08:17 PM PDT 24
Finished May 28 01:08:50 PM PDT 24
Peak memory 211904 kb
Host smart-425d2631-23b0-4f3a-8974-a172c9a7bee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054337772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4054337772
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1107234207
Short name T246
Test name
Test status
Simulation time 8095545963 ps
CPU time 16.84 seconds
Started May 28 01:08:08 PM PDT 24
Finished May 28 01:08:26 PM PDT 24
Peak memory 211040 kb
Host smart-8627c6eb-65d7-492a-b012-221bd803efb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1107234207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1107234207
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2545882724
Short name T242
Test name
Test status
Simulation time 369431764 ps
CPU time 10.32 seconds
Started May 28 01:08:36 PM PDT 24
Finished May 28 01:08:49 PM PDT 24
Peak memory 219080 kb
Host smart-e41ef486-2b74-4753-b803-ca0659d73bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545882724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2545882724
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2930263158
Short name T275
Test name
Test status
Simulation time 4110411890 ps
CPU time 29.8 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:09:05 PM PDT 24
Peak memory 219212 kb
Host smart-f6600613-55bb-4508-8cf7-c67c903adc56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930263158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2930263158
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3606131200
Short name T55
Test name
Test status
Simulation time 106484145866 ps
CPU time 1381 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:31:23 PM PDT 24
Peak memory 227680 kb
Host smart-d249d13b-f9ca-4942-a5f2-8f4fd738f383
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606131200 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3606131200
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2029540695
Short name T231
Test name
Test status
Simulation time 905542763 ps
CPU time 9.93 seconds
Started May 28 01:08:13 PM PDT 24
Finished May 28 01:08:25 PM PDT 24
Peak memory 210948 kb
Host smart-278f266b-4824-4ad7-90bc-b272f1b62b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029540695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2029540695
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2067667452
Short name T289
Test name
Test status
Simulation time 4251193756 ps
CPU time 136.64 seconds
Started May 28 01:08:08 PM PDT 24
Finished May 28 01:10:26 PM PDT 24
Peak memory 220132 kb
Host smart-0665bc90-7d9b-4f4f-ad6d-6af22d96f469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067667452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2067667452
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2260218787
Short name T152
Test name
Test status
Simulation time 4347767239 ps
CPU time 35.41 seconds
Started May 28 01:08:25 PM PDT 24
Finished May 28 01:09:02 PM PDT 24
Peak memory 211780 kb
Host smart-04b08e48-dadb-4528-9944-432f42dd7020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260218787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2260218787
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.906438028
Short name T368
Test name
Test status
Simulation time 12668356625 ps
CPU time 16.13 seconds
Started May 28 01:08:09 PM PDT 24
Finished May 28 01:08:27 PM PDT 24
Peak memory 210948 kb
Host smart-79f6033a-6ce7-46e3-b6fe-66fa175ea00c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906438028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.906438028
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.259675726
Short name T286
Test name
Test status
Simulation time 10932722732 ps
CPU time 25.45 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:08:51 PM PDT 24
Peak memory 213808 kb
Host smart-a2f69ff8-6b3e-40ce-894e-fcf2238e6e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259675726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.259675726
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2215009086
Short name T364
Test name
Test status
Simulation time 26262464271 ps
CPU time 69.56 seconds
Started May 28 01:08:18 PM PDT 24
Finished May 28 01:09:29 PM PDT 24
Peak memory 219212 kb
Host smart-4950985e-28ba-4a6b-91ee-640d4c40d103
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215009086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2215009086
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4254267967
Short name T241
Test name
Test status
Simulation time 3028071368 ps
CPU time 13.22 seconds
Started May 28 01:08:44 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 211052 kb
Host smart-353c00ec-9f4a-4649-a645-5cc46746fa29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254267967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4254267967
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2860705653
Short name T343
Test name
Test status
Simulation time 41129859670 ps
CPU time 146.77 seconds
Started May 28 01:08:34 PM PDT 24
Finished May 28 01:11:04 PM PDT 24
Peak memory 212224 kb
Host smart-47f09a97-ced8-4c67-b3be-bdf6ea62f508
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860705653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2860705653
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2157554932
Short name T170
Test name
Test status
Simulation time 2140740573 ps
CPU time 22.16 seconds
Started May 28 01:08:13 PM PDT 24
Finished May 28 01:08:37 PM PDT 24
Peak memory 210896 kb
Host smart-5f356f61-d8bd-442b-bb9c-e15019600cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157554932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2157554932
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1279602375
Short name T50
Test name
Test status
Simulation time 14349007122 ps
CPU time 15.8 seconds
Started May 28 01:08:27 PM PDT 24
Finished May 28 01:08:44 PM PDT 24
Peak memory 210964 kb
Host smart-024cf748-8ad5-44d2-ac71-59426bca48ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279602375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1279602375
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1138783494
Short name T186
Test name
Test status
Simulation time 3542936998 ps
CPU time 20.63 seconds
Started May 28 01:08:35 PM PDT 24
Finished May 28 01:08:58 PM PDT 24
Peak memory 212912 kb
Host smart-b8831671-b8bb-4257-ac5e-909e6014e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138783494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1138783494
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2836636535
Short name T36
Test name
Test status
Simulation time 10601605996 ps
CPU time 88.41 seconds
Started May 28 01:08:35 PM PDT 24
Finished May 28 01:10:06 PM PDT 24
Peak memory 217408 kb
Host smart-0d1bc79c-f3a7-4b2a-9441-5763eaadcc02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836636535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2836636535
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.89459113
Short name T267
Test name
Test status
Simulation time 2443890814 ps
CPU time 9.56 seconds
Started May 28 01:08:31 PM PDT 24
Finished May 28 01:08:42 PM PDT 24
Peak memory 211012 kb
Host smart-63a696f9-e0d4-41d7-b7e4-a12a731b3c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89459113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.89459113
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.473985641
Short name T229
Test name
Test status
Simulation time 32880501341 ps
CPU time 294.27 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:13:29 PM PDT 24
Peak memory 234556 kb
Host smart-d11719a6-4e30-448a-8308-45b66896bc74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473985641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.473985641
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.501598208
Short name T93
Test name
Test status
Simulation time 3791466992 ps
CPU time 30.68 seconds
Started May 28 01:08:27 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 211728 kb
Host smart-0653b8f0-5afd-4588-8227-fc524195cbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501598208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.501598208
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3333786716
Short name T314
Test name
Test status
Simulation time 11638082261 ps
CPU time 16.5 seconds
Started May 28 01:08:15 PM PDT 24
Finished May 28 01:08:33 PM PDT 24
Peak memory 210940 kb
Host smart-81f29a00-d8a5-4e25-9214-124a37731a94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333786716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3333786716
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.646696278
Short name T224
Test name
Test status
Simulation time 1990632365 ps
CPU time 16.6 seconds
Started May 28 01:08:11 PM PDT 24
Finished May 28 01:08:29 PM PDT 24
Peak memory 212860 kb
Host smart-96978fb2-941e-4367-8a19-7b8e92be0b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646696278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.646696278
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1082180504
Short name T173
Test name
Test status
Simulation time 8609843088 ps
CPU time 31.91 seconds
Started May 28 01:08:25 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 214172 kb
Host smart-daa5ecca-5cbf-4689-9649-0b27c593951a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082180504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1082180504
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1497503334
Short name T156
Test name
Test status
Simulation time 111700514 ps
CPU time 4.18 seconds
Started May 28 01:08:13 PM PDT 24
Finished May 28 01:08:18 PM PDT 24
Peak memory 210932 kb
Host smart-c8cb44b5-31fb-4587-85a2-133ed6c74d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497503334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1497503334
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.577686535
Short name T43
Test name
Test status
Simulation time 13509375961 ps
CPU time 216.65 seconds
Started May 28 01:08:31 PM PDT 24
Finished May 28 01:12:10 PM PDT 24
Peak memory 213388 kb
Host smart-f67fae06-297e-483d-924f-233251b0ad50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577686535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.577686535
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2301443599
Short name T145
Test name
Test status
Simulation time 471004086 ps
CPU time 11.21 seconds
Started May 28 01:08:30 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 211664 kb
Host smart-48c5d492-d6f3-42ee-b5a3-e9a1cb12452b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301443599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2301443599
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2212491780
Short name T279
Test name
Test status
Simulation time 380998108 ps
CPU time 8.21 seconds
Started May 28 01:08:15 PM PDT 24
Finished May 28 01:08:25 PM PDT 24
Peak memory 210876 kb
Host smart-c7bd8e9d-15ff-49c4-86f4-9e616aac12e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212491780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2212491780
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1629234701
Short name T42
Test name
Test status
Simulation time 1732153299 ps
CPU time 21.96 seconds
Started May 28 01:08:26 PM PDT 24
Finished May 28 01:08:50 PM PDT 24
Peak memory 219084 kb
Host smart-0101dd3b-108c-45de-8869-5478a1c89cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629234701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1629234701
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.523092885
Short name T293
Test name
Test status
Simulation time 1839666603 ps
CPU time 27.78 seconds
Started May 28 01:08:17 PM PDT 24
Finished May 28 01:08:46 PM PDT 24
Peak memory 215936 kb
Host smart-8d5b1f60-52cd-426e-be16-c399306da5b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523092885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.523092885
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2400142115
Short name T17
Test name
Test status
Simulation time 46096896935 ps
CPU time 1732.18 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:37:28 PM PDT 24
Peak memory 235600 kb
Host smart-bc283c1e-3628-4405-8d44-427dca487363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400142115 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2400142115
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.22283036
Short name T64
Test name
Test status
Simulation time 171484789 ps
CPU time 4.38 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:08:30 PM PDT 24
Peak memory 210928 kb
Host smart-2601c7d3-2f32-49b3-b57c-078f38c116c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.22283036
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1017636870
Short name T49
Test name
Test status
Simulation time 344728247830 ps
CPU time 156.75 seconds
Started May 28 01:08:24 PM PDT 24
Finished May 28 01:11:03 PM PDT 24
Peak memory 227396 kb
Host smart-7b978fdd-5876-46e6-be06-86b008cfece2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017636870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1017636870
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1308476704
Short name T311
Test name
Test status
Simulation time 24106758379 ps
CPU time 29.75 seconds
Started May 28 01:08:26 PM PDT 24
Finished May 28 01:08:57 PM PDT 24
Peak memory 211968 kb
Host smart-1bc24f8b-0605-4de2-871e-ebb0bfd81ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308476704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1308476704
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3905560164
Short name T319
Test name
Test status
Simulation time 100840067 ps
CPU time 5.84 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:08:35 PM PDT 24
Peak memory 210900 kb
Host smart-efdec522-362f-4a02-9c1e-3a0fa9998a5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905560164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3905560164
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.588686194
Short name T278
Test name
Test status
Simulation time 8544218854 ps
CPU time 24.31 seconds
Started May 28 01:08:27 PM PDT 24
Finished May 28 01:08:53 PM PDT 24
Peak memory 219112 kb
Host smart-1656a4db-8cdf-4952-a7ec-58efb4c2aa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588686194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.588686194
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2872899356
Short name T212
Test name
Test status
Simulation time 4171393737 ps
CPU time 28.93 seconds
Started May 28 01:08:17 PM PDT 24
Finished May 28 01:08:48 PM PDT 24
Peak memory 219120 kb
Host smart-59bc5bce-6f31-4817-8065-54b5aa55a1a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872899356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2872899356
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2589423196
Short name T33
Test name
Test status
Simulation time 2068962048 ps
CPU time 6.39 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:08:36 PM PDT 24
Peak memory 210932 kb
Host smart-300b9e94-866e-40d0-a4f9-a3ea85c8f429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589423196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2589423196
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1211594106
Short name T247
Test name
Test status
Simulation time 2188748465 ps
CPU time 124.87 seconds
Started May 28 01:08:13 PM PDT 24
Finished May 28 01:10:20 PM PDT 24
Peak memory 228796 kb
Host smart-25bd1880-e2bf-4437-9504-4e7d4e230dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211594106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1211594106
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3826178706
Short name T312
Test name
Test status
Simulation time 11600505811 ps
CPU time 22.72 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:08:58 PM PDT 24
Peak memory 211960 kb
Host smart-d4b4aca8-76a7-4cf2-86db-c06d94e9ae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826178706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3826178706
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.920091339
Short name T130
Test name
Test status
Simulation time 1729379786 ps
CPU time 15.81 seconds
Started May 28 01:08:41 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 210884 kb
Host smart-419c4deb-610b-4ff9-b5c7-49c297d598b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920091339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.920091339
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2783127012
Short name T205
Test name
Test status
Simulation time 11348847010 ps
CPU time 32.47 seconds
Started May 28 01:08:25 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 214132 kb
Host smart-3d79a565-e50c-4155-bb62-9778d0483e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783127012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2783127012
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.388377127
Short name T235
Test name
Test status
Simulation time 3982801538 ps
CPU time 14.73 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:08:44 PM PDT 24
Peak memory 210988 kb
Host smart-b960ba62-cd91-4e8c-9701-8680f18cc08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388377127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.388377127
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1112274958
Short name T27
Test name
Test status
Simulation time 41112287940 ps
CPU time 482.84 seconds
Started May 28 01:08:38 PM PDT 24
Finished May 28 01:16:43 PM PDT 24
Peak memory 224708 kb
Host smart-1b304544-13ab-4fa1-a831-ffa38456afb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112274958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1112274958
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2941134484
Short name T337
Test name
Test status
Simulation time 5715994185 ps
CPU time 34 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:08:56 PM PDT 24
Peak memory 212360 kb
Host smart-7a3879d9-978f-45ce-b001-7e1705be6063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941134484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2941134484
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2738201140
Short name T257
Test name
Test status
Simulation time 513353904 ps
CPU time 7.31 seconds
Started May 28 01:08:34 PM PDT 24
Finished May 28 01:08:44 PM PDT 24
Peak memory 210884 kb
Host smart-3952b3bc-b62c-4212-a363-b69ebee6fa32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738201140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2738201140
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.232766125
Short name T94
Test name
Test status
Simulation time 8157510565 ps
CPU time 42.28 seconds
Started May 28 01:08:24 PM PDT 24
Finished May 28 01:09:09 PM PDT 24
Peak memory 219108 kb
Host smart-5ef7c9ca-b71d-4941-9647-586a815669de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232766125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.232766125
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2082031802
Short name T154
Test name
Test status
Simulation time 2055022309 ps
CPU time 23.78 seconds
Started May 28 01:08:14 PM PDT 24
Finished May 28 01:08:39 PM PDT 24
Peak memory 219048 kb
Host smart-c7853699-9df5-41bd-85e9-5fdd9950a272
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082031802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2082031802
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3722100018
Short name T248
Test name
Test status
Simulation time 1881663811 ps
CPU time 15.42 seconds
Started May 28 01:08:14 PM PDT 24
Finished May 28 01:08:32 PM PDT 24
Peak memory 210920 kb
Host smart-24818d44-b17a-433a-acab-17635bc4425b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722100018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3722100018
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1380997852
Short name T148
Test name
Test status
Simulation time 5469002249 ps
CPU time 82.64 seconds
Started May 28 01:08:20 PM PDT 24
Finished May 28 01:09:45 PM PDT 24
Peak memory 236164 kb
Host smart-bc44523d-1306-4ce5-a3a4-be3169c641e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380997852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1380997852
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.733278173
Short name T318
Test name
Test status
Simulation time 17123104862 ps
CPU time 34.34 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:08:56 PM PDT 24
Peak memory 212148 kb
Host smart-055ba377-6d5c-4854-a585-4a03f0081837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733278173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.733278173
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3923429134
Short name T139
Test name
Test status
Simulation time 542251349 ps
CPU time 5.3 seconds
Started May 28 01:08:20 PM PDT 24
Finished May 28 01:08:28 PM PDT 24
Peak memory 210876 kb
Host smart-9c03f124-d08b-4c26-b43e-79794be41d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923429134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3923429134
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.481326549
Short name T228
Test name
Test status
Simulation time 1019988897 ps
CPU time 17.08 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 212548 kb
Host smart-90241dbe-111c-47c2-a6f8-d6b6c7b7b306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481326549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.481326549
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2784523345
Short name T137
Test name
Test status
Simulation time 1549199606 ps
CPU time 15.04 seconds
Started May 28 01:08:36 PM PDT 24
Finished May 28 01:08:54 PM PDT 24
Peak memory 219048 kb
Host smart-a746aaa6-c106-47fd-b4dd-1864f97c738e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784523345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2784523345
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2019894966
Short name T239
Test name
Test status
Simulation time 415753887 ps
CPU time 6.7 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:08:41 PM PDT 24
Peak memory 210868 kb
Host smart-b2de52fc-a870-4835-84d4-9da6954aad20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019894966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2019894966
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1789813537
Short name T196
Test name
Test status
Simulation time 54200112247 ps
CPU time 603.13 seconds
Started May 28 01:08:35 PM PDT 24
Finished May 28 01:18:41 PM PDT 24
Peak memory 224280 kb
Host smart-bcb3cf28-57c3-4664-bb71-c972e4752bbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789813537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1789813537
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.359267913
Short name T5
Test name
Test status
Simulation time 818368774 ps
CPU time 15.63 seconds
Started May 28 01:08:29 PM PDT 24
Finished May 28 01:08:47 PM PDT 24
Peak memory 211576 kb
Host smart-6657f8b7-1d13-49ff-a179-1ec9d425829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359267913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.359267913
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.894548496
Short name T301
Test name
Test status
Simulation time 2094142825 ps
CPU time 18.18 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:08:53 PM PDT 24
Peak memory 211020 kb
Host smart-66d97d8f-ec9c-4e99-ac5f-5ddb4b4f55b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894548496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.894548496
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1665990021
Short name T133
Test name
Test status
Simulation time 30035623013 ps
CPU time 28.37 seconds
Started May 28 01:08:24 PM PDT 24
Finished May 28 01:08:55 PM PDT 24
Peak memory 213784 kb
Host smart-792fde8b-a1a3-4f89-b616-bab7f228dad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665990021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1665990021
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3023661309
Short name T271
Test name
Test status
Simulation time 1551701601 ps
CPU time 33.24 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:09:03 PM PDT 24
Peak memory 215068 kb
Host smart-4d3e61cf-2d12-4449-bea6-3240b77c7095
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023661309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3023661309
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2888449975
Short name T251
Test name
Test status
Simulation time 1241543708 ps
CPU time 12.08 seconds
Started May 28 01:08:10 PM PDT 24
Finished May 28 01:08:23 PM PDT 24
Peak memory 210932 kb
Host smart-0563302b-1df0-4111-adbf-61d349e5e92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888449975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2888449975
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3388696347
Short name T208
Test name
Test status
Simulation time 136325830649 ps
CPU time 324.86 seconds
Started May 28 01:08:10 PM PDT 24
Finished May 28 01:13:36 PM PDT 24
Peak memory 238636 kb
Host smart-9d05f504-f38b-4846-b694-9ac0da16a7dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388696347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3388696347
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1456410789
Short name T183
Test name
Test status
Simulation time 6461672042 ps
CPU time 27.67 seconds
Started May 28 01:08:04 PM PDT 24
Finished May 28 01:08:33 PM PDT 24
Peak memory 211104 kb
Host smart-807831bb-c676-4009-a74d-2e43b98f878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456410789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1456410789
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.256544456
Short name T124
Test name
Test status
Simulation time 4940255642 ps
CPU time 12.51 seconds
Started May 28 01:08:04 PM PDT 24
Finished May 28 01:08:18 PM PDT 24
Peak memory 211044 kb
Host smart-97d7556c-29be-4bb6-b34d-af1c62a24221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256544456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.256544456
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3611641014
Short name T35
Test name
Test status
Simulation time 543151756 ps
CPU time 51.71 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:09:13 PM PDT 24
Peak memory 233144 kb
Host smart-7b1c01ca-728f-47a7-8bca-9ef3149bc335
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611641014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3611641014
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3441751520
Short name T316
Test name
Test status
Simulation time 2562190102 ps
CPU time 13.96 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:08:39 PM PDT 24
Peak memory 219216 kb
Host smart-3bed0a99-45d9-44c1-81b3-f935ec68ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441751520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3441751520
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1662309400
Short name T261
Test name
Test status
Simulation time 9047849688 ps
CPU time 60.76 seconds
Started May 28 01:08:05 PM PDT 24
Finished May 28 01:09:07 PM PDT 24
Peak memory 219076 kb
Host smart-549fc923-b336-439f-9f09-45004eab84f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662309400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1662309400
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3847525050
Short name T336
Test name
Test status
Simulation time 86584760 ps
CPU time 4.26 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:08:38 PM PDT 24
Peak memory 210932 kb
Host smart-ead668d3-ab42-463e-953c-eaf4d2253819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847525050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3847525050
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2401398592
Short name T244
Test name
Test status
Simulation time 34591532517 ps
CPU time 353.27 seconds
Started May 28 01:08:34 PM PDT 24
Finished May 28 01:14:30 PM PDT 24
Peak memory 233940 kb
Host smart-4a9cc41c-1f7d-4c32-aae3-aeed9abd71d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401398592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2401398592
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2632519373
Short name T315
Test name
Test status
Simulation time 327597607 ps
CPU time 9.48 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:08:45 PM PDT 24
Peak memory 211520 kb
Host smart-f20b8d54-3387-4ed5-84fc-572fd8cc114d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632519373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2632519373
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2539231239
Short name T165
Test name
Test status
Simulation time 1668380070 ps
CPU time 15.69 seconds
Started May 28 01:08:26 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 210980 kb
Host smart-d9fa37f6-ce5c-4324-9a1b-b7fa3d3d7b58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539231239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2539231239
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1093310686
Short name T192
Test name
Test status
Simulation time 61230137012 ps
CPU time 32.54 seconds
Started May 28 01:08:22 PM PDT 24
Finished May 28 01:09:02 PM PDT 24
Peak memory 213968 kb
Host smart-be909dff-1c69-4448-9c4c-4e7e1360440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093310686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1093310686
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1205873627
Short name T141
Test name
Test status
Simulation time 34884836234 ps
CPU time 25.63 seconds
Started May 28 01:08:43 PM PDT 24
Finished May 28 01:09:10 PM PDT 24
Peak memory 219112 kb
Host smart-27890fa5-9aa1-4629-822b-9e4bdc8a4529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205873627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1205873627
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3341377984
Short name T56
Test name
Test status
Simulation time 7817814086 ps
CPU time 303.02 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:13:43 PM PDT 24
Peak memory 222696 kb
Host smart-2f434db9-ade2-4e80-b5fa-982340859e18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341377984 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3341377984
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3371558312
Short name T185
Test name
Test status
Simulation time 2905526145 ps
CPU time 12.69 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:08:53 PM PDT 24
Peak memory 210960 kb
Host smart-46f7dc17-3812-47c9-9c27-a6fa0629eec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371558312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3371558312
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.734596034
Short name T328
Test name
Test status
Simulation time 4322835824 ps
CPU time 142.73 seconds
Started May 28 01:08:26 PM PDT 24
Finished May 28 01:10:51 PM PDT 24
Peak memory 229440 kb
Host smart-0a085a1e-4c98-49dd-ab0c-4c257ea10b8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734596034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.734596034
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1435776484
Short name T10
Test name
Test status
Simulation time 6838646029 ps
CPU time 19.67 seconds
Started May 28 01:08:36 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 211244 kb
Host smart-5fe20e5b-0673-4531-9bde-6642ecc94e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435776484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1435776484
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1267643720
Short name T259
Test name
Test status
Simulation time 4538073406 ps
CPU time 11.29 seconds
Started May 28 01:08:50 PM PDT 24
Finished May 28 01:09:02 PM PDT 24
Peak memory 210960 kb
Host smart-e0dcf87f-bfa2-46d4-aad2-d103a6735d50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267643720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1267643720
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2629305984
Short name T272
Test name
Test status
Simulation time 2068668807 ps
CPU time 22.29 seconds
Started May 28 01:08:29 PM PDT 24
Finished May 28 01:08:53 PM PDT 24
Peak memory 212880 kb
Host smart-aa6d3322-52f4-4060-b8e2-6113d7a6ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629305984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2629305984
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.476761163
Short name T317
Test name
Test status
Simulation time 2175794319 ps
CPU time 28.27 seconds
Started May 28 01:08:25 PM PDT 24
Finished May 28 01:08:56 PM PDT 24
Peak memory 215128 kb
Host smart-c05b2fea-55b8-4562-9e88-ebf2c16cf955
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476761163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.476761163
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.12595215
Short name T54
Test name
Test status
Simulation time 18066574052 ps
CPU time 6508.45 seconds
Started May 28 01:08:34 PM PDT 24
Finished May 28 02:57:06 PM PDT 24
Peak memory 231504 kb
Host smart-89869744-43ca-4f09-9ec7-f469d7bf9b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12595215 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.12595215
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3877088257
Short name T175
Test name
Test status
Simulation time 5228565123 ps
CPU time 9.6 seconds
Started May 28 01:08:31 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 210988 kb
Host smart-8c6d334c-af9b-45af-8698-d2d6151be659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877088257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3877088257
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2067851238
Short name T367
Test name
Test status
Simulation time 58313397969 ps
CPU time 315.13 seconds
Started May 28 01:08:31 PM PDT 24
Finished May 28 01:13:48 PM PDT 24
Peak memory 232328 kb
Host smart-5c7a4cca-ce83-4e84-96db-13090d6a4c1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067851238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2067851238
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2769019123
Short name T295
Test name
Test status
Simulation time 168399410 ps
CPU time 9.58 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:08:50 PM PDT 24
Peak memory 211576 kb
Host smart-1a983530-1574-4308-98cc-5f0126c74ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769019123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2769019123
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2309032750
Short name T201
Test name
Test status
Simulation time 2028425738 ps
CPU time 9.02 seconds
Started May 28 01:08:34 PM PDT 24
Finished May 28 01:08:46 PM PDT 24
Peak memory 210876 kb
Host smart-00dddf0f-978a-4bc1-a483-2a63cf315c36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309032750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2309032750
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1894688239
Short name T258
Test name
Test status
Simulation time 21413326118 ps
CPU time 17.72 seconds
Started May 28 01:08:38 PM PDT 24
Finished May 28 01:08:58 PM PDT 24
Peak memory 219128 kb
Host smart-d960af31-f8fa-40de-9daf-f45fd8be8baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894688239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1894688239
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3754510906
Short name T12
Test name
Test status
Simulation time 1239804248 ps
CPU time 27.72 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:09:02 PM PDT 24
Peak memory 215352 kb
Host smart-66d12e4a-4aaf-424a-9461-d8e95ef200c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754510906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3754510906
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3199837250
Short name T161
Test name
Test status
Simulation time 132231219 ps
CPU time 4.2 seconds
Started May 28 01:08:35 PM PDT 24
Finished May 28 01:08:42 PM PDT 24
Peak memory 210940 kb
Host smart-025d4626-1f6f-4ff4-80cb-07c5288cd2f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199837250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3199837250
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3908268257
Short name T365
Test name
Test status
Simulation time 42246084883 ps
CPU time 273.45 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:13:07 PM PDT 24
Peak memory 236796 kb
Host smart-326337b0-9362-423a-9ea4-0070619141ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908268257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3908268257
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.898809146
Short name T234
Test name
Test status
Simulation time 6496699408 ps
CPU time 28.52 seconds
Started May 28 01:08:35 PM PDT 24
Finished May 28 01:09:06 PM PDT 24
Peak memory 211916 kb
Host smart-d5bc4735-ccbb-46e9-b1eb-41d97955a7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898809146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.898809146
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3870077816
Short name T252
Test name
Test status
Simulation time 95204060 ps
CPU time 5.6 seconds
Started May 28 01:08:22 PM PDT 24
Finished May 28 01:08:30 PM PDT 24
Peak memory 210900 kb
Host smart-d3acb21d-a52b-483b-8bdf-4009fab0fa49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870077816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3870077816
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1535905266
Short name T294
Test name
Test status
Simulation time 20567217061 ps
CPU time 35.29 seconds
Started May 28 01:08:29 PM PDT 24
Finished May 28 01:09:07 PM PDT 24
Peak memory 214192 kb
Host smart-5b78e262-4b73-40a3-9a09-8dfce262873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535905266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1535905266
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2307947916
Short name T309
Test name
Test status
Simulation time 6340955787 ps
CPU time 33.2 seconds
Started May 28 01:08:31 PM PDT 24
Finished May 28 01:09:05 PM PDT 24
Peak memory 219212 kb
Host smart-ac0477da-ccb6-4348-9619-25aa22a777ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307947916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2307947916
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2239535736
Short name T297
Test name
Test status
Simulation time 981215054 ps
CPU time 10.65 seconds
Started May 28 01:08:36 PM PDT 24
Finished May 28 01:08:49 PM PDT 24
Peak memory 210948 kb
Host smart-ce89ee5d-fac8-4178-ab63-399e2962426f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239535736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2239535736
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2425990379
Short name T277
Test name
Test status
Simulation time 346851695730 ps
CPU time 444.59 seconds
Started May 28 01:08:36 PM PDT 24
Finished May 28 01:16:03 PM PDT 24
Peak memory 234572 kb
Host smart-b3020eca-9886-4f78-b4b6-7b0ef124c1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425990379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2425990379
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1811668461
Short name T128
Test name
Test status
Simulation time 4442466282 ps
CPU time 23.6 seconds
Started May 28 01:08:34 PM PDT 24
Finished May 28 01:09:00 PM PDT 24
Peak memory 211788 kb
Host smart-5aecbbc8-78c3-411a-8a30-98e0872c8575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811668461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1811668461
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2533649337
Short name T153
Test name
Test status
Simulation time 2975598316 ps
CPU time 10.67 seconds
Started May 28 01:08:42 PM PDT 24
Finished May 28 01:08:55 PM PDT 24
Peak memory 210940 kb
Host smart-3d2ed1c0-eeec-440b-8adc-58f4bd811584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533649337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2533649337
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.149847234
Short name T163
Test name
Test status
Simulation time 181937384 ps
CPU time 10.18 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:08:50 PM PDT 24
Peak memory 219052 kb
Host smart-6aee6eaa-092c-43ca-9f2e-8310bbf3065c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149847234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.149847234
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4260740019
Short name T122
Test name
Test status
Simulation time 939366146 ps
CPU time 13.87 seconds
Started May 28 01:08:39 PM PDT 24
Finished May 28 01:08:56 PM PDT 24
Peak memory 213252 kb
Host smart-c7c84db3-8a78-44f1-b431-d902030eca44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260740019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4260740019
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.227133892
Short name T268
Test name
Test status
Simulation time 89142408 ps
CPU time 4.41 seconds
Started May 28 01:08:44 PM PDT 24
Finished May 28 01:08:51 PM PDT 24
Peak memory 211036 kb
Host smart-aed528e1-8ca7-41c1-85ea-49bb626d8012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227133892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.227133892
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2120057565
Short name T296
Test name
Test status
Simulation time 2109020066 ps
CPU time 129.69 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:10:43 PM PDT 24
Peak memory 237328 kb
Host smart-1f56eb4f-5fa7-4f8d-9a8d-5ba274de85f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120057565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2120057565
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4111331164
Short name T24
Test name
Test status
Simulation time 3497000302 ps
CPU time 29.79 seconds
Started May 28 01:08:25 PM PDT 24
Finished May 28 01:08:57 PM PDT 24
Peak memory 211476 kb
Host smart-870d8ca3-7b8b-444b-8ee9-77429ea179e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111331164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4111331164
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4252509815
Short name T338
Test name
Test status
Simulation time 1116274733 ps
CPU time 12.69 seconds
Started May 28 01:08:28 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 210972 kb
Host smart-d2edcb7e-47fb-415c-b39f-afc8293fe8a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252509815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4252509815
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.211742932
Short name T330
Test name
Test status
Simulation time 12895906997 ps
CPU time 29.01 seconds
Started May 28 01:08:38 PM PDT 24
Finished May 28 01:09:10 PM PDT 24
Peak memory 213956 kb
Host smart-c7872237-0b32-45b5-93da-7057429b5af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211742932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.211742932
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.886730343
Short name T197
Test name
Test status
Simulation time 49597547907 ps
CPU time 112.57 seconds
Started May 28 01:08:30 PM PDT 24
Finished May 28 01:10:24 PM PDT 24
Peak memory 219132 kb
Host smart-98364cca-300d-4d4e-b78a-ebcd974a7aab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886730343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.886730343
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2717416088
Short name T57
Test name
Test status
Simulation time 220199221190 ps
CPU time 2044.1 seconds
Started May 28 01:08:30 PM PDT 24
Finished May 28 01:42:36 PM PDT 24
Peak memory 237364 kb
Host smart-0ad13fbe-c44f-4894-a286-d3050a4090cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717416088 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2717416088
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1771480210
Short name T187
Test name
Test status
Simulation time 212795828 ps
CPU time 5.89 seconds
Started May 28 01:08:29 PM PDT 24
Finished May 28 01:08:37 PM PDT 24
Peak memory 210932 kb
Host smart-c55dc182-1ebd-4dcd-85e5-c4422104e44f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771480210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1771480210
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1897590657
Short name T26
Test name
Test status
Simulation time 7430254197 ps
CPU time 201.67 seconds
Started May 28 01:08:22 PM PDT 24
Finished May 28 01:11:46 PM PDT 24
Peak memory 237444 kb
Host smart-2b4e2c31-7948-4de5-84d3-eebda8a9a412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897590657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1897590657
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.965810965
Short name T97
Test name
Test status
Simulation time 1791370394 ps
CPU time 12.49 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:08:47 PM PDT 24
Peak memory 211472 kb
Host smart-edbecde8-6809-43a6-98c7-ebc2d3466d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965810965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.965810965
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1536316357
Short name T125
Test name
Test status
Simulation time 760078048 ps
CPU time 10.52 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:08:45 PM PDT 24
Peak memory 210840 kb
Host smart-bf04acfb-ed5b-4a14-8603-465cc8bea1dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536316357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1536316357
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.342358886
Short name T126
Test name
Test status
Simulation time 713641540 ps
CPU time 10.55 seconds
Started May 28 01:08:29 PM PDT 24
Finished May 28 01:08:41 PM PDT 24
Peak memory 219068 kb
Host smart-dce83b77-0a69-47aa-9a9d-193f81f37143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342358886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.342358886
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3078451028
Short name T162
Test name
Test status
Simulation time 19758101434 ps
CPU time 58.47 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:09:24 PM PDT 24
Peak memory 216240 kb
Host smart-5ce9e60a-51c0-41a0-b5e0-fbe3451e80e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078451028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3078451028
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3531503329
Short name T322
Test name
Test status
Simulation time 155780248 ps
CPU time 4.25 seconds
Started May 28 01:08:39 PM PDT 24
Finished May 28 01:08:46 PM PDT 24
Peak memory 210948 kb
Host smart-693c9dcf-01fc-4e58-b5bc-e6aeadd5c9ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531503329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3531503329
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2922812418
Short name T354
Test name
Test status
Simulation time 1585623692 ps
CPU time 57.07 seconds
Started May 28 01:08:47 PM PDT 24
Finished May 28 01:09:46 PM PDT 24
Peak memory 236004 kb
Host smart-1d08082c-2eb9-4022-bee1-9945e83d0a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922812418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2922812418
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3153656350
Short name T326
Test name
Test status
Simulation time 3074706320 ps
CPU time 18.84 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 211564 kb
Host smart-6b569991-1db0-4795-b0e4-734c155338b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153656350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3153656350
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1747728946
Short name T308
Test name
Test status
Simulation time 32971771297 ps
CPU time 16.33 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:08:52 PM PDT 24
Peak memory 210940 kb
Host smart-fe6f5964-3733-4266-b779-79e43ff9f069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747728946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1747728946
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2613312032
Short name T194
Test name
Test status
Simulation time 1652558557 ps
CPU time 20.8 seconds
Started May 28 01:08:35 PM PDT 24
Finished May 28 01:08:58 PM PDT 24
Peak memory 219048 kb
Host smart-97578e45-b9fd-413f-a374-e7024936414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613312032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2613312032
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.364779783
Short name T90
Test name
Test status
Simulation time 1765205445 ps
CPU time 35.09 seconds
Started May 28 01:08:31 PM PDT 24
Finished May 28 01:09:08 PM PDT 24
Peak memory 214884 kb
Host smart-9695025b-552c-4d0c-8811-6b276612d253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364779783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.364779783
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2585947057
Short name T352
Test name
Test status
Simulation time 49253104151 ps
CPU time 3944.58 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 02:14:21 PM PDT 24
Peak memory 235584 kb
Host smart-e3f22470-24bd-4a8a-8ae3-92a1f62b34f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585947057 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2585947057
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1603198455
Short name T218
Test name
Test status
Simulation time 7384537619 ps
CPU time 15.69 seconds
Started May 28 01:08:36 PM PDT 24
Finished May 28 01:08:55 PM PDT 24
Peak memory 210980 kb
Host smart-4787ed04-7f2c-435c-906f-bfe9daf4502e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603198455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1603198455
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1712914718
Short name T193
Test name
Test status
Simulation time 3626995302 ps
CPU time 103.02 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:10:19 PM PDT 24
Peak memory 218292 kb
Host smart-c9f424c9-d0f7-4dc1-b2c8-0d02551d5a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712914718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1712914718
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2591126085
Short name T142
Test name
Test status
Simulation time 5420235207 ps
CPU time 25.11 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:09:01 PM PDT 24
Peak memory 212980 kb
Host smart-d88456dd-a74a-4ec2-bc3d-45dc4348c4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591126085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2591126085
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1948036226
Short name T298
Test name
Test status
Simulation time 452122959 ps
CPU time 8.18 seconds
Started May 28 01:08:38 PM PDT 24
Finished May 28 01:08:49 PM PDT 24
Peak memory 210876 kb
Host smart-5ed8fa03-c085-4c5d-98b0-c41298215d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948036226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1948036226
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1211521865
Short name T353
Test name
Test status
Simulation time 1740737794 ps
CPU time 21.24 seconds
Started May 28 01:08:31 PM PDT 24
Finished May 28 01:08:54 PM PDT 24
Peak memory 219044 kb
Host smart-4e586899-253a-4687-956b-524f6dad0992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211521865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1211521865
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.217639285
Short name T207
Test name
Test status
Simulation time 5754975372 ps
CPU time 30 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:09:05 PM PDT 24
Peak memory 219112 kb
Host smart-3e0b2413-96ec-40dd-88da-d3eb7042d8b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217639285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.217639285
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3012217195
Short name T284
Test name
Test status
Simulation time 1879520572 ps
CPU time 7.14 seconds
Started May 28 01:08:40 PM PDT 24
Finished May 28 01:08:50 PM PDT 24
Peak memory 210944 kb
Host smart-9745c46d-7978-4774-b0d3-a2962650da3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012217195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3012217195
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2595211715
Short name T220
Test name
Test status
Simulation time 76914068819 ps
CPU time 384.92 seconds
Started May 28 01:08:32 PM PDT 24
Finished May 28 01:14:59 PM PDT 24
Peak memory 238388 kb
Host smart-fa1b3441-08fd-402a-8da7-4883f5819db1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595211715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2595211715
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4057085016
Short name T204
Test name
Test status
Simulation time 1277970349 ps
CPU time 9.36 seconds
Started May 28 01:08:36 PM PDT 24
Finished May 28 01:08:48 PM PDT 24
Peak memory 211536 kb
Host smart-d694c5de-49f3-4188-9aa4-1895f58e74d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057085016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4057085016
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2556185117
Short name T143
Test name
Test status
Simulation time 3090094668 ps
CPU time 14.36 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:08:49 PM PDT 24
Peak memory 211040 kb
Host smart-85938d3c-ee28-4c34-a88a-fa646b797d12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2556185117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2556185117
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4060637987
Short name T70
Test name
Test status
Simulation time 189540338 ps
CPU time 10.29 seconds
Started May 28 01:08:36 PM PDT 24
Finished May 28 01:08:49 PM PDT 24
Peak memory 212808 kb
Host smart-c3db1bb0-e66a-4c77-a9ff-fedd0139275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060637987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4060637987
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3225246631
Short name T245
Test name
Test status
Simulation time 2792409653 ps
CPU time 50.16 seconds
Started May 28 01:08:30 PM PDT 24
Finished May 28 01:09:22 PM PDT 24
Peak memory 215724 kb
Host smart-072f71b2-ff2f-454b-a128-9df38075ca34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225246631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3225246631
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1929583347
Short name T313
Test name
Test status
Simulation time 2819306081 ps
CPU time 6.65 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:08:32 PM PDT 24
Peak memory 211072 kb
Host smart-e008cc45-892d-47f7-97af-ec447146321a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929583347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1929583347
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2870961110
Short name T282
Test name
Test status
Simulation time 6490286773 ps
CPU time 137.36 seconds
Started May 28 01:08:12 PM PDT 24
Finished May 28 01:10:31 PM PDT 24
Peak memory 228256 kb
Host smart-77b781d0-43a0-4650-be12-0c1d936995db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870961110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2870961110
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2717377328
Short name T155
Test name
Test status
Simulation time 168745197 ps
CPU time 9.67 seconds
Started May 28 01:08:04 PM PDT 24
Finished May 28 01:08:15 PM PDT 24
Peak memory 211508 kb
Host smart-440d66b4-eb29-44cf-a07d-01e3cb25f9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717377328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2717377328
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3316876703
Short name T8
Test name
Test status
Simulation time 15161746481 ps
CPU time 13.81 seconds
Started May 28 01:07:55 PM PDT 24
Finished May 28 01:08:10 PM PDT 24
Peak memory 210960 kb
Host smart-38a9873a-50a4-4ce9-9ae3-bcb709853787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316876703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3316876703
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.862500061
Short name T28
Test name
Test status
Simulation time 7085846421 ps
CPU time 61.09 seconds
Started May 28 01:08:06 PM PDT 24
Finished May 28 01:09:08 PM PDT 24
Peak memory 236380 kb
Host smart-ad287a29-f337-4169-b8f4-43db0b9ed469
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862500061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.862500061
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1001517251
Short name T158
Test name
Test status
Simulation time 4313224892 ps
CPU time 33.48 seconds
Started May 28 01:08:03 PM PDT 24
Finished May 28 01:08:37 PM PDT 24
Peak memory 211124 kb
Host smart-6c53c093-ba36-443c-b06e-c1dd86ab6f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001517251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1001517251
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3459352106
Short name T200
Test name
Test status
Simulation time 410499836 ps
CPU time 20.25 seconds
Started May 28 01:08:18 PM PDT 24
Finished May 28 01:08:41 PM PDT 24
Peak memory 215028 kb
Host smart-770057cf-9d10-4bc8-a255-e07902872239
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459352106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3459352106
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3215612851
Short name T52
Test name
Test status
Simulation time 62921197026 ps
CPU time 9270.7 seconds
Started May 28 01:07:55 PM PDT 24
Finished May 28 03:42:28 PM PDT 24
Peak memory 233844 kb
Host smart-153cc30e-181f-48a5-a143-b3ce46e26eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215612851 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3215612851
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.866960066
Short name T38
Test name
Test status
Simulation time 995188975 ps
CPU time 10.06 seconds
Started May 28 01:08:39 PM PDT 24
Finished May 28 01:08:52 PM PDT 24
Peak memory 210932 kb
Host smart-25ed39f1-b24c-4588-a4fe-321d932b9a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866960066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.866960066
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.778619241
Short name T23
Test name
Test status
Simulation time 44194149990 ps
CPU time 290.76 seconds
Started May 28 01:08:45 PM PDT 24
Finished May 28 01:13:38 PM PDT 24
Peak memory 234472 kb
Host smart-4aa39278-f150-401a-9452-3716d265957b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778619241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.778619241
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3839219857
Short name T20
Test name
Test status
Simulation time 341201120 ps
CPU time 9.4 seconds
Started May 28 01:08:38 PM PDT 24
Finished May 28 01:08:51 PM PDT 24
Peak memory 211548 kb
Host smart-9e0eead4-0d81-47bd-89b2-c3b82906a927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839219857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3839219857
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2910210386
Short name T135
Test name
Test status
Simulation time 8988090992 ps
CPU time 17.95 seconds
Started May 28 01:08:41 PM PDT 24
Finished May 28 01:09:01 PM PDT 24
Peak memory 210980 kb
Host smart-9ff8f60f-4711-419f-9eff-75e7b1d10d43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910210386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2910210386
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.303848705
Short name T269
Test name
Test status
Simulation time 3872046552 ps
CPU time 30.92 seconds
Started May 28 01:08:39 PM PDT 24
Finished May 28 01:09:13 PM PDT 24
Peak memory 213576 kb
Host smart-05dad09c-db5c-41e2-9c0c-4ffc2e7d039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303848705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.303848705
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.634712619
Short name T292
Test name
Test status
Simulation time 4713492569 ps
CPU time 13.98 seconds
Started May 28 01:08:39 PM PDT 24
Finished May 28 01:08:56 PM PDT 24
Peak memory 212112 kb
Host smart-9c75d021-d16c-474b-bbcd-93a33c3ece42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634712619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.634712619
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3017586927
Short name T195
Test name
Test status
Simulation time 4301096955 ps
CPU time 10.42 seconds
Started May 28 01:08:44 PM PDT 24
Finished May 28 01:08:57 PM PDT 24
Peak memory 211012 kb
Host smart-af430860-d5d4-4f35-87d5-a8c8b397378a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017586927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3017586927
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3353903097
Short name T147
Test name
Test status
Simulation time 7243038397 ps
CPU time 100.77 seconds
Started May 28 01:08:43 PM PDT 24
Finished May 28 01:10:26 PM PDT 24
Peak memory 219332 kb
Host smart-0c2333e5-5e91-42fd-90ef-c1e51861af05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353903097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3353903097
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2921646027
Short name T288
Test name
Test status
Simulation time 4723165570 ps
CPU time 23.48 seconds
Started May 28 01:08:51 PM PDT 24
Finished May 28 01:09:17 PM PDT 24
Peak memory 210972 kb
Host smart-45a0556a-6504-412f-aaa2-c4fd22df4485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921646027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2921646027
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3044629892
Short name T123
Test name
Test status
Simulation time 7334481834 ps
CPU time 16.28 seconds
Started May 28 01:08:50 PM PDT 24
Finished May 28 01:09:08 PM PDT 24
Peak memory 211040 kb
Host smart-b2e0f717-e013-4f7b-a947-c059b3d71601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3044629892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3044629892
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4009056697
Short name T203
Test name
Test status
Simulation time 3294884693 ps
CPU time 32.11 seconds
Started May 28 01:08:44 PM PDT 24
Finished May 28 01:09:18 PM PDT 24
Peak memory 212780 kb
Host smart-5783f61d-90c8-401e-8db8-175ac14cacf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009056697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4009056697
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4209809871
Short name T342
Test name
Test status
Simulation time 6149417265 ps
CPU time 29.09 seconds
Started May 28 01:08:39 PM PDT 24
Finished May 28 01:09:11 PM PDT 24
Peak memory 219132 kb
Host smart-fb7a3e2f-8087-4bff-9b50-498d663ab0f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209809871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4209809871
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3552802812
Short name T237
Test name
Test status
Simulation time 22679956814 ps
CPU time 6537.73 seconds
Started May 28 01:08:58 PM PDT 24
Finished May 28 02:58:00 PM PDT 24
Peak memory 229056 kb
Host smart-04ee0a9f-50de-4736-a9c2-2816e6d69150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552802812 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3552802812
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3290288291
Short name T281
Test name
Test status
Simulation time 2139970643 ps
CPU time 15.38 seconds
Started May 28 01:08:39 PM PDT 24
Finished May 28 01:08:57 PM PDT 24
Peak memory 210928 kb
Host smart-0557c8c3-30d2-4216-9369-cb3099e87c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290288291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3290288291
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1407660028
Short name T325
Test name
Test status
Simulation time 59801319560 ps
CPU time 353.47 seconds
Started May 28 01:08:45 PM PDT 24
Finished May 28 01:14:41 PM PDT 24
Peak memory 234620 kb
Host smart-3f564e50-64b5-489c-94e5-767a9d65ba37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407660028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1407660028
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.327064378
Short name T146
Test name
Test status
Simulation time 2965471338 ps
CPU time 28.03 seconds
Started May 28 01:08:50 PM PDT 24
Finished May 28 01:09:20 PM PDT 24
Peak memory 211628 kb
Host smart-6ebac762-df97-46a8-9205-1c07a2f47f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327064378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.327064378
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.303905168
Short name T168
Test name
Test status
Simulation time 8056297629 ps
CPU time 17.1 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:08:57 PM PDT 24
Peak memory 210960 kb
Host smart-c8bd3444-30c1-4455-93ab-115f872d7b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303905168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.303905168
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3692902122
Short name T151
Test name
Test status
Simulation time 374191391 ps
CPU time 9.78 seconds
Started May 28 01:08:46 PM PDT 24
Finished May 28 01:08:58 PM PDT 24
Peak memory 213032 kb
Host smart-13eb1437-568b-4e70-86b4-da40ae306239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692902122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3692902122
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.836349973
Short name T68
Test name
Test status
Simulation time 4485360738 ps
CPU time 48.25 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:09:28 PM PDT 24
Peak memory 213112 kb
Host smart-6984934b-5b7a-4989-b689-bfc2aa432262
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836349973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.836349973
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3787907264
Short name T273
Test name
Test status
Simulation time 12121376886 ps
CPU time 549.74 seconds
Started May 28 01:08:34 PM PDT 24
Finished May 28 01:17:46 PM PDT 24
Peak memory 221140 kb
Host smart-068b438f-b58d-48b3-8228-93625eea61f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787907264 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3787907264
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3742058831
Short name T166
Test name
Test status
Simulation time 858703232 ps
CPU time 5.71 seconds
Started May 28 01:08:44 PM PDT 24
Finished May 28 01:08:52 PM PDT 24
Peak memory 210892 kb
Host smart-1934537a-1a39-4402-a94f-ae8ec18e60b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742058831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3742058831
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3937777035
Short name T206
Test name
Test status
Simulation time 61101559205 ps
CPU time 332.18 seconds
Started May 28 01:08:45 PM PDT 24
Finished May 28 01:14:19 PM PDT 24
Peak memory 237396 kb
Host smart-490d7791-2d72-4147-91f1-ca4cdc3652db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937777035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3937777035
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2941955837
Short name T226
Test name
Test status
Simulation time 5130980804 ps
CPU time 24.29 seconds
Started May 28 01:08:40 PM PDT 24
Finished May 28 01:09:07 PM PDT 24
Peak memory 219260 kb
Host smart-561cc5b8-4b44-41d4-92ef-0ac776413249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941955837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2941955837
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3898447495
Short name T255
Test name
Test status
Simulation time 7340315959 ps
CPU time 15.89 seconds
Started May 28 01:08:46 PM PDT 24
Finished May 28 01:09:04 PM PDT 24
Peak memory 210900 kb
Host smart-8e9ac284-7f8a-4f4c-bc23-534cb1755c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898447495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3898447495
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.369643240
Short name T174
Test name
Test status
Simulation time 7916149585 ps
CPU time 44.93 seconds
Started May 28 01:08:40 PM PDT 24
Finished May 28 01:09:28 PM PDT 24
Peak memory 213428 kb
Host smart-bbec5534-a75b-4bc9-bc27-8fb65983498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369643240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.369643240
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.845009495
Short name T199
Test name
Test status
Simulation time 1752808217 ps
CPU time 22.88 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:09:03 PM PDT 24
Peak memory 213852 kb
Host smart-eedc0441-e3a5-4b4c-acf9-ad883fbc4c98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845009495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.845009495
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2606184978
Short name T340
Test name
Test status
Simulation time 1462888724 ps
CPU time 12.52 seconds
Started May 28 01:08:41 PM PDT 24
Finished May 28 01:08:55 PM PDT 24
Peak memory 210932 kb
Host smart-467ff29b-fbdb-425f-90da-19482ea8393e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606184978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2606184978
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1445738908
Short name T45
Test name
Test status
Simulation time 62457806817 ps
CPU time 224.44 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:12:20 PM PDT 24
Peak memory 229952 kb
Host smart-353eb03b-c21f-49f5-b8ca-1050fe10d4be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445738908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1445738908
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2139800062
Short name T300
Test name
Test status
Simulation time 172098841 ps
CPU time 9.65 seconds
Started May 28 01:08:49 PM PDT 24
Finished May 28 01:09:00 PM PDT 24
Peak memory 211504 kb
Host smart-8e675b3f-f04f-4258-bcd9-d3188d7577f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139800062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2139800062
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.691589709
Short name T131
Test name
Test status
Simulation time 99639001 ps
CPU time 5.47 seconds
Started May 28 01:08:46 PM PDT 24
Finished May 28 01:08:53 PM PDT 24
Peak memory 210884 kb
Host smart-1c92f4ca-93f7-42fe-be1d-7f5cea915e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691589709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.691589709
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3370377514
Short name T15
Test name
Test status
Simulation time 7249735827 ps
CPU time 23.33 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:09:04 PM PDT 24
Peak memory 213892 kb
Host smart-cc90125a-51a0-4589-b25f-8767466776a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370377514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3370377514
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1036077689
Short name T65
Test name
Test status
Simulation time 2064510912 ps
CPU time 30.07 seconds
Started May 28 01:08:45 PM PDT 24
Finished May 28 01:09:18 PM PDT 24
Peak memory 213644 kb
Host smart-b89e7411-048f-4c84-8d03-5bb722b97d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036077689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1036077689
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2395223544
Short name T335
Test name
Test status
Simulation time 45745251689 ps
CPU time 762.81 seconds
Started May 28 01:09:02 PM PDT 24
Finished May 28 01:21:49 PM PDT 24
Peak memory 227784 kb
Host smart-029a1ecd-09ed-4154-8934-5abca3a90f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395223544 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2395223544
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3470110566
Short name T233
Test name
Test status
Simulation time 1677818030 ps
CPU time 13.23 seconds
Started May 28 01:09:03 PM PDT 24
Finished May 28 01:09:20 PM PDT 24
Peak memory 211032 kb
Host smart-7fa8e1f5-07e4-4408-bbbd-f7980edac4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470110566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3470110566
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.70931774
Short name T44
Test name
Test status
Simulation time 64973403562 ps
CPU time 619.1 seconds
Started May 28 01:08:44 PM PDT 24
Finished May 28 01:19:05 PM PDT 24
Peak memory 229940 kb
Host smart-240c18f2-9eaa-473e-9718-a797c9641ce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70931774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_co
rrupt_sig_fatal_chk.70931774
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4087746237
Short name T216
Test name
Test status
Simulation time 3612984096 ps
CPU time 25.36 seconds
Started May 28 01:08:43 PM PDT 24
Finished May 28 01:09:11 PM PDT 24
Peak memory 211552 kb
Host smart-f4f9b706-510c-4ac5-9f93-0dcb3b3c532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087746237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4087746237
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.977041751
Short name T260
Test name
Test status
Simulation time 1249327435 ps
CPU time 8.44 seconds
Started May 28 01:09:01 PM PDT 24
Finished May 28 01:09:13 PM PDT 24
Peak memory 210864 kb
Host smart-cc4b3098-04a2-474d-a3fb-c758b825d614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977041751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.977041751
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3178582126
Short name T358
Test name
Test status
Simulation time 1345305864 ps
CPU time 9.83 seconds
Started May 28 01:08:48 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 219056 kb
Host smart-4511e41a-13b8-4f25-98cf-b5e9c53b17af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178582126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3178582126
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.949235941
Short name T291
Test name
Test status
Simulation time 410610729 ps
CPU time 11.14 seconds
Started May 28 01:08:50 PM PDT 24
Finished May 28 01:09:03 PM PDT 24
Peak memory 219072 kb
Host smart-4bc8279c-e914-4b05-aaf8-3d07845dd09f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949235941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.949235941
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3031545534
Short name T31
Test name
Test status
Simulation time 925716512 ps
CPU time 7.12 seconds
Started May 28 01:08:45 PM PDT 24
Finished May 28 01:08:55 PM PDT 24
Peak memory 210928 kb
Host smart-e32733f8-2131-41e2-a934-a8d4b2a1c626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031545534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3031545534
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1718390672
Short name T253
Test name
Test status
Simulation time 3793232719 ps
CPU time 130.47 seconds
Started May 28 01:08:52 PM PDT 24
Finished May 28 01:11:07 PM PDT 24
Peak memory 228148 kb
Host smart-0d473688-3986-4951-ad2d-4f84c947da20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718390672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1718390672
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.386039954
Short name T167
Test name
Test status
Simulation time 14008797188 ps
CPU time 30.27 seconds
Started May 28 01:08:52 PM PDT 24
Finished May 28 01:09:26 PM PDT 24
Peak memory 211820 kb
Host smart-e8513d19-4d73-46ea-b9e3-60429efb187f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386039954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.386039954
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.711088532
Short name T2
Test name
Test status
Simulation time 1685548271 ps
CPU time 14.57 seconds
Started May 28 01:08:47 PM PDT 24
Finished May 28 01:09:03 PM PDT 24
Peak memory 210884 kb
Host smart-d380b3ef-c5dd-49b4-8803-60b0ecc00344
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711088532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.711088532
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1734965878
Short name T362
Test name
Test status
Simulation time 1812292077 ps
CPU time 20.52 seconds
Started May 28 01:08:52 PM PDT 24
Finished May 28 01:09:16 PM PDT 24
Peak memory 213216 kb
Host smart-097b26b4-cd4d-434a-9c4a-17b96fe083b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734965878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1734965878
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2897919052
Short name T348
Test name
Test status
Simulation time 2513014154 ps
CPU time 12.66 seconds
Started May 28 01:08:48 PM PDT 24
Finished May 28 01:09:02 PM PDT 24
Peak memory 211604 kb
Host smart-af5a739f-890d-4d37-8543-2201479ef350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897919052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2897919052
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2119314111
Short name T149
Test name
Test status
Simulation time 4118075162 ps
CPU time 16.24 seconds
Started May 28 01:08:41 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 210976 kb
Host smart-43dd41a0-9eb8-4e0c-903d-71b892aadff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119314111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2119314111
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1546156054
Short name T138
Test name
Test status
Simulation time 21084407535 ps
CPU time 113.59 seconds
Started May 28 01:08:46 PM PDT 24
Finished May 28 01:10:42 PM PDT 24
Peak memory 212208 kb
Host smart-a76ff92f-1f3c-4f4e-9f3c-46bac4a56537
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546156054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1546156054
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3670091613
Short name T304
Test name
Test status
Simulation time 691185832 ps
CPU time 13.49 seconds
Started May 28 01:08:48 PM PDT 24
Finished May 28 01:09:03 PM PDT 24
Peak memory 211536 kb
Host smart-ab5133b2-0551-45dd-aeb8-668234e11e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670091613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3670091613
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2156948285
Short name T324
Test name
Test status
Simulation time 4516986549 ps
CPU time 11.7 seconds
Started May 28 01:08:44 PM PDT 24
Finished May 28 01:08:57 PM PDT 24
Peak memory 210936 kb
Host smart-3e0039fb-373a-443c-a71e-06632d865d8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156948285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2156948285
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2998126574
Short name T347
Test name
Test status
Simulation time 15178571834 ps
CPU time 36.49 seconds
Started May 28 01:08:45 PM PDT 24
Finished May 28 01:09:23 PM PDT 24
Peak memory 214268 kb
Host smart-bda9d0e0-65d0-4b5f-b99d-33eeaca3260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998126574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2998126574
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.91373846
Short name T176
Test name
Test status
Simulation time 20898088672 ps
CPU time 65.21 seconds
Started May 28 01:08:42 PM PDT 24
Finished May 28 01:09:49 PM PDT 24
Peak memory 219112 kb
Host smart-1422263e-edf8-409c-bdd8-6db8cb90eae6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91373846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.rom_ctrl_stress_all.91373846
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1342157191
Short name T264
Test name
Test status
Simulation time 622076382 ps
CPU time 8.56 seconds
Started May 28 01:08:51 PM PDT 24
Finished May 28 01:09:03 PM PDT 24
Peak memory 210932 kb
Host smart-1072ea6d-3804-4646-a3e7-0b482528a6d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342157191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1342157191
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.31942333
Short name T188
Test name
Test status
Simulation time 89085637222 ps
CPU time 191.2 seconds
Started May 28 01:08:51 PM PDT 24
Finished May 28 01:12:04 PM PDT 24
Peak memory 219376 kb
Host smart-ad2dcb31-f721-4ced-a56c-091b254d4aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31942333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_co
rrupt_sig_fatal_chk.31942333
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3157787636
Short name T283
Test name
Test status
Simulation time 1438024300 ps
CPU time 11.95 seconds
Started May 28 01:08:58 PM PDT 24
Finished May 28 01:09:13 PM PDT 24
Peak memory 210948 kb
Host smart-293a5502-9d10-42df-8fdd-df6bccfa47e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157787636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3157787636
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.387633293
Short name T140
Test name
Test status
Simulation time 3780776177 ps
CPU time 8.41 seconds
Started May 28 01:08:47 PM PDT 24
Finished May 28 01:08:57 PM PDT 24
Peak memory 210928 kb
Host smart-4fe715c0-a749-42f3-be4c-c3ba119d29e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387633293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.387633293
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3896298404
Short name T299
Test name
Test status
Simulation time 1849096799 ps
CPU time 22.45 seconds
Started May 28 01:08:36 PM PDT 24
Finished May 28 01:09:06 PM PDT 24
Peak memory 219048 kb
Host smart-dce0dcd9-bebd-4da7-8857-12bcd8c83f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896298404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3896298404
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3526824954
Short name T285
Test name
Test status
Simulation time 377167630 ps
CPU time 14.38 seconds
Started May 28 01:09:06 PM PDT 24
Finished May 28 01:09:25 PM PDT 24
Peak memory 219056 kb
Host smart-2b981dd8-09b7-46a1-9b70-ae435e9000a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526824954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3526824954
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2966173742
Short name T254
Test name
Test status
Simulation time 12822338310 ps
CPU time 10.85 seconds
Started May 28 01:08:58 PM PDT 24
Finished May 28 01:09:12 PM PDT 24
Peak memory 210992 kb
Host smart-e5979e30-e3b3-438e-a59c-d0e63ed584f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966173742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2966173742
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1000989687
Short name T249
Test name
Test status
Simulation time 93976550521 ps
CPU time 236.66 seconds
Started May 28 01:09:00 PM PDT 24
Finished May 28 01:13:01 PM PDT 24
Peak memory 237168 kb
Host smart-e7fa6fc6-672b-4c7f-a4f1-3f12f4c39b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000989687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1000989687
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.654149144
Short name T191
Test name
Test status
Simulation time 15352771385 ps
CPU time 31.36 seconds
Started May 28 01:08:58 PM PDT 24
Finished May 28 01:09:33 PM PDT 24
Peak memory 211904 kb
Host smart-6ce10919-3f17-4244-a76f-f28b831cdce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654149144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.654149144
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2503009098
Short name T227
Test name
Test status
Simulation time 1659326117 ps
CPU time 15.32 seconds
Started May 28 01:08:52 PM PDT 24
Finished May 28 01:09:11 PM PDT 24
Peak memory 210880 kb
Host smart-7b25a417-3353-42c1-998c-b11405873377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2503009098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2503009098
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2499695953
Short name T171
Test name
Test status
Simulation time 17870598705 ps
CPU time 36.17 seconds
Started May 28 01:09:01 PM PDT 24
Finished May 28 01:09:41 PM PDT 24
Peak memory 215240 kb
Host smart-5629c40c-e374-4071-adcf-530efb8af32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499695953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2499695953
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2313259409
Short name T287
Test name
Test status
Simulation time 6988271246 ps
CPU time 20.76 seconds
Started May 28 01:08:52 PM PDT 24
Finished May 28 01:09:17 PM PDT 24
Peak memory 211252 kb
Host smart-0d9acaab-1920-43cd-8002-1e038373b93e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313259409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2313259409
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2507473923
Short name T265
Test name
Test status
Simulation time 640385324 ps
CPU time 4.4 seconds
Started May 28 01:08:18 PM PDT 24
Finished May 28 01:08:25 PM PDT 24
Peak memory 210952 kb
Host smart-87c38033-24e9-458a-9274-0486e92cacff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507473923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2507473923
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2306474507
Short name T22
Test name
Test status
Simulation time 31487220165 ps
CPU time 373.57 seconds
Started May 28 01:08:23 PM PDT 24
Finished May 28 01:14:39 PM PDT 24
Peak memory 224312 kb
Host smart-bc9acedd-44fb-422a-8e17-77a340efcee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306474507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2306474507
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.681657004
Short name T302
Test name
Test status
Simulation time 72022283964 ps
CPU time 31.94 seconds
Started May 28 01:08:14 PM PDT 24
Finished May 28 01:08:48 PM PDT 24
Peak memory 211984 kb
Host smart-b77d5ad4-a7fc-4499-9e0b-f2833d9a48d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681657004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.681657004
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.960735127
Short name T104
Test name
Test status
Simulation time 213280367 ps
CPU time 5.69 seconds
Started May 28 01:08:19 PM PDT 24
Finished May 28 01:08:28 PM PDT 24
Peak memory 210960 kb
Host smart-6ce4fa37-2600-4c25-9833-26946064a003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960735127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.960735127
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.220681497
Short name T276
Test name
Test status
Simulation time 12672200052 ps
CPU time 27.48 seconds
Started May 28 01:08:06 PM PDT 24
Finished May 28 01:08:35 PM PDT 24
Peak memory 219100 kb
Host smart-c061c489-2456-44a1-a65e-5d68dcff49fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220681497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.220681497
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3460155317
Short name T172
Test name
Test status
Simulation time 4017044428 ps
CPU time 14.74 seconds
Started May 28 01:08:41 PM PDT 24
Finished May 28 01:08:58 PM PDT 24
Peak memory 210904 kb
Host smart-25ed58cd-67ff-416c-88c3-9fa24c3ba08b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460155317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3460155317
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2563584639
Short name T350
Test name
Test status
Simulation time 49507274862 ps
CPU time 466.51 seconds
Started May 28 01:07:51 PM PDT 24
Finished May 28 01:15:38 PM PDT 24
Peak memory 227412 kb
Host smart-5a1df445-c013-4966-a459-96e2ad2c9a7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563584639 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2563584639
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2042638952
Short name T266
Test name
Test status
Simulation time 6847693263 ps
CPU time 16.39 seconds
Started May 28 01:08:09 PM PDT 24
Finished May 28 01:08:27 PM PDT 24
Peak memory 210992 kb
Host smart-d94656b8-525b-4025-9408-9926fe46b362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042638952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2042638952
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2715975195
Short name T182
Test name
Test status
Simulation time 3352014958 ps
CPU time 114.51 seconds
Started May 28 01:08:14 PM PDT 24
Finished May 28 01:10:11 PM PDT 24
Peak memory 228228 kb
Host smart-b5b22944-c6cb-4d8b-a40b-f68c0d8c2b5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715975195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2715975195
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1229735978
Short name T223
Test name
Test status
Simulation time 4370044321 ps
CPU time 33.29 seconds
Started May 28 01:08:18 PM PDT 24
Finished May 28 01:08:54 PM PDT 24
Peak memory 211760 kb
Host smart-87f3311c-dce1-49ad-b128-7b6732634bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229735978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1229735978
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2629722081
Short name T132
Test name
Test status
Simulation time 3001611380 ps
CPU time 14.94 seconds
Started May 28 01:08:41 PM PDT 24
Finished May 28 01:08:59 PM PDT 24
Peak memory 210964 kb
Host smart-af8e5d04-3c5a-42ab-af77-535a049a9350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2629722081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2629722081
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4048284243
Short name T181
Test name
Test status
Simulation time 4456920827 ps
CPU time 23.69 seconds
Started May 28 01:08:10 PM PDT 24
Finished May 28 01:08:35 PM PDT 24
Peak memory 213148 kb
Host smart-985e205c-e370-4428-b6ae-5e8e7bc6718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048284243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4048284243
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.641579238
Short name T222
Test name
Test status
Simulation time 210536770 ps
CPU time 7.6 seconds
Started May 28 01:08:08 PM PDT 24
Finished May 28 01:08:17 PM PDT 24
Peak memory 210784 kb
Host smart-0dcea175-b4a5-4f11-b6d4-d767934de67a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641579238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.641579238
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1647185466
Short name T290
Test name
Test status
Simulation time 26539218605 ps
CPU time 998.43 seconds
Started May 28 01:08:04 PM PDT 24
Finished May 28 01:24:43 PM PDT 24
Peak memory 228656 kb
Host smart-1c248aed-17b0-49fa-942a-cf6a80e4df48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647185466 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1647185466
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1791398075
Short name T236
Test name
Test status
Simulation time 616581405 ps
CPU time 8.12 seconds
Started May 28 01:08:06 PM PDT 24
Finished May 28 01:08:15 PM PDT 24
Peak memory 210552 kb
Host smart-b4253ea2-9966-4755-8d52-a232dc970605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791398075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1791398075
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1032359734
Short name T21
Test name
Test status
Simulation time 55137584457 ps
CPU time 320.93 seconds
Started May 28 01:08:07 PM PDT 24
Finished May 28 01:13:29 PM PDT 24
Peak memory 227920 kb
Host smart-6923abca-8181-46cf-862e-593b6a003566
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032359734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1032359734
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1987604868
Short name T243
Test name
Test status
Simulation time 11770299313 ps
CPU time 27.23 seconds
Started May 28 01:08:14 PM PDT 24
Finished May 28 01:08:43 PM PDT 24
Peak memory 211980 kb
Host smart-e4efd185-405f-40ad-a1b3-160644dfaa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987604868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1987604868
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3482198256
Short name T262
Test name
Test status
Simulation time 179394605 ps
CPU time 6.56 seconds
Started May 28 01:08:15 PM PDT 24
Finished May 28 01:08:23 PM PDT 24
Peak memory 210876 kb
Host smart-5834cf22-f629-45a7-aacd-a927fdd8b483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3482198256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3482198256
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.269491056
Short name T189
Test name
Test status
Simulation time 367864623 ps
CPU time 10.42 seconds
Started May 28 01:08:05 PM PDT 24
Finished May 28 01:08:17 PM PDT 24
Peak memory 213064 kb
Host smart-047f9318-09fd-4668-960d-a954c125e6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269491056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.269491056
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.127127040
Short name T339
Test name
Test status
Simulation time 57134025122 ps
CPU time 105.4 seconds
Started May 28 01:08:20 PM PDT 24
Finished May 28 01:10:08 PM PDT 24
Peak memory 219132 kb
Host smart-13412d5c-0277-4ffb-a061-9da236a176de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127127040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.127127040
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.386134426
Short name T91
Test name
Test status
Simulation time 2242343964 ps
CPU time 13.69 seconds
Started May 28 01:07:59 PM PDT 24
Finished May 28 01:08:13 PM PDT 24
Peak memory 211000 kb
Host smart-e6a9b01b-5d2d-4244-93d0-5c66d3f0fdb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386134426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.386134426
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1715814182
Short name T136
Test name
Test status
Simulation time 5023262245 ps
CPU time 85.38 seconds
Started May 28 01:08:49 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 236784 kb
Host smart-8ea98d32-60a7-435a-998d-aeff8db5b715
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715814182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1715814182
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.584744358
Short name T329
Test name
Test status
Simulation time 6562535340 ps
CPU time 28.89 seconds
Started May 28 01:08:00 PM PDT 24
Finished May 28 01:08:30 PM PDT 24
Peak memory 210380 kb
Host smart-ea84a108-2a03-46a7-8c35-b3dde8150180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584744358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.584744358
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3243377852
Short name T164
Test name
Test status
Simulation time 6073230495 ps
CPU time 17.58 seconds
Started May 28 01:08:33 PM PDT 24
Finished May 28 01:08:54 PM PDT 24
Peak memory 211272 kb
Host smart-04923ef8-fedd-40da-bb26-f64cc3a47e46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3243377852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3243377852
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3063717688
Short name T3
Test name
Test status
Simulation time 4045046995 ps
CPU time 44.04 seconds
Started May 28 01:08:17 PM PDT 24
Finished May 28 01:09:03 PM PDT 24
Peak memory 212980 kb
Host smart-3c02d6c3-7817-4fd6-9e48-ec62d7a33b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063717688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3063717688
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2737740864
Short name T270
Test name
Test status
Simulation time 4136750827 ps
CPU time 37.01 seconds
Started May 28 01:08:13 PM PDT 24
Finished May 28 01:08:51 PM PDT 24
Peak memory 219104 kb
Host smart-a2152eb0-c1a2-44e0-b09d-ff5d48119629
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737740864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2737740864
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4062964611
Short name T51
Test name
Test status
Simulation time 32427127610 ps
CPU time 1162 seconds
Started May 28 01:08:00 PM PDT 24
Finished May 28 01:27:23 PM PDT 24
Peak memory 234008 kb
Host smart-5665d625-272e-4599-95a1-030f0053c7b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062964611 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.4062964611
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1623178642
Short name T351
Test name
Test status
Simulation time 111406556 ps
CPU time 4.18 seconds
Started May 28 01:08:06 PM PDT 24
Finished May 28 01:08:11 PM PDT 24
Peak memory 211036 kb
Host smart-7f44ccf5-6525-4972-9e09-56a00d62b3af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623178642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1623178642
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.389583076
Short name T305
Test name
Test status
Simulation time 1537116293 ps
CPU time 59.08 seconds
Started May 28 01:08:22 PM PDT 24
Finished May 28 01:09:23 PM PDT 24
Peak memory 236344 kb
Host smart-fff02899-c9ca-4bf8-be6a-0ff599ac154e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389583076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.389583076
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.572494819
Short name T127
Test name
Test status
Simulation time 8867895151 ps
CPU time 22.37 seconds
Started May 28 01:08:08 PM PDT 24
Finished May 28 01:08:32 PM PDT 24
Peak memory 211444 kb
Host smart-1d057752-a7ed-4c84-a5e7-fea60ab3f62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572494819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.572494819
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3080208549
Short name T321
Test name
Test status
Simulation time 222067305 ps
CPU time 5.72 seconds
Started May 28 01:08:03 PM PDT 24
Finished May 28 01:08:10 PM PDT 24
Peak memory 210776 kb
Host smart-f54d718a-5211-4d0e-882a-d1e72a9436e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080208549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3080208549
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.571481590
Short name T210
Test name
Test status
Simulation time 1515797198 ps
CPU time 20.11 seconds
Started May 28 01:08:37 PM PDT 24
Finished May 28 01:09:00 PM PDT 24
Peak memory 213696 kb
Host smart-c7fbd5d6-5f17-4fbf-8319-7d9ddd220509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571481590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.571481590
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1216585006
Short name T359
Test name
Test status
Simulation time 25511069463 ps
CPU time 75.92 seconds
Started May 28 01:08:18 PM PDT 24
Finished May 28 01:09:35 PM PDT 24
Peak memory 217292 kb
Host smart-c9080799-cd6b-4254-b446-9df6f386ca8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216585006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1216585006
Directory /workspace/9.rom_ctrl_stress_all/latest
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