Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.57 96.97 93.16 97.88 100.00 98.69 97.89 98.37


Total test records in report: 462
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T300 /workspace/coverage/default/8.rom_ctrl_smoke.142881119 May 30 12:35:16 PM PDT 24 May 30 12:35:28 PM PDT 24 354767206 ps
T301 /workspace/coverage/default/27.rom_ctrl_alert_test.4165074285 May 30 12:35:52 PM PDT 24 May 30 12:36:01 PM PDT 24 2335339913 ps
T302 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1136805368 May 30 12:35:58 PM PDT 24 May 30 12:36:14 PM PDT 24 30792110601 ps
T303 /workspace/coverage/default/29.rom_ctrl_stress_all.3029696685 May 30 12:35:36 PM PDT 24 May 30 12:35:56 PM PDT 24 10461439096 ps
T304 /workspace/coverage/default/49.rom_ctrl_smoke.1223640615 May 30 12:36:08 PM PDT 24 May 30 12:36:32 PM PDT 24 15046801441 ps
T305 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.667495158 May 30 12:35:53 PM PDT 24 May 30 12:36:07 PM PDT 24 2219365813 ps
T306 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1684537411 May 30 12:35:52 PM PDT 24 May 30 12:36:15 PM PDT 24 1986098717 ps
T307 /workspace/coverage/default/20.rom_ctrl_alert_test.2933426153 May 30 12:35:48 PM PDT 24 May 30 12:35:54 PM PDT 24 661884063 ps
T308 /workspace/coverage/default/22.rom_ctrl_alert_test.3135633960 May 30 12:35:35 PM PDT 24 May 30 12:35:51 PM PDT 24 18084217942 ps
T309 /workspace/coverage/default/5.rom_ctrl_alert_test.2153284616 May 30 12:35:17 PM PDT 24 May 30 12:35:35 PM PDT 24 9643062990 ps
T310 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.367243807 May 30 12:35:14 PM PDT 24 May 30 12:35:21 PM PDT 24 102100124 ps
T311 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1252410192 May 30 12:35:32 PM PDT 24 May 30 12:35:42 PM PDT 24 624506827 ps
T312 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1233052434 May 30 12:35:15 PM PDT 24 May 30 12:35:34 PM PDT 24 2098583601 ps
T37 /workspace/coverage/default/3.rom_ctrl_sec_cm.2762179670 May 30 12:35:23 PM PDT 24 May 30 12:36:17 PM PDT 24 1216345677 ps
T313 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2116232909 May 30 12:35:35 PM PDT 24 May 30 12:36:29 PM PDT 24 1006818034 ps
T314 /workspace/coverage/default/7.rom_ctrl_alert_test.2746329453 May 30 12:35:49 PM PDT 24 May 30 12:36:04 PM PDT 24 2611467493 ps
T315 /workspace/coverage/default/42.rom_ctrl_stress_all.2047591445 May 30 12:35:56 PM PDT 24 May 30 12:36:14 PM PDT 24 3123599045 ps
T316 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3428949431 May 30 12:36:03 PM PDT 24 May 30 12:36:13 PM PDT 24 1682369982 ps
T317 /workspace/coverage/default/37.rom_ctrl_stress_all.3558669667 May 30 12:35:52 PM PDT 24 May 30 12:36:24 PM PDT 24 3380773285 ps
T318 /workspace/coverage/default/15.rom_ctrl_stress_all.1345686140 May 30 12:35:39 PM PDT 24 May 30 12:36:11 PM PDT 24 12606196981 ps
T319 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1124206776 May 30 12:35:53 PM PDT 24 May 30 12:38:26 PM PDT 24 12227251204 ps
T320 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.10769988 May 30 12:36:43 PM PDT 24 May 30 12:36:55 PM PDT 24 4330036233 ps
T321 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3906236715 May 30 12:35:40 PM PDT 24 May 30 12:35:49 PM PDT 24 362146777 ps
T322 /workspace/coverage/default/6.rom_ctrl_alert_test.1027000440 May 30 12:35:36 PM PDT 24 May 30 12:35:49 PM PDT 24 1169276382 ps
T323 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.449066737 May 30 12:35:22 PM PDT 24 May 30 12:39:20 PM PDT 24 22487368245 ps
T324 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.989667082 May 30 12:35:22 PM PDT 24 May 30 12:35:52 PM PDT 24 12435588897 ps
T325 /workspace/coverage/default/34.rom_ctrl_stress_all.3341606027 May 30 12:35:48 PM PDT 24 May 30 12:36:18 PM PDT 24 1099827417 ps
T326 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.579997224 May 30 12:35:50 PM PDT 24 May 30 12:41:27 PM PDT 24 70060860522 ps
T327 /workspace/coverage/default/7.rom_ctrl_smoke.2496602970 May 30 12:35:15 PM PDT 24 May 30 12:35:27 PM PDT 24 764848429 ps
T328 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4118826274 May 30 12:35:44 PM PDT 24 May 30 12:36:03 PM PDT 24 10693151574 ps
T329 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4269624950 May 30 12:35:29 PM PDT 24 May 30 12:40:13 PM PDT 24 28785977836 ps
T330 /workspace/coverage/default/33.rom_ctrl_stress_all.3388715092 May 30 12:36:03 PM PDT 24 May 30 12:36:36 PM PDT 24 2368331543 ps
T331 /workspace/coverage/default/30.rom_ctrl_alert_test.3815317162 May 30 12:35:41 PM PDT 24 May 30 12:35:55 PM PDT 24 27040450322 ps
T332 /workspace/coverage/default/16.rom_ctrl_smoke.2427736964 May 30 12:35:29 PM PDT 24 May 30 12:36:04 PM PDT 24 16379611729 ps
T333 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2190164754 May 30 12:35:35 PM PDT 24 May 30 12:35:53 PM PDT 24 24641959682 ps
T334 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.337885772 May 30 12:35:34 PM PDT 24 May 30 12:42:21 PM PDT 24 37722134016 ps
T335 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.824135518 May 30 12:35:28 PM PDT 24 May 30 12:35:42 PM PDT 24 7543187619 ps
T24 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3388114293 May 30 12:35:39 PM PDT 24 May 30 12:36:05 PM PDT 24 2623399344 ps
T336 /workspace/coverage/default/25.rom_ctrl_alert_test.4230368737 May 30 12:36:33 PM PDT 24 May 30 12:36:39 PM PDT 24 86478196 ps
T337 /workspace/coverage/default/22.rom_ctrl_smoke.488190652 May 30 12:35:41 PM PDT 24 May 30 12:36:17 PM PDT 24 19453169741 ps
T338 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.186061150 May 30 12:35:17 PM PDT 24 May 30 12:37:50 PM PDT 24 2725063235 ps
T339 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2427033324 May 30 12:35:37 PM PDT 24 May 30 12:35:52 PM PDT 24 7615212861 ps
T340 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2239961075 May 30 12:35:44 PM PDT 24 May 30 12:35:55 PM PDT 24 1038923037 ps
T341 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.792818498 May 30 12:35:36 PM PDT 24 May 30 12:36:06 PM PDT 24 6190506313 ps
T342 /workspace/coverage/default/10.rom_ctrl_stress_all.888421216 May 30 12:35:23 PM PDT 24 May 30 12:36:21 PM PDT 24 6540274150 ps
T343 /workspace/coverage/default/14.rom_ctrl_alert_test.2280052770 May 30 12:35:20 PM PDT 24 May 30 12:35:29 PM PDT 24 1361228417 ps
T344 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1784490351 May 30 12:36:06 PM PDT 24 May 30 12:36:42 PM PDT 24 4383526588 ps
T345 /workspace/coverage/default/12.rom_ctrl_smoke.192030042 May 30 12:35:34 PM PDT 24 May 30 12:35:57 PM PDT 24 3321780821 ps
T346 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3956368822 May 30 12:35:26 PM PDT 24 May 30 12:35:43 PM PDT 24 7258884950 ps
T347 /workspace/coverage/default/31.rom_ctrl_alert_test.2130542510 May 30 12:35:46 PM PDT 24 May 30 12:35:58 PM PDT 24 4257021688 ps
T348 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1767039576 May 30 12:35:54 PM PDT 24 May 30 12:36:12 PM PDT 24 1958189837 ps
T349 /workspace/coverage/default/2.rom_ctrl_stress_all.2990555968 May 30 12:35:28 PM PDT 24 May 30 12:35:38 PM PDT 24 471215198 ps
T350 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.38385639 May 30 12:35:33 PM PDT 24 May 30 12:38:25 PM PDT 24 23697590718 ps
T351 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3145830522 May 30 12:36:05 PM PDT 24 May 30 12:36:27 PM PDT 24 6991509277 ps
T352 /workspace/coverage/default/47.rom_ctrl_alert_test.1074289290 May 30 12:35:57 PM PDT 24 May 30 12:36:14 PM PDT 24 7329353272 ps
T353 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1612997506 May 30 12:35:31 PM PDT 24 May 30 12:35:47 PM PDT 24 1774623912 ps
T354 /workspace/coverage/default/37.rom_ctrl_alert_test.1250131019 May 30 12:35:51 PM PDT 24 May 30 12:36:08 PM PDT 24 2042341113 ps
T355 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3373642555 May 30 12:35:55 PM PDT 24 May 30 12:39:40 PM PDT 24 161258886311 ps
T356 /workspace/coverage/default/29.rom_ctrl_alert_test.903190610 May 30 12:35:42 PM PDT 24 May 30 12:35:47 PM PDT 24 309393355 ps
T357 /workspace/coverage/default/16.rom_ctrl_stress_all.3589452336 May 30 12:35:27 PM PDT 24 May 30 12:36:16 PM PDT 24 37900446880 ps
T358 /workspace/coverage/default/17.rom_ctrl_smoke.1738516952 May 30 12:35:36 PM PDT 24 May 30 12:35:52 PM PDT 24 2116978717 ps
T359 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.191931554 May 30 12:36:48 PM PDT 24 May 30 12:37:20 PM PDT 24 3519646612 ps
T360 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1273879579 May 30 12:35:27 PM PDT 24 May 30 12:39:45 PM PDT 24 38864970827 ps
T361 /workspace/coverage/default/26.rom_ctrl_smoke.939659978 May 30 12:35:45 PM PDT 24 May 30 12:36:20 PM PDT 24 2728128265 ps
T362 /workspace/coverage/default/44.rom_ctrl_stress_all.2188914989 May 30 12:35:46 PM PDT 24 May 30 12:36:02 PM PDT 24 827252081 ps
T363 /workspace/coverage/default/32.rom_ctrl_alert_test.2800540656 May 30 12:35:34 PM PDT 24 May 30 12:35:45 PM PDT 24 3385704845 ps
T364 /workspace/coverage/default/48.rom_ctrl_alert_test.1140230495 May 30 12:36:12 PM PDT 24 May 30 12:36:21 PM PDT 24 389587509 ps
T365 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2215967481 May 30 12:36:07 PM PDT 24 May 30 12:36:17 PM PDT 24 493480133 ps
T366 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.207445194 May 30 12:36:16 PM PDT 24 May 30 12:36:35 PM PDT 24 13128846461 ps
T59 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.76223687 May 30 12:36:01 PM PDT 24 May 30 12:36:41 PM PDT 24 1037953525 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3888464053 May 30 12:36:06 PM PDT 24 May 30 12:36:15 PM PDT 24 971953400 ps
T63 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4153027290 May 30 12:36:23 PM PDT 24 May 30 12:36:39 PM PDT 24 1876330998 ps
T67 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3353688258 May 30 12:35:56 PM PDT 24 May 30 12:36:09 PM PDT 24 1390090675 ps
T91 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.907596830 May 30 12:36:14 PM PDT 24 May 30 12:36:23 PM PDT 24 454370419 ps
T367 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2720381627 May 30 12:36:05 PM PDT 24 May 30 12:36:27 PM PDT 24 12552255907 ps
T60 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1863489315 May 30 12:36:09 PM PDT 24 May 30 12:37:24 PM PDT 24 6811193568 ps
T92 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1244024377 May 30 12:36:08 PM PDT 24 May 30 12:37:08 PM PDT 24 6585544186 ps
T61 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3857540310 May 30 12:36:15 PM PDT 24 May 30 12:37:36 PM PDT 24 8727562552 ps
T97 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3179644029 May 30 12:36:25 PM PDT 24 May 30 12:36:53 PM PDT 24 1177952043 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.301412567 May 30 12:36:11 PM PDT 24 May 30 12:36:26 PM PDT 24 1256445300 ps
T368 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1238165675 May 30 12:36:08 PM PDT 24 May 30 12:36:19 PM PDT 24 15788590402 ps
T69 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3704672900 May 30 12:36:24 PM PDT 24 May 30 12:36:36 PM PDT 24 4434402554 ps
T70 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.236818742 May 30 12:36:17 PM PDT 24 May 30 12:36:37 PM PDT 24 378642824 ps
T369 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2495362246 May 30 12:36:04 PM PDT 24 May 30 12:36:20 PM PDT 24 12092454072 ps
T370 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2083593909 May 30 12:36:11 PM PDT 24 May 30 12:36:21 PM PDT 24 465542683 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1298423804 May 30 12:36:16 PM PDT 24 May 30 12:36:29 PM PDT 24 1222077025 ps
T72 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.349925165 May 30 12:35:58 PM PDT 24 May 30 12:36:12 PM PDT 24 6329293173 ps
T73 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1060100231 May 30 12:36:08 PM PDT 24 May 30 12:36:17 PM PDT 24 1222076396 ps
T74 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3714553628 May 30 12:36:05 PM PDT 24 May 30 12:36:10 PM PDT 24 158976318 ps
T371 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.833647935 May 30 12:36:20 PM PDT 24 May 30 12:36:39 PM PDT 24 3234213534 ps
T103 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3760372164 May 30 12:36:04 PM PDT 24 May 30 12:36:46 PM PDT 24 4637829120 ps
T75 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4219933947 May 30 12:36:12 PM PDT 24 May 30 12:37:03 PM PDT 24 31777426116 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2691267696 May 30 12:36:09 PM PDT 24 May 30 12:36:27 PM PDT 24 2135557858 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3847058211 May 30 12:36:16 PM PDT 24 May 30 12:36:45 PM PDT 24 7640420153 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1149983942 May 30 12:36:18 PM PDT 24 May 30 12:36:27 PM PDT 24 4127956454 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.676242820 May 30 12:36:04 PM PDT 24 May 30 12:36:19 PM PDT 24 3735718594 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2542476277 May 30 12:36:09 PM PDT 24 May 30 12:36:26 PM PDT 24 7635271980 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.861045958 May 30 12:36:11 PM PDT 24 May 30 12:36:25 PM PDT 24 5457679405 ps
T375 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1557687493 May 30 12:36:13 PM PDT 24 May 30 12:36:26 PM PDT 24 1516220335 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.666816181 May 30 12:35:57 PM PDT 24 May 30 12:36:12 PM PDT 24 3595645912 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3869302915 May 30 12:36:11 PM PDT 24 May 30 12:36:58 PM PDT 24 3632371579 ps
T79 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2192174557 May 30 12:35:45 PM PDT 24 May 30 12:35:57 PM PDT 24 2500264740 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3089788904 May 30 12:36:01 PM PDT 24 May 30 12:36:06 PM PDT 24 175608124 ps
T80 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1562840324 May 30 12:36:09 PM PDT 24 May 30 12:36:15 PM PDT 24 89291420 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3100160169 May 30 12:36:16 PM PDT 24 May 30 12:36:33 PM PDT 24 8038079555 ps
T378 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.455076215 May 30 12:36:15 PM PDT 24 May 30 12:36:24 PM PDT 24 346842067 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.970779688 May 30 12:36:16 PM PDT 24 May 30 12:36:22 PM PDT 24 91087554 ps
T380 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.153945159 May 30 12:36:11 PM PDT 24 May 30 12:37:17 PM PDT 24 16461642589 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1642663529 May 30 12:36:11 PM PDT 24 May 30 12:36:22 PM PDT 24 652969521 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.206002487 May 30 12:36:09 PM PDT 24 May 30 12:36:15 PM PDT 24 363439291 ps
T95 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.620798290 May 30 12:36:05 PM PDT 24 May 30 12:36:13 PM PDT 24 2053173642 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2582678569 May 30 12:36:09 PM PDT 24 May 30 12:36:15 PM PDT 24 830899093 ps
T384 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3525224872 May 30 12:36:14 PM PDT 24 May 30 12:36:30 PM PDT 24 6438013565 ps
T385 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1921339712 May 30 12:36:08 PM PDT 24 May 30 12:36:17 PM PDT 24 193664470 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1487424285 May 30 12:35:56 PM PDT 24 May 30 12:36:13 PM PDT 24 3690955424 ps
T99 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4257967745 May 30 12:36:06 PM PDT 24 May 30 12:37:18 PM PDT 24 610239870 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2656037024 May 30 12:36:01 PM PDT 24 May 30 12:36:14 PM PDT 24 7162059442 ps
T82 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1814705338 May 30 12:36:28 PM PDT 24 May 30 12:36:56 PM PDT 24 857464857 ps
T96 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.593283593 May 30 12:35:41 PM PDT 24 May 30 12:35:55 PM PDT 24 1092317685 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1221830673 May 30 12:36:13 PM PDT 24 May 30 12:36:19 PM PDT 24 87389920 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2429765167 May 30 12:36:16 PM PDT 24 May 30 12:37:26 PM PDT 24 581058405 ps
T105 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3311575528 May 30 12:36:14 PM PDT 24 May 30 12:37:33 PM PDT 24 2225719325 ps
T389 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1963373595 May 30 12:36:22 PM PDT 24 May 30 12:36:38 PM PDT 24 7835281480 ps
T390 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3343986869 May 30 12:36:15 PM PDT 24 May 30 12:36:24 PM PDT 24 758979853 ps
T391 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.806948542 May 30 12:36:07 PM PDT 24 May 30 12:36:23 PM PDT 24 1707398219 ps
T392 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2488598156 May 30 12:36:17 PM PDT 24 May 30 12:36:32 PM PDT 24 1980324701 ps
T393 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.30921180 May 30 12:36:00 PM PDT 24 May 30 12:36:11 PM PDT 24 5967653291 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3086529024 May 30 12:35:59 PM PDT 24 May 30 12:36:17 PM PDT 24 2264713180 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2852616986 May 30 12:36:11 PM PDT 24 May 30 12:36:26 PM PDT 24 1486275861 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2101364046 May 30 12:36:06 PM PDT 24 May 30 12:36:12 PM PDT 24 85783132 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4049755018 May 30 12:36:19 PM PDT 24 May 30 12:37:36 PM PDT 24 1648806807 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.167688113 May 30 12:36:03 PM PDT 24 May 30 12:36:19 PM PDT 24 3654479861 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.747195583 May 30 12:36:09 PM PDT 24 May 30 12:37:29 PM PDT 24 51084898187 ps
T397 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1316928173 May 30 12:36:15 PM PDT 24 May 30 12:36:27 PM PDT 24 865847607 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3748900085 May 30 12:36:08 PM PDT 24 May 30 12:36:28 PM PDT 24 2116461505 ps
T88 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4157750427 May 30 12:36:15 PM PDT 24 May 30 12:36:24 PM PDT 24 5757975941 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.810243880 May 30 12:36:11 PM PDT 24 May 30 12:37:25 PM PDT 24 962262610 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3298378247 May 30 12:36:09 PM PDT 24 May 30 12:36:28 PM PDT 24 8257999249 ps
T401 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.170856004 May 30 12:36:10 PM PDT 24 May 30 12:36:26 PM PDT 24 949906214 ps
T402 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2272566394 May 30 12:36:15 PM PDT 24 May 30 12:36:22 PM PDT 24 102033013 ps
T403 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4065723836 May 30 12:36:28 PM PDT 24 May 30 12:36:43 PM PDT 24 1408726144 ps
T404 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2016681055 May 30 12:36:04 PM PDT 24 May 30 12:36:19 PM PDT 24 1233347074 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1520556768 May 30 12:36:09 PM PDT 24 May 30 12:36:14 PM PDT 24 87304131 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2313835032 May 30 12:36:01 PM PDT 24 May 30 12:36:16 PM PDT 24 1460806475 ps
T407 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.836461133 May 30 12:36:12 PM PDT 24 May 30 12:36:20 PM PDT 24 1201331723 ps
T408 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2323751561 May 30 12:36:14 PM PDT 24 May 30 12:36:26 PM PDT 24 518974567 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3851809294 May 30 12:36:25 PM PDT 24 May 30 12:36:35 PM PDT 24 334390204 ps
T410 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2679249380 May 30 12:36:19 PM PDT 24 May 30 12:36:32 PM PDT 24 5987269638 ps
T411 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3068434587 May 30 12:36:24 PM PDT 24 May 30 12:36:34 PM PDT 24 2975587154 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1222723476 May 30 12:36:13 PM PDT 24 May 30 12:36:33 PM PDT 24 5209993219 ps
T413 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2136703657 May 30 12:36:25 PM PDT 24 May 30 12:36:41 PM PDT 24 6374280407 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2869645342 May 30 12:35:53 PM PDT 24 May 30 12:36:41 PM PDT 24 1927578141 ps
T100 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4220577689 May 30 12:36:07 PM PDT 24 May 30 12:37:22 PM PDT 24 1451514031 ps
T414 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.398640232 May 30 12:36:04 PM PDT 24 May 30 12:36:16 PM PDT 24 603425560 ps
T415 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2554625571 May 30 12:36:10 PM PDT 24 May 30 12:36:24 PM PDT 24 1364097459 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2279891517 May 30 12:36:02 PM PDT 24 May 30 12:36:18 PM PDT 24 13434133970 ps
T416 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3149492012 May 30 12:36:27 PM PDT 24 May 30 12:37:33 PM PDT 24 8731519611 ps
T417 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4198501176 May 30 12:36:10 PM PDT 24 May 30 12:37:07 PM PDT 24 25043859198 ps
T418 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2363396829 May 30 12:36:09 PM PDT 24 May 30 12:36:15 PM PDT 24 138217584 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4197634858 May 30 12:36:00 PM PDT 24 May 30 12:36:05 PM PDT 24 96692711 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1366191678 May 30 12:36:12 PM PDT 24 May 30 12:36:22 PM PDT 24 2119674998 ps
T89 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2505920645 May 30 12:36:11 PM PDT 24 May 30 12:36:27 PM PDT 24 7187766109 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2074283524 May 30 12:36:07 PM PDT 24 May 30 12:36:20 PM PDT 24 1538124820 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2295041182 May 30 12:36:03 PM PDT 24 May 30 12:36:10 PM PDT 24 1391455431 ps
T423 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.194715893 May 30 12:36:10 PM PDT 24 May 30 12:36:19 PM PDT 24 1548888425 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.615826815 May 30 12:36:17 PM PDT 24 May 30 12:36:33 PM PDT 24 1771095374 ps
T425 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3709413637 May 30 12:36:18 PM PDT 24 May 30 12:36:29 PM PDT 24 728754337 ps
T85 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2746906333 May 30 12:36:10 PM PDT 24 May 30 12:36:54 PM PDT 24 8088079375 ps
T86 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1706612843 May 30 12:36:06 PM PDT 24 May 30 12:36:26 PM PDT 24 369559067 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3409306970 May 30 12:36:11 PM PDT 24 May 30 12:37:24 PM PDT 24 1926841008 ps
T106 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1889304054 May 30 12:36:12 PM PDT 24 May 30 12:37:32 PM PDT 24 2150737188 ps
T90 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1217340823 May 30 12:36:00 PM PDT 24 May 30 12:36:40 PM PDT 24 1847045853 ps
T426 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2316110774 May 30 12:36:23 PM PDT 24 May 30 12:36:34 PM PDT 24 1847768178 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2601911181 May 30 12:36:09 PM PDT 24 May 30 12:36:15 PM PDT 24 168076281 ps
T428 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2455857210 May 30 12:36:13 PM PDT 24 May 30 12:36:32 PM PDT 24 8479385342 ps
T429 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3275985865 May 30 12:36:04 PM PDT 24 May 30 12:36:09 PM PDT 24 555106504 ps
T430 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2100536344 May 30 12:36:10 PM PDT 24 May 30 12:36:21 PM PDT 24 807839978 ps
T431 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1033988919 May 30 12:36:09 PM PDT 24 May 30 12:36:37 PM PDT 24 563388011 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.147833290 May 30 12:36:28 PM PDT 24 May 30 12:36:47 PM PDT 24 1490494905 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1839584204 May 30 12:36:07 PM PDT 24 May 30 12:36:20 PM PDT 24 2471671939 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2672728069 May 30 12:35:52 PM PDT 24 May 30 12:36:01 PM PDT 24 110549569 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2307154496 May 30 12:36:09 PM PDT 24 May 30 12:36:31 PM PDT 24 1997824209 ps
T436 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3884879581 May 30 12:36:17 PM PDT 24 May 30 12:36:23 PM PDT 24 346365919 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3927167142 May 30 12:36:21 PM PDT 24 May 30 12:36:35 PM PDT 24 7346194946 ps
T438 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3596083757 May 30 12:36:20 PM PDT 24 May 30 12:36:40 PM PDT 24 394800316 ps
T107 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1422007784 May 30 12:36:19 PM PDT 24 May 30 12:37:39 PM PDT 24 2022586099 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.805312609 May 30 12:36:10 PM PDT 24 May 30 12:37:24 PM PDT 24 11535808331 ps
T439 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1553684643 May 30 12:36:17 PM PDT 24 May 30 12:36:34 PM PDT 24 1938702460 ps
T87 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3322520321 May 30 12:36:10 PM PDT 24 May 30 12:37:32 PM PDT 24 38083815866 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2925068668 May 30 12:36:08 PM PDT 24 May 30 12:36:21 PM PDT 24 5823433867 ps
T441 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2844783495 May 30 12:36:14 PM PDT 24 May 30 12:37:28 PM PDT 24 4658303991 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2843908155 May 30 12:36:07 PM PDT 24 May 30 12:36:12 PM PDT 24 89819908 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1836401796 May 30 12:36:05 PM PDT 24 May 30 12:36:13 PM PDT 24 1308816397 ps
T444 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2853736366 May 30 12:36:27 PM PDT 24 May 30 12:37:04 PM PDT 24 556650315 ps
T445 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4175315045 May 30 12:36:20 PM PDT 24 May 30 12:37:31 PM PDT 24 1331281894 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1805109573 May 30 12:36:03 PM PDT 24 May 30 12:36:16 PM PDT 24 3809422358 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2084585634 May 30 12:36:12 PM PDT 24 May 30 12:36:30 PM PDT 24 8793148186 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3604994229 May 30 12:35:59 PM PDT 24 May 30 12:36:07 PM PDT 24 604634289 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.625357979 May 30 12:35:55 PM PDT 24 May 30 12:36:04 PM PDT 24 421870813 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4095328531 May 30 12:36:06 PM PDT 24 May 30 12:36:41 PM PDT 24 2599695892 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2345007435 May 30 12:36:13 PM PDT 24 May 30 12:36:27 PM PDT 24 1365828154 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3540422573 May 30 12:36:10 PM PDT 24 May 30 12:36:26 PM PDT 24 7890248092 ps
T453 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2908107751 May 30 12:36:10 PM PDT 24 May 30 12:36:23 PM PDT 24 5129626932 ps
T454 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.695823024 May 30 12:36:12 PM PDT 24 May 30 12:36:56 PM PDT 24 1207311091 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3049204666 May 30 12:36:06 PM PDT 24 May 30 12:36:18 PM PDT 24 3705096933 ps
T456 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.992534461 May 30 12:36:01 PM PDT 24 May 30 12:37:14 PM PDT 24 6536974634 ps
T457 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1465365277 May 30 12:36:09 PM PDT 24 May 30 12:36:19 PM PDT 24 125453166 ps
T458 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1084637390 May 30 12:36:10 PM PDT 24 May 30 12:36:16 PM PDT 24 347903667 ps
T459 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1586295012 May 30 12:36:01 PM PDT 24 May 30 12:36:13 PM PDT 24 1184095326 ps
T460 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.593159630 May 30 12:36:17 PM PDT 24 May 30 12:36:32 PM PDT 24 1464125832 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3908687555 May 30 12:36:07 PM PDT 24 May 30 12:36:20 PM PDT 24 2774248957 ps
T462 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3852096714 May 30 12:36:09 PM PDT 24 May 30 12:36:28 PM PDT 24 1554060522 ps

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2163336014
Short name T9
Test name
Test status
Simulation time 5534992369 ps
CPU time 56.05 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:36:34 PM PDT 24
Peak memory 219288 kb
Host smart-26794a01-f0ce-4e2b-b64b-ef021a0c12f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163336014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2163336014
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1130760933
Short name T13
Test name
Test status
Simulation time 96992963731 ps
CPU time 891.25 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:50:44 PM PDT 24
Peak memory 235824 kb
Host smart-68a71e74-f6b4-4923-9059-0c19b7444d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130760933 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1130760933
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.670141618
Short name T22
Test name
Test status
Simulation time 17315456952 ps
CPU time 137.7 seconds
Started May 30 12:35:28 PM PDT 24
Finished May 30 12:37:47 PM PDT 24
Peak memory 230020 kb
Host smart-ff7605a3-8b2f-461c-b938-b185c17b81f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670141618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.670141618
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3765630264
Short name T14
Test name
Test status
Simulation time 3058397614 ps
CPU time 141.32 seconds
Started May 30 12:35:46 PM PDT 24
Finished May 30 12:38:08 PM PDT 24
Peak memory 237788 kb
Host smart-67ca2b06-438e-41ce-87ba-0122e24e1db9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765630264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3765630264
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4257967745
Short name T99
Test name
Test status
Simulation time 610239870 ps
CPU time 71.06 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:37:18 PM PDT 24
Peak memory 211152 kb
Host smart-00819948-6348-4ff7-99ae-e100983b5416
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257967745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4257967745
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.929277938
Short name T16
Test name
Test status
Simulation time 158543775469 ps
CPU time 1469.89 seconds
Started May 30 12:35:28 PM PDT 24
Finished May 30 12:59:59 PM PDT 24
Peak memory 236064 kb
Host smart-8d4af1d2-827a-4974-a86a-ba46db4c501b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929277938 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.929277938
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.733372087
Short name T36
Test name
Test status
Simulation time 565829588 ps
CPU time 53.66 seconds
Started May 30 12:35:15 PM PDT 24
Finished May 30 12:36:11 PM PDT 24
Peak memory 237076 kb
Host smart-f894870c-22ad-4183-a55d-e4727f67fc51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733372087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.733372087
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3869302915
Short name T78
Test name
Test status
Simulation time 3632371579 ps
CPU time 45.17 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:36:58 PM PDT 24
Peak memory 211236 kb
Host smart-492156f5-1ad4-4d54-9143-b31477a8be0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869302915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3869302915
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3409306970
Short name T101
Test name
Test status
Simulation time 1926841008 ps
CPU time 71.07 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:37:24 PM PDT 24
Peak memory 211148 kb
Host smart-c4a8ecdb-676a-4a8c-a6d5-b8c7e11f3a02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409306970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3409306970
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3411428256
Short name T1
Test name
Test status
Simulation time 346870682 ps
CPU time 4.05 seconds
Started May 30 12:35:46 PM PDT 24
Finished May 30 12:35:51 PM PDT 24
Peak memory 210980 kb
Host smart-229b97f5-df89-416c-98bd-e10121df5612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411428256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3411428256
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3353688258
Short name T67
Test name
Test status
Simulation time 1390090675 ps
CPU time 11.51 seconds
Started May 30 12:35:56 PM PDT 24
Finished May 30 12:36:09 PM PDT 24
Peak memory 211124 kb
Host smart-028f9342-7442-4970-9290-25bdfb80ca75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353688258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3353688258
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1177832536
Short name T123
Test name
Test status
Simulation time 2195164293 ps
CPU time 16.3 seconds
Started May 30 12:35:01 PM PDT 24
Finished May 30 12:35:18 PM PDT 24
Peak memory 211820 kb
Host smart-d9ef8df4-17ac-4918-bcd4-560e1fcb9ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177832536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1177832536
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1924208179
Short name T204
Test name
Test status
Simulation time 2923811657 ps
CPU time 27.43 seconds
Started May 30 12:35:26 PM PDT 24
Finished May 30 12:35:54 PM PDT 24
Peak memory 212372 kb
Host smart-6c21713a-d348-494f-9e28-3c1646bd48e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924208179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1924208179
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3388114293
Short name T24
Test name
Test status
Simulation time 2623399344 ps
CPU time 24.34 seconds
Started May 30 12:35:39 PM PDT 24
Finished May 30 12:36:05 PM PDT 24
Peak memory 211936 kb
Host smart-47543459-a09d-49f0-8b66-05517b18a8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388114293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3388114293
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3488090093
Short name T5
Test name
Test status
Simulation time 8753986797 ps
CPU time 77.89 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:36:54 PM PDT 24
Peak memory 215952 kb
Host smart-da615990-850f-4149-8b47-0c83463ee108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488090093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3488090093
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2869645342
Short name T104
Test name
Test status
Simulation time 1927578141 ps
CPU time 47.33 seconds
Started May 30 12:35:53 PM PDT 24
Finished May 30 12:36:41 PM PDT 24
Peak memory 213048 kb
Host smart-3d6c7ae0-4894-47f7-b9ec-d991db182592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869645342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2869645342
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1422007784
Short name T107
Test name
Test status
Simulation time 2022586099 ps
CPU time 78.59 seconds
Started May 30 12:36:19 PM PDT 24
Finished May 30 12:37:39 PM PDT 24
Peak memory 212148 kb
Host smart-ecf9a357-dc87-45e0-84ca-ab351ce682df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422007784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1422007784
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.593283593
Short name T96
Test name
Test status
Simulation time 1092317685 ps
CPU time 7.8 seconds
Started May 30 12:35:41 PM PDT 24
Finished May 30 12:35:55 PM PDT 24
Peak memory 211144 kb
Host smart-fc5132c3-0095-417f-9847-7ede425498d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593283593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.593283593
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.860629545
Short name T18
Test name
Test status
Simulation time 200317770664 ps
CPU time 1765.22 seconds
Started May 30 12:35:38 PM PDT 24
Finished May 30 01:05:05 PM PDT 24
Peak memory 235792 kb
Host smart-d0724055-618d-4fb2-943c-46a2f0ddca80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860629545 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.860629545
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3086529024
Short name T394
Test name
Test status
Simulation time 2264713180 ps
CPU time 16.25 seconds
Started May 30 12:35:59 PM PDT 24
Finished May 30 12:36:17 PM PDT 24
Peak memory 211204 kb
Host smart-565f202a-916f-4e33-a883-137dcac4601b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086529024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3086529024
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1487424285
Short name T386
Test name
Test status
Simulation time 3690955424 ps
CPU time 15.39 seconds
Started May 30 12:35:56 PM PDT 24
Finished May 30 12:36:13 PM PDT 24
Peak memory 211212 kb
Host smart-05275c1b-7dc9-442c-8fb6-995bdc114aad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487424285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1487424285
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2295041182
Short name T422
Test name
Test status
Simulation time 1391455431 ps
CPU time 6.12 seconds
Started May 30 12:36:03 PM PDT 24
Finished May 30 12:36:10 PM PDT 24
Peak memory 213040 kb
Host smart-1e934d35-9273-4cc6-853d-b5723df86d96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295041182 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2295041182
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1805109573
Short name T446
Test name
Test status
Simulation time 3809422358 ps
CPU time 11.83 seconds
Started May 30 12:36:03 PM PDT 24
Finished May 30 12:36:16 PM PDT 24
Peak memory 211196 kb
Host smart-0c0d46a2-d5ad-4281-95f7-1300b95a230d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805109573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1805109573
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2656037024
Short name T387
Test name
Test status
Simulation time 7162059442 ps
CPU time 11.63 seconds
Started May 30 12:36:01 PM PDT 24
Finished May 30 12:36:14 PM PDT 24
Peak memory 211068 kb
Host smart-ce44aeab-a35c-4d39-a7a8-3e25ae5b34b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656037024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2656037024
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3089788904
Short name T377
Test name
Test status
Simulation time 175608124 ps
CPU time 4.03 seconds
Started May 30 12:36:01 PM PDT 24
Finished May 30 12:36:06 PM PDT 24
Peak memory 211032 kb
Host smart-b69236ee-aab3-4e3d-9e5d-d33abe279851
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089788904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3089788904
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.747195583
Short name T98
Test name
Test status
Simulation time 51084898187 ps
CPU time 78.37 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:37:29 PM PDT 24
Peak memory 211244 kb
Host smart-fce8acad-cf0d-47b7-8862-cf6d049e181a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747195583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.747195583
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2672728069
Short name T434
Test name
Test status
Simulation time 110549569 ps
CPU time 7.81 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 219384 kb
Host smart-2a56b96a-d3ca-4d91-83de-93b1a3f5ad45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672728069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2672728069
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.167688113
Short name T83
Test name
Test status
Simulation time 3654479861 ps
CPU time 14.48 seconds
Started May 30 12:36:03 PM PDT 24
Finished May 30 12:36:19 PM PDT 24
Peak memory 211164 kb
Host smart-bd48de08-1f8f-4523-bf39-a802814fbd1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167688113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.167688113
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.676242820
Short name T374
Test name
Test status
Simulation time 3735718594 ps
CPU time 14.53 seconds
Started May 30 12:36:04 PM PDT 24
Finished May 30 12:36:19 PM PDT 24
Peak memory 211188 kb
Host smart-02b1455d-bc71-4e86-b455-e4f77899ad3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676242820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.676242820
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2192174557
Short name T79
Test name
Test status
Simulation time 2500264740 ps
CPU time 11.14 seconds
Started May 30 12:35:45 PM PDT 24
Finished May 30 12:35:57 PM PDT 24
Peak memory 211220 kb
Host smart-7ea025f5-88cf-409e-81c9-494065152151
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192174557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2192174557
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.206002487
Short name T382
Test name
Test status
Simulation time 363439291 ps
CPU time 4.41 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:15 PM PDT 24
Peak memory 213240 kb
Host smart-9fd5705e-2c61-409e-9ed9-7a3437f68cb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206002487 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.206002487
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2691267696
Short name T372
Test name
Test status
Simulation time 2135557858 ps
CPU time 16.58 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:27 PM PDT 24
Peak memory 211192 kb
Host smart-347ad92c-c999-49dd-9223-5fd2ee53abb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691267696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2691267696
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1520556768
Short name T405
Test name
Test status
Simulation time 87304131 ps
CPU time 4.09 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:14 PM PDT 24
Peak memory 211000 kb
Host smart-df08d5a3-d8b6-432b-b60e-c0d60f58a424
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520556768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1520556768
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3604994229
Short name T448
Test name
Test status
Simulation time 604634289 ps
CPU time 7.58 seconds
Started May 30 12:35:59 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 211048 kb
Host smart-06b5fcf0-5b5c-41f0-b8be-09e6cc2c75ef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604994229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3604994229
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1244024377
Short name T92
Test name
Test status
Simulation time 6585544186 ps
CPU time 58.3 seconds
Started May 30 12:36:08 PM PDT 24
Finished May 30 12:37:08 PM PDT 24
Peak memory 211336 kb
Host smart-2d3379db-bcda-4332-a594-f4702903e59c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244024377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1244024377
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4197634858
Short name T419
Test name
Test status
Simulation time 96692711 ps
CPU time 4.25 seconds
Started May 30 12:36:00 PM PDT 24
Finished May 30 12:36:05 PM PDT 24
Peak memory 211084 kb
Host smart-c23983a9-d70b-432d-954a-dc5497e48063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197634858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4197634858
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.625357979
Short name T449
Test name
Test status
Simulation time 421870813 ps
CPU time 7.58 seconds
Started May 30 12:35:55 PM PDT 24
Finished May 30 12:36:04 PM PDT 24
Peak memory 219408 kb
Host smart-cd84eb1c-4842-44dd-a422-ff18c4edc15a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625357979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.625357979
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.992534461
Short name T456
Test name
Test status
Simulation time 6536974634 ps
CPU time 71.47 seconds
Started May 30 12:36:01 PM PDT 24
Finished May 30 12:37:14 PM PDT 24
Peak memory 212420 kb
Host smart-6dba900b-7eed-433e-aab3-2582bbd4ac50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992534461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.992534461
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1839584204
Short name T433
Test name
Test status
Simulation time 2471671939 ps
CPU time 11.77 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:20 PM PDT 24
Peak memory 219440 kb
Host smart-0710d158-a735-435d-a346-2b338a73d17c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839584204 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1839584204
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2505920645
Short name T89
Test name
Test status
Simulation time 7187766109 ps
CPU time 14.6 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:36:27 PM PDT 24
Peak memory 211200 kb
Host smart-42f06f69-51b3-4312-a263-56b44c41828c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505920645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2505920645
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1033988919
Short name T431
Test name
Test status
Simulation time 563388011 ps
CPU time 27.38 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:37 PM PDT 24
Peak memory 211132 kb
Host smart-e1ae85ea-70c6-4392-96ca-c14583daf317
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033988919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1033988919
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.620798290
Short name T95
Test name
Test status
Simulation time 2053173642 ps
CPU time 6.8 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:36:13 PM PDT 24
Peak memory 211112 kb
Host smart-e737c32f-7da1-4f57-87e2-dbd6afd3d7a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620798290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.620798290
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3852096714
Short name T462
Test name
Test status
Simulation time 1554060522 ps
CPU time 17.32 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:28 PM PDT 24
Peak memory 219468 kb
Host smart-45064345-971c-40ae-86af-cdb0cb82d4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852096714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3852096714
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1863489315
Short name T60
Test name
Test status
Simulation time 6811193568 ps
CPU time 74.61 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:37:24 PM PDT 24
Peak memory 219496 kb
Host smart-7e71ce0b-0d6a-4211-912b-18979ce68abb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863489315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1863489315
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.194715893
Short name T423
Test name
Test status
Simulation time 1548888425 ps
CPU time 6.76 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:36:19 PM PDT 24
Peak memory 219396 kb
Host smart-05e1e76f-b9eb-4e2c-bd23-e56a3c344195
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194715893 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.194715893
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.806948542
Short name T391
Test name
Test status
Simulation time 1707398219 ps
CPU time 14.4 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:23 PM PDT 24
Peak memory 211116 kb
Host smart-a4fdc9ca-bf9d-4ef9-8d86-27b672ae06aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806948542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.806948542
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4198501176
Short name T417
Test name
Test status
Simulation time 25043859198 ps
CPU time 55.47 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:37:07 PM PDT 24
Peak memory 211212 kb
Host smart-51006d37-3b85-4bfd-8779-7d3c35646da5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198501176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4198501176
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3709413637
Short name T425
Test name
Test status
Simulation time 728754337 ps
CPU time 8.79 seconds
Started May 30 12:36:18 PM PDT 24
Finished May 30 12:36:29 PM PDT 24
Peak memory 211168 kb
Host smart-897a47e0-a1a1-4608-8075-2d6e87ea2007
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709413637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3709413637
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1465365277
Short name T457
Test name
Test status
Simulation time 125453166 ps
CPU time 8.49 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:19 PM PDT 24
Peak memory 219404 kb
Host smart-cbb805a1-34de-45dc-9662-343082c8b2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465365277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1465365277
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4049755018
Short name T108
Test name
Test status
Simulation time 1648806807 ps
CPU time 75.73 seconds
Started May 30 12:36:19 PM PDT 24
Finished May 30 12:37:36 PM PDT 24
Peak memory 212088 kb
Host smart-522f5d20-5816-4ab9-b283-6dc59b4c6333
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049755018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4049755018
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1316928173
Short name T397
Test name
Test status
Simulation time 865847607 ps
CPU time 9.88 seconds
Started May 30 12:36:15 PM PDT 24
Finished May 30 12:36:27 PM PDT 24
Peak memory 219472 kb
Host smart-acbe536c-f305-466d-8e77-32980410ba46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316928173 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1316928173
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4153027290
Short name T63
Test name
Test status
Simulation time 1876330998 ps
CPU time 14.92 seconds
Started May 30 12:36:23 PM PDT 24
Finished May 30 12:36:39 PM PDT 24
Peak memory 211156 kb
Host smart-a0f08f48-cc5c-4f26-aa47-b44bd5286cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153027290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4153027290
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.153945159
Short name T380
Test name
Test status
Simulation time 16461642589 ps
CPU time 64.04 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:37:17 PM PDT 24
Peak memory 211216 kb
Host smart-c9d76a18-c92b-4c81-913a-80ba32ca2af3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153945159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.153945159
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3884879581
Short name T436
Test name
Test status
Simulation time 346365919 ps
CPU time 4.12 seconds
Started May 30 12:36:17 PM PDT 24
Finished May 30 12:36:23 PM PDT 24
Peak memory 211172 kb
Host smart-832db8a3-504c-4188-9a82-c69907b55b21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884879581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3884879581
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2488598156
Short name T392
Test name
Test status
Simulation time 1980324701 ps
CPU time 13.32 seconds
Started May 30 12:36:17 PM PDT 24
Finished May 30 12:36:32 PM PDT 24
Peak memory 219504 kb
Host smart-962ecf51-e426-4264-b8a2-c2b3d5557ac7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488598156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2488598156
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2844783495
Short name T441
Test name
Test status
Simulation time 4658303991 ps
CPU time 72.86 seconds
Started May 30 12:36:14 PM PDT 24
Finished May 30 12:37:28 PM PDT 24
Peak memory 219368 kb
Host smart-764dd116-b3c1-46f7-be4d-df73ec6e3b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844783495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2844783495
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.615826815
Short name T424
Test name
Test status
Simulation time 1771095374 ps
CPU time 14.92 seconds
Started May 30 12:36:17 PM PDT 24
Finished May 30 12:36:33 PM PDT 24
Peak memory 213452 kb
Host smart-bb0bda53-4ab8-4eb7-8608-a52040aabd0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615826815 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.615826815
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3100160169
Short name T81
Test name
Test status
Simulation time 8038079555 ps
CPU time 15.43 seconds
Started May 30 12:36:16 PM PDT 24
Finished May 30 12:36:33 PM PDT 24
Peak memory 211228 kb
Host smart-d6acb1d8-d5c7-41c1-8b7a-765b30fa65fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100160169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3100160169
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.907596830
Short name T91
Test name
Test status
Simulation time 454370419 ps
CPU time 7.41 seconds
Started May 30 12:36:14 PM PDT 24
Finished May 30 12:36:23 PM PDT 24
Peak memory 211160 kb
Host smart-9e310c7b-964d-47ab-a0b4-0b166d5d2467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907596830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.907596830
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.207445194
Short name T366
Test name
Test status
Simulation time 13128846461 ps
CPU time 17.67 seconds
Started May 30 12:36:16 PM PDT 24
Finished May 30 12:36:35 PM PDT 24
Peak memory 219452 kb
Host smart-90dee8b1-0254-4bc0-bc8d-a129030927df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207445194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.207445194
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4175315045
Short name T445
Test name
Test status
Simulation time 1331281894 ps
CPU time 70.44 seconds
Started May 30 12:36:20 PM PDT 24
Finished May 30 12:37:31 PM PDT 24
Peak memory 212172 kb
Host smart-8c9bffbb-5e21-4e26-8a21-29cf67e4d79a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175315045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4175315045
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3068434587
Short name T411
Test name
Test status
Simulation time 2975587154 ps
CPU time 8.93 seconds
Started May 30 12:36:24 PM PDT 24
Finished May 30 12:36:34 PM PDT 24
Peak memory 213744 kb
Host smart-74140a1d-98e6-482e-acfe-60151977a89c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068434587 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3068434587
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3704672900
Short name T69
Test name
Test status
Simulation time 4434402554 ps
CPU time 11.56 seconds
Started May 30 12:36:24 PM PDT 24
Finished May 30 12:36:36 PM PDT 24
Peak memory 211196 kb
Host smart-347cc59c-fef9-4010-9dfa-9c7821abf681
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704672900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3704672900
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3179644029
Short name T97
Test name
Test status
Simulation time 1177952043 ps
CPU time 26.71 seconds
Started May 30 12:36:25 PM PDT 24
Finished May 30 12:36:53 PM PDT 24
Peak memory 211156 kb
Host smart-22ffce30-1768-4a38-a9a6-a510dfa867b3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179644029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3179644029
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2100536344
Short name T430
Test name
Test status
Simulation time 807839978 ps
CPU time 9.06 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:36:21 PM PDT 24
Peak memory 211236 kb
Host smart-72522c94-cf0d-4d4d-8734-393498462ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100536344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2100536344
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3851809294
Short name T409
Test name
Test status
Simulation time 334390204 ps
CPU time 8.99 seconds
Started May 30 12:36:25 PM PDT 24
Finished May 30 12:36:35 PM PDT 24
Peak memory 219396 kb
Host smart-db867c43-251a-46e6-b11a-eef579887f33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851809294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3851809294
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3311575528
Short name T105
Test name
Test status
Simulation time 2225719325 ps
CPU time 77.21 seconds
Started May 30 12:36:14 PM PDT 24
Finished May 30 12:37:33 PM PDT 24
Peak memory 219496 kb
Host smart-b4875eb3-bdb9-4a24-a3db-5cbbb1bbdfbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311575528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3311575528
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2136703657
Short name T413
Test name
Test status
Simulation time 6374280407 ps
CPU time 14.64 seconds
Started May 30 12:36:25 PM PDT 24
Finished May 30 12:36:41 PM PDT 24
Peak memory 219520 kb
Host smart-66bd6cee-4f0f-45d9-b446-51e1e248bce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136703657 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2136703657
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1298423804
Short name T71
Test name
Test status
Simulation time 1222077025 ps
CPU time 11.44 seconds
Started May 30 12:36:16 PM PDT 24
Finished May 30 12:36:29 PM PDT 24
Peak memory 211256 kb
Host smart-1c5eb3c5-f815-4c87-88d8-fa584eb12912
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298423804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1298423804
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4219933947
Short name T75
Test name
Test status
Simulation time 31777426116 ps
CPU time 49.52 seconds
Started May 30 12:36:12 PM PDT 24
Finished May 30 12:37:03 PM PDT 24
Peak memory 211344 kb
Host smart-c4a6b773-615d-4fa8-89fa-54e389e5dc41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219933947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4219933947
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1553684643
Short name T439
Test name
Test status
Simulation time 1938702460 ps
CPU time 15.27 seconds
Started May 30 12:36:17 PM PDT 24
Finished May 30 12:36:34 PM PDT 24
Peak memory 211244 kb
Host smart-8fccad92-4b94-4e7f-97ff-0f41e2c4b98e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553684643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1553684643
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2455857210
Short name T428
Test name
Test status
Simulation time 8479385342 ps
CPU time 18.09 seconds
Started May 30 12:36:13 PM PDT 24
Finished May 30 12:36:32 PM PDT 24
Peak memory 219564 kb
Host smart-f496d29e-97a5-42c1-a907-1b0391441f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455857210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2455857210
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1889304054
Short name T106
Test name
Test status
Simulation time 2150737188 ps
CPU time 78.32 seconds
Started May 30 12:36:12 PM PDT 24
Finished May 30 12:37:32 PM PDT 24
Peak memory 211896 kb
Host smart-bedbb342-2d78-4080-a18e-b8c5beeaa0a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889304054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1889304054
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.593159630
Short name T460
Test name
Test status
Simulation time 1464125832 ps
CPU time 13 seconds
Started May 30 12:36:17 PM PDT 24
Finished May 30 12:36:32 PM PDT 24
Peak memory 219448 kb
Host smart-b85c400c-21ea-46ef-87c8-75f8bf7632c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593159630 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.593159630
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4157750427
Short name T88
Test name
Test status
Simulation time 5757975941 ps
CPU time 8 seconds
Started May 30 12:36:15 PM PDT 24
Finished May 30 12:36:24 PM PDT 24
Peak memory 211216 kb
Host smart-7dce0d24-725b-48c9-8298-c08025468e3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157750427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4157750427
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3149492012
Short name T416
Test name
Test status
Simulation time 8731519611 ps
CPU time 65.14 seconds
Started May 30 12:36:27 PM PDT 24
Finished May 30 12:37:33 PM PDT 24
Peak memory 211240 kb
Host smart-cd868998-9910-43f9-af48-c9059e0ba5c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149492012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3149492012
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4065723836
Short name T403
Test name
Test status
Simulation time 1408726144 ps
CPU time 13.9 seconds
Started May 30 12:36:28 PM PDT 24
Finished May 30 12:36:43 PM PDT 24
Peak memory 211176 kb
Host smart-cf7e6b0b-ddf5-4036-a68e-34b6cc041664
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065723836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4065723836
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3525224872
Short name T384
Test name
Test status
Simulation time 6438013565 ps
CPU time 14.45 seconds
Started May 30 12:36:14 PM PDT 24
Finished May 30 12:36:30 PM PDT 24
Peak memory 217160 kb
Host smart-5a475290-7cd7-4400-8e96-4c530bafb7c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525224872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3525224872
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2429765167
Short name T102
Test name
Test status
Simulation time 581058405 ps
CPU time 68.29 seconds
Started May 30 12:36:16 PM PDT 24
Finished May 30 12:37:26 PM PDT 24
Peak memory 212352 kb
Host smart-bef70f67-bc03-4940-8f03-3138942a9c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429765167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2429765167
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2272566394
Short name T402
Test name
Test status
Simulation time 102033013 ps
CPU time 4.91 seconds
Started May 30 12:36:15 PM PDT 24
Finished May 30 12:36:22 PM PDT 24
Peak memory 219440 kb
Host smart-86320182-5af9-45bb-8f47-750a9d05c5f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272566394 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2272566394
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3343986869
Short name T390
Test name
Test status
Simulation time 758979853 ps
CPU time 6.72 seconds
Started May 30 12:36:15 PM PDT 24
Finished May 30 12:36:24 PM PDT 24
Peak memory 211260 kb
Host smart-39277089-909e-46e1-a726-57f67277c3d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343986869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3343986869
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.236818742
Short name T70
Test name
Test status
Simulation time 378642824 ps
CPU time 18.48 seconds
Started May 30 12:36:17 PM PDT 24
Finished May 30 12:36:37 PM PDT 24
Peak memory 211168 kb
Host smart-b063740b-5673-453d-ac0d-b74066f37cd5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236818742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.236818742
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1222723476
Short name T412
Test name
Test status
Simulation time 5209993219 ps
CPU time 18.58 seconds
Started May 30 12:36:13 PM PDT 24
Finished May 30 12:36:33 PM PDT 24
Peak memory 211200 kb
Host smart-8d47ba5a-bfe3-4d57-a0e4-c5e4791e9b85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222723476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1222723476
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.455076215
Short name T378
Test name
Test status
Simulation time 346842067 ps
CPU time 7.72 seconds
Started May 30 12:36:15 PM PDT 24
Finished May 30 12:36:24 PM PDT 24
Peak memory 219368 kb
Host smart-a1c1e31b-6c41-4871-b94b-c530bc352e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455076215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.455076215
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2083593909
Short name T370
Test name
Test status
Simulation time 465542683 ps
CPU time 7.57 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:36:21 PM PDT 24
Peak memory 212628 kb
Host smart-f1044caf-eabf-4c1d-b15d-8b7716ab4fd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083593909 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2083593909
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2542476277
Short name T93
Test name
Test status
Simulation time 7635271980 ps
CPU time 14.97 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 211232 kb
Host smart-48e767f8-5742-4f32-bfae-708ecd3f1ca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542476277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2542476277
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.147833290
Short name T432
Test name
Test status
Simulation time 1490494905 ps
CPU time 18.29 seconds
Started May 30 12:36:28 PM PDT 24
Finished May 30 12:36:47 PM PDT 24
Peak memory 211176 kb
Host smart-4bbbcaf8-e458-415f-91d8-a8548a77d3f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147833290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.147833290
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3275985865
Short name T429
Test name
Test status
Simulation time 555106504 ps
CPU time 4.28 seconds
Started May 30 12:36:04 PM PDT 24
Finished May 30 12:36:09 PM PDT 24
Peak memory 211140 kb
Host smart-3fc16f3f-9cce-4748-b09e-0780a27037ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275985865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3275985865
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2323751561
Short name T408
Test name
Test status
Simulation time 518974567 ps
CPU time 9.56 seconds
Started May 30 12:36:14 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 219344 kb
Host smart-dede525b-ab6d-4ea8-b1b0-07b8430265c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323751561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2323751561
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3857540310
Short name T61
Test name
Test status
Simulation time 8727562552 ps
CPU time 78.8 seconds
Started May 30 12:36:15 PM PDT 24
Finished May 30 12:37:36 PM PDT 24
Peak memory 212180 kb
Host smart-75462cba-b93d-46ad-a8dc-e1cfaf83565c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857540310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3857540310
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2316110774
Short name T426
Test name
Test status
Simulation time 1847768178 ps
CPU time 9.67 seconds
Started May 30 12:36:23 PM PDT 24
Finished May 30 12:36:34 PM PDT 24
Peak memory 219340 kb
Host smart-3f73ec74-34f9-4286-bcfa-3cab3f45825d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316110774 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2316110774
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2679249380
Short name T410
Test name
Test status
Simulation time 5987269638 ps
CPU time 12.41 seconds
Started May 30 12:36:19 PM PDT 24
Finished May 30 12:36:32 PM PDT 24
Peak memory 211172 kb
Host smart-54853bb2-67d8-4be8-b9ab-0ce7675ee772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679249380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2679249380
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1814705338
Short name T82
Test name
Test status
Simulation time 857464857 ps
CPU time 27 seconds
Started May 30 12:36:28 PM PDT 24
Finished May 30 12:36:56 PM PDT 24
Peak memory 211168 kb
Host smart-6377a4d1-b7d0-4f8f-a64a-92f664870f7a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814705338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1814705338
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1963373595
Short name T389
Test name
Test status
Simulation time 7835281480 ps
CPU time 15.11 seconds
Started May 30 12:36:22 PM PDT 24
Finished May 30 12:36:38 PM PDT 24
Peak memory 211160 kb
Host smart-0514840b-d397-4f0c-8a24-71ec9fd1c623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963373595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1963373595
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.833647935
Short name T371
Test name
Test status
Simulation time 3234213534 ps
CPU time 17.48 seconds
Started May 30 12:36:20 PM PDT 24
Finished May 30 12:36:39 PM PDT 24
Peak memory 219568 kb
Host smart-88ea1c77-3a3b-4fc5-a2ec-8539fa19fa5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833647935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.833647935
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2853736366
Short name T444
Test name
Test status
Simulation time 556650315 ps
CPU time 36.04 seconds
Started May 30 12:36:27 PM PDT 24
Finished May 30 12:37:04 PM PDT 24
Peak memory 211152 kb
Host smart-72557585-e41d-4e6b-84b8-4d8632040f96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853736366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2853736366
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1221830673
Short name T388
Test name
Test status
Simulation time 87389920 ps
CPU time 4.26 seconds
Started May 30 12:36:13 PM PDT 24
Finished May 30 12:36:19 PM PDT 24
Peak memory 211128 kb
Host smart-d0a589f2-f205-47a9-8545-651d948f786b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221830673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1221830673
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2843908155
Short name T442
Test name
Test status
Simulation time 89819908 ps
CPU time 4.27 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:12 PM PDT 24
Peak memory 211148 kb
Host smart-10e9e6ba-c755-4eac-9f3f-b813cf265c14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843908155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2843908155
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1642663529
Short name T381
Test name
Test status
Simulation time 652969521 ps
CPU time 9.95 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:36:22 PM PDT 24
Peak memory 211152 kb
Host smart-ab8a4e51-34c3-425f-986f-2cf80fea32cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642663529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1642663529
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1836401796
Short name T443
Test name
Test status
Simulation time 1308816397 ps
CPU time 6.95 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:36:13 PM PDT 24
Peak memory 219324 kb
Host smart-0ae38531-0f37-4b28-b474-6399d9e1bd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836401796 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1836401796
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2582678569
Short name T383
Test name
Test status
Simulation time 830899093 ps
CPU time 4.14 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:15 PM PDT 24
Peak memory 211120 kb
Host smart-81ea4c78-ed2c-4dbf-b9d7-5d499b0684a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582678569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2582678569
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2908107751
Short name T453
Test name
Test status
Simulation time 5129626932 ps
CPU time 11.19 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:36:23 PM PDT 24
Peak memory 211156 kb
Host smart-7ae57e9a-460f-4c2d-ba78-398c25080269
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908107751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2908107751
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.666816181
Short name T376
Test name
Test status
Simulation time 3595645912 ps
CPU time 14 seconds
Started May 30 12:35:57 PM PDT 24
Finished May 30 12:36:12 PM PDT 24
Peak memory 211228 kb
Host smart-f3a0b925-cf12-45cc-86e6-9eca02771254
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666816181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
666816181
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4095328531
Short name T450
Test name
Test status
Simulation time 2599695892 ps
CPU time 33.88 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:36:41 PM PDT 24
Peak memory 211228 kb
Host smart-4be089e0-cd17-4fa6-acff-1ac51f6fe8dc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095328531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4095328531
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.301412567
Short name T68
Test name
Test status
Simulation time 1256445300 ps
CPU time 13.5 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 211244 kb
Host smart-42bbd5b6-9627-4696-b573-3dfa441450c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301412567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.301412567
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.398640232
Short name T414
Test name
Test status
Simulation time 603425560 ps
CPU time 10.2 seconds
Started May 30 12:36:04 PM PDT 24
Finished May 30 12:36:16 PM PDT 24
Peak memory 219476 kb
Host smart-11bd502e-f454-4e25-83a4-55554a96cd86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398640232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.398640232
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2279891517
Short name T84
Test name
Test status
Simulation time 13434133970 ps
CPU time 15.21 seconds
Started May 30 12:36:02 PM PDT 24
Finished May 30 12:36:18 PM PDT 24
Peak memory 211228 kb
Host smart-53029a76-cd4e-4247-a117-b7caffc50999
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279891517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2279891517
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3888464053
Short name T62
Test name
Test status
Simulation time 971953400 ps
CPU time 7.47 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:36:15 PM PDT 24
Peak memory 211160 kb
Host smart-baf5c1fc-1ad5-47d7-9002-efdc7ad972f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888464053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3888464053
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3748900085
Short name T398
Test name
Test status
Simulation time 2116461505 ps
CPU time 18.35 seconds
Started May 30 12:36:08 PM PDT 24
Finished May 30 12:36:28 PM PDT 24
Peak memory 211136 kb
Host smart-fcc2664a-46b9-4e0e-93a4-e442acb1dd9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748900085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3748900085
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2313835032
Short name T406
Test name
Test status
Simulation time 1460806475 ps
CPU time 13.41 seconds
Started May 30 12:36:01 PM PDT 24
Finished May 30 12:36:16 PM PDT 24
Peak memory 219352 kb
Host smart-fd82f07a-a767-4006-9fcb-435e8eec4f24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313835032 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2313835032
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2345007435
Short name T451
Test name
Test status
Simulation time 1365828154 ps
CPU time 12.35 seconds
Started May 30 12:36:13 PM PDT 24
Finished May 30 12:36:27 PM PDT 24
Peak memory 211240 kb
Host smart-16d7991d-76f8-466e-94f7-147f2d7c0c56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345007435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2345007435
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2074283524
Short name T421
Test name
Test status
Simulation time 1538124820 ps
CPU time 12.59 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:20 PM PDT 24
Peak memory 211096 kb
Host smart-7c82e8c6-88af-4914-a6f6-a997826c498f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074283524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2074283524
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1084637390
Short name T458
Test name
Test status
Simulation time 347903667 ps
CPU time 4.07 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:36:16 PM PDT 24
Peak memory 211168 kb
Host smart-9c7b1374-5808-4f13-96fc-a5bd0318ac1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084637390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1084637390
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2307154496
Short name T435
Test name
Test status
Simulation time 1997824209 ps
CPU time 15.42 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:31 PM PDT 24
Peak memory 211108 kb
Host smart-2059b878-af08-4f1c-a336-7062fb6b2d0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307154496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2307154496
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3298378247
Short name T400
Test name
Test status
Simulation time 8257999249 ps
CPU time 17.82 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:28 PM PDT 24
Peak memory 219568 kb
Host smart-bff58be5-809f-4735-b9d5-dcac6d4d3d7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298378247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3298378247
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.76223687
Short name T59
Test name
Test status
Simulation time 1037953525 ps
CPU time 39.05 seconds
Started May 30 12:36:01 PM PDT 24
Finished May 30 12:36:41 PM PDT 24
Peak memory 211232 kb
Host smart-372b9848-2786-41bf-b484-b0636b0f48ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76223687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg
_err.76223687
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2601911181
Short name T427
Test name
Test status
Simulation time 168076281 ps
CPU time 4.11 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:15 PM PDT 24
Peak memory 211132 kb
Host smart-5afdd051-e505-4e6a-8e00-9abd4766e571
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601911181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2601911181
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.970779688
Short name T379
Test name
Test status
Simulation time 91087554 ps
CPU time 4.58 seconds
Started May 30 12:36:16 PM PDT 24
Finished May 30 12:36:22 PM PDT 24
Peak memory 211116 kb
Host smart-7e366209-9d3a-4bdd-9f47-2d60af1a54b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970779688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.970779688
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3908687555
Short name T461
Test name
Test status
Simulation time 2774248957 ps
CPU time 11.66 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:20 PM PDT 24
Peak memory 211220 kb
Host smart-53de0d02-9662-4bae-9d77-3bc4a79788c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908687555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3908687555
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3540422573
Short name T452
Test name
Test status
Simulation time 7890248092 ps
CPU time 14.59 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 214408 kb
Host smart-12352e08-54d4-448e-8ad4-346ff8d942f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540422573 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3540422573
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1366191678
Short name T420
Test name
Test status
Simulation time 2119674998 ps
CPU time 7.97 seconds
Started May 30 12:36:12 PM PDT 24
Finished May 30 12:36:22 PM PDT 24
Peak memory 211148 kb
Host smart-547ccb59-5d5c-4559-9ff3-be93365c2dba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366191678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1366191678
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2925068668
Short name T440
Test name
Test status
Simulation time 5823433867 ps
CPU time 12.52 seconds
Started May 30 12:36:08 PM PDT 24
Finished May 30 12:36:21 PM PDT 24
Peak memory 211156 kb
Host smart-8e8dafdd-e90e-4e30-8621-9a6e76d68f03
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925068668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2925068668
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1149983942
Short name T373
Test name
Test status
Simulation time 4127956454 ps
CPU time 7.35 seconds
Started May 30 12:36:18 PM PDT 24
Finished May 30 12:36:27 PM PDT 24
Peak memory 211228 kb
Host smart-cdf07e37-2b3e-4c9e-901d-379501e281e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149983942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1149983942
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3847058211
Short name T77
Test name
Test status
Simulation time 7640420153 ps
CPU time 27.57 seconds
Started May 30 12:36:16 PM PDT 24
Finished May 30 12:36:45 PM PDT 24
Peak memory 211284 kb
Host smart-8b6aa10b-9a8c-4a03-9ad1-957d82063abf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847058211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3847058211
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2852616986
Short name T395
Test name
Test status
Simulation time 1486275861 ps
CPU time 12.88 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 211224 kb
Host smart-b4d9f437-debd-46ed-9707-b866b7308659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852616986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2852616986
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3049204666
Short name T455
Test name
Test status
Simulation time 3705096933 ps
CPU time 11.08 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:36:18 PM PDT 24
Peak memory 219440 kb
Host smart-09247ea2-ca0d-4369-8a7b-402f2e438969
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049204666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3049204666
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1238165675
Short name T368
Test name
Test status
Simulation time 15788590402 ps
CPU time 9.58 seconds
Started May 30 12:36:08 PM PDT 24
Finished May 30 12:36:19 PM PDT 24
Peak memory 219428 kb
Host smart-4653b206-3af1-4e11-9d2f-236efdf078ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238165675 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1238165675
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3714553628
Short name T74
Test name
Test status
Simulation time 158976318 ps
CPU time 4.13 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:36:10 PM PDT 24
Peak memory 211104 kb
Host smart-ded885f0-8720-4d40-b069-a3397152fbf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714553628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3714553628
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1217340823
Short name T90
Test name
Test status
Simulation time 1847045853 ps
CPU time 39.3 seconds
Started May 30 12:36:00 PM PDT 24
Finished May 30 12:36:40 PM PDT 24
Peak memory 211168 kb
Host smart-c87ce694-40f8-4746-9477-def2c8a59410
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217340823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1217340823
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.861045958
Short name T94
Test name
Test status
Simulation time 5457679405 ps
CPU time 12.5 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:36:25 PM PDT 24
Peak memory 211228 kb
Host smart-dccde5c3-767a-4d00-a001-e38c3f91f7f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861045958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.861045958
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2016681055
Short name T404
Test name
Test status
Simulation time 1233347074 ps
CPU time 14.09 seconds
Started May 30 12:36:04 PM PDT 24
Finished May 30 12:36:19 PM PDT 24
Peak memory 219368 kb
Host smart-a5f86892-416c-4ebb-8091-59e3747a711d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016681055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2016681055
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.805312609
Short name T109
Test name
Test status
Simulation time 11535808331 ps
CPU time 72.67 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:37:24 PM PDT 24
Peak memory 212328 kb
Host smart-df2e2f94-008a-46cf-b898-4afbc4c9c66b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805312609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.805312609
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2495362246
Short name T369
Test name
Test status
Simulation time 12092454072 ps
CPU time 14.38 seconds
Started May 30 12:36:04 PM PDT 24
Finished May 30 12:36:20 PM PDT 24
Peak memory 219492 kb
Host smart-be68116d-9171-4e65-85bb-48f71a0b6929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495362246 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2495362246
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2554625571
Short name T415
Test name
Test status
Simulation time 1364097459 ps
CPU time 12.14 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:36:24 PM PDT 24
Peak memory 211104 kb
Host smart-071b617f-ff0c-434c-a426-8d1ae9b78e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554625571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2554625571
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3322520321
Short name T87
Test name
Test status
Simulation time 38083815866 ps
CPU time 80.35 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:37:32 PM PDT 24
Peak memory 211216 kb
Host smart-686afc3a-e35a-417c-92d5-658d8ddd74ad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322520321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3322520321
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2101364046
Short name T396
Test name
Test status
Simulation time 85783132 ps
CPU time 4.35 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:36:12 PM PDT 24
Peak memory 211108 kb
Host smart-5f98bd4b-39d2-46f4-9a13-99c54d51d852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101364046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2101364046
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1921339712
Short name T385
Test name
Test status
Simulation time 193664470 ps
CPU time 7.12 seconds
Started May 30 12:36:08 PM PDT 24
Finished May 30 12:36:17 PM PDT 24
Peak memory 219424 kb
Host smart-4c313104-e9e8-4d03-ba53-10da7abc0b78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921339712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1921339712
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.695823024
Short name T454
Test name
Test status
Simulation time 1207311091 ps
CPU time 42.19 seconds
Started May 30 12:36:12 PM PDT 24
Finished May 30 12:36:56 PM PDT 24
Peak memory 211688 kb
Host smart-ea1f6316-3069-404d-b996-17820a9b0aab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695823024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.695823024
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.30921180
Short name T393
Test name
Test status
Simulation time 5967653291 ps
CPU time 10.02 seconds
Started May 30 12:36:00 PM PDT 24
Finished May 30 12:36:11 PM PDT 24
Peak memory 212780 kb
Host smart-34f5161e-02d4-4416-abde-156a4a923909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30921180 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.30921180
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.836461133
Short name T407
Test name
Test status
Simulation time 1201331723 ps
CPU time 6.07 seconds
Started May 30 12:36:12 PM PDT 24
Finished May 30 12:36:20 PM PDT 24
Peak memory 211260 kb
Host smart-cac76c9b-5d25-4a8e-9a7a-2cd40c739337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836461133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.836461133
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1706612843
Short name T86
Test name
Test status
Simulation time 369559067 ps
CPU time 18.57 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 211124 kb
Host smart-869c9e2a-304c-43bc-87f0-8022d508458f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706612843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1706612843
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1060100231
Short name T73
Test name
Test status
Simulation time 1222076396 ps
CPU time 8.03 seconds
Started May 30 12:36:08 PM PDT 24
Finished May 30 12:36:17 PM PDT 24
Peak memory 211144 kb
Host smart-2d2f954d-280c-4ed9-b685-0b2321603eaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060100231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1060100231
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2720381627
Short name T367
Test name
Test status
Simulation time 12552255907 ps
CPU time 20.97 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:36:27 PM PDT 24
Peak memory 216212 kb
Host smart-6ff3ee48-539d-4504-9f0e-ed7c7d6cdfdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720381627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2720381627
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3760372164
Short name T103
Test name
Test status
Simulation time 4637829120 ps
CPU time 40.84 seconds
Started May 30 12:36:04 PM PDT 24
Finished May 30 12:36:46 PM PDT 24
Peak memory 212192 kb
Host smart-0757eb04-dd36-4caf-9aea-fb90087cacfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760372164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3760372164
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2363396829
Short name T418
Test name
Test status
Simulation time 138217584 ps
CPU time 5.33 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:15 PM PDT 24
Peak memory 219304 kb
Host smart-63edce75-f281-4855-86c5-372d4dd8a395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363396829 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2363396829
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.349925165
Short name T72
Test name
Test status
Simulation time 6329293173 ps
CPU time 13.13 seconds
Started May 30 12:35:58 PM PDT 24
Finished May 30 12:36:12 PM PDT 24
Peak memory 211216 kb
Host smart-fceeca99-c9bf-4c68-9ea1-2760d1aa365a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349925165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.349925165
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3596083757
Short name T438
Test name
Test status
Simulation time 394800316 ps
CPU time 18.51 seconds
Started May 30 12:36:20 PM PDT 24
Finished May 30 12:36:40 PM PDT 24
Peak memory 211104 kb
Host smart-97c0252d-7bba-4655-96bd-7ef0963b3b33
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596083757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3596083757
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3927167142
Short name T437
Test name
Test status
Simulation time 7346194946 ps
CPU time 13.43 seconds
Started May 30 12:36:21 PM PDT 24
Finished May 30 12:36:35 PM PDT 24
Peak memory 211324 kb
Host smart-67b428c0-9fd4-42f2-9646-d0bfb9894490
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927167142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3927167142
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2084585634
Short name T447
Test name
Test status
Simulation time 8793148186 ps
CPU time 15.98 seconds
Started May 30 12:36:12 PM PDT 24
Finished May 30 12:36:30 PM PDT 24
Peak memory 219528 kb
Host smart-121634c1-9685-4106-b8d7-7a8e7bca352c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084585634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2084585634
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4220577689
Short name T100
Test name
Test status
Simulation time 1451514031 ps
CPU time 73.86 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:37:22 PM PDT 24
Peak memory 211936 kb
Host smart-5c0f0ebe-60ff-4062-a40c-c31bdb6777b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220577689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4220577689
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1557687493
Short name T375
Test name
Test status
Simulation time 1516220335 ps
CPU time 11.94 seconds
Started May 30 12:36:13 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 213900 kb
Host smart-d3933417-d2fe-4c2c-99cb-e15c74fdc998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557687493 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1557687493
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1562840324
Short name T80
Test name
Test status
Simulation time 89291420 ps
CPU time 4.25 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:15 PM PDT 24
Peak memory 211088 kb
Host smart-d9557abc-a071-47f6-bd6f-b793fb5f704e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562840324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1562840324
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2746906333
Short name T85
Test name
Test status
Simulation time 8088079375 ps
CPU time 42.11 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:36:54 PM PDT 24
Peak memory 211344 kb
Host smart-0fb95472-38d6-421e-a18f-d7e72b212753
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746906333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2746906333
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1586295012
Short name T459
Test name
Test status
Simulation time 1184095326 ps
CPU time 11.42 seconds
Started May 30 12:36:01 PM PDT 24
Finished May 30 12:36:13 PM PDT 24
Peak memory 211128 kb
Host smart-f64bc31b-fddd-4ad2-b067-a9cd7bdfc6ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586295012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1586295012
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.170856004
Short name T401
Test name
Test status
Simulation time 949906214 ps
CPU time 13.65 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 219364 kb
Host smart-18db9eb7-4028-4f84-b8b7-cc1461d253ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170856004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.170856004
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.810243880
Short name T399
Test name
Test status
Simulation time 962262610 ps
CPU time 72.11 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:37:25 PM PDT 24
Peak memory 212040 kb
Host smart-9c52e401-b300-4a82-aa0b-ffe7cbc94023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810243880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.810243880
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2097529154
Short name T3
Test name
Test status
Simulation time 25887906763 ps
CPU time 14.59 seconds
Started May 30 12:35:17 PM PDT 24
Finished May 30 12:35:32 PM PDT 24
Peak memory 211112 kb
Host smart-ac23d9aa-dda8-4017-8ebd-2c7987021b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097529154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2097529154
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.546010815
Short name T180
Test name
Test status
Simulation time 101986786578 ps
CPU time 244.93 seconds
Started May 30 12:35:04 PM PDT 24
Finished May 30 12:39:09 PM PDT 24
Peak memory 228432 kb
Host smart-2cc0f49f-33cb-4971-8347-6f42c108bc46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546010815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.546010815
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2582977121
Short name T283
Test name
Test status
Simulation time 386542695 ps
CPU time 5.94 seconds
Started May 30 12:35:17 PM PDT 24
Finished May 30 12:35:24 PM PDT 24
Peak memory 211000 kb
Host smart-eab5780e-2288-4a7c-925e-13a3646ee777
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582977121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2582977121
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3960476763
Short name T32
Test name
Test status
Simulation time 1985634255 ps
CPU time 61.78 seconds
Started May 30 12:35:15 PM PDT 24
Finished May 30 12:36:18 PM PDT 24
Peak memory 237804 kb
Host smart-81963b86-a7b9-4bfc-a940-96293ab4cffe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960476763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3960476763
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2272405144
Short name T45
Test name
Test status
Simulation time 761513429 ps
CPU time 10.14 seconds
Started May 30 12:35:26 PM PDT 24
Finished May 30 12:35:37 PM PDT 24
Peak memory 219324 kb
Host smart-98cd6fa6-987c-4022-9f0a-956745098011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272405144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2272405144
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3821567037
Short name T232
Test name
Test status
Simulation time 946728270 ps
CPU time 7.18 seconds
Started May 30 12:35:16 PM PDT 24
Finished May 30 12:35:24 PM PDT 24
Peak memory 210996 kb
Host smart-47af7983-a7f9-4349-a33f-5a26bee0dd3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821567037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3821567037
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4130664672
Short name T179
Test name
Test status
Simulation time 488289026 ps
CPU time 4.31 seconds
Started May 30 12:35:30 PM PDT 24
Finished May 30 12:35:35 PM PDT 24
Peak memory 211064 kb
Host smart-7426abdf-4f9d-416f-9742-7f9aa1e50bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130664672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4130664672
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1861292567
Short name T235
Test name
Test status
Simulation time 26302794990 ps
CPU time 156.78 seconds
Started May 30 12:35:30 PM PDT 24
Finished May 30 12:38:08 PM PDT 24
Peak memory 229820 kb
Host smart-2d9f7d76-2420-47e3-a2a5-3266e891b56b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861292567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1861292567
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.690836339
Short name T141
Test name
Test status
Simulation time 399871809 ps
CPU time 5.34 seconds
Started May 30 12:35:26 PM PDT 24
Finished May 30 12:35:32 PM PDT 24
Peak memory 211152 kb
Host smart-c63a8f35-704e-4b79-9751-8991982c9b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690836339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.690836339
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2129281051
Short name T191
Test name
Test status
Simulation time 13695202755 ps
CPU time 33.33 seconds
Started May 30 12:35:21 PM PDT 24
Finished May 30 12:35:55 PM PDT 24
Peak memory 214416 kb
Host smart-3480dd2b-4f43-4519-967a-d2bc391a1286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129281051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2129281051
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.257758385
Short name T230
Test name
Test status
Simulation time 13321628376 ps
CPU time 33.07 seconds
Started May 30 12:35:27 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 213648 kb
Host smart-fe3da41b-0f39-4c9e-a817-6bb2fc8c6481
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257758385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.257758385
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4166460771
Short name T255
Test name
Test status
Simulation time 318965965750 ps
CPU time 2915.95 seconds
Started May 30 12:35:16 PM PDT 24
Finished May 30 01:23:53 PM PDT 24
Peak memory 246044 kb
Host smart-03d84b6b-8d35-4c88-a46d-809f89eba0ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166460771 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.4166460771
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2976142350
Short name T299
Test name
Test status
Simulation time 1290056906 ps
CPU time 11.99 seconds
Started May 30 12:35:41 PM PDT 24
Finished May 30 12:35:54 PM PDT 24
Peak memory 211076 kb
Host smart-311d2416-986d-4978-a01b-f7fbf5b36f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976142350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2976142350
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1273879579
Short name T360
Test name
Test status
Simulation time 38864970827 ps
CPU time 256.6 seconds
Started May 30 12:35:27 PM PDT 24
Finished May 30 12:39:45 PM PDT 24
Peak memory 212384 kb
Host smart-de68de0e-bd82-4ed1-a1aa-1fa4f45edbc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273879579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1273879579
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3848920068
Short name T292
Test name
Test status
Simulation time 6998950730 ps
CPU time 16.16 seconds
Started May 30 12:35:40 PM PDT 24
Finished May 30 12:35:57 PM PDT 24
Peak memory 212364 kb
Host smart-e40ad9a1-1a55-46e1-9d57-4c5ade8b5377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848920068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3848920068
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1612997506
Short name T353
Test name
Test status
Simulation time 1774623912 ps
CPU time 15.63 seconds
Started May 30 12:35:31 PM PDT 24
Finished May 30 12:35:47 PM PDT 24
Peak memory 211056 kb
Host smart-a61476e8-7a46-441c-a69b-71ab9c6fd3f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612997506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1612997506
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1683498664
Short name T161
Test name
Test status
Simulation time 6740766808 ps
CPU time 32.57 seconds
Started May 30 12:35:25 PM PDT 24
Finished May 30 12:36:08 PM PDT 24
Peak memory 214156 kb
Host smart-de78e31e-43ae-4004-9a51-3285d9b857ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683498664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1683498664
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.888421216
Short name T342
Test name
Test status
Simulation time 6540274150 ps
CPU time 57.08 seconds
Started May 30 12:35:23 PM PDT 24
Finished May 30 12:36:21 PM PDT 24
Peak memory 219228 kb
Host smart-fde4569a-32ed-4245-9cbd-4064ec11006e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888421216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.888421216
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.362628395
Short name T276
Test name
Test status
Simulation time 8651017292 ps
CPU time 13.66 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:51 PM PDT 24
Peak memory 211164 kb
Host smart-7f9214e1-6e78-4ed5-96b6-b3e5a7c81613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362628395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.362628395
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2714869463
Short name T266
Test name
Test status
Simulation time 94264235074 ps
CPU time 188.67 seconds
Started May 30 12:35:30 PM PDT 24
Finished May 30 12:38:39 PM PDT 24
Peak memory 236836 kb
Host smart-8f81e75a-85bd-480d-868f-21b25b7ca308
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714869463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2714869463
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.792320988
Short name T19
Test name
Test status
Simulation time 976721713 ps
CPU time 9.53 seconds
Started May 30 12:35:26 PM PDT 24
Finished May 30 12:35:36 PM PDT 24
Peak memory 211840 kb
Host smart-086b0e4b-90cf-446a-97df-41ddb8793414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792320988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.792320988
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.824135518
Short name T335
Test name
Test status
Simulation time 7543187619 ps
CPU time 12.92 seconds
Started May 30 12:35:28 PM PDT 24
Finished May 30 12:35:42 PM PDT 24
Peak memory 211144 kb
Host smart-74ed92cc-e3c9-45eb-b54b-5ea93501374e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824135518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.824135518
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.832788354
Short name T234
Test name
Test status
Simulation time 2931210427 ps
CPU time 32.11 seconds
Started May 30 12:35:31 PM PDT 24
Finished May 30 12:36:04 PM PDT 24
Peak memory 213528 kb
Host smart-7e68ce8f-77ea-4724-b0b3-f9545b7801ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832788354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.832788354
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3813155955
Short name T250
Test name
Test status
Simulation time 7244706057 ps
CPU time 15.39 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:52 PM PDT 24
Peak memory 211152 kb
Host smart-ae2b6704-e5c9-446f-89af-21e3f16d4770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813155955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3813155955
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1995954422
Short name T285
Test name
Test status
Simulation time 29812412771 ps
CPU time 208 seconds
Started May 30 12:35:32 PM PDT 24
Finished May 30 12:39:01 PM PDT 24
Peak memory 236880 kb
Host smart-8413813c-61aa-4adf-a8f2-ab87580fb8d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995954422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1995954422
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2519891629
Short name T256
Test name
Test status
Simulation time 348402184 ps
CPU time 9.53 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:48 PM PDT 24
Peak memory 211704 kb
Host smart-8dd13ac0-1f66-482b-8d24-280d1932853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519891629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2519891629
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3906236715
Short name T321
Test name
Test status
Simulation time 362146777 ps
CPU time 7.69 seconds
Started May 30 12:35:40 PM PDT 24
Finished May 30 12:35:49 PM PDT 24
Peak memory 211044 kb
Host smart-274ba182-859a-430b-9ee7-cb30771f6699
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906236715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3906236715
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.192030042
Short name T345
Test name
Test status
Simulation time 3321780821 ps
CPU time 22.15 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:35:57 PM PDT 24
Peak memory 213580 kb
Host smart-2cea6334-1c70-469a-9ba9-a1693ab16b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192030042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.192030042
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.920120188
Short name T111
Test name
Test status
Simulation time 6770189142 ps
CPU time 62.88 seconds
Started May 30 12:35:31 PM PDT 24
Finished May 30 12:36:35 PM PDT 24
Peak memory 215072 kb
Host smart-32f8a4f8-20d4-43d2-a2fa-6c7e76d97393
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920120188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.920120188
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1934954987
Short name T259
Test name
Test status
Simulation time 41897859088 ps
CPU time 1530.33 seconds
Started May 30 12:35:23 PM PDT 24
Finished May 30 01:00:55 PM PDT 24
Peak memory 232068 kb
Host smart-d5fc2bc1-dc03-465b-bbfd-c2ec39e2c7d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934954987 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1934954987
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1878308323
Short name T39
Test name
Test status
Simulation time 6325175837 ps
CPU time 14.02 seconds
Started May 30 12:35:40 PM PDT 24
Finished May 30 12:35:55 PM PDT 24
Peak memory 211112 kb
Host smart-6ef1f020-1aef-44e0-8cd4-782dfe02abf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878308323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1878308323
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.337885772
Short name T334
Test name
Test status
Simulation time 37722134016 ps
CPU time 406.23 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:42:21 PM PDT 24
Peak memory 242048 kb
Host smart-62d68112-3b59-4a98-a43a-75f22ea5c2b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337885772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.337885772
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3381755041
Short name T212
Test name
Test status
Simulation time 8491310051 ps
CPU time 22.41 seconds
Started May 30 12:35:33 PM PDT 24
Finished May 30 12:35:56 PM PDT 24
Peak memory 212416 kb
Host smart-4e002292-1f4b-493f-9c17-66a5a361aa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381755041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3381755041
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2423062846
Short name T227
Test name
Test status
Simulation time 7474195099 ps
CPU time 18.26 seconds
Started May 30 12:35:33 PM PDT 24
Finished May 30 12:35:52 PM PDT 24
Peak memory 211104 kb
Host smart-331b8243-e27f-4566-a7a5-0b608ce61af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423062846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2423062846
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3335552689
Short name T182
Test name
Test status
Simulation time 923096969 ps
CPU time 16.74 seconds
Started May 30 12:35:46 PM PDT 24
Finished May 30 12:36:04 PM PDT 24
Peak memory 219212 kb
Host smart-29a9d454-c55b-4cce-bf0a-e1c7bde02e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335552689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3335552689
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.19674766
Short name T2
Test name
Test status
Simulation time 546981259 ps
CPU time 8.06 seconds
Started May 30 12:35:44 PM PDT 24
Finished May 30 12:35:53 PM PDT 24
Peak memory 210996 kb
Host smart-b3bd4432-020d-4772-b931-06327b7150b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19674766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.rom_ctrl_stress_all.19674766
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2280052770
Short name T343
Test name
Test status
Simulation time 1361228417 ps
CPU time 8.38 seconds
Started May 30 12:35:20 PM PDT 24
Finished May 30 12:35:29 PM PDT 24
Peak memory 211048 kb
Host smart-9f0f427a-b253-48ee-a810-6dc53c762d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280052770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2280052770
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.963556334
Short name T48
Test name
Test status
Simulation time 4953996356 ps
CPU time 75.75 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:36:53 PM PDT 24
Peak memory 228608 kb
Host smart-9c615206-4e0b-4c9a-84a2-57b8c3855c62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963556334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.963556334
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.989667082
Short name T324
Test name
Test status
Simulation time 12435588897 ps
CPU time 28.84 seconds
Started May 30 12:35:22 PM PDT 24
Finished May 30 12:35:52 PM PDT 24
Peak memory 212124 kb
Host smart-4f520190-0230-4207-8841-2302f76686ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989667082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.989667082
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3956368822
Short name T346
Test name
Test status
Simulation time 7258884950 ps
CPU time 16.26 seconds
Started May 30 12:35:26 PM PDT 24
Finished May 30 12:35:43 PM PDT 24
Peak memory 211244 kb
Host smart-e6ebea5c-3440-4ce7-8b90-7bbdbfb33ac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3956368822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3956368822
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.301968919
Short name T280
Test name
Test status
Simulation time 1429132435 ps
CPU time 18.67 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:55 PM PDT 24
Peak memory 219192 kb
Host smart-f637f173-6bfa-4492-8a32-2025f9342c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301968919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.301968919
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1455538445
Short name T41
Test name
Test status
Simulation time 49393419312 ps
CPU time 77.06 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:36:53 PM PDT 24
Peak memory 218436 kb
Host smart-3d9ca805-a67f-4c6d-b04e-ed1060fb5f8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455538445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1455538445
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3201873532
Short name T66
Test name
Test status
Simulation time 8336566289 ps
CPU time 15.1 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:53 PM PDT 24
Peak memory 211268 kb
Host smart-3b1ad993-613b-47ad-a20b-e145445e1d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201873532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3201873532
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.928064975
Short name T263
Test name
Test status
Simulation time 56621969090 ps
CPU time 301.21 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:40:38 PM PDT 24
Peak memory 234208 kb
Host smart-7de23a7d-9e68-4b2e-bd04-8e2caad9a41f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928064975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.928064975
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3226109492
Short name T158
Test name
Test status
Simulation time 1782352100 ps
CPU time 21.05 seconds
Started May 30 12:35:25 PM PDT 24
Finished May 30 12:35:46 PM PDT 24
Peak memory 212136 kb
Host smart-8ba61669-c505-4fc0-ba4b-1b52eb3bea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226109492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3226109492
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2427033324
Short name T339
Test name
Test status
Simulation time 7615212861 ps
CPU time 13.57 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:35:52 PM PDT 24
Peak memory 211232 kb
Host smart-650cfb43-8f77-41e3-a1a1-a51bc691b070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427033324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2427033324
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.354481370
Short name T133
Test name
Test status
Simulation time 717647971 ps
CPU time 10.21 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:48 PM PDT 24
Peak memory 213804 kb
Host smart-320e7d74-1de4-4879-8629-bc177cfa464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354481370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.354481370
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1345686140
Short name T318
Test name
Test status
Simulation time 12606196981 ps
CPU time 30.13 seconds
Started May 30 12:35:39 PM PDT 24
Finished May 30 12:36:11 PM PDT 24
Peak memory 213796 kb
Host smart-ba273107-8c98-4fe2-9939-ae5507ff46cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345686140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1345686140
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1721028704
Short name T219
Test name
Test status
Simulation time 86729928503 ps
CPU time 5775 seconds
Started May 30 12:35:44 PM PDT 24
Finished May 30 02:12:01 PM PDT 24
Peak memory 235764 kb
Host smart-965adf66-0e7a-4ad5-ba62-0ef3a67a96cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721028704 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1721028704
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2459276464
Short name T225
Test name
Test status
Simulation time 6329120637 ps
CPU time 13.38 seconds
Started May 30 12:35:27 PM PDT 24
Finished May 30 12:35:41 PM PDT 24
Peak memory 211172 kb
Host smart-2b23bfe5-4e79-40b5-bac8-5f774fead724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459276464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2459276464
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2561338953
Short name T268
Test name
Test status
Simulation time 59116043285 ps
CPU time 433.37 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:42:48 PM PDT 24
Peak memory 236872 kb
Host smart-b1df6d24-7530-408a-8b6f-3cc1e539085d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561338953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2561338953
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.792818498
Short name T341
Test name
Test status
Simulation time 6190506313 ps
CPU time 27.55 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:36:06 PM PDT 24
Peak memory 212040 kb
Host smart-e1441ffe-655c-4639-8d7d-4fbdc6098fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792818498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.792818498
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2584231316
Short name T147
Test name
Test status
Simulation time 4775133897 ps
CPU time 12.41 seconds
Started May 30 12:35:31 PM PDT 24
Finished May 30 12:35:44 PM PDT 24
Peak memory 211124 kb
Host smart-9220427d-a4c3-4f82-bdf5-1e4510a06898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584231316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2584231316
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2427736964
Short name T332
Test name
Test status
Simulation time 16379611729 ps
CPU time 34.74 seconds
Started May 30 12:35:29 PM PDT 24
Finished May 30 12:36:04 PM PDT 24
Peak memory 219324 kb
Host smart-57c87389-8b89-40a3-af4b-f8630145e376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427736964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2427736964
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3589452336
Short name T357
Test name
Test status
Simulation time 37900446880 ps
CPU time 48.76 seconds
Started May 30 12:35:27 PM PDT 24
Finished May 30 12:36:16 PM PDT 24
Peak memory 216624 kb
Host smart-e01de7a8-0f28-47bc-8990-64a88ffc4ea5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589452336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3589452336
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2138118911
Short name T132
Test name
Test status
Simulation time 4945428924 ps
CPU time 11.92 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:36:06 PM PDT 24
Peak memory 211280 kb
Host smart-e96a24de-470d-43ef-bd9d-1430413207b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138118911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2138118911
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.588983259
Short name T173
Test name
Test status
Simulation time 1185304553 ps
CPU time 9.17 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:45 PM PDT 24
Peak memory 211688 kb
Host smart-aa911206-7070-4327-8343-56652b58f2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588983259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.588983259
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2610995089
Short name T131
Test name
Test status
Simulation time 6890626163 ps
CPU time 15.02 seconds
Started May 30 12:35:31 PM PDT 24
Finished May 30 12:35:47 PM PDT 24
Peak memory 210988 kb
Host smart-320c59dc-ddba-493e-a554-fbf17050cab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2610995089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2610995089
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1738516952
Short name T358
Test name
Test status
Simulation time 2116978717 ps
CPU time 14.81 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:52 PM PDT 24
Peak memory 213772 kb
Host smart-08b26586-4302-4fc5-bfb5-830524564428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738516952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1738516952
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3478352933
Short name T53
Test name
Test status
Simulation time 35925919376 ps
CPU time 44.73 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:36:21 PM PDT 24
Peak memory 219232 kb
Host smart-0f65cebd-b038-44fc-afa7-172ea8cb555f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478352933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3478352933
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1661327865
Short name T281
Test name
Test status
Simulation time 1254903585 ps
CPU time 11.78 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:49 PM PDT 24
Peak memory 210984 kb
Host smart-84f8763b-0cea-422d-b4c2-b124e32d0796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661327865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1661327865
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1567887878
Short name T295
Test name
Test status
Simulation time 100765055555 ps
CPU time 291.89 seconds
Started May 30 12:35:43 PM PDT 24
Finished May 30 12:40:41 PM PDT 24
Peak memory 233272 kb
Host smart-9c741fe9-47a9-4965-ba9f-2136fc1b8662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567887878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1567887878
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1171284138
Short name T154
Test name
Test status
Simulation time 173910543 ps
CPU time 9.38 seconds
Started May 30 12:35:56 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 211600 kb
Host smart-ab54ee57-99d1-4e31-989e-4b7557fafd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171284138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1171284138
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1120996758
Short name T150
Test name
Test status
Simulation time 4260822849 ps
CPU time 18.27 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:54 PM PDT 24
Peak memory 211096 kb
Host smart-7648c1d5-1925-4b37-a14e-068491f7dd55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120996758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1120996758
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3324478015
Short name T220
Test name
Test status
Simulation time 724950763 ps
CPU time 9.81 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:48 PM PDT 24
Peak memory 213324 kb
Host smart-a396d014-e342-4e5c-a860-9569bfea2e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324478015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3324478015
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.154721074
Short name T112
Test name
Test status
Simulation time 1337184906 ps
CPU time 25.28 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:36:03 PM PDT 24
Peak memory 212564 kb
Host smart-e0ba67be-ef6e-4603-bc3d-db3d14e56e12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154721074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.154721074
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3685301028
Short name T216
Test name
Test status
Simulation time 3103691678 ps
CPU time 13.67 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:35:49 PM PDT 24
Peak memory 211128 kb
Host smart-f839094d-59d9-4772-9a03-9f54fca70bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685301028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3685301028
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3699886573
Short name T208
Test name
Test status
Simulation time 55447657828 ps
CPU time 311.81 seconds
Started May 30 12:35:45 PM PDT 24
Finished May 30 12:40:57 PM PDT 24
Peak memory 212436 kb
Host smart-5aec1e0c-509e-4166-8015-58879141ede8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699886573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3699886573
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1451470505
Short name T190
Test name
Test status
Simulation time 693140768 ps
CPU time 8.89 seconds
Started May 30 12:36:43 PM PDT 24
Finished May 30 12:36:53 PM PDT 24
Peak memory 211596 kb
Host smart-8441167d-56ab-4d5f-bab8-3155995857d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451470505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1451470505
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.698793087
Short name T226
Test name
Test status
Simulation time 1865387032 ps
CPU time 11.23 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:36:04 PM PDT 24
Peak memory 210888 kb
Host smart-b183c17e-d29a-4c72-88dc-46bf68340c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=698793087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.698793087
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2721221032
Short name T183
Test name
Test status
Simulation time 2257996393 ps
CPU time 27.62 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:36:06 PM PDT 24
Peak memory 213256 kb
Host smart-fc925a3b-1924-42cf-a018-59e8f8840d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721221032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2721221032
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2451526223
Short name T42
Test name
Test status
Simulation time 19701391091 ps
CPU time 84.37 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:37:01 PM PDT 24
Peak memory 217420 kb
Host smart-13b5dc0e-ddeb-477f-b300-327c0079e811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451526223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2451526223
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1244044476
Short name T273
Test name
Test status
Simulation time 3792761344 ps
CPU time 15.16 seconds
Started May 30 12:35:10 PM PDT 24
Finished May 30 12:35:27 PM PDT 24
Peak memory 211108 kb
Host smart-057170d3-a8f4-48f5-81e7-fc8eb5084df1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244044476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1244044476
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.449066737
Short name T323
Test name
Test status
Simulation time 22487368245 ps
CPU time 235.9 seconds
Started May 30 12:35:22 PM PDT 24
Finished May 30 12:39:20 PM PDT 24
Peak memory 225072 kb
Host smart-5640da52-2bc3-4fcc-8d14-4b89562b5311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449066737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.449066737
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2449014250
Short name T198
Test name
Test status
Simulation time 177504912 ps
CPU time 9.32 seconds
Started May 30 12:35:26 PM PDT 24
Finished May 30 12:35:36 PM PDT 24
Peak memory 211952 kb
Host smart-323252f6-864e-456d-adcc-f55a43256c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449014250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2449014250
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.367243807
Short name T310
Test name
Test status
Simulation time 102100124 ps
CPU time 5.62 seconds
Started May 30 12:35:14 PM PDT 24
Finished May 30 12:35:21 PM PDT 24
Peak memory 210980 kb
Host smart-3224c941-b806-46df-a9bf-6dc25c980015
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367243807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.367243807
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3398124864
Short name T31
Test name
Test status
Simulation time 539182223 ps
CPU time 60.21 seconds
Started May 30 12:35:18 PM PDT 24
Finished May 30 12:36:19 PM PDT 24
Peak memory 236492 kb
Host smart-7f41d624-285f-47b1-bdf5-a036425f3632
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398124864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3398124864
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.245621905
Short name T148
Test name
Test status
Simulation time 2320551590 ps
CPU time 22.95 seconds
Started May 30 12:35:09 PM PDT 24
Finished May 30 12:35:33 PM PDT 24
Peak memory 213360 kb
Host smart-048e2bee-b87d-4b30-a198-497050cdbe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245621905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.245621905
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2990555968
Short name T349
Test name
Test status
Simulation time 471215198 ps
CPU time 9.4 seconds
Started May 30 12:35:28 PM PDT 24
Finished May 30 12:35:38 PM PDT 24
Peak memory 210992 kb
Host smart-189255b0-c290-4b7c-8f8f-bbf763f2fe99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990555968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2990555968
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2933426153
Short name T307
Test name
Test status
Simulation time 661884063 ps
CPU time 5.4 seconds
Started May 30 12:35:48 PM PDT 24
Finished May 30 12:35:54 PM PDT 24
Peak memory 211000 kb
Host smart-bdb70eb3-95f5-4d12-91a5-11250accb391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933426153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2933426153
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4269624950
Short name T329
Test name
Test status
Simulation time 28785977836 ps
CPU time 283.12 seconds
Started May 30 12:35:29 PM PDT 24
Finished May 30 12:40:13 PM PDT 24
Peak memory 228344 kb
Host smart-137ca220-a0ba-45a8-bf64-f3608f9c5847
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269624950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4269624950
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1554314273
Short name T160
Test name
Test status
Simulation time 4958593108 ps
CPU time 24.79 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:36:03 PM PDT 24
Peak memory 212172 kb
Host smart-3ab6d08d-bc57-419a-91b1-5d987e7f50ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554314273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1554314273
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2597674659
Short name T205
Test name
Test status
Simulation time 1275868490 ps
CPU time 12.72 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:49 PM PDT 24
Peak memory 210956 kb
Host smart-66571515-c11b-4be3-b314-d0114c4808e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597674659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2597674659
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2306802374
Short name T113
Test name
Test status
Simulation time 279124015 ps
CPU time 12.39 seconds
Started May 30 12:35:40 PM PDT 24
Finished May 30 12:35:54 PM PDT 24
Peak memory 211900 kb
Host smart-02fcf809-add8-474c-8f65-9b0260a6cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306802374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2306802374
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.724143714
Short name T174
Test name
Test status
Simulation time 4632501237 ps
CPU time 39.01 seconds
Started May 30 12:35:49 PM PDT 24
Finished May 30 12:36:29 PM PDT 24
Peak memory 216488 kb
Host smart-1dc1bc5c-598e-4fd4-b6ef-a46694b95060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724143714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.724143714
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4238839591
Short name T157
Test name
Test status
Simulation time 89232264 ps
CPU time 4.05 seconds
Started May 30 12:36:26 PM PDT 24
Finished May 30 12:36:31 PM PDT 24
Peak memory 211020 kb
Host smart-fa3a857b-70c2-4f7d-8219-71a8db6bfb55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238839591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4238839591
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.38385639
Short name T350
Test name
Test status
Simulation time 23697590718 ps
CPU time 170.98 seconds
Started May 30 12:35:33 PM PDT 24
Finished May 30 12:38:25 PM PDT 24
Peak memory 237796 kb
Host smart-3cf63152-646f-4c16-baac-137a546045f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38385639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_co
rrupt_sig_fatal_chk.38385639
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1910073944
Short name T145
Test name
Test status
Simulation time 1229044177 ps
CPU time 17.59 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:35:57 PM PDT 24
Peak memory 211784 kb
Host smart-9206fa84-8f08-41a9-abcd-3f4a222e28ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910073944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1910073944
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.617714912
Short name T169
Test name
Test status
Simulation time 1883476238 ps
CPU time 15.95 seconds
Started May 30 12:36:18 PM PDT 24
Finished May 30 12:36:35 PM PDT 24
Peak memory 211020 kb
Host smart-5d13d324-17f4-464a-abee-f20c18471b33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617714912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.617714912
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1340875252
Short name T187
Test name
Test status
Simulation time 8628557182 ps
CPU time 26.13 seconds
Started May 30 12:35:43 PM PDT 24
Finished May 30 12:36:10 PM PDT 24
Peak memory 213988 kb
Host smart-53d5a61c-c88f-415a-9b7c-69d1fb0933fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340875252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1340875252
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4126603724
Short name T189
Test name
Test status
Simulation time 8648608639 ps
CPU time 27.61 seconds
Started May 30 12:35:46 PM PDT 24
Finished May 30 12:36:14 PM PDT 24
Peak memory 215368 kb
Host smart-5de1f7fb-c4b5-4286-8b15-8e6828d85043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126603724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4126603724
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3135633960
Short name T308
Test name
Test status
Simulation time 18084217942 ps
CPU time 13.31 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:51 PM PDT 24
Peak memory 211168 kb
Host smart-6093ba18-a2d2-4ed1-993f-53136da000b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135633960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3135633960
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1584141223
Short name T229
Test name
Test status
Simulation time 25667188626 ps
CPU time 279.24 seconds
Started May 30 12:35:32 PM PDT 24
Finished May 30 12:40:12 PM PDT 24
Peak memory 236752 kb
Host smart-f347400a-b0fa-41b0-9285-191ba206038f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584141223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1584141223
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.274042408
Short name T27
Test name
Test status
Simulation time 581394142 ps
CPU time 13.73 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:51 PM PDT 24
Peak memory 211112 kb
Host smart-3c460528-169f-4f77-90c4-5e06ccda0535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274042408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.274042408
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1559455952
Short name T272
Test name
Test status
Simulation time 7226609312 ps
CPU time 16.04 seconds
Started May 30 12:36:18 PM PDT 24
Finished May 30 12:36:36 PM PDT 24
Peak memory 211136 kb
Host smart-e6e8d31d-b0d8-44d0-a41c-ecf1bb90d9d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559455952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1559455952
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.488190652
Short name T337
Test name
Test status
Simulation time 19453169741 ps
CPU time 34.16 seconds
Started May 30 12:35:41 PM PDT 24
Finished May 30 12:36:17 PM PDT 24
Peak memory 214204 kb
Host smart-3b43d294-9f2c-4e11-8d9c-ee7d0179f1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488190652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.488190652
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2420275090
Short name T293
Test name
Test status
Simulation time 2740777570 ps
CPU time 30.21 seconds
Started May 30 12:35:40 PM PDT 24
Finished May 30 12:36:11 PM PDT 24
Peak memory 214264 kb
Host smart-e89067b2-99bc-4033-b171-7412f84f2a09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420275090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2420275090
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1178182491
Short name T165
Test name
Test status
Simulation time 5775058962 ps
CPU time 11.08 seconds
Started May 30 12:35:48 PM PDT 24
Finished May 30 12:36:00 PM PDT 24
Peak memory 211200 kb
Host smart-daf9025d-b6b7-47b9-b070-f0eedb73fb03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178182491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1178182491
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1148043389
Short name T239
Test name
Test status
Simulation time 19222179966 ps
CPU time 93.77 seconds
Started May 30 12:36:43 PM PDT 24
Finished May 30 12:38:18 PM PDT 24
Peak memory 237720 kb
Host smart-7e2a1dcb-02d9-44cd-b6f1-62adc1a595e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148043389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1148043389
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3933506180
Short name T172
Test name
Test status
Simulation time 982977659 ps
CPU time 16.44 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:35:55 PM PDT 24
Peak memory 211788 kb
Host smart-52d8c904-ca6e-4128-b0ab-b8ac86055020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933506180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3933506180
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3891179028
Short name T193
Test name
Test status
Simulation time 486785334 ps
CPU time 8.38 seconds
Started May 30 12:35:44 PM PDT 24
Finished May 30 12:35:54 PM PDT 24
Peak memory 211088 kb
Host smart-f3256c4e-46fe-4eef-ad27-3a45a86c1665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891179028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3891179028
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3796978798
Short name T290
Test name
Test status
Simulation time 760921870 ps
CPU time 9.41 seconds
Started May 30 12:36:46 PM PDT 24
Finished May 30 12:36:56 PM PDT 24
Peak memory 219148 kb
Host smart-d46be83e-7a0e-4795-b874-01e598beb7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796978798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3796978798
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4070613660
Short name T126
Test name
Test status
Simulation time 10074173565 ps
CPU time 51.86 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:36:30 PM PDT 24
Peak memory 216008 kb
Host smart-b626ddf6-cd0a-4ee8-95a0-29e4848bd73d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070613660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4070613660
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1768082912
Short name T221
Test name
Test status
Simulation time 10437430798 ps
CPU time 15.55 seconds
Started May 30 12:35:45 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 210956 kb
Host smart-c02f8da7-65c9-4498-9521-3b4e74edb660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768082912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1768082912
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3686912340
Short name T47
Test name
Test status
Simulation time 49440920449 ps
CPU time 308.37 seconds
Started May 30 12:36:33 PM PDT 24
Finished May 30 12:41:43 PM PDT 24
Peak memory 235404 kb
Host smart-8bcb6f07-3b31-4d14-b877-8f135f7a548f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686912340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3686912340
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3047681689
Short name T26
Test name
Test status
Simulation time 67024947241 ps
CPU time 33.36 seconds
Started May 30 12:35:38 PM PDT 24
Finished May 30 12:36:13 PM PDT 24
Peak memory 212228 kb
Host smart-59e684f0-9f54-4ad5-a368-20164070b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047681689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3047681689
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.38911440
Short name T153
Test name
Test status
Simulation time 98067490 ps
CPU time 5.53 seconds
Started May 30 12:35:31 PM PDT 24
Finished May 30 12:35:38 PM PDT 24
Peak memory 211044 kb
Host smart-b76dbae6-ea9b-40bc-91a5-93ca4ef94d40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38911440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.38911440
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1664554937
Short name T166
Test name
Test status
Simulation time 218639081 ps
CPU time 9.94 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:47 PM PDT 24
Peak memory 213448 kb
Host smart-3271188c-87d4-4d46-b85c-5df90c4c3b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664554937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1664554937
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4230368737
Short name T336
Test name
Test status
Simulation time 86478196 ps
CPU time 4.29 seconds
Started May 30 12:36:33 PM PDT 24
Finished May 30 12:36:39 PM PDT 24
Peak memory 209436 kb
Host smart-f368f218-c0fa-45e9-bb7b-d5fd6d364aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230368737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4230368737
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2279583773
Short name T243
Test name
Test status
Simulation time 27792961264 ps
CPU time 177.49 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:38:34 PM PDT 24
Peak memory 236792 kb
Host smart-38226d82-44e0-4c5f-bdb1-d0981f28983a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279583773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2279583773
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.191931554
Short name T359
Test name
Test status
Simulation time 3519646612 ps
CPU time 30.42 seconds
Started May 30 12:36:48 PM PDT 24
Finished May 30 12:37:20 PM PDT 24
Peak memory 211172 kb
Host smart-04aa596b-f5aa-4253-934f-3567ad1935e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191931554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.191931554
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2554991649
Short name T252
Test name
Test status
Simulation time 8971767827 ps
CPU time 17.4 seconds
Started May 30 12:35:33 PM PDT 24
Finished May 30 12:35:52 PM PDT 24
Peak memory 211168 kb
Host smart-2b9ef5de-8ef8-4f88-bb6b-f34aa4a4f2dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554991649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2554991649
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.686742944
Short name T162
Test name
Test status
Simulation time 7071143453 ps
CPU time 29.23 seconds
Started May 30 12:36:48 PM PDT 24
Finished May 30 12:37:18 PM PDT 24
Peak memory 214288 kb
Host smart-faabaa7e-bde8-4837-8dd7-f3e369cff8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686742944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.686742944
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1552923132
Short name T224
Test name
Test status
Simulation time 8102972139 ps
CPU time 24.72 seconds
Started May 30 12:36:44 PM PDT 24
Finished May 30 12:37:10 PM PDT 24
Peak memory 213180 kb
Host smart-3a971e50-51f7-4d5e-90f3-048f429e653c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552923132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1552923132
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2710043450
Short name T43
Test name
Test status
Simulation time 48704738991 ps
CPU time 4325.12 seconds
Started May 30 12:35:44 PM PDT 24
Finished May 30 01:47:50 PM PDT 24
Peak memory 235836 kb
Host smart-ae2fee93-cf54-44fe-b371-8976c784a048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710043450 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2710043450
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1806945474
Short name T34
Test name
Test status
Simulation time 226869662 ps
CPU time 4.25 seconds
Started May 30 12:35:47 PM PDT 24
Finished May 30 12:35:53 PM PDT 24
Peak memory 210764 kb
Host smart-3cddd202-82bc-49c1-9d10-69fe39f06461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806945474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1806945474
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3955439459
Short name T251
Test name
Test status
Simulation time 13382194961 ps
CPU time 187.99 seconds
Started May 30 12:36:48 PM PDT 24
Finished May 30 12:39:57 PM PDT 24
Peak memory 235804 kb
Host smart-c0b5ddc4-96b4-4cd4-9dee-97fbf338d27a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955439459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3955439459
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.756683161
Short name T201
Test name
Test status
Simulation time 593435305 ps
CPU time 9.47 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:35:49 PM PDT 24
Peak memory 211804 kb
Host smart-03954cf2-b5b9-430a-a3cd-cd91cd267cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756683161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.756683161
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.10769988
Short name T320
Test name
Test status
Simulation time 4330036233 ps
CPU time 11.13 seconds
Started May 30 12:36:43 PM PDT 24
Finished May 30 12:36:55 PM PDT 24
Peak memory 211092 kb
Host smart-23287aaa-23ee-45ea-85e7-4016988b1e06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10769988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.10769988
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.939659978
Short name T361
Test name
Test status
Simulation time 2728128265 ps
CPU time 33.86 seconds
Started May 30 12:35:45 PM PDT 24
Finished May 30 12:36:20 PM PDT 24
Peak memory 212420 kb
Host smart-545220fa-520a-474f-aaf0-005b2950dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939659978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.939659978
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.703808604
Short name T186
Test name
Test status
Simulation time 15534763066 ps
CPU time 102.45 seconds
Started May 30 12:36:33 PM PDT 24
Finished May 30 12:38:17 PM PDT 24
Peak memory 215312 kb
Host smart-27ecc63c-0f4e-4359-ae56-8f20dbd4e88b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703808604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.703808604
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4165074285
Short name T301
Test name
Test status
Simulation time 2335339913 ps
CPU time 7.94 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 211112 kb
Host smart-90ca6283-d991-4bdf-8b2c-24c6479a3aa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165074285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4165074285
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3295506488
Short name T178
Test name
Test status
Simulation time 2100871980 ps
CPU time 11.98 seconds
Started May 30 12:35:43 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 211152 kb
Host smart-b6262c2a-6533-42a5-8171-b059761019c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295506488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3295506488
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2685055732
Short name T185
Test name
Test status
Simulation time 9560889254 ps
CPU time 27.65 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 214264 kb
Host smart-5b131806-568c-4c53-bb32-9624037fcb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685055732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2685055732
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.937971619
Short name T270
Test name
Test status
Simulation time 291368790 ps
CPU time 11.53 seconds
Started May 30 12:35:38 PM PDT 24
Finished May 30 12:35:51 PM PDT 24
Peak memory 212464 kb
Host smart-d9807af7-b817-4e8b-8381-d9224afb8101
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937971619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.937971619
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3282620938
Short name T64
Test name
Test status
Simulation time 89013635 ps
CPU time 4.29 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:41 PM PDT 24
Peak memory 211036 kb
Host smart-b8edf030-a210-4fcf-8f70-780c1b44ea4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282620938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3282620938
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1124206776
Short name T319
Test name
Test status
Simulation time 12227251204 ps
CPU time 149.21 seconds
Started May 30 12:35:53 PM PDT 24
Finished May 30 12:38:26 PM PDT 24
Peak memory 211428 kb
Host smart-4299bb53-d70e-48dd-961b-52c6ae4167b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124206776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1124206776
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.326262265
Short name T265
Test name
Test status
Simulation time 4096991509 ps
CPU time 16.01 seconds
Started May 30 12:36:00 PM PDT 24
Finished May 30 12:36:17 PM PDT 24
Peak memory 211856 kb
Host smart-94164d8c-b407-4f7b-ba58-e8904188df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326262265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.326262265
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.667495158
Short name T305
Test name
Test status
Simulation time 2219365813 ps
CPU time 12.66 seconds
Started May 30 12:35:53 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 211216 kb
Host smart-a23886d3-6f24-44fd-9388-6572d4e63dff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667495158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.667495158
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2851742089
Short name T4
Test name
Test status
Simulation time 4679492057 ps
CPU time 16.96 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:36:11 PM PDT 24
Peak memory 213740 kb
Host smart-b671c820-849e-4115-aaa4-870bc2b63d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851742089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2851742089
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.4272240251
Short name T54
Test name
Test status
Simulation time 560741334078 ps
CPU time 1561.72 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 01:01:39 PM PDT 24
Peak memory 234232 kb
Host smart-0e25eb2b-dbfc-4ec9-9ad4-c2201fc24e3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272240251 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.4272240251
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.903190610
Short name T356
Test name
Test status
Simulation time 309393355 ps
CPU time 4.29 seconds
Started May 30 12:35:42 PM PDT 24
Finished May 30 12:35:47 PM PDT 24
Peak memory 210960 kb
Host smart-e1c9b39a-2d55-4cef-b9ad-da61bdb9ed79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903190610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.903190610
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.909131559
Short name T222
Test name
Test status
Simulation time 163737493167 ps
CPU time 252.99 seconds
Started May 30 12:35:53 PM PDT 24
Finished May 30 12:40:07 PM PDT 24
Peak memory 233732 kb
Host smart-82554071-fed1-46f6-af3d-0a0375071b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909131559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.909131559
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.410989273
Short name T210
Test name
Test status
Simulation time 2403475987 ps
CPU time 17.49 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:55 PM PDT 24
Peak memory 211760 kb
Host smart-741e3572-85e2-4e89-8203-e6e779ace9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410989273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.410989273
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2598614823
Short name T128
Test name
Test status
Simulation time 2273085848 ps
CPU time 12.38 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:49 PM PDT 24
Peak memory 211112 kb
Host smart-b8ad8957-ff23-4c26-88bd-d83cbf106679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598614823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2598614823
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.726037003
Short name T200
Test name
Test status
Simulation time 184516359 ps
CPU time 9.92 seconds
Started May 30 12:35:51 PM PDT 24
Finished May 30 12:36:02 PM PDT 24
Peak memory 219156 kb
Host smart-b146c33a-b77c-4833-88aa-3886e1713f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726037003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.726037003
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3029696685
Short name T303
Test name
Test status
Simulation time 10461439096 ps
CPU time 18.22 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:56 PM PDT 24
Peak memory 218180 kb
Host smart-330c5cb6-276e-4633-93b2-679d072a5045
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029696685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3029696685
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2982750848
Short name T228
Test name
Test status
Simulation time 1241032826 ps
CPU time 11.73 seconds
Started May 30 12:35:31 PM PDT 24
Finished May 30 12:35:43 PM PDT 24
Peak memory 211032 kb
Host smart-e659108d-5831-4f62-b828-71fd9c2085a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982750848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2982750848
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3701837788
Short name T30
Test name
Test status
Simulation time 27373074453 ps
CPU time 142.92 seconds
Started May 30 12:35:15 PM PDT 24
Finished May 30 12:37:39 PM PDT 24
Peak memory 236472 kb
Host smart-78959648-def6-4efb-8b4f-20ee4025036d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701837788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3701837788
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.356865648
Short name T262
Test name
Test status
Simulation time 11564174507 ps
CPU time 19.35 seconds
Started May 30 12:35:20 PM PDT 24
Finished May 30 12:35:39 PM PDT 24
Peak memory 212116 kb
Host smart-fca07e1e-1045-4f7b-899b-6722cda52ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356865648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.356865648
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3348021166
Short name T197
Test name
Test status
Simulation time 3253253215 ps
CPU time 15.02 seconds
Started May 30 12:35:21 PM PDT 24
Finished May 30 12:35:37 PM PDT 24
Peak memory 210984 kb
Host smart-694eb675-3ab1-42a2-8667-4dc1e1a29d1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348021166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3348021166
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2762179670
Short name T37
Test name
Test status
Simulation time 1216345677 ps
CPU time 52.78 seconds
Started May 30 12:35:23 PM PDT 24
Finished May 30 12:36:17 PM PDT 24
Peak memory 236644 kb
Host smart-582f1f08-3cbd-4713-b146-cf00dd15375f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762179670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2762179670
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1202416312
Short name T125
Test name
Test status
Simulation time 8774280408 ps
CPU time 21.02 seconds
Started May 30 12:35:25 PM PDT 24
Finished May 30 12:35:47 PM PDT 24
Peak memory 213924 kb
Host smart-d4701432-a01b-4722-a3ce-6fa2ec40c182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202416312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1202416312
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2940846556
Short name T288
Test name
Test status
Simulation time 6329255468 ps
CPU time 50.33 seconds
Started May 30 12:35:32 PM PDT 24
Finished May 30 12:36:29 PM PDT 24
Peak memory 212864 kb
Host smart-aca72e54-a1d1-41d8-9945-1e3124066a54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940846556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2940846556
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3815317162
Short name T331
Test name
Test status
Simulation time 27040450322 ps
CPU time 13.38 seconds
Started May 30 12:35:41 PM PDT 24
Finished May 30 12:35:55 PM PDT 24
Peak memory 211156 kb
Host smart-3608d547-b101-4d3c-97ea-0273ea28db57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815317162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3815317162
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1403529861
Short name T298
Test name
Test status
Simulation time 138598530475 ps
CPU time 288.94 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:41:00 PM PDT 24
Peak memory 212884 kb
Host smart-463e9303-cb45-4687-a452-34aeb997f767
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403529861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1403529861
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1345083286
Short name T40
Test name
Test status
Simulation time 3021280736 ps
CPU time 27.14 seconds
Started May 30 12:35:57 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 211844 kb
Host smart-631cb6dc-001c-43d2-beab-e0a2ac915805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345083286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1345083286
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4006703030
Short name T167
Test name
Test status
Simulation time 227731206 ps
CPU time 5.57 seconds
Started May 30 12:35:45 PM PDT 24
Finished May 30 12:35:52 PM PDT 24
Peak memory 211004 kb
Host smart-d9f60f7b-f9aa-4230-bc05-f90fa7913384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006703030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4006703030
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.69508965
Short name T261
Test name
Test status
Simulation time 443302795 ps
CPU time 12.82 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:23 PM PDT 24
Peak memory 213632 kb
Host smart-3728f557-7c06-4eff-b53a-ab1e4ae31ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69508965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.69508965
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2315413661
Short name T246
Test name
Test status
Simulation time 5023795163 ps
CPU time 58.8 seconds
Started May 30 12:35:41 PM PDT 24
Finished May 30 12:36:40 PM PDT 24
Peak memory 219104 kb
Host smart-f7938e32-980d-40a7-baf2-2aa29fb1ebdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315413661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2315413661
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2130542510
Short name T347
Test name
Test status
Simulation time 4257021688 ps
CPU time 10.48 seconds
Started May 30 12:35:46 PM PDT 24
Finished May 30 12:35:58 PM PDT 24
Peak memory 211084 kb
Host smart-8df6e3d9-a2f3-4d71-ac6d-264d5127760d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130542510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2130542510
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3960640188
Short name T156
Test name
Test status
Simulation time 16951805146 ps
CPU time 131.06 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:38:06 PM PDT 24
Peak memory 228588 kb
Host smart-64ba82b7-ffc5-48bb-a638-40c42f436f65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960640188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3960640188
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2102742220
Short name T213
Test name
Test status
Simulation time 421600717 ps
CPU time 12.64 seconds
Started May 30 12:35:56 PM PDT 24
Finished May 30 12:36:10 PM PDT 24
Peak memory 211660 kb
Host smart-a8d8b9f6-6e2f-4427-9355-77288a0668e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102742220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2102742220
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.313712865
Short name T136
Test name
Test status
Simulation time 21261723994 ps
CPU time 17.45 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:55 PM PDT 24
Peak memory 211152 kb
Host smart-c2ad4530-afee-4767-b35d-5b5bfbd5323a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313712865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.313712865
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1884769507
Short name T116
Test name
Test status
Simulation time 206758400 ps
CPU time 10.57 seconds
Started May 30 12:35:53 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 213192 kb
Host smart-7a3eacf2-0e92-4dfa-ab0d-13373f8c3861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884769507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1884769507
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1246490607
Short name T52
Test name
Test status
Simulation time 1308698388 ps
CPU time 21.87 seconds
Started May 30 12:35:53 PM PDT 24
Finished May 30 12:36:16 PM PDT 24
Peak memory 219116 kb
Host smart-dda71e7d-8f81-4805-8fc7-8f11954949d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246490607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1246490607
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2692509552
Short name T58
Test name
Test status
Simulation time 136653916111 ps
CPU time 1139.62 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:54:37 PM PDT 24
Peak memory 233948 kb
Host smart-1a9b71ff-5bd6-442f-9740-9e8f5eaf8577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692509552 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2692509552
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2800540656
Short name T363
Test name
Test status
Simulation time 3385704845 ps
CPU time 9.27 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:35:45 PM PDT 24
Peak memory 210904 kb
Host smart-53ad6c8d-cefa-4eca-b85f-ed6932fe3471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800540656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2800540656
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1904891331
Short name T127
Test name
Test status
Simulation time 42675159001 ps
CPU time 98.04 seconds
Started May 30 12:35:33 PM PDT 24
Finished May 30 12:37:11 PM PDT 24
Peak memory 237808 kb
Host smart-f5857371-856b-4677-99f0-bd54ef4872b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904891331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1904891331
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2239961075
Short name T340
Test name
Test status
Simulation time 1038923037 ps
CPU time 9.23 seconds
Started May 30 12:35:44 PM PDT 24
Finished May 30 12:35:55 PM PDT 24
Peak memory 211780 kb
Host smart-a22874a0-6cfd-42a8-83a1-9880f8a94ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239961075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2239961075
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4118826274
Short name T328
Test name
Test status
Simulation time 10693151574 ps
CPU time 17.75 seconds
Started May 30 12:35:44 PM PDT 24
Finished May 30 12:36:03 PM PDT 24
Peak memory 211180 kb
Host smart-5ca82adf-5368-41c6-8ad5-48e6be533cda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118826274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4118826274
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.74982472
Short name T238
Test name
Test status
Simulation time 705723313 ps
CPU time 14.18 seconds
Started May 30 12:35:48 PM PDT 24
Finished May 30 12:36:04 PM PDT 24
Peak memory 213068 kb
Host smart-4ba2eb4c-9d7a-4a24-baf2-238e06fdbe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74982472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.74982472
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2443096893
Short name T254
Test name
Test status
Simulation time 31274713782 ps
CPU time 68.04 seconds
Started May 30 12:35:53 PM PDT 24
Finished May 30 12:37:03 PM PDT 24
Peak memory 217136 kb
Host smart-33dc1027-7e03-4c0d-a5d6-0827e4e81ada
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443096893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2443096893
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1956029658
Short name T275
Test name
Test status
Simulation time 3500413115 ps
CPU time 14.19 seconds
Started May 30 12:35:50 PM PDT 24
Finished May 30 12:36:16 PM PDT 24
Peak memory 210528 kb
Host smart-8e7af6df-65db-4e51-985d-e8c03b369274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956029658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1956029658
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4068010744
Short name T29
Test name
Test status
Simulation time 3918778606 ps
CPU time 123.95 seconds
Started May 30 12:35:53 PM PDT 24
Finished May 30 12:37:59 PM PDT 24
Peak memory 224620 kb
Host smart-267b3880-6c34-4126-a8b7-134d0278ad37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068010744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4068010744
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1684537411
Short name T306
Test name
Test status
Simulation time 1986098717 ps
CPU time 21.75 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:36:15 PM PDT 24
Peak memory 212164 kb
Host smart-63909831-51d9-49ca-b763-5eb641b64037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684537411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1684537411
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2190164754
Short name T333
Test name
Test status
Simulation time 24641959682 ps
CPU time 16.28 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:53 PM PDT 24
Peak memory 211128 kb
Host smart-8d4d4bc6-060f-4d8d-91ab-7000cf31d7ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190164754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2190164754
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1224101486
Short name T240
Test name
Test status
Simulation time 186229669 ps
CPU time 10.24 seconds
Started May 30 12:35:55 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 219216 kb
Host smart-e0083854-c742-42c8-8799-a9c0779ab653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224101486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1224101486
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3388715092
Short name T330
Test name
Test status
Simulation time 2368331543 ps
CPU time 32.44 seconds
Started May 30 12:36:03 PM PDT 24
Finished May 30 12:36:36 PM PDT 24
Peak memory 213524 kb
Host smart-8e7b2efa-caa4-4294-a9b2-9e2aba1c5f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388715092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3388715092
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1516855368
Short name T17
Test name
Test status
Simulation time 171636548244 ps
CPU time 1054.33 seconds
Started May 30 12:35:42 PM PDT 24
Finished May 30 12:53:18 PM PDT 24
Peak memory 235800 kb
Host smart-34961ffe-4f7e-4152-a116-485b976df722
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516855368 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1516855368
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.889262920
Short name T207
Test name
Test status
Simulation time 3957975161 ps
CPU time 10.16 seconds
Started May 30 12:35:31 PM PDT 24
Finished May 30 12:35:42 PM PDT 24
Peak memory 211080 kb
Host smart-a416a323-ba66-4f88-8bda-498998eb0b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889262920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.889262920
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.100811538
Short name T135
Test name
Test status
Simulation time 25513950561 ps
CPU time 264.56 seconds
Started May 30 12:35:39 PM PDT 24
Finished May 30 12:40:05 PM PDT 24
Peak memory 224992 kb
Host smart-bb956db1-6d6c-4e90-9388-93922750288a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100811538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.100811538
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.957402071
Short name T249
Test name
Test status
Simulation time 1505255415 ps
CPU time 18.88 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:35:54 PM PDT 24
Peak memory 211860 kb
Host smart-a8c789df-edda-42e1-a5df-9912dc2d5e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957402071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.957402071
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4125934536
Short name T15
Test name
Test status
Simulation time 660633109 ps
CPU time 9.68 seconds
Started May 30 12:35:46 PM PDT 24
Finished May 30 12:35:57 PM PDT 24
Peak memory 211088 kb
Host smart-8d68ad75-70c9-48ff-be40-d4306028995f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125934536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4125934536
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2664112641
Short name T129
Test name
Test status
Simulation time 4164754893 ps
CPU time 18.74 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 213520 kb
Host smart-a4ee0945-9745-45d0-af1f-1dd0a0ef5410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664112641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2664112641
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3341606027
Short name T325
Test name
Test status
Simulation time 1099827417 ps
CPU time 28.36 seconds
Started May 30 12:35:48 PM PDT 24
Finished May 30 12:36:18 PM PDT 24
Peak memory 215524 kb
Host smart-dcdcdbc0-18ac-41c4-9c65-0d3492b01491
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341606027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3341606027
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2218044630
Short name T55
Test name
Test status
Simulation time 23565144932 ps
CPU time 907.52 seconds
Started May 30 12:35:39 PM PDT 24
Finished May 30 12:50:48 PM PDT 24
Peak memory 228976 kb
Host smart-6c54844d-ed09-4e0c-aa5f-30fa4800a8aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218044630 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2218044630
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4031144927
Short name T245
Test name
Test status
Simulation time 4104129375 ps
CPU time 10.37 seconds
Started May 30 12:35:39 PM PDT 24
Finished May 30 12:35:51 PM PDT 24
Peak memory 210980 kb
Host smart-f56e930a-d076-45bc-b689-bb7378dd7492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031144927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4031144927
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.31241682
Short name T247
Test name
Test status
Simulation time 130667038130 ps
CPU time 332.14 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:41:11 PM PDT 24
Peak memory 227888 kb
Host smart-a5bf0cdc-2bc5-4172-8ced-06bbe8919ac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31241682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_co
rrupt_sig_fatal_chk.31241682
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2916341240
Short name T242
Test name
Test status
Simulation time 191499171 ps
CPU time 9.46 seconds
Started May 30 12:35:51 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 211784 kb
Host smart-461984dd-598d-4f20-82b9-b722845f8e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916341240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2916341240
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3331514239
Short name T44
Test name
Test status
Simulation time 8643114222 ps
CPU time 17.66 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:54 PM PDT 24
Peak memory 211144 kb
Host smart-9cfb8201-2b8b-4b7e-a787-eee9fee8c561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331514239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3331514239
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.451593929
Short name T143
Test name
Test status
Simulation time 3720293699 ps
CPU time 35.67 seconds
Started May 30 12:36:03 PM PDT 24
Finished May 30 12:36:39 PM PDT 24
Peak memory 213424 kb
Host smart-5decb70b-3267-4c39-ab13-84fee17cae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451593929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.451593929
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1608390910
Short name T271
Test name
Test status
Simulation time 17146286277 ps
CPU time 74.19 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:36:50 PM PDT 24
Peak memory 217448 kb
Host smart-e527fa4a-1d19-48c2-aab3-93158f1ba736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608390910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1608390910
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3730924814
Short name T65
Test name
Test status
Simulation time 220394615 ps
CPU time 5.77 seconds
Started May 30 12:35:39 PM PDT 24
Finished May 30 12:35:46 PM PDT 24
Peak memory 211032 kb
Host smart-dac183c9-5754-4e81-80a6-8bfd6c2ccb9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730924814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3730924814
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.207462193
Short name T121
Test name
Test status
Simulation time 8488722121 ps
CPU time 67.6 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:37:03 PM PDT 24
Peak memory 237216 kb
Host smart-4510a6f1-662f-4b71-a5c9-49212a2344a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207462193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.207462193
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.526142776
Short name T170
Test name
Test status
Simulation time 958709567 ps
CPU time 11.22 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:49 PM PDT 24
Peak memory 211808 kb
Host smart-20e4fb86-ff5d-4274-aef6-9c7e83d1c49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526142776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.526142776
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1136805368
Short name T302
Test name
Test status
Simulation time 30792110601 ps
CPU time 14.7 seconds
Started May 30 12:35:58 PM PDT 24
Finished May 30 12:36:14 PM PDT 24
Peak memory 211168 kb
Host smart-e035334a-321f-4a95-ab31-6a508e78c793
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136805368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1136805368
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.869534394
Short name T7
Test name
Test status
Simulation time 3143516067 ps
CPU time 33.61 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:36:40 PM PDT 24
Peak memory 219276 kb
Host smart-4fff5633-a701-4a08-b42f-5a8caa51c4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869534394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.869534394
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1145406955
Short name T206
Test name
Test status
Simulation time 634840479 ps
CPU time 35.19 seconds
Started May 30 12:36:08 PM PDT 24
Finished May 30 12:36:44 PM PDT 24
Peak memory 216012 kb
Host smart-a02f6536-be73-46ed-81e7-128ee0469479
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145406955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1145406955
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1250131019
Short name T354
Test name
Test status
Simulation time 2042341113 ps
CPU time 16.09 seconds
Started May 30 12:35:51 PM PDT 24
Finished May 30 12:36:08 PM PDT 24
Peak memory 211144 kb
Host smart-0af01dc8-a8eb-45c1-9b25-75244ced5934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250131019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1250131019
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2897878706
Short name T296
Test name
Test status
Simulation time 13037886076 ps
CPU time 236.97 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:40:04 PM PDT 24
Peak memory 233128 kb
Host smart-8bbc39fc-e963-4a78-a85b-db1c896baf7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897878706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2897878706
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2932788690
Short name T233
Test name
Test status
Simulation time 168852155 ps
CPU time 9.6 seconds
Started May 30 12:35:48 PM PDT 24
Finished May 30 12:35:59 PM PDT 24
Peak memory 212196 kb
Host smart-1970ad93-d180-48f3-a90c-c1d707d378f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932788690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2932788690
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.809112497
Short name T284
Test name
Test status
Simulation time 2735159579 ps
CPU time 12.03 seconds
Started May 30 12:35:38 PM PDT 24
Finished May 30 12:35:52 PM PDT 24
Peak memory 211100 kb
Host smart-2493a4bd-18e1-4b44-9c29-06d66127421c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809112497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.809112497
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.283359118
Short name T6
Test name
Test status
Simulation time 337054683 ps
CPU time 10.38 seconds
Started May 30 12:35:54 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 219260 kb
Host smart-4601f4fd-1689-4eb8-b540-f47b847ad20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283359118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.283359118
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3558669667
Short name T317
Test name
Test status
Simulation time 3380773285 ps
CPU time 30.38 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:36:24 PM PDT 24
Peak memory 215840 kb
Host smart-9582cdb2-06f3-4ab8-a238-5e6ae4e7db26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558669667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3558669667
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1993006179
Short name T260
Test name
Test status
Simulation time 3819759084 ps
CPU time 15.43 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:35:54 PM PDT 24
Peak memory 211084 kb
Host smart-744356b5-208d-4e8d-a640-9d70f5732172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993006179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1993006179
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4178668015
Short name T194
Test name
Test status
Simulation time 3164637835 ps
CPU time 99.99 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:37:47 PM PDT 24
Peak memory 228308 kb
Host smart-89e61a6f-1dbf-4c41-bfe2-c629a691b5e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178668015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4178668015
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1858568006
Short name T287
Test name
Test status
Simulation time 8867084276 ps
CPU time 21.62 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:36:29 PM PDT 24
Peak memory 212344 kb
Host smart-a3a81ff6-0e00-4e4b-a621-aff1558a9a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858568006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1858568006
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.383975418
Short name T142
Test name
Test status
Simulation time 3477811676 ps
CPU time 14.79 seconds
Started May 30 12:35:50 PM PDT 24
Finished May 30 12:36:05 PM PDT 24
Peak memory 211060 kb
Host smart-7e112a9d-0ed1-45b7-a599-c3e1add97830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383975418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.383975418
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.593599998
Short name T297
Test name
Test status
Simulation time 3494367981 ps
CPU time 29.03 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 212736 kb
Host smart-7d295c96-667e-4bd2-b998-9107c70c8b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593599998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.593599998
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3330279453
Short name T279
Test name
Test status
Simulation time 1159520074 ps
CPU time 15.85 seconds
Started May 30 12:35:48 PM PDT 24
Finished May 30 12:36:04 PM PDT 24
Peak memory 219172 kb
Host smart-8c56cfe9-01d3-4964-a855-4b94f01650d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330279453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3330279453
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3277606318
Short name T241
Test name
Test status
Simulation time 1798106813 ps
CPU time 7.22 seconds
Started May 30 12:35:48 PM PDT 24
Finished May 30 12:35:56 PM PDT 24
Peak memory 210764 kb
Host smart-8103acaf-d0a3-4539-97dd-7ad9335582bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277606318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3277606318
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3875626768
Short name T49
Test name
Test status
Simulation time 100667192351 ps
CPU time 220.23 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:39:50 PM PDT 24
Peak memory 212704 kb
Host smart-57eef16f-7798-4814-a5c3-8fe073f75d55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875626768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3875626768
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3145830522
Short name T351
Test name
Test status
Simulation time 6991509277 ps
CPU time 21.12 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:36:27 PM PDT 24
Peak memory 212244 kb
Host smart-5e09f6ad-f2c5-425b-a3db-db4d3639f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145830522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3145830522
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2215967481
Short name T365
Test name
Test status
Simulation time 493480133 ps
CPU time 8.62 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:17 PM PDT 24
Peak memory 211064 kb
Host smart-fc8cbb19-ff73-40b0-ae47-4957122d59b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215967481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2215967481
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1108291585
Short name T294
Test name
Test status
Simulation time 6573990969 ps
CPU time 20.11 seconds
Started May 30 12:35:40 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 219268 kb
Host smart-a191b622-ae94-494a-9222-4c076c599396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108291585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1108291585
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.346304295
Short name T236
Test name
Test status
Simulation time 15196772414 ps
CPU time 36.57 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:36:43 PM PDT 24
Peak memory 219284 kb
Host smart-6cac283c-5bf9-43c1-a1e8-719b0bd1d74b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346304295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.346304295
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1305376406
Short name T57
Test name
Test status
Simulation time 81705843253 ps
CPU time 2240.97 seconds
Started May 30 12:35:40 PM PDT 24
Finished May 30 01:13:02 PM PDT 24
Peak memory 235824 kb
Host smart-8b5cb45d-a31f-4716-bdac-2904ecf59868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305376406 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1305376406
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3813719540
Short name T155
Test name
Test status
Simulation time 1711822072 ps
CPU time 14.71 seconds
Started May 30 12:35:22 PM PDT 24
Finished May 30 12:35:38 PM PDT 24
Peak memory 211048 kb
Host smart-f4f3c219-81f1-43e0-82da-2266655a0c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813719540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3813719540
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1735420052
Short name T46
Test name
Test status
Simulation time 88914603767 ps
CPU time 315.88 seconds
Started May 30 12:35:17 PM PDT 24
Finished May 30 12:40:34 PM PDT 24
Peak memory 237276 kb
Host smart-9a9049fc-f7e2-484f-9bce-90a0b98d71db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735420052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1735420052
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2882536938
Short name T144
Test name
Test status
Simulation time 5256478421 ps
CPU time 25.65 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:36:04 PM PDT 24
Peak memory 212288 kb
Host smart-b552c280-7ed6-4f23-ae95-a0ce6f8ec6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882536938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2882536938
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1967801850
Short name T175
Test name
Test status
Simulation time 1117104499 ps
CPU time 12.1 seconds
Started May 30 12:35:45 PM PDT 24
Finished May 30 12:35:59 PM PDT 24
Peak memory 210760 kb
Host smart-79c07065-f894-4c60-a58c-273ff754b5f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967801850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1967801850
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1897056338
Short name T33
Test name
Test status
Simulation time 823322021 ps
CPU time 56.46 seconds
Started May 30 12:35:28 PM PDT 24
Finished May 30 12:36:25 PM PDT 24
Peak memory 236460 kb
Host smart-abeadcfc-ef17-4225-83de-314bedcba477
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897056338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1897056338
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2812276320
Short name T278
Test name
Test status
Simulation time 2713289390 ps
CPU time 18.5 seconds
Started May 30 12:35:21 PM PDT 24
Finished May 30 12:35:41 PM PDT 24
Peak memory 213200 kb
Host smart-e0585c88-b131-493d-82d6-c676f2ccd215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812276320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2812276320
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1266269119
Short name T244
Test name
Test status
Simulation time 322477087 ps
CPU time 16.05 seconds
Started May 30 12:35:32 PM PDT 24
Finished May 30 12:35:49 PM PDT 24
Peak memory 219116 kb
Host smart-cc47081f-e1c3-47b9-87ae-506d61c2855a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266269119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1266269119
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4088215191
Short name T282
Test name
Test status
Simulation time 47049930832 ps
CPU time 269.44 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:40:23 PM PDT 24
Peak memory 218428 kb
Host smart-23683783-9b42-4858-bc66-fed83adf7c73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088215191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4088215191
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.132638511
Short name T119
Test name
Test status
Simulation time 860001977 ps
CPU time 15.01 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:35:53 PM PDT 24
Peak memory 211812 kb
Host smart-58451436-85f7-4671-baab-6ab597aaaeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132638511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.132638511
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2474984451
Short name T163
Test name
Test status
Simulation time 436146320 ps
CPU time 6.96 seconds
Started May 30 12:35:48 PM PDT 24
Finished May 30 12:35:56 PM PDT 24
Peak memory 211140 kb
Host smart-115dc945-5dd9-4de4-86aa-e9f54fae8eb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2474984451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2474984451
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1164297928
Short name T117
Test name
Test status
Simulation time 7232849860 ps
CPU time 24.95 seconds
Started May 30 12:35:54 PM PDT 24
Finished May 30 12:36:26 PM PDT 24
Peak memory 214572 kb
Host smart-4bd48858-ce97-45bd-8310-36e34bbe6caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164297928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1164297928
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.725995008
Short name T199
Test name
Test status
Simulation time 84240242253 ps
CPU time 45.84 seconds
Started May 30 12:35:51 PM PDT 24
Finished May 30 12:36:38 PM PDT 24
Peak memory 219352 kb
Host smart-c0a49fb9-1d4b-43e7-9622-95d0384d2788
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725995008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.725995008
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1629426017
Short name T215
Test name
Test status
Simulation time 4388252624 ps
CPU time 15.58 seconds
Started May 30 12:35:50 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 210440 kb
Host smart-c3a338bf-8a76-4b80-8db9-7e757651cd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629426017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1629426017
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2116232909
Short name T313
Test name
Test status
Simulation time 1006818034 ps
CPU time 51.15 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:36:29 PM PDT 24
Peak memory 232548 kb
Host smart-d127b80d-5564-4323-9537-7a503ef45407
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116232909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2116232909
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3900607103
Short name T25
Test name
Test status
Simulation time 2007280884 ps
CPU time 21.39 seconds
Started May 30 12:35:59 PM PDT 24
Finished May 30 12:36:21 PM PDT 24
Peak memory 211264 kb
Host smart-fed9720e-703c-4da9-9891-866ad8c93c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900607103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3900607103
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1559238320
Short name T8
Test name
Test status
Simulation time 435934400 ps
CPU time 8.17 seconds
Started May 30 12:35:38 PM PDT 24
Finished May 30 12:35:48 PM PDT 24
Peak memory 211012 kb
Host smart-b846dc20-6440-4610-91f8-483eded4b183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559238320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1559238320
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.522035538
Short name T209
Test name
Test status
Simulation time 178443300 ps
CPU time 10.18 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:48 PM PDT 24
Peak memory 213008 kb
Host smart-7ff79ef9-5bce-498f-9a0d-26de0bcd0fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522035538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.522035538
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3852572803
Short name T192
Test name
Test status
Simulation time 6879713277 ps
CPU time 68.82 seconds
Started May 30 12:36:00 PM PDT 24
Finished May 30 12:37:10 PM PDT 24
Peak memory 219380 kb
Host smart-68e8ddc5-c1be-440e-8b9c-3ec7ad7c7ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852572803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3852572803
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3816166145
Short name T223
Test name
Test status
Simulation time 65425282490 ps
CPU time 2437 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 01:16:44 PM PDT 24
Peak memory 235804 kb
Host smart-0bd00a35-bcc3-494e-bf9d-25b35051bc6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816166145 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3816166145
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3472511887
Short name T35
Test name
Test status
Simulation time 89760895 ps
CPU time 4.33 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:12 PM PDT 24
Peak memory 211160 kb
Host smart-f5b0a691-f50f-4f05-b1ad-102878b7d397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472511887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3472511887
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2669202349
Short name T159
Test name
Test status
Simulation time 1146929316 ps
CPU time 78.95 seconds
Started May 30 12:35:51 PM PDT 24
Finished May 30 12:37:11 PM PDT 24
Peak memory 228216 kb
Host smart-9d3a1962-4139-48cb-a22f-90f1e2eb0366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669202349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2669202349
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1738073628
Short name T20
Test name
Test status
Simulation time 1384579759 ps
CPU time 9.59 seconds
Started May 30 12:35:51 PM PDT 24
Finished May 30 12:36:02 PM PDT 24
Peak memory 211936 kb
Host smart-68028f83-98c4-4628-a568-53ea741e90ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738073628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1738073628
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1419025350
Short name T218
Test name
Test status
Simulation time 1810392902 ps
CPU time 10.52 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:19 PM PDT 24
Peak memory 211024 kb
Host smart-5608076e-31f4-4969-9f99-09b6ff0baa0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419025350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1419025350
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2047577757
Short name T291
Test name
Test status
Simulation time 8601669973 ps
CPU time 25.12 seconds
Started May 30 12:36:02 PM PDT 24
Finished May 30 12:36:28 PM PDT 24
Peak memory 219348 kb
Host smart-6802c6cd-0651-4752-b1be-4d2e9e9b5874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047577757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2047577757
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2047591445
Short name T315
Test name
Test status
Simulation time 3123599045 ps
CPU time 16.52 seconds
Started May 30 12:35:56 PM PDT 24
Finished May 30 12:36:14 PM PDT 24
Peak memory 210972 kb
Host smart-7da4d447-c435-4e58-a4f0-d417c2d62996
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047591445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2047591445
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3173089096
Short name T264
Test name
Test status
Simulation time 4095465179 ps
CPU time 7.09 seconds
Started May 30 12:35:54 PM PDT 24
Finished May 30 12:36:03 PM PDT 24
Peak memory 211068 kb
Host smart-4abc4078-e6a4-407e-bb9c-e9a463e8bc9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173089096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3173089096
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1694592376
Short name T217
Test name
Test status
Simulation time 30716238396 ps
CPU time 247.72 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:40:14 PM PDT 24
Peak memory 237904 kb
Host smart-c08880b6-3023-4ba4-8163-f52ec0d8725c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694592376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1694592376
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3440438743
Short name T181
Test name
Test status
Simulation time 11544289573 ps
CPU time 20.9 seconds
Started May 30 12:36:12 PM PDT 24
Finished May 30 12:36:35 PM PDT 24
Peak memory 212504 kb
Host smart-93e6ae6d-e74a-4d21-816c-d44c20959309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440438743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3440438743
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3782381862
Short name T122
Test name
Test status
Simulation time 94773017 ps
CPU time 5.26 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:35:59 PM PDT 24
Peak memory 211028 kb
Host smart-867541d2-17c8-41ba-8c15-e92be0442f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782381862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3782381862
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3034010952
Short name T23
Test name
Test status
Simulation time 4383561227 ps
CPU time 26.82 seconds
Started May 30 12:36:03 PM PDT 24
Finished May 30 12:36:31 PM PDT 24
Peak memory 213860 kb
Host smart-679844bd-93de-475a-bf15-3fe942f3164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034010952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3034010952
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2244170977
Short name T139
Test name
Test status
Simulation time 132014686341 ps
CPU time 82.31 seconds
Started May 30 12:36:17 PM PDT 24
Finished May 30 12:37:41 PM PDT 24
Peak memory 219264 kb
Host smart-90e0b25e-dab5-4e06-bba7-62c92dd627e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244170977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2244170977
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3851730891
Short name T202
Test name
Test status
Simulation time 168701924 ps
CPU time 4.19 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:12 PM PDT 24
Peak memory 211132 kb
Host smart-7e38dfb9-ba28-44f6-bb31-9019d2ce67bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851730891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3851730891
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3373642555
Short name T355
Test name
Test status
Simulation time 161258886311 ps
CPU time 222.62 seconds
Started May 30 12:35:55 PM PDT 24
Finished May 30 12:39:40 PM PDT 24
Peak memory 237780 kb
Host smart-c0b83055-4a8e-4438-b3e8-4344cff3fd5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373642555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3373642555
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1784490351
Short name T344
Test name
Test status
Simulation time 4383526588 ps
CPU time 35.17 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:36:42 PM PDT 24
Peak memory 212212 kb
Host smart-1b6ad8ad-4b9f-4765-8723-927bfb60d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784490351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1784490351
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2510722825
Short name T214
Test name
Test status
Simulation time 8205744624 ps
CPU time 17.13 seconds
Started May 30 12:35:49 PM PDT 24
Finished May 30 12:36:07 PM PDT 24
Peak memory 211164 kb
Host smart-df6ec00b-999c-4b51-9127-6ffc8dd6a4ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510722825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2510722825
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.929776242
Short name T248
Test name
Test status
Simulation time 372625400 ps
CPU time 10.21 seconds
Started May 30 12:36:04 PM PDT 24
Finished May 30 12:36:15 PM PDT 24
Peak memory 219196 kb
Host smart-27bbd236-87eb-4f5b-b4b7-f603acb4dbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929776242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.929776242
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2188914989
Short name T362
Test name
Test status
Simulation time 827252081 ps
CPU time 15.35 seconds
Started May 30 12:35:46 PM PDT 24
Finished May 30 12:36:02 PM PDT 24
Peak memory 211652 kb
Host smart-ad7d3a4b-f8bf-4203-9e13-77b872ac43d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188914989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2188914989
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1544043433
Short name T184
Test name
Test status
Simulation time 18863903675 ps
CPU time 14.59 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:36:22 PM PDT 24
Peak memory 211184 kb
Host smart-e536887a-8f39-4608-b627-6206905c687f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544043433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1544043433
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2128192859
Short name T289
Test name
Test status
Simulation time 1567761341 ps
CPU time 88.74 seconds
Started May 30 12:36:10 PM PDT 24
Finished May 30 12:37:40 PM PDT 24
Peak memory 237680 kb
Host smart-771f3484-249e-465a-b7eb-9a6deffc4cff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128192859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2128192859
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.99042247
Short name T146
Test name
Test status
Simulation time 2800552794 ps
CPU time 18.77 seconds
Started May 30 12:36:02 PM PDT 24
Finished May 30 12:36:22 PM PDT 24
Peak memory 211780 kb
Host smart-e613686a-95b8-459c-89b4-ad4437a5de83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99042247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.99042247
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3428949431
Short name T316
Test name
Test status
Simulation time 1682369982 ps
CPU time 8.53 seconds
Started May 30 12:36:03 PM PDT 24
Finished May 30 12:36:13 PM PDT 24
Peak memory 211016 kb
Host smart-f42a828d-2cb7-4e36-b6f2-cbf98700fefe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428949431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3428949431
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1932851175
Short name T124
Test name
Test status
Simulation time 2969772034 ps
CPU time 28.18 seconds
Started May 30 12:36:04 PM PDT 24
Finished May 30 12:36:33 PM PDT 24
Peak memory 219240 kb
Host smart-e19cf34f-602a-4008-b40c-cccc437a700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932851175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1932851175
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.62139361
Short name T195
Test name
Test status
Simulation time 599911177 ps
CPU time 16.06 seconds
Started May 30 12:36:04 PM PDT 24
Finished May 30 12:36:22 PM PDT 24
Peak memory 219116 kb
Host smart-a20ec979-f81b-4296-a2d5-c8fb1af48564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62139361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.rom_ctrl_stress_all.62139361
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.904081276
Short name T56
Test name
Test status
Simulation time 181064436230 ps
CPU time 1613.16 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 01:03:01 PM PDT 24
Peak memory 238692 kb
Host smart-1a4ebcd6-e625-4130-8866-574285a9dbd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904081276 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.904081276
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3143532125
Short name T257
Test name
Test status
Simulation time 1651487710 ps
CPU time 14.34 seconds
Started May 30 12:36:07 PM PDT 24
Finished May 30 12:36:23 PM PDT 24
Peak memory 211028 kb
Host smart-7fefbe44-af79-41d6-9a40-f41baa9cd383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143532125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3143532125
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2852857856
Short name T267
Test name
Test status
Simulation time 82128023561 ps
CPU time 437.33 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:43:11 PM PDT 24
Peak memory 229768 kb
Host smart-76d2d764-1eb0-46b9-82dd-85a7f43d0378
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852857856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2852857856
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.29865087
Short name T277
Test name
Test status
Simulation time 1685884491 ps
CPU time 20.2 seconds
Started May 30 12:35:44 PM PDT 24
Finished May 30 12:36:11 PM PDT 24
Peak memory 211708 kb
Host smart-f3675126-cefa-4805-b005-c9e710233255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29865087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.29865087
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1767039576
Short name T348
Test name
Test status
Simulation time 1958189837 ps
CPU time 16.31 seconds
Started May 30 12:35:54 PM PDT 24
Finished May 30 12:36:12 PM PDT 24
Peak memory 210996 kb
Host smart-6a243ae3-e312-486f-8cd4-b139505858a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767039576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1767039576
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.440613645
Short name T237
Test name
Test status
Simulation time 3680393363 ps
CPU time 37.64 seconds
Started May 30 12:36:02 PM PDT 24
Finished May 30 12:36:41 PM PDT 24
Peak memory 213120 kb
Host smart-76c58d93-7835-4a4d-9e23-13c6e77cb4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440613645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.440613645
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.4062827545
Short name T286
Test name
Test status
Simulation time 9258242816 ps
CPU time 48.96 seconds
Started May 30 12:35:55 PM PDT 24
Finished May 30 12:36:46 PM PDT 24
Peak memory 216372 kb
Host smart-2f06c0e0-a8df-4192-8d47-4f8ce405e562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062827545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.4062827545
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1074289290
Short name T352
Test name
Test status
Simulation time 7329353272 ps
CPU time 15.62 seconds
Started May 30 12:35:57 PM PDT 24
Finished May 30 12:36:14 PM PDT 24
Peak memory 211136 kb
Host smart-433c844a-0bac-4f0e-9d6a-2a022411063e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074289290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1074289290
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.145723884
Short name T28
Test name
Test status
Simulation time 55891107874 ps
CPU time 186.76 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:39:20 PM PDT 24
Peak memory 220496 kb
Host smart-ac34661e-90bd-4faa-8f74-39cc5cdd4e9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145723884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.145723884
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.219183294
Short name T203
Test name
Test status
Simulation time 2792700549 ps
CPU time 17.96 seconds
Started May 30 12:36:06 PM PDT 24
Finished May 30 12:36:25 PM PDT 24
Peak memory 211856 kb
Host smart-059da2ef-8177-4e1a-b5ef-1fcf4947e2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219183294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.219183294
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1622657587
Short name T51
Test name
Test status
Simulation time 100205070 ps
CPU time 5.68 seconds
Started May 30 12:35:54 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 211060 kb
Host smart-64b169d0-b74c-4e5c-95ba-be4e2d3d2d7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622657587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1622657587
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4056594703
Short name T12
Test name
Test status
Simulation time 682388968 ps
CPU time 10.02 seconds
Started May 30 12:35:51 PM PDT 24
Finished May 30 12:36:02 PM PDT 24
Peak memory 213680 kb
Host smart-e6d947fe-ded9-4a70-ac8c-5ceb7e63621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056594703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4056594703
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3607693980
Short name T114
Test name
Test status
Simulation time 2072691130 ps
CPU time 22.48 seconds
Started May 30 12:35:54 PM PDT 24
Finished May 30 12:36:18 PM PDT 24
Peak memory 213628 kb
Host smart-826dc0ad-c65d-438d-913c-bbbcd31782b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607693980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3607693980
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1140230495
Short name T364
Test name
Test status
Simulation time 389587509 ps
CPU time 7.21 seconds
Started May 30 12:36:12 PM PDT 24
Finished May 30 12:36:21 PM PDT 24
Peak memory 210972 kb
Host smart-4b6403ba-e5f3-4902-9c25-7bc9fdf3d556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140230495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1140230495
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3127867328
Short name T38
Test name
Test status
Simulation time 21171308365 ps
CPU time 132.44 seconds
Started May 30 12:35:52 PM PDT 24
Finished May 30 12:38:06 PM PDT 24
Peak memory 227948 kb
Host smart-43b7525c-8d2f-4230-b5f4-2206f6d585ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127867328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3127867328
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.390073974
Short name T168
Test name
Test status
Simulation time 4854745191 ps
CPU time 19.12 seconds
Started May 30 12:35:55 PM PDT 24
Finished May 30 12:36:16 PM PDT 24
Peak memory 212288 kb
Host smart-018d495c-66fc-45cc-be45-0ed413a37833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390073974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.390073974
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3935013837
Short name T188
Test name
Test status
Simulation time 2165889733 ps
CPU time 18.23 seconds
Started May 30 12:35:58 PM PDT 24
Finished May 30 12:36:18 PM PDT 24
Peak memory 211076 kb
Host smart-9fe0852d-e660-4246-9bfb-439801ec1e29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3935013837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3935013837
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.4024740343
Short name T130
Test name
Test status
Simulation time 183348426 ps
CPU time 10.04 seconds
Started May 30 12:36:01 PM PDT 24
Finished May 30 12:36:12 PM PDT 24
Peak memory 213236 kb
Host smart-cb997b5f-fbc5-4348-8c3d-2494acb1785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024740343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.4024740343
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1818997237
Short name T151
Test name
Test status
Simulation time 1362186861 ps
CPU time 17.65 seconds
Started May 30 12:36:09 PM PDT 24
Finished May 30 12:36:28 PM PDT 24
Peak memory 213464 kb
Host smart-040a0747-e0cc-4312-a0c7-b7cb51c6da5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818997237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1818997237
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3620771583
Short name T149
Test name
Test status
Simulation time 3067927722 ps
CPU time 9.85 seconds
Started May 30 12:36:01 PM PDT 24
Finished May 30 12:36:11 PM PDT 24
Peak memory 211156 kb
Host smart-a0f84dd1-0d0f-4b75-bf58-f3548f1e8222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620771583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3620771583
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.579997224
Short name T326
Test name
Test status
Simulation time 70060860522 ps
CPU time 336.18 seconds
Started May 30 12:35:50 PM PDT 24
Finished May 30 12:41:27 PM PDT 24
Peak memory 232916 kb
Host smart-5aeac5e0-738b-4905-b4a0-cfa54cfa2a7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579997224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.579997224
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1770416630
Short name T211
Test name
Test status
Simulation time 13381348353 ps
CPU time 28.43 seconds
Started May 30 12:36:08 PM PDT 24
Finished May 30 12:36:38 PM PDT 24
Peak memory 213792 kb
Host smart-06305322-85fc-4481-8e23-50b86101fef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770416630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1770416630
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4135036459
Short name T115
Test name
Test status
Simulation time 5403631751 ps
CPU time 12.65 seconds
Started May 30 12:36:11 PM PDT 24
Finished May 30 12:36:25 PM PDT 24
Peak memory 211152 kb
Host smart-122903c6-bf7d-4f8e-80ad-c6f77e82c623
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135036459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4135036459
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1223640615
Short name T304
Test name
Test status
Simulation time 15046801441 ps
CPU time 22.6 seconds
Started May 30 12:36:08 PM PDT 24
Finished May 30 12:36:32 PM PDT 24
Peak memory 219284 kb
Host smart-494f52f9-32a8-4524-91b0-db7a72da7a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223640615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1223640615
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1184599826
Short name T274
Test name
Test status
Simulation time 3702696376 ps
CPU time 23.1 seconds
Started May 30 12:36:05 PM PDT 24
Finished May 30 12:36:29 PM PDT 24
Peak memory 213880 kb
Host smart-e04e8ad7-ac70-47b3-a53a-52f3a54962dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184599826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1184599826
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2153284616
Short name T309
Test name
Test status
Simulation time 9643062990 ps
CPU time 17.06 seconds
Started May 30 12:35:17 PM PDT 24
Finished May 30 12:35:35 PM PDT 24
Peak memory 211104 kb
Host smart-42702eba-1359-4542-b44d-c45307ae15a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153284616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2153284616
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.784134392
Short name T50
Test name
Test status
Simulation time 11089188687 ps
CPU time 174.61 seconds
Started May 30 12:35:22 PM PDT 24
Finished May 30 12:38:18 PM PDT 24
Peak memory 234420 kb
Host smart-54b260e3-1caf-4433-bd5d-d608e68df05e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784134392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.784134392
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3560834458
Short name T21
Test name
Test status
Simulation time 4316055561 ps
CPU time 15 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:35:50 PM PDT 24
Peak memory 212208 kb
Host smart-1f802275-bbcb-4473-b47c-7c367bb55ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560834458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3560834458
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1233052434
Short name T312
Test name
Test status
Simulation time 2098583601 ps
CPU time 17.96 seconds
Started May 30 12:35:15 PM PDT 24
Finished May 30 12:35:34 PM PDT 24
Peak memory 211024 kb
Host smart-454b29f4-172d-4397-b3df-be605784acef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233052434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1233052434
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2387421676
Short name T120
Test name
Test status
Simulation time 5379460749 ps
CPU time 16.46 seconds
Started May 30 12:35:12 PM PDT 24
Finished May 30 12:35:30 PM PDT 24
Peak memory 219160 kb
Host smart-72e7a6a0-3f7b-45a3-aa14-32202224ea76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387421676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2387421676
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.842486056
Short name T171
Test name
Test status
Simulation time 14244842119 ps
CPU time 32.64 seconds
Started May 30 12:35:23 PM PDT 24
Finished May 30 12:35:57 PM PDT 24
Peak memory 215120 kb
Host smart-dc13b776-25f9-4c48-951c-772cc8f9f307
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842486056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.842486056
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1027000440
Short name T322
Test name
Test status
Simulation time 1169276382 ps
CPU time 11.29 seconds
Started May 30 12:35:36 PM PDT 24
Finished May 30 12:35:49 PM PDT 24
Peak memory 211008 kb
Host smart-7edc55b0-5dad-4323-a9c1-6c657acd0f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027000440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1027000440
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.186061150
Short name T338
Test name
Test status
Simulation time 2725063235 ps
CPU time 151.54 seconds
Started May 30 12:35:17 PM PDT 24
Finished May 30 12:37:50 PM PDT 24
Peak memory 236976 kb
Host smart-c2086c56-d256-4351-9286-d34556c5ad58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186061150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.186061150
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1706170947
Short name T134
Test name
Test status
Simulation time 6239473210 ps
CPU time 19.92 seconds
Started May 30 12:35:20 PM PDT 24
Finished May 30 12:35:40 PM PDT 24
Peak memory 212344 kb
Host smart-cd5f736b-01d3-4cfe-94d0-18f1eab87909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706170947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1706170947
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4159401362
Short name T138
Test name
Test status
Simulation time 1376688507 ps
CPU time 13.67 seconds
Started May 30 12:35:18 PM PDT 24
Finished May 30 12:35:33 PM PDT 24
Peak memory 211004 kb
Host smart-f43892f3-2c59-4364-9a8a-847cbc1c5630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159401362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4159401362
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1741661694
Short name T76
Test name
Test status
Simulation time 462938189 ps
CPU time 13.29 seconds
Started May 30 12:35:16 PM PDT 24
Finished May 30 12:35:31 PM PDT 24
Peak memory 213216 kb
Host smart-8304001d-d93e-4e13-9e64-c0a7a85a5760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741661694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1741661694
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3294463297
Short name T231
Test name
Test status
Simulation time 237147528 ps
CPU time 12.3 seconds
Started May 30 12:35:17 PM PDT 24
Finished May 30 12:35:30 PM PDT 24
Peak memory 212000 kb
Host smart-3262ab14-8511-419e-976b-a5ff0a2d08eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294463297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3294463297
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2746329453
Short name T314
Test name
Test status
Simulation time 2611467493 ps
CPU time 14.54 seconds
Started May 30 12:35:49 PM PDT 24
Finished May 30 12:36:04 PM PDT 24
Peak memory 211108 kb
Host smart-3b38ce99-818e-407f-a42a-46bd76a9ca1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746329453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2746329453
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.989633115
Short name T269
Test name
Test status
Simulation time 126429358053 ps
CPU time 320.67 seconds
Started May 30 12:35:15 PM PDT 24
Finished May 30 12:40:37 PM PDT 24
Peak memory 224688 kb
Host smart-7ea550ef-1c85-4aa4-891e-629ab4577373
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989633115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.989633115
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3729027996
Short name T196
Test name
Test status
Simulation time 3946489911 ps
CPU time 32.05 seconds
Started May 30 12:35:13 PM PDT 24
Finished May 30 12:35:46 PM PDT 24
Peak memory 211996 kb
Host smart-1f3294d0-3d12-4c11-9b18-654c4d4ecc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729027996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3729027996
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3099882712
Short name T10
Test name
Test status
Simulation time 8878166240 ps
CPU time 17.63 seconds
Started May 30 12:35:16 PM PDT 24
Finished May 30 12:35:39 PM PDT 24
Peak memory 211168 kb
Host smart-2d6987e0-06c9-4711-a70e-8ed8823aaa87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099882712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3099882712
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2496602970
Short name T327
Test name
Test status
Simulation time 764848429 ps
CPU time 10.41 seconds
Started May 30 12:35:15 PM PDT 24
Finished May 30 12:35:27 PM PDT 24
Peak memory 213832 kb
Host smart-16a6034f-00bf-4ec0-b243-a7bcd6ff6488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496602970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2496602970
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.992774038
Short name T11
Test name
Test status
Simulation time 8719713908 ps
CPU time 87.5 seconds
Started May 30 12:35:24 PM PDT 24
Finished May 30 12:36:52 PM PDT 24
Peak memory 216868 kb
Host smart-2d79fb49-5498-4f15-b1bb-962307b393c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992774038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.992774038
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1226619658
Short name T118
Test name
Test status
Simulation time 22121845608 ps
CPU time 16.53 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:53 PM PDT 24
Peak memory 211028 kb
Host smart-3b3a9933-0790-46f5-812b-84a1e16c4bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226619658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1226619658
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1684396072
Short name T258
Test name
Test status
Simulation time 19741599789 ps
CPU time 196.51 seconds
Started May 30 12:35:37 PM PDT 24
Finished May 30 12:38:55 PM PDT 24
Peak memory 227972 kb
Host smart-973380e5-4708-436a-b922-5bf79d1bab7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684396072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1684396072
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1252410192
Short name T311
Test name
Test status
Simulation time 624506827 ps
CPU time 9.42 seconds
Started May 30 12:35:32 PM PDT 24
Finished May 30 12:35:42 PM PDT 24
Peak memory 213496 kb
Host smart-f72ee536-de0d-427a-9ee3-5c1abb467e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252410192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1252410192
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1534590912
Short name T137
Test name
Test status
Simulation time 3240409355 ps
CPU time 14.27 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:51 PM PDT 24
Peak memory 211036 kb
Host smart-0970805f-78b4-4813-bff0-9f07204e3478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534590912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1534590912
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.142881119
Short name T300
Test name
Test status
Simulation time 354767206 ps
CPU time 10.6 seconds
Started May 30 12:35:16 PM PDT 24
Finished May 30 12:35:28 PM PDT 24
Peak memory 213236 kb
Host smart-77d47d7a-5f51-4bb8-9b11-5f04f306c164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142881119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.142881119
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1006939970
Short name T177
Test name
Test status
Simulation time 3280258456 ps
CPU time 35.03 seconds
Started May 30 12:35:24 PM PDT 24
Finished May 30 12:36:00 PM PDT 24
Peak memory 219200 kb
Host smart-3acf3c9f-2c27-48cd-a584-dab7edc636e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006939970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1006939970
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3708650666
Short name T140
Test name
Test status
Simulation time 173441905 ps
CPU time 5.4 seconds
Started May 30 12:35:34 PM PDT 24
Finished May 30 12:35:40 PM PDT 24
Peak memory 211048 kb
Host smart-c75848d6-226a-4cfe-b68a-47504583dab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708650666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3708650666
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1696938234
Short name T110
Test name
Test status
Simulation time 11216475646 ps
CPU time 125.1 seconds
Started May 30 12:35:24 PM PDT 24
Finished May 30 12:37:30 PM PDT 24
Peak memory 212836 kb
Host smart-67421a9d-3411-4482-b83e-68c353e14d81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696938234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1696938234
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2676008386
Short name T164
Test name
Test status
Simulation time 36882630787 ps
CPU time 31.34 seconds
Started May 30 12:35:33 PM PDT 24
Finished May 30 12:36:05 PM PDT 24
Peak memory 212184 kb
Host smart-9c85151a-d5a8-44e4-b53b-62228b4ef5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676008386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2676008386
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2970919043
Short name T152
Test name
Test status
Simulation time 28868763243 ps
CPU time 16.58 seconds
Started May 30 12:35:47 PM PDT 24
Finished May 30 12:36:05 PM PDT 24
Peak memory 210880 kb
Host smart-cbcc471f-8306-474e-a037-c6974bdc5251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970919043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2970919043
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3462082996
Short name T253
Test name
Test status
Simulation time 14403087755 ps
CPU time 29.41 seconds
Started May 30 12:35:31 PM PDT 24
Finished May 30 12:36:01 PM PDT 24
Peak memory 213984 kb
Host smart-852af687-291c-4afc-89b1-4788b1a4e3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462082996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3462082996
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1405797973
Short name T176
Test name
Test status
Simulation time 6954894000 ps
CPU time 14.38 seconds
Started May 30 12:35:35 PM PDT 24
Finished May 30 12:35:50 PM PDT 24
Peak memory 212320 kb
Host smart-30491c25-e20c-43cd-b37c-bb53d40a15fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405797973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1405797973
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%