Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.55 96.97 93.02 97.88 100.00 98.69 97.89 98.37


Total test records in report: 466
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T302 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2309427930 Jun 02 12:41:59 PM PDT 24 Jun 02 12:42:18 PM PDT 24 1234123053 ps
T303 /workspace/coverage/default/31.rom_ctrl_stress_all.1730167917 Jun 02 12:42:20 PM PDT 24 Jun 02 12:42:31 PM PDT 24 788195200 ps
T304 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1702858635 Jun 02 12:42:13 PM PDT 24 Jun 02 12:42:49 PM PDT 24 4493043684 ps
T305 /workspace/coverage/default/20.rom_ctrl_stress_all.2882072456 Jun 02 12:42:14 PM PDT 24 Jun 02 12:42:44 PM PDT 24 10076807134 ps
T306 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2365590884 Jun 02 12:42:16 PM PDT 24 Jun 02 12:47:09 PM PDT 24 118933177602 ps
T307 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3782968236 Jun 02 12:42:27 PM PDT 24 Jun 02 12:43:00 PM PDT 24 8001822517 ps
T308 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2411458067 Jun 02 12:42:31 PM PDT 24 Jun 02 12:42:44 PM PDT 24 1392905979 ps
T309 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1398900615 Jun 02 12:42:31 PM PDT 24 Jun 02 12:42:40 PM PDT 24 2445849615 ps
T310 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2054326038 Jun 02 12:42:08 PM PDT 24 Jun 02 12:42:21 PM PDT 24 2450153157 ps
T311 /workspace/coverage/default/31.rom_ctrl_smoke.1575103601 Jun 02 12:42:29 PM PDT 24 Jun 02 12:42:55 PM PDT 24 9605478755 ps
T312 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1317314143 Jun 02 12:42:36 PM PDT 24 Jun 02 12:42:46 PM PDT 24 9334409394 ps
T313 /workspace/coverage/default/7.rom_ctrl_stress_all.2339641577 Jun 02 12:41:45 PM PDT 24 Jun 02 12:41:58 PM PDT 24 190860511 ps
T314 /workspace/coverage/default/45.rom_ctrl_smoke.229661614 Jun 02 12:42:30 PM PDT 24 Jun 02 12:42:40 PM PDT 24 719206814 ps
T315 /workspace/coverage/default/26.rom_ctrl_stress_all.3266325339 Jun 02 12:42:20 PM PDT 24 Jun 02 12:43:09 PM PDT 24 4254264644 ps
T316 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3232445008 Jun 02 12:42:03 PM PDT 24 Jun 02 12:42:38 PM PDT 24 34063261452 ps
T317 /workspace/coverage/default/33.rom_ctrl_alert_test.676956760 Jun 02 12:42:15 PM PDT 24 Jun 02 12:42:19 PM PDT 24 347279679 ps
T318 /workspace/coverage/default/0.rom_ctrl_stress_all.2001940318 Jun 02 12:41:42 PM PDT 24 Jun 02 12:42:08 PM PDT 24 8672064756 ps
T319 /workspace/coverage/default/8.rom_ctrl_alert_test.1043143010 Jun 02 12:42:04 PM PDT 24 Jun 02 12:42:21 PM PDT 24 7925553689 ps
T320 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3265122175 Jun 02 12:41:54 PM PDT 24 Jun 02 12:42:11 PM PDT 24 13170050657 ps
T321 /workspace/coverage/default/25.rom_ctrl_smoke.3902096847 Jun 02 12:42:20 PM PDT 24 Jun 02 12:42:43 PM PDT 24 1850806738 ps
T322 /workspace/coverage/default/33.rom_ctrl_smoke.2903310921 Jun 02 12:42:32 PM PDT 24 Jun 02 12:42:52 PM PDT 24 2369444037 ps
T323 /workspace/coverage/default/49.rom_ctrl_smoke.3668310440 Jun 02 12:42:38 PM PDT 24 Jun 02 12:42:48 PM PDT 24 189565096 ps
T324 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.723223999 Jun 02 12:42:14 PM PDT 24 Jun 02 12:44:48 PM PDT 24 45578945427 ps
T325 /workspace/coverage/default/39.rom_ctrl_stress_all.3658362262 Jun 02 12:42:31 PM PDT 24 Jun 02 12:43:01 PM PDT 24 8088127689 ps
T326 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2318001136 Jun 02 12:42:08 PM PDT 24 Jun 02 12:42:14 PM PDT 24 368586336 ps
T327 /workspace/coverage/default/19.rom_ctrl_alert_test.712756929 Jun 02 12:42:00 PM PDT 24 Jun 02 12:42:14 PM PDT 24 3441112489 ps
T328 /workspace/coverage/default/48.rom_ctrl_alert_test.1903010535 Jun 02 12:42:34 PM PDT 24 Jun 02 12:42:39 PM PDT 24 332565835 ps
T329 /workspace/coverage/default/32.rom_ctrl_alert_test.3732243926 Jun 02 12:42:20 PM PDT 24 Jun 02 12:42:27 PM PDT 24 292642830 ps
T330 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1261805165 Jun 02 12:41:57 PM PDT 24 Jun 02 12:44:32 PM PDT 24 51193638056 ps
T331 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.159203292 Jun 02 12:42:26 PM PDT 24 Jun 02 01:16:39 PM PDT 24 293038474987 ps
T332 /workspace/coverage/default/10.rom_ctrl_stress_all.1468426990 Jun 02 12:41:59 PM PDT 24 Jun 02 12:42:32 PM PDT 24 2537971531 ps
T333 /workspace/coverage/default/10.rom_ctrl_smoke.621995386 Jun 02 12:41:55 PM PDT 24 Jun 02 12:42:28 PM PDT 24 16433425658 ps
T334 /workspace/coverage/default/43.rom_ctrl_stress_all.3580271360 Jun 02 12:42:30 PM PDT 24 Jun 02 12:42:55 PM PDT 24 1546382780 ps
T335 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2499003387 Jun 02 12:42:25 PM PDT 24 Jun 02 12:42:37 PM PDT 24 251533666 ps
T336 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3811764004 Jun 02 12:41:55 PM PDT 24 Jun 02 12:42:09 PM PDT 24 1366355075 ps
T337 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4197040943 Jun 02 12:42:27 PM PDT 24 Jun 02 12:42:37 PM PDT 24 611537515 ps
T338 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2718829621 Jun 02 12:42:10 PM PDT 24 Jun 02 12:42:43 PM PDT 24 3888479456 ps
T339 /workspace/coverage/default/20.rom_ctrl_smoke.744147282 Jun 02 12:42:22 PM PDT 24 Jun 02 12:42:40 PM PDT 24 2372282008 ps
T340 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1196414535 Jun 02 12:42:16 PM PDT 24 Jun 02 01:27:50 PM PDT 24 274560632728 ps
T341 /workspace/coverage/default/36.rom_ctrl_alert_test.2570440113 Jun 02 12:42:34 PM PDT 24 Jun 02 12:42:48 PM PDT 24 1593081090 ps
T342 /workspace/coverage/default/1.rom_ctrl_stress_all.3549649583 Jun 02 12:42:02 PM PDT 24 Jun 02 12:42:13 PM PDT 24 2470129925 ps
T343 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1575712127 Jun 02 12:42:04 PM PDT 24 Jun 02 12:42:35 PM PDT 24 3505976624 ps
T344 /workspace/coverage/default/43.rom_ctrl_alert_test.315028701 Jun 02 12:42:32 PM PDT 24 Jun 02 12:42:37 PM PDT 24 89117221 ps
T345 /workspace/coverage/default/12.rom_ctrl_smoke.3766023263 Jun 02 12:42:03 PM PDT 24 Jun 02 12:42:41 PM PDT 24 3947336951 ps
T346 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.370754842 Jun 02 12:42:26 PM PDT 24 Jun 02 12:42:41 PM PDT 24 2365365853 ps
T347 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1034522289 Jun 02 12:41:42 PM PDT 24 Jun 02 12:41:59 PM PDT 24 31813918087 ps
T348 /workspace/coverage/default/30.rom_ctrl_stress_all.2482396703 Jun 02 12:42:30 PM PDT 24 Jun 02 12:42:53 PM PDT 24 396158599 ps
T349 /workspace/coverage/default/19.rom_ctrl_stress_all.3591253101 Jun 02 12:42:19 PM PDT 24 Jun 02 12:42:33 PM PDT 24 230020482 ps
T350 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3267945041 Jun 02 12:41:53 PM PDT 24 Jun 02 01:26:07 PM PDT 24 69127706809 ps
T351 /workspace/coverage/default/15.rom_ctrl_smoke.2934905686 Jun 02 12:42:08 PM PDT 24 Jun 02 12:42:42 PM PDT 24 6212111800 ps
T352 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2563705452 Jun 02 12:42:29 PM PDT 24 Jun 02 01:21:23 PM PDT 24 58101228496 ps
T353 /workspace/coverage/default/33.rom_ctrl_stress_all.905422980 Jun 02 12:42:24 PM PDT 24 Jun 02 12:43:03 PM PDT 24 9461599331 ps
T354 /workspace/coverage/default/9.rom_ctrl_stress_all.767604265 Jun 02 12:42:06 PM PDT 24 Jun 02 12:42:29 PM PDT 24 2554230458 ps
T355 /workspace/coverage/default/24.rom_ctrl_stress_all.3184712269 Jun 02 12:42:13 PM PDT 24 Jun 02 12:42:35 PM PDT 24 2161228786 ps
T37 /workspace/coverage/default/1.rom_ctrl_sec_cm.2170062846 Jun 02 12:42:06 PM PDT 24 Jun 02 12:43:01 PM PDT 24 925056783 ps
T356 /workspace/coverage/default/22.rom_ctrl_alert_test.1628420414 Jun 02 12:42:26 PM PDT 24 Jun 02 12:42:31 PM PDT 24 86395325 ps
T357 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3126999552 Jun 02 12:42:32 PM PDT 24 Jun 02 12:46:17 PM PDT 24 162934877567 ps
T358 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.722103105 Jun 02 12:42:29 PM PDT 24 Jun 02 12:46:17 PM PDT 24 15184202178 ps
T359 /workspace/coverage/default/34.rom_ctrl_smoke.2423332852 Jun 02 12:42:15 PM PDT 24 Jun 02 12:42:26 PM PDT 24 707822892 ps
T360 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3385399650 Jun 02 12:41:59 PM PDT 24 Jun 02 12:45:27 PM PDT 24 29379149780 ps
T361 /workspace/coverage/default/44.rom_ctrl_stress_all.4030486364 Jun 02 12:42:40 PM PDT 24 Jun 02 12:43:37 PM PDT 24 5131757420 ps
T362 /workspace/coverage/default/22.rom_ctrl_stress_all.1893193214 Jun 02 12:42:27 PM PDT 24 Jun 02 12:42:55 PM PDT 24 1054433388 ps
T363 /workspace/coverage/default/24.rom_ctrl_alert_test.120309087 Jun 02 12:42:13 PM PDT 24 Jun 02 12:42:18 PM PDT 24 172018300 ps
T364 /workspace/coverage/default/3.rom_ctrl_smoke.267997614 Jun 02 12:42:04 PM PDT 24 Jun 02 12:42:39 PM PDT 24 4055325055 ps
T365 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.155101434 Jun 02 12:42:26 PM PDT 24 Jun 02 12:45:40 PM PDT 24 21592604819 ps
T366 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.994193185 Jun 02 12:42:03 PM PDT 24 Jun 02 12:42:09 PM PDT 24 370137151 ps
T367 /workspace/coverage/default/16.rom_ctrl_alert_test.3674913799 Jun 02 12:41:58 PM PDT 24 Jun 02 12:42:12 PM PDT 24 1360742230 ps
T368 /workspace/coverage/default/9.rom_ctrl_smoke.823968997 Jun 02 12:41:58 PM PDT 24 Jun 02 12:42:23 PM PDT 24 2096307713 ps
T369 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2119398266 Jun 02 12:42:05 PM PDT 24 Jun 02 12:42:22 PM PDT 24 9050048496 ps
T370 /workspace/coverage/default/31.rom_ctrl_alert_test.2646191699 Jun 02 12:42:26 PM PDT 24 Jun 02 12:42:36 PM PDT 24 779565759 ps
T371 /workspace/coverage/default/43.rom_ctrl_smoke.763749100 Jun 02 12:42:39 PM PDT 24 Jun 02 12:43:05 PM PDT 24 6964147265 ps
T67 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1646314805 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:12 PM PDT 24 16594676970 ps
T68 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3635921140 Jun 02 12:43:03 PM PDT 24 Jun 02 12:43:19 PM PDT 24 4802166721 ps
T69 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3263958180 Jun 02 12:42:58 PM PDT 24 Jun 02 12:43:26 PM PDT 24 2344195425 ps
T77 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3269281894 Jun 02 12:42:57 PM PDT 24 Jun 02 12:44:05 PM PDT 24 62807434889 ps
T64 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3148725399 Jun 02 12:43:03 PM PDT 24 Jun 02 12:44:14 PM PDT 24 225293387 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1767552890 Jun 02 12:42:53 PM PDT 24 Jun 02 12:43:14 PM PDT 24 8329194963 ps
T78 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.916389762 Jun 02 12:43:01 PM PDT 24 Jun 02 12:43:11 PM PDT 24 781791650 ps
T373 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.547440796 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:18 PM PDT 24 3432964694 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.649333886 Jun 02 12:43:07 PM PDT 24 Jun 02 12:43:24 PM PDT 24 23553985601 ps
T375 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.290155641 Jun 02 12:43:00 PM PDT 24 Jun 02 12:43:17 PM PDT 24 3358923955 ps
T79 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1511260244 Jun 02 12:42:53 PM PDT 24 Jun 02 12:42:58 PM PDT 24 168090832 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1980036366 Jun 02 12:42:58 PM PDT 24 Jun 02 12:43:08 PM PDT 24 116482508 ps
T65 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1659433052 Jun 02 12:43:02 PM PDT 24 Jun 02 12:43:49 PM PDT 24 9604350075 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2649242920 Jun 02 12:42:45 PM PDT 24 Jun 02 12:43:06 PM PDT 24 2209809440 ps
T113 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3655609297 Jun 02 12:43:02 PM PDT 24 Jun 02 12:43:15 PM PDT 24 1471017172 ps
T114 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1249339164 Jun 02 12:42:54 PM PDT 24 Jun 02 12:43:57 PM PDT 24 24665517032 ps
T115 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3442991186 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:26 PM PDT 24 543004812 ps
T80 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3878317617 Jun 02 12:42:47 PM PDT 24 Jun 02 12:43:03 PM PDT 24 8726457087 ps
T66 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2298518617 Jun 02 12:42:53 PM PDT 24 Jun 02 12:43:34 PM PDT 24 3369386398 ps
T107 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2064539306 Jun 02 12:43:01 PM PDT 24 Jun 02 12:43:09 PM PDT 24 1972529472 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.36447423 Jun 02 12:42:54 PM PDT 24 Jun 02 12:43:11 PM PDT 24 8879628227 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2210111129 Jun 02 12:42:41 PM PDT 24 Jun 02 12:42:46 PM PDT 24 346658022 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3907963196 Jun 02 12:42:53 PM PDT 24 Jun 02 12:42:59 PM PDT 24 389805167 ps
T381 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2349054970 Jun 02 12:42:55 PM PDT 24 Jun 02 12:43:16 PM PDT 24 10357746027 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.136408808 Jun 02 12:42:53 PM PDT 24 Jun 02 12:43:02 PM PDT 24 88051319 ps
T383 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2048800371 Jun 02 12:43:00 PM PDT 24 Jun 02 12:43:13 PM PDT 24 1180995426 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.957243038 Jun 02 12:42:58 PM PDT 24 Jun 02 12:43:05 PM PDT 24 86594297 ps
T108 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3870289136 Jun 02 12:42:48 PM PDT 24 Jun 02 12:42:56 PM PDT 24 3080447831 ps
T109 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3991012355 Jun 02 12:43:05 PM PDT 24 Jun 02 12:43:10 PM PDT 24 171957264 ps
T120 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1278452240 Jun 02 12:42:48 PM PDT 24 Jun 02 12:43:52 PM PDT 24 55625822427 ps
T385 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4066128688 Jun 02 12:42:58 PM PDT 24 Jun 02 12:43:13 PM PDT 24 5427938280 ps
T81 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1132017122 Jun 02 12:43:05 PM PDT 24 Jun 02 12:43:14 PM PDT 24 1254653784 ps
T82 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2574401042 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:45 PM PDT 24 4906052050 ps
T386 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3543365128 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:14 PM PDT 24 7687435487 ps
T110 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3990784489 Jun 02 12:42:59 PM PDT 24 Jun 02 12:43:04 PM PDT 24 85412890 ps
T123 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1247547952 Jun 02 12:43:03 PM PDT 24 Jun 02 12:43:49 PM PDT 24 1783706204 ps
T128 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.7527930 Jun 02 12:42:56 PM PDT 24 Jun 02 12:44:13 PM PDT 24 12472800746 ps
T129 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3536451819 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:42 PM PDT 24 6240512201 ps
T387 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4055199554 Jun 02 12:43:00 PM PDT 24 Jun 02 12:43:17 PM PDT 24 6111288126 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2946326094 Jun 02 12:42:53 PM PDT 24 Jun 02 12:42:58 PM PDT 24 333356264 ps
T121 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.792680265 Jun 02 12:42:43 PM PDT 24 Jun 02 12:44:01 PM PDT 24 3963676984 ps
T126 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3806395738 Jun 02 12:42:40 PM PDT 24 Jun 02 12:43:59 PM PDT 24 2071273856 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2211952244 Jun 02 12:42:50 PM PDT 24 Jun 02 12:43:07 PM PDT 24 2180460770 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1673093711 Jun 02 12:42:40 PM PDT 24 Jun 02 12:42:57 PM PDT 24 4038415283 ps
T111 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.771820060 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:14 PM PDT 24 2033628177 ps
T83 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3061090353 Jun 02 12:42:49 PM PDT 24 Jun 02 12:43:20 PM PDT 24 6652372370 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1614907978 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:03 PM PDT 24 326745157 ps
T391 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1130167023 Jun 02 12:42:59 PM PDT 24 Jun 02 12:43:17 PM PDT 24 1568892951 ps
T122 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2379112550 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:46 PM PDT 24 5339434859 ps
T131 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1222548305 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:41 PM PDT 24 740656340 ps
T112 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3035156929 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:07 PM PDT 24 1020880221 ps
T392 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3280391488 Jun 02 12:42:59 PM PDT 24 Jun 02 12:43:11 PM PDT 24 1161269696 ps
T393 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2941926363 Jun 02 12:43:00 PM PDT 24 Jun 02 12:43:08 PM PDT 24 3089251490 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4148445281 Jun 02 12:42:55 PM PDT 24 Jun 02 12:43:11 PM PDT 24 4472623041 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.881037618 Jun 02 12:42:53 PM PDT 24 Jun 02 12:43:04 PM PDT 24 914816012 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3874029719 Jun 02 12:43:01 PM PDT 24 Jun 02 12:43:14 PM PDT 24 2724221452 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2841005886 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:18 PM PDT 24 1918814793 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.582383123 Jun 02 12:42:49 PM PDT 24 Jun 02 12:44:03 PM PDT 24 4788147072 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2686858405 Jun 02 12:42:51 PM PDT 24 Jun 02 12:43:02 PM PDT 24 1080132385 ps
T85 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.837215527 Jun 02 12:43:11 PM PDT 24 Jun 02 12:43:17 PM PDT 24 127586167 ps
T400 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.760186688 Jun 02 12:42:58 PM PDT 24 Jun 02 12:43:14 PM PDT 24 1968491221 ps
T401 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2440939574 Jun 02 12:43:01 PM PDT 24 Jun 02 12:43:18 PM PDT 24 5666195222 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3256711348 Jun 02 12:42:54 PM PDT 24 Jun 02 12:43:02 PM PDT 24 6128785149 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1490150965 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:10 PM PDT 24 5569750374 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3625497031 Jun 02 12:42:59 PM PDT 24 Jun 02 12:43:16 PM PDT 24 4120835593 ps
T405 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2441231647 Jun 02 12:43:11 PM PDT 24 Jun 02 12:43:23 PM PDT 24 905371676 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2628261194 Jun 02 12:42:44 PM PDT 24 Jun 02 12:42:58 PM PDT 24 3166268503 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1101310522 Jun 02 12:42:58 PM PDT 24 Jun 02 12:43:15 PM PDT 24 8424445723 ps
T407 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1971834950 Jun 02 12:42:53 PM PDT 24 Jun 02 12:43:10 PM PDT 24 4149793869 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1737902964 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:09 PM PDT 24 1069334816 ps
T94 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.453670642 Jun 02 12:42:41 PM PDT 24 Jun 02 12:42:57 PM PDT 24 1966145554 ps
T409 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.776603406 Jun 02 12:43:02 PM PDT 24 Jun 02 12:43:07 PM PDT 24 89255739 ps
T127 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1861892270 Jun 02 12:42:54 PM PDT 24 Jun 02 12:44:08 PM PDT 24 2113438417 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1313149139 Jun 02 12:42:48 PM PDT 24 Jun 02 12:42:55 PM PDT 24 350893553 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.91212922 Jun 02 12:42:48 PM PDT 24 Jun 02 12:43:02 PM PDT 24 5266757961 ps
T412 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.783212162 Jun 02 12:42:55 PM PDT 24 Jun 02 12:43:00 PM PDT 24 99636152 ps
T413 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2357877393 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:14 PM PDT 24 10075022353 ps
T95 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2076879736 Jun 02 12:43:09 PM PDT 24 Jun 02 12:44:13 PM PDT 24 6264691030 ps
T414 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3366743746 Jun 02 12:42:42 PM PDT 24 Jun 02 12:42:58 PM PDT 24 6432345954 ps
T130 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1200924637 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:37 PM PDT 24 1426278196 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1490379005 Jun 02 12:42:54 PM PDT 24 Jun 02 12:42:59 PM PDT 24 346722410 ps
T416 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2975859030 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:15 PM PDT 24 1630526129 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4065909767 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:02 PM PDT 24 1119736779 ps
T418 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1811387751 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:38 PM PDT 24 2097314777 ps
T419 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1276905542 Jun 02 12:43:01 PM PDT 24 Jun 02 12:43:18 PM PDT 24 5861360601 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2783811292 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:16 PM PDT 24 1039751041 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1258979744 Jun 02 12:42:45 PM PDT 24 Jun 02 12:43:03 PM PDT 24 8733720118 ps
T124 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4180076683 Jun 02 12:43:03 PM PDT 24 Jun 02 12:44:21 PM PDT 24 8304889806 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1103538784 Jun 02 12:42:54 PM PDT 24 Jun 02 12:42:59 PM PDT 24 175502830 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.510328196 Jun 02 12:42:41 PM PDT 24 Jun 02 12:42:52 PM PDT 24 6871952636 ps
T96 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4245272791 Jun 02 12:43:10 PM PDT 24 Jun 02 12:44:34 PM PDT 24 40480673097 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3225053788 Jun 02 12:42:47 PM PDT 24 Jun 02 12:42:56 PM PDT 24 608881206 ps
T425 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2720256688 Jun 02 12:42:51 PM PDT 24 Jun 02 12:43:07 PM PDT 24 3945286097 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.575612315 Jun 02 12:42:48 PM PDT 24 Jun 02 12:43:05 PM PDT 24 4010981600 ps
T97 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2141549602 Jun 02 12:42:58 PM PDT 24 Jun 02 12:43:41 PM PDT 24 5060085807 ps
T99 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4077580459 Jun 02 12:42:44 PM PDT 24 Jun 02 12:42:50 PM PDT 24 171587649 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3891885975 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:08 PM PDT 24 2053381118 ps
T427 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3931563730 Jun 02 12:42:59 PM PDT 24 Jun 02 12:43:17 PM PDT 24 16743149034 ps
T428 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.17743934 Jun 02 12:43:00 PM PDT 24 Jun 02 12:43:47 PM PDT 24 37724819850 ps
T429 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.847422471 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:14 PM PDT 24 8277285876 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2362883777 Jun 02 12:42:43 PM PDT 24 Jun 02 12:43:33 PM PDT 24 9577424883 ps
T431 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3061124880 Jun 02 12:43:03 PM PDT 24 Jun 02 12:43:19 PM PDT 24 1649692418 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.617266743 Jun 02 12:43:01 PM PDT 24 Jun 02 12:44:03 PM PDT 24 10625525994 ps
T125 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1788190901 Jun 02 12:42:56 PM PDT 24 Jun 02 12:44:14 PM PDT 24 4718422838 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.749258728 Jun 02 12:42:48 PM PDT 24 Jun 02 12:43:06 PM PDT 24 1664647553 ps
T105 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2646528190 Jun 02 12:43:02 PM PDT 24 Jun 02 12:43:07 PM PDT 24 168052167 ps
T434 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1917754928 Jun 02 12:43:01 PM PDT 24 Jun 02 12:43:12 PM PDT 24 3656362487 ps
T435 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1660256711 Jun 02 12:42:59 PM PDT 24 Jun 02 12:43:04 PM PDT 24 85772878 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3453738920 Jun 02 12:42:50 PM PDT 24 Jun 02 12:43:01 PM PDT 24 1063423880 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3587215821 Jun 02 12:42:49 PM PDT 24 Jun 02 12:42:54 PM PDT 24 168564309 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.602139031 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:14 PM PDT 24 516591032 ps
T438 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2211538068 Jun 02 12:43:02 PM PDT 24 Jun 02 12:43:09 PM PDT 24 168039676 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3980635796 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:22 PM PDT 24 1201765251 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1522767187 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:10 PM PDT 24 3318515445 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4225712238 Jun 02 12:43:00 PM PDT 24 Jun 02 12:43:07 PM PDT 24 827128507 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.663379498 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:12 PM PDT 24 1253380955 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1490666656 Jun 02 12:42:51 PM PDT 24 Jun 02 12:43:04 PM PDT 24 2976962414 ps
T103 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4199011270 Jun 02 12:42:57 PM PDT 24 Jun 02 12:43:55 PM PDT 24 6654209914 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2967099391 Jun 02 12:42:40 PM PDT 24 Jun 02 12:42:54 PM PDT 24 1505639842 ps
T444 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2276679150 Jun 02 12:43:06 PM PDT 24 Jun 02 12:43:10 PM PDT 24 89891763 ps
T445 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1423595607 Jun 02 12:43:00 PM PDT 24 Jun 02 12:43:08 PM PDT 24 1776977710 ps
T100 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2109447192 Jun 02 12:42:53 PM PDT 24 Jun 02 12:44:03 PM PDT 24 15145895247 ps
T446 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.122180730 Jun 02 12:43:01 PM PDT 24 Jun 02 12:44:14 PM PDT 24 7427815117 ps
T447 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3801685189 Jun 02 12:42:55 PM PDT 24 Jun 02 12:43:06 PM PDT 24 2032352447 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3272991489 Jun 02 12:42:40 PM PDT 24 Jun 02 12:42:53 PM PDT 24 16569692624 ps
T449 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1886751549 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:47 PM PDT 24 2630294644 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2592627710 Jun 02 12:43:00 PM PDT 24 Jun 02 12:43:34 PM PDT 24 2579886749 ps
T451 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4199636203 Jun 02 12:42:55 PM PDT 24 Jun 02 12:43:04 PM PDT 24 1172896293 ps
T101 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.284042281 Jun 02 12:43:01 PM PDT 24 Jun 02 12:43:06 PM PDT 24 171324318 ps
T452 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.238849055 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:16 PM PDT 24 4921979119 ps
T106 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3109519285 Jun 02 12:43:01 PM PDT 24 Jun 02 12:43:57 PM PDT 24 38215579000 ps
T453 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.407735609 Jun 02 12:43:06 PM PDT 24 Jun 02 12:43:16 PM PDT 24 134756039 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4155090648 Jun 02 12:42:53 PM PDT 24 Jun 02 12:44:13 PM PDT 24 2334373652 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3496693121 Jun 02 12:42:44 PM PDT 24 Jun 02 12:43:03 PM PDT 24 15135462774 ps
T456 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3321337385 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:19 PM PDT 24 3965736881 ps
T457 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2280240424 Jun 02 12:42:53 PM PDT 24 Jun 02 12:42:59 PM PDT 24 1383120149 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1403379759 Jun 02 12:42:44 PM PDT 24 Jun 02 12:42:53 PM PDT 24 2431103610 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.987326056 Jun 02 12:42:56 PM PDT 24 Jun 02 12:43:09 PM PDT 24 5728531301 ps
T460 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3150512778 Jun 02 12:42:44 PM PDT 24 Jun 02 12:43:41 PM PDT 24 6262102790 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2468507191 Jun 02 12:42:43 PM PDT 24 Jun 02 12:42:52 PM PDT 24 1011806063 ps
T462 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1640862105 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:11 PM PDT 24 333855376 ps
T463 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4130023760 Jun 02 12:43:02 PM PDT 24 Jun 02 12:43:45 PM PDT 24 1204728336 ps
T464 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.427186205 Jun 02 12:42:44 PM PDT 24 Jun 02 12:43:01 PM PDT 24 7552491565 ps
T465 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2010493010 Jun 02 12:42:53 PM PDT 24 Jun 02 12:43:02 PM PDT 24 537505013 ps
T466 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2912496824 Jun 02 12:43:04 PM PDT 24 Jun 02 12:43:21 PM PDT 24 3493199430 ps

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3070398984
Short name T7
Test name
Test status
Simulation time 31831934912 ps
CPU time 345.93 seconds
Started Jun 02 12:42:48 PM PDT 24
Finished Jun 02 12:48:35 PM PDT 24
Peak memory 220176 kb
Host smart-c11f0d02-447d-4080-b890-3dc4f811ab08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070398984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3070398984
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1256344248
Short name T5
Test name
Test status
Simulation time 671695663 ps
CPU time 5.96 seconds
Started Jun 02 12:42:00 PM PDT 24
Finished Jun 02 12:42:06 PM PDT 24
Peak memory 210972 kb
Host smart-e524bbc6-4aa7-4d4a-8fc7-ba5ebfd033e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256344248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1256344248
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4215078299
Short name T23
Test name
Test status
Simulation time 1427831831206 ps
CPU time 4004.13 seconds
Started Jun 02 12:42:10 PM PDT 24
Finished Jun 02 01:48:55 PM PDT 24
Peak memory 244756 kb
Host smart-d4a7507a-3501-40c8-8ac3-9b199cf45cb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215078299 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.4215078299
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3641167994
Short name T15
Test name
Test status
Simulation time 3891540028 ps
CPU time 175.55 seconds
Started Jun 02 12:41:57 PM PDT 24
Finished Jun 02 12:44:53 PM PDT 24
Peak memory 212304 kb
Host smart-00784652-fb95-43c1-a8b5-e6d223c4e133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641167994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3641167994
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2314417971
Short name T134
Test name
Test status
Simulation time 987467823 ps
CPU time 10.81 seconds
Started Jun 02 12:42:40 PM PDT 24
Finished Jun 02 12:42:51 PM PDT 24
Peak memory 210976 kb
Host smart-5eb65f1e-100e-4e95-bb75-313370716d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314417971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2314417971
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.7527930
Short name T128
Test name
Test status
Simulation time 12472800746 ps
CPU time 75.82 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 212484 kb
Host smart-28601724-a5f5-4397-9b51-dc63e0b64dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7527930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_
err.7527930
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.401831169
Short name T9
Test name
Test status
Simulation time 89883396 ps
CPU time 4.28 seconds
Started Jun 02 12:42:23 PM PDT 24
Finished Jun 02 12:42:28 PM PDT 24
Peak memory 211100 kb
Host smart-a5a10b79-b2ac-4fe2-b0b4-6e0f7ba890b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401831169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.401831169
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.367412688
Short name T118
Test name
Test status
Simulation time 5943593156 ps
CPU time 14.86 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:29 PM PDT 24
Peak memory 211064 kb
Host smart-68da1367-87bf-4ec2-b9df-eefa9fd58db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367412688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.367412688
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1018250740
Short name T32
Test name
Test status
Simulation time 517990835 ps
CPU time 54.68 seconds
Started Jun 02 12:41:51 PM PDT 24
Finished Jun 02 12:42:46 PM PDT 24
Peak memory 237320 kb
Host smart-21434d38-86f0-4a63-99e6-745dc0350e29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018250740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1018250740
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.353906271
Short name T6
Test name
Test status
Simulation time 1595383117 ps
CPU time 21.07 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:42:20 PM PDT 24
Peak memory 214140 kb
Host smart-1b195bf6-4d8a-431d-be16-cfcd4532fb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353906271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.353906271
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3269281894
Short name T77
Test name
Test status
Simulation time 62807434889 ps
CPU time 67.78 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:44:05 PM PDT 24
Peak memory 218388 kb
Host smart-a33d94c1-04f4-4942-b24e-5859bcd11364
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269281894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3269281894
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.792680265
Short name T121
Test name
Test status
Simulation time 3963676984 ps
CPU time 76.35 seconds
Started Jun 02 12:42:43 PM PDT 24
Finished Jun 02 12:44:01 PM PDT 24
Peak memory 219392 kb
Host smart-9eba3e0c-c7e4-4056-af9d-f3ec737e80fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792680265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.792680265
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2109447192
Short name T100
Test name
Test status
Simulation time 15145895247 ps
CPU time 69.63 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 211192 kb
Host smart-89ae2217-a897-4248-b7a3-0b176cf7086c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109447192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2109447192
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3739339350
Short name T1
Test name
Test status
Simulation time 4315273802 ps
CPU time 33.42 seconds
Started Jun 02 12:41:43 PM PDT 24
Finished Jun 02 12:42:17 PM PDT 24
Peak memory 212196 kb
Host smart-575d910c-5792-4b7e-b0d7-1eb6967bbdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739339350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3739339350
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.439655105
Short name T140
Test name
Test status
Simulation time 722259587 ps
CPU time 6.96 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:42:07 PM PDT 24
Peak memory 211052 kb
Host smart-0008c977-a92f-43b9-b024-a6cda27fb0aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439655105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.439655105
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3797795975
Short name T27
Test name
Test status
Simulation time 168986941 ps
CPU time 9.63 seconds
Started Jun 02 12:42:09 PM PDT 24
Finished Jun 02 12:42:19 PM PDT 24
Peak memory 211696 kb
Host smart-1f9b28a5-fd72-4792-9348-a42a65a45884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797795975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3797795975
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2751609416
Short name T30
Test name
Test status
Simulation time 9240220153 ps
CPU time 23.1 seconds
Started Jun 02 12:42:31 PM PDT 24
Finished Jun 02 12:42:54 PM PDT 24
Peak memory 212252 kb
Host smart-7ac228fc-cfd3-4561-bb25-6187c4e64e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751609416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2751609416
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2379112550
Short name T122
Test name
Test status
Simulation time 5339434859 ps
CPU time 41.14 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:46 PM PDT 24
Peak memory 219364 kb
Host smart-c6a4fee9-5a9d-4be0-a9af-76702908b5be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379112550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2379112550
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1801849560
Short name T135
Test name
Test status
Simulation time 827400835 ps
CPU time 40.77 seconds
Started Jun 02 12:42:12 PM PDT 24
Finished Jun 02 12:42:54 PM PDT 24
Peak memory 216252 kb
Host smart-f0291173-412d-4cd3-944e-620389329e89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801849560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1801849560
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4180076683
Short name T124
Test name
Test status
Simulation time 8304889806 ps
CPU time 77.19 seconds
Started Jun 02 12:43:03 PM PDT 24
Finished Jun 02 12:44:21 PM PDT 24
Peak memory 219476 kb
Host smart-9459826d-090b-4d61-8c7e-e9c3886ed368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180076683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4180076683
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4077580459
Short name T99
Test name
Test status
Simulation time 171587649 ps
CPU time 4.21 seconds
Started Jun 02 12:42:44 PM PDT 24
Finished Jun 02 12:42:50 PM PDT 24
Peak memory 211484 kb
Host smart-9bbcba9b-f608-4926-8f37-e91d8726531b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077580459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4077580459
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3132364626
Short name T92
Test name
Test status
Simulation time 1646711592 ps
CPU time 22.77 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:49 PM PDT 24
Peak memory 213312 kb
Host smart-03221438-4cc3-4788-8b30-e412f1890b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132364626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3132364626
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2967099391
Short name T104
Test name
Test status
Simulation time 1505639842 ps
CPU time 12.91 seconds
Started Jun 02 12:42:40 PM PDT 24
Finished Jun 02 12:42:54 PM PDT 24
Peak memory 211108 kb
Host smart-509c6709-1a0b-47be-b9b9-d01a169dde24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967099391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2967099391
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3496693121
Short name T455
Test name
Test status
Simulation time 15135462774 ps
CPU time 16.9 seconds
Started Jun 02 12:42:44 PM PDT 24
Finished Jun 02 12:43:03 PM PDT 24
Peak memory 211192 kb
Host smart-fc135997-c939-4e18-a1f9-b93884216e20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496693121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3496693121
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.510328196
Short name T423
Test name
Test status
Simulation time 6871952636 ps
CPU time 10.82 seconds
Started Jun 02 12:42:41 PM PDT 24
Finished Jun 02 12:42:52 PM PDT 24
Peak memory 219432 kb
Host smart-34ab60bb-0c9a-4eda-8ddb-e49ede6a69a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510328196 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.510328196
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2210111129
Short name T379
Test name
Test status
Simulation time 346658022 ps
CPU time 4.17 seconds
Started Jun 02 12:42:41 PM PDT 24
Finished Jun 02 12:42:46 PM PDT 24
Peak memory 211120 kb
Host smart-8b045370-d6a3-459a-8db0-aa47ca2bce00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210111129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2210111129
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.987326056
Short name T459
Test name
Test status
Simulation time 5728531301 ps
CPU time 12.76 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:09 PM PDT 24
Peak memory 211092 kb
Host smart-fb85a200-7cd5-4cfa-83e7-f571fd7b853d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987326056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.987326056
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4148445281
Short name T394
Test name
Test status
Simulation time 4472623041 ps
CPU time 15.67 seconds
Started Jun 02 12:42:55 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 211120 kb
Host smart-14133ae4-6b32-4f9a-8bc4-b0967fbf70eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148445281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4148445281
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3870289136
Short name T108
Test name
Test status
Simulation time 3080447831 ps
CPU time 6.97 seconds
Started Jun 02 12:42:48 PM PDT 24
Finished Jun 02 12:42:56 PM PDT 24
Peak memory 211284 kb
Host smart-fdb00210-71a9-4d9a-8f3a-b608e64089b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870289136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3870289136
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1767552890
Short name T372
Test name
Test status
Simulation time 8329194963 ps
CPU time 20.42 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 216060 kb
Host smart-30befcc5-4356-4ac4-803b-c2c56984438a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767552890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1767552890
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4155090648
Short name T454
Test name
Test status
Simulation time 2334373652 ps
CPU time 79.24 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 219456 kb
Host smart-5c543c39-093e-4bc8-bfe0-0dd29abd8613
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155090648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4155090648
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3878317617
Short name T80
Test name
Test status
Simulation time 8726457087 ps
CPU time 15.38 seconds
Started Jun 02 12:42:47 PM PDT 24
Finished Jun 02 12:43:03 PM PDT 24
Peak memory 211180 kb
Host smart-a45b1909-9085-4114-a71f-ad518fa5357f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878317617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3878317617
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1258979744
Short name T421
Test name
Test status
Simulation time 8733720118 ps
CPU time 17.09 seconds
Started Jun 02 12:42:45 PM PDT 24
Finished Jun 02 12:43:03 PM PDT 24
Peak memory 211456 kb
Host smart-18cc35ec-0f0a-4d7a-b13b-fba5ef671bcd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258979744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1258979744
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.91212922
Short name T411
Test name
Test status
Simulation time 5266757961 ps
CPU time 13.79 seconds
Started Jun 02 12:42:48 PM PDT 24
Finished Jun 02 12:43:02 PM PDT 24
Peak memory 211208 kb
Host smart-7d5cd581-bc97-4dcb-88ed-5308c40596c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91212922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_res
et.91212922
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2468507191
Short name T461
Test name
Test status
Simulation time 1011806063 ps
CPU time 7.01 seconds
Started Jun 02 12:42:43 PM PDT 24
Finished Jun 02 12:42:52 PM PDT 24
Peak memory 219360 kb
Host smart-f03039bc-d589-406b-9b3e-e1137f6669e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468507191 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2468507191
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3225053788
Short name T424
Test name
Test status
Simulation time 608881206 ps
CPU time 7.91 seconds
Started Jun 02 12:42:47 PM PDT 24
Finished Jun 02 12:42:56 PM PDT 24
Peak memory 211244 kb
Host smart-36134b9e-098b-4a0b-84f8-07e544159d15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225053788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3225053788
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.881037618
Short name T395
Test name
Test status
Simulation time 914816012 ps
CPU time 10 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:43:04 PM PDT 24
Peak memory 210972 kb
Host smart-759e053b-29a4-4703-99e6-49bab4a9131d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881037618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.881037618
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1403379759
Short name T458
Test name
Test status
Simulation time 2431103610 ps
CPU time 7.84 seconds
Started Jun 02 12:42:44 PM PDT 24
Finished Jun 02 12:42:53 PM PDT 24
Peak memory 211144 kb
Host smart-543937e6-5cf9-4fcd-99c3-3cf4b4867345
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403379759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1403379759
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3150512778
Short name T460
Test name
Test status
Simulation time 6262102790 ps
CPU time 55.76 seconds
Started Jun 02 12:42:44 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 211564 kb
Host smart-eb8eb6ed-78f3-478d-bb74-70b29a71c93d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150512778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3150512778
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3366743746
Short name T414
Test name
Test status
Simulation time 6432345954 ps
CPU time 15.23 seconds
Started Jun 02 12:42:42 PM PDT 24
Finished Jun 02 12:42:58 PM PDT 24
Peak memory 211312 kb
Host smart-525c37c8-c057-4f2a-b556-de409f441d2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366743746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3366743746
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.136408808
Short name T382
Test name
Test status
Simulation time 88051319 ps
CPU time 8.34 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:43:02 PM PDT 24
Peak memory 214772 kb
Host smart-ef528979-3b8c-4309-8e8d-ef4ef7cd06cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136408808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.136408808
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.582383123
Short name T398
Test name
Test status
Simulation time 4788147072 ps
CPU time 73.16 seconds
Started Jun 02 12:42:49 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 212416 kb
Host smart-7b4572a9-9e8a-4c95-8be8-ebd37dc1bc8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582383123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.582383123
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2048800371
Short name T383
Test name
Test status
Simulation time 1180995426 ps
CPU time 12.63 seconds
Started Jun 02 12:43:00 PM PDT 24
Finished Jun 02 12:43:13 PM PDT 24
Peak memory 219352 kb
Host smart-f9b5355e-6d6c-40e0-a56d-4e89a1b3407c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048800371 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2048800371
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.776603406
Short name T409
Test name
Test status
Simulation time 89255739 ps
CPU time 4.19 seconds
Started Jun 02 12:43:02 PM PDT 24
Finished Jun 02 12:43:07 PM PDT 24
Peak memory 211132 kb
Host smart-d0c8cee8-aaa6-4762-a8bb-87295a5fb4fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776603406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.776603406
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2574401042
Short name T82
Test name
Test status
Simulation time 4906052050 ps
CPU time 46.54 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:45 PM PDT 24
Peak memory 211212 kb
Host smart-73ad50d4-d2ca-4693-bd71-bf361ef37bd3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574401042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2574401042
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3035156929
Short name T112
Test name
Test status
Simulation time 1020880221 ps
CPU time 9.46 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:07 PM PDT 24
Peak memory 211128 kb
Host smart-856f6350-c305-4a8e-b1e8-112543814502
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035156929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3035156929
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1423595607
Short name T445
Test name
Test status
Simulation time 1776977710 ps
CPU time 7.41 seconds
Started Jun 02 12:43:00 PM PDT 24
Finished Jun 02 12:43:08 PM PDT 24
Peak memory 215356 kb
Host smart-55dbdb0e-4ebd-451b-9764-e0843bbab979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423595607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1423595607
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1222548305
Short name T131
Test name
Test status
Simulation time 740656340 ps
CPU time 36.49 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 211196 kb
Host smart-4acbffe8-f714-41c9-90f1-2e25bde10504
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222548305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1222548305
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.783212162
Short name T412
Test name
Test status
Simulation time 99636152 ps
CPU time 4.75 seconds
Started Jun 02 12:42:55 PM PDT 24
Finished Jun 02 12:43:00 PM PDT 24
Peak memory 213192 kb
Host smart-1cd37675-086e-4145-bb0d-4fb547796d13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783212162 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.783212162
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3655609297
Short name T113
Test name
Test status
Simulation time 1471017172 ps
CPU time 12.47 seconds
Started Jun 02 12:43:02 PM PDT 24
Finished Jun 02 12:43:15 PM PDT 24
Peak memory 211136 kb
Host smart-e21ceda4-0296-4be5-ab30-1484f0745d0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655609297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3655609297
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3263958180
Short name T69
Test name
Test status
Simulation time 2344195425 ps
CPU time 28.01 seconds
Started Jun 02 12:42:58 PM PDT 24
Finished Jun 02 12:43:26 PM PDT 24
Peak memory 211360 kb
Host smart-6f20b4de-7a9c-4399-bf43-44f30de70385
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263958180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3263958180
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.847422471
Short name T429
Test name
Test status
Simulation time 8277285876 ps
CPU time 16.55 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 211228 kb
Host smart-f371c689-fe71-4106-bfd8-24c75f0fe57f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847422471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.847422471
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4066128688
Short name T385
Test name
Test status
Simulation time 5427938280 ps
CPU time 14.36 seconds
Started Jun 02 12:42:58 PM PDT 24
Finished Jun 02 12:43:13 PM PDT 24
Peak memory 219468 kb
Host smart-e21d5513-2ef3-40c0-a7a8-61b70f7b0498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066128688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4066128688
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3536451819
Short name T129
Test name
Test status
Simulation time 6240512201 ps
CPU time 45.73 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:42 PM PDT 24
Peak memory 219392 kb
Host smart-ece28605-cf74-4091-982b-6f5feef5c13b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536451819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3536451819
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3635921140
Short name T68
Test name
Test status
Simulation time 4802166721 ps
CPU time 14.24 seconds
Started Jun 02 12:43:03 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 219408 kb
Host smart-e69870af-df01-4ba4-a4a1-413c06585d58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635921140 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3635921140
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.284042281
Short name T101
Test name
Test status
Simulation time 171324318 ps
CPU time 4.15 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:43:06 PM PDT 24
Peak memory 211164 kb
Host smart-c76d59bf-bbdd-46ea-9768-d28d2867a616
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284042281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.284042281
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2975859030
Short name T416
Test name
Test status
Simulation time 1630526129 ps
CPU time 18.52 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:15 PM PDT 24
Peak memory 211168 kb
Host smart-349d761a-0ee4-4a8c-a3fc-9a3fc791f561
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975859030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2975859030
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2064539306
Short name T107
Test name
Test status
Simulation time 1972529472 ps
CPU time 7.55 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:43:09 PM PDT 24
Peak memory 211128 kb
Host smart-c78ccbb5-c16f-4f51-911f-28c052552f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064539306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2064539306
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3931563730
Short name T427
Test name
Test status
Simulation time 16743149034 ps
CPU time 16.9 seconds
Started Jun 02 12:42:59 PM PDT 24
Finished Jun 02 12:43:17 PM PDT 24
Peak memory 219468 kb
Host smart-e34fc9ef-ed73-47e0-8ae0-69e31d454631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931563730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3931563730
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4130023760
Short name T463
Test name
Test status
Simulation time 1204728336 ps
CPU time 42.81 seconds
Started Jun 02 12:43:02 PM PDT 24
Finished Jun 02 12:43:45 PM PDT 24
Peak memory 212004 kb
Host smart-355bd78c-f64c-47b5-952a-42e121ec21ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130023760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4130023760
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2357877393
Short name T413
Test name
Test status
Simulation time 10075022353 ps
CPU time 15.81 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 219540 kb
Host smart-e94932ce-5522-42a0-aff4-fec2f6d8587d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357877393 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2357877393
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1101310522
Short name T93
Test name
Test status
Simulation time 8424445723 ps
CPU time 16.07 seconds
Started Jun 02 12:42:58 PM PDT 24
Finished Jun 02 12:43:15 PM PDT 24
Peak memory 211224 kb
Host smart-0d090831-c547-428e-a72b-be5fdaaac651
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101310522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1101310522
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3980635796
Short name T439
Test name
Test status
Simulation time 1201765251 ps
CPU time 25.82 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:22 PM PDT 24
Peak memory 211184 kb
Host smart-74e175c4-3855-4747-9298-ee0d8a109c41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980635796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3980635796
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1660256711
Short name T435
Test name
Test status
Simulation time 85772878 ps
CPU time 4.32 seconds
Started Jun 02 12:42:59 PM PDT 24
Finished Jun 02 12:43:04 PM PDT 24
Peak memory 211168 kb
Host smart-74426726-7f3c-496e-81d1-2d870bfc71c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660256711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1660256711
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.290155641
Short name T375
Test name
Test status
Simulation time 3358923955 ps
CPU time 17.38 seconds
Started Jun 02 12:43:00 PM PDT 24
Finished Jun 02 12:43:17 PM PDT 24
Peak memory 219544 kb
Host smart-07fe6bcb-fa17-4ca7-96b1-368882dd333d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290155641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.290155641
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1886751549
Short name T449
Test name
Test status
Simulation time 2630294644 ps
CPU time 42.55 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:47 PM PDT 24
Peak memory 212100 kb
Host smart-e98c89ce-cb49-4e4f-ad84-7686a52af0e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886751549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1886751549
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3280391488
Short name T392
Test name
Test status
Simulation time 1161269696 ps
CPU time 11.64 seconds
Started Jun 02 12:42:59 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 219440 kb
Host smart-f319ad64-9807-42ff-ad9b-e7dfed89f107
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280391488 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3280391488
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3891885975
Short name T102
Test name
Test status
Simulation time 2053381118 ps
CPU time 10.27 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:08 PM PDT 24
Peak memory 211140 kb
Host smart-c7ba6d87-8426-4932-9e44-1aa010029b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891885975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3891885975
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1811387751
Short name T418
Test name
Test status
Simulation time 2097314777 ps
CPU time 40.45 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:38 PM PDT 24
Peak memory 211176 kb
Host smart-b37ff305-a936-4a08-9d59-695fa9641f35
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811387751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1811387751
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1276905542
Short name T419
Test name
Test status
Simulation time 5861360601 ps
CPU time 16.15 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 211312 kb
Host smart-57515de0-5fd2-4685-8f42-bfcc9d68d255
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276905542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1276905542
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1640862105
Short name T462
Test name
Test status
Simulation time 333855376 ps
CPU time 6.72 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 219380 kb
Host smart-77cf07ce-aee1-4a6b-ab66-b30626a5fd91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640862105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1640862105
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3874029719
Short name T396
Test name
Test status
Simulation time 2724221452 ps
CPU time 12.36 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 219500 kb
Host smart-01d472f4-ad0f-4ab0-902c-276bdbcac07a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874029719 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3874029719
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2646528190
Short name T105
Test name
Test status
Simulation time 168052167 ps
CPU time 4.13 seconds
Started Jun 02 12:43:02 PM PDT 24
Finished Jun 02 12:43:07 PM PDT 24
Peak memory 211140 kb
Host smart-f14f1f15-238b-4cc7-83ab-c40e0ccd936c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646528190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2646528190
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3442991186
Short name T115
Test name
Test status
Simulation time 543004812 ps
CPU time 28.42 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:26 PM PDT 24
Peak memory 211136 kb
Host smart-629a2c48-b3bd-4e17-a991-79a6f21dc992
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442991186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3442991186
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2783811292
Short name T420
Test name
Test status
Simulation time 1039751041 ps
CPU time 10.57 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:16 PM PDT 24
Peak memory 211508 kb
Host smart-f7a25c1b-c7ca-49ab-9b15-0684d2796560
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783811292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2783811292
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2349054970
Short name T381
Test name
Test status
Simulation time 10357746027 ps
CPU time 20.33 seconds
Started Jun 02 12:42:55 PM PDT 24
Finished Jun 02 12:43:16 PM PDT 24
Peak memory 219472 kb
Host smart-9df9b66a-9ce5-4d60-8d4d-0f4076cf50de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349054970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2349054970
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3148725399
Short name T64
Test name
Test status
Simulation time 225293387 ps
CPU time 70.84 seconds
Started Jun 02 12:43:03 PM PDT 24
Finished Jun 02 12:44:14 PM PDT 24
Peak memory 212232 kb
Host smart-8d8d4789-b7df-4f14-a403-daad540ca359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148725399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3148725399
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.547440796
Short name T373
Test name
Test status
Simulation time 3432964694 ps
CPU time 13.66 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 213496 kb
Host smart-773e2076-b389-4ba7-af57-684f228b1566
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547440796 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.547440796
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2276679150
Short name T444
Test name
Test status
Simulation time 89891763 ps
CPU time 4.16 seconds
Started Jun 02 12:43:06 PM PDT 24
Finished Jun 02 12:43:10 PM PDT 24
Peak memory 211240 kb
Host smart-d47d363e-01b8-4e90-982a-007f06cf33ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276679150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2276679150
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3109519285
Short name T106
Test name
Test status
Simulation time 38215579000 ps
CPU time 55.21 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:43:57 PM PDT 24
Peak memory 211196 kb
Host smart-c1c92a74-2015-4457-9fa6-4c3c1e41659f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109519285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3109519285
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2912496824
Short name T466
Test name
Test status
Simulation time 3493199430 ps
CPU time 15.73 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:21 PM PDT 24
Peak memory 211244 kb
Host smart-c466be94-f97b-47d7-a59e-b8d2f7ee1a93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912496824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2912496824
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.407735609
Short name T453
Test name
Test status
Simulation time 134756039 ps
CPU time 9.75 seconds
Started Jun 02 12:43:06 PM PDT 24
Finished Jun 02 12:43:16 PM PDT 24
Peak memory 219384 kb
Host smart-032562e6-21b6-4457-9f10-c9a53c4f41c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407735609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.407735609
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3061124880
Short name T431
Test name
Test status
Simulation time 1649692418 ps
CPU time 14.74 seconds
Started Jun 02 12:43:03 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 219372 kb
Host smart-7256e6e8-c929-40ac-9cf0-f4de9cb2d797
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061124880 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3061124880
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.238849055
Short name T452
Test name
Test status
Simulation time 4921979119 ps
CPU time 11.57 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:16 PM PDT 24
Peak memory 211256 kb
Host smart-6a1b9ee0-3f99-424c-a4c1-62fec11812e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238849055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.238849055
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2076879736
Short name T95
Test name
Test status
Simulation time 6264691030 ps
CPU time 64.43 seconds
Started Jun 02 12:43:09 PM PDT 24
Finished Jun 02 12:44:13 PM PDT 24
Peak memory 211240 kb
Host smart-c3f6e2c5-3165-4003-b5d4-018c575ba1c1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076879736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2076879736
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1917754928
Short name T434
Test name
Test status
Simulation time 3656362487 ps
CPU time 10.38 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:43:12 PM PDT 24
Peak memory 211188 kb
Host smart-f4e611ce-d06a-44bf-b7ad-18919ace55bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917754928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1917754928
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2211538068
Short name T438
Test name
Test status
Simulation time 168039676 ps
CPU time 6.22 seconds
Started Jun 02 12:43:02 PM PDT 24
Finished Jun 02 12:43:09 PM PDT 24
Peak memory 219488 kb
Host smart-6070d0d0-a3eb-4392-a02b-6bb77a7e4470
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211538068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2211538068
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1247547952
Short name T123
Test name
Test status
Simulation time 1783706204 ps
CPU time 45.06 seconds
Started Jun 02 12:43:03 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 212116 kb
Host smart-f5e5c81d-9008-4ee4-9995-6617a4e4b58f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247547952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1247547952
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.649333886
Short name T374
Test name
Test status
Simulation time 23553985601 ps
CPU time 16.78 seconds
Started Jun 02 12:43:07 PM PDT 24
Finished Jun 02 12:43:24 PM PDT 24
Peak memory 219424 kb
Host smart-d108e734-75b3-4d4e-a713-3fbe349e434d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649333886 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.649333886
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1132017122
Short name T81
Test name
Test status
Simulation time 1254653784 ps
CPU time 8.02 seconds
Started Jun 02 12:43:05 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 211128 kb
Host smart-af95b4a0-d6b6-4005-85ee-d3859cf77f1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132017122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1132017122
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.617266743
Short name T432
Test name
Test status
Simulation time 10625525994 ps
CPU time 61.92 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 211536 kb
Host smart-6c5e0d5b-f78b-4349-bf74-7ade7452e89a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617266743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.617266743
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3991012355
Short name T109
Test name
Test status
Simulation time 171957264 ps
CPU time 4.36 seconds
Started Jun 02 12:43:05 PM PDT 24
Finished Jun 02 12:43:10 PM PDT 24
Peak memory 211096 kb
Host smart-df0df211-5e05-487c-b854-074e37c6018f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991012355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3991012355
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3321337385
Short name T456
Test name
Test status
Simulation time 3965736881 ps
CPU time 14.11 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 219468 kb
Host smart-25a837d6-eb97-4de7-81ba-dee325308e91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321337385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3321337385
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1659433052
Short name T65
Test name
Test status
Simulation time 9604350075 ps
CPU time 46.26 seconds
Started Jun 02 12:43:02 PM PDT 24
Finished Jun 02 12:43:49 PM PDT 24
Peak memory 213144 kb
Host smart-8e452993-67f4-4217-83d8-f9857f2dff3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659433052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1659433052
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2441231647
Short name T405
Test name
Test status
Simulation time 905371676 ps
CPU time 11.2 seconds
Started Jun 02 12:43:11 PM PDT 24
Finished Jun 02 12:43:23 PM PDT 24
Peak memory 219452 kb
Host smart-1037a857-8b1f-4c6b-8259-c813d42f0461
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441231647 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2441231647
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.771820060
Short name T111
Test name
Test status
Simulation time 2033628177 ps
CPU time 9.88 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 211136 kb
Host smart-61a47c90-6c5c-4a39-b6c1-a80061d29b6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771820060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.771820060
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4245272791
Short name T96
Test name
Test status
Simulation time 40480673097 ps
CPU time 83.36 seconds
Started Jun 02 12:43:10 PM PDT 24
Finished Jun 02 12:44:34 PM PDT 24
Peak memory 211244 kb
Host smart-a3767def-099e-4fa7-9213-e3993996283b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245272791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4245272791
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.837215527
Short name T85
Test name
Test status
Simulation time 127586167 ps
CPU time 4.99 seconds
Started Jun 02 12:43:11 PM PDT 24
Finished Jun 02 12:43:17 PM PDT 24
Peak memory 211076 kb
Host smart-9988e945-d917-4165-b4ef-3854ae93903c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837215527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.837215527
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.602139031
Short name T437
Test name
Test status
Simulation time 516591032 ps
CPU time 9.41 seconds
Started Jun 02 12:43:04 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 219420 kb
Host smart-6f50ec46-32bb-4c6d-9cfb-ff0efb397368
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602139031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.602139031
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.122180730
Short name T446
Test name
Test status
Simulation time 7427815117 ps
CPU time 72.11 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:44:14 PM PDT 24
Peak memory 212600 kb
Host smart-ed214abd-5bed-41de-a4d1-42d66f8ae7be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122180730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.122180730
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.453670642
Short name T94
Test name
Test status
Simulation time 1966145554 ps
CPU time 15.34 seconds
Started Jun 02 12:42:41 PM PDT 24
Finished Jun 02 12:42:57 PM PDT 24
Peak memory 211260 kb
Host smart-bb454a8b-cfcc-4722-82bc-01e12c260061
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453670642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.453670642
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1673093711
Short name T390
Test name
Test status
Simulation time 4038415283 ps
CPU time 16.3 seconds
Started Jun 02 12:42:40 PM PDT 24
Finished Jun 02 12:42:57 PM PDT 24
Peak memory 211300 kb
Host smart-f759ffc8-e98b-41a9-9872-3a7117e9e1ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673093711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1673093711
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2628261194
Short name T406
Test name
Test status
Simulation time 3166268503 ps
CPU time 11.9 seconds
Started Jun 02 12:42:44 PM PDT 24
Finished Jun 02 12:42:58 PM PDT 24
Peak memory 211196 kb
Host smart-47bce446-2b69-4bc1-9a94-a934d39e44fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628261194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2628261194
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3907963196
Short name T380
Test name
Test status
Simulation time 389805167 ps
CPU time 4.89 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:42:59 PM PDT 24
Peak memory 219364 kb
Host smart-93c2e1f8-8f0f-4af9-b763-4b398a3a5b2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907963196 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3907963196
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3272991489
Short name T448
Test name
Test status
Simulation time 16569692624 ps
CPU time 12.07 seconds
Started Jun 02 12:42:40 PM PDT 24
Finished Jun 02 12:42:53 PM PDT 24
Peak memory 211180 kb
Host smart-6cc47228-fa58-4887-83e1-b8632ec447ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272991489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3272991489
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.427186205
Short name T464
Test name
Test status
Simulation time 7552491565 ps
CPU time 15.55 seconds
Started Jun 02 12:42:44 PM PDT 24
Finished Jun 02 12:43:01 PM PDT 24
Peak memory 211436 kb
Host smart-aab8bbf5-ccb5-47f6-914b-56dc619f133f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427186205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.427186205
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3453738920
Short name T436
Test name
Test status
Simulation time 1063423880 ps
CPU time 10.49 seconds
Started Jun 02 12:42:50 PM PDT 24
Finished Jun 02 12:43:01 PM PDT 24
Peak memory 211048 kb
Host smart-49cc211b-6fbd-438d-8859-e8a6c91177aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453738920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3453738920
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1278452240
Short name T120
Test name
Test status
Simulation time 55625822427 ps
CPU time 62.57 seconds
Started Jun 02 12:42:48 PM PDT 24
Finished Jun 02 12:43:52 PM PDT 24
Peak memory 211240 kb
Host smart-b7273792-ee6d-4bdd-9309-23d8c30d8a0b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278452240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1278452240
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1103538784
Short name T422
Test name
Test status
Simulation time 175502830 ps
CPU time 4.32 seconds
Started Jun 02 12:42:54 PM PDT 24
Finished Jun 02 12:42:59 PM PDT 24
Peak memory 211224 kb
Host smart-b76a7dc4-3509-49d8-9a8a-621ea36a3959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103538784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1103538784
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1490666656
Short name T443
Test name
Test status
Simulation time 2976962414 ps
CPU time 13.25 seconds
Started Jun 02 12:42:51 PM PDT 24
Finished Jun 02 12:43:04 PM PDT 24
Peak memory 219468 kb
Host smart-2cf980fb-b9cb-406b-a1b2-e476c4604561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490666656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1490666656
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3806395738
Short name T126
Test name
Test status
Simulation time 2071273856 ps
CPU time 78.41 seconds
Started Jun 02 12:42:40 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 211228 kb
Host smart-72654513-0fc7-4bc0-b41e-578ff65ddf0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806395738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3806395738
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3587215821
Short name T98
Test name
Test status
Simulation time 168564309 ps
CPU time 4.25 seconds
Started Jun 02 12:42:49 PM PDT 24
Finished Jun 02 12:42:54 PM PDT 24
Peak memory 211144 kb
Host smart-42e512c9-eebb-4991-9c08-58357298709c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587215821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3587215821
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.36447423
Short name T378
Test name
Test status
Simulation time 8879628227 ps
CPU time 16.6 seconds
Started Jun 02 12:42:54 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 211280 kb
Host smart-e8d55d3e-3670-4a94-a286-805244319ae8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36447423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_ba
sh.36447423
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1313149139
Short name T410
Test name
Test status
Simulation time 350893553 ps
CPU time 5.92 seconds
Started Jun 02 12:42:48 PM PDT 24
Finished Jun 02 12:42:55 PM PDT 24
Peak memory 211132 kb
Host smart-f878e860-79a6-4f82-91b8-0fafc9014377
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313149139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1313149139
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2211952244
Short name T389
Test name
Test status
Simulation time 2180460770 ps
CPU time 16.64 seconds
Started Jun 02 12:42:50 PM PDT 24
Finished Jun 02 12:43:07 PM PDT 24
Peak memory 219456 kb
Host smart-621892be-033f-4d7a-9711-56dfa7541c61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211952244 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2211952244
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2946326094
Short name T388
Test name
Test status
Simulation time 333356264 ps
CPU time 4.31 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:42:58 PM PDT 24
Peak memory 211476 kb
Host smart-b9924c29-e804-4f94-a3eb-a9788439ff09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946326094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2946326094
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4065909767
Short name T417
Test name
Test status
Simulation time 1119736779 ps
CPU time 5.79 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:02 PM PDT 24
Peak memory 211052 kb
Host smart-d4c0f739-bfaa-40fd-bd84-3bfe7030f623
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065909767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4065909767
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4225712238
Short name T441
Test name
Test status
Simulation time 827128507 ps
CPU time 6.5 seconds
Started Jun 02 12:43:00 PM PDT 24
Finished Jun 02 12:43:07 PM PDT 24
Peak memory 211084 kb
Host smart-cd6d45a8-d98f-4f90-a6ef-470ef69c486f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225712238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4225712238
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2362883777
Short name T430
Test name
Test status
Simulation time 9577424883 ps
CPU time 48.23 seconds
Started Jun 02 12:42:43 PM PDT 24
Finished Jun 02 12:43:33 PM PDT 24
Peak memory 211300 kb
Host smart-89b4929b-072f-47de-bed1-7a98eda379c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362883777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2362883777
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2720256688
Short name T425
Test name
Test status
Simulation time 3945286097 ps
CPU time 15.89 seconds
Started Jun 02 12:42:51 PM PDT 24
Finished Jun 02 12:43:07 PM PDT 24
Peak memory 211492 kb
Host smart-a97d20b8-9d1e-41df-96de-2379e2c641c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720256688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2720256688
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2649242920
Short name T377
Test name
Test status
Simulation time 2209809440 ps
CPU time 20.11 seconds
Started Jun 02 12:42:45 PM PDT 24
Finished Jun 02 12:43:06 PM PDT 24
Peak memory 219424 kb
Host smart-8485f1c6-1b18-4062-9964-d10de41259be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649242920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2649242920
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.575612315
Short name T426
Test name
Test status
Simulation time 4010981600 ps
CPU time 15.97 seconds
Started Jun 02 12:42:48 PM PDT 24
Finished Jun 02 12:43:05 PM PDT 24
Peak memory 211324 kb
Host smart-cd9ebe44-77d1-4bbd-b107-2e55f7825e6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575612315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.575612315
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2686858405
Short name T399
Test name
Test status
Simulation time 1080132385 ps
CPU time 10.69 seconds
Started Jun 02 12:42:51 PM PDT 24
Finished Jun 02 12:43:02 PM PDT 24
Peak memory 211168 kb
Host smart-f8f38526-2efd-4385-8fdd-a01d75869412
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686858405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2686858405
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.749258728
Short name T433
Test name
Test status
Simulation time 1664647553 ps
CPU time 16.8 seconds
Started Jun 02 12:42:48 PM PDT 24
Finished Jun 02 12:43:06 PM PDT 24
Peak memory 211264 kb
Host smart-9a22cead-ebe9-4731-a996-cb5be2b65d55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749258728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.749258728
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2010493010
Short name T465
Test name
Test status
Simulation time 537505013 ps
CPU time 8.7 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:43:02 PM PDT 24
Peak memory 219376 kb
Host smart-6dd3d50b-ce16-4775-a040-e91ffb8a86da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010493010 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2010493010
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1646314805
Short name T67
Test name
Test status
Simulation time 16594676970 ps
CPU time 15.75 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:12 PM PDT 24
Peak memory 211256 kb
Host smart-0ca962aa-9e86-4367-bdba-1275a1ab61c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646314805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1646314805
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1522767187
Short name T440
Test name
Test status
Simulation time 3318515445 ps
CPU time 12.33 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:10 PM PDT 24
Peak memory 211040 kb
Host smart-b6159067-d255-4000-8e50-7155a7712b90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522767187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1522767187
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3256711348
Short name T402
Test name
Test status
Simulation time 6128785149 ps
CPU time 7.36 seconds
Started Jun 02 12:42:54 PM PDT 24
Finished Jun 02 12:43:02 PM PDT 24
Peak memory 211264 kb
Host smart-a9fad019-3e35-42e1-8087-65e456d05e90
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256711348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3256711348
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3061090353
Short name T83
Test name
Test status
Simulation time 6652372370 ps
CPU time 30.68 seconds
Started Jun 02 12:42:49 PM PDT 24
Finished Jun 02 12:43:20 PM PDT 24
Peak memory 211176 kb
Host smart-297e4b39-4f08-46bf-9bdf-e10926e549b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061090353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3061090353
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1737902964
Short name T408
Test name
Test status
Simulation time 1069334816 ps
CPU time 12.19 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:09 PM PDT 24
Peak memory 211160 kb
Host smart-db8b93c5-d03f-49bf-9bb8-ffa2b2a6bab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737902964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1737902964
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.663379498
Short name T442
Test name
Test status
Simulation time 1253380955 ps
CPU time 14.59 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:12 PM PDT 24
Peak memory 219380 kb
Host smart-c7597b85-4fdd-4d3e-9f04-561fc9786441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663379498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.663379498
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1788190901
Short name T125
Test name
Test status
Simulation time 4718422838 ps
CPU time 77.62 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:44:14 PM PDT 24
Peak memory 219392 kb
Host smart-777444ae-db91-4a24-afff-e122d32cc34a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788190901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1788190901
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3543365128
Short name T386
Test name
Test status
Simulation time 7687435487 ps
CPU time 17.79 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 219428 kb
Host smart-8f27bedc-e255-4c58-8fd1-985bb8cd7782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543365128 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3543365128
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1511260244
Short name T79
Test name
Test status
Simulation time 168090832 ps
CPU time 4.27 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:42:58 PM PDT 24
Peak memory 211244 kb
Host smart-faca4294-4f19-4f96-a21a-42c890b26420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511260244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1511260244
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1249339164
Short name T114
Test name
Test status
Simulation time 24665517032 ps
CPU time 62.47 seconds
Started Jun 02 12:42:54 PM PDT 24
Finished Jun 02 12:43:57 PM PDT 24
Peak memory 211244 kb
Host smart-5d95548b-dae2-42bd-8b2f-26a82f3d5a2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249339164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1249339164
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3990784489
Short name T110
Test name
Test status
Simulation time 85412890 ps
CPU time 4.4 seconds
Started Jun 02 12:42:59 PM PDT 24
Finished Jun 02 12:43:04 PM PDT 24
Peak memory 211196 kb
Host smart-edff379c-4d95-4626-9f8f-f82723bedc33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990784489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3990784489
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2841005886
Short name T397
Test name
Test status
Simulation time 1918814793 ps
CPU time 19.81 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 219756 kb
Host smart-32426aaf-016b-40ce-9ebf-fc6dd10a85ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841005886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2841005886
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1200924637
Short name T130
Test name
Test status
Simulation time 1426278196 ps
CPU time 40.11 seconds
Started Jun 02 12:42:56 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 211648 kb
Host smart-9bab568a-1b19-44a8-8199-f35e8d5d4b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200924637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1200924637
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4055199554
Short name T387
Test name
Test status
Simulation time 6111288126 ps
CPU time 16.94 seconds
Started Jun 02 12:43:00 PM PDT 24
Finished Jun 02 12:43:17 PM PDT 24
Peak memory 219428 kb
Host smart-456259ef-4f9a-4bd0-ac5f-8c87035cf592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055199554 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4055199554
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1614907978
Short name T84
Test name
Test status
Simulation time 326745157 ps
CPU time 5.42 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:03 PM PDT 24
Peak memory 211204 kb
Host smart-14abbdff-a6c5-4aa3-b4f2-588a130fb6dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614907978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1614907978
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.916389762
Short name T78
Test name
Test status
Simulation time 781791650 ps
CPU time 8.93 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:43:11 PM PDT 24
Peak memory 211216 kb
Host smart-ecf5f874-82c8-4eda-ba1c-761fd1167cb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916389762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.916389762
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1130167023
Short name T391
Test name
Test status
Simulation time 1568892951 ps
CPU time 17.55 seconds
Started Jun 02 12:42:59 PM PDT 24
Finished Jun 02 12:43:17 PM PDT 24
Peak memory 219400 kb
Host smart-a26c2140-c13e-434f-a583-0603313fd2de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130167023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1130167023
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1971834950
Short name T407
Test name
Test status
Simulation time 4149793869 ps
CPU time 16.07 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:43:10 PM PDT 24
Peak memory 219432 kb
Host smart-ac4e3aa5-45fd-4c69-8953-cd0f777a0376
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971834950 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1971834950
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4199636203
Short name T451
Test name
Test status
Simulation time 1172896293 ps
CPU time 7.86 seconds
Started Jun 02 12:42:55 PM PDT 24
Finished Jun 02 12:43:04 PM PDT 24
Peak memory 211232 kb
Host smart-89c37a32-a112-4aee-811d-9f029657d26e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199636203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4199636203
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2141549602
Short name T97
Test name
Test status
Simulation time 5060085807 ps
CPU time 41.64 seconds
Started Jun 02 12:42:58 PM PDT 24
Finished Jun 02 12:43:41 PM PDT 24
Peak memory 211320 kb
Host smart-a418cff7-3e47-4a16-b142-2627a8b7db5c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141549602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2141549602
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2280240424
Short name T457
Test name
Test status
Simulation time 1383120149 ps
CPU time 4.52 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:42:59 PM PDT 24
Peak memory 211172 kb
Host smart-31af13f7-022c-40f0-b649-883e8acc3ff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280240424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2280240424
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1980036366
Short name T376
Test name
Test status
Simulation time 116482508 ps
CPU time 8.81 seconds
Started Jun 02 12:42:58 PM PDT 24
Finished Jun 02 12:43:08 PM PDT 24
Peak memory 219696 kb
Host smart-b7088356-1c82-41f1-a23c-808644b389bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980036366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1980036366
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1861892270
Short name T127
Test name
Test status
Simulation time 2113438417 ps
CPU time 73.04 seconds
Started Jun 02 12:42:54 PM PDT 24
Finished Jun 02 12:44:08 PM PDT 24
Peak memory 212180 kb
Host smart-f6cefe0b-c51e-4e25-8c90-da6bef399e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861892270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1861892270
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2941926363
Short name T393
Test name
Test status
Simulation time 3089251490 ps
CPU time 7.63 seconds
Started Jun 02 12:43:00 PM PDT 24
Finished Jun 02 12:43:08 PM PDT 24
Peak memory 219472 kb
Host smart-575840d4-3d19-4b40-8041-2c159b25e65c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941926363 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2941926363
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1490379005
Short name T415
Test name
Test status
Simulation time 346722410 ps
CPU time 4.32 seconds
Started Jun 02 12:42:54 PM PDT 24
Finished Jun 02 12:42:59 PM PDT 24
Peak memory 211120 kb
Host smart-0b283777-cdbf-4234-abc5-e4757a204b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490379005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1490379005
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2592627710
Short name T450
Test name
Test status
Simulation time 2579886749 ps
CPU time 33.81 seconds
Started Jun 02 12:43:00 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 211224 kb
Host smart-c6bfffc3-3479-4ba1-9c9b-350903e46dc9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592627710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2592627710
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1490150965
Short name T403
Test name
Test status
Simulation time 5569750374 ps
CPU time 12.14 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:10 PM PDT 24
Peak memory 211304 kb
Host smart-6646d8cb-9c3b-462f-a895-8b7fa7d00bc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490150965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1490150965
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.957243038
Short name T384
Test name
Test status
Simulation time 86594297 ps
CPU time 6.73 seconds
Started Jun 02 12:42:58 PM PDT 24
Finished Jun 02 12:43:05 PM PDT 24
Peak memory 219504 kb
Host smart-3f9a19c5-cd9d-45d4-afeb-7124bfd84794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957243038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.957243038
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2298518617
Short name T66
Test name
Test status
Simulation time 3369386398 ps
CPU time 39.71 seconds
Started Jun 02 12:42:53 PM PDT 24
Finished Jun 02 12:43:34 PM PDT 24
Peak memory 213148 kb
Host smart-df853d80-6cf3-4f2f-bdd9-2adf5297dc85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298518617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2298518617
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.760186688
Short name T400
Test name
Test status
Simulation time 1968491221 ps
CPU time 15.18 seconds
Started Jun 02 12:42:58 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 219720 kb
Host smart-4f9480a0-166b-4506-98b5-e1d03570bc65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760186688 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.760186688
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3625497031
Short name T404
Test name
Test status
Simulation time 4120835593 ps
CPU time 16.42 seconds
Started Jun 02 12:42:59 PM PDT 24
Finished Jun 02 12:43:16 PM PDT 24
Peak memory 211232 kb
Host smart-3be4d257-7ea3-4b72-b360-91808a1355b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625497031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3625497031
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4199011270
Short name T103
Test name
Test status
Simulation time 6654209914 ps
CPU time 57.26 seconds
Started Jun 02 12:42:57 PM PDT 24
Finished Jun 02 12:43:55 PM PDT 24
Peak memory 211200 kb
Host smart-1ed62fbd-8959-4727-91d3-2c328ef3db54
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199011270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.4199011270
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3801685189
Short name T447
Test name
Test status
Simulation time 2032352447 ps
CPU time 10.57 seconds
Started Jun 02 12:42:55 PM PDT 24
Finished Jun 02 12:43:06 PM PDT 24
Peak memory 211236 kb
Host smart-a30c9afa-afd6-4f28-a341-ff68ec664e56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801685189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3801685189
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2440939574
Short name T401
Test name
Test status
Simulation time 5666195222 ps
CPU time 16.27 seconds
Started Jun 02 12:43:01 PM PDT 24
Finished Jun 02 12:43:18 PM PDT 24
Peak memory 219552 kb
Host smart-20ae5d42-b6d2-49a6-aad7-e76b081ee0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440939574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2440939574
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.17743934
Short name T428
Test name
Test status
Simulation time 37724819850 ps
CPU time 46.15 seconds
Started Jun 02 12:43:00 PM PDT 24
Finished Jun 02 12:43:47 PM PDT 24
Peak memory 212280 kb
Host smart-a65dce73-61f4-4fdd-9346-bc47a79b3c93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17743934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg
_err.17743934
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3570633926
Short name T262
Test name
Test status
Simulation time 9514241357 ps
CPU time 15.42 seconds
Started Jun 02 12:41:50 PM PDT 24
Finished Jun 02 12:42:06 PM PDT 24
Peak memory 211164 kb
Host smart-ca6ba6ae-10bb-4cec-a636-79a51da41f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570633926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3570633926
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2842804712
Short name T42
Test name
Test status
Simulation time 2053492315 ps
CPU time 121.72 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 236668 kb
Host smart-05000f55-0151-4e2b-88e7-26dfe3a0cd7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842804712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2842804712
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3465863154
Short name T246
Test name
Test status
Simulation time 4483890507 ps
CPU time 17.08 seconds
Started Jun 02 12:41:51 PM PDT 24
Finished Jun 02 12:42:08 PM PDT 24
Peak memory 212152 kb
Host smart-dc784586-c254-4083-810a-56f6f3b2571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465863154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3465863154
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1034522289
Short name T347
Test name
Test status
Simulation time 31813918087 ps
CPU time 16.46 seconds
Started Jun 02 12:41:42 PM PDT 24
Finished Jun 02 12:41:59 PM PDT 24
Peak memory 211140 kb
Host smart-5ad82115-91f2-4111-9cad-b1ec4812f6be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034522289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1034522289
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4190718856
Short name T36
Test name
Test status
Simulation time 7960750134 ps
CPU time 64.15 seconds
Started Jun 02 12:42:09 PM PDT 24
Finished Jun 02 12:43:14 PM PDT 24
Peak memory 236732 kb
Host smart-5e1b1134-5597-493d-aea5-50300e7cc98e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190718856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4190718856
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4265359934
Short name T61
Test name
Test status
Simulation time 1108072374 ps
CPU time 18.57 seconds
Started Jun 02 12:41:51 PM PDT 24
Finished Jun 02 12:42:10 PM PDT 24
Peak memory 219192 kb
Host smart-5a8e4c9f-2768-4966-af38-00fc21cf862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265359934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4265359934
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2001940318
Short name T318
Test name
Test status
Simulation time 8672064756 ps
CPU time 24.93 seconds
Started Jun 02 12:41:42 PM PDT 24
Finished Jun 02 12:42:08 PM PDT 24
Peak memory 214644 kb
Host smart-89dc8c5f-655f-4c54-a7e2-e10583245c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001940318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2001940318
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3267945041
Short name T350
Test name
Test status
Simulation time 69127706809 ps
CPU time 2653.8 seconds
Started Jun 02 12:41:53 PM PDT 24
Finished Jun 02 01:26:07 PM PDT 24
Peak memory 239772 kb
Host smart-09bd5075-bca4-443d-b575-f626e75ad804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267945041 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3267945041
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1304901335
Short name T275
Test name
Test status
Simulation time 88934517 ps
CPU time 4.47 seconds
Started Jun 02 12:42:03 PM PDT 24
Finished Jun 02 12:42:08 PM PDT 24
Peak memory 210980 kb
Host smart-50bb35c5-ce7d-481a-adf7-11fda7d53278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304901335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1304901335
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.86215771
Short name T159
Test name
Test status
Simulation time 3116107537 ps
CPU time 75.6 seconds
Started Jun 02 12:41:45 PM PDT 24
Finished Jun 02 12:43:01 PM PDT 24
Peak memory 212344 kb
Host smart-84b958e5-888b-4bd7-9f4c-0541fc5a19cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86215771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.86215771
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2119398266
Short name T369
Test name
Test status
Simulation time 9050048496 ps
CPU time 16.83 seconds
Started Jun 02 12:42:05 PM PDT 24
Finished Jun 02 12:42:22 PM PDT 24
Peak memory 211144 kb
Host smart-0e856ec5-b1fd-48cb-bfaf-b7619d870823
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119398266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2119398266
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2170062846
Short name T37
Test name
Test status
Simulation time 925056783 ps
CPU time 54.59 seconds
Started Jun 02 12:42:06 PM PDT 24
Finished Jun 02 12:43:01 PM PDT 24
Peak memory 233428 kb
Host smart-6bde9d36-e82e-46fd-bcc9-c64dab5003d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170062846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2170062846
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3549649583
Short name T342
Test name
Test status
Simulation time 2470129925 ps
CPU time 10.74 seconds
Started Jun 02 12:42:02 PM PDT 24
Finished Jun 02 12:42:13 PM PDT 24
Peak memory 211944 kb
Host smart-1940a82e-6b8a-48a8-b637-879a9dc03550
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549649583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3549649583
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.310156190
Short name T254
Test name
Test status
Simulation time 1313766377 ps
CPU time 12.2 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:42:12 PM PDT 24
Peak memory 210964 kb
Host smart-cdafb456-aee0-430a-ba61-ee7402a9d81e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310156190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.310156190
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1516061048
Short name T44
Test name
Test status
Simulation time 20014714592 ps
CPU time 280.93 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:46:40 PM PDT 24
Peak memory 233736 kb
Host smart-6e8dff6c-3cb3-4a65-9429-400a8f405318
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516061048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1516061048
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2318001136
Short name T326
Test name
Test status
Simulation time 368586336 ps
CPU time 5.41 seconds
Started Jun 02 12:42:08 PM PDT 24
Finished Jun 02 12:42:14 PM PDT 24
Peak memory 210960 kb
Host smart-e50e81e4-aade-499c-a649-6c9bd58ddc95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2318001136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2318001136
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.621995386
Short name T333
Test name
Test status
Simulation time 16433425658 ps
CPU time 32.6 seconds
Started Jun 02 12:41:55 PM PDT 24
Finished Jun 02 12:42:28 PM PDT 24
Peak memory 213948 kb
Host smart-f3ede5cb-cde8-4e2f-9ee9-92a35349d911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621995386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.621995386
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1468426990
Short name T332
Test name
Test status
Simulation time 2537971531 ps
CPU time 32.74 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:42:32 PM PDT 24
Peak memory 213072 kb
Host smart-a79b6037-82e4-4b14-9c57-a0204e09d405
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468426990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1468426990
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3074137998
Short name T249
Test name
Test status
Simulation time 1901329790 ps
CPU time 15.03 seconds
Started Jun 02 12:41:57 PM PDT 24
Finished Jun 02 12:42:13 PM PDT 24
Peak memory 211028 kb
Host smart-1eaf0274-183c-4f46-a627-328e86bd9f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074137998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3074137998
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1261805165
Short name T330
Test name
Test status
Simulation time 51193638056 ps
CPU time 154.44 seconds
Started Jun 02 12:41:57 PM PDT 24
Finished Jun 02 12:44:32 PM PDT 24
Peak memory 228588 kb
Host smart-f9dfdd60-d4cb-4992-92a4-2594b88d42d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261805165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1261805165
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2420433084
Short name T163
Test name
Test status
Simulation time 16149916323 ps
CPU time 31.72 seconds
Started Jun 02 12:42:16 PM PDT 24
Finished Jun 02 12:42:48 PM PDT 24
Peak memory 211940 kb
Host smart-69ff940c-95dd-4b7d-ba06-6ce31aad3efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420433084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2420433084
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3736536771
Short name T205
Test name
Test status
Simulation time 630356087 ps
CPU time 9.85 seconds
Started Jun 02 12:42:03 PM PDT 24
Finished Jun 02 12:42:13 PM PDT 24
Peak memory 210976 kb
Host smart-6fb770a2-6671-40dc-af4e-7b7492448ec0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3736536771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3736536771
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3187928252
Short name T10
Test name
Test status
Simulation time 7915791996 ps
CPU time 38.14 seconds
Started Jun 02 12:42:00 PM PDT 24
Finished Jun 02 12:42:39 PM PDT 24
Peak memory 213620 kb
Host smart-07037b7f-f7c6-492f-9b2d-b10bf84b698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187928252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3187928252
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4023125974
Short name T291
Test name
Test status
Simulation time 950201014 ps
CPU time 16.9 seconds
Started Jun 02 12:42:10 PM PDT 24
Finished Jun 02 12:42:28 PM PDT 24
Peak memory 213132 kb
Host smart-64894b59-ce9f-4bc9-90a8-883db0b0f2b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023125974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4023125974
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.403124088
Short name T259
Test name
Test status
Simulation time 5159088433 ps
CPU time 10.52 seconds
Started Jun 02 12:41:52 PM PDT 24
Finished Jun 02 12:42:02 PM PDT 24
Peak memory 211156 kb
Host smart-b2070f86-6075-48c7-9293-45e872774737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403124088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.403124088
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3284755009
Short name T290
Test name
Test status
Simulation time 46550640385 ps
CPU time 439.98 seconds
Started Jun 02 12:42:08 PM PDT 24
Finished Jun 02 12:49:29 PM PDT 24
Peak memory 212328 kb
Host smart-9fe244ae-7b50-4144-aecc-221ac64634e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284755009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3284755009
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.950426277
Short name T3
Test name
Test status
Simulation time 7133171901 ps
CPU time 21.06 seconds
Started Jun 02 12:41:57 PM PDT 24
Finished Jun 02 12:42:19 PM PDT 24
Peak memory 212192 kb
Host smart-ecb8e2c6-285a-45ed-bc59-992e9e50d939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950426277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.950426277
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3766023263
Short name T345
Test name
Test status
Simulation time 3947336951 ps
CPU time 37.42 seconds
Started Jun 02 12:42:03 PM PDT 24
Finished Jun 02 12:42:41 PM PDT 24
Peak memory 219264 kb
Host smart-d1fa9d79-fcbe-4ffd-add3-731137373cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766023263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3766023263
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1764409972
Short name T56
Test name
Test status
Simulation time 1568728730 ps
CPU time 6.78 seconds
Started Jun 02 12:42:11 PM PDT 24
Finished Jun 02 12:42:18 PM PDT 24
Peak memory 211100 kb
Host smart-e7a1969c-1a9d-495c-ac8d-f390a037e0ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764409972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1764409972
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1658446890
Short name T220
Test name
Test status
Simulation time 13733890036 ps
CPU time 152.7 seconds
Started Jun 02 12:41:50 PM PDT 24
Finished Jun 02 12:44:23 PM PDT 24
Peak memory 236708 kb
Host smart-5f469ead-c490-4a88-9737-6d6835c753f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658446890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1658446890
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4265112911
Short name T153
Test name
Test status
Simulation time 1674426436 ps
CPU time 14.85 seconds
Started Jun 02 12:42:03 PM PDT 24
Finished Jun 02 12:42:18 PM PDT 24
Peak memory 211900 kb
Host smart-de061af4-c73e-4698-b094-c4e74e4171df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265112911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4265112911
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4079474406
Short name T282
Test name
Test status
Simulation time 141413182 ps
CPU time 6.49 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:42:05 PM PDT 24
Peak memory 211000 kb
Host smart-a1f16449-99ac-4052-98b9-a12dcae04414
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079474406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4079474406
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.173542095
Short name T210
Test name
Test status
Simulation time 186617988 ps
CPU time 10.58 seconds
Started Jun 02 12:42:05 PM PDT 24
Finished Jun 02 12:42:16 PM PDT 24
Peak memory 213484 kb
Host smart-cb59ae6f-5dd1-41a4-b20f-d00e142dbf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173542095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.173542095
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3005870515
Short name T219
Test name
Test status
Simulation time 1115527879 ps
CPU time 16.32 seconds
Started Jun 02 12:42:02 PM PDT 24
Finished Jun 02 12:42:18 PM PDT 24
Peak memory 211868 kb
Host smart-e431f40a-11fd-4a4d-9ba0-12d130e98403
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005870515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3005870515
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4191024392
Short name T24
Test name
Test status
Simulation time 156960430246 ps
CPU time 1777.18 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 01:11:37 PM PDT 24
Peak memory 244084 kb
Host smart-663abe32-57b6-4802-b2ed-f8ad59bc9227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191024392 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.4191024392
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.844746667
Short name T75
Test name
Test status
Simulation time 2568882521 ps
CPU time 7.07 seconds
Started Jun 02 12:42:02 PM PDT 24
Finished Jun 02 12:42:15 PM PDT 24
Peak memory 211092 kb
Host smart-d8fff349-3ddf-4546-be42-579a3c926ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844746667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.844746667
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3385399650
Short name T360
Test name
Test status
Simulation time 29379149780 ps
CPU time 208.18 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:45:27 PM PDT 24
Peak memory 228384 kb
Host smart-f29406ab-4b41-493f-a491-2b652780354b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385399650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3385399650
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2309427930
Short name T302
Test name
Test status
Simulation time 1234123053 ps
CPU time 17.64 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:42:18 PM PDT 24
Peak memory 212208 kb
Host smart-66155c0a-ce45-4254-bf1d-a994fba46691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309427930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2309427930
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3604871411
Short name T218
Test name
Test status
Simulation time 3968803744 ps
CPU time 42.56 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:42:42 PM PDT 24
Peak memory 212656 kb
Host smart-d8c00424-da7a-4c6b-936f-a2aaa2bf8e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604871411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3604871411
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.199193047
Short name T231
Test name
Test status
Simulation time 16677863721 ps
CPU time 45.03 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:42:44 PM PDT 24
Peak memory 217108 kb
Host smart-3e183d79-4bb5-4909-b352-5676ea2c77c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199193047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.199193047
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.349145323
Short name T74
Test name
Test status
Simulation time 3553377726 ps
CPU time 10.95 seconds
Started Jun 02 12:42:10 PM PDT 24
Finished Jun 02 12:42:21 PM PDT 24
Peak memory 211096 kb
Host smart-3cf42057-a97c-481b-8354-38ef4e94f8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349145323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.349145323
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3021625279
Short name T227
Test name
Test status
Simulation time 41074547986 ps
CPU time 420.05 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:48:59 PM PDT 24
Peak memory 212348 kb
Host smart-9c6c6b06-70dd-401c-8fc8-6f1acfb2832c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021625279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3021625279
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3319999758
Short name T235
Test name
Test status
Simulation time 175243985 ps
CPU time 9.72 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:42:10 PM PDT 24
Peak memory 212016 kb
Host smart-ce25e471-83a3-4e14-a9a2-b3d41a895240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319999758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3319999758
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.994193185
Short name T366
Test name
Test status
Simulation time 370137151 ps
CPU time 5.56 seconds
Started Jun 02 12:42:03 PM PDT 24
Finished Jun 02 12:42:09 PM PDT 24
Peak memory 211028 kb
Host smart-80c8bc08-a5e6-4fac-98e3-c826006bffa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994193185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.994193185
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2934905686
Short name T351
Test name
Test status
Simulation time 6212111800 ps
CPU time 33.12 seconds
Started Jun 02 12:42:08 PM PDT 24
Finished Jun 02 12:42:42 PM PDT 24
Peak memory 213988 kb
Host smart-3f4eb75e-0476-4271-a4a2-a65a97475f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934905686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2934905686
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3461457736
Short name T12
Test name
Test status
Simulation time 3539112037 ps
CPU time 15.79 seconds
Started Jun 02 12:41:57 PM PDT 24
Finished Jun 02 12:42:14 PM PDT 24
Peak memory 219204 kb
Host smart-41a23bbf-7819-4c4f-8dc2-4ced73a54117
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461457736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3461457736
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3674913799
Short name T367
Test name
Test status
Simulation time 1360742230 ps
CPU time 13.03 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:42:12 PM PDT 24
Peak memory 211040 kb
Host smart-b1726500-c707-4141-97d7-56b18c06d5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674913799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3674913799
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3991756558
Short name T253
Test name
Test status
Simulation time 93744926862 ps
CPU time 269.88 seconds
Started Jun 02 12:41:57 PM PDT 24
Finished Jun 02 12:46:28 PM PDT 24
Peak memory 224976 kb
Host smart-ef3db2ef-d75c-4c51-bd44-082c36c9bb0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991756558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3991756558
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3102091570
Short name T287
Test name
Test status
Simulation time 825568873 ps
CPU time 15.33 seconds
Started Jun 02 12:42:11 PM PDT 24
Finished Jun 02 12:42:27 PM PDT 24
Peak memory 211720 kb
Host smart-75d26eae-24d7-4d29-a0c3-1017f8001bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102091570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3102091570
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1792930521
Short name T179
Test name
Test status
Simulation time 1537635038 ps
CPU time 14.42 seconds
Started Jun 02 12:42:11 PM PDT 24
Finished Jun 02 12:42:26 PM PDT 24
Peak memory 211076 kb
Host smart-58425ca5-21f3-4a52-af24-ff37bde6ae42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792930521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1792930521
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4203331891
Short name T268
Test name
Test status
Simulation time 2017384138 ps
CPU time 24.64 seconds
Started Jun 02 12:42:06 PM PDT 24
Finished Jun 02 12:42:31 PM PDT 24
Peak memory 211748 kb
Host smart-ed9b573c-ed3d-4f1b-902d-4972366ca64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203331891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4203331891
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2475862493
Short name T214
Test name
Test status
Simulation time 218466743 ps
CPU time 12.69 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:42:12 PM PDT 24
Peak memory 213424 kb
Host smart-2b9a4780-ddbb-4de1-a43e-dcaf63acad4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475862493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2475862493
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.975337077
Short name T301
Test name
Test status
Simulation time 13310562595 ps
CPU time 447.92 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:49:27 PM PDT 24
Peak memory 224468 kb
Host smart-a8eac044-5636-47c1-82cb-c06bc0c41f45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975337077 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.975337077
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3063150970
Short name T263
Test name
Test status
Simulation time 3972692179 ps
CPU time 11.1 seconds
Started Jun 02 12:42:09 PM PDT 24
Finished Jun 02 12:42:21 PM PDT 24
Peak memory 211028 kb
Host smart-bc4b9a0c-277a-4f81-b286-2cc16aabaee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063150970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3063150970
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3442872046
Short name T161
Test name
Test status
Simulation time 9559281416 ps
CPU time 117.2 seconds
Started Jun 02 12:42:22 PM PDT 24
Finished Jun 02 12:44:20 PM PDT 24
Peak memory 230852 kb
Host smart-2b621195-f659-4404-9218-2d2d0dac8383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442872046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3442872046
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3025396370
Short name T274
Test name
Test status
Simulation time 24334618092 ps
CPU time 32.68 seconds
Started Jun 02 12:42:15 PM PDT 24
Finished Jun 02 12:42:48 PM PDT 24
Peak memory 212464 kb
Host smart-96b61664-73e0-4aed-8ab3-f3d900e021fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025396370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3025396370
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1678006267
Short name T244
Test name
Test status
Simulation time 98613127 ps
CPU time 5.87 seconds
Started Jun 02 12:42:12 PM PDT 24
Finished Jun 02 12:42:19 PM PDT 24
Peak memory 211024 kb
Host smart-9f93dc37-4270-4b66-ba0d-44c2c106c812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678006267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1678006267
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.239160860
Short name T177
Test name
Test status
Simulation time 3339464849 ps
CPU time 32.4 seconds
Started Jun 02 12:42:11 PM PDT 24
Finished Jun 02 12:42:43 PM PDT 24
Peak memory 213204 kb
Host smart-ce14b053-c854-49a6-8be7-cbff15de7b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239160860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.239160860
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1930508662
Short name T88
Test name
Test status
Simulation time 14040971858 ps
CPU time 62.2 seconds
Started Jun 02 12:42:00 PM PDT 24
Finished Jun 02 12:43:02 PM PDT 24
Peak memory 219640 kb
Host smart-bb225fd0-fab2-4cc0-8b50-a70bb6d88b93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930508662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1930508662
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2668383194
Short name T71
Test name
Test status
Simulation time 1925103072 ps
CPU time 6.43 seconds
Started Jun 02 12:42:05 PM PDT 24
Finished Jun 02 12:42:12 PM PDT 24
Peak memory 211048 kb
Host smart-2a964e11-6dbc-487a-9272-2061b6661eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668383194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2668383194
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1579110778
Short name T293
Test name
Test status
Simulation time 52368247433 ps
CPU time 375.9 seconds
Started Jun 02 12:42:14 PM PDT 24
Finished Jun 02 12:48:31 PM PDT 24
Peak memory 234120 kb
Host smart-f9cb3972-2eea-453d-bc1c-3a96aa2a28dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579110778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1579110778
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4132905472
Short name T39
Test name
Test status
Simulation time 3909086619 ps
CPU time 20.99 seconds
Started Jun 02 12:42:12 PM PDT 24
Finished Jun 02 12:42:33 PM PDT 24
Peak memory 211944 kb
Host smart-9d2c17b0-ec88-495c-a852-bcad84bda1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132905472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4132905472
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1301094914
Short name T117
Test name
Test status
Simulation time 4313176594 ps
CPU time 11.04 seconds
Started Jun 02 12:42:04 PM PDT 24
Finished Jun 02 12:42:16 PM PDT 24
Peak memory 211032 kb
Host smart-4bc7c03a-59c6-4172-9ec6-fbb69eb75633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301094914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1301094914
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.814475733
Short name T209
Test name
Test status
Simulation time 8955376149 ps
CPU time 39.13 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:42:39 PM PDT 24
Peak memory 219252 kb
Host smart-e8a4c26d-61e4-4abc-a536-41dce575460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814475733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.814475733
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.843936514
Short name T144
Test name
Test status
Simulation time 7172420645 ps
CPU time 28.5 seconds
Started Jun 02 12:42:14 PM PDT 24
Finished Jun 02 12:42:43 PM PDT 24
Peak memory 214736 kb
Host smart-d9476994-460f-4654-95da-048a0771be11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843936514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.843936514
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1196414535
Short name T340
Test name
Test status
Simulation time 274560632728 ps
CPU time 2733.38 seconds
Started Jun 02 12:42:16 PM PDT 24
Finished Jun 02 01:27:50 PM PDT 24
Peak memory 237564 kb
Host smart-a3f724b3-3b92-4d21-9802-e4c028f1f403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196414535 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1196414535
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.712756929
Short name T327
Test name
Test status
Simulation time 3441112489 ps
CPU time 14.04 seconds
Started Jun 02 12:42:00 PM PDT 24
Finished Jun 02 12:42:14 PM PDT 24
Peak memory 211100 kb
Host smart-a760975b-3c48-433b-be40-39193ce769f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712756929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.712756929
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1736216532
Short name T16
Test name
Test status
Simulation time 13672580520 ps
CPU time 150.24 seconds
Started Jun 02 12:42:04 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 237276 kb
Host smart-ff66a44b-e224-4ce4-a2ee-bc84f134facf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736216532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1736216532
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3740116456
Short name T31
Test name
Test status
Simulation time 18985224056 ps
CPU time 28.66 seconds
Started Jun 02 12:42:24 PM PDT 24
Finished Jun 02 12:42:54 PM PDT 24
Peak memory 212192 kb
Host smart-248d55d7-a68d-49fa-85d5-623e4caa7a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740116456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3740116456
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3971236495
Short name T169
Test name
Test status
Simulation time 683440179 ps
CPU time 9.82 seconds
Started Jun 02 12:42:23 PM PDT 24
Finished Jun 02 12:42:34 PM PDT 24
Peak memory 211004 kb
Host smart-1d2f3a86-89a2-4a35-8635-2833b57a71e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971236495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3971236495
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1138014317
Short name T19
Test name
Test status
Simulation time 363088672 ps
CPU time 13.37 seconds
Started Jun 02 12:42:11 PM PDT 24
Finished Jun 02 12:42:25 PM PDT 24
Peak memory 213040 kb
Host smart-ac7aa35d-ab62-4c85-8b29-49777e860239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138014317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1138014317
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3591253101
Short name T349
Test name
Test status
Simulation time 230020482 ps
CPU time 13.99 seconds
Started Jun 02 12:42:19 PM PDT 24
Finished Jun 02 12:42:33 PM PDT 24
Peak memory 212812 kb
Host smart-853005ee-6435-47dd-a461-03cb39edc8e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591253101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3591253101
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3448774417
Short name T55
Test name
Test status
Simulation time 80901440936 ps
CPU time 722 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:54:00 PM PDT 24
Peak memory 229540 kb
Host smart-910b03b5-3921-40c9-9bcf-a3f6e267026e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448774417 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3448774417
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1687538027
Short name T160
Test name
Test status
Simulation time 1404672346 ps
CPU time 12.66 seconds
Started Jun 02 12:41:50 PM PDT 24
Finished Jun 02 12:42:03 PM PDT 24
Peak memory 211052 kb
Host smart-087c3f22-7005-45d2-911b-ddded8f59222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687538027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1687538027
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1944092800
Short name T223
Test name
Test status
Simulation time 9179699093 ps
CPU time 152.11 seconds
Started Jun 02 12:41:55 PM PDT 24
Finished Jun 02 12:44:27 PM PDT 24
Peak memory 230060 kb
Host smart-43d6dd1c-c3ef-4971-bb8a-044cc09a5a74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944092800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1944092800
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2491113956
Short name T233
Test name
Test status
Simulation time 6974968817 ps
CPU time 18.46 seconds
Started Jun 02 12:41:53 PM PDT 24
Finished Jun 02 12:42:12 PM PDT 24
Peak memory 212284 kb
Host smart-aed6e463-2e21-4f8b-8e0e-dee2eb95faee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491113956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2491113956
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.279388415
Short name T215
Test name
Test status
Simulation time 3114564549 ps
CPU time 10.43 seconds
Started Jun 02 12:41:52 PM PDT 24
Finished Jun 02 12:42:03 PM PDT 24
Peak memory 211048 kb
Host smart-4ee90434-8236-4ea3-9da4-c2b3a8cda26a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279388415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.279388415
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1283504766
Short name T33
Test name
Test status
Simulation time 1875479871 ps
CPU time 58.43 seconds
Started Jun 02 12:41:56 PM PDT 24
Finished Jun 02 12:42:56 PM PDT 24
Peak memory 230148 kb
Host smart-8ab9d2e8-75e7-41ce-9724-a9a1caceb18e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283504766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1283504766
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.792557440
Short name T11
Test name
Test status
Simulation time 1131979014 ps
CPU time 16.93 seconds
Started Jun 02 12:41:55 PM PDT 24
Finished Jun 02 12:42:13 PM PDT 24
Peak memory 219200 kb
Host smart-8d82767d-ed44-42a0-a2a0-faa45f54f608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792557440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.792557440
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2744581026
Short name T197
Test name
Test status
Simulation time 4367750461 ps
CPU time 42.61 seconds
Started Jun 02 12:42:05 PM PDT 24
Finished Jun 02 12:42:48 PM PDT 24
Peak memory 211984 kb
Host smart-090d1a9c-4890-4a95-bf9f-a24f66859c88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744581026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2744581026
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2306910722
Short name T188
Test name
Test status
Simulation time 8005301524 ps
CPU time 15.45 seconds
Started Jun 02 12:42:04 PM PDT 24
Finished Jun 02 12:42:20 PM PDT 24
Peak memory 211148 kb
Host smart-bc27de62-cd86-49cb-8c51-278b48c544ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306910722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2306910722
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2365590884
Short name T306
Test name
Test status
Simulation time 118933177602 ps
CPU time 292.78 seconds
Started Jun 02 12:42:16 PM PDT 24
Finished Jun 02 12:47:09 PM PDT 24
Peak memory 224812 kb
Host smart-2d52508f-c1b5-412a-aea4-aa89ca5cd7b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365590884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2365590884
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1936928619
Short name T252
Test name
Test status
Simulation time 8682486199 ps
CPU time 34.68 seconds
Started Jun 02 12:42:15 PM PDT 24
Finished Jun 02 12:42:50 PM PDT 24
Peak memory 212640 kb
Host smart-53de6901-45b5-4b1d-8936-f3ac93136c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936928619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1936928619
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3761141466
Short name T4
Test name
Test status
Simulation time 1622173097 ps
CPU time 14.55 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:28 PM PDT 24
Peak memory 211012 kb
Host smart-928cf5b2-90d3-480c-82ad-0aa04af6157d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761141466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3761141466
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.744147282
Short name T339
Test name
Test status
Simulation time 2372282008 ps
CPU time 18.07 seconds
Started Jun 02 12:42:22 PM PDT 24
Finished Jun 02 12:42:40 PM PDT 24
Peak memory 219188 kb
Host smart-9c35684c-ee13-4bf7-b3af-cd9ebd2874ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744147282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.744147282
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2882072456
Short name T305
Test name
Test status
Simulation time 10076807134 ps
CPU time 29.27 seconds
Started Jun 02 12:42:14 PM PDT 24
Finished Jun 02 12:42:44 PM PDT 24
Peak memory 213736 kb
Host smart-687ad033-de96-4a64-9e47-78cfa085f0e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882072456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2882072456
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1699010260
Short name T73
Test name
Test status
Simulation time 5166716646 ps
CPU time 14.92 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:28 PM PDT 24
Peak memory 211144 kb
Host smart-623bbd20-6a31-4e4b-ba2c-974d77530a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699010260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1699010260
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2896095156
Short name T186
Test name
Test status
Simulation time 9105610545 ps
CPU time 150.27 seconds
Started Jun 02 12:42:10 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 230788 kb
Host smart-1be9cadc-ed03-4f84-b2dd-abf1e5d868e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896095156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2896095156
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2718829621
Short name T338
Test name
Test status
Simulation time 3888479456 ps
CPU time 32.15 seconds
Started Jun 02 12:42:10 PM PDT 24
Finished Jun 02 12:42:43 PM PDT 24
Peak memory 211716 kb
Host smart-4c23ea50-f461-4bc8-88cd-93d82c8ed13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718829621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2718829621
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2054326038
Short name T310
Test name
Test status
Simulation time 2450153157 ps
CPU time 12.48 seconds
Started Jun 02 12:42:08 PM PDT 24
Finished Jun 02 12:42:21 PM PDT 24
Peak memory 211024 kb
Host smart-76267c51-50d3-4641-a7c0-b58c0fcf0d46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054326038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2054326038
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2397026208
Short name T43
Test name
Test status
Simulation time 866837074 ps
CPU time 13.83 seconds
Started Jun 02 12:42:07 PM PDT 24
Finished Jun 02 12:42:21 PM PDT 24
Peak memory 212780 kb
Host smart-663f9dae-3fa9-47e5-865c-92084065d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397026208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2397026208
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2002451787
Short name T279
Test name
Test status
Simulation time 21792901784 ps
CPU time 22.92 seconds
Started Jun 02 12:42:00 PM PDT 24
Finished Jun 02 12:42:23 PM PDT 24
Peak memory 211340 kb
Host smart-c3823f21-bfc2-4fba-9ded-43aaf7bb376e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002451787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2002451787
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1628420414
Short name T356
Test name
Test status
Simulation time 86395325 ps
CPU time 4.48 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:31 PM PDT 24
Peak memory 211136 kb
Host smart-72fcb65c-3c0a-44d6-8c91-9d3e9904578c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628420414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1628420414
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3668384183
Short name T296
Test name
Test status
Simulation time 56091145681 ps
CPU time 137.2 seconds
Started Jun 02 12:42:14 PM PDT 24
Finished Jun 02 12:44:32 PM PDT 24
Peak memory 237356 kb
Host smart-6145fdff-1a6c-4641-920f-c04f63c20420
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668384183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3668384183
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4220730854
Short name T150
Test name
Test status
Simulation time 3835820552 ps
CPU time 33.61 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:47 PM PDT 24
Peak memory 211836 kb
Host smart-af019ce9-1fb3-458a-add2-672c35c11ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220730854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4220730854
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3926260559
Short name T270
Test name
Test status
Simulation time 3280533691 ps
CPU time 9.46 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:42:39 PM PDT 24
Peak memory 210996 kb
Host smart-f78c5206-64b1-481c-9b52-2516e70785bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926260559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3926260559
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.182150158
Short name T232
Test name
Test status
Simulation time 181381561 ps
CPU time 10.6 seconds
Started Jun 02 12:42:12 PM PDT 24
Finished Jun 02 12:42:23 PM PDT 24
Peak memory 213456 kb
Host smart-0627246c-a9ba-4457-bc82-d9582c3e5095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182150158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.182150158
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1893193214
Short name T362
Test name
Test status
Simulation time 1054433388 ps
CPU time 27.78 seconds
Started Jun 02 12:42:27 PM PDT 24
Finished Jun 02 12:42:55 PM PDT 24
Peak memory 214588 kb
Host smart-b6055c9a-f086-4eed-846a-e8d627f523a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893193214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1893193214
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.723223999
Short name T324
Test name
Test status
Simulation time 45578945427 ps
CPU time 153.35 seconds
Started Jun 02 12:42:14 PM PDT 24
Finished Jun 02 12:44:48 PM PDT 24
Peak memory 230408 kb
Host smart-84535656-f38d-461d-8d50-b0dbc9b74958
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723223999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.723223999
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2677149574
Short name T166
Test name
Test status
Simulation time 2868001030 ps
CPU time 26.95 seconds
Started Jun 02 12:42:12 PM PDT 24
Finished Jun 02 12:42:39 PM PDT 24
Peak memory 211928 kb
Host smart-83d75773-d088-4f6a-8e77-134f32caa32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677149574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2677149574
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.594358467
Short name T184
Test name
Test status
Simulation time 13273027040 ps
CPU time 17.12 seconds
Started Jun 02 12:42:17 PM PDT 24
Finished Jun 02 12:42:35 PM PDT 24
Peak memory 211156 kb
Host smart-d1205689-404c-45e0-ac49-2180ed1df9d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=594358467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.594358467
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4193922959
Short name T91
Test name
Test status
Simulation time 2489512347 ps
CPU time 14.69 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:28 PM PDT 24
Peak memory 211700 kb
Host smart-b91bcb07-34f5-4089-a4e5-2442a2018ca3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193922959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4193922959
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.120309087
Short name T363
Test name
Test status
Simulation time 172018300 ps
CPU time 4.23 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:18 PM PDT 24
Peak memory 211036 kb
Host smart-6790081d-d412-4297-bac8-06d81e15542e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120309087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.120309087
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1221034842
Short name T14
Test name
Test status
Simulation time 30373303821 ps
CPU time 253.94 seconds
Started Jun 02 12:42:18 PM PDT 24
Finished Jun 02 12:46:32 PM PDT 24
Peak memory 224916 kb
Host smart-b7aaaa00-4e96-47c5-a410-a7a9cc9454d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221034842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1221034842
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1434429089
Short name T20
Test name
Test status
Simulation time 665977963 ps
CPU time 9.32 seconds
Started Jun 02 12:42:15 PM PDT 24
Finished Jun 02 12:42:25 PM PDT 24
Peak memory 211788 kb
Host smart-600472eb-41bd-45f8-a440-61a5b8cd491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434429089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1434429089
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.684091887
Short name T278
Test name
Test status
Simulation time 2237933114 ps
CPU time 9.15 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:23 PM PDT 24
Peak memory 211072 kb
Host smart-0151d0d0-cb4b-4e72-8bab-50c795d98f87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684091887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.684091887
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1832616528
Short name T236
Test name
Test status
Simulation time 16741007646 ps
CPU time 31.93 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:46 PM PDT 24
Peak memory 214316 kb
Host smart-abc4b7fd-90c6-4049-afd7-e9f3612b29e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832616528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1832616528
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3184712269
Short name T355
Test name
Test status
Simulation time 2161228786 ps
CPU time 20.73 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:35 PM PDT 24
Peak memory 210992 kb
Host smart-a39f0d9d-7f75-40dc-b781-35179535c555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184712269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3184712269
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1839148115
Short name T158
Test name
Test status
Simulation time 1617870968 ps
CPU time 9.7 seconds
Started Jun 02 12:42:14 PM PDT 24
Finished Jun 02 12:42:24 PM PDT 24
Peak memory 211012 kb
Host smart-74717b6f-0768-43e4-be5b-4af523bb950f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839148115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1839148115
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.780609142
Short name T132
Test name
Test status
Simulation time 7080047347 ps
CPU time 97.39 seconds
Started Jun 02 12:42:19 PM PDT 24
Finished Jun 02 12:43:57 PM PDT 24
Peak memory 212516 kb
Host smart-d8b8d8dd-f7ef-4cf4-bbd1-4e9e89628e04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780609142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.780609142
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3882327306
Short name T40
Test name
Test status
Simulation time 17856613678 ps
CPU time 35.72 seconds
Started Jun 02 12:42:28 PM PDT 24
Finished Jun 02 12:43:05 PM PDT 24
Peak memory 212560 kb
Host smart-cac41a4a-ed09-4a9c-886c-5e2ffadcb783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882327306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3882327306
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.971430250
Short name T178
Test name
Test status
Simulation time 4461225876 ps
CPU time 11.63 seconds
Started Jun 02 12:42:17 PM PDT 24
Finished Jun 02 12:42:30 PM PDT 24
Peak memory 211092 kb
Host smart-b0aa5517-a822-41cf-b01e-de615e65bd58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971430250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.971430250
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3902096847
Short name T321
Test name
Test status
Simulation time 1850806738 ps
CPU time 21.8 seconds
Started Jun 02 12:42:20 PM PDT 24
Finished Jun 02 12:42:43 PM PDT 24
Peak memory 213280 kb
Host smart-0c789f2f-8840-4105-8af4-667e52153a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902096847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3902096847
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.296622160
Short name T146
Test name
Test status
Simulation time 36542904426 ps
CPU time 54.2 seconds
Started Jun 02 12:42:24 PM PDT 24
Finished Jun 02 12:43:19 PM PDT 24
Peak memory 217132 kb
Host smart-8a610d1f-7ad5-4469-b865-188169826350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296622160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.296622160
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3585875437
Short name T213
Test name
Test status
Simulation time 2975710869 ps
CPU time 13.27 seconds
Started Jun 02 12:42:22 PM PDT 24
Finished Jun 02 12:42:36 PM PDT 24
Peak memory 210996 kb
Host smart-6c90de71-689a-4548-bb66-3c3d86817327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585875437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3585875437
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3693366098
Short name T241
Test name
Test status
Simulation time 14716073410 ps
CPU time 200.47 seconds
Started Jun 02 12:42:18 PM PDT 24
Finished Jun 02 12:45:39 PM PDT 24
Peak memory 234432 kb
Host smart-9224a415-8e06-40ec-b115-44c6ef2a2629
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693366098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3693366098
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1702858635
Short name T304
Test name
Test status
Simulation time 4493043684 ps
CPU time 35.1 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:49 PM PDT 24
Peak memory 212108 kb
Host smart-88a98d03-d71d-4cf6-a114-a498d15a0fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702858635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1702858635
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.326981763
Short name T258
Test name
Test status
Simulation time 1907113690 ps
CPU time 16.23 seconds
Started Jun 02 12:42:23 PM PDT 24
Finished Jun 02 12:42:39 PM PDT 24
Peak memory 211052 kb
Host smart-06b8ed55-ead3-4eac-8551-87b243040262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326981763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.326981763
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3405405631
Short name T299
Test name
Test status
Simulation time 10154318160 ps
CPU time 18.39 seconds
Started Jun 02 12:42:15 PM PDT 24
Finished Jun 02 12:42:34 PM PDT 24
Peak memory 213600 kb
Host smart-515aac9b-2cbe-449b-9e70-60c3b0583b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405405631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3405405631
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3266325339
Short name T315
Test name
Test status
Simulation time 4254264644 ps
CPU time 48.35 seconds
Started Jun 02 12:42:20 PM PDT 24
Finished Jun 02 12:43:09 PM PDT 24
Peak memory 219148 kb
Host smart-ca6f7d4b-649c-40ce-97e4-3d9862e712d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266325339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3266325339
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2408906820
Short name T52
Test name
Test status
Simulation time 62719633504 ps
CPU time 10120.8 seconds
Started Jun 02 12:42:22 PM PDT 24
Finished Jun 02 03:31:04 PM PDT 24
Peak memory 235824 kb
Host smart-7cf95af8-7c0a-4fb0-b797-c456db31707f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408906820 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2408906820
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3244797755
Short name T256
Test name
Test status
Simulation time 168610757 ps
CPU time 4.29 seconds
Started Jun 02 12:42:15 PM PDT 24
Finished Jun 02 12:42:20 PM PDT 24
Peak memory 211048 kb
Host smart-a3ed03d6-4740-487c-8988-87efe7e6c04c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244797755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3244797755
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3517845528
Short name T195
Test name
Test status
Simulation time 17387211981 ps
CPU time 138.6 seconds
Started Jun 02 12:42:16 PM PDT 24
Finished Jun 02 12:44:35 PM PDT 24
Peak memory 228320 kb
Host smart-c647f035-80b6-4107-bdb7-4dfaad42ca89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517845528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3517845528
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2780271790
Short name T142
Test name
Test status
Simulation time 4817847025 ps
CPU time 17.43 seconds
Started Jun 02 12:42:16 PM PDT 24
Finished Jun 02 12:42:34 PM PDT 24
Peak memory 212088 kb
Host smart-d36cbd7d-f242-4505-a250-0bcd85cc7b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780271790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2780271790
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3712034926
Short name T18
Test name
Test status
Simulation time 4135091682 ps
CPU time 12.03 seconds
Started Jun 02 12:42:14 PM PDT 24
Finished Jun 02 12:42:26 PM PDT 24
Peak memory 211008 kb
Host smart-17850bbd-54d2-4681-aa3e-b9e06561f3de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712034926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3712034926
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2832437510
Short name T86
Test name
Test status
Simulation time 356907591 ps
CPU time 12.64 seconds
Started Jun 02 12:42:19 PM PDT 24
Finished Jun 02 12:42:33 PM PDT 24
Peak memory 219164 kb
Host smart-860db62a-1178-417a-add2-96f35415319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832437510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2832437510
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2437673478
Short name T272
Test name
Test status
Simulation time 13035261568 ps
CPU time 39.25 seconds
Started Jun 02 12:42:19 PM PDT 24
Finished Jun 02 12:42:59 PM PDT 24
Peak memory 216592 kb
Host smart-f4506238-5ed8-4c5c-a873-e9f37e8e2386
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437673478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2437673478
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2551631935
Short name T190
Test name
Test status
Simulation time 2112505623 ps
CPU time 16.63 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:43 PM PDT 24
Peak memory 211056 kb
Host smart-5db009e2-3883-4fbb-a3f0-36ea9090e2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551631935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2551631935
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.848138893
Short name T224
Test name
Test status
Simulation time 8454017045 ps
CPU time 138.31 seconds
Started Jun 02 12:42:22 PM PDT 24
Finished Jun 02 12:44:41 PM PDT 24
Peak memory 234980 kb
Host smart-cc18bdab-c075-4df5-81c2-4289cabeb516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848138893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.848138893
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1889992153
Short name T273
Test name
Test status
Simulation time 84816939069 ps
CPU time 35.32 seconds
Started Jun 02 12:42:17 PM PDT 24
Finished Jun 02 12:42:53 PM PDT 24
Peak memory 212440 kb
Host smart-a86a1ad8-8e14-49b8-8992-30dd5571d7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889992153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1889992153
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1959331387
Short name T216
Test name
Test status
Simulation time 8186798029 ps
CPU time 16.08 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:42:46 PM PDT 24
Peak memory 211056 kb
Host smart-9beb09f4-1d86-461b-9764-d93ddf39fb34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1959331387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1959331387
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3152158891
Short name T240
Test name
Test status
Simulation time 375930888 ps
CPU time 10.36 seconds
Started Jun 02 12:42:16 PM PDT 24
Finished Jun 02 12:42:27 PM PDT 24
Peak memory 213516 kb
Host smart-d1794a19-e7f5-4fe1-9e5a-480b345de257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152158891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3152158891
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3168514322
Short name T137
Test name
Test status
Simulation time 1860661588 ps
CPU time 25.07 seconds
Started Jun 02 12:42:24 PM PDT 24
Finished Jun 02 12:42:49 PM PDT 24
Peak memory 216220 kb
Host smart-396fef63-d5c0-4bb9-a90a-4e0295474769
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168514322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3168514322
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2563705452
Short name T352
Test name
Test status
Simulation time 58101228496 ps
CPU time 2333.21 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 01:21:23 PM PDT 24
Peak memory 244004 kb
Host smart-95300ccb-26f2-4ff0-838c-bca2d30bbb1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563705452 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2563705452
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2304653948
Short name T8
Test name
Test status
Simulation time 333947390 ps
CPU time 4.23 seconds
Started Jun 02 12:42:19 PM PDT 24
Finished Jun 02 12:42:24 PM PDT 24
Peak memory 210964 kb
Host smart-b19ac724-b922-4c10-abc4-415797e068dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304653948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2304653948
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3609854405
Short name T17
Test name
Test status
Simulation time 49176827523 ps
CPU time 351.97 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 12:48:24 PM PDT 24
Peak memory 235056 kb
Host smart-3b26a33c-41eb-4f57-b57c-1765b98b6c92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609854405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3609854405
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4197040943
Short name T337
Test name
Test status
Simulation time 611537515 ps
CPU time 9.03 seconds
Started Jun 02 12:42:27 PM PDT 24
Finished Jun 02 12:42:37 PM PDT 24
Peak memory 211028 kb
Host smart-ddaf514e-ef38-48cd-aa0c-34d0cad97c98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197040943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4197040943
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1030481255
Short name T185
Test name
Test status
Simulation time 12014377500 ps
CPU time 27.29 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:42:57 PM PDT 24
Peak memory 213716 kb
Host smart-a2f28658-833c-403a-8a91-f35b69f2a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030481255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1030481255
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4077652095
Short name T237
Test name
Test status
Simulation time 51144588418 ps
CPU time 107.37 seconds
Started Jun 02 12:42:24 PM PDT 24
Finished Jun 02 12:44:12 PM PDT 24
Peak memory 219344 kb
Host smart-10098bf4-600f-472c-8071-653a72d9e96f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077652095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4077652095
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1322271320
Short name T54
Test name
Test status
Simulation time 89355644146 ps
CPU time 5260.06 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 02:10:13 PM PDT 24
Peak memory 233316 kb
Host smart-52fc23b3-5d02-499e-be82-1f05c5a4866f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322271320 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1322271320
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3711554245
Short name T187
Test name
Test status
Simulation time 827125523 ps
CPU time 4.35 seconds
Started Jun 02 12:41:55 PM PDT 24
Finished Jun 02 12:41:59 PM PDT 24
Peak memory 211424 kb
Host smart-7487b99a-a97e-4ac7-a0a2-b566d546cccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711554245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3711554245
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.877204667
Short name T300
Test name
Test status
Simulation time 2083479674 ps
CPU time 125.89 seconds
Started Jun 02 12:41:53 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 236468 kb
Host smart-0a922e03-5860-4e1d-9cd5-83db73343a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877204667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.877204667
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1046297293
Short name T250
Test name
Test status
Simulation time 13355384091 ps
CPU time 16.74 seconds
Started Jun 02 12:41:59 PM PDT 24
Finished Jun 02 12:42:16 PM PDT 24
Peak memory 212184 kb
Host smart-044e0ea9-2f9f-4813-a403-4f00902b2050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046297293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1046297293
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2612587509
Short name T133
Test name
Test status
Simulation time 194512850 ps
CPU time 5.85 seconds
Started Jun 02 12:41:52 PM PDT 24
Finished Jun 02 12:41:59 PM PDT 24
Peak memory 210988 kb
Host smart-3e80f084-e6d1-4ec2-a812-34419dfa4f4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612587509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2612587509
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.267997614
Short name T364
Test name
Test status
Simulation time 4055325055 ps
CPU time 34.17 seconds
Started Jun 02 12:42:04 PM PDT 24
Finished Jun 02 12:42:39 PM PDT 24
Peak memory 219240 kb
Host smart-429569ed-8e76-4090-ab64-64014e90c54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267997614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.267997614
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.555958442
Short name T251
Test name
Test status
Simulation time 3576766234 ps
CPU time 40.32 seconds
Started Jun 02 12:41:44 PM PDT 24
Finished Jun 02 12:42:25 PM PDT 24
Peak memory 213272 kb
Host smart-2e9d4af7-d927-406a-8737-414c084e3a87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555958442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.555958442
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1749986908
Short name T145
Test name
Test status
Simulation time 89032835 ps
CPU time 4.24 seconds
Started Jun 02 12:42:13 PM PDT 24
Finished Jun 02 12:42:18 PM PDT 24
Peak memory 210992 kb
Host smart-bcfa4af9-0498-4441-8d6e-0d83a74ee9f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749986908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1749986908
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4145520022
Short name T29
Test name
Test status
Simulation time 20250288104 ps
CPU time 255.1 seconds
Started Jun 02 12:42:30 PM PDT 24
Finished Jun 02 12:46:46 PM PDT 24
Peak memory 229900 kb
Host smart-4d85a508-ec18-4541-8a86-847ad8400ed5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145520022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4145520022
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3960700015
Short name T261
Test name
Test status
Simulation time 173616310 ps
CPU time 9.63 seconds
Started Jun 02 12:42:28 PM PDT 24
Finished Jun 02 12:42:38 PM PDT 24
Peak memory 212228 kb
Host smart-cac09f10-b9af-4cc6-b466-75fa6b05f127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960700015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3960700015
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2411458067
Short name T308
Test name
Test status
Simulation time 1392905979 ps
CPU time 12.98 seconds
Started Jun 02 12:42:31 PM PDT 24
Finished Jun 02 12:42:44 PM PDT 24
Peak memory 211112 kb
Host smart-cfa4180f-e172-4711-96f4-d3ad98ff4c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411458067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2411458067
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1226692974
Short name T257
Test name
Test status
Simulation time 356091808 ps
CPU time 13.09 seconds
Started Jun 02 12:42:15 PM PDT 24
Finished Jun 02 12:42:28 PM PDT 24
Peak memory 213000 kb
Host smart-4193e306-4bc4-44c0-b9b4-fc82df327b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226692974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1226692974
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2482396703
Short name T348
Test name
Test status
Simulation time 396158599 ps
CPU time 21.99 seconds
Started Jun 02 12:42:30 PM PDT 24
Finished Jun 02 12:42:53 PM PDT 24
Peak memory 219164 kb
Host smart-44d6747b-4add-445a-a774-41de1f9eb563
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482396703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2482396703
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2646191699
Short name T370
Test name
Test status
Simulation time 779565759 ps
CPU time 8.82 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:36 PM PDT 24
Peak memory 211048 kb
Host smart-5f49430a-7cbd-4b82-ab01-438b757a7bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646191699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2646191699
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1205924773
Short name T180
Test name
Test status
Simulation time 338971291912 ps
CPU time 239.68 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:46:30 PM PDT 24
Peak memory 228276 kb
Host smart-ca263666-9a90-4594-b86d-1fcd6b4c52a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205924773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1205924773
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2614302019
Short name T172
Test name
Test status
Simulation time 2378331851 ps
CPU time 24.8 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:51 PM PDT 24
Peak memory 211692 kb
Host smart-2061c091-6f3e-4389-8196-0ded77d70e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614302019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2614302019
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2592307677
Short name T202
Test name
Test status
Simulation time 821355184 ps
CPU time 10.61 seconds
Started Jun 02 12:42:19 PM PDT 24
Finished Jun 02 12:42:30 PM PDT 24
Peak memory 211040 kb
Host smart-dbc40a59-ea10-40ee-8ff7-7e4ede267115
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2592307677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2592307677
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1575103601
Short name T311
Test name
Test status
Simulation time 9605478755 ps
CPU time 25.11 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:42:55 PM PDT 24
Peak memory 214232 kb
Host smart-19ea4706-a041-4faa-b463-01bd962e679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575103601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1575103601
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1730167917
Short name T303
Test name
Test status
Simulation time 788195200 ps
CPU time 10.93 seconds
Started Jun 02 12:42:20 PM PDT 24
Finished Jun 02 12:42:31 PM PDT 24
Peak memory 210932 kb
Host smart-847de383-8360-4971-a807-dd4c5195ea06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730167917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1730167917
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3732243926
Short name T329
Test name
Test status
Simulation time 292642830 ps
CPU time 6.12 seconds
Started Jun 02 12:42:20 PM PDT 24
Finished Jun 02 12:42:27 PM PDT 24
Peak memory 211052 kb
Host smart-671ea9c7-3c93-4ce3-9340-ce032562bb85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732243926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3732243926
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3126999552
Short name T357
Test name
Test status
Simulation time 162934877567 ps
CPU time 224.05 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 12:46:17 PM PDT 24
Peak memory 237700 kb
Host smart-9f61bfd1-dfa1-43e9-84e6-1b97f806a90f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126999552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3126999552
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4181841657
Short name T229
Test name
Test status
Simulation time 3495628362 ps
CPU time 29.66 seconds
Started Jun 02 12:42:28 PM PDT 24
Finished Jun 02 12:42:58 PM PDT 24
Peak memory 211288 kb
Host smart-ecd151d2-9cd1-4da8-8639-5142901ea408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181841657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4181841657
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2048978989
Short name T139
Test name
Test status
Simulation time 7612594517 ps
CPU time 16.84 seconds
Started Jun 02 12:42:25 PM PDT 24
Finished Jun 02 12:42:42 PM PDT 24
Peak memory 211168 kb
Host smart-3c79bb34-4ee0-4805-a934-7f3ffb8bdb0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048978989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2048978989
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3118671878
Short name T28
Test name
Test status
Simulation time 11216212568 ps
CPU time 34.11 seconds
Started Jun 02 12:42:25 PM PDT 24
Finished Jun 02 12:43:00 PM PDT 24
Peak memory 219340 kb
Host smart-137a5628-3bfc-4c83-a41e-88654b3bd659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118671878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3118671878
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2989394181
Short name T230
Test name
Test status
Simulation time 3646820733 ps
CPU time 15.18 seconds
Started Jun 02 12:42:23 PM PDT 24
Finished Jun 02 12:42:39 PM PDT 24
Peak memory 213864 kb
Host smart-527ef8f3-8339-452c-9287-104c158c05fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989394181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2989394181
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.676956760
Short name T317
Test name
Test status
Simulation time 347279679 ps
CPU time 4.25 seconds
Started Jun 02 12:42:15 PM PDT 24
Finished Jun 02 12:42:19 PM PDT 24
Peak memory 211152 kb
Host smart-e9f6091b-66d0-4966-a612-5d8107e9ea2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676956760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.676956760
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4021605667
Short name T152
Test name
Test status
Simulation time 1227540458 ps
CPU time 95.7 seconds
Started Jun 02 12:42:23 PM PDT 24
Finished Jun 02 12:43:59 PM PDT 24
Peak memory 237672 kb
Host smart-10c9629b-5012-4634-bab7-1bc7bab76096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021605667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4021605667
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3991098707
Short name T260
Test name
Test status
Simulation time 170165751 ps
CPU time 9.44 seconds
Started Jun 02 12:42:19 PM PDT 24
Finished Jun 02 12:42:29 PM PDT 24
Peak memory 211812 kb
Host smart-0a0bb1d8-b002-4a3b-af03-73236aee9b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991098707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3991098707
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.937734475
Short name T21
Test name
Test status
Simulation time 448435223 ps
CPU time 6.33 seconds
Started Jun 02 12:42:24 PM PDT 24
Finished Jun 02 12:42:31 PM PDT 24
Peak memory 210972 kb
Host smart-6fc4d577-3dc6-4b1e-aefc-ce5c445b7529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937734475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.937734475
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2903310921
Short name T322
Test name
Test status
Simulation time 2369444037 ps
CPU time 19.53 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 12:42:52 PM PDT 24
Peak memory 213324 kb
Host smart-e41909c3-573b-4708-9f4b-a4ca990426fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903310921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2903310921
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.905422980
Short name T353
Test name
Test status
Simulation time 9461599331 ps
CPU time 38.01 seconds
Started Jun 02 12:42:24 PM PDT 24
Finished Jun 02 12:43:03 PM PDT 24
Peak memory 216760 kb
Host smart-28832f4f-7226-4bf2-b5b2-a4a28be1f001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905422980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.905422980
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2288920000
Short name T62
Test name
Test status
Simulation time 261358135 ps
CPU time 4.99 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:32 PM PDT 24
Peak memory 211084 kb
Host smart-67892de7-8b28-41ba-b8a4-dab3191243c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288920000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2288920000
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2651127871
Short name T48
Test name
Test status
Simulation time 245859136702 ps
CPU time 352.83 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:48:20 PM PDT 24
Peak memory 237888 kb
Host smart-6df607d3-b01a-4c65-8b66-72d23bb9f96d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651127871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2651127871
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3947921754
Short name T155
Test name
Test status
Simulation time 8187015530 ps
CPU time 34.34 seconds
Started Jun 02 12:42:22 PM PDT 24
Finished Jun 02 12:42:56 PM PDT 24
Peak memory 212600 kb
Host smart-0dc6f696-012a-4034-808d-a63ebdba1267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947921754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3947921754
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.370754842
Short name T346
Test name
Test status
Simulation time 2365365853 ps
CPU time 14.09 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:41 PM PDT 24
Peak memory 211176 kb
Host smart-c61e24f5-474c-45bc-87b0-6a5840be4e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370754842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.370754842
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2423332852
Short name T359
Test name
Test status
Simulation time 707822892 ps
CPU time 10.14 seconds
Started Jun 02 12:42:15 PM PDT 24
Finished Jun 02 12:42:26 PM PDT 24
Peak memory 213052 kb
Host smart-33193397-c53b-41b9-a5fd-7d6ff3ee78b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423332852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2423332852
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2954701625
Short name T271
Test name
Test status
Simulation time 2556363881 ps
CPU time 15.82 seconds
Started Jun 02 12:42:18 PM PDT 24
Finished Jun 02 12:42:35 PM PDT 24
Peak memory 211312 kb
Host smart-c5647f0c-bb8e-4c3b-8476-c70faee81c34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954701625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2954701625
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4009591299
Short name T157
Test name
Test status
Simulation time 4107352248 ps
CPU time 10.42 seconds
Started Jun 02 12:42:24 PM PDT 24
Finished Jun 02 12:42:35 PM PDT 24
Peak memory 211084 kb
Host smart-11af409a-dfcd-4858-b941-b44dcf012d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009591299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4009591299
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2614266362
Short name T175
Test name
Test status
Simulation time 55290082213 ps
CPU time 143.19 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:44:50 PM PDT 24
Peak memory 227576 kb
Host smart-f35248ec-afc6-4033-8686-9babdd147a50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614266362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2614266362
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2499003387
Short name T335
Test name
Test status
Simulation time 251533666 ps
CPU time 11.18 seconds
Started Jun 02 12:42:25 PM PDT 24
Finished Jun 02 12:42:37 PM PDT 24
Peak memory 211660 kb
Host smart-e39a9b18-7a48-4a77-944f-72b3dd229f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499003387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2499003387
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.151613080
Short name T116
Test name
Test status
Simulation time 5349681845 ps
CPU time 13.12 seconds
Started Jun 02 12:42:20 PM PDT 24
Finished Jun 02 12:42:34 PM PDT 24
Peak memory 211172 kb
Host smart-90fb38c2-eddd-4e2d-b983-f9b22859929f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151613080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.151613080
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1229274313
Short name T147
Test name
Test status
Simulation time 8941152293 ps
CPU time 26.2 seconds
Started Jun 02 12:42:41 PM PDT 24
Finished Jun 02 12:43:09 PM PDT 24
Peak memory 219328 kb
Host smart-f88eb189-5a93-4dfe-89cf-9b78096fc31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229274313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1229274313
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4105352576
Short name T277
Test name
Test status
Simulation time 2398635281 ps
CPU time 16.87 seconds
Started Jun 02 12:42:31 PM PDT 24
Finished Jun 02 12:42:48 PM PDT 24
Peak memory 210912 kb
Host smart-de25b24f-8dbc-4e3b-af30-cb0ca6cd141f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105352576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4105352576
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3512851010
Short name T41
Test name
Test status
Simulation time 86671398948 ps
CPU time 1681.43 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 01:10:35 PM PDT 24
Peak memory 236052 kb
Host smart-01d696c6-8476-45d2-b96c-2422b2af1e4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512851010 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3512851010
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2570440113
Short name T341
Test name
Test status
Simulation time 1593081090 ps
CPU time 13.32 seconds
Started Jun 02 12:42:34 PM PDT 24
Finished Jun 02 12:42:48 PM PDT 24
Peak memory 211276 kb
Host smart-d752fbfa-f736-4447-acc2-3c0049cc44ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570440113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2570440113
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2198675377
Short name T59
Test name
Test status
Simulation time 118007733406 ps
CPU time 157.72 seconds
Started Jun 02 12:42:42 PM PDT 24
Finished Jun 02 12:45:20 PM PDT 24
Peak memory 212436 kb
Host smart-f38be14f-47c4-4a8f-9973-b1b5212b57eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198675377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2198675377
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3149428356
Short name T165
Test name
Test status
Simulation time 3838043374 ps
CPU time 31.44 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 12:43:04 PM PDT 24
Peak memory 211908 kb
Host smart-b9b70709-9b6c-4627-9323-390d9b5e4181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149428356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3149428356
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3613236697
Short name T269
Test name
Test status
Simulation time 95461114 ps
CPU time 5.44 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 12:42:38 PM PDT 24
Peak memory 210984 kb
Host smart-40e0bbf7-6156-404b-9be8-fa753de938e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613236697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3613236697
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3005343878
Short name T285
Test name
Test status
Simulation time 7118689892 ps
CPU time 12.74 seconds
Started Jun 02 12:42:25 PM PDT 24
Finished Jun 02 12:42:38 PM PDT 24
Peak memory 214244 kb
Host smart-e3f00cdb-9a89-407c-b8b1-9b004a80b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005343878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3005343878
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2525631665
Short name T264
Test name
Test status
Simulation time 867031355 ps
CPU time 11.1 seconds
Started Jun 02 12:42:34 PM PDT 24
Finished Jun 02 12:42:45 PM PDT 24
Peak memory 211116 kb
Host smart-24c3c9b4-1dea-469f-a949-289f667ac905
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525631665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2525631665
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1782114315
Short name T242
Test name
Test status
Simulation time 4907724274 ps
CPU time 11.94 seconds
Started Jun 02 12:42:21 PM PDT 24
Finished Jun 02 12:42:33 PM PDT 24
Peak memory 211084 kb
Host smart-d5601f10-2393-43aa-8e46-9375a9964be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782114315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1782114315
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2044464521
Short name T182
Test name
Test status
Simulation time 1460056312 ps
CPU time 82.53 seconds
Started Jun 02 12:42:21 PM PDT 24
Finished Jun 02 12:43:44 PM PDT 24
Peak memory 211940 kb
Host smart-123dd762-09fd-4ed5-a70b-754b9b8905fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044464521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2044464521
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2874112796
Short name T176
Test name
Test status
Simulation time 2945496031 ps
CPU time 26.54 seconds
Started Jun 02 12:42:25 PM PDT 24
Finished Jun 02 12:42:53 PM PDT 24
Peak memory 211908 kb
Host smart-5d9c4167-cd56-49b5-8bac-a3f59e996762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874112796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2874112796
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3544641096
Short name T204
Test name
Test status
Simulation time 383553656 ps
CPU time 5.76 seconds
Started Jun 02 12:42:41 PM PDT 24
Finished Jun 02 12:42:48 PM PDT 24
Peak memory 210936 kb
Host smart-6367c834-e5eb-4408-9f77-7cf2291179dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3544641096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3544641096
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1587372048
Short name T298
Test name
Test status
Simulation time 588307228 ps
CPU time 15.95 seconds
Started Jun 02 12:42:33 PM PDT 24
Finished Jun 02 12:42:50 PM PDT 24
Peak memory 212608 kb
Host smart-3d1e976e-01bc-4cf2-9078-4e527799b448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587372048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1587372048
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2846113718
Short name T89
Test name
Test status
Simulation time 4557409435 ps
CPU time 17.19 seconds
Started Jun 02 12:42:39 PM PDT 24
Finished Jun 02 12:42:57 PM PDT 24
Peak memory 212300 kb
Host smart-dae4f508-7aa6-4e86-9607-7d439a09603a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846113718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2846113718
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1213043202
Short name T35
Test name
Test status
Simulation time 380851076 ps
CPU time 6.84 seconds
Started Jun 02 12:42:33 PM PDT 24
Finished Jun 02 12:42:40 PM PDT 24
Peak memory 211276 kb
Host smart-dec0a18e-9f26-4e48-b936-0c37b7da0001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213043202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1213043202
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.155101434
Short name T365
Test name
Test status
Simulation time 21592604819 ps
CPU time 192.85 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:45:40 PM PDT 24
Peak memory 213420 kb
Host smart-e5391230-3da2-4a6f-9c1b-995290946a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155101434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.155101434
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3782968236
Short name T307
Test name
Test status
Simulation time 8001822517 ps
CPU time 32.78 seconds
Started Jun 02 12:42:27 PM PDT 24
Finished Jun 02 12:43:00 PM PDT 24
Peak memory 212644 kb
Host smart-2c320448-65f2-403a-9281-9a5e39f26fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782968236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3782968236
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1406874792
Short name T286
Test name
Test status
Simulation time 1323727362 ps
CPU time 13.02 seconds
Started Jun 02 12:42:20 PM PDT 24
Finished Jun 02 12:42:34 PM PDT 24
Peak memory 211092 kb
Host smart-ec84f618-f6db-406a-a5fa-0231fec60926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406874792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1406874792
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3625914259
Short name T57
Test name
Test status
Simulation time 3692224223 ps
CPU time 27.71 seconds
Started Jun 02 12:42:21 PM PDT 24
Finished Jun 02 12:42:49 PM PDT 24
Peak memory 213736 kb
Host smart-1a9f5ea9-3be1-4a2d-b13b-3cb79b2be9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625914259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3625914259
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3786064766
Short name T234
Test name
Test status
Simulation time 9436552626 ps
CPU time 30.78 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:57 PM PDT 24
Peak memory 214108 kb
Host smart-136c8a2b-35b6-4077-b000-cc567861114a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786064766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3786064766
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.20494122
Short name T25
Test name
Test status
Simulation time 56514485209 ps
CPU time 534.7 seconds
Started Jun 02 12:42:37 PM PDT 24
Finished Jun 02 12:51:32 PM PDT 24
Peak memory 232668 kb
Host smart-1d375709-d4e5-485c-b7b0-0af32a60c26a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20494122 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.20494122
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.611010513
Short name T168
Test name
Test status
Simulation time 2049126386 ps
CPU time 8.04 seconds
Started Jun 02 12:42:41 PM PDT 24
Finished Jun 02 12:42:50 PM PDT 24
Peak memory 210976 kb
Host smart-0c4328f3-fea6-4362-87ef-5b142288569c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611010513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.611010513
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3580086209
Short name T22
Test name
Test status
Simulation time 4067761450 ps
CPU time 101.97 seconds
Started Jun 02 12:42:21 PM PDT 24
Finished Jun 02 12:44:03 PM PDT 24
Peak memory 212376 kb
Host smart-24ecceea-7cae-4cac-b55a-15847510d172
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580086209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3580086209
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2030087736
Short name T164
Test name
Test status
Simulation time 5843765967 ps
CPU time 24.44 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:42:55 PM PDT 24
Peak memory 212448 kb
Host smart-4a91ee2b-d0e4-4a67-8b1a-cbc9af7ab9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030087736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2030087736
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3331458464
Short name T206
Test name
Test status
Simulation time 1884648353 ps
CPU time 16.87 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:43 PM PDT 24
Peak memory 210976 kb
Host smart-01176f86-1803-47b3-aec2-f418e680a4cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331458464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3331458464
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2780823868
Short name T255
Test name
Test status
Simulation time 729111322 ps
CPU time 10.42 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:42:41 PM PDT 24
Peak memory 213708 kb
Host smart-8ee87c41-79d6-4b02-bc74-577d00e382e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780823868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2780823868
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3658362262
Short name T325
Test name
Test status
Simulation time 8088127689 ps
CPU time 29.28 seconds
Started Jun 02 12:42:31 PM PDT 24
Finished Jun 02 12:43:01 PM PDT 24
Peak memory 213820 kb
Host smart-a86b1bf8-e477-4d2c-ae5a-6bf53abc54c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658362262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3658362262
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.195204977
Short name T200
Test name
Test status
Simulation time 6746163084 ps
CPU time 13.99 seconds
Started Jun 02 12:41:54 PM PDT 24
Finished Jun 02 12:42:09 PM PDT 24
Peak memory 211068 kb
Host smart-354b6d96-7234-44e0-8be7-e6b7535c1a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195204977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.195204977
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3650774064
Short name T143
Test name
Test status
Simulation time 10243775419 ps
CPU time 168.08 seconds
Started Jun 02 12:42:02 PM PDT 24
Finished Jun 02 12:44:51 PM PDT 24
Peak memory 237824 kb
Host smart-bf8b40b2-0f3a-4067-9de6-6fd785fca4ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650774064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3650774064
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1575712127
Short name T343
Test name
Test status
Simulation time 3505976624 ps
CPU time 29.61 seconds
Started Jun 02 12:42:04 PM PDT 24
Finished Jun 02 12:42:35 PM PDT 24
Peak memory 211880 kb
Host smart-e036f3df-e143-4de3-8218-6963e2b75523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575712127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1575712127
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3265122175
Short name T320
Test name
Test status
Simulation time 13170050657 ps
CPU time 16.23 seconds
Started Jun 02 12:41:54 PM PDT 24
Finished Jun 02 12:42:11 PM PDT 24
Peak memory 211052 kb
Host smart-282c0ed8-5408-43c1-b51c-62b314cd8873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265122175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3265122175
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3396776935
Short name T34
Test name
Test status
Simulation time 1643308035 ps
CPU time 62.47 seconds
Started Jun 02 12:41:54 PM PDT 24
Finished Jun 02 12:42:57 PM PDT 24
Peak memory 236116 kb
Host smart-27fd612e-1cbe-4bf2-a7fa-090777203b76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396776935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3396776935
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4095127107
Short name T151
Test name
Test status
Simulation time 1006548726 ps
CPU time 16.73 seconds
Started Jun 02 12:41:54 PM PDT 24
Finished Jun 02 12:42:11 PM PDT 24
Peak memory 219192 kb
Host smart-5f3cea74-3d5b-4123-9da3-9e79a6663013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095127107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4095127107
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2941707282
Short name T247
Test name
Test status
Simulation time 28509118849 ps
CPU time 37.33 seconds
Started Jun 02 12:42:05 PM PDT 24
Finished Jun 02 12:42:43 PM PDT 24
Peak memory 219268 kb
Host smart-8c25cedd-6202-4dd7-a58b-7da943fd5c04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941707282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2941707282
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2858020045
Short name T208
Test name
Test status
Simulation time 2508463580 ps
CPU time 11.96 seconds
Started Jun 02 12:42:47 PM PDT 24
Finished Jun 02 12:43:00 PM PDT 24
Peak memory 211336 kb
Host smart-28ec0aa4-749a-49bd-bd63-016488a65dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858020045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2858020045
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.169876962
Short name T243
Test name
Test status
Simulation time 156412586990 ps
CPU time 381.22 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:48:52 PM PDT 24
Peak memory 228632 kb
Host smart-32ed1439-dd45-4801-91ba-af37a6a21f2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169876962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.169876962
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.887319708
Short name T148
Test name
Test status
Simulation time 2491306961 ps
CPU time 11.23 seconds
Started Jun 02 12:42:28 PM PDT 24
Finished Jun 02 12:42:40 PM PDT 24
Peak memory 211988 kb
Host smart-c1c6f8fd-3dce-4d63-b151-7701bb574745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887319708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.887319708
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4059068784
Short name T192
Test name
Test status
Simulation time 99429724 ps
CPU time 5.72 seconds
Started Jun 02 12:42:24 PM PDT 24
Finished Jun 02 12:42:30 PM PDT 24
Peak memory 211020 kb
Host smart-ffb2b1eb-2b0e-4de1-9b70-76d0ef38f213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4059068784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4059068784
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.542275704
Short name T239
Test name
Test status
Simulation time 5401230658 ps
CPU time 36.46 seconds
Started Jun 02 12:42:23 PM PDT 24
Finished Jun 02 12:43:00 PM PDT 24
Peak memory 213500 kb
Host smart-2749cb3b-4d75-407d-9214-d8e6e3d76968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542275704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.542275704
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1749772836
Short name T284
Test name
Test status
Simulation time 983495865 ps
CPU time 16.76 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:42:43 PM PDT 24
Peak memory 219132 kb
Host smart-c634d4cd-4376-49e2-84d0-510e4c49968c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749772836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1749772836
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3421540342
Short name T51
Test name
Test status
Simulation time 89439785093 ps
CPU time 1625.07 seconds
Started Jun 02 12:42:41 PM PDT 24
Finished Jun 02 01:09:47 PM PDT 24
Peak memory 235752 kb
Host smart-77e6fe08-4b30-45dc-8dec-c57c875b168a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421540342 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3421540342
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.399619293
Short name T70
Test name
Test status
Simulation time 555726398 ps
CPU time 7.8 seconds
Started Jun 02 12:42:30 PM PDT 24
Finished Jun 02 12:42:38 PM PDT 24
Peak memory 211036 kb
Host smart-ad3cc3a9-c50d-4908-8061-c06213e85ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399619293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.399619293
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2398358402
Short name T49
Test name
Test status
Simulation time 9556646430 ps
CPU time 222.59 seconds
Started Jun 02 12:42:31 PM PDT 24
Finished Jun 02 12:46:14 PM PDT 24
Peak memory 238748 kb
Host smart-f4f0f31a-6914-4198-a662-de4149964617
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398358402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2398358402
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2809062741
Short name T225
Test name
Test status
Simulation time 64026798227 ps
CPU time 30.17 seconds
Started Jun 02 12:42:28 PM PDT 24
Finished Jun 02 12:42:59 PM PDT 24
Peak memory 212240 kb
Host smart-11291f03-f31e-4314-a8ce-d62d647ac66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809062741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2809062741
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1317314143
Short name T312
Test name
Test status
Simulation time 9334409394 ps
CPU time 9.36 seconds
Started Jun 02 12:42:36 PM PDT 24
Finished Jun 02 12:42:46 PM PDT 24
Peak memory 211116 kb
Host smart-7a6cd577-303f-4a6c-8dbb-47e155127824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317314143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1317314143
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1509890056
Short name T203
Test name
Test status
Simulation time 1306257136 ps
CPU time 11.26 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:42:41 PM PDT 24
Peak memory 213404 kb
Host smart-de8b0739-dfcf-489a-8848-9dac34a55991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509890056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1509890056
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1269379604
Short name T63
Test name
Test status
Simulation time 30719802373 ps
CPU time 33.99 seconds
Started Jun 02 12:42:31 PM PDT 24
Finished Jun 02 12:43:06 PM PDT 24
Peak memory 214400 kb
Host smart-6163c716-7ac2-4a8a-a188-daba23a06a0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269379604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1269379604
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2389943972
Short name T53
Test name
Test status
Simulation time 111117425710 ps
CPU time 4038.6 seconds
Started Jun 02 12:42:30 PM PDT 24
Finished Jun 02 01:49:50 PM PDT 24
Peak memory 245780 kb
Host smart-e318b66f-3f57-471c-81a2-f1f96d95c22d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389943972 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2389943972
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3444405156
Short name T297
Test name
Test status
Simulation time 773421502 ps
CPU time 5.95 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:42:36 PM PDT 24
Peak memory 211000 kb
Host smart-c8fe7287-3b9f-4046-a3e1-c4e2ae299a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444405156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3444405156
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3788492818
Short name T221
Test name
Test status
Simulation time 99717571540 ps
CPU time 234.52 seconds
Started Jun 02 12:42:39 PM PDT 24
Finished Jun 02 12:46:34 PM PDT 24
Peak memory 232708 kb
Host smart-490b2da5-fbd9-47eb-88b2-03783934473f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788492818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3788492818
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2806781470
Short name T149
Test name
Test status
Simulation time 8864838766 ps
CPU time 35.68 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:43:06 PM PDT 24
Peak memory 212160 kb
Host smart-bfff00bc-d845-474d-a6d9-8ed68c64d97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806781470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2806781470
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2776421516
Short name T174
Test name
Test status
Simulation time 370155973 ps
CPU time 5.68 seconds
Started Jun 02 12:42:28 PM PDT 24
Finished Jun 02 12:42:34 PM PDT 24
Peak memory 211404 kb
Host smart-b6f1bc7e-e7cd-4234-af87-324024807048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776421516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2776421516
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2063441681
Short name T87
Test name
Test status
Simulation time 3634126377 ps
CPU time 35.28 seconds
Started Jun 02 12:42:39 PM PDT 24
Finished Jun 02 12:43:15 PM PDT 24
Peak memory 213240 kb
Host smart-3095fbcd-8596-4f5b-b3b7-e638bcce99e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063441681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2063441681
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4036149378
Short name T173
Test name
Test status
Simulation time 8620421988 ps
CPU time 40.87 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 12:43:08 PM PDT 24
Peak memory 213832 kb
Host smart-8f01e21e-2227-4582-bd15-f70d8faa5334
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036149378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4036149378
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.315028701
Short name T344
Test name
Test status
Simulation time 89117221 ps
CPU time 4.36 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 12:42:37 PM PDT 24
Peak memory 211048 kb
Host smart-88522a10-9c08-4b7f-bdc5-4fc6e0fa3367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315028701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.315028701
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1378981605
Short name T265
Test name
Test status
Simulation time 72076085196 ps
CPU time 369.8 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 12:48:43 PM PDT 24
Peak memory 212504 kb
Host smart-23cf0fd5-f669-410e-bbeb-5e93d58d7a59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378981605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1378981605
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1908968800
Short name T212
Test name
Test status
Simulation time 14711523133 ps
CPU time 30.58 seconds
Started Jun 02 12:42:27 PM PDT 24
Finished Jun 02 12:42:59 PM PDT 24
Peak memory 212172 kb
Host smart-3c208e2a-6a10-49a9-a0c3-1174890123be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908968800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1908968800
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2568458484
Short name T193
Test name
Test status
Simulation time 376222267 ps
CPU time 5.71 seconds
Started Jun 02 12:42:43 PM PDT 24
Finished Jun 02 12:42:50 PM PDT 24
Peak memory 211240 kb
Host smart-a023e102-de7f-4b86-b9fc-7cf322e01d8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568458484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2568458484
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.763749100
Short name T371
Test name
Test status
Simulation time 6964147265 ps
CPU time 25.02 seconds
Started Jun 02 12:42:39 PM PDT 24
Finished Jun 02 12:43:05 PM PDT 24
Peak memory 214684 kb
Host smart-cb46641d-9069-4228-8506-15d315db0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763749100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.763749100
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3580271360
Short name T334
Test name
Test status
Simulation time 1546382780 ps
CPU time 24.26 seconds
Started Jun 02 12:42:30 PM PDT 24
Finished Jun 02 12:42:55 PM PDT 24
Peak memory 213772 kb
Host smart-86286757-f952-4043-9050-9a820909c3c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580271360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3580271360
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.159203292
Short name T331
Test name
Test status
Simulation time 293038474987 ps
CPU time 2051.68 seconds
Started Jun 02 12:42:26 PM PDT 24
Finished Jun 02 01:16:39 PM PDT 24
Peak memory 243992 kb
Host smart-0c741d2b-38fd-417d-86ef-0cb5f2f31960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159203292 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.159203292
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1162056649
Short name T45
Test name
Test status
Simulation time 1691082817 ps
CPU time 13.82 seconds
Started Jun 02 12:42:31 PM PDT 24
Finished Jun 02 12:42:45 PM PDT 24
Peak memory 211052 kb
Host smart-16d37288-1015-471d-a388-91c397718797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162056649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1162056649
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.722103105
Short name T358
Test name
Test status
Simulation time 15184202178 ps
CPU time 226.85 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:46:17 PM PDT 24
Peak memory 224944 kb
Host smart-f4946eef-bb45-4d42-bb58-f4b96d0ade94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722103105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.722103105
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3146594664
Short name T288
Test name
Test status
Simulation time 707745078 ps
CPU time 13.07 seconds
Started Jun 02 12:42:27 PM PDT 24
Finished Jun 02 12:42:41 PM PDT 24
Peak memory 211880 kb
Host smart-fe7fa2cf-608d-4142-b09f-ebf9140a3234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146594664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3146594664
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1164406125
Short name T90
Test name
Test status
Simulation time 3488797467 ps
CPU time 32.73 seconds
Started Jun 02 12:42:30 PM PDT 24
Finished Jun 02 12:43:04 PM PDT 24
Peak memory 219256 kb
Host smart-c3599484-a05c-44b7-bd14-2a2f2e608cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164406125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1164406125
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4030486364
Short name T361
Test name
Test status
Simulation time 5131757420 ps
CPU time 56.1 seconds
Started Jun 02 12:42:40 PM PDT 24
Finished Jun 02 12:43:37 PM PDT 24
Peak memory 219172 kb
Host smart-a023d746-49df-4668-bfdc-84c6e1ea3174
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030486364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4030486364
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.978519710
Short name T50
Test name
Test status
Simulation time 86308844766 ps
CPU time 777.27 seconds
Started Jun 02 12:42:29 PM PDT 24
Finished Jun 02 12:55:28 PM PDT 24
Peak memory 235788 kb
Host smart-921782ab-77b1-4fac-b503-26530f8f5687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978519710 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.978519710
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3052555783
Short name T228
Test name
Test status
Simulation time 1488408403 ps
CPU time 12.88 seconds
Started Jun 02 12:42:35 PM PDT 24
Finished Jun 02 12:42:48 PM PDT 24
Peak memory 210964 kb
Host smart-76a2caf7-7c2d-43d5-8e33-56d11876105b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052555783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3052555783
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.209577173
Short name T47
Test name
Test status
Simulation time 24768499976 ps
CPU time 313.3 seconds
Started Jun 02 12:42:27 PM PDT 24
Finished Jun 02 12:47:41 PM PDT 24
Peak memory 212404 kb
Host smart-07ee7696-3b4a-4b14-a932-48719fca1dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209577173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.209577173
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3649384992
Short name T181
Test name
Test status
Simulation time 19025365825 ps
CPU time 23.62 seconds
Started Jun 02 12:42:44 PM PDT 24
Finished Jun 02 12:43:09 PM PDT 24
Peak memory 212316 kb
Host smart-e7a32a7c-5c46-41da-96e1-01b9526496a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649384992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3649384992
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1854430337
Short name T217
Test name
Test status
Simulation time 4192885764 ps
CPU time 17.17 seconds
Started Jun 02 12:42:35 PM PDT 24
Finished Jun 02 12:42:52 PM PDT 24
Peak memory 211100 kb
Host smart-73d22a66-f88a-4d11-9235-97537a21c9f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854430337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1854430337
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.229661614
Short name T314
Test name
Test status
Simulation time 719206814 ps
CPU time 9.82 seconds
Started Jun 02 12:42:30 PM PDT 24
Finished Jun 02 12:42:40 PM PDT 24
Peak memory 213072 kb
Host smart-ecf2c407-7e0a-48d5-ac8f-a44138e5faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229661614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.229661614
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3216121418
Short name T191
Test name
Test status
Simulation time 1165361539 ps
CPU time 17.38 seconds
Started Jun 02 12:42:27 PM PDT 24
Finished Jun 02 12:42:46 PM PDT 24
Peak memory 211900 kb
Host smart-c6101182-4bd2-476a-a93e-1607c354fbf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216121418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3216121418
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4097546455
Short name T76
Test name
Test status
Simulation time 1730197728 ps
CPU time 14.24 seconds
Started Jun 02 12:42:36 PM PDT 24
Finished Jun 02 12:42:51 PM PDT 24
Peak memory 211052 kb
Host smart-e9137fe6-e200-4f72-bd94-b7254190bb2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097546455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4097546455
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1589708148
Short name T58
Test name
Test status
Simulation time 13904915744 ps
CPU time 109.59 seconds
Started Jun 02 12:42:38 PM PDT 24
Finished Jun 02 12:44:28 PM PDT 24
Peak memory 212404 kb
Host smart-d68ba98c-5ccd-439d-825a-c13cce1e6fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589708148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1589708148
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2196230092
Short name T26
Test name
Test status
Simulation time 499621031 ps
CPU time 13.32 seconds
Started Jun 02 12:42:47 PM PDT 24
Finished Jun 02 12:43:02 PM PDT 24
Peak memory 211764 kb
Host smart-9b00473c-a676-4152-bd7d-b38383eb0159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196230092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2196230092
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1398900615
Short name T309
Test name
Test status
Simulation time 2445849615 ps
CPU time 9.14 seconds
Started Jun 02 12:42:31 PM PDT 24
Finished Jun 02 12:42:40 PM PDT 24
Peak memory 211108 kb
Host smart-cbe0363a-2215-4cf7-b197-01a1da4095a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398900615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1398900615
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4202236259
Short name T245
Test name
Test status
Simulation time 11021961829 ps
CPU time 25.62 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 12:42:58 PM PDT 24
Peak memory 213940 kb
Host smart-f67e7de6-c3fd-4577-89a6-e5924cbb16d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202236259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4202236259
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2029610832
Short name T281
Test name
Test status
Simulation time 8095201282 ps
CPU time 28.66 seconds
Started Jun 02 12:42:35 PM PDT 24
Finished Jun 02 12:43:04 PM PDT 24
Peak memory 212664 kb
Host smart-96409478-1f6f-4364-8e6e-b931e88596f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029610832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2029610832
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2379826004
Short name T170
Test name
Test status
Simulation time 4363285694 ps
CPU time 11.13 seconds
Started Jun 02 12:42:37 PM PDT 24
Finished Jun 02 12:42:48 PM PDT 24
Peak memory 211092 kb
Host smart-7356a99c-e658-4950-8e71-98c6c83425fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379826004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2379826004
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.624651238
Short name T13
Test name
Test status
Simulation time 2501054055 ps
CPU time 88.45 seconds
Started Jun 02 12:42:33 PM PDT 24
Finished Jun 02 12:44:02 PM PDT 24
Peak memory 237712 kb
Host smart-0ec249b7-9562-49e3-b870-e5a359ede55e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624651238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.624651238
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3800960107
Short name T196
Test name
Test status
Simulation time 1975226515 ps
CPU time 16.46 seconds
Started Jun 02 12:42:35 PM PDT 24
Finished Jun 02 12:42:51 PM PDT 24
Peak memory 211736 kb
Host smart-bc139486-ea0a-4a87-97fe-6a1141c977be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800960107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3800960107
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.159848658
Short name T136
Test name
Test status
Simulation time 3386085240 ps
CPU time 12.39 seconds
Started Jun 02 12:42:36 PM PDT 24
Finished Jun 02 12:42:49 PM PDT 24
Peak memory 211060 kb
Host smart-71c8c603-3f36-483c-9ddd-264663acb4fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159848658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.159848658
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2748519161
Short name T141
Test name
Test status
Simulation time 704776056 ps
CPU time 14.55 seconds
Started Jun 02 12:42:34 PM PDT 24
Finished Jun 02 12:42:49 PM PDT 24
Peak memory 212996 kb
Host smart-17a55530-7e21-42c9-8fb6-3d20c4b8a6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748519161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2748519161
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3822088258
Short name T226
Test name
Test status
Simulation time 206842074 ps
CPU time 6.97 seconds
Started Jun 02 12:42:36 PM PDT 24
Finished Jun 02 12:42:44 PM PDT 24
Peak memory 210852 kb
Host smart-6bc6815f-8880-4cb3-8c8a-8b09fe1d52a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822088258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3822088258
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1903010535
Short name T328
Test name
Test status
Simulation time 332565835 ps
CPU time 4.17 seconds
Started Jun 02 12:42:34 PM PDT 24
Finished Jun 02 12:42:39 PM PDT 24
Peak memory 211100 kb
Host smart-1e045f28-cadc-45b4-acbc-f342eee0963c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903010535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1903010535
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3624958192
Short name T266
Test name
Test status
Simulation time 32670245313 ps
CPU time 21.85 seconds
Started Jun 02 12:42:34 PM PDT 24
Finished Jun 02 12:42:56 PM PDT 24
Peak memory 212164 kb
Host smart-1bc81e6a-7b42-42e6-bc56-551c4ff533aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624958192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3624958192
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2982866428
Short name T207
Test name
Test status
Simulation time 1311824071 ps
CPU time 13 seconds
Started Jun 02 12:42:48 PM PDT 24
Finished Jun 02 12:43:02 PM PDT 24
Peak memory 211104 kb
Host smart-ade191eb-e6dd-4b2a-8f50-b17d434536d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982866428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2982866428
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.821790239
Short name T280
Test name
Test status
Simulation time 185533019 ps
CPU time 10.19 seconds
Started Jun 02 12:42:34 PM PDT 24
Finished Jun 02 12:42:44 PM PDT 24
Peak memory 219192 kb
Host smart-17642dcb-5268-4467-90d6-1fc8bb44a49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821790239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.821790239
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3841771760
Short name T46
Test name
Test status
Simulation time 1764652443 ps
CPU time 24.92 seconds
Started Jun 02 12:42:32 PM PDT 24
Finished Jun 02 12:42:58 PM PDT 24
Peak memory 215160 kb
Host smart-0a6bdf1b-3c3d-4aff-ab07-c0657b643945
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841771760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3841771760
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2530023713
Short name T294
Test name
Test status
Simulation time 52191687466 ps
CPU time 2007.35 seconds
Started Jun 02 12:42:40 PM PDT 24
Finished Jun 02 01:16:08 PM PDT 24
Peak memory 234068 kb
Host smart-9fb40220-c991-426d-8c02-e14848310655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530023713 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2530023713
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3768479863
Short name T189
Test name
Test status
Simulation time 6564667877 ps
CPU time 14.18 seconds
Started Jun 02 12:42:42 PM PDT 24
Finished Jun 02 12:42:57 PM PDT 24
Peak memory 211228 kb
Host smart-549db82b-afc0-4418-a8aa-26040379d6a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768479863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3768479863
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4095643573
Short name T60
Test name
Test status
Simulation time 61777676126 ps
CPU time 183.17 seconds
Started Jun 02 12:42:45 PM PDT 24
Finished Jun 02 12:45:49 PM PDT 24
Peak memory 237588 kb
Host smart-13bef253-f5d6-4fb5-948f-8869743f64ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095643573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4095643573
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4157789934
Short name T183
Test name
Test status
Simulation time 4128662527 ps
CPU time 33.55 seconds
Started Jun 02 12:42:36 PM PDT 24
Finished Jun 02 12:43:10 PM PDT 24
Peak memory 211984 kb
Host smart-a92624b4-3eb1-4a19-a4e3-2063555304bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157789934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4157789934
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.438892386
Short name T138
Test name
Test status
Simulation time 526534590 ps
CPU time 5.34 seconds
Started Jun 02 12:42:51 PM PDT 24
Finished Jun 02 12:42:57 PM PDT 24
Peak memory 211040 kb
Host smart-9f341f85-d86e-430f-b869-db93b2254f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438892386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.438892386
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3668310440
Short name T323
Test name
Test status
Simulation time 189565096 ps
CPU time 9.62 seconds
Started Jun 02 12:42:38 PM PDT 24
Finished Jun 02 12:42:48 PM PDT 24
Peak memory 213176 kb
Host smart-58be89a0-9870-4d0c-9730-ab38c9f6592f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668310440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3668310440
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.453636691
Short name T119
Test name
Test status
Simulation time 2672023134 ps
CPU time 15.68 seconds
Started Jun 02 12:42:34 PM PDT 24
Finished Jun 02 12:42:50 PM PDT 24
Peak memory 212380 kb
Host smart-a69c8d46-ed4f-4be6-b6d4-33b168d41110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453636691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.453636691
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.338129088
Short name T72
Test name
Test status
Simulation time 893242841 ps
CPU time 10.16 seconds
Started Jun 02 12:41:47 PM PDT 24
Finished Jun 02 12:41:57 PM PDT 24
Peak memory 210932 kb
Host smart-79ea97dc-27fb-4bec-8136-4077d8e27d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338129088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.338129088
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3951177749
Short name T194
Test name
Test status
Simulation time 91237129729 ps
CPU time 262.04 seconds
Started Jun 02 12:42:00 PM PDT 24
Finished Jun 02 12:46:22 PM PDT 24
Peak memory 228980 kb
Host smart-19f3d48f-e1ff-4f86-950e-cc72d4262ba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951177749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3951177749
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3232445008
Short name T316
Test name
Test status
Simulation time 34063261452 ps
CPU time 34.16 seconds
Started Jun 02 12:42:03 PM PDT 24
Finished Jun 02 12:42:38 PM PDT 24
Peak memory 212144 kb
Host smart-9628e35d-5a72-4df0-b217-ed1a1c78fa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232445008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3232445008
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.709488547
Short name T211
Test name
Test status
Simulation time 1013552717 ps
CPU time 11.75 seconds
Started Jun 02 12:42:01 PM PDT 24
Finished Jun 02 12:42:14 PM PDT 24
Peak memory 211004 kb
Host smart-289a0878-e534-4b8a-9de4-995889453792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709488547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.709488547
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1057074037
Short name T199
Test name
Test status
Simulation time 5317630365 ps
CPU time 25.59 seconds
Started Jun 02 12:41:51 PM PDT 24
Finished Jun 02 12:42:17 PM PDT 24
Peak memory 213480 kb
Host smart-a4cd0d38-3f44-4105-9c2f-6ca2200289d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057074037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1057074037
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1563770347
Short name T248
Test name
Test status
Simulation time 813488323 ps
CPU time 13.55 seconds
Started Jun 02 12:42:05 PM PDT 24
Finished Jun 02 12:42:20 PM PDT 24
Peak memory 212240 kb
Host smart-52d6edb7-18a6-4bfb-a121-78031ef72c48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563770347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1563770347
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3705408166
Short name T238
Test name
Test status
Simulation time 551334761 ps
CPU time 7.75 seconds
Started Jun 02 12:41:56 PM PDT 24
Finished Jun 02 12:42:09 PM PDT 24
Peak memory 211024 kb
Host smart-a1afd447-5524-4572-973b-6379351e7b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705408166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3705408166
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.224155622
Short name T289
Test name
Test status
Simulation time 5384145770 ps
CPU time 87.86 seconds
Started Jun 02 12:41:45 PM PDT 24
Finished Jun 02 12:43:13 PM PDT 24
Peak memory 233692 kb
Host smart-7979f75c-fbb2-49de-8237-2916cfe0e7e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224155622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.224155622
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1641750768
Short name T201
Test name
Test status
Simulation time 967016313 ps
CPU time 16.13 seconds
Started Jun 02 12:41:49 PM PDT 24
Finished Jun 02 12:42:05 PM PDT 24
Peak memory 211116 kb
Host smart-48f5770d-89bd-43c3-a033-aafb4b7ce717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641750768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1641750768
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.776043006
Short name T198
Test name
Test status
Simulation time 14530619321 ps
CPU time 11.63 seconds
Started Jun 02 12:41:51 PM PDT 24
Finished Jun 02 12:42:03 PM PDT 24
Peak memory 211100 kb
Host smart-a12b9ec8-9022-42b7-a473-1bc7da1ad426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776043006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.776043006
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.300362827
Short name T267
Test name
Test status
Simulation time 15256263628 ps
CPU time 28.85 seconds
Started Jun 02 12:41:55 PM PDT 24
Finished Jun 02 12:42:24 PM PDT 24
Peak memory 214048 kb
Host smart-abaaa662-aa4c-4599-8529-58d5cda52155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300362827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.300362827
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1549577859
Short name T154
Test name
Test status
Simulation time 21293164206 ps
CPU time 12.79 seconds
Started Jun 02 12:41:54 PM PDT 24
Finished Jun 02 12:42:07 PM PDT 24
Peak memory 210976 kb
Host smart-12776cea-8c34-481a-a080-403387d81ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549577859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1549577859
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3635072105
Short name T156
Test name
Test status
Simulation time 4263095373 ps
CPU time 174.67 seconds
Started Jun 02 12:41:56 PM PDT 24
Finished Jun 02 12:44:51 PM PDT 24
Peak memory 236936 kb
Host smart-2c46daa8-f97e-4e22-b16e-6bdeefc96624
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635072105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3635072105
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1083345243
Short name T222
Test name
Test status
Simulation time 3778186577 ps
CPU time 32.54 seconds
Started Jun 02 12:41:56 PM PDT 24
Finished Jun 02 12:42:29 PM PDT 24
Peak memory 211712 kb
Host smart-7f709ee6-b48b-4b5f-811c-ab54237b3fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083345243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1083345243
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.432382910
Short name T171
Test name
Test status
Simulation time 187495422 ps
CPU time 5.55 seconds
Started Jun 02 12:41:48 PM PDT 24
Finished Jun 02 12:41:54 PM PDT 24
Peak memory 211020 kb
Host smart-084dfe9d-1076-4499-9332-0265b681eff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432382910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.432382910
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1638556657
Short name T292
Test name
Test status
Simulation time 370214213 ps
CPU time 10.15 seconds
Started Jun 02 12:41:56 PM PDT 24
Finished Jun 02 12:42:06 PM PDT 24
Peak memory 212896 kb
Host smart-2c1e2f5c-df9a-4779-b47b-f3f06fb75ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638556657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1638556657
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2339641577
Short name T313
Test name
Test status
Simulation time 190860511 ps
CPU time 12.08 seconds
Started Jun 02 12:41:45 PM PDT 24
Finished Jun 02 12:41:58 PM PDT 24
Peak memory 214196 kb
Host smart-04479954-84d2-4d0f-ba02-b509ca508f75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339641577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2339641577
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1043143010
Short name T319
Test name
Test status
Simulation time 7925553689 ps
CPU time 16.18 seconds
Started Jun 02 12:42:04 PM PDT 24
Finished Jun 02 12:42:21 PM PDT 24
Peak memory 211128 kb
Host smart-5ce182c8-cb61-4ff7-9c31-5f06e1efb61a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043143010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1043143010
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1344981840
Short name T162
Test name
Test status
Simulation time 2126333262 ps
CPU time 22.78 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:42:21 PM PDT 24
Peak memory 211696 kb
Host smart-7468d7b0-dce0-4ecf-a59e-f6c65e159cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344981840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1344981840
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3811764004
Short name T336
Test name
Test status
Simulation time 1366355075 ps
CPU time 13.17 seconds
Started Jun 02 12:41:55 PM PDT 24
Finished Jun 02 12:42:09 PM PDT 24
Peak memory 211032 kb
Host smart-29c33561-ea74-4fe6-bda3-778537179858
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811764004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3811764004
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2508536593
Short name T38
Test name
Test status
Simulation time 375365780 ps
CPU time 9.95 seconds
Started Jun 02 12:41:54 PM PDT 24
Finished Jun 02 12:42:04 PM PDT 24
Peak memory 213184 kb
Host smart-16c2a41f-cc06-4e3e-8f6b-52b8da84f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508536593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2508536593
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1207137993
Short name T2
Test name
Test status
Simulation time 396061512 ps
CPU time 10.4 seconds
Started Jun 02 12:42:03 PM PDT 24
Finished Jun 02 12:42:14 PM PDT 24
Peak memory 213432 kb
Host smart-364a7f8b-99b7-419c-b863-e0433f1d22ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207137993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1207137993
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1644133052
Short name T295
Test name
Test status
Simulation time 660687767 ps
CPU time 8.59 seconds
Started Jun 02 12:42:06 PM PDT 24
Finished Jun 02 12:42:20 PM PDT 24
Peak memory 211028 kb
Host smart-0b2d95fe-ba2d-4a78-9ac8-1d36df5219dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644133052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1644133052
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2864962006
Short name T283
Test name
Test status
Simulation time 448793165164 ps
CPU time 351.41 seconds
Started Jun 02 12:42:05 PM PDT 24
Finished Jun 02 12:47:57 PM PDT 24
Peak memory 233700 kb
Host smart-db5562f9-3fb5-48c6-992b-676d38a1ff0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864962006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2864962006
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4135950374
Short name T167
Test name
Test status
Simulation time 175748964 ps
CPU time 9.43 seconds
Started Jun 02 12:42:03 PM PDT 24
Finished Jun 02 12:42:12 PM PDT 24
Peak memory 212028 kb
Host smart-f88c4f2e-3399-4f9d-85d4-ad72d2efdb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135950374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4135950374
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1899676725
Short name T276
Test name
Test status
Simulation time 40294437751 ps
CPU time 18.9 seconds
Started Jun 02 12:41:53 PM PDT 24
Finished Jun 02 12:42:12 PM PDT 24
Peak memory 211072 kb
Host smart-f240e890-01ff-4fc6-97f6-43b08e39e48c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899676725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1899676725
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.823968997
Short name T368
Test name
Test status
Simulation time 2096307713 ps
CPU time 23.86 seconds
Started Jun 02 12:41:58 PM PDT 24
Finished Jun 02 12:42:23 PM PDT 24
Peak memory 213744 kb
Host smart-6e8c2d0c-6739-42ba-a01c-bb41c2d67bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823968997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.823968997
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.767604265
Short name T354
Test name
Test status
Simulation time 2554230458 ps
CPU time 22.56 seconds
Started Jun 02 12:42:06 PM PDT 24
Finished Jun 02 12:42:29 PM PDT 24
Peak memory 211480 kb
Host smart-0965f3d1-b1ce-4088-b31f-ff7360ea53b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767604265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.767604265
Directory /workspace/9.rom_ctrl_stress_all/latest
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