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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 96.97 93.59 97.88 100.00 99.02 98.04 99.07


Total test records in report: 465
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T298 /workspace/coverage/default/3.rom_ctrl_smoke.1664672270 Jun 04 12:47:34 PM PDT 24 Jun 04 12:47:45 PM PDT 24 218619506 ps
T299 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2793367387 Jun 04 12:47:31 PM PDT 24 Jun 04 12:50:07 PM PDT 24 15852971070 ps
T300 /workspace/coverage/default/23.rom_ctrl_smoke.3242986721 Jun 04 12:47:58 PM PDT 24 Jun 04 12:48:32 PM PDT 24 4082258881 ps
T301 /workspace/coverage/default/48.rom_ctrl_alert_test.1914941190 Jun 04 12:48:18 PM PDT 24 Jun 04 12:48:32 PM PDT 24 6530238390 ps
T302 /workspace/coverage/default/38.rom_ctrl_stress_all.2172151880 Jun 04 12:48:10 PM PDT 24 Jun 04 12:49:12 PM PDT 24 20408087242 ps
T303 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3701500636 Jun 04 12:48:23 PM PDT 24 Jun 04 12:48:35 PM PDT 24 501098060 ps
T304 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2801999038 Jun 04 12:48:07 PM PDT 24 Jun 04 12:48:17 PM PDT 24 4506700691 ps
T305 /workspace/coverage/default/33.rom_ctrl_stress_all.3803018867 Jun 04 12:48:04 PM PDT 24 Jun 04 12:48:21 PM PDT 24 3701484986 ps
T306 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2211248327 Jun 04 12:47:58 PM PDT 24 Jun 04 12:59:00 PM PDT 24 47187150025 ps
T307 /workspace/coverage/default/36.rom_ctrl_alert_test.4231523649 Jun 04 12:48:07 PM PDT 24 Jun 04 12:48:13 PM PDT 24 123115980 ps
T308 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2542190756 Jun 04 12:48:09 PM PDT 24 Jun 04 12:49:34 PM PDT 24 2264401725 ps
T309 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2374489867 Jun 04 12:47:51 PM PDT 24 Jun 04 12:50:49 PM PDT 24 37300333704 ps
T310 /workspace/coverage/default/21.rom_ctrl_stress_all.4050294161 Jun 04 12:47:58 PM PDT 24 Jun 04 12:48:09 PM PDT 24 198601882 ps
T311 /workspace/coverage/default/15.rom_ctrl_stress_all.1302031184 Jun 04 12:47:51 PM PDT 24 Jun 04 12:48:45 PM PDT 24 55776955980 ps
T312 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4223755074 Jun 04 12:48:17 PM PDT 24 Jun 04 12:48:35 PM PDT 24 2514565406 ps
T313 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3813455096 Jun 04 12:48:08 PM PDT 24 Jun 04 12:48:21 PM PDT 24 14273422330 ps
T314 /workspace/coverage/default/6.rom_ctrl_stress_all.2911779163 Jun 04 12:47:39 PM PDT 24 Jun 04 12:48:30 PM PDT 24 2061258217 ps
T315 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1507287518 Jun 04 12:48:13 PM PDT 24 Jun 04 12:52:11 PM PDT 24 90919316270 ps
T316 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3468095567 Jun 04 12:47:57 PM PDT 24 Jun 04 12:48:10 PM PDT 24 5168262908 ps
T317 /workspace/coverage/default/24.rom_ctrl_alert_test.1528117361 Jun 04 12:48:02 PM PDT 24 Jun 04 12:48:08 PM PDT 24 232825042 ps
T318 /workspace/coverage/default/43.rom_ctrl_alert_test.1463076814 Jun 04 12:48:09 PM PDT 24 Jun 04 12:48:25 PM PDT 24 1739583420 ps
T319 /workspace/coverage/default/41.rom_ctrl_smoke.1112697107 Jun 04 12:48:08 PM PDT 24 Jun 04 12:48:28 PM PDT 24 1125364034 ps
T320 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1284169818 Jun 04 12:47:49 PM PDT 24 Jun 04 12:48:01 PM PDT 24 416392137 ps
T321 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2577043560 Jun 04 12:47:59 PM PDT 24 Jun 04 12:48:19 PM PDT 24 8278934420 ps
T322 /workspace/coverage/default/0.rom_ctrl_alert_test.1138628348 Jun 04 12:47:30 PM PDT 24 Jun 04 12:47:36 PM PDT 24 86665602 ps
T323 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.508027113 Jun 04 12:47:31 PM PDT 24 Jun 04 12:47:38 PM PDT 24 376311186 ps
T324 /workspace/coverage/default/29.rom_ctrl_alert_test.1897035151 Jun 04 12:48:00 PM PDT 24 Jun 04 12:48:18 PM PDT 24 4058908196 ps
T325 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1021555185 Jun 04 12:48:00 PM PDT 24 Jun 04 12:51:52 PM PDT 24 47653152603 ps
T326 /workspace/coverage/default/17.rom_ctrl_stress_all.4275676101 Jun 04 12:47:52 PM PDT 24 Jun 04 12:48:27 PM PDT 24 4211843519 ps
T327 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.747107477 Jun 04 12:48:08 PM PDT 24 Jun 04 12:48:30 PM PDT 24 12241052273 ps
T328 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1944052401 Jun 04 12:47:58 PM PDT 24 Jun 04 01:28:36 PM PDT 24 12200494992 ps
T329 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2811164477 Jun 04 12:48:13 PM PDT 24 Jun 04 12:55:35 PM PDT 24 115733349058 ps
T330 /workspace/coverage/default/18.rom_ctrl_smoke.3782756069 Jun 04 12:48:07 PM PDT 24 Jun 04 12:48:45 PM PDT 24 30210459523 ps
T331 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3557253742 Jun 04 12:47:58 PM PDT 24 Jun 04 12:52:42 PM PDT 24 31877091924 ps
T332 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3640272187 Jun 04 12:48:11 PM PDT 24 Jun 04 12:48:44 PM PDT 24 4062225862 ps
T333 /workspace/coverage/default/43.rom_ctrl_stress_all.2865182778 Jun 04 12:48:12 PM PDT 24 Jun 04 12:48:39 PM PDT 24 1803915007 ps
T334 /workspace/coverage/default/14.rom_ctrl_smoke.3185692235 Jun 04 12:47:49 PM PDT 24 Jun 04 12:48:13 PM PDT 24 4573318302 ps
T335 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.427033904 Jun 04 12:47:36 PM PDT 24 Jun 04 12:47:49 PM PDT 24 463489031 ps
T336 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1534087459 Jun 04 12:47:42 PM PDT 24 Jun 04 12:48:12 PM PDT 24 3192237302 ps
T337 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3354365703 Jun 04 12:47:48 PM PDT 24 Jun 04 12:50:39 PM PDT 24 44868890103 ps
T338 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2082330831 Jun 04 12:48:18 PM PDT 24 Jun 04 12:50:58 PM PDT 24 13073727303 ps
T339 /workspace/coverage/default/5.rom_ctrl_smoke.2145834116 Jun 04 12:47:35 PM PDT 24 Jun 04 12:47:50 PM PDT 24 7050772976 ps
T340 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2649160701 Jun 04 12:47:46 PM PDT 24 Jun 04 12:48:05 PM PDT 24 4060968860 ps
T341 /workspace/coverage/default/16.rom_ctrl_stress_all.4189869759 Jun 04 12:47:52 PM PDT 24 Jun 04 12:48:53 PM PDT 24 23806254712 ps
T342 /workspace/coverage/default/5.rom_ctrl_stress_all.1889840181 Jun 04 12:47:36 PM PDT 24 Jun 04 12:48:47 PM PDT 24 63521600350 ps
T343 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3350174257 Jun 04 12:47:49 PM PDT 24 Jun 04 12:48:00 PM PDT 24 175694190 ps
T344 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1277589128 Jun 04 12:48:10 PM PDT 24 Jun 04 12:48:39 PM PDT 24 13545079349 ps
T345 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.663006358 Jun 04 12:48:18 PM PDT 24 Jun 04 12:48:40 PM PDT 24 1653403111 ps
T346 /workspace/coverage/default/22.rom_ctrl_smoke.489142249 Jun 04 12:48:04 PM PDT 24 Jun 04 12:48:17 PM PDT 24 279075410 ps
T347 /workspace/coverage/default/49.rom_ctrl_alert_test.1848046129 Jun 04 12:48:16 PM PDT 24 Jun 04 12:48:32 PM PDT 24 1872386155 ps
T348 /workspace/coverage/default/13.rom_ctrl_alert_test.697693073 Jun 04 12:47:47 PM PDT 24 Jun 04 12:47:57 PM PDT 24 1452463076 ps
T349 /workspace/coverage/default/25.rom_ctrl_stress_all.1376381740 Jun 04 12:47:59 PM PDT 24 Jun 04 12:48:41 PM PDT 24 23010502523 ps
T350 /workspace/coverage/default/12.rom_ctrl_alert_test.311630057 Jun 04 12:48:00 PM PDT 24 Jun 04 12:48:18 PM PDT 24 1977985394 ps
T351 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1073974914 Jun 04 12:48:10 PM PDT 24 Jun 04 12:49:56 PM PDT 24 3378272538 ps
T352 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2988385075 Jun 04 12:47:58 PM PDT 24 Jun 04 12:48:11 PM PDT 24 3006897371 ps
T353 /workspace/coverage/default/42.rom_ctrl_alert_test.292681107 Jun 04 12:48:09 PM PDT 24 Jun 04 12:48:26 PM PDT 24 3447110217 ps
T354 /workspace/coverage/default/45.rom_ctrl_alert_test.2943538694 Jun 04 12:48:20 PM PDT 24 Jun 04 12:48:28 PM PDT 24 1109124334 ps
T355 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2773836003 Jun 04 12:47:42 PM PDT 24 Jun 04 12:49:59 PM PDT 24 57521489281 ps
T356 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3951123192 Jun 04 12:47:59 PM PDT 24 Jun 04 12:57:23 PM PDT 24 55850917952 ps
T357 /workspace/coverage/default/7.rom_ctrl_smoke.2210429393 Jun 04 12:47:53 PM PDT 24 Jun 04 12:48:17 PM PDT 24 7905287760 ps
T358 /workspace/coverage/default/42.rom_ctrl_smoke.4244913214 Jun 04 12:48:36 PM PDT 24 Jun 04 12:49:11 PM PDT 24 4154308965 ps
T359 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1265861951 Jun 04 12:47:56 PM PDT 24 Jun 04 12:48:11 PM PDT 24 4949297331 ps
T360 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.737986943 Jun 04 12:47:42 PM PDT 24 Jun 04 12:48:09 PM PDT 24 5539716542 ps
T361 /workspace/coverage/default/19.rom_ctrl_smoke.817128845 Jun 04 12:47:51 PM PDT 24 Jun 04 12:48:18 PM PDT 24 11571420969 ps
T362 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.553098120 Jun 04 12:47:54 PM PDT 24 Jun 04 12:55:44 PM PDT 24 205217395160 ps
T363 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3781143997 Jun 04 12:47:55 PM PDT 24 Jun 04 12:48:14 PM PDT 24 2008782793 ps
T364 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1824400514 Jun 04 12:47:49 PM PDT 24 Jun 04 12:50:20 PM PDT 24 59277025147 ps
T365 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1212717111 Jun 04 12:47:43 PM PDT 24 Jun 04 12:47:58 PM PDT 24 536860066 ps
T366 /workspace/coverage/default/10.rom_ctrl_stress_all.418092655 Jun 04 12:47:43 PM PDT 24 Jun 04 12:48:09 PM PDT 24 4674042418 ps
T367 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4234069602 Jun 04 12:47:58 PM PDT 24 Jun 04 12:48:18 PM PDT 24 8457281003 ps
T67 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3888609048 Jun 04 12:43:47 PM PDT 24 Jun 04 12:44:37 PM PDT 24 19277567646 ps
T68 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1936811890 Jun 04 12:43:37 PM PDT 24 Jun 04 12:43:47 PM PDT 24 2360998166 ps
T69 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3408764414 Jun 04 12:43:25 PM PDT 24 Jun 04 12:43:39 PM PDT 24 22815128744 ps
T368 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4173836146 Jun 04 12:43:53 PM PDT 24 Jun 04 12:44:02 PM PDT 24 515782113 ps
T369 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1370252432 Jun 04 12:43:17 PM PDT 24 Jun 04 12:43:29 PM PDT 24 1205674211 ps
T111 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2304307048 Jun 04 12:43:35 PM PDT 24 Jun 04 12:44:15 PM PDT 24 13817301766 ps
T71 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2663166460 Jun 04 12:43:26 PM PDT 24 Jun 04 12:43:42 PM PDT 24 5895205617 ps
T105 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1003394608 Jun 04 12:43:24 PM PDT 24 Jun 04 12:43:31 PM PDT 24 1545229018 ps
T64 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1554978651 Jun 04 12:43:18 PM PDT 24 Jun 04 12:44:31 PM PDT 24 4931190133 ps
T112 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3265453786 Jun 04 12:43:21 PM PDT 24 Jun 04 12:43:26 PM PDT 24 346295371 ps
T72 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.977581225 Jun 04 12:43:45 PM PDT 24 Jun 04 12:45:22 PM PDT 24 144697562402 ps
T370 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2063009361 Jun 04 12:43:26 PM PDT 24 Jun 04 12:43:42 PM PDT 24 7018592189 ps
T73 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.482654515 Jun 04 12:43:36 PM PDT 24 Jun 04 12:43:47 PM PDT 24 1102114305 ps
T74 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3775956241 Jun 04 12:43:31 PM PDT 24 Jun 04 12:43:42 PM PDT 24 1060854753 ps
T113 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.223133260 Jun 04 12:43:26 PM PDT 24 Jun 04 12:43:45 PM PDT 24 1509028873 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.204911100 Jun 04 12:42:57 PM PDT 24 Jun 04 12:43:10 PM PDT 24 10965626784 ps
T372 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1154150877 Jun 04 12:43:24 PM PDT 24 Jun 04 12:43:38 PM PDT 24 1238518326 ps
T373 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4121092993 Jun 04 12:43:21 PM PDT 24 Jun 04 12:43:28 PM PDT 24 823796702 ps
T374 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1350368334 Jun 04 12:43:36 PM PDT 24 Jun 04 12:43:47 PM PDT 24 1711330623 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1086291650 Jun 04 12:43:08 PM PDT 24 Jun 04 12:44:17 PM PDT 24 886456118 ps
T375 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3061811331 Jun 04 12:43:45 PM PDT 24 Jun 04 12:43:58 PM PDT 24 1186978704 ps
T75 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3255670533 Jun 04 12:43:09 PM PDT 24 Jun 04 12:43:23 PM PDT 24 3482133106 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1360047107 Jun 04 12:42:59 PM PDT 24 Jun 04 12:43:03 PM PDT 24 319986737 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1915529548 Jun 04 12:43:29 PM PDT 24 Jun 04 12:43:34 PM PDT 24 184952422 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1217524117 Jun 04 12:43:49 PM PDT 24 Jun 04 12:44:03 PM PDT 24 3628717101 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4234199114 Jun 04 12:43:18 PM PDT 24 Jun 04 12:43:35 PM PDT 24 2873032640 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.186541776 Jun 04 12:43:18 PM PDT 24 Jun 04 12:43:30 PM PDT 24 1109226208 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1697342757 Jun 04 12:43:25 PM PDT 24 Jun 04 12:43:31 PM PDT 24 168463934 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1452424494 Jun 04 12:43:16 PM PDT 24 Jun 04 12:43:26 PM PDT 24 3757045030 ps
T106 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2860511186 Jun 04 12:43:55 PM PDT 24 Jun 04 12:44:11 PM PDT 24 7797500123 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.550276011 Jun 04 12:43:10 PM PDT 24 Jun 04 12:43:24 PM PDT 24 6284840628 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1200382958 Jun 04 12:42:58 PM PDT 24 Jun 04 12:43:12 PM PDT 24 2243435266 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3477391217 Jun 04 12:43:48 PM PDT 24 Jun 04 12:44:03 PM PDT 24 1737062807 ps
T383 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3993235327 Jun 04 12:43:48 PM PDT 24 Jun 04 12:43:57 PM PDT 24 1780976822 ps
T107 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1054300639 Jun 04 12:43:28 PM PDT 24 Jun 04 12:43:43 PM PDT 24 1623074427 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1965393922 Jun 04 12:42:59 PM PDT 24 Jun 04 12:43:15 PM PDT 24 8838546639 ps
T385 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1930245169 Jun 04 12:43:46 PM PDT 24 Jun 04 12:44:04 PM PDT 24 3271272556 ps
T386 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2042465728 Jun 04 12:43:25 PM PDT 24 Jun 04 12:43:35 PM PDT 24 2047237228 ps
T66 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.698800102 Jun 04 12:43:35 PM PDT 24 Jun 04 12:44:43 PM PDT 24 264834044 ps
T387 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3075077344 Jun 04 12:43:54 PM PDT 24 Jun 04 12:44:11 PM PDT 24 1583844582 ps
T117 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4187931163 Jun 04 12:42:57 PM PDT 24 Jun 04 12:43:37 PM PDT 24 3070934273 ps
T388 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.966268658 Jun 04 12:43:46 PM PDT 24 Jun 04 12:43:54 PM PDT 24 120916103 ps
T79 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2642072396 Jun 04 12:42:59 PM PDT 24 Jun 04 12:43:10 PM PDT 24 801497075 ps
T108 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1437378669 Jun 04 12:43:46 PM PDT 24 Jun 04 12:43:51 PM PDT 24 88112547 ps
T118 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.230758567 Jun 04 12:43:27 PM PDT 24 Jun 04 12:44:44 PM PDT 24 1312898674 ps
T109 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1690450505 Jun 04 12:43:38 PM PDT 24 Jun 04 12:44:29 PM PDT 24 21130076974 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2664506103 Jun 04 12:43:17 PM PDT 24 Jun 04 12:43:34 PM PDT 24 4201479064 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2258282885 Jun 04 12:43:00 PM PDT 24 Jun 04 12:43:08 PM PDT 24 461412095 ps
T110 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3677018794 Jun 04 12:43:36 PM PDT 24 Jun 04 12:43:49 PM PDT 24 6681066495 ps
T391 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.30264854 Jun 04 12:43:26 PM PDT 24 Jun 04 12:43:32 PM PDT 24 321551544 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.989573279 Jun 04 12:43:08 PM PDT 24 Jun 04 12:43:16 PM PDT 24 1027500170 ps
T120 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1608852025 Jun 04 12:43:54 PM PDT 24 Jun 04 12:45:11 PM PDT 24 3845564096 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.104197386 Jun 04 12:43:19 PM PDT 24 Jun 04 12:43:26 PM PDT 24 812428522 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3274042828 Jun 04 12:43:45 PM PDT 24 Jun 04 12:44:30 PM PDT 24 5082967979 ps
T116 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.948657346 Jun 04 12:43:36 PM PDT 24 Jun 04 12:44:06 PM PDT 24 1510013166 ps
T121 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3208394861 Jun 04 12:43:38 PM PDT 24 Jun 04 12:44:50 PM PDT 24 1127697956 ps
T394 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2146997350 Jun 04 12:43:37 PM PDT 24 Jun 04 12:43:52 PM PDT 24 6435584698 ps
T395 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2341158419 Jun 04 12:43:26 PM PDT 24 Jun 04 12:43:35 PM PDT 24 118951290 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.993697305 Jun 04 12:43:00 PM PDT 24 Jun 04 12:44:20 PM PDT 24 36096452281 ps
T397 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4087187797 Jun 04 12:42:59 PM PDT 24 Jun 04 12:43:08 PM PDT 24 2799148694 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.738279601 Jun 04 12:43:27 PM PDT 24 Jun 04 12:44:13 PM PDT 24 4624760864 ps
T124 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4135826586 Jun 04 12:42:59 PM PDT 24 Jun 04 12:44:10 PM PDT 24 1186347212 ps
T86 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.924784801 Jun 04 12:43:31 PM PDT 24 Jun 04 12:44:14 PM PDT 24 8734075095 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.282768689 Jun 04 12:43:10 PM PDT 24 Jun 04 12:43:27 PM PDT 24 11665614749 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4280646289 Jun 04 12:42:56 PM PDT 24 Jun 04 12:43:08 PM PDT 24 1106843644 ps
T401 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1515192684 Jun 04 12:43:26 PM PDT 24 Jun 04 12:43:35 PM PDT 24 550549822 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.544603558 Jun 04 12:42:59 PM PDT 24 Jun 04 12:43:15 PM PDT 24 5981678028 ps
T403 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1639692200 Jun 04 12:43:29 PM PDT 24 Jun 04 12:43:44 PM PDT 24 1023376194 ps
T87 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2123300926 Jun 04 12:43:10 PM PDT 24 Jun 04 12:43:43 PM PDT 24 2110305328 ps
T88 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1299512763 Jun 04 12:43:26 PM PDT 24 Jun 04 12:43:34 PM PDT 24 917657042 ps
T404 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1846217777 Jun 04 12:43:35 PM PDT 24 Jun 04 12:43:51 PM PDT 24 2645302503 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1510442040 Jun 04 12:43:09 PM PDT 24 Jun 04 12:43:19 PM PDT 24 4495783972 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3999039608 Jun 04 12:43:17 PM PDT 24 Jun 04 12:43:30 PM PDT 24 537861378 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1069623213 Jun 04 12:43:07 PM PDT 24 Jun 04 12:43:22 PM PDT 24 1355277179 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1985677547 Jun 04 12:43:17 PM PDT 24 Jun 04 12:43:34 PM PDT 24 7854036418 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1537485975 Jun 04 12:43:21 PM PDT 24 Jun 04 12:43:32 PM PDT 24 4096633789 ps
T410 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4101935318 Jun 04 12:43:57 PM PDT 24 Jun 04 12:44:07 PM PDT 24 885739861 ps
T411 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.526058133 Jun 04 12:43:25 PM PDT 24 Jun 04 12:43:35 PM PDT 24 1497594690 ps
T122 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3800891630 Jun 04 12:43:26 PM PDT 24 Jun 04 12:44:05 PM PDT 24 272342713 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1570137768 Jun 04 12:43:45 PM PDT 24 Jun 04 12:43:57 PM PDT 24 894953913 ps
T413 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.956266180 Jun 04 12:43:44 PM PDT 24 Jun 04 12:43:54 PM PDT 24 680736796 ps
T414 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.106853775 Jun 04 12:43:35 PM PDT 24 Jun 04 12:43:45 PM PDT 24 1707384757 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2449469974 Jun 04 12:43:22 PM PDT 24 Jun 04 12:43:33 PM PDT 24 4252393325 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1206315934 Jun 04 12:43:22 PM PDT 24 Jun 04 12:43:40 PM PDT 24 10110971308 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2077629000 Jun 04 12:43:10 PM PDT 24 Jun 04 12:43:25 PM PDT 24 3513570171 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2502712593 Jun 04 12:43:08 PM PDT 24 Jun 04 12:43:22 PM PDT 24 7350628232 ps
T417 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1502078489 Jun 04 12:43:34 PM PDT 24 Jun 04 12:43:53 PM PDT 24 3184163472 ps
T127 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2135698893 Jun 04 12:43:38 PM PDT 24 Jun 04 12:44:52 PM PDT 24 11073237551 ps
T418 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2016596921 Jun 04 12:43:34 PM PDT 24 Jun 04 12:43:47 PM PDT 24 5034039064 ps
T419 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.162907024 Jun 04 12:43:34 PM PDT 24 Jun 04 12:43:52 PM PDT 24 8943928241 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4185867700 Jun 04 12:43:46 PM PDT 24 Jun 04 12:44:32 PM PDT 24 1587566433 ps
T421 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3118993362 Jun 04 12:43:37 PM PDT 24 Jun 04 12:43:49 PM PDT 24 2620880991 ps
T422 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2294983669 Jun 04 12:43:36 PM PDT 24 Jun 04 12:44:17 PM PDT 24 9036282623 ps
T423 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1814946370 Jun 04 12:43:37 PM PDT 24 Jun 04 12:43:45 PM PDT 24 318187896 ps
T424 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3881753903 Jun 04 12:43:30 PM PDT 24 Jun 04 12:43:41 PM PDT 24 3924667599 ps
T425 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1718955954 Jun 04 12:43:28 PM PDT 24 Jun 04 12:44:03 PM PDT 24 6097400421 ps
T128 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2240774116 Jun 04 12:43:46 PM PDT 24 Jun 04 12:44:29 PM PDT 24 5065124520 ps
T426 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1362531966 Jun 04 12:43:34 PM PDT 24 Jun 04 12:43:45 PM PDT 24 1263843573 ps
T91 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.121365553 Jun 04 12:43:19 PM PDT 24 Jun 04 12:43:35 PM PDT 24 8148808101 ps
T125 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2739370874 Jun 04 12:43:25 PM PDT 24 Jun 04 12:44:07 PM PDT 24 5454839846 ps
T427 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1384437650 Jun 04 12:43:39 PM PDT 24 Jun 04 12:43:47 PM PDT 24 1303655474 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.148320651 Jun 04 12:43:18 PM PDT 24 Jun 04 12:43:37 PM PDT 24 377823143 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2495601210 Jun 04 12:43:18 PM PDT 24 Jun 04 12:43:23 PM PDT 24 172007469 ps
T429 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1085345862 Jun 04 12:43:37 PM PDT 24 Jun 04 12:43:42 PM PDT 24 168482023 ps
T430 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2150129548 Jun 04 12:43:45 PM PDT 24 Jun 04 12:43:51 PM PDT 24 90079792 ps
T431 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3531327692 Jun 04 12:43:25 PM PDT 24 Jun 04 12:43:31 PM PDT 24 92996141 ps
T432 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2770625776 Jun 04 12:43:45 PM PDT 24 Jun 04 12:43:56 PM PDT 24 1164729451 ps
T433 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.702466571 Jun 04 12:43:25 PM PDT 24 Jun 04 12:44:42 PM PDT 24 6168791615 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3605547577 Jun 04 12:43:17 PM PDT 24 Jun 04 12:43:27 PM PDT 24 955941627 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4154655549 Jun 04 12:43:08 PM PDT 24 Jun 04 12:43:22 PM PDT 24 2798148040 ps
T436 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1270067026 Jun 04 12:43:53 PM PDT 24 Jun 04 12:44:30 PM PDT 24 765327399 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1368666961 Jun 04 12:43:07 PM PDT 24 Jun 04 12:43:21 PM PDT 24 1436531450 ps
T438 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2733503839 Jun 04 12:43:54 PM PDT 24 Jun 04 12:44:02 PM PDT 24 499521673 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.206669575 Jun 04 12:43:46 PM PDT 24 Jun 04 12:43:52 PM PDT 24 399407352 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2377780232 Jun 04 12:43:09 PM PDT 24 Jun 04 12:43:23 PM PDT 24 1596407375 ps
T126 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3683764050 Jun 04 12:43:45 PM PDT 24 Jun 04 12:44:27 PM PDT 24 1074172095 ps
T123 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4148654623 Jun 04 12:43:17 PM PDT 24 Jun 04 12:43:56 PM PDT 24 2058326098 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.815268671 Jun 04 12:43:46 PM PDT 24 Jun 04 12:43:58 PM PDT 24 3430506939 ps
T442 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3638974655 Jun 04 12:43:25 PM PDT 24 Jun 04 12:43:32 PM PDT 24 387021577 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3727612459 Jun 04 12:42:57 PM PDT 24 Jun 04 12:43:11 PM PDT 24 5285421299 ps
T444 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1175984556 Jun 04 12:43:36 PM PDT 24 Jun 04 12:43:49 PM PDT 24 5880521387 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.923027924 Jun 04 12:43:00 PM PDT 24 Jun 04 12:43:14 PM PDT 24 8581253935 ps
T94 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1906163666 Jun 04 12:43:56 PM PDT 24 Jun 04 12:44:56 PM PDT 24 29038973736 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1924419510 Jun 04 12:43:10 PM PDT 24 Jun 04 12:43:15 PM PDT 24 85712023 ps
T447 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1331175602 Jun 04 12:43:47 PM PDT 24 Jun 04 12:43:57 PM PDT 24 3737292409 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3120380057 Jun 04 12:43:00 PM PDT 24 Jun 04 12:43:15 PM PDT 24 3507811329 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2023529784 Jun 04 12:43:22 PM PDT 24 Jun 04 12:43:39 PM PDT 24 2104919302 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1328237222 Jun 04 12:43:46 PM PDT 24 Jun 04 12:44:51 PM PDT 24 11866756795 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2844231439 Jun 04 12:43:18 PM PDT 24 Jun 04 12:43:26 PM PDT 24 627115760 ps
T452 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3672704068 Jun 04 12:43:47 PM PDT 24 Jun 04 12:43:54 PM PDT 24 1479825689 ps
T453 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.232910748 Jun 04 12:43:09 PM PDT 24 Jun 04 12:43:19 PM PDT 24 940623648 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.701991929 Jun 04 12:43:09 PM PDT 24 Jun 04 12:43:24 PM PDT 24 2022077931 ps
T93 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.416528540 Jun 04 12:43:25 PM PDT 24 Jun 04 12:44:51 PM PDT 24 9991111660 ps
T455 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3909011520 Jun 04 12:43:54 PM PDT 24 Jun 04 12:44:09 PM PDT 24 15683228471 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.618425184 Jun 04 12:42:59 PM PDT 24 Jun 04 12:43:34 PM PDT 24 4979959412 ps
T457 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.316089564 Jun 04 12:42:57 PM PDT 24 Jun 04 12:43:07 PM PDT 24 1711663847 ps
T458 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4183350387 Jun 04 12:43:35 PM PDT 24 Jun 04 12:43:46 PM PDT 24 612735433 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4113190997 Jun 04 12:43:21 PM PDT 24 Jun 04 12:44:06 PM PDT 24 2514245657 ps
T460 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2908346715 Jun 04 12:43:47 PM PDT 24 Jun 04 12:43:52 PM PDT 24 167825221 ps
T119 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2200072497 Jun 04 12:43:25 PM PDT 24 Jun 04 12:44:03 PM PDT 24 288359323 ps
T461 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4145509349 Jun 04 12:43:36 PM PDT 24 Jun 04 12:44:58 PM PDT 24 9392308709 ps
T462 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.259349799 Jun 04 12:43:26 PM PDT 24 Jun 04 12:43:40 PM PDT 24 3000716435 ps
T463 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2259837427 Jun 04 12:43:36 PM PDT 24 Jun 04 12:44:34 PM PDT 24 7048378308 ps
T464 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.232031018 Jun 04 12:43:55 PM PDT 24 Jun 04 12:44:08 PM PDT 24 2771251752 ps
T465 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3512115009 Jun 04 12:43:44 PM PDT 24 Jun 04 12:45:14 PM PDT 24 47170994972 ps

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.976392552
Short name T2
Test name
Test status
Simulation time 323957988682 ps
CPU time 330.27 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:53:30 PM PDT 24
Peak memory 212708 kb
Host smart-6ea97db0-cad0-4e80-8d50-7b0a07096427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976392552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.976392552
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3866366937
Short name T14
Test name
Test status
Simulation time 101854647903 ps
CPU time 977.93 seconds
Started Jun 04 12:47:52 PM PDT 24
Finished Jun 04 01:04:11 PM PDT 24
Peak memory 235840 kb
Host smart-bb400efa-fd65-4d56-bab2-aafccf7cf45e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866366937 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3866366937
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.74095440
Short name T1
Test name
Test status
Simulation time 8212940927 ps
CPU time 27.08 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:28 PM PDT 24
Peak memory 214700 kb
Host smart-1002b930-ed61-4699-a8c1-e02db0279fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74095440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.74095440
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1086291650
Short name T65
Test name
Test status
Simulation time 886456118 ps
CPU time 68.97 seconds
Started Jun 04 12:43:08 PM PDT 24
Finished Jun 04 12:44:17 PM PDT 24
Peak memory 212272 kb
Host smart-c242eb0b-34c3-4f43-b171-8e069be5ade0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086291650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1086291650
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3052532919
Short name T22
Test name
Test status
Simulation time 3303682030 ps
CPU time 28.83 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:29 PM PDT 24
Peak memory 211788 kb
Host smart-9b39aeeb-b564-4f12-adbd-12e8c094e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052532919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3052532919
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1969823909
Short name T31
Test name
Test status
Simulation time 5773252572 ps
CPU time 104.34 seconds
Started Jun 04 12:47:48 PM PDT 24
Finished Jun 04 12:49:34 PM PDT 24
Peak memory 225788 kb
Host smart-7158f04b-1143-46aa-82d2-9dc315829166
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969823909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1969823909
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4202398791
Short name T39
Test name
Test status
Simulation time 4510573404 ps
CPU time 111.86 seconds
Started Jun 04 12:47:35 PM PDT 24
Finished Jun 04 12:49:28 PM PDT 24
Peak memory 234044 kb
Host smart-f7507333-9841-4d43-90e7-cf9279c0f92e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202398791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4202398791
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3888609048
Short name T67
Test name
Test status
Simulation time 19277567646 ps
CPU time 49.06 seconds
Started Jun 04 12:43:47 PM PDT 24
Finished Jun 04 12:44:37 PM PDT 24
Peak memory 211328 kb
Host smart-26b22aac-00cd-403f-a237-3cc5829643bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888609048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3888609048
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3769736011
Short name T5
Test name
Test status
Simulation time 2064932154 ps
CPU time 6.57 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:47:58 PM PDT 24
Peak memory 210996 kb
Host smart-6add6115-c9f3-4d18-9610-3dfc269f81ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769736011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3769736011
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1554978651
Short name T64
Test name
Test status
Simulation time 4931190133 ps
CPU time 72.24 seconds
Started Jun 04 12:43:18 PM PDT 24
Finished Jun 04 12:44:31 PM PDT 24
Peak memory 213352 kb
Host smart-fd817d39-c55b-41fc-afc8-79bc6c2a4aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554978651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1554978651
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3191388635
Short name T131
Test name
Test status
Simulation time 54959557066 ps
CPU time 8824.85 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 03:15:16 PM PDT 24
Peak memory 235948 kb
Host smart-851ea64f-4f24-4b6b-adc1-da58490ed15d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191388635 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3191388635
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3136543358
Short name T19
Test name
Test status
Simulation time 126355943676 ps
CPU time 1143.46 seconds
Started Jun 04 12:48:07 PM PDT 24
Finished Jun 04 01:07:12 PM PDT 24
Peak memory 231700 kb
Host smart-5629fbd8-13a7-425e-ac07-7c9ea3494ed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136543358 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3136543358
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1052564822
Short name T10
Test name
Test status
Simulation time 7281125004 ps
CPU time 22.09 seconds
Started Jun 04 12:47:48 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 212496 kb
Host smart-fc3d31bb-dafe-498e-b931-f9aa4674ede0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052564822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1052564822
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.700501259
Short name T25
Test name
Test status
Simulation time 30028477735 ps
CPU time 34.46 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:37 PM PDT 24
Peak memory 211236 kb
Host smart-6c98b486-f8b9-4943-a254-bfae60957d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700501259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.700501259
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1166217343
Short name T16
Test name
Test status
Simulation time 139830998472 ps
CPU time 1989.03 seconds
Started Jun 04 12:47:50 PM PDT 24
Finished Jun 04 01:21:01 PM PDT 24
Peak memory 237064 kb
Host smart-bb57e0e2-b845-41f8-a3f8-0c7226d6f132
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166217343 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1166217343
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.948657346
Short name T116
Test name
Test status
Simulation time 1510013166 ps
CPU time 29.26 seconds
Started Jun 04 12:43:36 PM PDT 24
Finished Jun 04 12:44:06 PM PDT 24
Peak memory 211272 kb
Host smart-287fa764-d6eb-45b2-af92-389056a6e085
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948657346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.948657346
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.698800102
Short name T66
Test name
Test status
Simulation time 264834044 ps
CPU time 66.9 seconds
Started Jun 04 12:43:35 PM PDT 24
Finished Jun 04 12:44:43 PM PDT 24
Peak memory 212200 kb
Host smart-dcafe0dc-ac99-4cc3-83fb-a0dc5e18f8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698800102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.698800102
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4148654623
Short name T123
Test name
Test status
Simulation time 2058326098 ps
CPU time 38.61 seconds
Started Jun 04 12:43:17 PM PDT 24
Finished Jun 04 12:43:56 PM PDT 24
Peak memory 211156 kb
Host smart-f0f7166a-fcb0-4ae2-8ee3-fb138d1667e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148654623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4148654623
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3306912797
Short name T61
Test name
Test status
Simulation time 393856079 ps
CPU time 8.42 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:10 PM PDT 24
Peak memory 211000 kb
Host smart-5df5db72-2f25-4376-b965-20cc492077e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306912797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3306912797
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3834104802
Short name T95
Test name
Test status
Simulation time 15785528878 ps
CPU time 39.34 seconds
Started Jun 04 12:48:07 PM PDT 24
Finished Jun 04 12:48:47 PM PDT 24
Peak memory 215000 kb
Host smart-194f7d12-710b-4c4f-8210-86bd48198601
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834104802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3834104802
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3120380057
Short name T448
Test name
Test status
Simulation time 3507811329 ps
CPU time 14.13 seconds
Started Jun 04 12:43:00 PM PDT 24
Finished Jun 04 12:43:15 PM PDT 24
Peak memory 211228 kb
Host smart-856f9921-542e-415d-ab8b-11c7076dd5cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120380057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3120380057
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4087187797
Short name T397
Test name
Test status
Simulation time 2799148694 ps
CPU time 8.81 seconds
Started Jun 04 12:42:59 PM PDT 24
Finished Jun 04 12:43:08 PM PDT 24
Peak memory 211208 kb
Host smart-a7dfe1b3-834f-4d0f-9ab5-13d4124e3ffb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087187797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4087187797
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3727612459
Short name T443
Test name
Test status
Simulation time 5285421299 ps
CPU time 13.15 seconds
Started Jun 04 12:42:57 PM PDT 24
Finished Jun 04 12:43:11 PM PDT 24
Peak memory 211200 kb
Host smart-72ae5311-2d8d-4be9-82d0-2953c8c972da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727612459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3727612459
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.544603558
Short name T402
Test name
Test status
Simulation time 5981678028 ps
CPU time 15.3 seconds
Started Jun 04 12:42:59 PM PDT 24
Finished Jun 04 12:43:15 PM PDT 24
Peak memory 219444 kb
Host smart-f18a3e96-35d6-4130-8f30-afc6bfc9a52c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544603558 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.544603558
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4280646289
Short name T400
Test name
Test status
Simulation time 1106843644 ps
CPU time 11 seconds
Started Jun 04 12:42:56 PM PDT 24
Finished Jun 04 12:43:08 PM PDT 24
Peak memory 211120 kb
Host smart-e76c927e-e198-4a46-a178-18c264b32e61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280646289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4280646289
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.923027924
Short name T445
Test name
Test status
Simulation time 8581253935 ps
CPU time 13.17 seconds
Started Jun 04 12:43:00 PM PDT 24
Finished Jun 04 12:43:14 PM PDT 24
Peak memory 211024 kb
Host smart-1a80cd16-1055-4eba-8f98-af5188531c4f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923027924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.923027924
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1965393922
Short name T384
Test name
Test status
Simulation time 8838546639 ps
CPU time 16.01 seconds
Started Jun 04 12:42:59 PM PDT 24
Finished Jun 04 12:43:15 PM PDT 24
Peak memory 211084 kb
Host smart-d84dff0a-f4e6-4073-91ec-9d89548b7d77
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965393922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1965393922
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.618425184
Short name T456
Test name
Test status
Simulation time 4979959412 ps
CPU time 34.1 seconds
Started Jun 04 12:42:59 PM PDT 24
Finished Jun 04 12:43:34 PM PDT 24
Peak memory 211172 kb
Host smart-31f27d44-b24d-4ef6-bb66-315280fa5b80
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618425184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.618425184
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2642072396
Short name T79
Test name
Test status
Simulation time 801497075 ps
CPU time 10.57 seconds
Started Jun 04 12:42:59 PM PDT 24
Finished Jun 04 12:43:10 PM PDT 24
Peak memory 211176 kb
Host smart-b9382377-4cac-4c2f-936a-8e83f3eceac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642072396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2642072396
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.204911100
Short name T371
Test name
Test status
Simulation time 10965626784 ps
CPU time 12.36 seconds
Started Jun 04 12:42:57 PM PDT 24
Finished Jun 04 12:43:10 PM PDT 24
Peak memory 219460 kb
Host smart-cb5694cb-798f-4b21-b5f4-9ce05ae9ba32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204911100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.204911100
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4187931163
Short name T117
Test name
Test status
Simulation time 3070934273 ps
CPU time 40.25 seconds
Started Jun 04 12:42:57 PM PDT 24
Finished Jun 04 12:43:37 PM PDT 24
Peak memory 211760 kb
Host smart-a195dc09-c0c4-4fac-9426-0e1c3458a831
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187931163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4187931163
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.989573279
Short name T85
Test name
Test status
Simulation time 1027500170 ps
CPU time 7.42 seconds
Started Jun 04 12:43:08 PM PDT 24
Finished Jun 04 12:43:16 PM PDT 24
Peak memory 211248 kb
Host smart-5d106e6b-ff77-4cbf-a239-e8e396ed7477
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989573279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.989573279
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1924419510
Short name T446
Test name
Test status
Simulation time 85712023 ps
CPU time 4.73 seconds
Started Jun 04 12:43:10 PM PDT 24
Finished Jun 04 12:43:15 PM PDT 24
Peak memory 211120 kb
Host smart-92fb56d4-b81c-4b35-8cd6-6ae55b179b98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924419510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1924419510
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1200382958
Short name T78
Test name
Test status
Simulation time 2243435266 ps
CPU time 12.61 seconds
Started Jun 04 12:42:58 PM PDT 24
Finished Jun 04 12:43:12 PM PDT 24
Peak memory 211160 kb
Host smart-3d3800bf-3919-4db7-a363-c1df213b9843
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200382958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1200382958
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.282768689
Short name T399
Test name
Test status
Simulation time 11665614749 ps
CPU time 16.34 seconds
Started Jun 04 12:43:10 PM PDT 24
Finished Jun 04 12:43:27 PM PDT 24
Peak memory 219424 kb
Host smart-1827dd87-b4a1-47a6-ab0d-4b1e483a48ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282768689 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.282768689
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1510442040
Short name T405
Test name
Test status
Simulation time 4495783972 ps
CPU time 9.86 seconds
Started Jun 04 12:43:09 PM PDT 24
Finished Jun 04 12:43:19 PM PDT 24
Peak memory 211160 kb
Host smart-f8c8c1e5-0107-4b66-8cbb-027a718cc12b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510442040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1510442040
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1360047107
Short name T376
Test name
Test status
Simulation time 319986737 ps
CPU time 3.97 seconds
Started Jun 04 12:42:59 PM PDT 24
Finished Jun 04 12:43:03 PM PDT 24
Peak memory 211000 kb
Host smart-444873f6-069b-42aa-905a-9e44742d99c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360047107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1360047107
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2258282885
Short name T390
Test name
Test status
Simulation time 461412095 ps
CPU time 7.08 seconds
Started Jun 04 12:43:00 PM PDT 24
Finished Jun 04 12:43:08 PM PDT 24
Peak memory 211180 kb
Host smart-d452a2d4-fa27-4ab5-94c4-ff392fc576c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258282885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2258282885
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.993697305
Short name T396
Test name
Test status
Simulation time 36096452281 ps
CPU time 78.83 seconds
Started Jun 04 12:43:00 PM PDT 24
Finished Jun 04 12:44:20 PM PDT 24
Peak memory 211216 kb
Host smart-5c319a66-e00f-4d11-8d1c-4ae6636c32f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993697305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.993697305
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.550276011
Short name T77
Test name
Test status
Simulation time 6284840628 ps
CPU time 13.59 seconds
Started Jun 04 12:43:10 PM PDT 24
Finished Jun 04 12:43:24 PM PDT 24
Peak memory 211140 kb
Host smart-002af40b-e0b6-4a11-b6ad-8fbef6accf95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550276011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.550276011
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.316089564
Short name T457
Test name
Test status
Simulation time 1711663847 ps
CPU time 9.35 seconds
Started Jun 04 12:42:57 PM PDT 24
Finished Jun 04 12:43:07 PM PDT 24
Peak memory 219400 kb
Host smart-e8b0d0f1-3ccc-4cda-8ad8-dbbe3fff3509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316089564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.316089564
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4135826586
Short name T124
Test name
Test status
Simulation time 1186347212 ps
CPU time 70.53 seconds
Started Jun 04 12:42:59 PM PDT 24
Finished Jun 04 12:44:10 PM PDT 24
Peak memory 219336 kb
Host smart-8c0209c4-fa17-4561-a76a-427793f4f546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135826586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4135826586
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4183350387
Short name T458
Test name
Test status
Simulation time 612735433 ps
CPU time 9.57 seconds
Started Jun 04 12:43:35 PM PDT 24
Finished Jun 04 12:43:46 PM PDT 24
Peak memory 219364 kb
Host smart-8006544a-2bea-431e-b2be-45289c58d2e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183350387 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4183350387
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.482654515
Short name T73
Test name
Test status
Simulation time 1102114305 ps
CPU time 10.9 seconds
Started Jun 04 12:43:36 PM PDT 24
Finished Jun 04 12:43:47 PM PDT 24
Peak memory 211132 kb
Host smart-52a2a5a3-99a5-4298-84c9-d14199034221
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482654515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.482654515
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.162907024
Short name T419
Test name
Test status
Simulation time 8943928241 ps
CPU time 16.64 seconds
Started Jun 04 12:43:34 PM PDT 24
Finished Jun 04 12:43:52 PM PDT 24
Peak memory 211196 kb
Host smart-a8bf7842-6d24-4b1f-8120-ff7514576bce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162907024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.162907024
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1814946370
Short name T423
Test name
Test status
Simulation time 318187896 ps
CPU time 7.15 seconds
Started Jun 04 12:43:37 PM PDT 24
Finished Jun 04 12:43:45 PM PDT 24
Peak memory 219356 kb
Host smart-ebec794c-17fb-4f58-94c3-316b98df2134
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814946370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1814946370
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2294983669
Short name T422
Test name
Test status
Simulation time 9036282623 ps
CPU time 40.53 seconds
Started Jun 04 12:43:36 PM PDT 24
Finished Jun 04 12:44:17 PM PDT 24
Peak memory 211992 kb
Host smart-55b79bd6-9b35-4ecd-aba1-9e37f24b1d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294983669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2294983669
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1936811890
Short name T68
Test name
Test status
Simulation time 2360998166 ps
CPU time 9.04 seconds
Started Jun 04 12:43:37 PM PDT 24
Finished Jun 04 12:43:47 PM PDT 24
Peak memory 219416 kb
Host smart-4619303d-225b-4bc4-a00b-9d806e735cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936811890 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1936811890
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2146997350
Short name T394
Test name
Test status
Simulation time 6435584698 ps
CPU time 14.38 seconds
Started Jun 04 12:43:37 PM PDT 24
Finished Jun 04 12:43:52 PM PDT 24
Peak memory 211188 kb
Host smart-8090b861-c853-4425-886a-c54a7e9827f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146997350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2146997350
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1690450505
Short name T109
Test name
Test status
Simulation time 21130076974 ps
CPU time 49.9 seconds
Started Jun 04 12:43:38 PM PDT 24
Finished Jun 04 12:44:29 PM PDT 24
Peak memory 211236 kb
Host smart-a19e3e89-3ce8-4271-b4f7-a1c239c47c8b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690450505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1690450505
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3677018794
Short name T110
Test name
Test status
Simulation time 6681066495 ps
CPU time 12.48 seconds
Started Jun 04 12:43:36 PM PDT 24
Finished Jun 04 12:43:49 PM PDT 24
Peak memory 211164 kb
Host smart-91a98491-28c9-4f6f-a60c-df66b9f0a4fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677018794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3677018794
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1362531966
Short name T426
Test name
Test status
Simulation time 1263843573 ps
CPU time 10.28 seconds
Started Jun 04 12:43:34 PM PDT 24
Finished Jun 04 12:43:45 PM PDT 24
Peak memory 219408 kb
Host smart-ab6562a7-e87a-4310-b376-fee55e337d7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362531966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1362531966
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1175984556
Short name T444
Test name
Test status
Simulation time 5880521387 ps
CPU time 12.51 seconds
Started Jun 04 12:43:36 PM PDT 24
Finished Jun 04 12:43:49 PM PDT 24
Peak memory 219412 kb
Host smart-8650d133-f996-485f-974f-b48d8ec300ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175984556 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1175984556
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.106853775
Short name T414
Test name
Test status
Simulation time 1707384757 ps
CPU time 9.37 seconds
Started Jun 04 12:43:35 PM PDT 24
Finished Jun 04 12:43:45 PM PDT 24
Peak memory 211120 kb
Host smart-fa8df12c-9691-4393-ba3c-9cafd4073eb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106853775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.106853775
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4145509349
Short name T461
Test name
Test status
Simulation time 9392308709 ps
CPU time 81.11 seconds
Started Jun 04 12:43:36 PM PDT 24
Finished Jun 04 12:44:58 PM PDT 24
Peak memory 212260 kb
Host smart-2b63107c-928b-4aa8-b1fc-5a691043c5fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145509349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4145509349
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3118993362
Short name T421
Test name
Test status
Simulation time 2620880991 ps
CPU time 12.05 seconds
Started Jun 04 12:43:37 PM PDT 24
Finished Jun 04 12:43:49 PM PDT 24
Peak memory 211184 kb
Host smart-66944f63-bf9c-4fe4-b825-7992ce786cad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118993362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3118993362
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1350368334
Short name T374
Test name
Test status
Simulation time 1711330623 ps
CPU time 11.03 seconds
Started Jun 04 12:43:36 PM PDT 24
Finished Jun 04 12:43:47 PM PDT 24
Peak memory 219404 kb
Host smart-25dd61c6-06f7-476a-b462-8dd86b7e282c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350368334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1350368334
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2135698893
Short name T127
Test name
Test status
Simulation time 11073237551 ps
CPU time 72.97 seconds
Started Jun 04 12:43:38 PM PDT 24
Finished Jun 04 12:44:52 PM PDT 24
Peak memory 219384 kb
Host smart-dd6428f1-35de-4de6-a0a2-09d890a357e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135698893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2135698893
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2016596921
Short name T418
Test name
Test status
Simulation time 5034039064 ps
CPU time 11.64 seconds
Started Jun 04 12:43:34 PM PDT 24
Finished Jun 04 12:43:47 PM PDT 24
Peak memory 219456 kb
Host smart-65ffec37-dacf-4203-abb2-e4d64f296da9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016596921 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2016596921
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1384437650
Short name T427
Test name
Test status
Simulation time 1303655474 ps
CPU time 7.76 seconds
Started Jun 04 12:43:39 PM PDT 24
Finished Jun 04 12:43:47 PM PDT 24
Peak memory 211152 kb
Host smart-86ce1757-fb36-4e5e-b3ea-ee7cce3a516d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384437650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1384437650
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2259837427
Short name T463
Test name
Test status
Simulation time 7048378308 ps
CPU time 57.67 seconds
Started Jun 04 12:43:36 PM PDT 24
Finished Jun 04 12:44:34 PM PDT 24
Peak memory 212268 kb
Host smart-fff5fad6-02f5-4b99-93b1-8491d14787e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259837427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2259837427
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1085345862
Short name T429
Test name
Test status
Simulation time 168482023 ps
CPU time 4.53 seconds
Started Jun 04 12:43:37 PM PDT 24
Finished Jun 04 12:43:42 PM PDT 24
Peak memory 211160 kb
Host smart-162affa1-5abd-4927-8e60-e0a8515f99dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085345862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1085345862
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1502078489
Short name T417
Test name
Test status
Simulation time 3184163472 ps
CPU time 17.96 seconds
Started Jun 04 12:43:34 PM PDT 24
Finished Jun 04 12:43:53 PM PDT 24
Peak memory 219404 kb
Host smart-19158356-1b0e-4cac-ac06-5977efe5572d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502078489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1502078489
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3208394861
Short name T121
Test name
Test status
Simulation time 1127697956 ps
CPU time 71.46 seconds
Started Jun 04 12:43:38 PM PDT 24
Finished Jun 04 12:44:50 PM PDT 24
Peak memory 211984 kb
Host smart-37e5dd02-7418-4a8e-bf21-9661977045b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208394861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3208394861
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1331175602
Short name T447
Test name
Test status
Simulation time 3737292409 ps
CPU time 9.84 seconds
Started Jun 04 12:43:47 PM PDT 24
Finished Jun 04 12:43:57 PM PDT 24
Peak memory 213756 kb
Host smart-4880c446-0afc-4305-a5c9-324d83292c07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331175602 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1331175602
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1437378669
Short name T108
Test name
Test status
Simulation time 88112547 ps
CPU time 4.21 seconds
Started Jun 04 12:43:46 PM PDT 24
Finished Jun 04 12:43:51 PM PDT 24
Peak memory 211072 kb
Host smart-6d4e04a5-c9e2-4131-bc6e-84203e3b9ba2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437378669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1437378669
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2304307048
Short name T111
Test name
Test status
Simulation time 13817301766 ps
CPU time 39.42 seconds
Started Jun 04 12:43:35 PM PDT 24
Finished Jun 04 12:44:15 PM PDT 24
Peak memory 211328 kb
Host smart-5b9c19e4-835e-4101-b468-638b9c02b5c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304307048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2304307048
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.206669575
Short name T439
Test name
Test status
Simulation time 399407352 ps
CPU time 6 seconds
Started Jun 04 12:43:46 PM PDT 24
Finished Jun 04 12:43:52 PM PDT 24
Peak memory 211168 kb
Host smart-7bcb474e-94b1-4e85-a115-2900854c58ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206669575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.206669575
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1846217777
Short name T404
Test name
Test status
Simulation time 2645302503 ps
CPU time 15.73 seconds
Started Jun 04 12:43:35 PM PDT 24
Finished Jun 04 12:43:51 PM PDT 24
Peak memory 219396 kb
Host smart-d16e52f2-6e0b-43a0-b9ef-62f5160d8b73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846217777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1846217777
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2240774116
Short name T128
Test name
Test status
Simulation time 5065124520 ps
CPU time 42.19 seconds
Started Jun 04 12:43:46 PM PDT 24
Finished Jun 04 12:44:29 PM PDT 24
Peak memory 211968 kb
Host smart-89d3f1e3-eab9-4e46-811f-aea265834e2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240774116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2240774116
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3061811331
Short name T375
Test name
Test status
Simulation time 1186978704 ps
CPU time 11.57 seconds
Started Jun 04 12:43:45 PM PDT 24
Finished Jun 04 12:43:58 PM PDT 24
Peak memory 219508 kb
Host smart-274604ec-bbaf-402f-975b-5f09519a99d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061811331 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3061811331
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2770625776
Short name T432
Test name
Test status
Simulation time 1164729451 ps
CPU time 10.94 seconds
Started Jun 04 12:43:45 PM PDT 24
Finished Jun 04 12:43:56 PM PDT 24
Peak memory 211180 kb
Host smart-7950267b-bd99-48bd-8f87-5437f6050978
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770625776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2770625776
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.956266180
Short name T413
Test name
Test status
Simulation time 680736796 ps
CPU time 8.95 seconds
Started Jun 04 12:43:44 PM PDT 24
Finished Jun 04 12:43:54 PM PDT 24
Peak memory 211160 kb
Host smart-b0304966-5f5b-46da-a668-d1dfbc91c11c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956266180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.956266180
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1217524117
Short name T378
Test name
Test status
Simulation time 3628717101 ps
CPU time 14.42 seconds
Started Jun 04 12:43:49 PM PDT 24
Finished Jun 04 12:44:03 PM PDT 24
Peak memory 219436 kb
Host smart-2e352733-8937-4336-8313-2bac95b9db6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217524117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1217524117
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4185867700
Short name T420
Test name
Test status
Simulation time 1587566433 ps
CPU time 44.82 seconds
Started Jun 04 12:43:46 PM PDT 24
Finished Jun 04 12:44:32 PM PDT 24
Peak memory 219336 kb
Host smart-feb311b6-a78d-4a4d-a05d-165ce7f289ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185867700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4185867700
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1930245169
Short name T385
Test name
Test status
Simulation time 3271272556 ps
CPU time 17.38 seconds
Started Jun 04 12:43:46 PM PDT 24
Finished Jun 04 12:44:04 PM PDT 24
Peak memory 214428 kb
Host smart-047848c6-0421-4cf1-b4c6-3061e485120b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930245169 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1930245169
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3477391217
Short name T382
Test name
Test status
Simulation time 1737062807 ps
CPU time 13.9 seconds
Started Jun 04 12:43:48 PM PDT 24
Finished Jun 04 12:44:03 PM PDT 24
Peak memory 211120 kb
Host smart-7e8e6f49-e01f-4df9-8ebd-265313adf6d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477391217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3477391217
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.977581225
Short name T72
Test name
Test status
Simulation time 144697562402 ps
CPU time 96.59 seconds
Started Jun 04 12:43:45 PM PDT 24
Finished Jun 04 12:45:22 PM PDT 24
Peak memory 212204 kb
Host smart-cf9127ab-c152-4e45-88a1-791261ec433b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977581225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.977581225
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3672704068
Short name T452
Test name
Test status
Simulation time 1479825689 ps
CPU time 6.74 seconds
Started Jun 04 12:43:47 PM PDT 24
Finished Jun 04 12:43:54 PM PDT 24
Peak memory 211196 kb
Host smart-49518908-2cfe-47a9-b5d5-1d4f32c5957a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672704068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3672704068
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.966268658
Short name T388
Test name
Test status
Simulation time 120916103 ps
CPU time 8.16 seconds
Started Jun 04 12:43:46 PM PDT 24
Finished Jun 04 12:43:54 PM PDT 24
Peak memory 219520 kb
Host smart-29f4b52d-c91d-4b8d-94c6-17218de2d2c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966268658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.966268658
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3274042828
Short name T393
Test name
Test status
Simulation time 5082967979 ps
CPU time 44.74 seconds
Started Jun 04 12:43:45 PM PDT 24
Finished Jun 04 12:44:30 PM PDT 24
Peak memory 212392 kb
Host smart-6ee5ef4d-9acf-4437-ba1b-2008c3fba024
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274042828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3274042828
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3993235327
Short name T383
Test name
Test status
Simulation time 1780976822 ps
CPU time 8.16 seconds
Started Jun 04 12:43:48 PM PDT 24
Finished Jun 04 12:43:57 PM PDT 24
Peak memory 219364 kb
Host smart-9625680d-5636-4635-b922-7fd42f37d143
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993235327 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3993235327
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2908346715
Short name T460
Test name
Test status
Simulation time 167825221 ps
CPU time 4.32 seconds
Started Jun 04 12:43:47 PM PDT 24
Finished Jun 04 12:43:52 PM PDT 24
Peak memory 211196 kb
Host smart-cac6d0a3-840d-408f-80cb-62a1d6d00554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908346715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2908346715
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3512115009
Short name T465
Test name
Test status
Simulation time 47170994972 ps
CPU time 89.9 seconds
Started Jun 04 12:43:44 PM PDT 24
Finished Jun 04 12:45:14 PM PDT 24
Peak memory 211248 kb
Host smart-ceadb219-e38c-44b3-a666-ba518817546e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512115009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3512115009
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2150129548
Short name T430
Test name
Test status
Simulation time 90079792 ps
CPU time 4.27 seconds
Started Jun 04 12:43:45 PM PDT 24
Finished Jun 04 12:43:51 PM PDT 24
Peak memory 211160 kb
Host smart-5824f3d9-8166-4319-98b9-d3079f234e42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150129548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2150129548
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1570137768
Short name T412
Test name
Test status
Simulation time 894953913 ps
CPU time 11.81 seconds
Started Jun 04 12:43:45 PM PDT 24
Finished Jun 04 12:43:57 PM PDT 24
Peak memory 219380 kb
Host smart-4c76ee96-3cc0-4a7e-9a11-c0a3ab3b88b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570137768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1570137768
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3683764050
Short name T126
Test name
Test status
Simulation time 1074172095 ps
CPU time 40.87 seconds
Started Jun 04 12:43:45 PM PDT 24
Finished Jun 04 12:44:27 PM PDT 24
Peak memory 219416 kb
Host smart-543e8945-11f2-4079-bdfa-b8a08d794bde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683764050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3683764050
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.232031018
Short name T464
Test name
Test status
Simulation time 2771251752 ps
CPU time 12.24 seconds
Started Jun 04 12:43:55 PM PDT 24
Finished Jun 04 12:44:08 PM PDT 24
Peak memory 213512 kb
Host smart-46e30028-70be-4a62-8b95-651037577cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232031018 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.232031018
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4101935318
Short name T410
Test name
Test status
Simulation time 885739861 ps
CPU time 9.77 seconds
Started Jun 04 12:43:57 PM PDT 24
Finished Jun 04 12:44:07 PM PDT 24
Peak memory 211140 kb
Host smart-ad931702-edc6-426a-9362-ca75c5b76435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101935318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4101935318
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1328237222
Short name T450
Test name
Test status
Simulation time 11866756795 ps
CPU time 64.05 seconds
Started Jun 04 12:43:46 PM PDT 24
Finished Jun 04 12:44:51 PM PDT 24
Peak memory 211208 kb
Host smart-cc4dc758-bfc0-44c5-b1cd-2923c903a273
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328237222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1328237222
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3909011520
Short name T455
Test name
Test status
Simulation time 15683228471 ps
CPU time 14.52 seconds
Started Jun 04 12:43:54 PM PDT 24
Finished Jun 04 12:44:09 PM PDT 24
Peak memory 211152 kb
Host smart-2f5ded00-999e-4e2e-aa29-58ffd18075ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909011520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3909011520
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.815268671
Short name T441
Test name
Test status
Simulation time 3430506939 ps
CPU time 12.05 seconds
Started Jun 04 12:43:46 PM PDT 24
Finished Jun 04 12:43:58 PM PDT 24
Peak memory 214564 kb
Host smart-74e9159c-198d-43ff-bf73-e3a15dac24e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815268671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.815268671
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1608852025
Short name T120
Test name
Test status
Simulation time 3845564096 ps
CPU time 76.07 seconds
Started Jun 04 12:43:54 PM PDT 24
Finished Jun 04 12:45:11 PM PDT 24
Peak memory 212048 kb
Host smart-2890871d-c0b3-47be-9443-81a529c66ff6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608852025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1608852025
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4173836146
Short name T368
Test name
Test status
Simulation time 515782113 ps
CPU time 8 seconds
Started Jun 04 12:43:53 PM PDT 24
Finished Jun 04 12:44:02 PM PDT 24
Peak memory 219364 kb
Host smart-7a2e463a-2b82-4899-9244-afaf8c2df2d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173836146 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4173836146
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2733503839
Short name T438
Test name
Test status
Simulation time 499521673 ps
CPU time 7.34 seconds
Started Jun 04 12:43:54 PM PDT 24
Finished Jun 04 12:44:02 PM PDT 24
Peak memory 211120 kb
Host smart-908d05cc-80e0-4262-b660-6613d66e89ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733503839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2733503839
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1906163666
Short name T94
Test name
Test status
Simulation time 29038973736 ps
CPU time 59.47 seconds
Started Jun 04 12:43:56 PM PDT 24
Finished Jun 04 12:44:56 PM PDT 24
Peak memory 211336 kb
Host smart-13c43d87-6661-48b9-b59f-d27c3693e75d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906163666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1906163666
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2860511186
Short name T106
Test name
Test status
Simulation time 7797500123 ps
CPU time 15.46 seconds
Started Jun 04 12:43:55 PM PDT 24
Finished Jun 04 12:44:11 PM PDT 24
Peak memory 211216 kb
Host smart-74b117b5-65f8-46f8-9938-cb8ca7303adc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860511186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2860511186
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3075077344
Short name T387
Test name
Test status
Simulation time 1583844582 ps
CPU time 16.66 seconds
Started Jun 04 12:43:54 PM PDT 24
Finished Jun 04 12:44:11 PM PDT 24
Peak memory 219404 kb
Host smart-d6e5643b-7fce-4d6a-b1d3-04e4b900151d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075077344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3075077344
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1270067026
Short name T436
Test name
Test status
Simulation time 765327399 ps
CPU time 35.9 seconds
Started Jun 04 12:43:53 PM PDT 24
Finished Jun 04 12:44:30 PM PDT 24
Peak memory 211228 kb
Host smart-dee6237f-5dd7-4b7c-8cc7-b24635cafeca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270067026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1270067026
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2502712593
Short name T90
Test name
Test status
Simulation time 7350628232 ps
CPU time 14.05 seconds
Started Jun 04 12:43:08 PM PDT 24
Finished Jun 04 12:43:22 PM PDT 24
Peak memory 211316 kb
Host smart-72dc496f-ba21-40e2-a3c7-7cc865df30b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502712593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2502712593
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2377780232
Short name T440
Test name
Test status
Simulation time 1596407375 ps
CPU time 13.53 seconds
Started Jun 04 12:43:09 PM PDT 24
Finished Jun 04 12:43:23 PM PDT 24
Peak memory 211244 kb
Host smart-a02a69ef-3277-40fc-9403-29a86105f772
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377780232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2377780232
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3255670533
Short name T75
Test name
Test status
Simulation time 3482133106 ps
CPU time 13.64 seconds
Started Jun 04 12:43:09 PM PDT 24
Finished Jun 04 12:43:23 PM PDT 24
Peak memory 211216 kb
Host smart-4d2cca99-860e-4705-ae94-f5f36f7e1c70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255670533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3255670533
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4154655549
Short name T435
Test name
Test status
Simulation time 2798148040 ps
CPU time 12.78 seconds
Started Jun 04 12:43:08 PM PDT 24
Finished Jun 04 12:43:22 PM PDT 24
Peak memory 219456 kb
Host smart-3c39aaaf-4fc0-4de1-b531-e13fc569bebe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154655549 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4154655549
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.701991929
Short name T454
Test name
Test status
Simulation time 2022077931 ps
CPU time 14.7 seconds
Started Jun 04 12:43:09 PM PDT 24
Finished Jun 04 12:43:24 PM PDT 24
Peak memory 211164 kb
Host smart-a249f201-3571-43a8-932c-295beafb13ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701991929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.701991929
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2077629000
Short name T416
Test name
Test status
Simulation time 3513570171 ps
CPU time 14.01 seconds
Started Jun 04 12:43:10 PM PDT 24
Finished Jun 04 12:43:25 PM PDT 24
Peak memory 211184 kb
Host smart-1a86c306-ab2a-4802-997b-6c5c7708a5d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077629000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2077629000
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.232910748
Short name T453
Test name
Test status
Simulation time 940623648 ps
CPU time 9.67 seconds
Started Jun 04 12:43:09 PM PDT 24
Finished Jun 04 12:43:19 PM PDT 24
Peak memory 211052 kb
Host smart-f6638b7b-6e25-4fc4-8797-bf8f97f364d0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232910748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
232910748
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2123300926
Short name T87
Test name
Test status
Simulation time 2110305328 ps
CPU time 31.81 seconds
Started Jun 04 12:43:10 PM PDT 24
Finished Jun 04 12:43:43 PM PDT 24
Peak memory 211152 kb
Host smart-ac91ed20-7c51-4bc5-b952-3131b9ce7d44
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123300926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2123300926
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1368666961
Short name T437
Test name
Test status
Simulation time 1436531450 ps
CPU time 14.03 seconds
Started Jun 04 12:43:07 PM PDT 24
Finished Jun 04 12:43:21 PM PDT 24
Peak memory 211272 kb
Host smart-6e2d1704-04ab-4a15-becf-eec3c088f392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368666961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1368666961
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1069623213
Short name T407
Test name
Test status
Simulation time 1355277179 ps
CPU time 14.54 seconds
Started Jun 04 12:43:07 PM PDT 24
Finished Jun 04 12:43:22 PM PDT 24
Peak memory 219524 kb
Host smart-2e0ccf10-0d93-4408-b7e3-b22626ae6ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069623213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1069623213
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.121365553
Short name T91
Test name
Test status
Simulation time 8148808101 ps
CPU time 15.49 seconds
Started Jun 04 12:43:19 PM PDT 24
Finished Jun 04 12:43:35 PM PDT 24
Peak memory 211220 kb
Host smart-50976365-c75d-4efe-b860-5fe545e3db65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121365553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.121365553
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2495601210
Short name T428
Test name
Test status
Simulation time 172007469 ps
CPU time 4.55 seconds
Started Jun 04 12:43:18 PM PDT 24
Finished Jun 04 12:43:23 PM PDT 24
Peak memory 211200 kb
Host smart-01ba1538-a50a-48db-bbc7-727709d01687
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495601210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2495601210
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2844231439
Short name T451
Test name
Test status
Simulation time 627115760 ps
CPU time 7.36 seconds
Started Jun 04 12:43:18 PM PDT 24
Finished Jun 04 12:43:26 PM PDT 24
Peak memory 211244 kb
Host smart-8c83c883-6e1b-47b7-8a51-1ce53777c23a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844231439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2844231439
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2023529784
Short name T449
Test name
Test status
Simulation time 2104919302 ps
CPU time 15.8 seconds
Started Jun 04 12:43:22 PM PDT 24
Finished Jun 04 12:43:39 PM PDT 24
Peak memory 219380 kb
Host smart-bd663eff-21a3-4f75-b2d9-81b2793fec2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023529784 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2023529784
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2664506103
Short name T389
Test name
Test status
Simulation time 4201479064 ps
CPU time 16.1 seconds
Started Jun 04 12:43:17 PM PDT 24
Finished Jun 04 12:43:34 PM PDT 24
Peak memory 211256 kb
Host smart-f0ae6de2-314e-4342-aa38-dc110e6e7836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664506103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2664506103
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.186541776
Short name T380
Test name
Test status
Simulation time 1109226208 ps
CPU time 10.9 seconds
Started Jun 04 12:43:18 PM PDT 24
Finished Jun 04 12:43:30 PM PDT 24
Peak memory 210956 kb
Host smart-7118e41c-6483-4a1b-96b7-1c9d04ff0680
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186541776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.186541776
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4121092993
Short name T373
Test name
Test status
Simulation time 823796702 ps
CPU time 6.81 seconds
Started Jun 04 12:43:21 PM PDT 24
Finished Jun 04 12:43:28 PM PDT 24
Peak memory 211056 kb
Host smart-aa664228-fef8-48b3-8994-425876fd2654
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121092993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4121092993
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.148320651
Short name T92
Test name
Test status
Simulation time 377823143 ps
CPU time 18.82 seconds
Started Jun 04 12:43:18 PM PDT 24
Finished Jun 04 12:43:37 PM PDT 24
Peak memory 211128 kb
Host smart-42cb0185-3015-46ce-aa04-b3e428d6c2e3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148320651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.148320651
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3605547577
Short name T434
Test name
Test status
Simulation time 955941627 ps
CPU time 10.19 seconds
Started Jun 04 12:43:17 PM PDT 24
Finished Jun 04 12:43:27 PM PDT 24
Peak memory 211228 kb
Host smart-513d6868-39e7-4bf2-973c-fd79bb62c91f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605547577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3605547577
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3999039608
Short name T406
Test name
Test status
Simulation time 537861378 ps
CPU time 11.94 seconds
Started Jun 04 12:43:17 PM PDT 24
Finished Jun 04 12:43:30 PM PDT 24
Peak memory 215760 kb
Host smart-47e1294b-7b41-4776-a50f-d02506d0f5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999039608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3999039608
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2449469974
Short name T89
Test name
Test status
Simulation time 4252393325 ps
CPU time 10.48 seconds
Started Jun 04 12:43:22 PM PDT 24
Finished Jun 04 12:43:33 PM PDT 24
Peak memory 211192 kb
Host smart-d86f54b6-d7dc-4743-88cb-84e877ccfde2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449469974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2449469974
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1370252432
Short name T369
Test name
Test status
Simulation time 1205674211 ps
CPU time 11.18 seconds
Started Jun 04 12:43:17 PM PDT 24
Finished Jun 04 12:43:29 PM PDT 24
Peak memory 211120 kb
Host smart-1612d903-e0c2-4e05-adfd-957d55aafe1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370252432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1370252432
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1206315934
Short name T415
Test name
Test status
Simulation time 10110971308 ps
CPU time 17.89 seconds
Started Jun 04 12:43:22 PM PDT 24
Finished Jun 04 12:43:40 PM PDT 24
Peak memory 211236 kb
Host smart-319c11c6-6335-49d1-9284-154453a7dbeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206315934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1206315934
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.104197386
Short name T392
Test name
Test status
Simulation time 812428522 ps
CPU time 6.29 seconds
Started Jun 04 12:43:19 PM PDT 24
Finished Jun 04 12:43:26 PM PDT 24
Peak memory 219488 kb
Host smart-382cbe0d-c1dd-4452-a8b5-a1dbf1e5237a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104197386 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.104197386
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3265453786
Short name T112
Test name
Test status
Simulation time 346295371 ps
CPU time 4.09 seconds
Started Jun 04 12:43:21 PM PDT 24
Finished Jun 04 12:43:26 PM PDT 24
Peak memory 211172 kb
Host smart-299925d0-0f92-4cba-877e-8f5cdd78bde3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265453786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3265453786
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1452424494
Short name T381
Test name
Test status
Simulation time 3757045030 ps
CPU time 9.41 seconds
Started Jun 04 12:43:16 PM PDT 24
Finished Jun 04 12:43:26 PM PDT 24
Peak memory 211036 kb
Host smart-c97fe75f-2d94-4daa-bd8a-0630dda3911e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452424494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1452424494
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1537485975
Short name T409
Test name
Test status
Simulation time 4096633789 ps
CPU time 10.27 seconds
Started Jun 04 12:43:21 PM PDT 24
Finished Jun 04 12:43:32 PM PDT 24
Peak memory 211168 kb
Host smart-18b5ec00-935a-4450-8a85-e71431075511
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537485975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1537485975
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4113190997
Short name T459
Test name
Test status
Simulation time 2514245657 ps
CPU time 44.03 seconds
Started Jun 04 12:43:21 PM PDT 24
Finished Jun 04 12:44:06 PM PDT 24
Peak memory 211188 kb
Host smart-d7bafa8e-039f-4730-b789-3b063319e4fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113190997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.4113190997
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1985677547
Short name T408
Test name
Test status
Simulation time 7854036418 ps
CPU time 16.55 seconds
Started Jun 04 12:43:17 PM PDT 24
Finished Jun 04 12:43:34 PM PDT 24
Peak memory 211220 kb
Host smart-0f4f110e-97d2-4299-b6fc-88f2f463e793
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985677547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1985677547
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4234199114
Short name T379
Test name
Test status
Simulation time 2873032640 ps
CPU time 16.06 seconds
Started Jun 04 12:43:18 PM PDT 24
Finished Jun 04 12:43:35 PM PDT 24
Peak memory 219552 kb
Host smart-89ab4b46-afe9-4ca4-8cbe-fb328cb9ca9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234199114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4234199114
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3638974655
Short name T442
Test name
Test status
Simulation time 387021577 ps
CPU time 5.32 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:43:32 PM PDT 24
Peak memory 219504 kb
Host smart-a4ddd99f-261d-4865-b3cc-283511dc6c74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638974655 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3638974655
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3775956241
Short name T74
Test name
Test status
Simulation time 1060854753 ps
CPU time 10.6 seconds
Started Jun 04 12:43:31 PM PDT 24
Finished Jun 04 12:43:42 PM PDT 24
Peak memory 211116 kb
Host smart-8b219f57-6007-4a52-8858-2d542702742e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775956241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3775956241
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.416528540
Short name T93
Test name
Test status
Simulation time 9991111660 ps
CPU time 86.08 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:44:51 PM PDT 24
Peak memory 211224 kb
Host smart-c0f4da17-ce2b-400c-8e65-13835fdc01ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416528540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.416528540
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1054300639
Short name T107
Test name
Test status
Simulation time 1623074427 ps
CPU time 14.95 seconds
Started Jun 04 12:43:28 PM PDT 24
Finished Jun 04 12:43:43 PM PDT 24
Peak memory 211272 kb
Host smart-c90bafef-6cde-4ae8-b049-308715a7055f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054300639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1054300639
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2042465728
Short name T386
Test name
Test status
Simulation time 2047237228 ps
CPU time 9.4 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:43:35 PM PDT 24
Peak memory 219368 kb
Host smart-4a62c6e5-4cf5-4c3e-82c8-a17f15f1076d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042465728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2042465728
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.702466571
Short name T433
Test name
Test status
Simulation time 6168791615 ps
CPU time 75.93 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:44:42 PM PDT 24
Peak memory 211432 kb
Host smart-12393882-2e9d-4d9e-bd1b-e0158e03000d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702466571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.702466571
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2063009361
Short name T370
Test name
Test status
Simulation time 7018592189 ps
CPU time 14.68 seconds
Started Jun 04 12:43:26 PM PDT 24
Finished Jun 04 12:43:42 PM PDT 24
Peak memory 211692 kb
Host smart-b9087a4d-38d0-47ee-93e0-be2e195c717f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063009361 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2063009361
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.30264854
Short name T391
Test name
Test status
Simulation time 321551544 ps
CPU time 4.32 seconds
Started Jun 04 12:43:26 PM PDT 24
Finished Jun 04 12:43:32 PM PDT 24
Peak memory 211440 kb
Host smart-5ed0ecae-650c-43e0-8e12-5890b40e758e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30264854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.30264854
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.924784801
Short name T86
Test name
Test status
Simulation time 8734075095 ps
CPU time 42.78 seconds
Started Jun 04 12:43:31 PM PDT 24
Finished Jun 04 12:44:14 PM PDT 24
Peak memory 211208 kb
Host smart-fb4b4ee1-fd71-468d-9db9-a553ca382c1b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924784801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.924784801
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3408764414
Short name T69
Test name
Test status
Simulation time 22815128744 ps
CPU time 13.47 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:43:39 PM PDT 24
Peak memory 211160 kb
Host smart-36d0dace-fca7-4add-bd65-f1bbe40d2e39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408764414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3408764414
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1639692200
Short name T403
Test name
Test status
Simulation time 1023376194 ps
CPU time 14.36 seconds
Started Jun 04 12:43:29 PM PDT 24
Finished Jun 04 12:43:44 PM PDT 24
Peak memory 219516 kb
Host smart-dedb8aa5-fc8d-4441-9e6b-65e19e210b55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639692200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1639692200
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.230758567
Short name T118
Test name
Test status
Simulation time 1312898674 ps
CPU time 75.79 seconds
Started Jun 04 12:43:27 PM PDT 24
Finished Jun 04 12:44:44 PM PDT 24
Peak memory 213208 kb
Host smart-7b157e9f-2193-41b8-be2c-bfd976f6dafc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230758567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.230758567
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1515192684
Short name T401
Test name
Test status
Simulation time 550549822 ps
CPU time 7.05 seconds
Started Jun 04 12:43:26 PM PDT 24
Finished Jun 04 12:43:35 PM PDT 24
Peak memory 219360 kb
Host smart-25907dad-f444-4f54-9d4e-8899fcaf46e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515192684 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1515192684
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1299512763
Short name T88
Test name
Test status
Simulation time 917657042 ps
CPU time 7.17 seconds
Started Jun 04 12:43:26 PM PDT 24
Finished Jun 04 12:43:34 PM PDT 24
Peak memory 211120 kb
Host smart-545a6c47-e24c-4d3d-8392-4f53db198117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299512763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1299512763
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.223133260
Short name T113
Test name
Test status
Simulation time 1509028873 ps
CPU time 18.77 seconds
Started Jun 04 12:43:26 PM PDT 24
Finished Jun 04 12:43:45 PM PDT 24
Peak memory 219296 kb
Host smart-b3a08fd9-fc17-46e3-adce-2844ce0688e4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223133260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.223133260
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.259349799
Short name T462
Test name
Test status
Simulation time 3000716435 ps
CPU time 13.2 seconds
Started Jun 04 12:43:26 PM PDT 24
Finished Jun 04 12:43:40 PM PDT 24
Peak memory 211172 kb
Host smart-1b77e0a0-e251-4fb6-b6c9-0ad86e51caa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259349799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.259349799
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2341158419
Short name T395
Test name
Test status
Simulation time 118951290 ps
CPU time 8.53 seconds
Started Jun 04 12:43:26 PM PDT 24
Finished Jun 04 12:43:35 PM PDT 24
Peak memory 219364 kb
Host smart-34851872-98b0-4792-b307-a9612cba0b15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341158419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2341158419
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2739370874
Short name T125
Test name
Test status
Simulation time 5454839846 ps
CPU time 41.38 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:44:07 PM PDT 24
Peak memory 212284 kb
Host smart-2d2ca44a-f813-423a-b7de-d39570d2e435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739370874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2739370874
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3531327692
Short name T431
Test name
Test status
Simulation time 92996141 ps
CPU time 4.64 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:43:31 PM PDT 24
Peak memory 212416 kb
Host smart-44761008-5eae-44ce-9bca-bdaf849f7dd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531327692 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3531327692
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2663166460
Short name T71
Test name
Test status
Simulation time 5895205617 ps
CPU time 14.46 seconds
Started Jun 04 12:43:26 PM PDT 24
Finished Jun 04 12:43:42 PM PDT 24
Peak memory 211224 kb
Host smart-c33a722c-dd9a-470f-85d1-849f34999a21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663166460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2663166460
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.738279601
Short name T398
Test name
Test status
Simulation time 4624760864 ps
CPU time 45.61 seconds
Started Jun 04 12:43:27 PM PDT 24
Finished Jun 04 12:44:13 PM PDT 24
Peak memory 211200 kb
Host smart-2784da7c-d55c-42fa-865d-e634e68f1c63
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738279601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.738279601
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1003394608
Short name T105
Test name
Test status
Simulation time 1545229018 ps
CPU time 6.81 seconds
Started Jun 04 12:43:24 PM PDT 24
Finished Jun 04 12:43:31 PM PDT 24
Peak memory 211160 kb
Host smart-ecba6968-b1de-4587-acd9-8486329c40c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003394608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1003394608
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1154150877
Short name T372
Test name
Test status
Simulation time 1238518326 ps
CPU time 13.08 seconds
Started Jun 04 12:43:24 PM PDT 24
Finished Jun 04 12:43:38 PM PDT 24
Peak memory 219376 kb
Host smart-e9f054c1-37c9-4cf4-bd09-addeb2e008f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154150877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1154150877
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2200072497
Short name T119
Test name
Test status
Simulation time 288359323 ps
CPU time 37.66 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:44:03 PM PDT 24
Peak memory 211160 kb
Host smart-7c455068-f794-4990-b20f-0ada1a3e04ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200072497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2200072497
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1915529548
Short name T377
Test name
Test status
Simulation time 184952422 ps
CPU time 4.92 seconds
Started Jun 04 12:43:29 PM PDT 24
Finished Jun 04 12:43:34 PM PDT 24
Peak memory 219356 kb
Host smart-a54cc5c9-9a35-4ed9-83d6-421299c4df26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915529548 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1915529548
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1697342757
Short name T76
Test name
Test status
Simulation time 168463934 ps
CPU time 4.36 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:43:31 PM PDT 24
Peak memory 211216 kb
Host smart-75acd1c5-a0ba-4517-9cea-fe8934f3ee59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697342757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1697342757
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1718955954
Short name T425
Test name
Test status
Simulation time 6097400421 ps
CPU time 34.92 seconds
Started Jun 04 12:43:28 PM PDT 24
Finished Jun 04 12:44:03 PM PDT 24
Peak memory 211244 kb
Host smart-9f79e093-d5f4-4444-a653-02427f2db8ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718955954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1718955954
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3881753903
Short name T424
Test name
Test status
Simulation time 3924667599 ps
CPU time 10.22 seconds
Started Jun 04 12:43:30 PM PDT 24
Finished Jun 04 12:43:41 PM PDT 24
Peak memory 211204 kb
Host smart-8fb08e29-c6c0-44bf-8fe4-3031458c47a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881753903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3881753903
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.526058133
Short name T411
Test name
Test status
Simulation time 1497594690 ps
CPU time 10.13 seconds
Started Jun 04 12:43:25 PM PDT 24
Finished Jun 04 12:43:35 PM PDT 24
Peak memory 219468 kb
Host smart-bae889bc-aa54-41ef-b19a-f1e8c1d70b72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526058133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.526058133
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3800891630
Short name T122
Test name
Test status
Simulation time 272342713 ps
CPU time 37.82 seconds
Started Jun 04 12:43:26 PM PDT 24
Finished Jun 04 12:44:05 PM PDT 24
Peak memory 212140 kb
Host smart-906a0a07-4cd0-40de-9d8d-3d342aa70627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800891630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3800891630
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1138628348
Short name T322
Test name
Test status
Simulation time 86665602 ps
CPU time 4.48 seconds
Started Jun 04 12:47:30 PM PDT 24
Finished Jun 04 12:47:36 PM PDT 24
Peak memory 210992 kb
Host smart-bfb87887-aaa3-40f1-903e-f8b2e88e9803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138628348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1138628348
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4240156814
Short name T269
Test name
Test status
Simulation time 19023561491 ps
CPU time 186.15 seconds
Started Jun 04 12:47:32 PM PDT 24
Finished Jun 04 12:50:39 PM PDT 24
Peak memory 228316 kb
Host smart-c19f7e8c-668a-475c-ae56-7442649e4a8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240156814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4240156814
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1300197804
Short name T100
Test name
Test status
Simulation time 1365613188 ps
CPU time 13.13 seconds
Started Jun 04 12:47:33 PM PDT 24
Finished Jun 04 12:47:46 PM PDT 24
Peak memory 211028 kb
Host smart-abf568a3-118e-42a5-b3a8-3ca51c73db0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300197804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1300197804
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3650873023
Short name T36
Test name
Test status
Simulation time 676157717 ps
CPU time 55.41 seconds
Started Jun 04 12:47:50 PM PDT 24
Finished Jun 04 12:48:47 PM PDT 24
Peak memory 239020 kb
Host smart-ae08c262-ea39-4848-801a-272a33a45ffa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650873023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3650873023
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3065833851
Short name T215
Test name
Test status
Simulation time 3145320309 ps
CPU time 24.48 seconds
Started Jun 04 12:47:29 PM PDT 24
Finished Jun 04 12:47:55 PM PDT 24
Peak memory 213828 kb
Host smart-df859162-8641-47a7-b16e-79fb2667618f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065833851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3065833851
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3266788570
Short name T84
Test name
Test status
Simulation time 226161116 ps
CPU time 14.56 seconds
Started Jun 04 12:47:55 PM PDT 24
Finished Jun 04 12:48:11 PM PDT 24
Peak memory 213152 kb
Host smart-98ac44cf-083e-465f-8e42-07e5df4bc198
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266788570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3266788570
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.690357125
Short name T192
Test name
Test status
Simulation time 14278144622 ps
CPU time 12.03 seconds
Started Jun 04 12:47:56 PM PDT 24
Finished Jun 04 12:48:09 PM PDT 24
Peak memory 211284 kb
Host smart-2af426d9-94a7-494b-873e-c1121d4e50fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690357125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.690357125
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.945571925
Short name T129
Test name
Test status
Simulation time 3522781187 ps
CPU time 68.43 seconds
Started Jun 04 12:47:38 PM PDT 24
Finished Jun 04 12:48:48 PM PDT 24
Peak memory 236676 kb
Host smart-3162574f-a28f-4dc6-ac82-9b2d5567dc5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945571925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.945571925
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1534087459
Short name T336
Test name
Test status
Simulation time 3192237302 ps
CPU time 28.58 seconds
Started Jun 04 12:47:42 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 211240 kb
Host smart-e3be7084-2333-44f8-9950-b59520ace19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534087459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1534087459
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2177255060
Short name T197
Test name
Test status
Simulation time 501957677 ps
CPU time 5.57 seconds
Started Jun 04 12:47:53 PM PDT 24
Finished Jun 04 12:48:00 PM PDT 24
Peak memory 210984 kb
Host smart-0d2c4d5b-ad09-40e6-9591-61b38c600b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177255060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2177255060
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2313592923
Short name T35
Test name
Test status
Simulation time 2098497917 ps
CPU time 109.86 seconds
Started Jun 04 12:47:31 PM PDT 24
Finished Jun 04 12:49:22 PM PDT 24
Peak memory 236648 kb
Host smart-5c0be37a-7668-4450-8935-b3d7b775fbb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313592923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2313592923
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2433499519
Short name T227
Test name
Test status
Simulation time 1121053391 ps
CPU time 9.7 seconds
Started Jun 04 12:47:48 PM PDT 24
Finished Jun 04 12:47:59 PM PDT 24
Peak memory 213424 kb
Host smart-24abc94c-1015-48c9-8b0b-dae7275664c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433499519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2433499519
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.864670036
Short name T232
Test name
Test status
Simulation time 1110648376 ps
CPU time 15.97 seconds
Started Jun 04 12:47:31 PM PDT 24
Finished Jun 04 12:47:48 PM PDT 24
Peak memory 213832 kb
Host smart-21bc26ef-32e6-4c1f-8a06-4f36e8ab144b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864670036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.864670036
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2015823337
Short name T38
Test name
Test status
Simulation time 20882367082 ps
CPU time 13.32 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:47:58 PM PDT 24
Peak memory 211248 kb
Host smart-7fa3dd08-fd17-46a2-94e5-619166fa32a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015823337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2015823337
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.553098120
Short name T362
Test name
Test status
Simulation time 205217395160 ps
CPU time 469.24 seconds
Started Jun 04 12:47:54 PM PDT 24
Finished Jun 04 12:55:44 PM PDT 24
Peak memory 236896 kb
Host smart-14161076-efab-4dd3-b5df-bd89d6b8421b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553098120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.553098120
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2009387436
Short name T236
Test name
Test status
Simulation time 18666944284 ps
CPU time 32.21 seconds
Started Jun 04 12:47:56 PM PDT 24
Finished Jun 04 12:48:29 PM PDT 24
Peak memory 212724 kb
Host smart-35ce22b3-c2d6-4423-a561-1d1e7e568d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009387436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2009387436
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.19364313
Short name T134
Test name
Test status
Simulation time 387675699 ps
CPU time 5.39 seconds
Started Jun 04 12:47:55 PM PDT 24
Finished Jun 04 12:48:01 PM PDT 24
Peak memory 211156 kb
Host smart-c0102b6a-3dd1-4e53-9840-29d13ad53484
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19364313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.19364313
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.339205843
Short name T248
Test name
Test status
Simulation time 47884815811 ps
CPU time 24.5 seconds
Started Jun 04 12:47:57 PM PDT 24
Finished Jun 04 12:48:22 PM PDT 24
Peak memory 219356 kb
Host smart-441a9837-31c5-47f7-ad48-766a63a5fbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339205843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.339205843
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.418092655
Short name T366
Test name
Test status
Simulation time 4674042418 ps
CPU time 24.15 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:48:09 PM PDT 24
Peak memory 214260 kb
Host smart-138108ff-4173-4445-ba30-4cc2906c3d45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418092655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.418092655
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2053471531
Short name T37
Test name
Test status
Simulation time 3936139120 ps
CPU time 11.52 seconds
Started Jun 04 12:47:44 PM PDT 24
Finished Jun 04 12:47:57 PM PDT 24
Peak memory 211192 kb
Host smart-9f3dce3f-d6a2-49c3-ad4b-178123045871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053471531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2053471531
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3665654320
Short name T51
Test name
Test status
Simulation time 63422801618 ps
CPU time 303.82 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:52:49 PM PDT 24
Peak memory 237872 kb
Host smart-1f54d6ff-1cc7-43f6-a75f-364e42b5ac88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665654320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3665654320
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3950024372
Short name T256
Test name
Test status
Simulation time 4072220460 ps
CPU time 32.72 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:48:17 PM PDT 24
Peak memory 211916 kb
Host smart-2482d8c8-5536-43bf-9ee1-34f6f38d00a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950024372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3950024372
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2284140852
Short name T284
Test name
Test status
Simulation time 1025532895 ps
CPU time 11.23 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:14 PM PDT 24
Peak memory 211044 kb
Host smart-de7f1142-6907-4154-8572-36a0d94a951c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284140852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2284140852
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2155703587
Short name T261
Test name
Test status
Simulation time 9534984611 ps
CPU time 34.15 seconds
Started Jun 04 12:47:40 PM PDT 24
Finished Jun 04 12:48:15 PM PDT 24
Peak memory 214168 kb
Host smart-37243af1-7fe7-459c-95ba-fa9d7151c649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155703587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2155703587
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4235068011
Short name T216
Test name
Test status
Simulation time 315965254 ps
CPU time 18.49 seconds
Started Jun 04 12:47:53 PM PDT 24
Finished Jun 04 12:48:13 PM PDT 24
Peak memory 219136 kb
Host smart-4e322851-6262-4976-be92-99426a68e0e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235068011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4235068011
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.347919707
Short name T15
Test name
Test status
Simulation time 61962397775 ps
CPU time 2455.77 seconds
Started Jun 04 12:47:54 PM PDT 24
Finished Jun 04 01:28:51 PM PDT 24
Peak memory 235848 kb
Host smart-d280ab87-c43d-4c37-8e1a-0a47a84f20f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347919707 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.347919707
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.311630057
Short name T350
Test name
Test status
Simulation time 1977985394 ps
CPU time 16.04 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:18 PM PDT 24
Peak memory 211084 kb
Host smart-ddba3cae-5132-4354-8feb-4c8191f35553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311630057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.311630057
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2833275411
Short name T277
Test name
Test status
Simulation time 14247877010 ps
CPU time 261.23 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:52:21 PM PDT 24
Peak memory 237856 kb
Host smart-cc8ec0c4-162e-4444-9c16-2eb44776cc6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833275411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2833275411
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.737986943
Short name T360
Test name
Test status
Simulation time 5539716542 ps
CPU time 25.97 seconds
Started Jun 04 12:47:42 PM PDT 24
Finished Jun 04 12:48:09 PM PDT 24
Peak memory 213728 kb
Host smart-9b6fa7f5-ba40-408a-9cde-71173654752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737986943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.737986943
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2017417072
Short name T255
Test name
Test status
Simulation time 380471978 ps
CPU time 5.5 seconds
Started Jun 04 12:47:41 PM PDT 24
Finished Jun 04 12:47:48 PM PDT 24
Peak memory 211064 kb
Host smart-f4a4fa19-0a7f-4cd0-8e6e-6f32a4a8e333
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017417072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2017417072
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4108396413
Short name T190
Test name
Test status
Simulation time 3551894345 ps
CPU time 23.34 seconds
Started Jun 04 12:47:41 PM PDT 24
Finished Jun 04 12:48:05 PM PDT 24
Peak memory 213664 kb
Host smart-90879935-2196-4991-a00a-b482d9110aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108396413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4108396413
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1382573226
Short name T145
Test name
Test status
Simulation time 14175640350 ps
CPU time 33.18 seconds
Started Jun 04 12:47:53 PM PDT 24
Finished Jun 04 12:48:27 PM PDT 24
Peak memory 213468 kb
Host smart-ea6ecd6c-d498-4557-b437-49b51570d7aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382573226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1382573226
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.697693073
Short name T348
Test name
Test status
Simulation time 1452463076 ps
CPU time 8.92 seconds
Started Jun 04 12:47:47 PM PDT 24
Finished Jun 04 12:47:57 PM PDT 24
Peak memory 211332 kb
Host smart-53b0b0fc-0986-486e-99ee-a7abf60ce38a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697693073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.697693073
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2542190756
Short name T308
Test name
Test status
Simulation time 2264401725 ps
CPU time 82.9 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 12:49:34 PM PDT 24
Peak memory 212380 kb
Host smart-921991bf-666d-4264-9176-b55ecfd87681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542190756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2542190756
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1249958318
Short name T211
Test name
Test status
Simulation time 1503743930 ps
CPU time 12.1 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:14 PM PDT 24
Peak memory 212068 kb
Host smart-1740a811-66db-46ae-99da-eb563f76c2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249958318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1249958318
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3186742351
Short name T275
Test name
Test status
Simulation time 3535560743 ps
CPU time 11.94 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:14 PM PDT 24
Peak memory 211124 kb
Host smart-510994ef-39e9-499f-9cd9-ed329eb96059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186742351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3186742351
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3937893857
Short name T238
Test name
Test status
Simulation time 2306581278 ps
CPU time 21.01 seconds
Started Jun 04 12:47:55 PM PDT 24
Finished Jun 04 12:48:17 PM PDT 24
Peak memory 213108 kb
Host smart-74b4b605-a82c-4758-bd07-314264f83163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937893857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3937893857
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1364716305
Short name T244
Test name
Test status
Simulation time 23421410868 ps
CPU time 42.79 seconds
Started Jun 04 12:47:46 PM PDT 24
Finished Jun 04 12:48:30 PM PDT 24
Peak memory 215984 kb
Host smart-192d3f6b-2c2b-4035-b3d2-839cf75b1b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364716305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1364716305
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1805427045
Short name T285
Test name
Test status
Simulation time 2074589091 ps
CPU time 7.63 seconds
Started Jun 04 12:48:03 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 211148 kb
Host smart-b77b4fad-0ea8-485a-b558-3ecd658498ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805427045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1805427045
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1021555185
Short name T325
Test name
Test status
Simulation time 47653152603 ps
CPU time 230.09 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 237836 kb
Host smart-0e9e4c03-bf3c-4e04-b4f7-55bf68e5741e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021555185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1021555185
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3952464120
Short name T221
Test name
Test status
Simulation time 504453055 ps
CPU time 13.19 seconds
Started Jun 04 12:47:52 PM PDT 24
Finished Jun 04 12:48:07 PM PDT 24
Peak memory 211828 kb
Host smart-7a446089-39cb-4b48-877a-8494023b5a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952464120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3952464120
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2710925120
Short name T203
Test name
Test status
Simulation time 7495349017 ps
CPU time 16.31 seconds
Started Jun 04 12:47:50 PM PDT 24
Finished Jun 04 12:48:08 PM PDT 24
Peak memory 211180 kb
Host smart-f2210f0c-35b0-4461-b2e6-01b01860a0c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2710925120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2710925120
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3185692235
Short name T334
Test name
Test status
Simulation time 4573318302 ps
CPU time 22.35 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:48:13 PM PDT 24
Peak memory 213324 kb
Host smart-bdf97597-2a62-4a22-88ff-3b59c0515a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185692235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3185692235
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.238820626
Short name T171
Test name
Test status
Simulation time 4773411862 ps
CPU time 37.11 seconds
Started Jun 04 12:47:53 PM PDT 24
Finished Jun 04 12:48:31 PM PDT 24
Peak memory 216820 kb
Host smart-1acc84bb-11c7-4f7d-8fec-d15735ae3349
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238820626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.238820626
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.178028645
Short name T47
Test name
Test status
Simulation time 62201059719 ps
CPU time 2535.87 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 01:30:07 PM PDT 24
Peak memory 238944 kb
Host smart-c5e90302-b372-400c-9f77-6074c7e9d87a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178028645 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.178028645
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2004945547
Short name T70
Test name
Test status
Simulation time 4528471356 ps
CPU time 11.85 seconds
Started Jun 04 12:47:56 PM PDT 24
Finished Jun 04 12:48:08 PM PDT 24
Peak memory 211180 kb
Host smart-223550c5-d666-47d1-959b-fa31150619a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004945547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2004945547
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3557253742
Short name T331
Test name
Test status
Simulation time 31877091924 ps
CPU time 281.48 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:52:42 PM PDT 24
Peak memory 237752 kb
Host smart-98b6d9db-783f-40b3-928d-c1160fbc257c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557253742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3557253742
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3846142
Short name T133
Test name
Test status
Simulation time 2552493960 ps
CPU time 25.3 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:28 PM PDT 24
Peak memory 211632 kb
Host smart-5bf65851-0a71-4dfa-b42f-7698c12747ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3846142
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2150709574
Short name T156
Test name
Test status
Simulation time 747582330 ps
CPU time 9.93 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 219240 kb
Host smart-41e4f0b0-30db-43fc-9316-d18cf8fa0c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150709574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2150709574
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1302031184
Short name T311
Test name
Test status
Simulation time 55776955980 ps
CPU time 52.33 seconds
Started Jun 04 12:47:51 PM PDT 24
Finished Jun 04 12:48:45 PM PDT 24
Peak memory 219232 kb
Host smart-0f2bf829-b0b6-4627-b997-b66ddaed816a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302031184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1302031184
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1171574647
Short name T165
Test name
Test status
Simulation time 47895505332 ps
CPU time 127.99 seconds
Started Jun 04 12:48:04 PM PDT 24
Finished Jun 04 12:50:13 PM PDT 24
Peak memory 212412 kb
Host smart-8626cdba-9aaf-42dd-92af-4c78d90c3c8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171574647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1171574647
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.271471464
Short name T8
Test name
Test status
Simulation time 6628957524 ps
CPU time 29.37 seconds
Started Jun 04 12:47:57 PM PDT 24
Finished Jun 04 12:48:28 PM PDT 24
Peak memory 212396 kb
Host smart-bf029253-04cb-4816-8fcd-0d57f026dcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271471464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.271471464
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2649160701
Short name T340
Test name
Test status
Simulation time 4060968860 ps
CPU time 17.67 seconds
Started Jun 04 12:47:46 PM PDT 24
Finished Jun 04 12:48:05 PM PDT 24
Peak memory 211160 kb
Host smart-96992fd3-861f-4ab4-a536-cffafccbaa13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649160701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2649160701
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2294714680
Short name T243
Test name
Test status
Simulation time 24688378794 ps
CPU time 24.6 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:48:16 PM PDT 24
Peak memory 214448 kb
Host smart-88521f0f-44dc-44f5-8e30-2ee6fdc941d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294714680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2294714680
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4189869759
Short name T341
Test name
Test status
Simulation time 23806254712 ps
CPU time 60.17 seconds
Started Jun 04 12:47:52 PM PDT 24
Finished Jun 04 12:48:53 PM PDT 24
Peak memory 217080 kb
Host smart-35aa17a2-f727-4529-983a-c2c5f9640d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189869759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4189869759
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2941810349
Short name T226
Test name
Test status
Simulation time 73677868942 ps
CPU time 1373.54 seconds
Started Jun 04 12:47:50 PM PDT 24
Finished Jun 04 01:10:46 PM PDT 24
Peak memory 235896 kb
Host smart-81ea7f72-7fdd-4360-9c89-3f2e883d805b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941810349 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2941810349
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3396354671
Short name T276
Test name
Test status
Simulation time 6734411685 ps
CPU time 9.07 seconds
Started Jun 04 12:48:03 PM PDT 24
Finished Jun 04 12:48:14 PM PDT 24
Peak memory 211204 kb
Host smart-212bd8f4-b25a-4a96-af0b-ebcba6396214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396354671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3396354671
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1824400514
Short name T364
Test name
Test status
Simulation time 59277025147 ps
CPU time 149.35 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:50:20 PM PDT 24
Peak memory 236724 kb
Host smart-13a511b6-7f92-4bc6-af9c-e03e30bd3cec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824400514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1824400514
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1284169818
Short name T320
Test name
Test status
Simulation time 416392137 ps
CPU time 9.36 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:48:01 PM PDT 24
Peak memory 211928 kb
Host smart-37b0db28-c11a-4483-8763-a95ad7a3d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284169818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1284169818
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3335108158
Short name T239
Test name
Test status
Simulation time 952016376 ps
CPU time 11.09 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:11 PM PDT 24
Peak memory 211136 kb
Host smart-f28971eb-da66-4682-af2b-979d5a051f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3335108158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3335108158
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3546656501
Short name T153
Test name
Test status
Simulation time 923318342 ps
CPU time 16.83 seconds
Started Jun 04 12:47:47 PM PDT 24
Finished Jun 04 12:48:05 PM PDT 24
Peak memory 213304 kb
Host smart-866aa2b4-81df-49e9-8e46-085487554f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546656501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3546656501
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4275676101
Short name T326
Test name
Test status
Simulation time 4211843519 ps
CPU time 33.84 seconds
Started Jun 04 12:47:52 PM PDT 24
Finished Jun 04 12:48:27 PM PDT 24
Peak memory 217296 kb
Host smart-ece43247-f6bd-46fb-8e28-91b5e330c7e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275676101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4275676101
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.217692955
Short name T273
Test name
Test status
Simulation time 4645490109 ps
CPU time 8.67 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:18 PM PDT 24
Peak memory 211096 kb
Host smart-69395fb3-dd86-47f5-9f5b-0196b3287f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217692955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.217692955
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3858494382
Short name T32
Test name
Test status
Simulation time 45363724200 ps
CPU time 420.85 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:54:52 PM PDT 24
Peak memory 213516 kb
Host smart-6b633a97-2fcc-4b0b-8de5-3d64625d5ee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858494382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3858494382
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2385333159
Short name T151
Test name
Test status
Simulation time 12024970399 ps
CPU time 33.16 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:36 PM PDT 24
Peak memory 212252 kb
Host smart-ed4870a2-fae8-4236-ae46-a7a6f19576cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385333159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2385333159
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3449689359
Short name T178
Test name
Test status
Simulation time 7836390132 ps
CPU time 13.88 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:15 PM PDT 24
Peak memory 211100 kb
Host smart-1e61896f-54d4-4ead-8685-3a13d6502c89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449689359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3449689359
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3782756069
Short name T330
Test name
Test status
Simulation time 30210459523 ps
CPU time 37.01 seconds
Started Jun 04 12:48:07 PM PDT 24
Finished Jun 04 12:48:45 PM PDT 24
Peak memory 219288 kb
Host smart-888a6dad-c485-48a5-aa2b-16952bca3529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782756069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3782756069
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1152415559
Short name T281
Test name
Test status
Simulation time 759918748 ps
CPU time 6.66 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:47:58 PM PDT 24
Peak memory 211168 kb
Host smart-4e7f9dc2-ed53-4a2d-ba93-206ddb4825d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152415559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1152415559
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3354365703
Short name T337
Test name
Test status
Simulation time 44868890103 ps
CPU time 168.02 seconds
Started Jun 04 12:47:48 PM PDT 24
Finished Jun 04 12:50:39 PM PDT 24
Peak memory 233216 kb
Host smart-edba67dc-2192-48f6-800c-4563e5f63150
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354365703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3354365703
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4277288758
Short name T286
Test name
Test status
Simulation time 577181863 ps
CPU time 13.64 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:15 PM PDT 24
Peak memory 211820 kb
Host smart-a1fd37b0-2382-41e2-b7b1-befe0e146731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277288758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4277288758
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3886802239
Short name T220
Test name
Test status
Simulation time 8982963310 ps
CPU time 17.84 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:48:09 PM PDT 24
Peak memory 211068 kb
Host smart-5fcfd06f-0a74-464f-b0df-275552b9f0c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886802239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3886802239
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.817128845
Short name T361
Test name
Test status
Simulation time 11571420969 ps
CPU time 25.82 seconds
Started Jun 04 12:47:51 PM PDT 24
Finished Jun 04 12:48:18 PM PDT 24
Peak memory 219360 kb
Host smart-ee24698d-f78b-4720-aedf-b0b5d62f7c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817128845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.817128845
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1229715193
Short name T98
Test name
Test status
Simulation time 6174321359 ps
CPU time 54.88 seconds
Started Jun 04 12:47:48 PM PDT 24
Finished Jun 04 12:48:45 PM PDT 24
Peak memory 219268 kb
Host smart-ea5f5791-7c08-45e1-8573-4139cfd081e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229715193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1229715193
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1949287971
Short name T223
Test name
Test status
Simulation time 1334814120 ps
CPU time 12.11 seconds
Started Jun 04 12:47:35 PM PDT 24
Finished Jun 04 12:47:49 PM PDT 24
Peak memory 210844 kb
Host smart-4e4d05f3-b755-4085-9f17-8957db6fb3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949287971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1949287971
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2442294482
Short name T28
Test name
Test status
Simulation time 12144526173 ps
CPU time 117.54 seconds
Started Jun 04 12:47:52 PM PDT 24
Finished Jun 04 12:49:51 PM PDT 24
Peak memory 233676 kb
Host smart-1b1bc753-bd8b-4829-906b-b87d800eb016
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442294482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2442294482
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1742300311
Short name T43
Test name
Test status
Simulation time 16365859279 ps
CPU time 32.62 seconds
Started Jun 04 12:47:28 PM PDT 24
Finished Jun 04 12:48:02 PM PDT 24
Peak memory 211408 kb
Host smart-fcd8a2cd-3cce-4025-8b9d-40311ac28f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742300311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1742300311
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.508027113
Short name T323
Test name
Test status
Simulation time 376311186 ps
CPU time 5.57 seconds
Started Jun 04 12:47:31 PM PDT 24
Finished Jun 04 12:47:38 PM PDT 24
Peak memory 210964 kb
Host smart-0e4d2442-2d3e-416b-879d-4e175546a3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508027113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.508027113
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3967454434
Short name T81
Test name
Test status
Simulation time 9882094165 ps
CPU time 24.75 seconds
Started Jun 04 12:47:45 PM PDT 24
Finished Jun 04 12:48:11 PM PDT 24
Peak memory 214136 kb
Host smart-69be8bb6-644e-4706-99ba-f009a1e749e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967454434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3967454434
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4173997239
Short name T287
Test name
Test status
Simulation time 5318195204 ps
CPU time 21.75 seconds
Started Jun 04 12:47:41 PM PDT 24
Finished Jun 04 12:48:04 PM PDT 24
Peak memory 219312 kb
Host smart-091e96a7-f95c-4985-a2bb-650f9743e0f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173997239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4173997239
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2083410919
Short name T162
Test name
Test status
Simulation time 598672333 ps
CPU time 7.78 seconds
Started Jun 04 12:47:56 PM PDT 24
Finished Jun 04 12:48:05 PM PDT 24
Peak memory 211080 kb
Host smart-acd7238a-eefc-470f-9ca0-9de7e74b9366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083410919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2083410919
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2897372859
Short name T24
Test name
Test status
Simulation time 29094580438 ps
CPU time 302.13 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:53:03 PM PDT 24
Peak memory 237752 kb
Host smart-09b2d70f-b5cd-488d-a191-4b00417732f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897372859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2897372859
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3350174257
Short name T343
Test name
Test status
Simulation time 175694190 ps
CPU time 9.33 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:48:00 PM PDT 24
Peak memory 211832 kb
Host smart-b4c087cb-8a1b-4974-831d-35979ba09c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350174257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3350174257
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1119311640
Short name T202
Test name
Test status
Simulation time 4952167558 ps
CPU time 13.6 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:13 PM PDT 24
Peak memory 211172 kb
Host smart-a7de6e5f-11f3-48f3-a383-35321b1ec40d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1119311640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1119311640
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3417178841
Short name T63
Test name
Test status
Simulation time 1009714918 ps
CPU time 11.68 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:13 PM PDT 24
Peak memory 219244 kb
Host smart-b0747699-1597-4b06-a049-e026da72cd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417178841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3417178841
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3698944325
Short name T168
Test name
Test status
Simulation time 4482560922 ps
CPU time 55.88 seconds
Started Jun 04 12:47:50 PM PDT 24
Finished Jun 04 12:48:48 PM PDT 24
Peak memory 215400 kb
Host smart-53bb4e55-74b1-4459-b4f5-9d157f566b77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698944325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3698944325
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3204140491
Short name T176
Test name
Test status
Simulation time 1720691007 ps
CPU time 8.89 seconds
Started Jun 04 12:47:54 PM PDT 24
Finished Jun 04 12:48:04 PM PDT 24
Peak memory 211068 kb
Host smart-f94f3c23-a2b1-4cf7-be68-88d35841758d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204140491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3204140491
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1507487697
Short name T214
Test name
Test status
Simulation time 2119211067 ps
CPU time 17.5 seconds
Started Jun 04 12:48:02 PM PDT 24
Finished Jun 04 12:48:21 PM PDT 24
Peak memory 210960 kb
Host smart-baf25a0c-06a6-4dc9-8bfb-d46c205e9a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507487697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1507487697
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2780685823
Short name T208
Test name
Test status
Simulation time 10354453620 ps
CPU time 31.06 seconds
Started Jun 04 12:48:39 PM PDT 24
Finished Jun 04 12:49:11 PM PDT 24
Peak memory 214092 kb
Host smart-04404480-5950-4f41-b657-d2f75f31a5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780685823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2780685823
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4050294161
Short name T310
Test name
Test status
Simulation time 198601882 ps
CPU time 8.5 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:09 PM PDT 24
Peak memory 210960 kb
Host smart-2744ce8e-75c9-4ff4-ae95-d82eeff1a1b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050294161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4050294161
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3432668700
Short name T296
Test name
Test status
Simulation time 5478957811 ps
CPU time 12.61 seconds
Started Jun 04 12:48:04 PM PDT 24
Finished Jun 04 12:48:18 PM PDT 24
Peak memory 211224 kb
Host smart-5b3516ae-3c35-49b1-98b7-dfc96ea3d875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432668700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3432668700
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.555632925
Short name T270
Test name
Test status
Simulation time 3380562971 ps
CPU time 53.4 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:55 PM PDT 24
Peak memory 211416 kb
Host smart-c4e3ac28-55d3-49c4-86d1-e197daa0eed6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555632925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.555632925
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.427636855
Short name T183
Test name
Test status
Simulation time 2032068891 ps
CPU time 20.43 seconds
Started Jun 04 12:48:02 PM PDT 24
Finished Jun 04 12:48:24 PM PDT 24
Peak memory 211884 kb
Host smart-3fe725d7-7052-46f0-b550-9c728958fa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427636855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.427636855
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3339460793
Short name T179
Test name
Test status
Simulation time 3049932688 ps
CPU time 14.32 seconds
Started Jun 04 12:47:52 PM PDT 24
Finished Jun 04 12:48:08 PM PDT 24
Peak memory 211104 kb
Host smart-58323a1b-005d-4058-9a2d-bf2032aff1d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3339460793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3339460793
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.489142249
Short name T346
Test name
Test status
Simulation time 279075410 ps
CPU time 11.98 seconds
Started Jun 04 12:48:04 PM PDT 24
Finished Jun 04 12:48:17 PM PDT 24
Peak memory 212628 kb
Host smart-9520e183-09d3-4c6e-a681-ac5925dd8001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489142249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.489142249
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1053825280
Short name T170
Test name
Test status
Simulation time 10506838850 ps
CPU time 31.23 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:31 PM PDT 24
Peak memory 217088 kb
Host smart-4314461a-e6aa-4f46-902f-00c7c7de0204
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053825280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1053825280
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3970761062
Short name T169
Test name
Test status
Simulation time 2364329957 ps
CPU time 8.05 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:11 PM PDT 24
Peak memory 211228 kb
Host smart-cc0303ac-bc68-45c1-9778-be7ac787116b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970761062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3970761062
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1664202711
Short name T247
Test name
Test status
Simulation time 15868008161 ps
CPU time 192.69 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:51:16 PM PDT 24
Peak memory 212476 kb
Host smart-faefb624-62c6-41f8-9458-4823e7d72a33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664202711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1664202711
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.228989026
Short name T20
Test name
Test status
Simulation time 665047533 ps
CPU time 9.32 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:09 PM PDT 24
Peak memory 210968 kb
Host smart-8b04ff73-0bb6-42e4-90e4-532afd622ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228989026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.228989026
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3409206653
Short name T163
Test name
Test status
Simulation time 1512502733 ps
CPU time 14.18 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:17 PM PDT 24
Peak memory 211060 kb
Host smart-b3302960-5631-4571-8db9-8ba8d991ab71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409206653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3409206653
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3242986721
Short name T300
Test name
Test status
Simulation time 4082258881 ps
CPU time 32 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:32 PM PDT 24
Peak memory 212796 kb
Host smart-420de280-e907-45a7-b51f-4fbc62a5c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242986721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3242986721
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.702352915
Short name T177
Test name
Test status
Simulation time 1535806690 ps
CPU time 27.49 seconds
Started Jun 04 12:48:12 PM PDT 24
Finished Jun 04 12:48:40 PM PDT 24
Peak memory 219152 kb
Host smart-1a9abe21-cd02-4061-8f79-6d284f08ea5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702352915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.702352915
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1528117361
Short name T317
Test name
Test status
Simulation time 232825042 ps
CPU time 4.28 seconds
Started Jun 04 12:48:02 PM PDT 24
Finished Jun 04 12:48:08 PM PDT 24
Peak memory 211060 kb
Host smart-6a7a0cb8-ea3f-4f4d-8c84-f788787a693a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528117361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1528117361
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2290015877
Short name T278
Test name
Test status
Simulation time 5863559735 ps
CPU time 90.81 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:49:31 PM PDT 24
Peak memory 228596 kb
Host smart-4e2e37bf-b8b3-481d-bff6-22fe0f75e3dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290015877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2290015877
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2088881689
Short name T268
Test name
Test status
Simulation time 175032837 ps
CPU time 9.53 seconds
Started Jun 04 12:47:56 PM PDT 24
Finished Jun 04 12:48:07 PM PDT 24
Peak memory 211600 kb
Host smart-07990dff-d166-4c2d-a200-50c285700f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088881689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2088881689
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4234069602
Short name T367
Test name
Test status
Simulation time 8457281003 ps
CPU time 17.52 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:18 PM PDT 24
Peak memory 210920 kb
Host smart-ad2e561d-a2f5-4957-88c3-b8451f00ff01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234069602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4234069602
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2885046110
Short name T234
Test name
Test status
Simulation time 194156613 ps
CPU time 10.07 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 219160 kb
Host smart-60a09b16-48cf-480a-a742-eda2e18aa8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885046110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2885046110
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2943686174
Short name T141
Test name
Test status
Simulation time 150865362688 ps
CPU time 97.41 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:49:40 PM PDT 24
Peak memory 216536 kb
Host smart-6cb86892-c366-48b1-b0e8-92d8a5ae2586
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943686174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2943686174
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3623361581
Short name T173
Test name
Test status
Simulation time 4753777795 ps
CPU time 11.54 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:14 PM PDT 24
Peak memory 211180 kb
Host smart-47b2b2ed-3560-441b-807c-97f01db6ae84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623361581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3623361581
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4053890491
Short name T180
Test name
Test status
Simulation time 17031910776 ps
CPU time 177.4 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:51:01 PM PDT 24
Peak memory 237744 kb
Host smart-fe13c260-ff83-4f3a-aa75-9ef9acb20579
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053890491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4053890491
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.224807527
Short name T204
Test name
Test status
Simulation time 2829108534 ps
CPU time 18.64 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:20 PM PDT 24
Peak memory 212844 kb
Host smart-552c7473-4294-4d3d-9127-c56bd40e72e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224807527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.224807527
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1265861951
Short name T359
Test name
Test status
Simulation time 4949297331 ps
CPU time 13.05 seconds
Started Jun 04 12:47:56 PM PDT 24
Finished Jun 04 12:48:11 PM PDT 24
Peak memory 211240 kb
Host smart-7fa84772-788c-4808-a851-2cc34cfdd3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265861951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1265861951
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3064692516
Short name T83
Test name
Test status
Simulation time 10657667332 ps
CPU time 27.47 seconds
Started Jun 04 12:47:57 PM PDT 24
Finished Jun 04 12:48:27 PM PDT 24
Peak memory 219352 kb
Host smart-3df64227-62d8-4610-9916-67cceb08c478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064692516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3064692516
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1376381740
Short name T349
Test name
Test status
Simulation time 23010502523 ps
CPU time 39.57 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:41 PM PDT 24
Peak memory 219304 kb
Host smart-f1a99e32-0b21-4dce-8516-064c9b745454
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376381740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1376381740
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1855471397
Short name T55
Test name
Test status
Simulation time 355345752029 ps
CPU time 940.43 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 01:03:49 PM PDT 24
Peak memory 231832 kb
Host smart-96090d69-8a4e-457e-b957-0f27ef98a8a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855471397 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1855471397
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1321230472
Short name T193
Test name
Test status
Simulation time 11325907648 ps
CPU time 13.1 seconds
Started Jun 04 12:48:06 PM PDT 24
Finished Jun 04 12:48:20 PM PDT 24
Peak memory 211132 kb
Host smart-e5f36a64-7da1-42d1-8cf4-cc504136c744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321230472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1321230472
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2169491775
Short name T52
Test name
Test status
Simulation time 369524225838 ps
CPU time 653.82 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:58:54 PM PDT 24
Peak memory 213260 kb
Host smart-c9c75f99-a84e-419a-9c31-4c50520d382f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169491775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2169491775
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.309440226
Short name T246
Test name
Test status
Simulation time 14164273979 ps
CPU time 31.18 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:33 PM PDT 24
Peak memory 212264 kb
Host smart-4ccdab7f-fcd7-4411-bb9c-7c0c60ee60e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309440226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.309440226
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3468095567
Short name T316
Test name
Test status
Simulation time 5168262908 ps
CPU time 12.81 seconds
Started Jun 04 12:47:57 PM PDT 24
Finished Jun 04 12:48:10 PM PDT 24
Peak memory 211208 kb
Host smart-258aa5ac-d21a-4c62-9ca8-448525673217
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3468095567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3468095567
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1191201233
Short name T263
Test name
Test status
Simulation time 29254421247 ps
CPU time 22.35 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:25 PM PDT 24
Peak memory 214048 kb
Host smart-459cea90-c10f-46e8-a5f9-b73f3c515d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191201233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1191201233
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4155850362
Short name T196
Test name
Test status
Simulation time 826085892 ps
CPU time 16.23 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:19 PM PDT 24
Peak memory 211956 kb
Host smart-0390cde7-0c0b-4050-8e20-abe8c8155f55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155850362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4155850362
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.485919867
Short name T229
Test name
Test status
Simulation time 1157117296 ps
CPU time 10.39 seconds
Started Jun 04 12:48:02 PM PDT 24
Finished Jun 04 12:48:14 PM PDT 24
Peak memory 211032 kb
Host smart-ef94620c-c11c-4e88-b349-df3774728e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485919867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.485919867
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.231114855
Short name T33
Test name
Test status
Simulation time 6696084045 ps
CPU time 108.3 seconds
Started Jun 04 12:48:04 PM PDT 24
Finished Jun 04 12:49:53 PM PDT 24
Peak memory 237500 kb
Host smart-cb6f6aae-d7bc-4fa4-abb5-00c75dff05b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231114855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.231114855
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3602203359
Short name T48
Test name
Test status
Simulation time 7261986554 ps
CPU time 25.56 seconds
Started Jun 04 12:48:06 PM PDT 24
Finished Jun 04 12:48:33 PM PDT 24
Peak memory 212456 kb
Host smart-95b27e9c-93c4-457c-ae46-550c05e3355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602203359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3602203359
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3781143997
Short name T363
Test name
Test status
Simulation time 2008782793 ps
CPU time 17.86 seconds
Started Jun 04 12:47:55 PM PDT 24
Finished Jun 04 12:48:14 PM PDT 24
Peak memory 211064 kb
Host smart-07bdf3fa-4eaf-44c4-aa8c-d8c7f4bbc24b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781143997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3781143997
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.422628090
Short name T297
Test name
Test status
Simulation time 7369788023 ps
CPU time 35.24 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:45 PM PDT 24
Peak memory 214108 kb
Host smart-48ee6c48-829f-4618-9cc7-45488f644fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422628090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.422628090
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2314278887
Short name T231
Test name
Test status
Simulation time 2071343015 ps
CPU time 19.8 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:22 PM PDT 24
Peak memory 212272 kb
Host smart-60a4666a-d15d-4019-aeca-b98b57a22e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314278887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2314278887
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3297941961
Short name T262
Test name
Test status
Simulation time 2633009365 ps
CPU time 8.34 seconds
Started Jun 04 12:48:02 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 211104 kb
Host smart-5dcb4160-bc32-4ab8-9ec0-28861372cd39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297941961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3297941961
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3527235176
Short name T130
Test name
Test status
Simulation time 241541572395 ps
CPU time 465.27 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:55:46 PM PDT 24
Peak memory 212460 kb
Host smart-28bc5f48-2b55-4de7-b01c-3484bbc10ebd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527235176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3527235176
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1848786968
Short name T103
Test name
Test status
Simulation time 2627498951 ps
CPU time 25.19 seconds
Started Jun 04 12:47:55 PM PDT 24
Finished Jun 04 12:48:21 PM PDT 24
Peak memory 211340 kb
Host smart-ba864292-e5ab-4b65-bb75-ed7e2308640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848786968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1848786968
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.278685739
Short name T7
Test name
Test status
Simulation time 101648444 ps
CPU time 5.69 seconds
Started Jun 04 12:48:03 PM PDT 24
Finished Jun 04 12:48:10 PM PDT 24
Peak memory 211172 kb
Host smart-3aa91747-ae04-4f63-a5fd-ade92985ca95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278685739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.278685739
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3505451405
Short name T44
Test name
Test status
Simulation time 3280246146 ps
CPU time 11.55 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:14 PM PDT 24
Peak memory 219272 kb
Host smart-49a25092-bd46-4648-8ec7-62e10a710fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505451405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3505451405
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1251522332
Short name T132
Test name
Test status
Simulation time 7846114539 ps
CPU time 47.84 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:51 PM PDT 24
Peak memory 215640 kb
Host smart-b0774c8d-0150-43cd-a04a-852c810b2932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251522332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1251522332
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2211248327
Short name T306
Test name
Test status
Simulation time 47187150025 ps
CPU time 659.27 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:59:00 PM PDT 24
Peak memory 228308 kb
Host smart-cbad7b59-6eaa-4b05-94b5-2c3831ba8c24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211248327 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2211248327
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1897035151
Short name T324
Test name
Test status
Simulation time 4058908196 ps
CPU time 15.89 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:18 PM PDT 24
Peak memory 211060 kb
Host smart-fea82e2c-7663-410c-bf25-e430e472824f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897035151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1897035151
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3951123192
Short name T356
Test name
Test status
Simulation time 55850917952 ps
CPU time 561.5 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:57:23 PM PDT 24
Peak memory 237004 kb
Host smart-29fbdc78-9208-4ce4-ba01-888058e96c9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951123192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3951123192
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2988385075
Short name T352
Test name
Test status
Simulation time 3006897371 ps
CPU time 11.61 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:11 PM PDT 24
Peak memory 211364 kb
Host smart-02f17329-03e2-49f4-a317-859cf0f6a960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988385075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2988385075
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2027046075
Short name T199
Test name
Test status
Simulation time 777987257 ps
CPU time 11.59 seconds
Started Jun 04 12:48:03 PM PDT 24
Finished Jun 04 12:48:16 PM PDT 24
Peak memory 212052 kb
Host smart-00aa066b-e430-4ce8-87e5-d9db891143aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027046075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2027046075
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1944052401
Short name T328
Test name
Test status
Simulation time 12200494992 ps
CPU time 2436.07 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 01:28:36 PM PDT 24
Peak memory 233816 kb
Host smart-a1413add-0226-4fe8-ae3f-944def972774
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944052401 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1944052401
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1689371211
Short name T228
Test name
Test status
Simulation time 85804485 ps
CPU time 4.38 seconds
Started Jun 04 12:47:30 PM PDT 24
Finished Jun 04 12:47:35 PM PDT 24
Peak memory 211124 kb
Host smart-aaab63ea-b050-4cb5-8920-5c32a679261f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689371211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1689371211
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2793367387
Short name T299
Test name
Test status
Simulation time 15852971070 ps
CPU time 154.4 seconds
Started Jun 04 12:47:31 PM PDT 24
Finished Jun 04 12:50:07 PM PDT 24
Peak memory 225340 kb
Host smart-6804af79-937d-443b-b9b6-395dd0c21238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793367387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2793367387
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.427033904
Short name T335
Test name
Test status
Simulation time 463489031 ps
CPU time 11.12 seconds
Started Jun 04 12:47:36 PM PDT 24
Finished Jun 04 12:47:49 PM PDT 24
Peak memory 211828 kb
Host smart-394a577f-9187-455e-be8f-664a71b4e9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427033904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.427033904
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.299901292
Short name T253
Test name
Test status
Simulation time 206026861 ps
CPU time 5.96 seconds
Started Jun 04 12:47:36 PM PDT 24
Finished Jun 04 12:47:44 PM PDT 24
Peak memory 211064 kb
Host smart-46d2c76c-3fb4-475a-9666-6508229d762b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=299901292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.299901292
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.787916935
Short name T40
Test name
Test status
Simulation time 6312926974 ps
CPU time 63.65 seconds
Started Jun 04 12:47:32 PM PDT 24
Finished Jun 04 12:48:37 PM PDT 24
Peak memory 233800 kb
Host smart-fc7863b5-aaf9-4ea9-b5e1-3af34fb83c81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787916935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.787916935
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1664672270
Short name T298
Test name
Test status
Simulation time 218619506 ps
CPU time 10.28 seconds
Started Jun 04 12:47:34 PM PDT 24
Finished Jun 04 12:47:45 PM PDT 24
Peak memory 212988 kb
Host smart-ca6fdf5d-67d6-4973-9f70-4931b89764af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664672270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1664672270
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.694321852
Short name T282
Test name
Test status
Simulation time 11566479663 ps
CPU time 17.53 seconds
Started Jun 04 12:47:47 PM PDT 24
Finished Jun 04 12:48:06 PM PDT 24
Peak memory 212036 kb
Host smart-40732950-6745-423d-b718-4153366bc744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694321852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.694321852
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3560595259
Short name T161
Test name
Test status
Simulation time 515633176 ps
CPU time 4.9 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:05 PM PDT 24
Peak memory 211168 kb
Host smart-f7884fde-e4fa-451a-9926-3f359f72f2a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560595259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3560595259
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2305451864
Short name T258
Test name
Test status
Simulation time 97104728037 ps
CPU time 236.5 seconds
Started Jun 04 12:48:02 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 236524 kb
Host smart-33688203-7634-42c9-9357-07696f24f24d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305451864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2305451864
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.495138389
Short name T257
Test name
Test status
Simulation time 348390376 ps
CPU time 9.42 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:10 PM PDT 24
Peak memory 211772 kb
Host smart-1738d910-e7ea-4e3b-a66d-13558d97b43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495138389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.495138389
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1123566495
Short name T13
Test name
Test status
Simulation time 1290757535 ps
CPU time 13.23 seconds
Started Jun 04 12:48:07 PM PDT 24
Finished Jun 04 12:48:21 PM PDT 24
Peak memory 210988 kb
Host smart-86bc92f4-cdae-4b2c-8717-7cde05ccd61d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123566495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1123566495
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1448810540
Short name T175
Test name
Test status
Simulation time 3134058514 ps
CPU time 37.51 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 12:48:48 PM PDT 24
Peak memory 213032 kb
Host smart-37034b22-c68d-463b-8509-012b905af76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448810540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1448810540
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1630366672
Short name T96
Test name
Test status
Simulation time 7200002805 ps
CPU time 18.9 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:19 PM PDT 24
Peak memory 211068 kb
Host smart-571265f7-4318-4c7b-b4a8-ac7cf64b8d4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630366672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1630366672
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4092898389
Short name T225
Test name
Test status
Simulation time 6733935428 ps
CPU time 13.98 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:16 PM PDT 24
Peak memory 211156 kb
Host smart-7863d39f-887c-442c-81a0-9032adcbb404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092898389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4092898389
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1761616565
Short name T235
Test name
Test status
Simulation time 110411818594 ps
CPU time 554.86 seconds
Started Jun 04 12:47:57 PM PDT 24
Finished Jun 04 12:57:14 PM PDT 24
Peak memory 224652 kb
Host smart-bb6823a7-756a-4614-88e1-6f2ee78a5430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761616565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1761616565
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.665713825
Short name T58
Test name
Test status
Simulation time 28621882360 ps
CPU time 33.18 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:36 PM PDT 24
Peak memory 212160 kb
Host smart-edb0f7a1-bc48-49d0-9b46-086f46628e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665713825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.665713825
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3372877813
Short name T200
Test name
Test status
Simulation time 1519096649 ps
CPU time 11.34 seconds
Started Jun 04 12:48:03 PM PDT 24
Finished Jun 04 12:48:15 PM PDT 24
Peak memory 211036 kb
Host smart-32b33fdd-b751-4230-aab4-b39657947b99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372877813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3372877813
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4282735718
Short name T230
Test name
Test status
Simulation time 9633486325 ps
CPU time 24.6 seconds
Started Jun 04 12:47:57 PM PDT 24
Finished Jun 04 12:48:24 PM PDT 24
Peak memory 219452 kb
Host smart-4a096754-c307-4d81-ae58-2a08b7be43f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282735718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4282735718
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2270235553
Short name T160
Test name
Test status
Simulation time 795053603 ps
CPU time 22.19 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:23 PM PDT 24
Peak memory 214520 kb
Host smart-81d5a9be-087b-459f-930f-a07df2cd9c06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270235553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2270235553
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2504039855
Short name T292
Test name
Test status
Simulation time 415511477 ps
CPU time 4.26 seconds
Started Jun 04 12:48:00 PM PDT 24
Finished Jun 04 12:48:06 PM PDT 24
Peak memory 211056 kb
Host smart-a188968c-c582-44fd-ba1b-69cbd8596afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504039855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2504039855
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2762805477
Short name T27
Test name
Test status
Simulation time 132844317740 ps
CPU time 245.99 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:52:07 PM PDT 24
Peak memory 230872 kb
Host smart-18b5c80b-11b3-4f03-b174-234377b44bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762805477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2762805477
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2671539341
Short name T264
Test name
Test status
Simulation time 7840843705 ps
CPU time 32.97 seconds
Started Jun 04 12:47:56 PM PDT 24
Finished Jun 04 12:48:30 PM PDT 24
Peak memory 212216 kb
Host smart-5a6f11a5-e5ca-4010-aa91-966dc0b945bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671539341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2671539341
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1887584692
Short name T210
Test name
Test status
Simulation time 12370092770 ps
CPU time 14.24 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:17 PM PDT 24
Peak memory 211112 kb
Host smart-cf56698b-d5b0-46e0-80ab-57289dba8885
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887584692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1887584692
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2430755655
Short name T209
Test name
Test status
Simulation time 998368049 ps
CPU time 13.44 seconds
Started Jun 04 12:47:57 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 212720 kb
Host smart-2b52d62c-a8b6-44e5-b3ef-5a1afdb1692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430755655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2430755655
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2301282957
Short name T224
Test name
Test status
Simulation time 2651134930 ps
CPU time 31.52 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:34 PM PDT 24
Peak memory 213688 kb
Host smart-8f71d786-21dc-477e-9e50-bd81fe75666c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301282957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2301282957
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2800186899
Short name T212
Test name
Test status
Simulation time 27822122159 ps
CPU time 12.9 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 211232 kb
Host smart-1cd457bb-198d-43a3-8baa-d352522974c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800186899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2800186899
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2220737571
Short name T213
Test name
Test status
Simulation time 46065508213 ps
CPU time 261.72 seconds
Started Jun 04 12:48:03 PM PDT 24
Finished Jun 04 12:52:26 PM PDT 24
Peak memory 237316 kb
Host smart-5dd13891-ea90-4fdd-8c4f-5801f7091531
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220737571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2220737571
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1774034099
Short name T186
Test name
Test status
Simulation time 8867499078 ps
CPU time 22.99 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 12:48:37 PM PDT 24
Peak memory 212240 kb
Host smart-3035800b-a486-4a47-8ed9-1ee53c57a4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774034099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1774034099
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3056958353
Short name T272
Test name
Test status
Simulation time 1129904251 ps
CPU time 8.41 seconds
Started Jun 04 12:48:03 PM PDT 24
Finished Jun 04 12:48:13 PM PDT 24
Peak memory 211044 kb
Host smart-290ca0bc-d79b-48c7-b580-5d625ce29369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056958353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3056958353
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1095824696
Short name T159
Test name
Test status
Simulation time 1898864028 ps
CPU time 21.55 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:22 PM PDT 24
Peak memory 212872 kb
Host smart-452d5b50-97eb-4985-babb-075ceb55d917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095824696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1095824696
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3803018867
Short name T305
Test name
Test status
Simulation time 3701484986 ps
CPU time 16.16 seconds
Started Jun 04 12:48:04 PM PDT 24
Finished Jun 04 12:48:21 PM PDT 24
Peak memory 212188 kb
Host smart-cedd0881-3533-40cb-8b74-d18f916e8fce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803018867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3803018867
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2479038106
Short name T56
Test name
Test status
Simulation time 159429700558 ps
CPU time 3334.98 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 01:43:39 PM PDT 24
Peak memory 251728 kb
Host smart-82ca92ab-859d-419d-b92e-4b45bbf136f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479038106 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2479038106
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1136320685
Short name T267
Test name
Test status
Simulation time 555076942 ps
CPU time 7.94 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 12:48:19 PM PDT 24
Peak memory 211040 kb
Host smart-98c66a88-3dfd-4994-a69e-6db464475f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136320685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1136320685
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2342042790
Short name T50
Test name
Test status
Simulation time 8309493535 ps
CPU time 131.19 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:50:21 PM PDT 24
Peak memory 237860 kb
Host smart-06e54fa3-4744-4637-9497-5a3918d0aa3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342042790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2342042790
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.747107477
Short name T327
Test name
Test status
Simulation time 12241052273 ps
CPU time 20.97 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:30 PM PDT 24
Peak memory 212056 kb
Host smart-8217ba88-34a0-4a65-98f3-cc607a057fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747107477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.747107477
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2577043560
Short name T321
Test name
Test status
Simulation time 8278934420 ps
CPU time 18.03 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:19 PM PDT 24
Peak memory 211208 kb
Host smart-0325145e-a5e2-4318-b5b8-24c908ce8d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577043560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2577043560
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4102640289
Short name T241
Test name
Test status
Simulation time 812066631 ps
CPU time 10.42 seconds
Started Jun 04 12:48:01 PM PDT 24
Finished Jun 04 12:48:13 PM PDT 24
Peak memory 213304 kb
Host smart-52f42797-9cff-41b6-9c19-cdff423abe6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102640289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4102640289
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2853309256
Short name T9
Test name
Test status
Simulation time 1846453987 ps
CPU time 15.42 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:16 PM PDT 24
Peak memory 214032 kb
Host smart-66a5cfc9-f89f-4436-a084-435889fb1141
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853309256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2853309256
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1395882167
Short name T187
Test name
Test status
Simulation time 348073439 ps
CPU time 4.18 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:13 PM PDT 24
Peak memory 211060 kb
Host smart-a6f83ae3-cb70-46c0-969c-ad0f87981f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395882167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1395882167
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1507287518
Short name T315
Test name
Test status
Simulation time 90919316270 ps
CPU time 236.74 seconds
Started Jun 04 12:48:13 PM PDT 24
Finished Jun 04 12:52:11 PM PDT 24
Peak memory 236884 kb
Host smart-a4b0e825-ed2f-4ae4-8467-846811924e77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507287518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1507287518
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2926934865
Short name T136
Test name
Test status
Simulation time 2059920481 ps
CPU time 13.03 seconds
Started Jun 04 12:48:12 PM PDT 24
Finished Jun 04 12:48:27 PM PDT 24
Peak memory 211772 kb
Host smart-7c92596e-a275-412b-ac9a-dac44a86a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926934865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2926934865
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3362739514
Short name T288
Test name
Test status
Simulation time 1075949319 ps
CPU time 12.06 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 12:48:23 PM PDT 24
Peak memory 210972 kb
Host smart-1fd02416-48f0-4fb8-90be-5b85582a5ec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362739514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3362739514
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3059903586
Short name T191
Test name
Test status
Simulation time 16176459154 ps
CPU time 36.27 seconds
Started Jun 04 12:48:07 PM PDT 24
Finished Jun 04 12:48:44 PM PDT 24
Peak memory 219428 kb
Host smart-aa3c8ec4-55e5-428b-853d-7064c9aa2cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059903586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3059903586
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1145670362
Short name T23
Test name
Test status
Simulation time 26878800167 ps
CPU time 57.73 seconds
Started Jun 04 12:48:11 PM PDT 24
Finished Jun 04 12:49:10 PM PDT 24
Peak memory 219388 kb
Host smart-974bd6a9-79f0-4c36-ac00-e8f121cc399b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145670362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1145670362
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4231523649
Short name T307
Test name
Test status
Simulation time 123115980 ps
CPU time 4.61 seconds
Started Jun 04 12:48:07 PM PDT 24
Finished Jun 04 12:48:13 PM PDT 24
Peak memory 211088 kb
Host smart-96dc700b-174f-45dd-a1c0-25dbb0d5ce0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231523649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4231523649
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2811164477
Short name T329
Test name
Test status
Simulation time 115733349058 ps
CPU time 440.88 seconds
Started Jun 04 12:48:13 PM PDT 24
Finished Jun 04 12:55:35 PM PDT 24
Peak memory 226328 kb
Host smart-bafde33d-a9d7-4ba0-952b-dd282655a7cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811164477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2811164477
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.822842403
Short name T290
Test name
Test status
Simulation time 16370325548 ps
CPU time 25.58 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:35 PM PDT 24
Peak memory 211312 kb
Host smart-45122875-4cba-44ea-887e-a9a9a3684ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822842403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.822842403
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3813455096
Short name T313
Test name
Test status
Simulation time 14273422330 ps
CPU time 11.36 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:21 PM PDT 24
Peak memory 211240 kb
Host smart-beb17a36-1f89-433b-91f1-9bea237fe9c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813455096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3813455096
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.632987863
Short name T219
Test name
Test status
Simulation time 7171426438 ps
CPU time 28.74 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 12:48:40 PM PDT 24
Peak memory 214224 kb
Host smart-9b98c217-a90a-4d6e-b633-cb99fd1adaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632987863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.632987863
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2473387230
Short name T150
Test name
Test status
Simulation time 8487250113 ps
CPU time 28.39 seconds
Started Jun 04 12:48:11 PM PDT 24
Finished Jun 04 12:48:41 PM PDT 24
Peak memory 219252 kb
Host smart-15f7477c-879b-479e-93e7-1d8ef113a72a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473387230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2473387230
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3146766305
Short name T104
Test name
Test status
Simulation time 3748102271 ps
CPU time 9.95 seconds
Started Jun 04 12:48:13 PM PDT 24
Finished Jun 04 12:48:24 PM PDT 24
Peak memory 211092 kb
Host smart-676d17e3-44c2-4453-b6de-ce748c629512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146766305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3146766305
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2864092930
Short name T174
Test name
Test status
Simulation time 7192872739 ps
CPU time 100.34 seconds
Started Jun 04 12:48:05 PM PDT 24
Finished Jun 04 12:49:46 PM PDT 24
Peak memory 212516 kb
Host smart-3602cd86-51d0-436f-a1ae-39baf489c9ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864092930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2864092930
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1277589128
Short name T344
Test name
Test status
Simulation time 13545079349 ps
CPU time 28.45 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 12:48:39 PM PDT 24
Peak memory 212112 kb
Host smart-692a9ffd-8377-4398-8e54-2492339ed536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277589128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1277589128
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3949903041
Short name T11
Test name
Test status
Simulation time 6737886833 ps
CPU time 15.72 seconds
Started Jun 04 12:48:12 PM PDT 24
Finished Jun 04 12:48:29 PM PDT 24
Peak memory 211152 kb
Host smart-585385cb-8ab3-437f-9f82-d5076848ca85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949903041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3949903041
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2540861836
Short name T3
Test name
Test status
Simulation time 3270432900 ps
CPU time 18.98 seconds
Started Jun 04 12:48:06 PM PDT 24
Finished Jun 04 12:48:26 PM PDT 24
Peak memory 213548 kb
Host smart-1195cd93-c997-41aa-95b6-d41090782f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540861836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2540861836
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3100003427
Short name T279
Test name
Test status
Simulation time 97701055 ps
CPU time 6.74 seconds
Started Jun 04 12:48:14 PM PDT 24
Finished Jun 04 12:48:21 PM PDT 24
Peak memory 210968 kb
Host smart-f91828d8-f2b1-4cad-a0cd-de90dff14ca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100003427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3100003427
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.833256358
Short name T17
Test name
Test status
Simulation time 65701170706 ps
CPU time 3144.56 seconds
Started Jun 04 12:48:11 PM PDT 24
Finished Jun 04 01:40:38 PM PDT 24
Peak memory 235824 kb
Host smart-d47c3da9-c241-44b9-9d22-7dd6ba266cae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833256358 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.833256358
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3764995597
Short name T251
Test name
Test status
Simulation time 2861949415 ps
CPU time 7.9 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 12:48:18 PM PDT 24
Peak memory 211152 kb
Host smart-00b0ce2e-fa6d-43d2-84e1-4956133d5411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764995597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3764995597
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3589672636
Short name T245
Test name
Test status
Simulation time 3650094897 ps
CPU time 100.44 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 12:49:52 PM PDT 24
Peak memory 232700 kb
Host smart-c63a40a1-b253-4889-80d0-c5dc49cdc857
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589672636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3589672636
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1033784480
Short name T207
Test name
Test status
Simulation time 2737495845 ps
CPU time 26.11 seconds
Started Jun 04 12:48:06 PM PDT 24
Finished Jun 04 12:48:33 PM PDT 24
Peak memory 211764 kb
Host smart-6a12d413-0d19-4e51-8f4f-32c74a055a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033784480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1033784480
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2801999038
Short name T304
Test name
Test status
Simulation time 4506700691 ps
CPU time 8.99 seconds
Started Jun 04 12:48:07 PM PDT 24
Finished Jun 04 12:48:17 PM PDT 24
Peak memory 211264 kb
Host smart-87a8b030-239b-4c63-b961-80a0d6c44fb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801999038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2801999038
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1681625582
Short name T194
Test name
Test status
Simulation time 1116800940 ps
CPU time 10.17 seconds
Started Jun 04 12:48:12 PM PDT 24
Finished Jun 04 12:48:24 PM PDT 24
Peak memory 213636 kb
Host smart-645acabd-4097-4e22-a8c5-eed088437372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681625582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1681625582
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2172151880
Short name T302
Test name
Test status
Simulation time 20408087242 ps
CPU time 60.87 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 12:49:12 PM PDT 24
Peak memory 215916 kb
Host smart-7517cb63-35b7-489e-b301-8bb19754fd31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172151880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2172151880
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2397628380
Short name T188
Test name
Test status
Simulation time 5064720920 ps
CPU time 12.35 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 12:48:23 PM PDT 24
Peak memory 211180 kb
Host smart-54fdb472-81dd-4943-bcc4-933b5be0d9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397628380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2397628380
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1344549840
Short name T217
Test name
Test status
Simulation time 32208410086 ps
CPU time 273.04 seconds
Started Jun 04 12:48:26 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 212428 kb
Host smart-462387aa-86f1-419a-b2f8-ac4a2b14117a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344549840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1344549840
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3424682937
Short name T102
Test name
Test status
Simulation time 13037774602 ps
CPU time 29.56 seconds
Started Jun 04 12:48:07 PM PDT 24
Finished Jun 04 12:48:38 PM PDT 24
Peak memory 211800 kb
Host smart-7d487cff-b646-4809-9796-03f3af6a706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424682937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3424682937
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4034316861
Short name T265
Test name
Test status
Simulation time 7931316978 ps
CPU time 16.64 seconds
Started Jun 04 12:48:06 PM PDT 24
Finished Jun 04 12:48:23 PM PDT 24
Peak memory 211144 kb
Host smart-0b352ceb-ed58-4774-89eb-d4b46f0dbc0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034316861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4034316861
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.33982098
Short name T82
Test name
Test status
Simulation time 10879139562 ps
CPU time 26.55 seconds
Started Jun 04 12:48:06 PM PDT 24
Finished Jun 04 12:48:33 PM PDT 24
Peak memory 213716 kb
Host smart-f20d7c2e-0421-409b-ad1e-05ac164e11f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33982098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.33982098
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4244352662
Short name T266
Test name
Test status
Simulation time 947263882 ps
CPU time 25.46 seconds
Started Jun 04 12:48:16 PM PDT 24
Finished Jun 04 12:48:42 PM PDT 24
Peak memory 215804 kb
Host smart-0a130883-8cea-4797-b7a4-e9f63271b037
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244352662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4244352662
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2024440900
Short name T166
Test name
Test status
Simulation time 858059263 ps
CPU time 5.94 seconds
Started Jun 04 12:47:45 PM PDT 24
Finished Jun 04 12:47:53 PM PDT 24
Peak memory 210996 kb
Host smart-78b52588-338d-41aa-91fa-ff12f4dce746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024440900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2024440900
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3446675982
Short name T201
Test name
Test status
Simulation time 15724172808 ps
CPU time 33.37 seconds
Started Jun 04 12:47:35 PM PDT 24
Finished Jun 04 12:48:10 PM PDT 24
Peak memory 212060 kb
Host smart-bc8a98aa-6a13-42c0-b7ae-4a73d1c4b6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446675982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3446675982
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2377669854
Short name T158
Test name
Test status
Simulation time 5604703874 ps
CPU time 13.63 seconds
Started Jun 04 12:47:46 PM PDT 24
Finished Jun 04 12:48:01 PM PDT 24
Peak memory 211192 kb
Host smart-995f30bf-11d0-4e2d-8ab5-b9bc44ba6e8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377669854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2377669854
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.469345634
Short name T34
Test name
Test status
Simulation time 1372609801 ps
CPU time 60.87 seconds
Started Jun 04 12:47:48 PM PDT 24
Finished Jun 04 12:48:50 PM PDT 24
Peak memory 233336 kb
Host smart-cd3c008a-4630-44f8-a9c0-7fdf764f7e04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469345634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.469345634
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.65996214
Short name T185
Test name
Test status
Simulation time 2996564519 ps
CPU time 27.32 seconds
Started Jun 04 12:47:52 PM PDT 24
Finished Jun 04 12:48:21 PM PDT 24
Peak memory 212984 kb
Host smart-61815ded-26c2-4fed-bbbc-89aa1f735a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65996214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.65996214
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3560369214
Short name T260
Test name
Test status
Simulation time 1448503375 ps
CPU time 12.62 seconds
Started Jun 04 12:47:36 PM PDT 24
Finished Jun 04 12:47:50 PM PDT 24
Peak memory 214140 kb
Host smart-2c171446-6910-4461-b577-4cb1d78176aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560369214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3560369214
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3342645507
Short name T294
Test name
Test status
Simulation time 2286067035 ps
CPU time 10.93 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:20 PM PDT 24
Peak memory 211032 kb
Host smart-3d6b19ed-22e2-44cc-8754-ea5446161897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342645507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3342645507
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2619923275
Short name T222
Test name
Test status
Simulation time 20976119608 ps
CPU time 210.07 seconds
Started Jun 04 12:48:11 PM PDT 24
Finished Jun 04 12:51:42 PM PDT 24
Peak memory 228556 kb
Host smart-961cd220-f191-4d2d-b62e-eb9f57d38ae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619923275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2619923275
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.663006358
Short name T345
Test name
Test status
Simulation time 1653403111 ps
CPU time 20.93 seconds
Started Jun 04 12:48:18 PM PDT 24
Finished Jun 04 12:48:40 PM PDT 24
Peak memory 211892 kb
Host smart-27fa00ed-9c68-4d47-b8a2-4316ba6f59d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663006358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.663006358
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.536659869
Short name T155
Test name
Test status
Simulation time 2687593651 ps
CPU time 9.87 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 12:48:21 PM PDT 24
Peak memory 211144 kb
Host smart-95e04631-cd63-4025-be6f-759e36feb7b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536659869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.536659869
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1526299169
Short name T62
Test name
Test status
Simulation time 253397559 ps
CPU time 10.33 seconds
Started Jun 04 12:48:33 PM PDT 24
Finished Jun 04 12:48:44 PM PDT 24
Peak memory 213388 kb
Host smart-edf79424-35cf-499d-bbeb-2faa8b1cf909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526299169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1526299169
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4031285073
Short name T240
Test name
Test status
Simulation time 7449435018 ps
CPU time 90.5 seconds
Started Jun 04 12:48:05 PM PDT 24
Finished Jun 04 12:49:36 PM PDT 24
Peak memory 219248 kb
Host smart-c88e8c24-de49-454f-bba9-f021b03ca9c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031285073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4031285073
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1476961708
Short name T252
Test name
Test status
Simulation time 4465830755 ps
CPU time 10.86 seconds
Started Jun 04 12:48:12 PM PDT 24
Finished Jun 04 12:48:25 PM PDT 24
Peak memory 211160 kb
Host smart-8211f022-2c69-47b0-bffd-b2f7bd77c0e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476961708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1476961708
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.372438148
Short name T293
Test name
Test status
Simulation time 645415633260 ps
CPU time 363.29 seconds
Started Jun 04 12:48:06 PM PDT 24
Finished Jun 04 12:54:10 PM PDT 24
Peak memory 212492 kb
Host smart-b2e95f12-5bab-4d1c-9164-dbb7cade9f43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372438148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.372438148
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1182323380
Short name T41
Test name
Test status
Simulation time 3194934002 ps
CPU time 28.69 seconds
Started Jun 04 12:48:13 PM PDT 24
Finished Jun 04 12:48:43 PM PDT 24
Peak memory 211772 kb
Host smart-e516fcae-2144-470b-96ca-c99c13d238dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182323380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1182323380
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2302431765
Short name T114
Test name
Test status
Simulation time 95893453 ps
CPU time 5.76 seconds
Started Jun 04 12:48:13 PM PDT 24
Finished Jun 04 12:48:20 PM PDT 24
Peak memory 211056 kb
Host smart-d1de4374-fb6b-48a6-95c5-dce2fa6faf32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302431765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2302431765
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1112697107
Short name T319
Test name
Test status
Simulation time 1125364034 ps
CPU time 18.08 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:28 PM PDT 24
Peak memory 219224 kb
Host smart-620f1022-67c4-4ce6-a116-dcacc8c7c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112697107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1112697107
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.419024702
Short name T152
Test name
Test status
Simulation time 6150869913 ps
CPU time 32.31 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:41 PM PDT 24
Peak memory 219408 kb
Host smart-5d7f29c5-2167-4dee-a3d9-119b89057bbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419024702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.419024702
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.292681107
Short name T353
Test name
Test status
Simulation time 3447110217 ps
CPU time 14.76 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 12:48:26 PM PDT 24
Peak memory 211160 kb
Host smart-8a58b09b-8502-4fbc-9f35-a5477b169de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292681107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.292681107
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1073974914
Short name T351
Test name
Test status
Simulation time 3378272538 ps
CPU time 105.36 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 12:49:56 PM PDT 24
Peak memory 238448 kb
Host smart-f978d465-d7dd-47c0-8bf2-b5608b3c25ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073974914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1073974914
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3686135443
Short name T21
Test name
Test status
Simulation time 229191907 ps
CPU time 9.4 seconds
Started Jun 04 12:48:06 PM PDT 24
Finished Jun 04 12:48:17 PM PDT 24
Peak memory 211756 kb
Host smart-51b9cbd6-74f2-4725-bebf-2100b6e53c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686135443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3686135443
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3144478422
Short name T295
Test name
Test status
Simulation time 8464998424 ps
CPU time 17.46 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 12:48:28 PM PDT 24
Peak memory 211172 kb
Host smart-044ccbf9-993d-4f1e-b2c9-1875e034fb27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144478422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3144478422
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4244913214
Short name T358
Test name
Test status
Simulation time 4154308965 ps
CPU time 34.05 seconds
Started Jun 04 12:48:36 PM PDT 24
Finished Jun 04 12:49:11 PM PDT 24
Peak memory 211752 kb
Host smart-ad776af0-6c72-4d62-8744-7203b2cb1eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244913214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4244913214
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.475766568
Short name T4
Test name
Test status
Simulation time 7472648789 ps
CPU time 24.21 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:33 PM PDT 24
Peak memory 219312 kb
Host smart-d7228407-5d1e-407b-9989-780c5669c65c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475766568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.475766568
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1463076814
Short name T318
Test name
Test status
Simulation time 1739583420 ps
CPU time 14.23 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 12:48:25 PM PDT 24
Peak memory 211168 kb
Host smart-ec120c7d-12f5-42f1-9b05-13fb9527b04e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463076814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1463076814
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1412193739
Short name T30
Test name
Test status
Simulation time 24374527406 ps
CPU time 139.12 seconds
Started Jun 04 12:48:33 PM PDT 24
Finished Jun 04 12:50:54 PM PDT 24
Peak memory 213232 kb
Host smart-c4b7108a-c06f-449f-8318-0e77ea5c0cae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412193739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1412193739
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4170265407
Short name T259
Test name
Test status
Simulation time 11210167621 ps
CPU time 25.56 seconds
Started Jun 04 12:48:09 PM PDT 24
Finished Jun 04 12:48:36 PM PDT 24
Peak memory 212540 kb
Host smart-71ac49de-2c75-47a2-87ba-b41edf1d5325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170265407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4170265407
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.515675329
Short name T42
Test name
Test status
Simulation time 3512263427 ps
CPU time 11.24 seconds
Started Jun 04 12:48:12 PM PDT 24
Finished Jun 04 12:48:25 PM PDT 24
Peak memory 211148 kb
Host smart-e65f9c21-c571-4e77-96d8-68b66649972f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515675329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.515675329
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3640538474
Short name T254
Test name
Test status
Simulation time 2788079274 ps
CPU time 14.79 seconds
Started Jun 04 12:48:41 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 213440 kb
Host smart-cee78b38-62ad-44cd-a741-ec012b6bf0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640538474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3640538474
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2865182778
Short name T333
Test name
Test status
Simulation time 1803915007 ps
CPU time 25.59 seconds
Started Jun 04 12:48:12 PM PDT 24
Finished Jun 04 12:48:39 PM PDT 24
Peak memory 213988 kb
Host smart-3fbf2817-a46e-436f-964a-060b97f8b09a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865182778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2865182778
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2537888144
Short name T18
Test name
Test status
Simulation time 68699317703 ps
CPU time 922.12 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 01:03:33 PM PDT 24
Peak memory 230108 kb
Host smart-aba9515f-aced-4f77-bf0a-4ccef7675671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537888144 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2537888144
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3457633928
Short name T97
Test name
Test status
Simulation time 815463369 ps
CPU time 9.51 seconds
Started Jun 04 12:48:20 PM PDT 24
Finished Jun 04 12:48:31 PM PDT 24
Peak memory 211032 kb
Host smart-48344c28-89c8-46d1-9475-591ae7da8876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457633928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3457633928
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2340697101
Short name T29
Test name
Test status
Simulation time 2993971374 ps
CPU time 143.35 seconds
Started Jun 04 12:48:10 PM PDT 24
Finished Jun 04 12:50:35 PM PDT 24
Peak memory 229776 kb
Host smart-9087a6c3-1bf2-4aa8-8be6-c02da20a1aed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340697101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2340697101
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3640272187
Short name T332
Test name
Test status
Simulation time 4062225862 ps
CPU time 32.13 seconds
Started Jun 04 12:48:11 PM PDT 24
Finished Jun 04 12:48:44 PM PDT 24
Peak memory 211768 kb
Host smart-efe2ad86-f350-4927-91ed-f2cf78fb4af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640272187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3640272187
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3538839748
Short name T157
Test name
Test status
Simulation time 11766893028 ps
CPU time 15.75 seconds
Started Jun 04 12:48:33 PM PDT 24
Finished Jun 04 12:48:49 PM PDT 24
Peak memory 211172 kb
Host smart-385ae5fe-2c48-43f4-839b-ebcb62bbf37b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538839748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3538839748
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2725712973
Short name T60
Test name
Test status
Simulation time 358387709 ps
CPU time 10.27 seconds
Started Jun 04 12:48:08 PM PDT 24
Finished Jun 04 12:48:20 PM PDT 24
Peak memory 213400 kb
Host smart-22187b50-e311-4e45-8fc8-3328420c9977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725712973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2725712973
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4096204246
Short name T142
Test name
Test status
Simulation time 2981486713 ps
CPU time 38.67 seconds
Started Jun 04 12:48:36 PM PDT 24
Finished Jun 04 12:49:16 PM PDT 24
Peak memory 219256 kb
Host smart-c7b1d45e-88c3-457f-80e3-5f3e7765b4e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096204246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4096204246
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.4004005970
Short name T218
Test name
Test status
Simulation time 290524934372 ps
CPU time 8239.86 seconds
Started Jun 04 12:48:27 PM PDT 24
Finished Jun 04 03:05:49 PM PDT 24
Peak memory 230940 kb
Host smart-7883a1cd-7a11-41b0-a39f-40267300080b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004005970 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.4004005970
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2943538694
Short name T354
Test name
Test status
Simulation time 1109124334 ps
CPU time 6.29 seconds
Started Jun 04 12:48:20 PM PDT 24
Finished Jun 04 12:48:28 PM PDT 24
Peak memory 211032 kb
Host smart-baf9bdad-303b-4ede-850f-33f7a4a2c360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943538694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2943538694
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2082330831
Short name T338
Test name
Test status
Simulation time 13073727303 ps
CPU time 159.58 seconds
Started Jun 04 12:48:18 PM PDT 24
Finished Jun 04 12:50:58 PM PDT 24
Peak memory 233844 kb
Host smart-fdf1c060-3c11-40df-907a-33af40af922d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082330831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2082330831
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3256223738
Short name T205
Test name
Test status
Simulation time 2780895645 ps
CPU time 18.79 seconds
Started Jun 04 12:48:15 PM PDT 24
Finished Jun 04 12:48:34 PM PDT 24
Peak memory 211908 kb
Host smart-32b63261-2cb2-48e8-b63b-b55bd16e2eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256223738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3256223738
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3566770854
Short name T143
Test name
Test status
Simulation time 1438779843 ps
CPU time 14.36 seconds
Started Jun 04 12:48:21 PM PDT 24
Finished Jun 04 12:48:36 PM PDT 24
Peak memory 211128 kb
Host smart-b5ebc111-6047-4810-aa0e-cd3c791c88c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566770854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3566770854
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1342223776
Short name T101
Test name
Test status
Simulation time 8893869086 ps
CPU time 23.19 seconds
Started Jun 04 12:48:18 PM PDT 24
Finished Jun 04 12:48:42 PM PDT 24
Peak memory 213988 kb
Host smart-687e51f3-1410-4d28-b5de-20b1c32a135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342223776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1342223776
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2914531308
Short name T271
Test name
Test status
Simulation time 57160599952 ps
CPU time 77.27 seconds
Started Jun 04 12:48:32 PM PDT 24
Finished Jun 04 12:49:51 PM PDT 24
Peak memory 219240 kb
Host smart-7583d189-3798-407f-88db-afa5477ce9bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914531308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2914531308
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3807913632
Short name T57
Test name
Test status
Simulation time 384225135753 ps
CPU time 1471.45 seconds
Started Jun 04 12:48:17 PM PDT 24
Finished Jun 04 01:12:50 PM PDT 24
Peak memory 235852 kb
Host smart-2cb60ae8-5d0e-4fd2-9d1f-08e254a8cdc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807913632 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3807913632
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3047019238
Short name T167
Test name
Test status
Simulation time 5352717754 ps
CPU time 11.97 seconds
Started Jun 04 12:48:15 PM PDT 24
Finished Jun 04 12:48:28 PM PDT 24
Peak memory 211196 kb
Host smart-8bc44d22-98c0-495b-8c20-fd7a2bb40ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047019238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3047019238
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1734693427
Short name T53
Test name
Test status
Simulation time 64912542272 ps
CPU time 342.12 seconds
Started Jun 04 12:48:17 PM PDT 24
Finished Jun 04 12:54:00 PM PDT 24
Peak memory 226580 kb
Host smart-80a9dc7e-b143-4615-b1d4-7288e68472c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734693427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1734693427
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1558298662
Short name T280
Test name
Test status
Simulation time 670391960 ps
CPU time 14.45 seconds
Started Jun 04 12:48:27 PM PDT 24
Finished Jun 04 12:48:43 PM PDT 24
Peak memory 211960 kb
Host smart-56a755b6-eecc-45c7-bd5c-61dfe4538d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558298662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1558298662
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1851435185
Short name T140
Test name
Test status
Simulation time 7660250815 ps
CPU time 15.64 seconds
Started Jun 04 12:48:34 PM PDT 24
Finished Jun 04 12:48:51 PM PDT 24
Peak memory 211120 kb
Host smart-10cedcf3-3646-4f04-bf4b-e4b1c62734fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851435185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1851435185
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.394496352
Short name T283
Test name
Test status
Simulation time 12016046624 ps
CPU time 17.61 seconds
Started Jun 04 12:48:20 PM PDT 24
Finished Jun 04 12:48:39 PM PDT 24
Peak memory 219292 kb
Host smart-0fb35253-2e97-42c1-b4d0-7cbdccda2ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394496352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.394496352
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.4128543413
Short name T249
Test name
Test status
Simulation time 175071579 ps
CPU time 4.99 seconds
Started Jun 04 12:48:17 PM PDT 24
Finished Jun 04 12:48:23 PM PDT 24
Peak memory 211028 kb
Host smart-42d33094-99b1-4434-af78-c009e20edb8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128543413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.4128543413
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3393311470
Short name T154
Test name
Test status
Simulation time 1629446667 ps
CPU time 6.86 seconds
Started Jun 04 12:48:19 PM PDT 24
Finished Jun 04 12:48:27 PM PDT 24
Peak memory 211168 kb
Host smart-2b5f9f81-6ff6-4cbf-a002-4796ce2e1aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393311470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3393311470
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4010369410
Short name T206
Test name
Test status
Simulation time 11344219943 ps
CPU time 161.87 seconds
Started Jun 04 12:48:23 PM PDT 24
Finished Jun 04 12:51:06 PM PDT 24
Peak memory 225568 kb
Host smart-73ab4129-b126-43c7-bf97-b4d2277e8d69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010369410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4010369410
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3701500636
Short name T303
Test name
Test status
Simulation time 501098060 ps
CPU time 11.29 seconds
Started Jun 04 12:48:23 PM PDT 24
Finished Jun 04 12:48:35 PM PDT 24
Peak memory 211776 kb
Host smart-1cfe7719-f3fd-4212-b88b-c37a45ebfb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701500636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3701500636
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1677355969
Short name T135
Test name
Test status
Simulation time 994599811 ps
CPU time 8.72 seconds
Started Jun 04 12:48:17 PM PDT 24
Finished Jun 04 12:48:26 PM PDT 24
Peak memory 211120 kb
Host smart-de51d1fd-3f45-4ce5-95c6-00a63bb61f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677355969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1677355969
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2527476566
Short name T184
Test name
Test status
Simulation time 760454235 ps
CPU time 10.11 seconds
Started Jun 04 12:48:18 PM PDT 24
Finished Jun 04 12:48:29 PM PDT 24
Peak memory 213764 kb
Host smart-0bc22824-0d62-439a-8bda-3c168895c78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527476566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2527476566
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.80965997
Short name T237
Test name
Test status
Simulation time 6186015911 ps
CPU time 46.63 seconds
Started Jun 04 12:48:15 PM PDT 24
Finished Jun 04 12:49:03 PM PDT 24
Peak memory 217120 kb
Host smart-db56d94e-6c57-4e11-bc1d-a32362c6a115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80965997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.rom_ctrl_stress_all.80965997
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1914941190
Short name T301
Test name
Test status
Simulation time 6530238390 ps
CPU time 13.87 seconds
Started Jun 04 12:48:18 PM PDT 24
Finished Jun 04 12:48:32 PM PDT 24
Peak memory 211104 kb
Host smart-7f17e2af-4460-4c58-99bb-548ad96e36f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914941190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1914941190
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3662536187
Short name T49
Test name
Test status
Simulation time 162123847982 ps
CPU time 177.84 seconds
Started Jun 04 12:48:20 PM PDT 24
Finished Jun 04 12:51:19 PM PDT 24
Peak memory 212420 kb
Host smart-c21a64af-6a4c-44c7-b347-6ead4c320475
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662536187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3662536187
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4223755074
Short name T312
Test name
Test status
Simulation time 2514565406 ps
CPU time 17.35 seconds
Started Jun 04 12:48:17 PM PDT 24
Finished Jun 04 12:48:35 PM PDT 24
Peak memory 212024 kb
Host smart-a7b21500-d762-4eaf-b7fa-fcba5bd65728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223755074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4223755074
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3626084923
Short name T45
Test name
Test status
Simulation time 3450235290 ps
CPU time 10.69 seconds
Started Jun 04 12:48:16 PM PDT 24
Finished Jun 04 12:48:27 PM PDT 24
Peak memory 211160 kb
Host smart-ea40dee3-cdd9-46ad-b705-7f25976919f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626084923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3626084923
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.4036541451
Short name T144
Test name
Test status
Simulation time 2313549379 ps
CPU time 14.18 seconds
Started Jun 04 12:48:31 PM PDT 24
Finished Jun 04 12:48:46 PM PDT 24
Peak memory 213040 kb
Host smart-4af9fd5f-3686-49e9-9e2e-9baab8cff33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036541451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.4036541451
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.657399870
Short name T46
Test name
Test status
Simulation time 19923817746 ps
CPU time 46.66 seconds
Started Jun 04 12:48:15 PM PDT 24
Finished Jun 04 12:49:03 PM PDT 24
Peak memory 219284 kb
Host smart-d6f8c7af-0615-44c4-bc6f-62768b83f919
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657399870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.657399870
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1848046129
Short name T347
Test name
Test status
Simulation time 1872386155 ps
CPU time 15.69 seconds
Started Jun 04 12:48:16 PM PDT 24
Finished Jun 04 12:48:32 PM PDT 24
Peak memory 211144 kb
Host smart-2091f3f8-38cd-4782-9bbd-c5b268c6b63d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848046129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1848046129
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.160161762
Short name T99
Test name
Test status
Simulation time 20509400743 ps
CPU time 35.28 seconds
Started Jun 04 12:48:23 PM PDT 24
Finished Jun 04 12:48:59 PM PDT 24
Peak memory 212372 kb
Host smart-5de4ae00-9bc7-4b5d-a85d-3a57c87b48e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160161762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.160161762
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.725536381
Short name T138
Test name
Test status
Simulation time 16590847013 ps
CPU time 13.02 seconds
Started Jun 04 12:48:26 PM PDT 24
Finished Jun 04 12:48:40 PM PDT 24
Peak memory 211268 kb
Host smart-055e5240-0d63-4c69-b1be-d21733c8f3fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725536381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.725536381
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2319218817
Short name T148
Test name
Test status
Simulation time 13904433529 ps
CPU time 31.37 seconds
Started Jun 04 12:48:19 PM PDT 24
Finished Jun 04 12:48:51 PM PDT 24
Peak memory 219292 kb
Host smart-a506ec9f-5475-476d-9685-d31bac4330a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319218817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2319218817
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4102208379
Short name T59
Test name
Test status
Simulation time 17500469774 ps
CPU time 40.78 seconds
Started Jun 04 12:48:38 PM PDT 24
Finished Jun 04 12:49:20 PM PDT 24
Peak memory 215920 kb
Host smart-60664ce7-c2a5-4d21-a7c2-9a93217588fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102208379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4102208379
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1225365464
Short name T195
Test name
Test status
Simulation time 4960356568 ps
CPU time 11.73 seconds
Started Jun 04 12:47:39 PM PDT 24
Finished Jun 04 12:47:52 PM PDT 24
Peak memory 211268 kb
Host smart-13476b96-21f4-4140-8b45-8ee7e1d2e04e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225365464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1225365464
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.304213131
Short name T274
Test name
Test status
Simulation time 69888454344 ps
CPU time 245.57 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 236748 kb
Host smart-c9fd02af-5728-408e-af17-33e780e296b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304213131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.304213131
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1804855753
Short name T139
Test name
Test status
Simulation time 953772173 ps
CPU time 16.03 seconds
Started Jun 04 12:47:51 PM PDT 24
Finished Jun 04 12:48:08 PM PDT 24
Peak memory 211908 kb
Host smart-e43c4793-a721-4b28-91f9-b92c2d4f7362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804855753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1804855753
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1048442135
Short name T137
Test name
Test status
Simulation time 116501029 ps
CPU time 5.8 seconds
Started Jun 04 12:47:32 PM PDT 24
Finished Jun 04 12:47:38 PM PDT 24
Peak memory 211080 kb
Host smart-e284e3b0-dc19-40a3-ad67-5f5de530acaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048442135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1048442135
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2145834116
Short name T339
Test name
Test status
Simulation time 7050772976 ps
CPU time 14.59 seconds
Started Jun 04 12:47:35 PM PDT 24
Finished Jun 04 12:47:50 PM PDT 24
Peak memory 219344 kb
Host smart-5900d140-ea22-4edd-b045-d06d999bfe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145834116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2145834116
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1889840181
Short name T342
Test name
Test status
Simulation time 63521600350 ps
CPU time 69.03 seconds
Started Jun 04 12:47:36 PM PDT 24
Finished Jun 04 12:48:47 PM PDT 24
Peak memory 219272 kb
Host smart-5f8b32c1-5083-4d3e-80c2-4bebe23f8c0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889840181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1889840181
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1420976383
Short name T181
Test name
Test status
Simulation time 348194400 ps
CPU time 4.4 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:48:05 PM PDT 24
Peak memory 211084 kb
Host smart-2a7c0035-a634-4cf1-8304-a2aeac4940c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420976383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1420976383
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2374489867
Short name T309
Test name
Test status
Simulation time 37300333704 ps
CPU time 176.66 seconds
Started Jun 04 12:47:51 PM PDT 24
Finished Jun 04 12:50:49 PM PDT 24
Peak memory 237584 kb
Host smart-b7a91ed5-f486-4794-b9f3-9d1306befcf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374489867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2374489867
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2319062823
Short name T26
Test name
Test status
Simulation time 1888233401 ps
CPU time 16.16 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:48:01 PM PDT 24
Peak memory 211672 kb
Host smart-08996bb1-2491-4643-acee-211b6e3fa774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319062823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2319062823
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1336896424
Short name T146
Test name
Test status
Simulation time 2377854651 ps
CPU time 12.24 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 211100 kb
Host smart-6cca4f7c-addb-4d6e-8568-591377526dc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1336896424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1336896424
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1714166541
Short name T242
Test name
Test status
Simulation time 1627887393 ps
CPU time 17.99 seconds
Started Jun 04 12:47:53 PM PDT 24
Finished Jun 04 12:48:12 PM PDT 24
Peak memory 213240 kb
Host smart-f86196b9-b3e7-40e2-92e2-98e29e125ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714166541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1714166541
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2911779163
Short name T314
Test name
Test status
Simulation time 2061258217 ps
CPU time 50.7 seconds
Started Jun 04 12:47:39 PM PDT 24
Finished Jun 04 12:48:30 PM PDT 24
Peak memory 215208 kb
Host smart-782884e0-fee5-4fc2-a0be-d4437414d8bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911779163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2911779163
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.186050714
Short name T250
Test name
Test status
Simulation time 857873563 ps
CPU time 6.03 seconds
Started Jun 04 12:47:42 PM PDT 24
Finished Jun 04 12:47:49 PM PDT 24
Peak memory 211092 kb
Host smart-2dee5d96-3d89-45f6-b15c-552de7d531be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186050714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.186050714
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.267588993
Short name T198
Test name
Test status
Simulation time 66390195233 ps
CPU time 100.74 seconds
Started Jun 04 12:47:59 PM PDT 24
Finished Jun 04 12:49:42 PM PDT 24
Peak memory 237196 kb
Host smart-e02d8148-f9e3-405e-b86b-a9ae428b939b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267588993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.267588993
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1212717111
Short name T365
Test name
Test status
Simulation time 536860066 ps
CPU time 13.11 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:47:58 PM PDT 24
Peak memory 211872 kb
Host smart-8734b82f-8126-4d66-82c9-9523a798dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212717111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1212717111
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1190700126
Short name T291
Test name
Test status
Simulation time 701406438 ps
CPU time 9.45 seconds
Started Jun 04 12:47:57 PM PDT 24
Finished Jun 04 12:48:08 PM PDT 24
Peak memory 211040 kb
Host smart-dbd46be7-0274-42a3-b8e9-bca42a599d62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190700126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1190700126
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2210429393
Short name T357
Test name
Test status
Simulation time 7905287760 ps
CPU time 22.59 seconds
Started Jun 04 12:47:53 PM PDT 24
Finished Jun 04 12:48:17 PM PDT 24
Peak memory 214004 kb
Host smart-3c6aa9a9-061d-4e12-bed0-4331ba07f79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210429393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2210429393
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3900761568
Short name T6
Test name
Test status
Simulation time 8086482005 ps
CPU time 34.16 seconds
Started Jun 04 12:47:54 PM PDT 24
Finished Jun 04 12:48:29 PM PDT 24
Peak memory 217328 kb
Host smart-e0ad9a5e-519c-4ffd-98a7-36560be97f02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900761568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3900761568
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2766707120
Short name T164
Test name
Test status
Simulation time 89071733 ps
CPU time 4.25 seconds
Started Jun 04 12:47:58 PM PDT 24
Finished Jun 04 12:48:05 PM PDT 24
Peak memory 211060 kb
Host smart-b37b0da1-6a3a-4e93-a291-628037b81e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766707120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2766707120
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.260386889
Short name T233
Test name
Test status
Simulation time 15644581007 ps
CPU time 143.37 seconds
Started Jun 04 12:47:48 PM PDT 24
Finished Jun 04 12:50:14 PM PDT 24
Peak memory 239992 kb
Host smart-f92f4b29-0975-4010-a2a0-a3c4b198c82f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260386889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.260386889
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3004115079
Short name T189
Test name
Test status
Simulation time 172233070 ps
CPU time 9.36 seconds
Started Jun 04 12:47:52 PM PDT 24
Finished Jun 04 12:48:03 PM PDT 24
Peak memory 211908 kb
Host smart-2a5179c8-f1cb-4a91-84a0-08294de55255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004115079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3004115079
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2444265156
Short name T12
Test name
Test status
Simulation time 5567319716 ps
CPU time 8.73 seconds
Started Jun 04 12:47:53 PM PDT 24
Finished Jun 04 12:48:03 PM PDT 24
Peak memory 211132 kb
Host smart-1fc78785-a230-49ba-99ab-3eb25c41fab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444265156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2444265156
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.230891410
Short name T147
Test name
Test status
Simulation time 753214345 ps
CPU time 10.12 seconds
Started Jun 04 12:47:47 PM PDT 24
Finished Jun 04 12:47:59 PM PDT 24
Peak memory 219168 kb
Host smart-19db7b65-4efa-4260-bccd-71c799d3344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230891410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.230891410
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1518946002
Short name T80
Test name
Test status
Simulation time 43362910060 ps
CPU time 87.91 seconds
Started Jun 04 12:47:43 PM PDT 24
Finished Jun 04 12:49:12 PM PDT 24
Peak memory 219332 kb
Host smart-8de5e2c3-8686-4b74-9e35-801e2e628e28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518946002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1518946002
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2534022315
Short name T54
Test name
Test status
Simulation time 51789172045 ps
CPU time 1936.46 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 01:20:08 PM PDT 24
Peak memory 236860 kb
Host smart-c6b9a4cf-7e6d-4434-92dc-32ae9cec26c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534022315 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2534022315
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1117005978
Short name T172
Test name
Test status
Simulation time 2822143897 ps
CPU time 13.38 seconds
Started Jun 04 12:47:39 PM PDT 24
Finished Jun 04 12:47:54 PM PDT 24
Peak memory 211108 kb
Host smart-a1d753f3-f4b5-4d17-bc60-b8df25f1de69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117005978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1117005978
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2773836003
Short name T355
Test name
Test status
Simulation time 57521489281 ps
CPU time 135.49 seconds
Started Jun 04 12:47:42 PM PDT 24
Finished Jun 04 12:49:59 PM PDT 24
Peak memory 236960 kb
Host smart-35208779-4ed5-4d07-a8b7-d730d5c49a10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773836003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2773836003
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2532206910
Short name T182
Test name
Test status
Simulation time 694418877 ps
CPU time 9.49 seconds
Started Jun 04 12:47:49 PM PDT 24
Finished Jun 04 12:48:00 PM PDT 24
Peak memory 211908 kb
Host smart-bd79aa0c-6480-44e1-8b39-0f5962d6d1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532206910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2532206910
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2998609414
Short name T289
Test name
Test status
Simulation time 102030172 ps
CPU time 5.63 seconds
Started Jun 04 12:47:57 PM PDT 24
Finished Jun 04 12:48:04 PM PDT 24
Peak memory 211076 kb
Host smart-9fe6e87d-5907-49ab-bf8b-901745ee41da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998609414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2998609414
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2121217152
Short name T149
Test name
Test status
Simulation time 3149925551 ps
CPU time 31.3 seconds
Started Jun 04 12:47:56 PM PDT 24
Finished Jun 04 12:48:28 PM PDT 24
Peak memory 219292 kb
Host smart-1a090137-00f4-4554-a288-aa5f1065fa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121217152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2121217152
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1942826122
Short name T115
Test name
Test status
Simulation time 4980247866 ps
CPU time 50.66 seconds
Started Jun 04 12:47:40 PM PDT 24
Finished Jun 04 12:48:31 PM PDT 24
Peak memory 216932 kb
Host smart-ba13c033-f45a-458c-8c32-f046ca7ffc6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942826122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1942826122
Directory /workspace/9.rom_ctrl_stress_all/latest
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