Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.49 96.97 93.02 97.88 100.00 98.37 98.04 98.14


Total test records in report: 467
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T300 /workspace/coverage/default/19.rom_ctrl_stress_all.2490997543 Jun 05 03:50:26 PM PDT 24 Jun 05 03:50:57 PM PDT 24 3173166078 ps
T301 /workspace/coverage/default/16.rom_ctrl_alert_test.1338147160 Jun 05 03:50:01 PM PDT 24 Jun 05 03:50:16 PM PDT 24 1689686051 ps
T302 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.549680209 Jun 05 03:50:09 PM PDT 24 Jun 05 03:53:39 PM PDT 24 14970272705 ps
T303 /workspace/coverage/default/24.rom_ctrl_smoke.2157651413 Jun 05 03:50:25 PM PDT 24 Jun 05 03:50:58 PM PDT 24 60119714075 ps
T304 /workspace/coverage/default/17.rom_ctrl_smoke.1870071450 Jun 05 03:50:00 PM PDT 24 Jun 05 03:50:17 PM PDT 24 934676797 ps
T305 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.47580666 Jun 05 03:49:49 PM PDT 24 Jun 05 03:51:14 PM PDT 24 1270704514 ps
T306 /workspace/coverage/default/16.rom_ctrl_smoke.3879813708 Jun 05 03:50:02 PM PDT 24 Jun 05 03:50:20 PM PDT 24 4759203161 ps
T36 /workspace/coverage/default/1.rom_ctrl_sec_cm.2733991638 Jun 05 03:49:48 PM PDT 24 Jun 05 03:51:42 PM PDT 24 3645363859 ps
T307 /workspace/coverage/default/44.rom_ctrl_alert_test.2676616653 Jun 05 03:50:39 PM PDT 24 Jun 05 03:50:44 PM PDT 24 377946669 ps
T308 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.601355722 Jun 05 03:50:09 PM PDT 24 Jun 05 03:50:33 PM PDT 24 2585315365 ps
T309 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3910577319 Jun 05 03:50:12 PM PDT 24 Jun 05 03:52:35 PM PDT 24 9566507091 ps
T310 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4180431924 Jun 05 03:50:33 PM PDT 24 Jun 05 03:51:04 PM PDT 24 3538965412 ps
T311 /workspace/coverage/default/5.rom_ctrl_stress_all.4017440831 Jun 05 03:49:51 PM PDT 24 Jun 05 03:50:14 PM PDT 24 933644260 ps
T312 /workspace/coverage/default/18.rom_ctrl_smoke.3454631073 Jun 05 03:50:06 PM PDT 24 Jun 05 03:50:40 PM PDT 24 17526534797 ps
T313 /workspace/coverage/default/44.rom_ctrl_stress_all.3659057391 Jun 05 03:50:46 PM PDT 24 Jun 05 03:51:06 PM PDT 24 7309925303 ps
T314 /workspace/coverage/default/34.rom_ctrl_alert_test.1206675822 Jun 05 03:50:21 PM PDT 24 Jun 05 03:50:26 PM PDT 24 89850473 ps
T315 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.186103656 Jun 05 03:49:58 PM PDT 24 Jun 05 03:50:08 PM PDT 24 2366293124 ps
T316 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3310879706 Jun 05 03:50:30 PM PDT 24 Jun 05 03:52:52 PM PDT 24 33159655910 ps
T317 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2552130546 Jun 05 03:50:12 PM PDT 24 Jun 05 03:50:38 PM PDT 24 2769439768 ps
T318 /workspace/coverage/default/33.rom_ctrl_stress_all.3228376170 Jun 05 03:50:29 PM PDT 24 Jun 05 03:51:27 PM PDT 24 22560076475 ps
T319 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2535022844 Jun 05 03:50:29 PM PDT 24 Jun 05 03:50:46 PM PDT 24 7323847341 ps
T320 /workspace/coverage/default/46.rom_ctrl_stress_all.2840487970 Jun 05 03:50:38 PM PDT 24 Jun 05 03:51:57 PM PDT 24 9541495629 ps
T321 /workspace/coverage/default/22.rom_ctrl_smoke.2552632278 Jun 05 03:50:27 PM PDT 24 Jun 05 03:50:38 PM PDT 24 754771210 ps
T322 /workspace/coverage/default/36.rom_ctrl_stress_all.154493758 Jun 05 03:50:28 PM PDT 24 Jun 05 03:50:50 PM PDT 24 1559884156 ps
T323 /workspace/coverage/default/8.rom_ctrl_alert_test.3902453245 Jun 05 03:49:51 PM PDT 24 Jun 05 03:50:07 PM PDT 24 5789524391 ps
T324 /workspace/coverage/default/7.rom_ctrl_stress_all.3554861274 Jun 05 03:49:55 PM PDT 24 Jun 05 03:50:54 PM PDT 24 5644414304 ps
T325 /workspace/coverage/default/30.rom_ctrl_smoke.3099569619 Jun 05 03:50:19 PM PDT 24 Jun 05 03:50:32 PM PDT 24 1192440798 ps
T326 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.64732582 Jun 05 03:50:39 PM PDT 24 Jun 05 03:52:07 PM PDT 24 2853552151 ps
T327 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2331959909 Jun 05 03:50:22 PM PDT 24 Jun 05 04:56:42 PM PDT 24 82248946553 ps
T328 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.177356312 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:10 PM PDT 24 1261788406 ps
T329 /workspace/coverage/default/11.rom_ctrl_alert_test.3492232523 Jun 05 03:49:57 PM PDT 24 Jun 05 03:50:11 PM PDT 24 2447766282 ps
T330 /workspace/coverage/default/0.rom_ctrl_alert_test.724221848 Jun 05 03:49:51 PM PDT 24 Jun 05 03:49:58 PM PDT 24 133632782 ps
T331 /workspace/coverage/default/11.rom_ctrl_smoke.1479396400 Jun 05 03:50:02 PM PDT 24 Jun 05 03:50:33 PM PDT 24 3482959952 ps
T332 /workspace/coverage/default/43.rom_ctrl_alert_test.1547682471 Jun 05 03:50:36 PM PDT 24 Jun 05 03:50:43 PM PDT 24 251285822 ps
T333 /workspace/coverage/default/23.rom_ctrl_smoke.4195710850 Jun 05 03:50:25 PM PDT 24 Jun 05 03:50:54 PM PDT 24 21718003230 ps
T334 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.936939534 Jun 05 03:50:46 PM PDT 24 Jun 05 03:51:10 PM PDT 24 8472147872 ps
T335 /workspace/coverage/default/25.rom_ctrl_alert_test.1326437045 Jun 05 03:50:08 PM PDT 24 Jun 05 03:50:23 PM PDT 24 6665335605 ps
T336 /workspace/coverage/default/46.rom_ctrl_alert_test.1045286359 Jun 05 03:50:40 PM PDT 24 Jun 05 03:50:50 PM PDT 24 3909904827 ps
T337 /workspace/coverage/default/28.rom_ctrl_smoke.2562205708 Jun 05 03:50:29 PM PDT 24 Jun 05 03:51:06 PM PDT 24 3707051603 ps
T338 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3212295351 Jun 05 03:49:52 PM PDT 24 Jun 05 03:53:31 PM PDT 24 11005612144 ps
T339 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1853411624 Jun 05 03:50:39 PM PDT 24 Jun 05 03:54:05 PM PDT 24 15966547131 ps
T340 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3111631692 Jun 05 03:50:15 PM PDT 24 Jun 05 03:50:22 PM PDT 24 200731695 ps
T341 /workspace/coverage/default/47.rom_ctrl_alert_test.3427299552 Jun 05 03:50:40 PM PDT 24 Jun 05 03:50:52 PM PDT 24 4824352810 ps
T342 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2410865809 Jun 05 03:50:05 PM PDT 24 Jun 05 03:56:27 PM PDT 24 221773033259 ps
T343 /workspace/coverage/default/15.rom_ctrl_stress_all.3997958845 Jun 05 03:50:01 PM PDT 24 Jun 05 03:50:58 PM PDT 24 15599892096 ps
T344 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2548493429 Jun 05 03:50:01 PM PDT 24 Jun 05 03:50:16 PM PDT 24 4807659231 ps
T345 /workspace/coverage/default/9.rom_ctrl_stress_all.2232433887 Jun 05 03:50:02 PM PDT 24 Jun 05 03:50:46 PM PDT 24 28800364409 ps
T346 /workspace/coverage/default/17.rom_ctrl_stress_all.152278977 Jun 05 03:49:59 PM PDT 24 Jun 05 03:50:35 PM PDT 24 24929781861 ps
T347 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3629322830 Jun 05 03:50:09 PM PDT 24 Jun 05 03:50:37 PM PDT 24 10329627183 ps
T348 /workspace/coverage/default/18.rom_ctrl_stress_all.1083908409 Jun 05 03:50:11 PM PDT 24 Jun 05 03:50:18 PM PDT 24 90702178 ps
T349 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3380695221 Jun 05 03:50:03 PM PDT 24 Jun 05 03:50:34 PM PDT 24 6978197153 ps
T350 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1050371432 Jun 05 03:50:39 PM PDT 24 Jun 05 03:50:52 PM PDT 24 1246209176 ps
T351 /workspace/coverage/default/9.rom_ctrl_smoke.3365616888 Jun 05 03:50:00 PM PDT 24 Jun 05 03:50:34 PM PDT 24 8247343282 ps
T352 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2296941706 Jun 05 03:50:42 PM PDT 24 Jun 05 03:50:54 PM PDT 24 2060086500 ps
T353 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1342050662 Jun 05 03:50:07 PM PDT 24 Jun 05 03:50:20 PM PDT 24 4314824521 ps
T104 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.730494688 Jun 05 03:50:27 PM PDT 24 Jun 05 04:26:23 PM PDT 24 105677798614 ps
T354 /workspace/coverage/default/18.rom_ctrl_alert_test.3986340291 Jun 05 03:50:10 PM PDT 24 Jun 05 03:50:16 PM PDT 24 460969120 ps
T355 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2507276145 Jun 05 03:49:56 PM PDT 24 Jun 05 03:50:24 PM PDT 24 11248518477 ps
T356 /workspace/coverage/default/10.rom_ctrl_stress_all.36914257 Jun 05 03:50:02 PM PDT 24 Jun 05 03:51:21 PM PDT 24 9849936217 ps
T357 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4250358727 Jun 05 03:50:21 PM PDT 24 Jun 05 03:51:53 PM PDT 24 3166558744 ps
T358 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4229584845 Jun 05 03:49:59 PM PDT 24 Jun 05 03:51:50 PM PDT 24 3846767441 ps
T359 /workspace/coverage/default/36.rom_ctrl_alert_test.1994393206 Jun 05 03:50:36 PM PDT 24 Jun 05 03:50:46 PM PDT 24 2724000493 ps
T360 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1681342311 Jun 05 03:49:58 PM PDT 24 Jun 05 03:53:00 PM PDT 24 26944740713 ps
T361 /workspace/coverage/default/27.rom_ctrl_smoke.2622538736 Jun 05 03:50:26 PM PDT 24 Jun 05 03:50:37 PM PDT 24 191538634 ps
T362 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2639655523 Jun 05 03:49:58 PM PDT 24 Jun 05 03:50:51 PM PDT 24 882677437 ps
T363 /workspace/coverage/default/0.rom_ctrl_stress_all.2418166306 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:15 PM PDT 24 6381363095 ps
T364 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.498413573 Jun 05 03:49:59 PM PDT 24 Jun 05 04:31:22 PM PDT 24 62204190370 ps
T365 /workspace/coverage/default/26.rom_ctrl_stress_all.3302187744 Jun 05 03:50:31 PM PDT 24 Jun 05 03:50:44 PM PDT 24 3214932128 ps
T366 /workspace/coverage/default/32.rom_ctrl_smoke.3580310176 Jun 05 03:50:23 PM PDT 24 Jun 05 03:50:43 PM PDT 24 2875487542 ps
T367 /workspace/coverage/default/43.rom_ctrl_smoke.143560686 Jun 05 03:50:41 PM PDT 24 Jun 05 03:50:52 PM PDT 24 667936637 ps
T368 /workspace/coverage/default/21.rom_ctrl_stress_all.230700137 Jun 05 03:50:06 PM PDT 24 Jun 05 03:50:40 PM PDT 24 3396417649 ps
T369 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3289038177 Jun 05 03:50:33 PM PDT 24 Jun 05 03:52:25 PM PDT 24 1594495503 ps
T62 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3451702156 Jun 05 03:49:48 PM PDT 24 Jun 05 03:49:56 PM PDT 24 467047907 ps
T58 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.154950163 Jun 05 03:49:39 PM PDT 24 Jun 05 03:50:50 PM PDT 24 253400209 ps
T370 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3538831140 Jun 05 03:49:52 PM PDT 24 Jun 05 03:50:14 PM PDT 24 1808413971 ps
T59 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2813004324 Jun 05 03:49:48 PM PDT 24 Jun 05 03:51:09 PM PDT 24 2405796886 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.758022245 Jun 05 03:49:48 PM PDT 24 Jun 05 03:49:55 PM PDT 24 377166683 ps
T65 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1885668284 Jun 05 03:49:51 PM PDT 24 Jun 05 03:50:05 PM PDT 24 5275659334 ps
T66 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3655643046 Jun 05 03:49:48 PM PDT 24 Jun 05 03:50:17 PM PDT 24 2147070374 ps
T67 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1799476430 Jun 05 03:49:52 PM PDT 24 Jun 05 03:50:05 PM PDT 24 1133407894 ps
T99 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1536029182 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:55 PM PDT 24 6629531750 ps
T100 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1588475326 Jun 05 03:49:36 PM PDT 24 Jun 05 03:49:48 PM PDT 24 995817369 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2985725372 Jun 05 03:49:47 PM PDT 24 Jun 05 03:49:56 PM PDT 24 838614361 ps
T101 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2345293178 Jun 05 03:49:56 PM PDT 24 Jun 05 03:50:15 PM PDT 24 2108810898 ps
T68 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.344978303 Jun 05 03:49:42 PM PDT 24 Jun 05 03:49:59 PM PDT 24 4020223423 ps
T69 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3369311082 Jun 05 03:49:47 PM PDT 24 Jun 05 03:50:00 PM PDT 24 1145550209 ps
T70 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3093160225 Jun 05 03:49:49 PM PDT 24 Jun 05 03:49:56 PM PDT 24 1227198316 ps
T102 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1703553964 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:48 PM PDT 24 1298703087 ps
T373 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2731713019 Jun 05 03:49:53 PM PDT 24 Jun 05 03:50:01 PM PDT 24 168344579 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3937235856 Jun 05 03:49:47 PM PDT 24 Jun 05 03:49:54 PM PDT 24 161359011 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2986538352 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:49 PM PDT 24 3246416399 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1463832885 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:47 PM PDT 24 384483534 ps
T71 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3236439230 Jun 05 03:49:38 PM PDT 24 Jun 05 03:49:43 PM PDT 24 830902216 ps
T72 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2868279430 Jun 05 03:49:42 PM PDT 24 Jun 05 03:51:16 PM PDT 24 11040576930 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1728642186 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:43 PM PDT 24 4962272337 ps
T96 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1233520992 Jun 05 03:49:37 PM PDT 24 Jun 05 03:49:53 PM PDT 24 7234126591 ps
T378 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3235588655 Jun 05 03:50:06 PM PDT 24 Jun 05 03:50:23 PM PDT 24 1440686574 ps
T379 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.305296466 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:52 PM PDT 24 3471877815 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1554442379 Jun 05 03:49:27 PM PDT 24 Jun 05 03:50:13 PM PDT 24 4460857002 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4134514856 Jun 05 03:49:42 PM PDT 24 Jun 05 03:50:02 PM PDT 24 14183872104 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.488244027 Jun 05 03:49:32 PM PDT 24 Jun 05 03:49:47 PM PDT 24 2650414958 ps
T60 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2291937510 Jun 05 03:49:40 PM PDT 24 Jun 05 03:50:50 PM PDT 24 4898231941 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3363369148 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:03 PM PDT 24 2480812319 ps
T73 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.298010257 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:49 PM PDT 24 177906825 ps
T74 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4106010043 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:02 PM PDT 24 4350699812 ps
T384 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3171406389 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:54 PM PDT 24 1657173821 ps
T79 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1922625888 Jun 05 03:49:48 PM PDT 24 Jun 05 03:50:08 PM PDT 24 361597000 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4101109272 Jun 05 03:49:51 PM PDT 24 Jun 05 03:50:08 PM PDT 24 2731979093 ps
T386 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2103805908 Jun 05 03:49:44 PM PDT 24 Jun 05 03:49:53 PM PDT 24 1068417296 ps
T387 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1571521137 Jun 05 03:49:55 PM PDT 24 Jun 05 03:50:04 PM PDT 24 3447572899 ps
T388 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.387886025 Jun 05 03:49:52 PM PDT 24 Jun 05 03:50:06 PM PDT 24 659513303 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.598586377 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:50 PM PDT 24 1028800605 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1537086327 Jun 05 03:49:29 PM PDT 24 Jun 05 03:49:41 PM PDT 24 5081280447 ps
T106 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2383677338 Jun 05 03:49:31 PM PDT 24 Jun 05 03:50:51 PM PDT 24 2253372984 ps
T391 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3564379377 Jun 05 03:49:49 PM PDT 24 Jun 05 03:49:59 PM PDT 24 131017378 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2564849365 Jun 05 03:49:32 PM PDT 24 Jun 05 03:49:44 PM PDT 24 1348212065 ps
T393 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.448883956 Jun 05 03:49:52 PM PDT 24 Jun 05 03:50:03 PM PDT 24 433986502 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.5324743 Jun 05 03:49:32 PM PDT 24 Jun 05 03:49:43 PM PDT 24 844137433 ps
T113 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1654960820 Jun 05 03:49:56 PM PDT 24 Jun 05 03:50:38 PM PDT 24 1166552547 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1345991660 Jun 05 03:49:30 PM PDT 24 Jun 05 03:49:39 PM PDT 24 519939162 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1498254983 Jun 05 03:49:33 PM PDT 24 Jun 05 03:49:51 PM PDT 24 1551073731 ps
T109 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1934126687 Jun 05 03:49:52 PM PDT 24 Jun 05 03:51:11 PM PDT 24 1369263904 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3722233856 Jun 05 03:49:44 PM PDT 24 Jun 05 03:49:57 PM PDT 24 1310702230 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.587813565 Jun 05 03:49:42 PM PDT 24 Jun 05 03:49:58 PM PDT 24 1936040259 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.565367453 Jun 05 03:49:32 PM PDT 24 Jun 05 03:50:24 PM PDT 24 4001618483 ps
T81 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3252752650 Jun 05 03:49:49 PM PDT 24 Jun 05 03:51:34 PM PDT 24 56047677847 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.957021223 Jun 05 03:49:30 PM PDT 24 Jun 05 03:49:38 PM PDT 24 915444378 ps
T82 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1913018090 Jun 05 03:49:52 PM PDT 24 Jun 05 03:50:23 PM PDT 24 2153816365 ps
T399 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3630826382 Jun 05 03:49:48 PM PDT 24 Jun 05 03:50:07 PM PDT 24 16598949439 ps
T400 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1146130336 Jun 05 03:49:58 PM PDT 24 Jun 05 03:50:07 PM PDT 24 763956019 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2502613129 Jun 05 03:49:45 PM PDT 24 Jun 05 03:49:55 PM PDT 24 807421915 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1245967454 Jun 05 03:50:06 PM PDT 24 Jun 05 03:50:18 PM PDT 24 8895397222 ps
T402 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.667120750 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:57 PM PDT 24 6204308810 ps
T403 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.38772057 Jun 05 03:49:53 PM PDT 24 Jun 05 03:51:16 PM PDT 24 27166964308 ps
T404 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1929624075 Jun 05 03:49:49 PM PDT 24 Jun 05 03:50:31 PM PDT 24 2354956292 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3153775865 Jun 05 03:49:37 PM PDT 24 Jun 05 03:49:42 PM PDT 24 87150618 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1485650130 Jun 05 03:49:48 PM PDT 24 Jun 05 03:49:53 PM PDT 24 87331036 ps
T407 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3724147255 Jun 05 03:49:36 PM PDT 24 Jun 05 03:49:54 PM PDT 24 6798691735 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3821076026 Jun 05 03:49:43 PM PDT 24 Jun 05 03:49:54 PM PDT 24 782943861 ps
T409 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.860066613 Jun 05 03:49:38 PM PDT 24 Jun 05 03:49:45 PM PDT 24 1529166172 ps
T83 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.478597360 Jun 05 03:49:45 PM PDT 24 Jun 05 03:50:00 PM PDT 24 3205646182 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1453116413 Jun 05 03:49:32 PM PDT 24 Jun 05 03:49:45 PM PDT 24 381173116 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.418475768 Jun 05 03:49:30 PM PDT 24 Jun 05 03:49:37 PM PDT 24 307987723 ps
T84 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.88170069 Jun 05 03:49:33 PM PDT 24 Jun 05 03:50:17 PM PDT 24 8123317483 ps
T412 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4189903899 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:46 PM PDT 24 369361252 ps
T413 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3431850307 Jun 05 03:49:52 PM PDT 24 Jun 05 03:49:59 PM PDT 24 587665892 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1613994419 Jun 05 03:49:42 PM PDT 24 Jun 05 03:49:51 PM PDT 24 424727167 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1141456407 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:54 PM PDT 24 1336873918 ps
T416 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2823368122 Jun 05 03:49:41 PM PDT 24 Jun 05 03:49:49 PM PDT 24 378608205 ps
T417 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.441787644 Jun 05 03:49:49 PM PDT 24 Jun 05 03:50:01 PM PDT 24 3932932210 ps
T418 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.696774633 Jun 05 03:49:45 PM PDT 24 Jun 05 03:49:55 PM PDT 24 1733891765 ps
T419 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1918068279 Jun 05 03:49:44 PM PDT 24 Jun 05 03:49:57 PM PDT 24 2215517645 ps
T420 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.961625436 Jun 05 03:49:52 PM PDT 24 Jun 05 03:51:03 PM PDT 24 16713442604 ps
T421 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3809983348 Jun 05 03:49:48 PM PDT 24 Jun 05 03:50:00 PM PDT 24 1086200349 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1239811250 Jun 05 03:49:42 PM PDT 24 Jun 05 03:50:55 PM PDT 24 4482745071 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1814332032 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:46 PM PDT 24 3444891460 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2089581800 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:44 PM PDT 24 1037245410 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.795959849 Jun 05 03:49:47 PM PDT 24 Jun 05 03:50:04 PM PDT 24 11448310973 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4232555766 Jun 05 03:49:46 PM PDT 24 Jun 05 03:49:55 PM PDT 24 3590854581 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.401576938 Jun 05 03:49:45 PM PDT 24 Jun 05 03:50:04 PM PDT 24 380452539 ps
T92 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1787635182 Jun 05 03:49:43 PM PDT 24 Jun 05 03:50:46 PM PDT 24 18261973527 ps
T91 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3881797946 Jun 05 03:49:51 PM PDT 24 Jun 05 03:51:13 PM PDT 24 8358595712 ps
T427 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2028893946 Jun 05 03:49:57 PM PDT 24 Jun 05 03:50:14 PM PDT 24 4321696922 ps
T428 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1686635549 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:05 PM PDT 24 3187034622 ps
T85 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.550126011 Jun 05 03:49:48 PM PDT 24 Jun 05 03:50:17 PM PDT 24 547101296 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2746369341 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:34 PM PDT 24 1239770336 ps
T429 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2482578207 Jun 05 03:49:49 PM PDT 24 Jun 05 03:50:04 PM PDT 24 1283602773 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4111057213 Jun 05 03:49:38 PM PDT 24 Jun 05 03:49:50 PM PDT 24 15608457379 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2177439011 Jun 05 03:49:28 PM PDT 24 Jun 05 03:49:38 PM PDT 24 7059628213 ps
T110 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.75334213 Jun 05 03:50:02 PM PDT 24 Jun 05 03:51:17 PM PDT 24 1355467398 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2455117491 Jun 05 03:49:41 PM PDT 24 Jun 05 03:51:01 PM PDT 24 2282291554 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1339830489 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:55 PM PDT 24 7515214403 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1263505673 Jun 05 03:49:34 PM PDT 24 Jun 05 03:50:54 PM PDT 24 20374425440 ps
T434 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1867901694 Jun 05 03:49:47 PM PDT 24 Jun 05 03:50:33 PM PDT 24 9414246735 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1957563325 Jun 05 03:49:30 PM PDT 24 Jun 05 03:49:44 PM PDT 24 8196416276 ps
T435 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3386077937 Jun 05 03:49:47 PM PDT 24 Jun 05 03:49:55 PM PDT 24 352597409 ps
T436 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1842851343 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:01 PM PDT 24 976081863 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3599047732 Jun 05 03:49:51 PM PDT 24 Jun 05 03:50:01 PM PDT 24 218448392 ps
T438 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2290804541 Jun 05 03:49:56 PM PDT 24 Jun 05 03:50:10 PM PDT 24 5544229227 ps
T112 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3607199897 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:34 PM PDT 24 2609293706 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1234841726 Jun 05 03:49:50 PM PDT 24 Jun 05 03:49:56 PM PDT 24 87985012 ps
T87 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.177578237 Jun 05 03:49:56 PM PDT 24 Jun 05 03:50:14 PM PDT 24 2119887810 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3782787738 Jun 05 03:49:43 PM PDT 24 Jun 05 03:49:49 PM PDT 24 332612582 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.192513439 Jun 05 03:49:43 PM PDT 24 Jun 05 03:51:00 PM PDT 24 15852870776 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2553211989 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:50 PM PDT 24 1724291150 ps
T443 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1869282708 Jun 05 03:49:48 PM PDT 24 Jun 05 03:50:05 PM PDT 24 2092603990 ps
T111 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1017351567 Jun 05 03:49:32 PM PDT 24 Jun 05 03:50:15 PM PDT 24 1110877763 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1904479653 Jun 05 03:49:52 PM PDT 24 Jun 05 03:50:01 PM PDT 24 280055645 ps
T88 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2830091260 Jun 05 03:49:53 PM PDT 24 Jun 05 03:51:14 PM PDT 24 9234677310 ps
T445 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2563842156 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:39 PM PDT 24 8556264938 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.593235236 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:49 PM PDT 24 2076773543 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1189868029 Jun 05 03:49:30 PM PDT 24 Jun 05 03:50:02 PM PDT 24 9642072379 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3552906866 Jun 05 03:49:38 PM PDT 24 Jun 05 03:49:55 PM PDT 24 8666204418 ps
T448 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3219350104 Jun 05 03:49:49 PM PDT 24 Jun 05 03:50:03 PM PDT 24 2863503089 ps
T449 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.251094302 Jun 05 03:49:48 PM PDT 24 Jun 05 03:50:03 PM PDT 24 1286780992 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1744446538 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:46 PM PDT 24 93860477 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2308247212 Jun 05 03:49:32 PM PDT 24 Jun 05 03:50:09 PM PDT 24 841884632 ps
T93 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.617138260 Jun 05 03:49:49 PM PDT 24 Jun 05 03:50:09 PM PDT 24 381603760 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2357163557 Jun 05 03:49:37 PM PDT 24 Jun 05 03:49:50 PM PDT 24 5474549715 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.52290407 Jun 05 03:49:49 PM PDT 24 Jun 05 03:49:57 PM PDT 24 97558255 ps
T94 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4041121884 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:26 PM PDT 24 5703291052 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2222492703 Jun 05 03:49:44 PM PDT 24 Jun 05 03:50:55 PM PDT 24 428025415 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.607306571 Jun 05 03:49:43 PM PDT 24 Jun 05 03:49:49 PM PDT 24 1184009526 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4151115988 Jun 05 03:49:42 PM PDT 24 Jun 05 03:49:53 PM PDT 24 884834367 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.429624666 Jun 05 03:49:48 PM PDT 24 Jun 05 03:50:31 PM PDT 24 1272475584 ps
T457 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1138092771 Jun 05 03:49:42 PM PDT 24 Jun 05 03:49:47 PM PDT 24 88233908 ps
T458 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3220150877 Jun 05 03:49:30 PM PDT 24 Jun 05 03:49:35 PM PDT 24 333502516 ps
T459 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3246712290 Jun 05 03:49:58 PM PDT 24 Jun 05 03:50:03 PM PDT 24 332562476 ps
T460 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2032648666 Jun 05 03:49:48 PM PDT 24 Jun 05 03:50:17 PM PDT 24 9036984582 ps
T114 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3292323863 Jun 05 03:49:50 PM PDT 24 Jun 05 03:50:39 PM PDT 24 1977096975 ps
T461 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4051936732 Jun 05 03:49:45 PM PDT 24 Jun 05 03:49:50 PM PDT 24 88328838 ps
T462 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.947557210 Jun 05 03:49:47 PM PDT 24 Jun 05 03:49:53 PM PDT 24 321413791 ps
T463 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1991992779 Jun 05 03:49:37 PM PDT 24 Jun 05 03:49:55 PM PDT 24 1565274631 ps
T464 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1797348022 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:52 PM PDT 24 2340392731 ps
T465 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.308065401 Jun 05 03:49:39 PM PDT 24 Jun 05 03:49:54 PM PDT 24 8691714358 ps
T466 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2782865747 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:47 PM PDT 24 1713628580 ps
T467 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1735082209 Jun 05 03:49:31 PM PDT 24 Jun 05 03:49:36 PM PDT 24 333375424 ps

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1106474785
Short name T7
Test name
Test status
Simulation time 22032850160 ps
CPU time 45.46 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:50:36 PM PDT 24
Peak memory 219164 kb
Host smart-27a9d46b-5beb-416e-bf87-6d20b38602d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106474785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1106474785
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1405099209
Short name T14
Test name
Test status
Simulation time 21766662976 ps
CPU time 260.44 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:54:15 PM PDT 24
Peak memory 227916 kb
Host smart-cf379ca3-c168-4e06-906d-9ad3e69906f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405099209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1405099209
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2687218332
Short name T16
Test name
Test status
Simulation time 387617287447 ps
CPU time 3325.72 seconds
Started Jun 05 03:50:11 PM PDT 24
Finished Jun 05 04:45:38 PM PDT 24
Peak memory 245084 kb
Host smart-2b12256a-e758-4b77-a91f-6cc1a6068370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687218332 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2687218332
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3145343194
Short name T24
Test name
Test status
Simulation time 12763967049 ps
CPU time 75.28 seconds
Started Jun 05 03:50:05 PM PDT 24
Finished Jun 05 03:51:21 PM PDT 24
Peak memory 219156 kb
Host smart-1c3d7b5f-c746-4ca8-8496-00ba536abaf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145343194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3145343194
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2383677338
Short name T106
Test name
Test status
Simulation time 2253372984 ps
CPU time 78.85 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:50:51 PM PDT 24
Peak memory 219388 kb
Host smart-d44a4161-f7d0-46d4-864c-8ad11aac6854
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383677338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2383677338
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.470256217
Short name T3
Test name
Test status
Simulation time 89063375 ps
CPU time 4.27 seconds
Started Jun 05 03:50:26 PM PDT 24
Finished Jun 05 03:50:31 PM PDT 24
Peak memory 210768 kb
Host smart-6ab73e0c-373e-4ad1-8edf-91fb155958f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470256217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.470256217
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2097001434
Short name T32
Test name
Test status
Simulation time 2426519185 ps
CPU time 107.63 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:51:42 PM PDT 24
Peak memory 237824 kb
Host smart-3b9f9367-bc40-4b04-9ba7-5170d00226fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097001434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2097001434
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1799476430
Short name T67
Test name
Test status
Simulation time 1133407894 ps
CPU time 10.63 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:05 PM PDT 24
Peak memory 211156 kb
Host smart-47a551a3-d704-42e3-9f70-39d84b4487a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799476430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1799476430
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1938420035
Short name T40
Test name
Test status
Simulation time 2164218435 ps
CPU time 23.38 seconds
Started Jun 05 03:50:30 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 211596 kb
Host smart-52bed728-b11f-4947-aebc-fada4691831d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938420035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1938420035
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2746369341
Short name T108
Test name
Test status
Simulation time 1239770336 ps
CPU time 41.73 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:34 PM PDT 24
Peak memory 211124 kb
Host smart-373a238d-670c-4077-aa4f-c36edd43c236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746369341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2746369341
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.178225990
Short name T133
Test name
Test status
Simulation time 7052232999 ps
CPU time 37.61 seconds
Started Jun 05 03:50:02 PM PDT 24
Finished Jun 05 03:50:41 PM PDT 24
Peak memory 216028 kb
Host smart-5f043e01-1aab-4111-a97a-ab5582254a58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178225990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.178225990
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.540417191
Short name T15
Test name
Test status
Simulation time 14388217235 ps
CPU time 26.61 seconds
Started Jun 05 03:50:09 PM PDT 24
Finished Jun 05 03:50:36 PM PDT 24
Peak memory 211972 kb
Host smart-a62f4dd8-05b9-4ee1-8ef7-431a17c3608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540417191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.540417191
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1934126687
Short name T109
Test name
Test status
Simulation time 1369263904 ps
CPU time 73.49 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:51:11 PM PDT 24
Peak memory 219664 kb
Host smart-f56e0736-ca45-404f-8ffa-6a8dd607e4a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934126687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1934126687
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3655643046
Short name T66
Test name
Test status
Simulation time 2147070374 ps
CPU time 27.89 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:50:17 PM PDT 24
Peak memory 211176 kb
Host smart-54530f56-fb82-470a-bc94-e6ed0d3aeb6b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655643046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3655643046
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.582965328
Short name T43
Test name
Test status
Simulation time 60548989269 ps
CPU time 283.14 seconds
Started Jun 05 03:50:20 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 234580 kb
Host smart-86a353b5-3237-454c-8e9d-fee5af44048d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582965328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.582965328
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1263505673
Short name T105
Test name
Test status
Simulation time 20374425440 ps
CPU time 79.49 seconds
Started Jun 05 03:49:34 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 219372 kb
Host smart-02466261-4746-4801-b844-a85203678fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263505673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1263505673
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2868279430
Short name T72
Test name
Test status
Simulation time 11040576930 ps
CPU time 92.38 seconds
Started Jun 05 03:49:42 PM PDT 24
Finished Jun 05 03:51:16 PM PDT 24
Peak memory 211208 kb
Host smart-9a608be8-7aa9-4b02-bffd-0491875cd13e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868279430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2868279430
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.305207228
Short name T37
Test name
Test status
Simulation time 937772707 ps
CPU time 11.24 seconds
Started Jun 05 03:49:56 PM PDT 24
Finished Jun 05 03:50:09 PM PDT 24
Peak memory 210840 kb
Host smart-06adc8c3-72e9-499c-8bee-bc5b229cd40a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305207228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.305207228
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3487003969
Short name T19
Test name
Test status
Simulation time 17252146362 ps
CPU time 636.51 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 04:00:50 PM PDT 24
Peak memory 234100 kb
Host smart-5d791b7c-78bf-4584-b6f1-68b21b7d3e4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487003969 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3487003969
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2477043913
Short name T31
Test name
Test status
Simulation time 2284013881 ps
CPU time 102.48 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:51:40 PM PDT 24
Peak memory 233680 kb
Host smart-2649ae35-73c7-4ad0-89b3-ae27567a4991
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477043913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2477043913
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3782787738
Short name T440
Test name
Test status
Simulation time 332612582 ps
CPU time 4.25 seconds
Started Jun 05 03:49:43 PM PDT 24
Finished Jun 05 03:49:49 PM PDT 24
Peak memory 211128 kb
Host smart-fa9be75d-dd51-4af1-b90a-2a1bedb51ee3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782787738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3782787738
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1588475326
Short name T100
Test name
Test status
Simulation time 995817369 ps
CPU time 10.56 seconds
Started Jun 05 03:49:36 PM PDT 24
Finished Jun 05 03:49:48 PM PDT 24
Peak memory 211156 kb
Host smart-df57b001-fa7e-4901-bd9e-be0699c50dd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588475326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1588475326
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.298010257
Short name T73
Test name
Test status
Simulation time 177906825 ps
CPU time 7.28 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:49 PM PDT 24
Peak memory 211064 kb
Host smart-b2432b28-3965-483d-aeef-717eaf3639e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298010257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.298010257
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2782865747
Short name T466
Test name
Test status
Simulation time 1713628580 ps
CPU time 14.35 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:47 PM PDT 24
Peak memory 213088 kb
Host smart-db83b900-1430-4005-b4bc-4822773efa98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782865747 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2782865747
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.418475768
Short name T411
Test name
Test status
Simulation time 307987723 ps
CPU time 6.38 seconds
Started Jun 05 03:49:30 PM PDT 24
Finished Jun 05 03:49:37 PM PDT 24
Peak memory 211108 kb
Host smart-86a305f2-d4d1-4dd4-a70d-a337f7bf7f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418475768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.418475768
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2564849365
Short name T392
Test name
Test status
Simulation time 1348212065 ps
CPU time 11.36 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:49:44 PM PDT 24
Peak memory 211024 kb
Host smart-b54c9a17-4ab7-48dc-8c4e-9985e204a55b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564849365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2564849365
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1537086327
Short name T390
Test name
Test status
Simulation time 5081280447 ps
CPU time 11.61 seconds
Started Jun 05 03:49:29 PM PDT 24
Finished Jun 05 03:49:41 PM PDT 24
Peak memory 211112 kb
Host smart-41ab6a31-2e39-404b-976a-de018405c0ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537086327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1537086327
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1189868029
Short name T89
Test name
Test status
Simulation time 9642072379 ps
CPU time 31.85 seconds
Started Jun 05 03:49:30 PM PDT 24
Finished Jun 05 03:50:02 PM PDT 24
Peak memory 211212 kb
Host smart-cb443385-fd26-4b2f-9c56-5578d795aef9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189868029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1189868029
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1735082209
Short name T467
Test name
Test status
Simulation time 333375424 ps
CPU time 4.25 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:36 PM PDT 24
Peak memory 211140 kb
Host smart-56818e9c-5338-4e4d-b383-86a3b386b5fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735082209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1735082209
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2986538352
Short name T375
Test name
Test status
Simulation time 3246416399 ps
CPU time 17.65 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:49 PM PDT 24
Peak memory 219468 kb
Host smart-42a0af06-8503-4963-8a0e-f4f17c152188
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986538352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2986538352
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1957563325
Short name T86
Test name
Test status
Simulation time 8196416276 ps
CPU time 13.8 seconds
Started Jun 05 03:49:30 PM PDT 24
Finished Jun 05 03:49:44 PM PDT 24
Peak memory 211208 kb
Host smart-bcb823ef-abe8-4756-8fc3-1f24eb569eef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957563325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1957563325
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2089581800
Short name T423
Test name
Test status
Simulation time 1037245410 ps
CPU time 11.13 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:44 PM PDT 24
Peak memory 210860 kb
Host smart-6f10771e-f50e-4435-87e8-11adfa9dc337
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089581800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2089581800
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2553211989
Short name T442
Test name
Test status
Simulation time 1724291150 ps
CPU time 17.71 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:50 PM PDT 24
Peak memory 211160 kb
Host smart-c0e93684-ec91-454e-afe0-9ad81e45fdb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553211989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2553211989
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1345991660
Short name T395
Test name
Test status
Simulation time 519939162 ps
CPU time 8.13 seconds
Started Jun 05 03:49:30 PM PDT 24
Finished Jun 05 03:49:39 PM PDT 24
Peak memory 219340 kb
Host smart-90485366-ab98-4bb2-bfe3-e5b233e2bc78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345991660 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1345991660
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3236439230
Short name T71
Test name
Test status
Simulation time 830902216 ps
CPU time 4.32 seconds
Started Jun 05 03:49:38 PM PDT 24
Finished Jun 05 03:49:43 PM PDT 24
Peak memory 211116 kb
Host smart-9c4572ec-202c-40ed-8ea6-f4af4105a1d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236439230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3236439230
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4232555766
Short name T425
Test name
Test status
Simulation time 3590854581 ps
CPU time 7.95 seconds
Started Jun 05 03:49:46 PM PDT 24
Finished Jun 05 03:49:55 PM PDT 24
Peak memory 211056 kb
Host smart-3a9da410-d8d7-42ed-a4d6-c5cae437c115
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232555766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4232555766
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.758022245
Short name T371
Test name
Test status
Simulation time 377166683 ps
CPU time 6.53 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:49:55 PM PDT 24
Peak memory 211028 kb
Host smart-903b9c3f-3c2d-4134-b8fb-ba5123c98e24
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758022245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
758022245
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1554442379
Short name T380
Test name
Test status
Simulation time 4460857002 ps
CPU time 44.64 seconds
Started Jun 05 03:49:27 PM PDT 24
Finished Jun 05 03:50:13 PM PDT 24
Peak memory 211240 kb
Host smart-bfd13c4a-a43e-4c34-a7fd-473c4e38316c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554442379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1554442379
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3093160225
Short name T70
Test name
Test status
Simulation time 1227198316 ps
CPU time 6.06 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:49:56 PM PDT 24
Peak memory 211148 kb
Host smart-960f4077-c54a-406f-ab37-e6c6cfe58e1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093160225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3093160225
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1141456407
Short name T415
Test name
Test status
Simulation time 1336873918 ps
CPU time 14.03 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:54 PM PDT 24
Peak memory 219400 kb
Host smart-309f2c2b-065f-4754-9839-514d73757e77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141456407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1141456407
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1017351567
Short name T111
Test name
Test status
Simulation time 1110877763 ps
CPU time 41.84 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:50:15 PM PDT 24
Peak memory 211612 kb
Host smart-e442f119-adca-4a99-8899-3046d4ef3814
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017351567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1017351567
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.308065401
Short name T465
Test name
Test status
Simulation time 8691714358 ps
CPU time 14.32 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:54 PM PDT 24
Peak memory 219432 kb
Host smart-5bf5abce-411b-4425-8c32-c4f1f3819879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308065401 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.308065401
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2028893946
Short name T427
Test name
Test status
Simulation time 4321696922 ps
CPU time 16.2 seconds
Started Jun 05 03:49:57 PM PDT 24
Finished Jun 05 03:50:14 PM PDT 24
Peak memory 211216 kb
Host smart-de60acdc-390f-4709-8d84-a9d35391a9b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028893946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2028893946
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1485650130
Short name T406
Test name
Test status
Simulation time 87331036 ps
CPU time 4.32 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:49:53 PM PDT 24
Peak memory 211084 kb
Host smart-130ee59d-c444-4d4e-bb3e-c56879367b46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485650130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1485650130
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3630826382
Short name T399
Test name
Test status
Simulation time 16598949439 ps
CPU time 17.34 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:50:07 PM PDT 24
Peak memory 219464 kb
Host smart-4131dade-b870-46ce-a02f-16068add66fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630826382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3630826382
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2291937510
Short name T60
Test name
Test status
Simulation time 4898231941 ps
CPU time 69.08 seconds
Started Jun 05 03:49:40 PM PDT 24
Finished Jun 05 03:50:50 PM PDT 24
Peak memory 212500 kb
Host smart-ecb8e768-6b76-4b97-84b3-437b892d89c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291937510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2291937510
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1463832885
Short name T376
Test name
Test status
Simulation time 384483534 ps
CPU time 5.26 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:47 PM PDT 24
Peak memory 219376 kb
Host smart-6b89736d-bc33-44e4-a275-f11a4c83fa7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463832885 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1463832885
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4106010043
Short name T74
Test name
Test status
Simulation time 4350699812 ps
CPU time 9.75 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:02 PM PDT 24
Peak memory 211220 kb
Host smart-cab9d571-202f-414e-a236-0268d2586a9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106010043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4106010043
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.38772057
Short name T403
Test name
Test status
Simulation time 27166964308 ps
CPU time 77.02 seconds
Started Jun 05 03:49:53 PM PDT 24
Finished Jun 05 03:51:16 PM PDT 24
Peak memory 211244 kb
Host smart-8de6083f-2649-4f48-b4e5-13b9ab4eb6f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38772057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pas
sthru_mem_tl_intg_err.38772057
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.667120750
Short name T402
Test name
Test status
Simulation time 6204308810 ps
CPU time 15.07 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:57 PM PDT 24
Peak memory 211224 kb
Host smart-087ad55e-4d93-4fce-97d5-5b6f6a74d03e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667120750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.667120750
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3724147255
Short name T407
Test name
Test status
Simulation time 6798691735 ps
CPU time 17.19 seconds
Started Jun 05 03:49:36 PM PDT 24
Finished Jun 05 03:49:54 PM PDT 24
Peak memory 219464 kb
Host smart-c4778669-b63b-4d19-b75c-53b91e704f63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724147255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3724147255
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.305296466
Short name T379
Test name
Test status
Simulation time 3471877815 ps
CPU time 9.62 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:52 PM PDT 24
Peak memory 219432 kb
Host smart-e6dc82ae-01bb-4dfb-af8c-7cb9cb6edee6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305296466 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.305296466
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1686635549
Short name T428
Test name
Test status
Simulation time 3187034622 ps
CPU time 13.38 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:05 PM PDT 24
Peak memory 211196 kb
Host smart-82fb7da3-b10f-4429-994d-6d3899eb4c96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686635549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1686635549
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2032648666
Short name T460
Test name
Test status
Simulation time 9036984582 ps
CPU time 27.23 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:50:17 PM PDT 24
Peak memory 211240 kb
Host smart-09080daa-25e3-4aa6-81fe-deb10c07cf37
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032648666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2032648666
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.696774633
Short name T418
Test name
Test status
Simulation time 1733891765 ps
CPU time 8.96 seconds
Started Jun 05 03:49:45 PM PDT 24
Finished Jun 05 03:49:55 PM PDT 24
Peak memory 211156 kb
Host smart-9c6ded6a-132c-4e09-907f-dbb2c6faa4b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696774633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.696774633
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1245967454
Short name T401
Test name
Test status
Simulation time 8895397222 ps
CPU time 11.04 seconds
Started Jun 05 03:50:06 PM PDT 24
Finished Jun 05 03:50:18 PM PDT 24
Peak memory 219316 kb
Host smart-a99a12a8-d7eb-4853-a6c0-6fb38ae417bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245967454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1245967454
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.75334213
Short name T110
Test name
Test status
Simulation time 1355467398 ps
CPU time 73 seconds
Started Jun 05 03:50:02 PM PDT 24
Finished Jun 05 03:51:17 PM PDT 24
Peak memory 211676 kb
Host smart-28b68c60-db30-4040-8356-1e685de4e979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75334213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_int
g_err.75334213
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1918068279
Short name T419
Test name
Test status
Simulation time 2215517645 ps
CPU time 11.06 seconds
Started Jun 05 03:49:44 PM PDT 24
Finished Jun 05 03:49:57 PM PDT 24
Peak memory 211900 kb
Host smart-2f6d6bb7-8646-4673-aa37-ab2156b4af79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918068279 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1918068279
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.441787644
Short name T417
Test name
Test status
Simulation time 3932932210 ps
CPU time 9.88 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:50:01 PM PDT 24
Peak memory 211216 kb
Host smart-2f358a92-35a5-4de0-b952-b759c92ba010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441787644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.441787644
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.550126011
Short name T85
Test name
Test status
Simulation time 547101296 ps
CPU time 27.63 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:50:17 PM PDT 24
Peak memory 211180 kb
Host smart-e2e7de37-dc11-45c9-9a69-4751c3c89726
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550126011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.550126011
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1234841726
Short name T439
Test name
Test status
Simulation time 87985012 ps
CPU time 4.17 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:49:56 PM PDT 24
Peak memory 211156 kb
Host smart-8813f518-c280-41a4-bb29-c1f03e4d83b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234841726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1234841726
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3538831140
Short name T370
Test name
Test status
Simulation time 1808413971 ps
CPU time 18.64 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:14 PM PDT 24
Peak memory 219400 kb
Host smart-30ca39fe-fef8-48a6-b7f2-96ba71358771
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538831140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3538831140
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3937235856
Short name T374
Test name
Test status
Simulation time 161359011 ps
CPU time 5.05 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:49:54 PM PDT 24
Peak memory 219368 kb
Host smart-88b1ec73-4cc8-4bfe-9fb3-b58bfafbb0f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937235856 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3937235856
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1885668284
Short name T65
Test name
Test status
Simulation time 5275659334 ps
CPU time 12.23 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:50:05 PM PDT 24
Peak memory 211220 kb
Host smart-8c77d19b-7a1d-4ecb-a2c0-969a58059f5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885668284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1885668284
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3369311082
Short name T69
Test name
Test status
Simulation time 1145550209 ps
CPU time 10.87 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:50:00 PM PDT 24
Peak memory 211148 kb
Host smart-7da18b12-f17b-4a0f-9b5d-06939750f2ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369311082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3369311082
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3599047732
Short name T437
Test name
Test status
Simulation time 218448392 ps
CPU time 7.81 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:50:01 PM PDT 24
Peak memory 219384 kb
Host smart-dd77f9c8-8654-4d04-b3b2-de1fa0628baa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599047732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3599047732
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1867901694
Short name T434
Test name
Test status
Simulation time 9414246735 ps
CPU time 45.38 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:50:33 PM PDT 24
Peak memory 212384 kb
Host smart-69d03d48-f18f-4d57-8e64-8b074d34387a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867901694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1867901694
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3431850307
Short name T413
Test name
Test status
Simulation time 587665892 ps
CPU time 4.54 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:49:59 PM PDT 24
Peak memory 212608 kb
Host smart-8befef69-99e0-41a7-ad8a-bfd93d8c64f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431850307 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3431850307
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2103805908
Short name T386
Test name
Test status
Simulation time 1068417296 ps
CPU time 8.19 seconds
Started Jun 05 03:49:44 PM PDT 24
Finished Jun 05 03:49:53 PM PDT 24
Peak memory 211156 kb
Host smart-681a2852-c90b-47ff-be29-1d23d4507103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103805908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2103805908
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4041121884
Short name T94
Test name
Test status
Simulation time 5703291052 ps
CPU time 24.67 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:26 PM PDT 24
Peak memory 211236 kb
Host smart-110e7dec-fce0-4548-a4f9-0b492e42c63c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041121884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4041121884
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3246712290
Short name T459
Test name
Test status
Simulation time 332562476 ps
CPU time 4.23 seconds
Started Jun 05 03:49:58 PM PDT 24
Finished Jun 05 03:50:03 PM PDT 24
Peak memory 211160 kb
Host smart-c0a68ebf-2ce7-4a94-90a8-f6b6b25ffa64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246712290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3246712290
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3564379377
Short name T391
Test name
Test status
Simulation time 131017378 ps
CPU time 8.5 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:49:59 PM PDT 24
Peak memory 214388 kb
Host smart-e84ec7f0-6557-4915-8863-8534d600f60b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564379377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3564379377
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2813004324
Short name T59
Test name
Test status
Simulation time 2405796886 ps
CPU time 79.45 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:51:09 PM PDT 24
Peak memory 211900 kb
Host smart-c139a1a1-770b-4284-944c-24bf266c8943
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813004324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2813004324
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3386077937
Short name T435
Test name
Test status
Simulation time 352597409 ps
CPU time 7.28 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:49:55 PM PDT 24
Peak memory 219372 kb
Host smart-f33e3f74-f24a-43b1-a3e2-b46d27f3aa4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386077937 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3386077937
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4051936732
Short name T461
Test name
Test status
Simulation time 88328838 ps
CPU time 4.3 seconds
Started Jun 05 03:49:45 PM PDT 24
Finished Jun 05 03:49:50 PM PDT 24
Peak memory 211428 kb
Host smart-68fa440b-d349-422d-aad0-99f36ed19ebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051936732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4051936732
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1913018090
Short name T82
Test name
Test status
Simulation time 2153816365 ps
CPU time 28 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:23 PM PDT 24
Peak memory 211244 kb
Host smart-9a0b8a4e-cc9a-416d-a8ab-c4356c252251
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913018090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1913018090
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1869282708
Short name T443
Test name
Test status
Simulation time 2092603990 ps
CPU time 15.4 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:50:05 PM PDT 24
Peak memory 211156 kb
Host smart-009e5a2e-c701-4d0e-8b7e-e825d740c434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869282708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1869282708
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3363369148
Short name T383
Test name
Test status
Simulation time 2480812319 ps
CPU time 11.67 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:03 PM PDT 24
Peak memory 219468 kb
Host smart-a4d07984-f5b2-4edf-838e-7cb5c5be3821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363369148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3363369148
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.429624666
Short name T456
Test name
Test status
Simulation time 1272475584 ps
CPU time 42.04 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:50:31 PM PDT 24
Peak memory 211928 kb
Host smart-9ebcb8c9-7a5c-4f0d-9046-31f2a89e79ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429624666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.429624666
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1571521137
Short name T387
Test name
Test status
Simulation time 3447572899 ps
CPU time 7.41 seconds
Started Jun 05 03:49:55 PM PDT 24
Finished Jun 05 03:50:04 PM PDT 24
Peak memory 219436 kb
Host smart-28c01f42-7c3b-4558-b9a8-529f6950f474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571521137 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1571521137
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2345293178
Short name T101
Test name
Test status
Simulation time 2108810898 ps
CPU time 17.33 seconds
Started Jun 05 03:49:56 PM PDT 24
Finished Jun 05 03:50:15 PM PDT 24
Peak memory 211144 kb
Host smart-6d9fdb72-a13e-43d6-a129-1fc4c7721ea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345293178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2345293178
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1922625888
Short name T79
Test name
Test status
Simulation time 361597000 ps
CPU time 18.44 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:50:08 PM PDT 24
Peak memory 211176 kb
Host smart-ae2d6b45-0e54-4d73-91a1-03da76c99470
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922625888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1922625888
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.52290407
Short name T453
Test name
Test status
Simulation time 97558255 ps
CPU time 6.18 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:49:57 PM PDT 24
Peak memory 211116 kb
Host smart-1bc0cec4-3146-4ee3-b154-e663dde5238a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52290407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ct
rl_same_csr_outstanding.52290407
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2731713019
Short name T373
Test name
Test status
Simulation time 168344579 ps
CPU time 6.31 seconds
Started Jun 05 03:49:53 PM PDT 24
Finished Jun 05 03:50:01 PM PDT 24
Peak memory 219336 kb
Host smart-ebf76359-0e0b-4a63-bec6-c9dc85ff6346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731713019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2731713019
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1654960820
Short name T113
Test name
Test status
Simulation time 1166552547 ps
CPU time 40.91 seconds
Started Jun 05 03:49:56 PM PDT 24
Finished Jun 05 03:50:38 PM PDT 24
Peak memory 211152 kb
Host smart-d81bcd40-a8b8-4416-8c4f-31d6aa4dd551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654960820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1654960820
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3219350104
Short name T448
Test name
Test status
Simulation time 2863503089 ps
CPU time 12.15 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:50:03 PM PDT 24
Peak memory 219384 kb
Host smart-294d9a51-2549-4bbe-b6b4-62489079905f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219350104 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3219350104
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.177578237
Short name T87
Test name
Test status
Simulation time 2119887810 ps
CPU time 16.48 seconds
Started Jun 05 03:49:56 PM PDT 24
Finished Jun 05 03:50:14 PM PDT 24
Peak memory 211152 kb
Host smart-0e337c4e-0a16-4e7f-affd-59fac5423189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177578237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.177578237
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3881797946
Short name T91
Test name
Test status
Simulation time 8358595712 ps
CPU time 79.06 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:51:13 PM PDT 24
Peak memory 211236 kb
Host smart-52cc602a-d3da-4fd5-bcd7-555fc57af161
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881797946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3881797946
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2290804541
Short name T438
Test name
Test status
Simulation time 5544229227 ps
CPU time 12.68 seconds
Started Jun 05 03:49:56 PM PDT 24
Finished Jun 05 03:50:10 PM PDT 24
Peak memory 211532 kb
Host smart-989f112b-5e69-4292-a3c0-9d1d86d5d872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290804541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2290804541
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.251094302
Short name T449
Test name
Test status
Simulation time 1286780992 ps
CPU time 13.59 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:50:03 PM PDT 24
Peak memory 219400 kb
Host smart-605b4a30-3939-4cf6-b9bb-4ae10623cf6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251094302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.251094302
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1929624075
Short name T404
Test name
Test status
Simulation time 2354956292 ps
CPU time 40.36 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:50:31 PM PDT 24
Peak memory 212108 kb
Host smart-bc50470b-5e73-46bc-9b7a-de8f7c0b6f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929624075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1929624075
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3451702156
Short name T62
Test name
Test status
Simulation time 467047907 ps
CPU time 7.56 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:49:56 PM PDT 24
Peak memory 219400 kb
Host smart-06e96d39-b52f-4493-bdcf-3f941a8bccbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451702156 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3451702156
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.617138260
Short name T93
Test name
Test status
Simulation time 381603760 ps
CPU time 19.11 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:50:09 PM PDT 24
Peak memory 211172 kb
Host smart-13b186b6-428b-450c-ac8c-614246128d26
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617138260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.617138260
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.947557210
Short name T462
Test name
Test status
Simulation time 321413791 ps
CPU time 4.21 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:49:53 PM PDT 24
Peak memory 211160 kb
Host smart-476839a8-2486-4983-8324-04c2613ed493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947557210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.947557210
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.387886025
Short name T388
Test name
Test status
Simulation time 659513303 ps
CPU time 11.5 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:06 PM PDT 24
Peak memory 219408 kb
Host smart-ebaec0e4-7c03-46a2-b529-a6d277d8c2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387886025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.387886025
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3607199897
Short name T112
Test name
Test status
Simulation time 2609293706 ps
CPU time 41.78 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:34 PM PDT 24
Peak memory 212012 kb
Host smart-d0174187-4003-4d89-b850-93b21a076e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607199897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3607199897
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.607306571
Short name T90
Test name
Test status
Simulation time 1184009526 ps
CPU time 4.32 seconds
Started Jun 05 03:49:43 PM PDT 24
Finished Jun 05 03:49:49 PM PDT 24
Peak memory 211156 kb
Host smart-a8c9e5b9-d7fc-457b-8efc-c50aeb170cc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607306571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.607306571
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2985725372
Short name T372
Test name
Test status
Simulation time 838614361 ps
CPU time 7.33 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:49:56 PM PDT 24
Peak memory 211128 kb
Host smart-3d19581a-14c0-4c91-99b2-8df3f90bbfaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985725372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2985725372
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1498254983
Short name T396
Test name
Test status
Simulation time 1551073731 ps
CPU time 17.03 seconds
Started Jun 05 03:49:33 PM PDT 24
Finished Jun 05 03:49:51 PM PDT 24
Peak memory 211148 kb
Host smart-e68f9025-a114-443f-ade6-1b32a29ac00e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498254983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1498254983
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.957021223
Short name T398
Test name
Test status
Simulation time 915444378 ps
CPU time 6.47 seconds
Started Jun 05 03:49:30 PM PDT 24
Finished Jun 05 03:49:38 PM PDT 24
Peak memory 219672 kb
Host smart-e67683dd-4fd9-4960-a5c8-f61531e1fe87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957021223 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.957021223
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.593235236
Short name T446
Test name
Test status
Simulation time 2076773543 ps
CPU time 17.3 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:49 PM PDT 24
Peak memory 211156 kb
Host smart-83c0e746-4797-4078-96b7-f3779eeacbfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593235236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.593235236
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3552906866
Short name T447
Test name
Test status
Simulation time 8666204418 ps
CPU time 16.09 seconds
Started Jun 05 03:49:38 PM PDT 24
Finished Jun 05 03:49:55 PM PDT 24
Peak memory 210372 kb
Host smart-5be98ee8-e8d8-449f-88dd-f05a8d7e53b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552906866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3552906866
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2177439011
Short name T431
Test name
Test status
Simulation time 7059628213 ps
CPU time 10.2 seconds
Started Jun 05 03:49:28 PM PDT 24
Finished Jun 05 03:49:38 PM PDT 24
Peak memory 211116 kb
Host smart-6bb5e7c2-9f79-413e-a731-6aba2d7e36a7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177439011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2177439011
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.565367453
Short name T80
Test name
Test status
Simulation time 4001618483 ps
CPU time 51.79 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:50:24 PM PDT 24
Peak memory 211240 kb
Host smart-a9d8600d-6186-452f-a96f-eebc3b58d0a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565367453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.565367453
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2502613129
Short name T98
Test name
Test status
Simulation time 807421915 ps
CPU time 9.11 seconds
Started Jun 05 03:49:45 PM PDT 24
Finished Jun 05 03:49:55 PM PDT 24
Peak memory 211124 kb
Host smart-7073fbd7-e75e-42e2-9f10-4ac0f7fe7f5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502613129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2502613129
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1991992779
Short name T463
Test name
Test status
Simulation time 1565274631 ps
CPU time 17.37 seconds
Started Jun 05 03:49:37 PM PDT 24
Finished Jun 05 03:49:55 PM PDT 24
Peak memory 215572 kb
Host smart-5a2d826d-4d4f-4abe-8354-7f87a29c2f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991992779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1991992779
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2308247212
Short name T451
Test name
Test status
Simulation time 841884632 ps
CPU time 35.98 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:50:09 PM PDT 24
Peak memory 211160 kb
Host smart-bdebe5e3-7a3f-4c7e-ae85-641dd8b481c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308247212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2308247212
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2357163557
Short name T452
Test name
Test status
Simulation time 5474549715 ps
CPU time 12.37 seconds
Started Jun 05 03:49:37 PM PDT 24
Finished Jun 05 03:49:50 PM PDT 24
Peak memory 211208 kb
Host smart-42ea7eea-0de4-405b-b5cf-404bdf4e126d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357163557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2357163557
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4151115988
Short name T455
Test name
Test status
Simulation time 884834367 ps
CPU time 9.86 seconds
Started Jun 05 03:49:42 PM PDT 24
Finished Jun 05 03:49:53 PM PDT 24
Peak memory 211160 kb
Host smart-6165b6f7-0f72-424c-9b27-7f25780807db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151115988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4151115988
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1703553964
Short name T102
Test name
Test status
Simulation time 1298703087 ps
CPU time 15.11 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:48 PM PDT 24
Peak memory 211468 kb
Host smart-fac7aa1d-12b4-403c-b722-97c096584876
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703553964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1703553964
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1728642186
Short name T377
Test name
Test status
Simulation time 4962272337 ps
CPU time 11.51 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:43 PM PDT 24
Peak memory 213408 kb
Host smart-1f27940d-f4ab-40dd-9b35-8038a601f8e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728642186 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1728642186
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1613994419
Short name T414
Test name
Test status
Simulation time 424727167 ps
CPU time 6.92 seconds
Started Jun 05 03:49:42 PM PDT 24
Finished Jun 05 03:49:51 PM PDT 24
Peak memory 211128 kb
Host smart-9033fbc2-4e93-40fd-b421-f563da04d165
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613994419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1613994419
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3153775865
Short name T405
Test name
Test status
Simulation time 87150618 ps
CPU time 4.17 seconds
Started Jun 05 03:49:37 PM PDT 24
Finished Jun 05 03:49:42 PM PDT 24
Peak memory 211000 kb
Host smart-b206d7a4-8593-4053-bd0d-948685143b78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153775865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3153775865
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1814332032
Short name T422
Test name
Test status
Simulation time 3444891460 ps
CPU time 14.49 seconds
Started Jun 05 03:49:31 PM PDT 24
Finished Jun 05 03:49:46 PM PDT 24
Peak memory 211424 kb
Host smart-73e7b39d-5fb9-4513-9261-aac34c3c0485
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814332032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1814332032
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.192513439
Short name T441
Test name
Test status
Simulation time 15852870776 ps
CPU time 74.97 seconds
Started Jun 05 03:49:43 PM PDT 24
Finished Jun 05 03:51:00 PM PDT 24
Peak memory 211240 kb
Host smart-3abe5a2e-721b-4e3e-991e-8c37ee3c2aeb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192513439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.192513439
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3220150877
Short name T458
Test name
Test status
Simulation time 333502516 ps
CPU time 4.33 seconds
Started Jun 05 03:49:30 PM PDT 24
Finished Jun 05 03:49:35 PM PDT 24
Peak memory 211120 kb
Host smart-f086c8ea-c9d2-452a-a6d3-fecc17a9bdf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220150877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3220150877
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1453116413
Short name T410
Test name
Test status
Simulation time 381173116 ps
CPU time 11.41 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:49:45 PM PDT 24
Peak memory 219404 kb
Host smart-3818a55f-8828-47fc-8b1b-8fc41d11dde9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453116413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1453116413
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2222492703
Short name T454
Test name
Test status
Simulation time 428025415 ps
CPU time 69.36 seconds
Started Jun 05 03:49:44 PM PDT 24
Finished Jun 05 03:50:55 PM PDT 24
Peak memory 212184 kb
Host smart-c8ae6b66-38e9-47ea-a3e6-06fb5edf2d51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222492703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2222492703
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.478597360
Short name T83
Test name
Test status
Simulation time 3205646182 ps
CPU time 13.92 seconds
Started Jun 05 03:49:45 PM PDT 24
Finished Jun 05 03:50:00 PM PDT 24
Peak memory 211192 kb
Host smart-b0a58834-bbed-489b-8679-9e3ab1c490a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478597360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.478597360
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4111057213
Short name T430
Test name
Test status
Simulation time 15608457379 ps
CPU time 10.43 seconds
Started Jun 05 03:49:38 PM PDT 24
Finished Jun 05 03:49:50 PM PDT 24
Peak memory 211224 kb
Host smart-66b499d1-ea01-4c56-9d11-258f2d827fa3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111057213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.4111057213
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.795959849
Short name T424
Test name
Test status
Simulation time 11448310973 ps
CPU time 14.98 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:50:04 PM PDT 24
Peak memory 211220 kb
Host smart-9286d63f-9918-40d0-a7d2-49ebe4dbc30b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795959849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.795959849
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4101109272
Short name T385
Test name
Test status
Simulation time 2731979093 ps
CPU time 15.17 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:50:08 PM PDT 24
Peak memory 219436 kb
Host smart-1eddea36-d9f4-4665-8957-c7c75f7760d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101109272 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4101109272
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1138092771
Short name T457
Test name
Test status
Simulation time 88233908 ps
CPU time 4.38 seconds
Started Jun 05 03:49:42 PM PDT 24
Finished Jun 05 03:49:47 PM PDT 24
Peak memory 210396 kb
Host smart-cdf57c49-f971-4d2a-b0e6-85e68c5f4ee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138092771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1138092771
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1339830489
Short name T433
Test name
Test status
Simulation time 7515214403 ps
CPU time 14.17 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:55 PM PDT 24
Peak memory 211056 kb
Host smart-bb6674fb-4b25-4d5b-8670-0e1fb370266c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339830489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1339830489
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.5324743
Short name T394
Test name
Test status
Simulation time 844137433 ps
CPU time 9.28 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:49:43 PM PDT 24
Peak memory 211080 kb
Host smart-d4282b8f-9cbd-4194-bf7e-3bee57faeddf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5324743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.5324743
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.88170069
Short name T84
Test name
Test status
Simulation time 8123317483 ps
CPU time 43.82 seconds
Started Jun 05 03:49:33 PM PDT 24
Finished Jun 05 03:50:17 PM PDT 24
Peak memory 211228 kb
Host smart-c9809b9c-b74a-49c8-9cd9-1c64bb8b6dc3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88170069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pass
thru_mem_tl_intg_err.88170069
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3821076026
Short name T408
Test name
Test status
Simulation time 782943861 ps
CPU time 9.19 seconds
Started Jun 05 03:49:43 PM PDT 24
Finished Jun 05 03:49:54 PM PDT 24
Peak memory 211464 kb
Host smart-078041e8-ea6d-4272-af7b-a6f1f1d45763
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821076026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3821076026
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.488244027
Short name T382
Test name
Test status
Simulation time 2650414958 ps
CPU time 14.05 seconds
Started Jun 05 03:49:32 PM PDT 24
Finished Jun 05 03:49:47 PM PDT 24
Peak memory 219472 kb
Host smart-0d0519b6-9d8b-4190-b7ff-d636273ff0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488244027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.488244027
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3809983348
Short name T421
Test name
Test status
Simulation time 1086200349 ps
CPU time 10.72 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:50:00 PM PDT 24
Peak memory 219332 kb
Host smart-11d3638a-2ae1-4ee3-b6c3-30dd65c993e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809983348 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3809983348
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1842851343
Short name T436
Test name
Test status
Simulation time 976081863 ps
CPU time 9.61 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:01 PM PDT 24
Peak memory 211152 kb
Host smart-57fc07ee-d036-48a3-856a-cc181d871dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842851343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1842851343
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.401576938
Short name T426
Test name
Test status
Simulation time 380452539 ps
CPU time 18.35 seconds
Started Jun 05 03:49:45 PM PDT 24
Finished Jun 05 03:50:04 PM PDT 24
Peak memory 211144 kb
Host smart-5ae6ac1d-b703-45ff-8579-d7fa91418562
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401576938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.401576938
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.587813565
Short name T97
Test name
Test status
Simulation time 1936040259 ps
CPU time 15.83 seconds
Started Jun 05 03:49:42 PM PDT 24
Finished Jun 05 03:49:58 PM PDT 24
Peak memory 211156 kb
Host smart-d5a3238d-58e9-4f28-bee8-72aab819d4e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587813565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.587813565
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.448883956
Short name T393
Test name
Test status
Simulation time 433986502 ps
CPU time 8.41 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:03 PM PDT 24
Peak memory 214544 kb
Host smart-29a0458c-2421-444c-a5c4-336f6e5aaaf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448883956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.448883956
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2563842156
Short name T445
Test name
Test status
Simulation time 8556264938 ps
CPU time 46.98 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:39 PM PDT 24
Peak memory 219392 kb
Host smart-23939be6-bc0d-426d-a783-045ef525e3e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563842156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2563842156
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1146130336
Short name T400
Test name
Test status
Simulation time 763956019 ps
CPU time 8.21 seconds
Started Jun 05 03:49:58 PM PDT 24
Finished Jun 05 03:50:07 PM PDT 24
Peak memory 213584 kb
Host smart-04b1b005-65f7-4ce8-9516-1ba733dd9e0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146130336 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1146130336
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.598586377
Short name T389
Test name
Test status
Simulation time 1028800605 ps
CPU time 10.22 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:50 PM PDT 24
Peak memory 211140 kb
Host smart-6981ebe6-cc63-4ae9-b23b-caa8903151f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598586377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.598586377
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1787635182
Short name T92
Test name
Test status
Simulation time 18261973527 ps
CPU time 61.5 seconds
Started Jun 05 03:49:43 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 210492 kb
Host smart-c505c3fc-f813-46cd-9cf4-4223ffcd535e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787635182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1787635182
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1233520992
Short name T96
Test name
Test status
Simulation time 7234126591 ps
CPU time 15.41 seconds
Started Jun 05 03:49:37 PM PDT 24
Finished Jun 05 03:49:53 PM PDT 24
Peak memory 211216 kb
Host smart-9676e402-001d-45ff-a4c2-924b5809dfde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233520992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1233520992
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3235588655
Short name T378
Test name
Test status
Simulation time 1440686574 ps
CPU time 15.43 seconds
Started Jun 05 03:50:06 PM PDT 24
Finished Jun 05 03:50:23 PM PDT 24
Peak memory 219228 kb
Host smart-b0c2dc3f-59c5-4bef-8b22-becd6de68af6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235588655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3235588655
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3292323863
Short name T114
Test name
Test status
Simulation time 1977096975 ps
CPU time 47.56 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:39 PM PDT 24
Peak memory 211988 kb
Host smart-9e475945-efd5-45bd-808b-e778a9282283
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292323863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3292323863
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3171406389
Short name T384
Test name
Test status
Simulation time 1657173821 ps
CPU time 13.91 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:54 PM PDT 24
Peak memory 219392 kb
Host smart-494b96e9-ba75-48ca-ba06-758cb9728722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171406389 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3171406389
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4189903899
Short name T412
Test name
Test status
Simulation time 369361252 ps
CPU time 6.19 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:46 PM PDT 24
Peak memory 211120 kb
Host smart-9903d7b9-6077-4fe4-a63c-e6c2d59d7a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189903899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4189903899
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3252752650
Short name T81
Test name
Test status
Simulation time 56047677847 ps
CPU time 103.06 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 211240 kb
Host smart-22492924-f854-4b4a-94d7-2573ac0ff873
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252752650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3252752650
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.860066613
Short name T409
Test name
Test status
Simulation time 1529166172 ps
CPU time 6.84 seconds
Started Jun 05 03:49:38 PM PDT 24
Finished Jun 05 03:49:45 PM PDT 24
Peak memory 211104 kb
Host smart-f12bb2c7-b1b7-4f2e-9340-608ce5ae5fb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860066613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.860066613
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2823368122
Short name T416
Test name
Test status
Simulation time 378608205 ps
CPU time 6.61 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:49:49 PM PDT 24
Peak memory 219400 kb
Host smart-93df5960-3754-49d3-87b9-60f16f0ab6ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823368122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2823368122
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1239811250
Short name T107
Test name
Test status
Simulation time 4482745071 ps
CPU time 71.5 seconds
Started Jun 05 03:49:42 PM PDT 24
Finished Jun 05 03:50:55 PM PDT 24
Peak memory 213620 kb
Host smart-5e906b1b-5ac0-4500-a17e-2e6728c3f6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239811250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1239811250
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1904479653
Short name T444
Test name
Test status
Simulation time 280055645 ps
CPU time 6.59 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:01 PM PDT 24
Peak memory 214292 kb
Host smart-e3f28528-f86b-4122-b2e1-e5619bfe695e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904479653 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1904479653
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3722233856
Short name T397
Test name
Test status
Simulation time 1310702230 ps
CPU time 12.57 seconds
Started Jun 05 03:49:44 PM PDT 24
Finished Jun 05 03:49:57 PM PDT 24
Peak memory 211136 kb
Host smart-e72ec73d-ed89-48b7-9a2e-0cc768e288f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722233856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3722233856
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2830091260
Short name T88
Test name
Test status
Simulation time 9234677310 ps
CPU time 79.06 seconds
Started Jun 05 03:49:53 PM PDT 24
Finished Jun 05 03:51:14 PM PDT 24
Peak memory 211236 kb
Host smart-dbcc467b-2bc0-417b-bada-daff20be0ee3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830091260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2830091260
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2482578207
Short name T429
Test name
Test status
Simulation time 1283602773 ps
CPU time 12.94 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:50:04 PM PDT 24
Peak memory 211156 kb
Host smart-bafb00bb-1ff3-4bd1-9e3d-dc31f290f9f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482578207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2482578207
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1744446538
Short name T450
Test name
Test status
Simulation time 93860477 ps
CPU time 6.36 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:46 PM PDT 24
Peak memory 219404 kb
Host smart-c457bfba-5fa8-41ff-96d8-13c5e306276c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744446538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1744446538
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2455117491
Short name T432
Test name
Test status
Simulation time 2282291554 ps
CPU time 79.29 seconds
Started Jun 05 03:49:41 PM PDT 24
Finished Jun 05 03:51:01 PM PDT 24
Peak memory 212128 kb
Host smart-0c1a75e8-01e1-4852-9070-e3b85e6f2ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455117491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2455117491
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1797348022
Short name T464
Test name
Test status
Simulation time 2340392731 ps
CPU time 12.28 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:52 PM PDT 24
Peak memory 219436 kb
Host smart-3e422e6f-7393-4372-b9a1-8167e5826f74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797348022 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1797348022
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1536029182
Short name T99
Test name
Test status
Simulation time 6629531750 ps
CPU time 14.5 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:49:55 PM PDT 24
Peak memory 211212 kb
Host smart-6289cc30-bfa9-4d39-8923-963eda981a78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536029182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1536029182
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.961625436
Short name T420
Test name
Test status
Simulation time 16713442604 ps
CPU time 68.86 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:51:03 PM PDT 24
Peak memory 211240 kb
Host smart-792d035b-aedd-4149-9788-14f326a05c00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961625436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.961625436
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.344978303
Short name T68
Test name
Test status
Simulation time 4020223423 ps
CPU time 16.12 seconds
Started Jun 05 03:49:42 PM PDT 24
Finished Jun 05 03:49:59 PM PDT 24
Peak memory 211220 kb
Host smart-b902f96e-3b11-48bd-b364-87808f4af56c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344978303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.344978303
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4134514856
Short name T381
Test name
Test status
Simulation time 14183872104 ps
CPU time 18.51 seconds
Started Jun 05 03:49:42 PM PDT 24
Finished Jun 05 03:50:02 PM PDT 24
Peak memory 219468 kb
Host smart-01c78ca2-a7d1-4469-863f-0629721750d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134514856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4134514856
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.154950163
Short name T58
Test name
Test status
Simulation time 253400209 ps
CPU time 70 seconds
Started Jun 05 03:49:39 PM PDT 24
Finished Jun 05 03:50:50 PM PDT 24
Peak memory 211992 kb
Host smart-40af0fc8-5e33-4222-a0f3-d68a922dd7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154950163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.154950163
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.724221848
Short name T330
Test name
Test status
Simulation time 133632782 ps
CPU time 5.08 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:49:58 PM PDT 24
Peak memory 211024 kb
Host smart-5b7c072d-8b03-4f89-a455-489bc2f3b49c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724221848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.724221848
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.254343215
Short name T146
Test name
Test status
Simulation time 2201993402 ps
CPU time 141.88 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:52:15 PM PDT 24
Peak memory 238832 kb
Host smart-c2241378-f19a-4bba-afa3-64604b32d418
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254343215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.254343215
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2507276145
Short name T355
Test name
Test status
Simulation time 11248518477 ps
CPU time 26.49 seconds
Started Jun 05 03:49:56 PM PDT 24
Finished Jun 05 03:50:24 PM PDT 24
Peak memory 212092 kb
Host smart-37b04ed2-9098-404b-8024-926e8c516b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507276145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2507276145
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.186103656
Short name T315
Test name
Test status
Simulation time 2366293124 ps
CPU time 8.52 seconds
Started Jun 05 03:49:58 PM PDT 24
Finished Jun 05 03:50:08 PM PDT 24
Peak memory 210940 kb
Host smart-738fc97f-6c9a-4c4e-a140-0c0a11769328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186103656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.186103656
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.17803770
Short name T136
Test name
Test status
Simulation time 370455040 ps
CPU time 10.4 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:50:01 PM PDT 24
Peak memory 213324 kb
Host smart-acea94a0-2e5e-439b-bdc8-86f19a2fafd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17803770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.17803770
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2418166306
Short name T363
Test name
Test status
Simulation time 6381363095 ps
CPU time 23.05 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:15 PM PDT 24
Peak memory 214220 kb
Host smart-941ce3eb-6af3-4808-83a7-dbb0a47b9d9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418166306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2418166306
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1365442827
Short name T6
Test name
Test status
Simulation time 4796428731 ps
CPU time 11.68 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:11 PM PDT 24
Peak memory 210720 kb
Host smart-25e2720d-a2c9-488d-aed4-11f57bb489bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365442827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1365442827
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.754559693
Short name T173
Test name
Test status
Simulation time 6156808952 ps
CPU time 137.68 seconds
Started Jun 05 03:49:54 PM PDT 24
Finished Jun 05 03:52:14 PM PDT 24
Peak memory 237536 kb
Host smart-c1d29d98-6fa2-45a3-a901-f211766b19ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754559693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.754559693
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3661612368
Short name T132
Test name
Test status
Simulation time 6827625870 ps
CPU time 15.28 seconds
Started Jun 05 03:49:53 PM PDT 24
Finished Jun 05 03:50:10 PM PDT 24
Peak memory 212192 kb
Host smart-5e9ebe89-67b5-4df1-ab0a-5c109b7f2dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661612368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3661612368
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2986455541
Short name T262
Test name
Test status
Simulation time 487906876 ps
CPU time 5.57 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:49:58 PM PDT 24
Peak memory 210908 kb
Host smart-e0bd66dd-84d6-4a8c-a047-3243d72fda50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986455541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2986455541
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2733991638
Short name T36
Test name
Test status
Simulation time 3645363859 ps
CPU time 112.06 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:51:42 PM PDT 24
Peak memory 238544 kb
Host smart-5b6bbb01-09c4-427d-8078-e2f133f75e42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733991638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2733991638
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2259247673
Short name T95
Test name
Test status
Simulation time 666366515 ps
CPU time 9.53 seconds
Started Jun 05 03:50:01 PM PDT 24
Finished Jun 05 03:50:12 PM PDT 24
Peak memory 219092 kb
Host smart-4ad5a17d-9860-4d04-a45f-45dd7899608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259247673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2259247673
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3119586510
Short name T153
Test name
Test status
Simulation time 266476953 ps
CPU time 5.91 seconds
Started Jun 05 03:50:04 PM PDT 24
Finished Jun 05 03:50:11 PM PDT 24
Peak memory 211016 kb
Host smart-7f62df17-1d88-40ed-a82f-e55fc009bdd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119586510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3119586510
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.579416195
Short name T42
Test name
Test status
Simulation time 75501190280 ps
CPU time 254.64 seconds
Started Jun 05 03:50:04 PM PDT 24
Finished Jun 05 03:54:19 PM PDT 24
Peak memory 237156 kb
Host smart-824f330b-0aa7-4e48-a143-06d8f7821109
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579416195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.579416195
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2289084486
Short name T201
Test name
Test status
Simulation time 39041609456 ps
CPU time 36.39 seconds
Started Jun 05 03:50:05 PM PDT 24
Finished Jun 05 03:50:42 PM PDT 24
Peak memory 212996 kb
Host smart-01d97598-0189-4865-a8b5-2ed244acbb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289084486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2289084486
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2075093953
Short name T254
Test name
Test status
Simulation time 1986999108 ps
CPU time 17.27 seconds
Started Jun 05 03:50:01 PM PDT 24
Finished Jun 05 03:50:20 PM PDT 24
Peak memory 210888 kb
Host smart-15bcc386-8104-4b4d-ab5f-9d70aa0b5a41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075093953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2075093953
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2017582852
Short name T56
Test name
Test status
Simulation time 2811323385 ps
CPU time 25.61 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:26 PM PDT 24
Peak memory 212536 kb
Host smart-38a5df32-52bc-4a3b-b20d-9fff3625b599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017582852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2017582852
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.36914257
Short name T356
Test name
Test status
Simulation time 9849936217 ps
CPU time 76.85 seconds
Started Jun 05 03:50:02 PM PDT 24
Finished Jun 05 03:51:21 PM PDT 24
Peak memory 217332 kb
Host smart-6d7e7546-56fa-44d4-b9ae-6d40523ec3f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36914257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 10.rom_ctrl_stress_all.36914257
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.498413573
Short name T364
Test name
Test status
Simulation time 62204190370 ps
CPU time 2481.83 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 04:31:22 PM PDT 24
Peak memory 250888 kb
Host smart-fd478bee-f918-4eb6-858e-c5c4447ec3bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498413573 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.498413573
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3492232523
Short name T329
Test name
Test status
Simulation time 2447766282 ps
CPU time 12.36 seconds
Started Jun 05 03:49:57 PM PDT 24
Finished Jun 05 03:50:11 PM PDT 24
Peak memory 211064 kb
Host smart-d47ef320-3d8d-4a3f-af7e-da83d5b7258f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492232523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3492232523
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4229584845
Short name T358
Test name
Test status
Simulation time 3846767441 ps
CPU time 110 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:51:50 PM PDT 24
Peak memory 237628 kb
Host smart-941496bf-b716-4159-8992-928db9fe887e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229584845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4229584845
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1490895150
Short name T250
Test name
Test status
Simulation time 3763726836 ps
CPU time 31.83 seconds
Started Jun 05 03:50:06 PM PDT 24
Finished Jun 05 03:50:39 PM PDT 24
Peak memory 211548 kb
Host smart-4362a07d-e538-441b-a7a1-67fdedd39f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490895150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1490895150
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1469933995
Short name T103
Test name
Test status
Simulation time 4974533171 ps
CPU time 12.84 seconds
Started Jun 05 03:50:00 PM PDT 24
Finished Jun 05 03:50:14 PM PDT 24
Peak memory 210984 kb
Host smart-afb575b1-2d2a-482f-a444-f5efe3aac560
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469933995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1469933995
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1479396400
Short name T331
Test name
Test status
Simulation time 3482959952 ps
CPU time 30.13 seconds
Started Jun 05 03:50:02 PM PDT 24
Finished Jun 05 03:50:33 PM PDT 24
Peak memory 219152 kb
Host smart-bdffe7c2-4228-4591-93a3-b0bfe184dc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479396400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1479396400
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.548284448
Short name T47
Test name
Test status
Simulation time 574154989511 ps
CPU time 5352.91 seconds
Started Jun 05 03:50:00 PM PDT 24
Finished Jun 05 05:19:15 PM PDT 24
Peak memory 252016 kb
Host smart-35c761d9-0ce4-4d0e-b80a-72f15b4dd496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548284448 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.548284448
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4154207626
Short name T280
Test name
Test status
Simulation time 333859735 ps
CPU time 4.15 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:04 PM PDT 24
Peak memory 211400 kb
Host smart-68cb9ce3-9461-4a19-9b00-fc5d3b94ccce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154207626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4154207626
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2419011103
Short name T234
Test name
Test status
Simulation time 8888434259 ps
CPU time 185.12 seconds
Started Jun 05 03:50:08 PM PDT 24
Finished Jun 05 03:53:14 PM PDT 24
Peak memory 234580 kb
Host smart-b0970e99-6300-4f18-8b71-6b7e610ea2f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419011103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2419011103
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.474418722
Short name T156
Test name
Test status
Simulation time 1324121100 ps
CPU time 17.95 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:18 PM PDT 24
Peak memory 211008 kb
Host smart-9d416da4-4ab4-4d0c-810a-720b8b88d769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474418722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.474418722
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.340092502
Short name T192
Test name
Test status
Simulation time 6585266663 ps
CPU time 16.19 seconds
Started Jun 05 03:49:57 PM PDT 24
Finished Jun 05 03:50:14 PM PDT 24
Peak memory 210936 kb
Host smart-16991ebe-e162-4340-8ce5-32e8db35514d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340092502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.340092502
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.48696949
Short name T125
Test name
Test status
Simulation time 3436466521 ps
CPU time 29.16 seconds
Started Jun 05 03:50:01 PM PDT 24
Finished Jun 05 03:50:31 PM PDT 24
Peak memory 213004 kb
Host smart-e32bfff5-651c-4072-a5c0-f2d81422e7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48696949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.48696949
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4162793729
Short name T275
Test name
Test status
Simulation time 171913229 ps
CPU time 4.32 seconds
Started Jun 05 03:49:58 PM PDT 24
Finished Jun 05 03:50:04 PM PDT 24
Peak memory 211036 kb
Host smart-f9b6eec1-72b0-4549-a562-1eb8ee8f67a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162793729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4162793729
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2410865809
Short name T342
Test name
Test status
Simulation time 221773033259 ps
CPU time 380.97 seconds
Started Jun 05 03:50:05 PM PDT 24
Finished Jun 05 03:56:27 PM PDT 24
Peak memory 213316 kb
Host smart-abde0b04-dec5-4f03-9df2-3947c5838066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410865809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2410865809
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2589309295
Short name T172
Test name
Test status
Simulation time 6559597039 ps
CPU time 20.33 seconds
Started Jun 05 03:50:07 PM PDT 24
Finished Jun 05 03:50:29 PM PDT 24
Peak memory 211392 kb
Host smart-92acf711-f944-4f2e-beb8-87039b8fd389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589309295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2589309295
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.230996089
Short name T199
Test name
Test status
Simulation time 873223393 ps
CPU time 11.07 seconds
Started Jun 05 03:50:02 PM PDT 24
Finished Jun 05 03:50:15 PM PDT 24
Peak memory 210888 kb
Host smart-f27295d7-b94e-49b0-9585-6dc8da7431fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230996089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.230996089
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1829852692
Short name T169
Test name
Test status
Simulation time 541468722 ps
CPU time 14.93 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:15 PM PDT 24
Peak memory 213236 kb
Host smart-5cf07566-f019-4f76-8b77-a380dd81d0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829852692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1829852692
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1287962061
Short name T208
Test name
Test status
Simulation time 621018545 ps
CPU time 18.89 seconds
Started Jun 05 03:50:00 PM PDT 24
Finished Jun 05 03:50:20 PM PDT 24
Peak memory 219080 kb
Host smart-2f474786-3009-446c-89aa-c9d41a8b5b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287962061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1287962061
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2586485222
Short name T64
Test name
Test status
Simulation time 10959525987 ps
CPU time 16.29 seconds
Started Jun 05 03:50:00 PM PDT 24
Finished Jun 05 03:50:17 PM PDT 24
Peak memory 211056 kb
Host smart-4bae52b2-0fc2-448c-8fa5-07d25ec8d5af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586485222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2586485222
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1681342311
Short name T360
Test name
Test status
Simulation time 26944740713 ps
CPU time 181.34 seconds
Started Jun 05 03:49:58 PM PDT 24
Finished Jun 05 03:53:00 PM PDT 24
Peak memory 229244 kb
Host smart-1753665f-0b93-49a2-86e8-d08d47eaa86a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681342311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1681342311
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2094078672
Short name T116
Test name
Test status
Simulation time 27355203672 ps
CPU time 19.59 seconds
Started Jun 05 03:50:01 PM PDT 24
Finished Jun 05 03:50:22 PM PDT 24
Peak memory 212060 kb
Host smart-f6091f94-bd72-4208-835f-c7a5d0c0ab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094078672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2094078672
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1342050662
Short name T353
Test name
Test status
Simulation time 4314824521 ps
CPU time 11.72 seconds
Started Jun 05 03:50:07 PM PDT 24
Finished Jun 05 03:50:20 PM PDT 24
Peak memory 210984 kb
Host smart-9cd80adc-a003-4843-9375-01c9f08a00cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342050662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1342050662
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.346900504
Short name T258
Test name
Test status
Simulation time 190680372 ps
CPU time 10.82 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:11 PM PDT 24
Peak memory 212860 kb
Host smart-d181db0d-72f7-46fd-a909-0613bfbb302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346900504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.346900504
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1072218701
Short name T222
Test name
Test status
Simulation time 8760796896 ps
CPU time 31 seconds
Started Jun 05 03:50:13 PM PDT 24
Finished Jun 05 03:50:45 PM PDT 24
Peak memory 219140 kb
Host smart-94534f4d-70c5-4982-80de-c935bf59bb8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072218701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1072218701
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4008835405
Short name T210
Test name
Test status
Simulation time 89083984 ps
CPU time 4.41 seconds
Started Jun 05 03:50:04 PM PDT 24
Finished Jun 05 03:50:09 PM PDT 24
Peak memory 211024 kb
Host smart-69a93b2e-f641-4489-8a3f-32d404528b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008835405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4008835405
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3836477275
Short name T41
Test name
Test status
Simulation time 21205236171 ps
CPU time 286.76 seconds
Started Jun 05 03:50:03 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 234000 kb
Host smart-dcf332a9-90d8-4739-92b4-64526742b3ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836477275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3836477275
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2154255899
Short name T120
Test name
Test status
Simulation time 3006132516 ps
CPU time 27.82 seconds
Started Jun 05 03:49:58 PM PDT 24
Finished Jun 05 03:50:27 PM PDT 24
Peak memory 211096 kb
Host smart-ab976fd0-02d7-467d-8d67-4fc1597b118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154255899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2154255899
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3641376195
Short name T142
Test name
Test status
Simulation time 6454677907 ps
CPU time 18.12 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:18 PM PDT 24
Peak memory 210588 kb
Host smart-00620d46-a6ea-4443-9098-5d7b5ac42def
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641376195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3641376195
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.686732519
Short name T12
Test name
Test status
Simulation time 13081064515 ps
CPU time 37.51 seconds
Started Jun 05 03:50:01 PM PDT 24
Finished Jun 05 03:50:40 PM PDT 24
Peak memory 214240 kb
Host smart-139a3936-447f-4e6a-9d19-8ef573ec3843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686732519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.686732519
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3997958845
Short name T343
Test name
Test status
Simulation time 15599892096 ps
CPU time 56.16 seconds
Started Jun 05 03:50:01 PM PDT 24
Finished Jun 05 03:50:58 PM PDT 24
Peak memory 216312 kb
Host smart-5e5b643f-b862-41f8-ae4f-3054c0c4040b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997958845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3997958845
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1338147160
Short name T301
Test name
Test status
Simulation time 1689686051 ps
CPU time 14.44 seconds
Started Jun 05 03:50:01 PM PDT 24
Finished Jun 05 03:50:16 PM PDT 24
Peak memory 211040 kb
Host smart-e214ecc6-9963-48e0-bec6-b90ea085df58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338147160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1338147160
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.514120682
Short name T123
Test name
Test status
Simulation time 69456433735 ps
CPU time 210.98 seconds
Started Jun 05 03:50:03 PM PDT 24
Finished Jun 05 03:53:35 PM PDT 24
Peak memory 230404 kb
Host smart-77e711d4-9546-4789-ad70-5a8433d02482
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514120682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.514120682
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1794681067
Short name T119
Test name
Test status
Simulation time 2128996592 ps
CPU time 22.11 seconds
Started Jun 05 03:50:02 PM PDT 24
Finished Jun 05 03:50:26 PM PDT 24
Peak memory 211624 kb
Host smart-6e1013bb-d61b-41af-9c0b-43c7e34ccbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794681067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1794681067
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3060364338
Short name T167
Test name
Test status
Simulation time 728262013 ps
CPU time 10.03 seconds
Started Jun 05 03:50:07 PM PDT 24
Finished Jun 05 03:50:18 PM PDT 24
Peak memory 210888 kb
Host smart-232294cb-148c-435e-a86b-30009a3cd1ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3060364338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3060364338
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3879813708
Short name T306
Test name
Test status
Simulation time 4759203161 ps
CPU time 16.82 seconds
Started Jun 05 03:50:02 PM PDT 24
Finished Jun 05 03:50:20 PM PDT 24
Peak memory 213776 kb
Host smart-84b0def1-41ba-465d-b0ec-37e43a308d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879813708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3879813708
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.808653280
Short name T180
Test name
Test status
Simulation time 28587916774 ps
CPU time 87.45 seconds
Started Jun 05 03:50:08 PM PDT 24
Finished Jun 05 03:51:36 PM PDT 24
Peak memory 219372 kb
Host smart-d1ddbc67-2bda-4085-9d2c-d04bfa218fe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808653280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.808653280
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2425939338
Short name T197
Test name
Test status
Simulation time 2546781557 ps
CPU time 12 seconds
Started Jun 05 03:50:06 PM PDT 24
Finished Jun 05 03:50:19 PM PDT 24
Peak memory 211096 kb
Host smart-db52c638-f442-43bc-8c2a-98c8a3066a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425939338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2425939338
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.340112819
Short name T131
Test name
Test status
Simulation time 3226612264 ps
CPU time 99.82 seconds
Started Jun 05 03:50:11 PM PDT 24
Finished Jun 05 03:51:52 PM PDT 24
Peak memory 237544 kb
Host smart-c0d22ed1-9797-43dd-b17b-69778b72e443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340112819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.340112819
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3130745933
Short name T270
Test name
Test status
Simulation time 173940753 ps
CPU time 9.3 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 03:50:22 PM PDT 24
Peak memory 211532 kb
Host smart-9963539b-e77d-4d78-8ff1-af73df2319bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130745933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3130745933
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2548493429
Short name T344
Test name
Test status
Simulation time 4807659231 ps
CPU time 13.2 seconds
Started Jun 05 03:50:01 PM PDT 24
Finished Jun 05 03:50:16 PM PDT 24
Peak memory 211068 kb
Host smart-15087b1c-3aad-4777-bea9-738f33314dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2548493429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2548493429
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1870071450
Short name T304
Test name
Test status
Simulation time 934676797 ps
CPU time 16.41 seconds
Started Jun 05 03:50:00 PM PDT 24
Finished Jun 05 03:50:17 PM PDT 24
Peak memory 213424 kb
Host smart-c459bcb7-bb3f-4938-bc8d-7d724ab6a88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870071450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1870071450
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.152278977
Short name T346
Test name
Test status
Simulation time 24929781861 ps
CPU time 34.72 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:35 PM PDT 24
Peak memory 212932 kb
Host smart-b13f0946-5cb3-4cc0-8ae4-18c94541e561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152278977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.152278977
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3986340291
Short name T354
Test name
Test status
Simulation time 460969120 ps
CPU time 5.24 seconds
Started Jun 05 03:50:10 PM PDT 24
Finished Jun 05 03:50:16 PM PDT 24
Peak memory 211012 kb
Host smart-4f51099d-2442-47c6-be64-74bc349ea94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986340291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3986340291
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3675687480
Short name T161
Test name
Test status
Simulation time 2055777458 ps
CPU time 122.48 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 03:52:16 PM PDT 24
Peak memory 238532 kb
Host smart-30ef3087-35eb-446c-bfb4-6cfd88e32146
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675687480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3675687480
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4051617157
Short name T23
Test name
Test status
Simulation time 8544001651 ps
CPU time 23.97 seconds
Started Jun 05 03:50:07 PM PDT 24
Finished Jun 05 03:50:32 PM PDT 24
Peak memory 212300 kb
Host smart-428b5a1d-42a8-4927-ac16-288b903987bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051617157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4051617157
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2513882701
Short name T163
Test name
Test status
Simulation time 5502913663 ps
CPU time 13.21 seconds
Started Jun 05 03:50:10 PM PDT 24
Finished Jun 05 03:50:24 PM PDT 24
Peak memory 210948 kb
Host smart-d6282031-35dd-4914-ad8b-75a33c05a289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513882701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2513882701
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3454631073
Short name T312
Test name
Test status
Simulation time 17526534797 ps
CPU time 32.09 seconds
Started Jun 05 03:50:06 PM PDT 24
Finished Jun 05 03:50:40 PM PDT 24
Peak memory 219472 kb
Host smart-812009c8-e353-41c3-acc0-ae3ae632dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454631073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3454631073
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1083908409
Short name T348
Test name
Test status
Simulation time 90702178 ps
CPU time 6.47 seconds
Started Jun 05 03:50:11 PM PDT 24
Finished Jun 05 03:50:18 PM PDT 24
Peak memory 210848 kb
Host smart-4579731d-3681-43fa-8fff-e6ddb8816751
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083908409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1083908409
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1964894668
Short name T49
Test name
Test status
Simulation time 158315052273 ps
CPU time 5434.6 seconds
Started Jun 05 03:50:34 PM PDT 24
Finished Jun 05 05:21:10 PM PDT 24
Peak memory 228592 kb
Host smart-75526606-6ed7-4b0f-8c9a-b230a9fe811a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964894668 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1964894668
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2579247468
Short name T285
Test name
Test status
Simulation time 6661234330 ps
CPU time 14.86 seconds
Started Jun 05 03:50:16 PM PDT 24
Finished Jun 05 03:50:31 PM PDT 24
Peak memory 211100 kb
Host smart-5366fd03-84f1-49e8-a6ce-0dd28ba4258e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579247468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2579247468
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.592033004
Short name T288
Test name
Test status
Simulation time 44472105093 ps
CPU time 449.3 seconds
Started Jun 05 03:50:13 PM PDT 24
Finished Jun 05 03:57:43 PM PDT 24
Peak memory 233956 kb
Host smart-94bb1498-d92a-4c55-b302-1d16cc826e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592033004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.592033004
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3990848984
Short name T117
Test name
Test status
Simulation time 11800724884 ps
CPU time 26.68 seconds
Started Jun 05 03:50:23 PM PDT 24
Finished Jun 05 03:50:50 PM PDT 24
Peak memory 211584 kb
Host smart-9f653105-9968-4da8-b678-bb118f4ea67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990848984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3990848984
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2648739488
Short name T219
Test name
Test status
Simulation time 1122041498 ps
CPU time 12.73 seconds
Started Jun 05 03:50:20 PM PDT 24
Finished Jun 05 03:50:34 PM PDT 24
Peak memory 210904 kb
Host smart-9cad4c48-f8bb-4d87-b0bf-84f4dd773672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648739488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2648739488
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.529757313
Short name T299
Test name
Test status
Simulation time 2889811099 ps
CPU time 26.93 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 213512 kb
Host smart-eb8f1619-8d18-40f4-813f-dd3eb689ebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529757313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.529757313
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2490997543
Short name T300
Test name
Test status
Simulation time 3173166078 ps
CPU time 29.83 seconds
Started Jun 05 03:50:26 PM PDT 24
Finished Jun 05 03:50:57 PM PDT 24
Peak memory 213236 kb
Host smart-8935041f-16d7-464d-8ac3-361367209896
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490997543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2490997543
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.644454698
Short name T171
Test name
Test status
Simulation time 479221998 ps
CPU time 7.56 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:49:58 PM PDT 24
Peak memory 211388 kb
Host smart-4ad2acdd-b3f7-4306-ba64-11ae802b186b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644454698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.644454698
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.47580666
Short name T305
Test name
Test status
Simulation time 1270704514 ps
CPU time 83.45 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:51:14 PM PDT 24
Peak memory 233360 kb
Host smart-32a2f6a8-b774-4455-b2b4-2e3a66787457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47580666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_cor
rupt_sig_fatal_chk.47580666
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.177356312
Short name T328
Test name
Test status
Simulation time 1261788406 ps
CPU time 18 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:10 PM PDT 24
Peak memory 211688 kb
Host smart-8818dc74-3b8b-4542-9d3a-266d14dfceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177356312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.177356312
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3183628319
Short name T255
Test name
Test status
Simulation time 98745368 ps
CPU time 5.51 seconds
Started Jun 05 03:49:54 PM PDT 24
Finished Jun 05 03:50:02 PM PDT 24
Peak memory 210924 kb
Host smart-ca30981f-bd70-40ca-99af-11111ab6f841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183628319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3183628319
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1599303838
Short name T33
Test name
Test status
Simulation time 4258315189 ps
CPU time 111.36 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:51:40 PM PDT 24
Peak memory 230568 kb
Host smart-91520d3a-489a-499e-83d4-4fd4a68e10f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599303838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1599303838
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1463140260
Short name T76
Test name
Test status
Simulation time 3878737427 ps
CPU time 18.45 seconds
Started Jun 05 03:49:53 PM PDT 24
Finished Jun 05 03:50:14 PM PDT 24
Peak memory 213416 kb
Host smart-7c1809ac-559e-4a60-ab97-d689c534ea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463140260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1463140260
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.289202362
Short name T248
Test name
Test status
Simulation time 2120971697 ps
CPU time 26.52 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:21 PM PDT 24
Peak memory 219068 kb
Host smart-8cb95a7f-816a-4281-88ea-c74f48c9e892
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289202362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.289202362
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2590131928
Short name T269
Test name
Test status
Simulation time 70671211367 ps
CPU time 303.68 seconds
Started Jun 05 03:50:34 PM PDT 24
Finished Jun 05 03:55:38 PM PDT 24
Peak memory 211284 kb
Host smart-377f15a4-f77c-4443-afb2-365eb2fd74a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590131928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2590131928
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.601355722
Short name T308
Test name
Test status
Simulation time 2585315365 ps
CPU time 23.78 seconds
Started Jun 05 03:50:09 PM PDT 24
Finished Jun 05 03:50:33 PM PDT 24
Peak memory 211600 kb
Host smart-4c265492-be30-4f6c-af62-a03d20a42d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601355722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.601355722
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.150118235
Short name T25
Test name
Test status
Simulation time 654296246 ps
CPU time 9.71 seconds
Started Jun 05 03:50:17 PM PDT 24
Finished Jun 05 03:50:28 PM PDT 24
Peak memory 210144 kb
Host smart-8d918667-c41c-44a6-8468-113ee1e08bb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150118235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.150118235
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2535478055
Short name T179
Test name
Test status
Simulation time 2294164453 ps
CPU time 24.25 seconds
Started Jun 05 03:50:06 PM PDT 24
Finished Jun 05 03:50:32 PM PDT 24
Peak memory 219136 kb
Host smart-5aeeebc9-1445-4a05-becc-ac64ab2b5614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535478055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2535478055
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2385035846
Short name T139
Test name
Test status
Simulation time 307731834 ps
CPU time 15.38 seconds
Started Jun 05 03:50:16 PM PDT 24
Finished Jun 05 03:50:32 PM PDT 24
Peak memory 213028 kb
Host smart-30ec7345-4c3f-404c-8dfc-74f6e9d31670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385035846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2385035846
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.403379461
Short name T51
Test name
Test status
Simulation time 42639449540 ps
CPU time 1840.17 seconds
Started Jun 05 03:50:09 PM PDT 24
Finished Jun 05 04:20:51 PM PDT 24
Peak memory 238988 kb
Host smart-0048d8bc-d276-4bd8-b6c6-9c6eb8182d40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403379461 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.403379461
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3016228351
Short name T245
Test name
Test status
Simulation time 9311010150 ps
CPU time 16.64 seconds
Started Jun 05 03:50:07 PM PDT 24
Finished Jun 05 03:50:25 PM PDT 24
Peak memory 211068 kb
Host smart-49c10377-4d49-421c-817b-f94a25b2ac02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016228351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3016228351
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1331847789
Short name T30
Test name
Test status
Simulation time 3379345872 ps
CPU time 93.86 seconds
Started Jun 05 03:50:09 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 212764 kb
Host smart-cb7450bc-1697-42ab-8361-6b122fa2362d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331847789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1331847789
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3829893385
Short name T212
Test name
Test status
Simulation time 976148287 ps
CPU time 9.58 seconds
Started Jun 05 03:50:15 PM PDT 24
Finished Jun 05 03:50:25 PM PDT 24
Peak memory 211492 kb
Host smart-49c977f8-02ee-455e-be1c-81c6710f3c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829893385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3829893385
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.956780511
Short name T144
Test name
Test status
Simulation time 397920844 ps
CPU time 5.44 seconds
Started Jun 05 03:50:15 PM PDT 24
Finished Jun 05 03:50:22 PM PDT 24
Peak memory 210928 kb
Host smart-3f27e35a-85e6-49b4-b031-eaf5352eb92f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956780511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.956780511
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1800385521
Short name T150
Test name
Test status
Simulation time 360056521 ps
CPU time 9.84 seconds
Started Jun 05 03:50:20 PM PDT 24
Finished Jun 05 03:50:30 PM PDT 24
Peak memory 219092 kb
Host smart-4f80cb9f-bb30-4a6e-b00d-72e0c7977c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800385521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1800385521
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.230700137
Short name T368
Test name
Test status
Simulation time 3396417649 ps
CPU time 32.97 seconds
Started Jun 05 03:50:06 PM PDT 24
Finished Jun 05 03:50:40 PM PDT 24
Peak memory 219256 kb
Host smart-5aba5e25-657b-469e-b43d-57dde87796b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230700137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.230700137
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.88668493
Short name T48
Test name
Test status
Simulation time 114828221300 ps
CPU time 2349.82 seconds
Started Jun 05 03:50:14 PM PDT 24
Finished Jun 05 04:29:25 PM PDT 24
Peak memory 235740 kb
Host smart-7db73528-07d0-4830-b687-939d8b8299db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88668493 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.88668493
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1168448131
Short name T230
Test name
Test status
Simulation time 5651387383 ps
CPU time 13.55 seconds
Started Jun 05 03:50:21 PM PDT 24
Finished Jun 05 03:50:35 PM PDT 24
Peak memory 211100 kb
Host smart-b7d195a6-6fbe-492f-be75-debaf8847330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168448131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1168448131
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2999897961
Short name T176
Test name
Test status
Simulation time 1755080389 ps
CPU time 122.15 seconds
Started Jun 05 03:50:22 PM PDT 24
Finished Jun 05 03:52:25 PM PDT 24
Peak memory 237344 kb
Host smart-99026705-14f4-4980-963c-4dfa5180b888
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999897961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2999897961
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1284728680
Short name T232
Test name
Test status
Simulation time 2386656538 ps
CPU time 9.5 seconds
Started Jun 05 03:50:22 PM PDT 24
Finished Jun 05 03:50:32 PM PDT 24
Peak memory 211944 kb
Host smart-b01f90ac-72b4-46cb-8a4f-83587d67cb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284728680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1284728680
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1991537078
Short name T198
Test name
Test status
Simulation time 3994359317 ps
CPU time 11.91 seconds
Started Jun 05 03:50:28 PM PDT 24
Finished Jun 05 03:50:41 PM PDT 24
Peak memory 210980 kb
Host smart-d927649f-0aa0-4b17-87ed-733172fcc3ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991537078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1991537078
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2552632278
Short name T321
Test name
Test status
Simulation time 754771210 ps
CPU time 10.47 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 03:50:38 PM PDT 24
Peak memory 213396 kb
Host smart-7fd0a03e-e569-42e4-beae-f462c04fb535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552632278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2552632278
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.444408031
Short name T183
Test name
Test status
Simulation time 2035899778 ps
CPU time 17.69 seconds
Started Jun 05 03:50:09 PM PDT 24
Finished Jun 05 03:50:28 PM PDT 24
Peak memory 214932 kb
Host smart-fb407839-1c40-4cb0-9e65-1e39645d5585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444408031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.444408031
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2216299884
Short name T297
Test name
Test status
Simulation time 3313861049 ps
CPU time 13.55 seconds
Started Jun 05 03:50:22 PM PDT 24
Finished Jun 05 03:50:36 PM PDT 24
Peak memory 211088 kb
Host smart-4f8dd94e-43ed-4f0d-b5c9-9c78f665f188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216299884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2216299884
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.549680209
Short name T302
Test name
Test status
Simulation time 14970272705 ps
CPU time 209.49 seconds
Started Jun 05 03:50:09 PM PDT 24
Finished Jun 05 03:53:39 PM PDT 24
Peak memory 212476 kb
Host smart-9bc54ae3-137e-407d-b0d0-8956dd885d2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549680209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.549680209
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3061697626
Short name T292
Test name
Test status
Simulation time 2919756632 ps
CPU time 10.53 seconds
Started Jun 05 03:50:11 PM PDT 24
Finished Jun 05 03:50:23 PM PDT 24
Peak memory 210984 kb
Host smart-90c241a7-1493-4b9d-ace6-e451990dd14a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061697626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3061697626
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4195710850
Short name T333
Test name
Test status
Simulation time 21718003230 ps
CPU time 27.84 seconds
Started Jun 05 03:50:25 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 218408 kb
Host smart-1687a62d-ae15-4d5c-af13-b07f5d07d02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195710850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4195710850
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.453776891
Short name T228
Test name
Test status
Simulation time 6313238971 ps
CPU time 27.88 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 03:50:55 PM PDT 24
Peak memory 213108 kb
Host smart-ab3498f0-401c-4830-ab48-a1c844626f56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453776891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.453776891
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.763647001
Short name T17
Test name
Test status
Simulation time 95676638588 ps
CPU time 869.84 seconds
Started Jun 05 03:50:23 PM PDT 24
Finished Jun 05 04:04:54 PM PDT 24
Peak memory 230932 kb
Host smart-e760204d-c965-4923-8b4e-ed12f9753ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763647001 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.763647001
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1505224439
Short name T249
Test name
Test status
Simulation time 3177077352 ps
CPU time 13.51 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:50:43 PM PDT 24
Peak memory 210788 kb
Host smart-7e869bbc-8e2c-4956-ba15-ee044eeba64a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505224439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1505224439
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.227202300
Short name T289
Test name
Test status
Simulation time 83783624647 ps
CPU time 203.38 seconds
Started Jun 05 03:50:08 PM PDT 24
Finished Jun 05 03:53:33 PM PDT 24
Peak memory 211364 kb
Host smart-5dfcabb4-3f5f-40c3-9f01-add345120cd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227202300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.227202300
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3629322830
Short name T347
Test name
Test status
Simulation time 10329627183 ps
CPU time 27.06 seconds
Started Jun 05 03:50:09 PM PDT 24
Finished Jun 05 03:50:37 PM PDT 24
Peak memory 212092 kb
Host smart-ba35a6fb-6de1-481d-9cc4-b050592e54d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629322830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3629322830
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2893224332
Short name T259
Test name
Test status
Simulation time 1726953951 ps
CPU time 11.24 seconds
Started Jun 05 03:50:10 PM PDT 24
Finished Jun 05 03:50:22 PM PDT 24
Peak memory 210904 kb
Host smart-e1b2a397-e32e-49c6-a86f-392d00c81bd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893224332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2893224332
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2157651413
Short name T303
Test name
Test status
Simulation time 60119714075 ps
CPU time 32.51 seconds
Started Jun 05 03:50:25 PM PDT 24
Finished Jun 05 03:50:58 PM PDT 24
Peak memory 219112 kb
Host smart-d570c22a-9127-4624-812a-3f1a13f04635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157651413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2157651413
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2651868880
Short name T164
Test name
Test status
Simulation time 5109047643 ps
CPU time 24.46 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 216556 kb
Host smart-85cca739-6023-44fb-bd0e-b099fbf9ca8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651868880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2651868880
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1326437045
Short name T335
Test name
Test status
Simulation time 6665335605 ps
CPU time 14.48 seconds
Started Jun 05 03:50:08 PM PDT 24
Finished Jun 05 03:50:23 PM PDT 24
Peak memory 211080 kb
Host smart-82f33d8c-ebc6-464f-8c94-1d3ef2542932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326437045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1326437045
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.649776272
Short name T181
Test name
Test status
Simulation time 11284369437 ps
CPU time 104.89 seconds
Started Jun 05 03:50:15 PM PDT 24
Finished Jun 05 03:52:01 PM PDT 24
Peak memory 232712 kb
Host smart-51fd9368-293c-48cd-93ed-18c83a160d52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649776272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.649776272
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.117283061
Short name T185
Test name
Test status
Simulation time 17934790685 ps
CPU time 26.58 seconds
Started Jun 05 03:50:09 PM PDT 24
Finished Jun 05 03:50:37 PM PDT 24
Peak memory 212012 kb
Host smart-3994f373-baf5-4e5b-883d-0f8377b42372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117283061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.117283061
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.855203099
Short name T122
Test name
Test status
Simulation time 1042757610 ps
CPU time 5.57 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 03:50:33 PM PDT 24
Peak memory 210692 kb
Host smart-131d87d6-4a95-4aef-8455-146f0d431d0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855203099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.855203099
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2963502982
Short name T231
Test name
Test status
Simulation time 4257945204 ps
CPU time 34.24 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 03:50:47 PM PDT 24
Peak memory 219152 kb
Host smart-06900db1-6337-4247-9cf1-2873153e0434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963502982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2963502982
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3403167500
Short name T186
Test name
Test status
Simulation time 5129897350 ps
CPU time 44.18 seconds
Started Jun 05 03:50:31 PM PDT 24
Finished Jun 05 03:51:16 PM PDT 24
Peak memory 213488 kb
Host smart-1cf5cdd0-f856-4a46-9528-473f96db9216
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403167500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3403167500
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3518276755
Short name T271
Test name
Test status
Simulation time 1211838878 ps
CPU time 11.28 seconds
Started Jun 05 03:50:11 PM PDT 24
Finished Jun 05 03:50:23 PM PDT 24
Peak memory 211024 kb
Host smart-a9164939-6178-4aab-8ecd-c28d54da329c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518276755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3518276755
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3910577319
Short name T309
Test name
Test status
Simulation time 9566507091 ps
CPU time 141.72 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 03:52:35 PM PDT 24
Peak memory 237556 kb
Host smart-2522a605-25b1-4584-8687-b3ab49d51297
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910577319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3910577319
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1974307079
Short name T226
Test name
Test status
Simulation time 2064277240 ps
CPU time 13.07 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 03:50:26 PM PDT 24
Peak memory 211604 kb
Host smart-2f648dc6-fbfe-4d05-9722-0980e3671b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974307079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1974307079
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2535022844
Short name T319
Test name
Test status
Simulation time 7323847341 ps
CPU time 15.8 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 210412 kb
Host smart-7f4a0547-370e-43d0-942b-7a9900c924aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2535022844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2535022844
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2962163273
Short name T128
Test name
Test status
Simulation time 183598934 ps
CPU time 10.51 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 03:50:24 PM PDT 24
Peak memory 212916 kb
Host smart-62ba469b-c5c7-4b43-8ac9-94b78ae47453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962163273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2962163273
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3302187744
Short name T365
Test name
Test status
Simulation time 3214932128 ps
CPU time 11.92 seconds
Started Jun 05 03:50:31 PM PDT 24
Finished Jun 05 03:50:44 PM PDT 24
Peak memory 210712 kb
Host smart-e734ba4b-dc1e-4615-8b8b-ccc4568bb5bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302187744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3302187744
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2944944724
Short name T205
Test name
Test status
Simulation time 40779923231 ps
CPU time 8578.67 seconds
Started Jun 05 03:50:18 PM PDT 24
Finished Jun 05 06:13:19 PM PDT 24
Peak memory 227440 kb
Host smart-c3b11e81-9c7e-4db3-9777-76c125ab3542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944944724 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2944944724
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3148498985
Short name T267
Test name
Test status
Simulation time 2313799769 ps
CPU time 16.72 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 03:50:29 PM PDT 24
Peak memory 211100 kb
Host smart-b0d76e1a-7cc9-4759-bb02-75238fe8634a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148498985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3148498985
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.487849877
Short name T162
Test name
Test status
Simulation time 10762361236 ps
CPU time 125.16 seconds
Started Jun 05 03:50:15 PM PDT 24
Finished Jun 05 03:52:21 PM PDT 24
Peak memory 236908 kb
Host smart-64f7262f-a7fb-47cf-9ee2-d461fb90b790
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487849877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.487849877
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2552130546
Short name T317
Test name
Test status
Simulation time 2769439768 ps
CPU time 24.85 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 03:50:38 PM PDT 24
Peak memory 211732 kb
Host smart-be3c468d-97d7-45c8-a52d-f299063d1265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552130546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2552130546
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.776215396
Short name T188
Test name
Test status
Simulation time 4922965502 ps
CPU time 12.63 seconds
Started Jun 05 03:50:14 PM PDT 24
Finished Jun 05 03:50:28 PM PDT 24
Peak memory 211068 kb
Host smart-8aebce20-5c8c-4bc8-b8b1-c49f940baa6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776215396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.776215396
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2622538736
Short name T361
Test name
Test status
Simulation time 191538634 ps
CPU time 10.52 seconds
Started Jun 05 03:50:26 PM PDT 24
Finished Jun 05 03:50:37 PM PDT 24
Peak memory 213416 kb
Host smart-86442dd4-e8fc-4a55-aa7b-622c0f5f9192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622538736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2622538736
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2060735706
Short name T278
Test name
Test status
Simulation time 13356914656 ps
CPU time 99.55 seconds
Started Jun 05 03:50:12 PM PDT 24
Finished Jun 05 03:51:53 PM PDT 24
Peak memory 219144 kb
Host smart-b86884c8-42fd-4d4b-91db-47790e3ded73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060735706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2060735706
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3179659096
Short name T189
Test name
Test status
Simulation time 1255585075 ps
CPU time 10.1 seconds
Started Jun 05 03:50:11 PM PDT 24
Finished Jun 05 03:50:22 PM PDT 24
Peak memory 211140 kb
Host smart-0d8b374f-985d-42ce-bc6e-880e7196886a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179659096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3179659096
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2149266123
Short name T57
Test name
Test status
Simulation time 72896387591 ps
CPU time 296.1 seconds
Started Jun 05 03:50:32 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 213332 kb
Host smart-f9aea533-5f88-40e7-88a9-8d9077f3de08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149266123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2149266123
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2563265861
Short name T22
Test name
Test status
Simulation time 312015401 ps
CPU time 9.23 seconds
Started Jun 05 03:50:34 PM PDT 24
Finished Jun 05 03:50:44 PM PDT 24
Peak memory 213420 kb
Host smart-c0aa64cc-ad6a-4df8-91f3-0f34a01d3c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563265861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2563265861
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3539115310
Short name T4
Test name
Test status
Simulation time 6954142315 ps
CPU time 14.59 seconds
Started Jun 05 03:50:21 PM PDT 24
Finished Jun 05 03:50:37 PM PDT 24
Peak memory 210964 kb
Host smart-e22c32ab-11f0-46b8-ab02-41060b91ba54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539115310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3539115310
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2562205708
Short name T337
Test name
Test status
Simulation time 3707051603 ps
CPU time 36.2 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:51:06 PM PDT 24
Peak memory 219136 kb
Host smart-3e7ad715-0cff-4328-a646-bcd53c599bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562205708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2562205708
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1907510966
Short name T160
Test name
Test status
Simulation time 24786775142 ps
CPU time 39.22 seconds
Started Jun 05 03:50:21 PM PDT 24
Finished Jun 05 03:51:00 PM PDT 24
Peak memory 219156 kb
Host smart-9e1e140f-27b2-4054-8f5a-046db83f4c0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907510966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1907510966
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3023864415
Short name T135
Test name
Test status
Simulation time 1383459595 ps
CPU time 7.07 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:50:37 PM PDT 24
Peak memory 211040 kb
Host smart-54e5cf6e-d3fa-4908-8859-31021d353e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023864415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3023864415
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.169180865
Short name T242
Test name
Test status
Simulation time 8810526933 ps
CPU time 35.67 seconds
Started Jun 05 03:50:19 PM PDT 24
Finished Jun 05 03:50:55 PM PDT 24
Peak memory 211796 kb
Host smart-f6e0a716-89bc-4eb6-904e-253cc8985a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169180865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.169180865
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2668925546
Short name T148
Test name
Test status
Simulation time 3583695463 ps
CPU time 16.62 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 03:50:44 PM PDT 24
Peak memory 210940 kb
Host smart-9e143238-c44e-49c6-9e48-039d8578c8eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668925546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2668925546
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.856869207
Short name T1
Test name
Test status
Simulation time 15303546489 ps
CPU time 38.54 seconds
Started Jun 05 03:50:14 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 219236 kb
Host smart-ae507ee2-869b-432b-a3be-fda56f025708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856869207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.856869207
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3257809939
Short name T298
Test name
Test status
Simulation time 10894449221 ps
CPU time 106.31 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:52:16 PM PDT 24
Peak memory 218880 kb
Host smart-41de42c9-e440-4afb-833e-93d87c4042d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257809939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3257809939
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1123900289
Short name T218
Test name
Test status
Simulation time 742537266 ps
CPU time 9.04 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:50:02 PM PDT 24
Peak memory 210840 kb
Host smart-058cc314-e611-470d-a252-b3591a9ae8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123900289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1123900289
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2246844219
Short name T227
Test name
Test status
Simulation time 14729957570 ps
CPU time 32.7 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:50:21 PM PDT 24
Peak memory 211880 kb
Host smart-223eac9a-becb-403d-ad8e-55cb085633e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246844219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2246844219
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1176139172
Short name T224
Test name
Test status
Simulation time 1890951522 ps
CPU time 17.3 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:12 PM PDT 24
Peak memory 210892 kb
Host smart-ba1e2612-0165-4862-b899-d91fca7e1a65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176139172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1176139172
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1088749768
Short name T11
Test name
Test status
Simulation time 14826293687 ps
CPU time 33.3 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:25 PM PDT 24
Peak memory 213944 kb
Host smart-70ebcd3a-4073-4315-a334-461c963eb84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088749768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1088749768
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3826735998
Short name T182
Test name
Test status
Simulation time 825230643 ps
CPU time 12.63 seconds
Started Jun 05 03:49:57 PM PDT 24
Finished Jun 05 03:50:11 PM PDT 24
Peak memory 212088 kb
Host smart-47228b79-84a7-4827-8878-0f7244bbd1d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826735998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3826735998
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1086607133
Short name T216
Test name
Test status
Simulation time 2725834733 ps
CPU time 8.59 seconds
Started Jun 05 03:50:17 PM PDT 24
Finished Jun 05 03:50:26 PM PDT 24
Peak memory 211172 kb
Host smart-c2aa15f7-7ebf-4e88-8de1-570c4f0dc4d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086607133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1086607133
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3310879706
Short name T316
Test name
Test status
Simulation time 33159655910 ps
CPU time 140.58 seconds
Started Jun 05 03:50:30 PM PDT 24
Finished Jun 05 03:52:52 PM PDT 24
Peak memory 228036 kb
Host smart-5fec2dd4-f4d8-4725-a8d0-59d690ace5b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310879706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3310879706
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4278109009
Short name T166
Test name
Test status
Simulation time 2852005836 ps
CPU time 15.2 seconds
Started Jun 05 03:50:19 PM PDT 24
Finished Jun 05 03:50:34 PM PDT 24
Peak memory 215660 kb
Host smart-79d55d5d-3a2b-471e-8a65-6a4a73603609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278109009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4278109009
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3111631692
Short name T340
Test name
Test status
Simulation time 200731695 ps
CPU time 5.36 seconds
Started Jun 05 03:50:15 PM PDT 24
Finished Jun 05 03:50:22 PM PDT 24
Peak memory 211008 kb
Host smart-76ba982e-7c09-4e49-aa01-40ccce1ca6d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111631692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3111631692
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3099569619
Short name T325
Test name
Test status
Simulation time 1192440798 ps
CPU time 11.95 seconds
Started Jun 05 03:50:19 PM PDT 24
Finished Jun 05 03:50:32 PM PDT 24
Peak memory 213384 kb
Host smart-493dd17b-94fc-40be-af0c-2813ea393820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099569619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3099569619
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3175744274
Short name T138
Test name
Test status
Simulation time 29679468737 ps
CPU time 71.73 seconds
Started Jun 05 03:50:30 PM PDT 24
Finished Jun 05 03:51:42 PM PDT 24
Peak memory 219140 kb
Host smart-51b1328e-0399-43a2-9157-f03419e40f4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175744274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3175744274
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2331959909
Short name T327
Test name
Test status
Simulation time 82248946553 ps
CPU time 3978.11 seconds
Started Jun 05 03:50:22 PM PDT 24
Finished Jun 05 04:56:42 PM PDT 24
Peak memory 235640 kb
Host smart-3c9b0548-28de-4f77-81b8-37c13af38749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331959909 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2331959909
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3552176175
Short name T207
Test name
Test status
Simulation time 195684881 ps
CPU time 4.41 seconds
Started Jun 05 03:50:32 PM PDT 24
Finished Jun 05 03:50:37 PM PDT 24
Peak memory 211060 kb
Host smart-5ee975f7-f6c7-45a1-8826-9c55d637b1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552176175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3552176175
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3555702409
Short name T246
Test name
Test status
Simulation time 17687820749 ps
CPU time 92.66 seconds
Started Jun 05 03:50:26 PM PDT 24
Finished Jun 05 03:51:59 PM PDT 24
Peak memory 236976 kb
Host smart-4f323b43-5ad5-4d5c-ab71-5ad81b89eab1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555702409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3555702409
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4231955170
Short name T9
Test name
Test status
Simulation time 6168214983 ps
CPU time 14.67 seconds
Started Jun 05 03:50:31 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 210964 kb
Host smart-89be25d4-694c-49f5-a572-268768e2c579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231955170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4231955170
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3498142445
Short name T233
Test name
Test status
Simulation time 4924467767 ps
CPU time 23.35 seconds
Started Jun 05 03:50:19 PM PDT 24
Finished Jun 05 03:50:43 PM PDT 24
Peak memory 213320 kb
Host smart-32b46057-58c0-4799-bd5d-5782a3a3e180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498142445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3498142445
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2706289911
Short name T158
Test name
Test status
Simulation time 14277543157 ps
CPU time 46.78 seconds
Started Jun 05 03:50:17 PM PDT 24
Finished Jun 05 03:51:04 PM PDT 24
Peak memory 219128 kb
Host smart-ea8f3c6e-f789-4ea1-900b-f1973de9bb92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706289911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2706289911
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.387930656
Short name T235
Test name
Test status
Simulation time 14444580397 ps
CPU time 13.13 seconds
Started Jun 05 03:50:19 PM PDT 24
Finished Jun 05 03:50:33 PM PDT 24
Peak memory 211100 kb
Host smart-ee002935-3067-4f72-9c3e-a8f83660c0d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387930656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.387930656
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4003262224
Short name T124
Test name
Test status
Simulation time 6145893422 ps
CPU time 144.02 seconds
Started Jun 05 03:50:17 PM PDT 24
Finished Jun 05 03:52:42 PM PDT 24
Peak memory 236536 kb
Host smart-80d98d81-e1c9-41f6-8ee7-9b47e1418b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003262224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.4003262224
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.398578277
Short name T134
Test name
Test status
Simulation time 22536453053 ps
CPU time 22.12 seconds
Started Jun 05 03:50:20 PM PDT 24
Finished Jun 05 03:50:43 PM PDT 24
Peak memory 212212 kb
Host smart-3d9645aa-612a-46b4-8a28-f3305bb19deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398578277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.398578277
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3436552904
Short name T204
Test name
Test status
Simulation time 692531438 ps
CPU time 7.78 seconds
Started Jun 05 03:50:23 PM PDT 24
Finished Jun 05 03:50:31 PM PDT 24
Peak memory 210856 kb
Host smart-9bbb9db6-e301-4f07-ac07-041eaee7b169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436552904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3436552904
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3580310176
Short name T366
Test name
Test status
Simulation time 2875487542 ps
CPU time 19.1 seconds
Started Jun 05 03:50:23 PM PDT 24
Finished Jun 05 03:50:43 PM PDT 24
Peak memory 213068 kb
Host smart-53e4beca-ffc4-4398-a2a9-fd9dbef752c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580310176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3580310176
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2187927190
Short name T244
Test name
Test status
Simulation time 13367635949 ps
CPU time 108.81 seconds
Started Jun 05 03:50:20 PM PDT 24
Finished Jun 05 03:52:10 PM PDT 24
Peak memory 216948 kb
Host smart-0534dc7e-a697-491d-9fa8-b978abf7e4da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187927190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2187927190
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.730494688
Short name T104
Test name
Test status
Simulation time 105677798614 ps
CPU time 2155.81 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 04:26:23 PM PDT 24
Peak memory 235660 kb
Host smart-890690b6-d41b-4512-b6c7-6bbf2a3b9c3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730494688 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.730494688
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2536599386
Short name T276
Test name
Test status
Simulation time 3123447227 ps
CPU time 12.51 seconds
Started Jun 05 03:50:22 PM PDT 24
Finished Jun 05 03:50:36 PM PDT 24
Peak memory 210984 kb
Host smart-ffcec443-dfe2-4e4f-918f-00033c3a08da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536599386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2536599386
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3963689992
Short name T44
Test name
Test status
Simulation time 299846947048 ps
CPU time 328.4 seconds
Started Jun 05 03:50:23 PM PDT 24
Finished Jun 05 03:55:52 PM PDT 24
Peak memory 212220 kb
Host smart-a193968f-9f89-4c3a-8dfb-f676d8856edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963689992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3963689992
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3470931702
Short name T155
Test name
Test status
Simulation time 2682644350 ps
CPU time 18.35 seconds
Started Jun 05 03:50:15 PM PDT 24
Finished Jun 05 03:50:34 PM PDT 24
Peak memory 211900 kb
Host smart-6650e59a-2bfc-48c0-b60f-6bffb15e9309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470931702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3470931702
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.670809937
Short name T54
Test name
Test status
Simulation time 404597347 ps
CPU time 5.52 seconds
Started Jun 05 03:50:15 PM PDT 24
Finished Jun 05 03:50:22 PM PDT 24
Peak memory 210948 kb
Host smart-9d5d5ea5-5f22-41ed-bd73-6e6f6de30a02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670809937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.670809937
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.330540253
Short name T174
Test name
Test status
Simulation time 372864098 ps
CPU time 9.89 seconds
Started Jun 05 03:50:20 PM PDT 24
Finished Jun 05 03:50:31 PM PDT 24
Peak memory 219208 kb
Host smart-1fef47f1-2478-4f65-9b8f-abb6c8316b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330540253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.330540253
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3228376170
Short name T318
Test name
Test status
Simulation time 22560076475 ps
CPU time 58.03 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:51:27 PM PDT 24
Peak memory 219116 kb
Host smart-a65cd605-2c3b-4b73-b79e-50bb02ef0db2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228376170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3228376170
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.3059412732
Short name T50
Test name
Test status
Simulation time 55773388607 ps
CPU time 2190.37 seconds
Started Jun 05 03:50:33 PM PDT 24
Finished Jun 05 04:27:04 PM PDT 24
Peak memory 235628 kb
Host smart-1d414534-ec0f-4914-8083-6a992f653166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059412732 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.3059412732
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1206675822
Short name T314
Test name
Test status
Simulation time 89850473 ps
CPU time 4.31 seconds
Started Jun 05 03:50:21 PM PDT 24
Finished Jun 05 03:50:26 PM PDT 24
Peak memory 211180 kb
Host smart-dd139ce5-92f2-4a5e-96c6-14c618e9d67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206675822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1206675822
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4250358727
Short name T357
Test name
Test status
Simulation time 3166558744 ps
CPU time 91.93 seconds
Started Jun 05 03:50:21 PM PDT 24
Finished Jun 05 03:51:53 PM PDT 24
Peak memory 229516 kb
Host smart-e7de4e97-e325-46c7-bd70-a5f5a7cec688
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250358727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4250358727
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1778638001
Short name T55
Test name
Test status
Simulation time 10515063489 ps
CPU time 21.94 seconds
Started Jun 05 03:50:34 PM PDT 24
Finished Jun 05 03:50:56 PM PDT 24
Peak memory 212348 kb
Host smart-1a1e3845-54ae-4171-853c-9d7d933b53e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778638001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1778638001
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2593276126
Short name T200
Test name
Test status
Simulation time 5065214956 ps
CPU time 13.65 seconds
Started Jun 05 03:50:38 PM PDT 24
Finished Jun 05 03:50:53 PM PDT 24
Peak memory 211304 kb
Host smart-1a303324-aa31-4c52-aa64-0a7b84a95057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593276126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2593276126
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2802204942
Short name T215
Test name
Test status
Simulation time 189623545 ps
CPU time 10.52 seconds
Started Jun 05 03:50:23 PM PDT 24
Finished Jun 05 03:50:34 PM PDT 24
Peak memory 219032 kb
Host smart-c0ae71a2-b6ee-4549-b948-6a071ef5b866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802204942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2802204942
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.526133379
Short name T143
Test name
Test status
Simulation time 98890862 ps
CPU time 7 seconds
Started Jun 05 03:50:46 PM PDT 24
Finished Jun 05 03:50:53 PM PDT 24
Peak memory 210836 kb
Host smart-bc423bb3-ad0d-4439-be6f-17585d6d23cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526133379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.526133379
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1912392690
Short name T20
Test name
Test status
Simulation time 545386075568 ps
CPU time 2789.6 seconds
Started Jun 05 03:50:20 PM PDT 24
Finished Jun 05 04:36:50 PM PDT 24
Peak memory 239216 kb
Host smart-e42e2422-a5c7-41a6-9cd4-ef11f227c6f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912392690 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1912392690
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2689821563
Short name T195
Test name
Test status
Simulation time 4752933520 ps
CPU time 11.33 seconds
Started Jun 05 03:50:26 PM PDT 24
Finished Jun 05 03:50:38 PM PDT 24
Peak memory 211172 kb
Host smart-fee2b7ee-e4a4-45f1-9d92-cf057896091f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689821563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2689821563
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2001790842
Short name T217
Test name
Test status
Simulation time 24270882109 ps
CPU time 149.85 seconds
Started Jun 05 03:50:40 PM PDT 24
Finished Jun 05 03:53:10 PM PDT 24
Peak memory 237856 kb
Host smart-00bf71b6-0166-42f4-b381-a9798ea9e43b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001790842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2001790842
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2551589884
Short name T39
Test name
Test status
Simulation time 5806152815 ps
CPU time 26.83 seconds
Started Jun 05 03:50:32 PM PDT 24
Finished Jun 05 03:51:00 PM PDT 24
Peak memory 212168 kb
Host smart-e5966c4c-f599-486a-9f8a-06d8e4b5ea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551589884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2551589884
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1411106516
Short name T196
Test name
Test status
Simulation time 1887932966 ps
CPU time 16.52 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 210888 kb
Host smart-94ce78db-26e2-42aa-8aa9-f915e3c51a92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411106516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1411106516
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.431111714
Short name T252
Test name
Test status
Simulation time 7211317662 ps
CPU time 21.27 seconds
Started Jun 05 03:50:22 PM PDT 24
Finished Jun 05 03:50:44 PM PDT 24
Peak memory 219104 kb
Host smart-87f51ad7-2db5-4a3c-bd3e-02f4b2ea5237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431111714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.431111714
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.555989340
Short name T61
Test name
Test status
Simulation time 1775803462 ps
CPU time 26.83 seconds
Started Jun 05 03:50:41 PM PDT 24
Finished Jun 05 03:51:09 PM PDT 24
Peak memory 214140 kb
Host smart-5ecc9510-911a-4b43-aa74-5a53d94a69c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555989340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.555989340
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1994393206
Short name T359
Test name
Test status
Simulation time 2724000493 ps
CPU time 8.99 seconds
Started Jun 05 03:50:36 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 211020 kb
Host smart-a352be6a-57bb-4023-9cb4-805b56e77b13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994393206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1994393206
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1764119556
Short name T268
Test name
Test status
Simulation time 147687882420 ps
CPU time 381.76 seconds
Started Jun 05 03:50:41 PM PDT 24
Finished Jun 05 03:57:04 PM PDT 24
Peak memory 234260 kb
Host smart-f4a24134-9093-4c70-b15c-5169ecc83d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764119556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1764119556
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1973605831
Short name T286
Test name
Test status
Simulation time 691363088 ps
CPU time 9.6 seconds
Started Jun 05 03:50:36 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 211676 kb
Host smart-519879ce-50ae-4471-818a-cdb0bda44eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973605831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1973605831
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1389717478
Short name T264
Test name
Test status
Simulation time 6261378233 ps
CPU time 15.52 seconds
Started Jun 05 03:50:32 PM PDT 24
Finished Jun 05 03:50:48 PM PDT 24
Peak memory 210964 kb
Host smart-0b21c6d7-8e2a-4054-a4c4-47ab64645481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389717478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1389717478
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3793332184
Short name T8
Test name
Test status
Simulation time 4945372319 ps
CPU time 28.42 seconds
Started Jun 05 03:50:32 PM PDT 24
Finished Jun 05 03:51:01 PM PDT 24
Peak memory 219256 kb
Host smart-318756b2-35ee-4eea-9130-bf8291eb9865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793332184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3793332184
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.154493758
Short name T322
Test name
Test status
Simulation time 1559884156 ps
CPU time 21.22 seconds
Started Jun 05 03:50:28 PM PDT 24
Finished Jun 05 03:50:50 PM PDT 24
Peak memory 214380 kb
Host smart-2064a9f1-3944-4d54-95db-7ec3d3d7b6d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154493758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.154493758
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2417021722
Short name T211
Test name
Test status
Simulation time 320426113 ps
CPU time 4.18 seconds
Started Jun 05 03:50:46 PM PDT 24
Finished Jun 05 03:50:51 PM PDT 24
Peak memory 210976 kb
Host smart-885404ec-75e1-4656-b59b-89dac415559f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417021722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2417021722
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2138959954
Short name T147
Test name
Test status
Simulation time 18187238623 ps
CPU time 182.07 seconds
Started Jun 05 03:50:36 PM PDT 24
Finished Jun 05 03:53:39 PM PDT 24
Peak memory 237708 kb
Host smart-b58f814d-0a61-4285-a9ff-f1d471bb5b3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138959954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2138959954
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1531065584
Short name T193
Test name
Test status
Simulation time 23679971376 ps
CPU time 21.36 seconds
Started Jun 05 03:50:35 PM PDT 24
Finished Jun 05 03:50:56 PM PDT 24
Peak memory 211780 kb
Host smart-d1f0c51e-9abc-4426-8212-d1404f890747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531065584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1531065584
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2347186625
Short name T214
Test name
Test status
Simulation time 762409830 ps
CPU time 5.36 seconds
Started Jun 05 03:50:36 PM PDT 24
Finished Jun 05 03:50:43 PM PDT 24
Peak memory 210872 kb
Host smart-adfdd65a-5fff-4f42-a91a-743a1be2f49a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347186625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2347186625
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1612597137
Short name T290
Test name
Test status
Simulation time 8269085930 ps
CPU time 30.71 seconds
Started Jun 05 03:50:35 PM PDT 24
Finished Jun 05 03:51:06 PM PDT 24
Peak memory 219152 kb
Host smart-416ad582-9d7a-4f97-a95f-07ed7b884eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612597137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1612597137
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1057331199
Short name T77
Test name
Test status
Simulation time 21129945786 ps
CPU time 71.48 seconds
Started Jun 05 03:50:36 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 216876 kb
Host smart-e5fc2d6b-71cf-4481-81f9-bc8e4e02a83c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057331199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1057331199
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.603167585
Short name T274
Test name
Test status
Simulation time 8603646406 ps
CPU time 14.57 seconds
Started Jun 05 03:50:28 PM PDT 24
Finished Jun 05 03:50:43 PM PDT 24
Peak memory 211088 kb
Host smart-9390dbed-833a-4f60-9920-a50aafccc87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603167585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.603167585
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.494661790
Short name T26
Test name
Test status
Simulation time 149766585597 ps
CPU time 181.26 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:53:31 PM PDT 24
Peak memory 224716 kb
Host smart-63c7be2a-1af9-411b-9e43-03ee88a5028a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494661790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.494661790
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.470618341
Short name T29
Test name
Test status
Simulation time 661243884 ps
CPU time 12.2 seconds
Started Jun 05 03:50:36 PM PDT 24
Finished Jun 05 03:50:49 PM PDT 24
Peak memory 211756 kb
Host smart-7a1f005f-cf90-491e-aa74-16b2f1be6e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470618341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.470618341
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2642128575
Short name T187
Test name
Test status
Simulation time 1095381314 ps
CPU time 8.84 seconds
Started Jun 05 03:50:28 PM PDT 24
Finished Jun 05 03:50:38 PM PDT 24
Peak memory 210888 kb
Host smart-10237665-87a1-47d8-9430-f12b6ab1f313
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642128575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2642128575
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2127044972
Short name T175
Test name
Test status
Simulation time 4961776193 ps
CPU time 18.07 seconds
Started Jun 05 03:50:42 PM PDT 24
Finished Jun 05 03:51:01 PM PDT 24
Peak memory 213592 kb
Host smart-ccc10896-2f4b-4525-9f28-0b38d6b62726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127044972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2127044972
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3736615897
Short name T279
Test name
Test status
Simulation time 6325028667 ps
CPU time 32.52 seconds
Started Jun 05 03:50:33 PM PDT 24
Finished Jun 05 03:51:06 PM PDT 24
Peak memory 219140 kb
Host smart-a36426da-2c67-4816-b54c-af356535bdd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736615897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3736615897
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.207311026
Short name T63
Test name
Test status
Simulation time 1572199141 ps
CPU time 9.3 seconds
Started Jun 05 03:50:26 PM PDT 24
Finished Jun 05 03:50:36 PM PDT 24
Peak memory 211012 kb
Host smart-c0f7c092-7960-4d19-84ce-37ac17fc5d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207311026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.207311026
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2668029233
Short name T287
Test name
Test status
Simulation time 60798260414 ps
CPU time 227.87 seconds
Started Jun 05 03:50:38 PM PDT 24
Finished Jun 05 03:54:27 PM PDT 24
Peak memory 218388 kb
Host smart-c0400a79-8f4f-44c7-babf-10eafb0131ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668029233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2668029233
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1474441917
Short name T118
Test name
Test status
Simulation time 3846114697 ps
CPU time 31.71 seconds
Started Jun 05 03:50:26 PM PDT 24
Finished Jun 05 03:50:58 PM PDT 24
Peak memory 211820 kb
Host smart-0e040fe0-cbb2-4229-a721-d53f4caa10fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474441917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1474441917
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.524949500
Short name T190
Test name
Test status
Simulation time 7418905580 ps
CPU time 16.65 seconds
Started Jun 05 03:50:25 PM PDT 24
Finished Jun 05 03:50:42 PM PDT 24
Peak memory 210988 kb
Host smart-7390f0ca-1748-4ae7-9441-3f48b0e62a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524949500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.524949500
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4006618183
Short name T243
Test name
Test status
Simulation time 8921824360 ps
CPU time 26.76 seconds
Started Jun 05 03:50:38 PM PDT 24
Finished Jun 05 03:51:05 PM PDT 24
Peak memory 219152 kb
Host smart-69e63c15-bd84-4685-8b6f-167b457a11e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006618183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4006618183
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4060519139
Short name T240
Test name
Test status
Simulation time 18545104529 ps
CPU time 18.39 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 210920 kb
Host smart-a211b68d-e757-4d55-84b3-276fa15076b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060519139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4060519139
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1295611531
Short name T253
Test name
Test status
Simulation time 348196461 ps
CPU time 4.37 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:49:58 PM PDT 24
Peak memory 210848 kb
Host smart-423bbf4c-dbec-4de0-a588-e827b99fb776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295611531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1295611531
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1631224506
Short name T13
Test name
Test status
Simulation time 112318004604 ps
CPU time 342.37 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:55:33 PM PDT 24
Peak memory 228308 kb
Host smart-7b6bfd6d-e915-4779-895a-fe8ae4351ead
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631224506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1631224506
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2761774091
Short name T206
Test name
Test status
Simulation time 192988299 ps
CPU time 9.62 seconds
Started Jun 05 03:49:57 PM PDT 24
Finished Jun 05 03:50:07 PM PDT 24
Peak memory 211552 kb
Host smart-f9de33cb-61ba-46f2-bb4d-b62cf91907fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761774091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2761774091
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3481566884
Short name T191
Test name
Test status
Simulation time 4597701116 ps
CPU time 12.26 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:50:06 PM PDT 24
Peak memory 210968 kb
Host smart-1ba2c4c4-473b-4458-aa76-0f9ef8b5c136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481566884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3481566884
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.789476835
Short name T35
Test name
Test status
Simulation time 318273803 ps
CPU time 54.22 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:50:45 PM PDT 24
Peak memory 230008 kb
Host smart-a7740292-7515-4f56-8f9e-b67d43b28215
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789476835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.789476835
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.908761025
Short name T145
Test name
Test status
Simulation time 9967014757 ps
CPU time 33.11 seconds
Started Jun 05 03:49:53 PM PDT 24
Finished Jun 05 03:50:28 PM PDT 24
Peak memory 219144 kb
Host smart-8b59a414-b025-47b7-b514-0c44810c1f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908761025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.908761025
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3313548820
Short name T75
Test name
Test status
Simulation time 5377058374 ps
CPU time 21.65 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:50:12 PM PDT 24
Peak memory 216020 kb
Host smart-015403f6-a198-4497-bad7-703a4c5e9d57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313548820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3313548820
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2847484688
Short name T293
Test name
Test status
Simulation time 86693769 ps
CPU time 4 seconds
Started Jun 05 03:50:41 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 211128 kb
Host smart-f140fb30-1250-43f3-80b5-3f0be8b530f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847484688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2847484688
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.661323023
Short name T46
Test name
Test status
Simulation time 40128949105 ps
CPU time 229.35 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 234040 kb
Host smart-4d857981-aef7-499b-ab91-af12966513ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661323023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.661323023
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2648381215
Short name T273
Test name
Test status
Simulation time 3429775370 ps
CPU time 29.93 seconds
Started Jun 05 03:50:36 PM PDT 24
Finished Jun 05 03:51:07 PM PDT 24
Peak memory 211536 kb
Host smart-0020c81c-b35b-4a95-ab74-c25073e60133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648381215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2648381215
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2958390465
Short name T221
Test name
Test status
Simulation time 1659439744 ps
CPU time 14.98 seconds
Started Jun 05 03:50:30 PM PDT 24
Finished Jun 05 03:50:45 PM PDT 24
Peak memory 210892 kb
Host smart-326ed794-2698-4715-9035-b5fa9bd700c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958390465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2958390465
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.4032835232
Short name T141
Test name
Test status
Simulation time 10081835587 ps
CPU time 26.67 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 03:50:55 PM PDT 24
Peak memory 219232 kb
Host smart-4c6528aa-6499-46af-99af-a81875f88678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032835232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.4032835232
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.791249227
Short name T130
Test name
Test status
Simulation time 5951553173 ps
CPU time 56.09 seconds
Started Jun 05 03:50:38 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 219176 kb
Host smart-e467f9a7-c395-4cd9-9ec3-0a9a21a9891c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791249227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.791249227
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3000860221
Short name T21
Test name
Test status
Simulation time 29045524223 ps
CPU time 2266.46 seconds
Started Jun 05 03:50:28 PM PDT 24
Finished Jun 05 04:28:15 PM PDT 24
Peak memory 234316 kb
Host smart-9072a767-4be5-480e-ba5d-fc8324bf2dc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000860221 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3000860221
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2943053111
Short name T265
Test name
Test status
Simulation time 3404522742 ps
CPU time 10.28 seconds
Started Jun 05 03:50:42 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 211084 kb
Host smart-dd5db9c4-86d0-46fa-aad6-084c00855f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943053111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2943053111
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4189863761
Short name T203
Test name
Test status
Simulation time 37635347318 ps
CPU time 124.97 seconds
Started Jun 05 03:50:40 PM PDT 24
Finished Jun 05 03:52:46 PM PDT 24
Peak memory 230424 kb
Host smart-af6cedf5-859f-4c54-8fa0-763690219395
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189863761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4189863761
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4180431924
Short name T310
Test name
Test status
Simulation time 3538965412 ps
CPU time 30.03 seconds
Started Jun 05 03:50:33 PM PDT 24
Finished Jun 05 03:51:04 PM PDT 24
Peak memory 211748 kb
Host smart-48eeff59-02ad-4066-9f79-f89e025c3980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180431924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4180431924
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3168093821
Short name T53
Test name
Test status
Simulation time 100324486 ps
CPU time 6.1 seconds
Started Jun 05 03:50:25 PM PDT 24
Finished Jun 05 03:50:32 PM PDT 24
Peak memory 210852 kb
Host smart-54b1e8c9-2dd7-445e-965d-0d6e15f42096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168093821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3168093821
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1548683171
Short name T157
Test name
Test status
Simulation time 24787243132 ps
CPU time 35.04 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:51:15 PM PDT 24
Peak memory 219152 kb
Host smart-d554030d-d2d4-405b-ba10-953eedae5091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548683171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1548683171
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3836799266
Short name T294
Test name
Test status
Simulation time 545377192 ps
CPU time 16.62 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 03:50:45 PM PDT 24
Peak memory 213360 kb
Host smart-be773b13-0070-47f4-bc29-b581e7035f08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836799266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3836799266
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2944055961
Short name T283
Test name
Test status
Simulation time 168306639 ps
CPU time 4.37 seconds
Started Jun 05 03:50:27 PM PDT 24
Finished Jun 05 03:50:32 PM PDT 24
Peak memory 211028 kb
Host smart-e61b4fca-24f5-469f-985f-eb66965ec9de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944055961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2944055961
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3289038177
Short name T369
Test name
Test status
Simulation time 1594495503 ps
CPU time 110.72 seconds
Started Jun 05 03:50:33 PM PDT 24
Finished Jun 05 03:52:25 PM PDT 24
Peak memory 236416 kb
Host smart-2911d8ea-56c5-4daf-ae99-3ab5c63041bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289038177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3289038177
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1355471881
Short name T127
Test name
Test status
Simulation time 5716878816 ps
CPU time 31.05 seconds
Started Jun 05 03:50:36 PM PDT 24
Finished Jun 05 03:51:08 PM PDT 24
Peak memory 211832 kb
Host smart-2d463375-24c0-4c44-83fe-593128f42b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355471881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1355471881
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4069030123
Short name T256
Test name
Test status
Simulation time 1574913039 ps
CPU time 13.04 seconds
Started Jun 05 03:50:33 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 210892 kb
Host smart-f7dd1cf1-bcd6-47e0-a344-f1b7d0da2755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069030123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4069030123
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2959522254
Short name T209
Test name
Test status
Simulation time 4011640984 ps
CPU time 33.83 seconds
Started Jun 05 03:50:29 PM PDT 24
Finished Jun 05 03:51:03 PM PDT 24
Peak memory 219444 kb
Host smart-5c467863-1c81-4802-83fa-7f386dadd5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959522254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2959522254
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1455905323
Short name T260
Test name
Test status
Simulation time 14310939824 ps
CPU time 56.37 seconds
Started Jun 05 03:50:34 PM PDT 24
Finished Jun 05 03:51:31 PM PDT 24
Peak memory 219144 kb
Host smart-97643c22-9fcf-4e4a-bd35-9c5563ee6da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455905323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1455905323
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1547682471
Short name T332
Test name
Test status
Simulation time 251285822 ps
CPU time 6.28 seconds
Started Jun 05 03:50:36 PM PDT 24
Finished Jun 05 03:50:43 PM PDT 24
Peak memory 211144 kb
Host smart-ca11efd7-c3d1-4afa-9eba-850aee9b239b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547682471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1547682471
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.60579842
Short name T159
Test name
Test status
Simulation time 18896445113 ps
CPU time 81.56 seconds
Started Jun 05 03:50:47 PM PDT 24
Finished Jun 05 03:52:09 PM PDT 24
Peak memory 212312 kb
Host smart-1898001b-5711-4641-b40e-ed44c36c5126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60579842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_co
rrupt_sig_fatal_chk.60579842
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.120848767
Short name T27
Test name
Test status
Simulation time 17372890567 ps
CPU time 34.07 seconds
Started Jun 05 03:50:37 PM PDT 24
Finished Jun 05 03:51:12 PM PDT 24
Peak memory 212200 kb
Host smart-ae1508f1-d9b2-412a-ad13-0eefca574124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120848767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.120848767
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2466606755
Short name T229
Test name
Test status
Simulation time 10114449993 ps
CPU time 13.41 seconds
Started Jun 05 03:50:40 PM PDT 24
Finished Jun 05 03:50:55 PM PDT 24
Peak memory 210924 kb
Host smart-c0b48b83-7b2a-433d-a741-b8cadc717b6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466606755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2466606755
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.143560686
Short name T367
Test name
Test status
Simulation time 667936637 ps
CPU time 10.37 seconds
Started Jun 05 03:50:41 PM PDT 24
Finished Jun 05 03:50:52 PM PDT 24
Peak memory 213368 kb
Host smart-cbcf72e7-fff2-4a0a-8b29-fc8b6016a78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143560686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.143560686
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2904516017
Short name T238
Test name
Test status
Simulation time 832476317 ps
CPU time 16.99 seconds
Started Jun 05 03:50:46 PM PDT 24
Finished Jun 05 03:51:04 PM PDT 24
Peak memory 215936 kb
Host smart-9c839340-4943-44c6-b596-4093ddcc7dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904516017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2904516017
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2676616653
Short name T307
Test name
Test status
Simulation time 377946669 ps
CPU time 4.45 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:50:44 PM PDT 24
Peak memory 210988 kb
Host smart-48e19371-b5d9-4057-a3f2-ba3c7459f1e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676616653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2676616653
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1218147045
Short name T281
Test name
Test status
Simulation time 55059597043 ps
CPU time 147.08 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:53:07 PM PDT 24
Peak memory 218332 kb
Host smart-a62ffa0d-4157-4b9d-a18b-f70cbdfedb35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218147045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1218147045
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2452210843
Short name T126
Test name
Test status
Simulation time 5415846769 ps
CPU time 25.8 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:51:06 PM PDT 24
Peak memory 211524 kb
Host smart-f2c2e88e-9aeb-4a1d-9d1d-4b14d592fd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452210843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2452210843
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.20304163
Short name T184
Test name
Test status
Simulation time 1717737457 ps
CPU time 9.14 seconds
Started Jun 05 03:50:48 PM PDT 24
Finished Jun 05 03:50:57 PM PDT 24
Peak memory 210924 kb
Host smart-65200dc3-4ef5-452c-b345-9d97a9d0ad45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20304163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.20304163
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.142108943
Short name T34
Test name
Test status
Simulation time 32851423966 ps
CPU time 45.11 seconds
Started Jun 05 03:50:42 PM PDT 24
Finished Jun 05 03:51:28 PM PDT 24
Peak memory 213836 kb
Host smart-6f4f5ed9-5874-4b23-862f-ebef3c099493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142108943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.142108943
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3659057391
Short name T313
Test name
Test status
Simulation time 7309925303 ps
CPU time 18.8 seconds
Started Jun 05 03:50:46 PM PDT 24
Finished Jun 05 03:51:06 PM PDT 24
Peak memory 210832 kb
Host smart-5d711b06-1644-4b15-94b4-68c614e8b15d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659057391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3659057391
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3284465687
Short name T194
Test name
Test status
Simulation time 578130975 ps
CPU time 8.22 seconds
Started Jun 05 03:50:38 PM PDT 24
Finished Jun 05 03:50:47 PM PDT 24
Peak memory 211148 kb
Host smart-f314877a-d203-404f-b2b0-5acfb5e48bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284465687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3284465687
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.64732582
Short name T326
Test name
Test status
Simulation time 2853552151 ps
CPU time 87.21 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:52:07 PM PDT 24
Peak memory 228532 kb
Host smart-da67ad72-601e-46dc-9f0e-72faa981091f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64732582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_co
rrupt_sig_fatal_chk.64732582
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2900727796
Short name T223
Test name
Test status
Simulation time 13951730961 ps
CPU time 30.94 seconds
Started Jun 05 03:50:43 PM PDT 24
Finished Jun 05 03:51:15 PM PDT 24
Peak memory 212176 kb
Host smart-e6afc526-9224-453f-92a8-4f2442bb1f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900727796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2900727796
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.975152035
Short name T129
Test name
Test status
Simulation time 1170403483 ps
CPU time 12.39 seconds
Started Jun 05 03:50:45 PM PDT 24
Finished Jun 05 03:50:59 PM PDT 24
Peak memory 211244 kb
Host smart-b572b54c-07c9-40a6-acba-7beb8bad45ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975152035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.975152035
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1711168447
Short name T152
Test name
Test status
Simulation time 30756518278 ps
CPU time 32.79 seconds
Started Jun 05 03:50:38 PM PDT 24
Finished Jun 05 03:51:12 PM PDT 24
Peak memory 214044 kb
Host smart-aa5f66ab-dace-4ba5-bd08-19ee2c3ca050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711168447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1711168447
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.929531929
Short name T263
Test name
Test status
Simulation time 10452983810 ps
CPU time 51.2 seconds
Started Jun 05 03:50:37 PM PDT 24
Finished Jun 05 03:51:29 PM PDT 24
Peak memory 216800 kb
Host smart-38916ac1-625d-4846-8f7c-1c5b91ce9fe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929531929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.929531929
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1045286359
Short name T336
Test name
Test status
Simulation time 3909904827 ps
CPU time 9.62 seconds
Started Jun 05 03:50:40 PM PDT 24
Finished Jun 05 03:50:50 PM PDT 24
Peak memory 211120 kb
Host smart-814c48e2-b1cd-47ea-a0c7-63da1158d475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045286359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1045286359
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1853411624
Short name T339
Test name
Test status
Simulation time 15966547131 ps
CPU time 205.88 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:54:05 PM PDT 24
Peak memory 233512 kb
Host smart-e93406c9-bfb9-4b17-9702-fd0c1ec025c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853411624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1853411624
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2444465090
Short name T28
Test name
Test status
Simulation time 13963267864 ps
CPU time 32.05 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:51:12 PM PDT 24
Peak memory 212076 kb
Host smart-ad112d07-b347-4482-bd48-66bf8b0f3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444465090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2444465090
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3888399234
Short name T165
Test name
Test status
Simulation time 99633547 ps
CPU time 5.99 seconds
Started Jun 05 03:50:41 PM PDT 24
Finished Jun 05 03:50:48 PM PDT 24
Peak memory 210904 kb
Host smart-cc881b4a-4f0d-46dc-8df5-3de102d19a59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888399234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3888399234
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.920423871
Short name T168
Test name
Test status
Simulation time 13993500506 ps
CPU time 29.86 seconds
Started Jun 05 03:50:41 PM PDT 24
Finished Jun 05 03:51:12 PM PDT 24
Peak memory 214084 kb
Host smart-6366b4e4-483b-4b01-be97-d213035177c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920423871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.920423871
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2840487970
Short name T320
Test name
Test status
Simulation time 9541495629 ps
CPU time 78.23 seconds
Started Jun 05 03:50:38 PM PDT 24
Finished Jun 05 03:51:57 PM PDT 24
Peak memory 219164 kb
Host smart-fecd8a60-6072-4f98-abf0-440bb0a7da21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840487970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2840487970
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.799660857
Short name T295
Test name
Test status
Simulation time 200617050832 ps
CPU time 842.35 seconds
Started Jun 05 03:50:45 PM PDT 24
Finished Jun 05 04:04:49 PM PDT 24
Peak memory 229480 kb
Host smart-628ee4dd-d6df-4a91-bb5c-f22f1735a480
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799660857 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.799660857
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3427299552
Short name T341
Test name
Test status
Simulation time 4824352810 ps
CPU time 11.25 seconds
Started Jun 05 03:50:40 PM PDT 24
Finished Jun 05 03:50:52 PM PDT 24
Peak memory 211084 kb
Host smart-e240c0d3-7047-4f9d-993c-b1389ae13477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427299552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3427299552
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1307398526
Short name T213
Test name
Test status
Simulation time 2767680790 ps
CPU time 160.93 seconds
Started Jun 05 03:50:40 PM PDT 24
Finished Jun 05 03:53:22 PM PDT 24
Peak memory 212284 kb
Host smart-39893ed6-7429-4bbc-8ebd-8438922dd5fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307398526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1307398526
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3326486308
Short name T296
Test name
Test status
Simulation time 3268424820 ps
CPU time 28.9 seconds
Started Jun 05 03:50:41 PM PDT 24
Finished Jun 05 03:51:11 PM PDT 24
Peak memory 211608 kb
Host smart-19aca76e-f3e6-4091-9c94-90f324c1cc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326486308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3326486308
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1050371432
Short name T350
Test name
Test status
Simulation time 1246209176 ps
CPU time 12.46 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:50:52 PM PDT 24
Peak memory 211028 kb
Host smart-ea7621fd-fdfb-4c0e-a323-47ed491aedf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1050371432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1050371432
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3588086026
Short name T38
Test name
Test status
Simulation time 746112067 ps
CPU time 10.06 seconds
Started Jun 05 03:50:37 PM PDT 24
Finished Jun 05 03:50:48 PM PDT 24
Peak memory 213372 kb
Host smart-814ae938-bfbd-4a65-82ff-e11bd7f72a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588086026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3588086026
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2865318609
Short name T272
Test name
Test status
Simulation time 7227113138 ps
CPU time 71.53 seconds
Started Jun 05 03:50:44 PM PDT 24
Finished Jun 05 03:51:56 PM PDT 24
Peak memory 216452 kb
Host smart-29725ce6-33cb-4d85-b364-895d8871f5d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865318609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2865318609
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1403244883
Short name T2
Test name
Test status
Simulation time 86289146 ps
CPU time 4.19 seconds
Started Jun 05 03:50:47 PM PDT 24
Finished Jun 05 03:50:52 PM PDT 24
Peak memory 211036 kb
Host smart-04c78422-293f-4cf5-b379-a384be3e9e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403244883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1403244883
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1978788638
Short name T251
Test name
Test status
Simulation time 111662678745 ps
CPU time 254.82 seconds
Started Jun 05 03:50:40 PM PDT 24
Finished Jun 05 03:54:56 PM PDT 24
Peak memory 229496 kb
Host smart-e53db8e1-19b2-419b-98c0-8b490b55747d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978788638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1978788638
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.936939534
Short name T334
Test name
Test status
Simulation time 8472147872 ps
CPU time 23.27 seconds
Started Jun 05 03:50:46 PM PDT 24
Finished Jun 05 03:51:10 PM PDT 24
Peak memory 212016 kb
Host smart-c617c9ec-cff1-47f8-bef8-c89971945f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936939534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.936939534
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3599882361
Short name T137
Test name
Test status
Simulation time 361099237 ps
CPU time 6.64 seconds
Started Jun 05 03:50:39 PM PDT 24
Finished Jun 05 03:50:47 PM PDT 24
Peak memory 210904 kb
Host smart-080f1cd8-9da1-4c74-9d5c-e568b537d1a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599882361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3599882361
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1259336650
Short name T257
Test name
Test status
Simulation time 3790195624 ps
CPU time 20.96 seconds
Started Jun 05 03:50:41 PM PDT 24
Finished Jun 05 03:51:03 PM PDT 24
Peak memory 213376 kb
Host smart-dcfad908-6f37-4801-8075-6c73b796d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259336650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1259336650
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2158107705
Short name T241
Test name
Test status
Simulation time 46939653728 ps
CPU time 31.55 seconds
Started Jun 05 03:50:42 PM PDT 24
Finished Jun 05 03:51:14 PM PDT 24
Peak memory 219160 kb
Host smart-d55e08ab-bd49-47e0-97e4-aab79117e270
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158107705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2158107705
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.665369963
Short name T18
Test name
Test status
Simulation time 92012997009 ps
CPU time 5788.01 seconds
Started Jun 05 03:50:40 PM PDT 24
Finished Jun 05 05:27:09 PM PDT 24
Peak memory 230092 kb
Host smart-7e532d96-fcc5-486f-8b9f-3fffb062af36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665369963 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.665369963
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1909472437
Short name T266
Test name
Test status
Simulation time 7431605034 ps
CPU time 15.57 seconds
Started Jun 05 03:50:42 PM PDT 24
Finished Jun 05 03:50:59 PM PDT 24
Peak memory 211204 kb
Host smart-980bcadd-cc5b-4c87-80d3-570324540ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909472437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1909472437
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3660723802
Short name T5
Test name
Test status
Simulation time 52262731754 ps
CPU time 187.36 seconds
Started Jun 05 03:50:42 PM PDT 24
Finished Jun 05 03:53:51 PM PDT 24
Peak memory 220300 kb
Host smart-0db7a1ce-89b4-4cba-9849-c35e3907c4c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660723802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3660723802
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3273175650
Short name T261
Test name
Test status
Simulation time 1109474915 ps
CPU time 16.4 seconds
Started Jun 05 03:50:44 PM PDT 24
Finished Jun 05 03:51:01 PM PDT 24
Peak memory 211840 kb
Host smart-b61c58b2-2fca-4a43-857e-132bb9b937ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273175650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3273175650
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2296941706
Short name T352
Test name
Test status
Simulation time 2060086500 ps
CPU time 11.36 seconds
Started Jun 05 03:50:42 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 210904 kb
Host smart-4750ed38-6165-4217-8c4c-15084606ba56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296941706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2296941706
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3684007953
Short name T149
Test name
Test status
Simulation time 5660964938 ps
CPU time 31.87 seconds
Started Jun 05 03:50:46 PM PDT 24
Finished Jun 05 03:51:18 PM PDT 24
Peak memory 213780 kb
Host smart-56aa5479-1576-4de6-832f-5fffc68229d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684007953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3684007953
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.980477564
Short name T78
Test name
Test status
Simulation time 294718163 ps
CPU time 15.62 seconds
Started Jun 05 03:50:41 PM PDT 24
Finished Jun 05 03:50:57 PM PDT 24
Peak memory 219396 kb
Host smart-5df30fbe-6616-4684-8668-3418d16d1fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980477564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.980477564
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2543584045
Short name T277
Test name
Test status
Simulation time 509375823 ps
CPU time 7.73 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:02 PM PDT 24
Peak memory 210720 kb
Host smart-df240854-9a76-413f-914b-bb27632a81b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543584045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2543584045
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3212295351
Short name T338
Test name
Test status
Simulation time 11005612144 ps
CPU time 216.91 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:53:31 PM PDT 24
Peak memory 230308 kb
Host smart-1177f009-f8be-4475-8df8-c45391a526ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212295351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3212295351
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.412143927
Short name T239
Test name
Test status
Simulation time 3555872932 ps
CPU time 31.46 seconds
Started Jun 05 03:49:53 PM PDT 24
Finished Jun 05 03:50:27 PM PDT 24
Peak memory 211976 kb
Host smart-60c788bc-4d1a-4c7c-af3e-7b9525f59356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412143927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.412143927
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1997158380
Short name T202
Test name
Test status
Simulation time 186696894 ps
CPU time 10.06 seconds
Started Jun 05 03:49:48 PM PDT 24
Finished Jun 05 03:49:59 PM PDT 24
Peak memory 219060 kb
Host smart-70bc116b-96bf-46aa-8394-1c9faa773094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997158380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1997158380
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4017440831
Short name T311
Test name
Test status
Simulation time 933644260 ps
CPU time 20.24 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:50:14 PM PDT 24
Peak memory 210896 kb
Host smart-80ce842c-c7d6-40f8-9c85-735718a9fc20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017440831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4017440831
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2807169902
Short name T225
Test name
Test status
Simulation time 1467024496 ps
CPU time 12.91 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:13 PM PDT 24
Peak memory 209548 kb
Host smart-4eb1aa0f-9ffd-41ca-87af-c00f67441e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807169902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2807169902
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2628905617
Short name T45
Test name
Test status
Simulation time 10496627157 ps
CPU time 184.5 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:53:04 PM PDT 24
Peak memory 224728 kb
Host smart-953912c4-eb4c-4c0f-a16e-5b67b3e9251b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628905617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2628905617
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.26944605
Short name T140
Test name
Test status
Simulation time 21981570190 ps
CPU time 34.1 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:35 PM PDT 24
Peak memory 211768 kb
Host smart-89420adb-edb3-4e51-9fa7-a5f6fc6287eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26944605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.26944605
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2204283020
Short name T178
Test name
Test status
Simulation time 1542272900 ps
CPU time 7.09 seconds
Started Jun 05 03:49:56 PM PDT 24
Finished Jun 05 03:50:05 PM PDT 24
Peak memory 211244 kb
Host smart-90d6e6a9-ba58-42a3-87a1-d616559597dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204283020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2204283020
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2972951778
Short name T115
Test name
Test status
Simulation time 176864922 ps
CPU time 9.94 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:02 PM PDT 24
Peak memory 219076 kb
Host smart-616b780e-1f75-4bc4-92ee-717f99ff402b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972951778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2972951778
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3055564291
Short name T284
Test name
Test status
Simulation time 4631358254 ps
CPU time 23.98 seconds
Started Jun 05 03:49:54 PM PDT 24
Finished Jun 05 03:50:19 PM PDT 24
Peak memory 218880 kb
Host smart-41b0ddf4-8252-4323-9aaf-92204430f814
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055564291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3055564291
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.610750001
Short name T52
Test name
Test status
Simulation time 23517817717 ps
CPU time 6050.64 seconds
Started Jun 05 03:49:53 PM PDT 24
Finished Jun 05 05:30:47 PM PDT 24
Peak memory 230304 kb
Host smart-601fbc70-9b87-48e6-b91e-4358c2dc3849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610750001 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.610750001
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1466693355
Short name T291
Test name
Test status
Simulation time 89144732 ps
CPU time 4.42 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:49:59 PM PDT 24
Peak memory 211036 kb
Host smart-7efd9a99-0da1-4b3e-a758-5ea588bfcdf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466693355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1466693355
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2196549414
Short name T177
Test name
Test status
Simulation time 135236070619 ps
CPU time 214.77 seconds
Started Jun 05 03:49:53 PM PDT 24
Finished Jun 05 03:53:30 PM PDT 24
Peak memory 211008 kb
Host smart-11c136f3-5dcf-4268-af96-babf96a30ad8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196549414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2196549414
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2874851681
Short name T220
Test name
Test status
Simulation time 7301490120 ps
CPU time 34.04 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:50:27 PM PDT 24
Peak memory 212176 kb
Host smart-313985a3-3ec5-4f19-ac6e-213fb1d07d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874851681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2874851681
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1515393826
Short name T10
Test name
Test status
Simulation time 2242401229 ps
CPU time 17 seconds
Started Jun 05 03:49:52 PM PDT 24
Finished Jun 05 03:50:12 PM PDT 24
Peak memory 210708 kb
Host smart-67604b36-d797-4741-9802-884ede097f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515393826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1515393826
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2599956747
Short name T282
Test name
Test status
Simulation time 22469472908 ps
CPU time 38.27 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:50:30 PM PDT 24
Peak memory 213512 kb
Host smart-f57aa444-ef47-4b35-8f97-6836eb549dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599956747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2599956747
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3554861274
Short name T324
Test name
Test status
Simulation time 5644414304 ps
CPU time 57.13 seconds
Started Jun 05 03:49:55 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 219156 kb
Host smart-cebe82f8-e801-451e-8a1f-7fefeb03fbe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554861274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3554861274
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3902453245
Short name T323
Test name
Test status
Simulation time 5789524391 ps
CPU time 13.14 seconds
Started Jun 05 03:49:51 PM PDT 24
Finished Jun 05 03:50:07 PM PDT 24
Peak memory 211080 kb
Host smart-635415ee-31d6-43cd-bb0b-fef6abc9ccf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902453245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3902453245
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1676164597
Short name T236
Test name
Test status
Simulation time 5753662952 ps
CPU time 118.99 seconds
Started Jun 05 03:49:49 PM PDT 24
Finished Jun 05 03:51:50 PM PDT 24
Peak memory 229584 kb
Host smart-9e7b0c77-a938-47a2-ad0f-e761d959c173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676164597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1676164597
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3380695221
Short name T349
Test name
Test status
Simulation time 6978197153 ps
CPU time 29.69 seconds
Started Jun 05 03:50:03 PM PDT 24
Finished Jun 05 03:50:34 PM PDT 24
Peak memory 212432 kb
Host smart-3e2b36cb-9d11-4638-8bce-b85c9e9b271e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380695221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3380695221
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1550610258
Short name T154
Test name
Test status
Simulation time 95590357 ps
CPU time 5.76 seconds
Started Jun 05 03:49:50 PM PDT 24
Finished Jun 05 03:49:57 PM PDT 24
Peak memory 210924 kb
Host smart-748b8b06-ac3d-4fb5-acb8-c4ae96871ef4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550610258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1550610258
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3141895453
Short name T170
Test name
Test status
Simulation time 4143256256 ps
CPU time 17.66 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:18 PM PDT 24
Peak memory 217824 kb
Host smart-b186a23a-3810-42ab-add5-a84097336fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141895453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3141895453
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2581345054
Short name T247
Test name
Test status
Simulation time 7263188618 ps
CPU time 65.34 seconds
Started Jun 05 03:49:47 PM PDT 24
Finished Jun 05 03:50:54 PM PDT 24
Peak memory 219140 kb
Host smart-fc65a9e4-b3cb-42d0-acf4-60bf2c681dbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581345054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2581345054
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.93892494
Short name T151
Test name
Test status
Simulation time 7502109609 ps
CPU time 15.62 seconds
Started Jun 05 03:50:01 PM PDT 24
Finished Jun 05 03:50:19 PM PDT 24
Peak memory 210968 kb
Host smart-bc75c951-57c6-49f9-8983-d33a63dbf000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93892494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.93892494
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2639655523
Short name T362
Test name
Test status
Simulation time 882677437 ps
CPU time 52.13 seconds
Started Jun 05 03:49:58 PM PDT 24
Finished Jun 05 03:50:51 PM PDT 24
Peak memory 226896 kb
Host smart-3cd6b91a-c48d-4e43-98ce-b789cdf19188
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639655523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2639655523
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.591407034
Short name T121
Test name
Test status
Simulation time 2238137184 ps
CPU time 23.44 seconds
Started Jun 05 03:49:58 PM PDT 24
Finished Jun 05 03:50:23 PM PDT 24
Peak memory 211876 kb
Host smart-f4a24bf5-c930-49c8-b29c-22f85c9c124d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591407034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.591407034
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.224410829
Short name T237
Test name
Test status
Simulation time 975213254 ps
CPU time 10.83 seconds
Started Jun 05 03:49:59 PM PDT 24
Finished Jun 05 03:50:11 PM PDT 24
Peak memory 210924 kb
Host smart-6ef1cf8f-fdb7-4cb0-ae1f-22f5136ccf1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224410829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.224410829
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3365616888
Short name T351
Test name
Test status
Simulation time 8247343282 ps
CPU time 32.22 seconds
Started Jun 05 03:50:00 PM PDT 24
Finished Jun 05 03:50:34 PM PDT 24
Peak memory 213748 kb
Host smart-cc864470-ed1a-4839-9bb3-c494a20070af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365616888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3365616888
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2232433887
Short name T345
Test name
Test status
Simulation time 28800364409 ps
CPU time 42.45 seconds
Started Jun 05 03:50:02 PM PDT 24
Finished Jun 05 03:50:46 PM PDT 24
Peak memory 216556 kb
Host smart-f30d3bcd-775f-4350-abe8-4ba859dcbe3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232433887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2232433887
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%