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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.88 92.13 97.72 100.00 98.62 97.45 98.37


Total test records in report: 472
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T300 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2968178127 Jun 06 12:28:03 PM PDT 24 Jun 06 12:30:13 PM PDT 24 13473387176 ps
T301 /workspace/coverage/default/5.rom_ctrl_stress_all.2323745052 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:37 PM PDT 24 280850335 ps
T302 /workspace/coverage/default/32.rom_ctrl_alert_test.2705960987 Jun 06 12:28:03 PM PDT 24 Jun 06 12:28:10 PM PDT 24 126468042 ps
T303 /workspace/coverage/default/42.rom_ctrl_alert_test.298641436 Jun 06 12:27:19 PM PDT 24 Jun 06 12:27:34 PM PDT 24 3406354104 ps
T304 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2428101439 Jun 06 12:27:16 PM PDT 24 Jun 06 12:27:30 PM PDT 24 500797767 ps
T305 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1364283834 Jun 06 12:27:57 PM PDT 24 Jun 06 12:28:15 PM PDT 24 3546584399 ps
T18 /workspace/coverage/default/3.rom_ctrl_sec_cm.1484560346 Jun 06 12:26:26 PM PDT 24 Jun 06 12:27:17 PM PDT 24 1520128866 ps
T306 /workspace/coverage/default/33.rom_ctrl_stress_all.1739026475 Jun 06 12:26:55 PM PDT 24 Jun 06 12:28:20 PM PDT 24 6459460736 ps
T307 /workspace/coverage/default/22.rom_ctrl_smoke.475497594 Jun 06 12:24:48 PM PDT 24 Jun 06 12:25:16 PM PDT 24 10874171321 ps
T308 /workspace/coverage/default/21.rom_ctrl_stress_all.676811172 Jun 06 12:27:52 PM PDT 24 Jun 06 12:28:32 PM PDT 24 4247297773 ps
T309 /workspace/coverage/default/45.rom_ctrl_alert_test.976708795 Jun 06 12:27:23 PM PDT 24 Jun 06 12:27:37 PM PDT 24 14633920986 ps
T310 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4000971117 Jun 06 12:26:27 PM PDT 24 Jun 06 12:26:45 PM PDT 24 2067861314 ps
T24 /workspace/coverage/default/2.rom_ctrl_sec_cm.320874765 Jun 06 12:24:00 PM PDT 24 Jun 06 12:25:42 PM PDT 24 420877949 ps
T311 /workspace/coverage/default/40.rom_ctrl_smoke.3743599326 Jun 06 12:27:17 PM PDT 24 Jun 06 12:27:49 PM PDT 24 6159786385 ps
T312 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1979212272 Jun 06 12:26:21 PM PDT 24 Jun 06 12:26:30 PM PDT 24 1346963648 ps
T313 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.336153148 Jun 06 12:27:22 PM PDT 24 Jun 06 12:44:59 PM PDT 24 28029836186 ps
T314 /workspace/coverage/default/27.rom_ctrl_smoke.805794776 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:40 PM PDT 24 6206343444 ps
T315 /workspace/coverage/default/1.rom_ctrl_stress_all.1607476280 Jun 06 12:22:13 PM PDT 24 Jun 06 12:22:48 PM PDT 24 17454399957 ps
T316 /workspace/coverage/default/10.rom_ctrl_smoke.3433657101 Jun 06 12:26:24 PM PDT 24 Jun 06 12:26:36 PM PDT 24 191208235 ps
T317 /workspace/coverage/default/21.rom_ctrl_smoke.3433213700 Jun 06 12:28:23 PM PDT 24 Jun 06 12:29:00 PM PDT 24 3723956639 ps
T318 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2103641669 Jun 06 12:28:03 PM PDT 24 Jun 06 12:31:13 PM PDT 24 7934937078 ps
T319 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3124574140 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:33 PM PDT 24 3027697707 ps
T320 /workspace/coverage/default/49.rom_ctrl_stress_all.321441994 Jun 06 12:27:24 PM PDT 24 Jun 06 12:28:06 PM PDT 24 8406391304 ps
T321 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.315388626 Jun 06 12:27:21 PM PDT 24 Jun 06 12:29:22 PM PDT 24 1932581415 ps
T322 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2061470798 Jun 06 12:26:24 PM PDT 24 Jun 06 12:31:03 PM PDT 24 96476040605 ps
T323 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3589939696 Jun 06 12:27:17 PM PDT 24 Jun 06 12:29:29 PM PDT 24 27073035714 ps
T324 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3665481385 Jun 06 12:23:59 PM PDT 24 Jun 06 12:28:30 PM PDT 24 43237943711 ps
T325 /workspace/coverage/default/23.rom_ctrl_smoke.2222862036 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:31 PM PDT 24 747986653 ps
T326 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1578263277 Jun 06 12:25:33 PM PDT 24 Jun 06 12:39:56 PM PDT 24 24177260459 ps
T327 /workspace/coverage/default/9.rom_ctrl_alert_test.2438444702 Jun 06 12:27:49 PM PDT 24 Jun 06 12:27:58 PM PDT 24 580539454 ps
T328 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2847419446 Jun 06 12:27:45 PM PDT 24 Jun 06 12:28:01 PM PDT 24 1545703091 ps
T329 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4110636235 Jun 06 12:27:08 PM PDT 24 Jun 06 12:27:15 PM PDT 24 1249051249 ps
T330 /workspace/coverage/default/25.rom_ctrl_smoke.2157291461 Jun 06 12:25:36 PM PDT 24 Jun 06 12:25:47 PM PDT 24 186782743 ps
T331 /workspace/coverage/default/47.rom_ctrl_alert_test.1082417341 Jun 06 12:27:24 PM PDT 24 Jun 06 12:27:41 PM PDT 24 8596552819 ps
T332 /workspace/coverage/default/36.rom_ctrl_stress_all.2408486754 Jun 06 12:27:12 PM PDT 24 Jun 06 12:28:03 PM PDT 24 13303530925 ps
T333 /workspace/coverage/default/0.rom_ctrl_smoke.4123136560 Jun 06 12:23:58 PM PDT 24 Jun 06 12:24:32 PM PDT 24 3852535372 ps
T25 /workspace/coverage/default/0.rom_ctrl_sec_cm.862817736 Jun 06 12:26:23 PM PDT 24 Jun 06 12:27:23 PM PDT 24 4002793267 ps
T334 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4266492141 Jun 06 12:27:17 PM PDT 24 Jun 06 12:28:33 PM PDT 24 4766217784 ps
T335 /workspace/coverage/default/9.rom_ctrl_stress_all.2453998595 Jun 06 12:24:55 PM PDT 24 Jun 06 12:25:30 PM PDT 24 6400891208 ps
T336 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2844991331 Jun 06 12:25:00 PM PDT 24 Jun 06 12:25:14 PM PDT 24 2548975657 ps
T337 /workspace/coverage/default/17.rom_ctrl_smoke.3649503419 Jun 06 12:28:14 PM PDT 24 Jun 06 12:28:52 PM PDT 24 27298671849 ps
T338 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1300328221 Jun 06 12:27:51 PM PDT 24 Jun 06 12:30:04 PM PDT 24 8674507673 ps
T339 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2388925627 Jun 06 12:26:24 PM PDT 24 Jun 06 12:26:32 PM PDT 24 96026401 ps
T340 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.128473236 Jun 06 12:27:46 PM PDT 24 Jun 06 12:28:05 PM PDT 24 8437752913 ps
T341 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2918676138 Jun 06 12:27:17 PM PDT 24 Jun 06 12:31:24 PM PDT 24 41757189489 ps
T342 /workspace/coverage/default/39.rom_ctrl_smoke.912442872 Jun 06 12:27:19 PM PDT 24 Jun 06 12:27:35 PM PDT 24 705705801 ps
T343 /workspace/coverage/default/17.rom_ctrl_alert_test.2066931629 Jun 06 12:24:39 PM PDT 24 Jun 06 12:24:44 PM PDT 24 332839610 ps
T344 /workspace/coverage/default/29.rom_ctrl_stress_all.1415687751 Jun 06 12:27:49 PM PDT 24 Jun 06 12:28:25 PM PDT 24 7551091424 ps
T345 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1464517963 Jun 06 12:26:02 PM PDT 24 Jun 06 12:28:39 PM PDT 24 9120946274 ps
T346 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.931698837 Jun 06 12:23:01 PM PDT 24 Jun 06 12:23:14 PM PDT 24 4288191004 ps
T347 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1194394343 Jun 06 12:27:19 PM PDT 24 Jun 06 12:27:30 PM PDT 24 3916658669 ps
T348 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.375163784 Jun 06 12:27:37 PM PDT 24 Jun 06 12:31:50 PM PDT 24 46765908051 ps
T349 /workspace/coverage/default/36.rom_ctrl_alert_test.446417421 Jun 06 12:28:15 PM PDT 24 Jun 06 12:28:20 PM PDT 24 85616949 ps
T350 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2353209696 Jun 06 12:26:37 PM PDT 24 Jun 06 12:35:56 PM PDT 24 63125270375 ps
T351 /workspace/coverage/default/15.rom_ctrl_stress_all.4244686482 Jun 06 12:27:45 PM PDT 24 Jun 06 12:28:22 PM PDT 24 1902518832 ps
T352 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2856761852 Jun 06 12:27:17 PM PDT 24 Jun 06 12:27:32 PM PDT 24 7007170281 ps
T353 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3785614085 Jun 06 12:27:18 PM PDT 24 Jun 06 12:36:10 PM PDT 24 249900861112 ps
T354 /workspace/coverage/default/11.rom_ctrl_stress_all.2051011256 Jun 06 12:27:59 PM PDT 24 Jun 06 12:28:37 PM PDT 24 5826637853 ps
T355 /workspace/coverage/default/0.rom_ctrl_alert_test.2882971432 Jun 06 12:26:25 PM PDT 24 Jun 06 12:26:32 PM PDT 24 85560629 ps
T356 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3266784328 Jun 06 12:27:17 PM PDT 24 Jun 06 12:27:27 PM PDT 24 348226898 ps
T357 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3540665544 Jun 06 12:27:11 PM PDT 24 Jun 06 12:27:33 PM PDT 24 9541015426 ps
T358 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4080629425 Jun 06 12:24:53 PM PDT 24 Jun 06 12:25:08 PM PDT 24 675586713 ps
T359 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.588964788 Jun 06 12:27:53 PM PDT 24 Jun 06 12:32:44 PM PDT 24 85864434526 ps
T360 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1289755545 Jun 06 12:27:20 PM PDT 24 Jun 06 12:27:31 PM PDT 24 2599836891 ps
T361 /workspace/coverage/default/37.rom_ctrl_stress_all.4120514906 Jun 06 12:28:15 PM PDT 24 Jun 06 12:28:31 PM PDT 24 1527396933 ps
T362 /workspace/coverage/default/30.rom_ctrl_smoke.389574719 Jun 06 12:26:45 PM PDT 24 Jun 06 12:27:17 PM PDT 24 12613169483 ps
T363 /workspace/coverage/default/15.rom_ctrl_smoke.2610003329 Jun 06 12:27:45 PM PDT 24 Jun 06 12:28:09 PM PDT 24 20699113338 ps
T364 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1522275998 Jun 06 12:28:15 PM PDT 24 Jun 06 12:28:46 PM PDT 24 9651653776 ps
T365 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1525942929 Jun 06 12:27:37 PM PDT 24 Jun 06 12:27:43 PM PDT 24 596381708 ps
T366 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2141071988 Jun 06 12:28:08 PM PDT 24 Jun 06 12:28:17 PM PDT 24 1099481970 ps
T367 /workspace/coverage/default/47.rom_ctrl_stress_all.974999018 Jun 06 12:27:24 PM PDT 24 Jun 06 12:27:53 PM PDT 24 486064604 ps
T368 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2592606122 Jun 06 12:27:46 PM PDT 24 Jun 06 12:28:22 PM PDT 24 38733732356 ps
T369 /workspace/coverage/default/43.rom_ctrl_smoke.2870867281 Jun 06 12:27:21 PM PDT 24 Jun 06 12:27:36 PM PDT 24 1200385874 ps
T370 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.134456431 Jun 06 12:26:49 PM PDT 24 Jun 06 12:26:59 PM PDT 24 692515985 ps
T371 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1221971045 Jun 06 12:27:50 PM PDT 24 Jun 06 12:28:03 PM PDT 24 5557471358 ps
T372 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1870113405 Jun 06 12:25:43 PM PDT 24 Jun 06 12:26:03 PM PDT 24 3452652200 ps
T373 /workspace/coverage/default/20.rom_ctrl_stress_all.700788765 Jun 06 12:27:51 PM PDT 24 Jun 06 12:28:13 PM PDT 24 8932473985 ps
T55 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1545901862 Jun 06 12:27:57 PM PDT 24 Jun 06 12:28:13 PM PDT 24 1655219737 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2461079533 Jun 06 12:26:17 PM PDT 24 Jun 06 12:26:30 PM PDT 24 2536879945 ps
T56 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1964327561 Jun 06 12:28:09 PM PDT 24 Jun 06 12:29:44 PM PDT 24 12322374721 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4090230841 Jun 06 12:27:45 PM PDT 24 Jun 06 12:27:58 PM PDT 24 1585967558 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2938754461 Jun 06 12:26:25 PM PDT 24 Jun 06 12:26:42 PM PDT 24 1928129773 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2516164750 Jun 06 12:27:52 PM PDT 24 Jun 06 12:27:58 PM PDT 24 333865647 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.171447309 Jun 06 12:26:32 PM PDT 24 Jun 06 12:26:48 PM PDT 24 1426253443 ps
T57 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1106743858 Jun 06 12:27:24 PM PDT 24 Jun 06 12:27:30 PM PDT 24 333490077 ps
T52 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3071584502 Jun 06 12:27:27 PM PDT 24 Jun 06 12:28:04 PM PDT 24 700960661 ps
T102 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2886211096 Jun 06 12:26:24 PM PDT 24 Jun 06 12:27:06 PM PDT 24 14543187902 ps
T61 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2972930452 Jun 06 12:26:25 PM PDT 24 Jun 06 12:26:35 PM PDT 24 785438987 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2235877383 Jun 06 12:26:37 PM PDT 24 Jun 06 12:26:55 PM PDT 24 6945356371 ps
T53 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2885686937 Jun 06 12:27:27 PM PDT 24 Jun 06 12:28:46 PM PDT 24 2223558600 ps
T54 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2297044272 Jun 06 12:27:24 PM PDT 24 Jun 06 12:28:40 PM PDT 24 5563586125 ps
T62 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3149323861 Jun 06 12:26:35 PM PDT 24 Jun 06 12:26:52 PM PDT 24 15551315804 ps
T63 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2777178552 Jun 06 12:27:20 PM PDT 24 Jun 06 12:27:32 PM PDT 24 1081008408 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3359382711 Jun 06 12:26:21 PM PDT 24 Jun 06 12:27:30 PM PDT 24 1892868395 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2934627947 Jun 06 12:27:28 PM PDT 24 Jun 06 12:27:37 PM PDT 24 292170646 ps
T381 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4115482704 Jun 06 12:27:50 PM PDT 24 Jun 06 12:27:56 PM PDT 24 390308813 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1126065363 Jun 06 12:24:40 PM PDT 24 Jun 06 12:25:48 PM PDT 24 7190446428 ps
T65 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.762024340 Jun 06 12:27:54 PM PDT 24 Jun 06 12:28:03 PM PDT 24 493109740 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3592372658 Jun 06 12:26:29 PM PDT 24 Jun 06 12:26:45 PM PDT 24 2278515847 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.9379457 Jun 06 12:27:05 PM PDT 24 Jun 06 12:27:18 PM PDT 24 13927088546 ps
T111 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3214504635 Jun 06 12:26:19 PM PDT 24 Jun 06 12:27:03 PM PDT 24 4645199626 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1944629403 Jun 06 12:26:37 PM PDT 24 Jun 06 12:26:50 PM PDT 24 5864497486 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.656353980 Jun 06 12:27:23 PM PDT 24 Jun 06 12:27:41 PM PDT 24 3131060360 ps
T67 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3538096448 Jun 06 12:23:44 PM PDT 24 Jun 06 12:24:01 PM PDT 24 25080597039 ps
T114 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4217719381 Jun 06 12:27:57 PM PDT 24 Jun 06 12:29:09 PM PDT 24 288726830 ps
T385 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2223772997 Jun 06 12:26:26 PM PDT 24 Jun 06 12:26:34 PM PDT 24 303498598 ps
T68 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1999317430 Jun 06 12:26:20 PM PDT 24 Jun 06 12:27:07 PM PDT 24 8748259922 ps
T75 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1521529292 Jun 06 12:27:38 PM PDT 24 Jun 06 12:27:57 PM PDT 24 414260046 ps
T98 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1276531813 Jun 06 12:27:37 PM PDT 24 Jun 06 12:27:50 PM PDT 24 5424290289 ps
T99 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2305908753 Jun 06 12:27:26 PM PDT 24 Jun 06 12:27:41 PM PDT 24 1473491498 ps
T386 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1811038338 Jun 06 12:27:20 PM PDT 24 Jun 06 12:27:35 PM PDT 24 14188485424 ps
T76 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.396352213 Jun 06 12:27:34 PM PDT 24 Jun 06 12:28:47 PM PDT 24 8594190759 ps
T387 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1188891186 Jun 06 12:28:21 PM PDT 24 Jun 06 12:28:40 PM PDT 24 7246591645 ps
T388 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2012349380 Jun 06 12:27:34 PM PDT 24 Jun 06 12:27:39 PM PDT 24 87238682 ps
T77 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.896234992 Jun 06 12:27:52 PM PDT 24 Jun 06 12:28:59 PM PDT 24 80742675232 ps
T389 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1028075311 Jun 06 12:27:38 PM PDT 24 Jun 06 12:27:52 PM PDT 24 797656344 ps
T108 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2436324077 Jun 06 12:27:57 PM PDT 24 Jun 06 12:29:05 PM PDT 24 411231350 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4196818103 Jun 06 12:27:26 PM PDT 24 Jun 06 12:27:34 PM PDT 24 333493410 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4114465350 Jun 06 12:22:30 PM PDT 24 Jun 06 12:22:38 PM PDT 24 1358432823 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4192400828 Jun 06 12:27:57 PM PDT 24 Jun 06 12:28:07 PM PDT 24 347716833 ps
T116 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.453745660 Jun 06 12:27:25 PM PDT 24 Jun 06 12:28:39 PM PDT 24 10574170981 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4236305359 Jun 06 12:27:23 PM PDT 24 Jun 06 12:27:36 PM PDT 24 2881578150 ps
T393 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2855801723 Jun 06 12:25:19 PM PDT 24 Jun 06 12:25:39 PM PDT 24 8172800763 ps
T79 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1608197658 Jun 06 12:26:21 PM PDT 24 Jun 06 12:26:39 PM PDT 24 1557906294 ps
T394 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3612160331 Jun 06 12:27:24 PM PDT 24 Jun 06 12:27:32 PM PDT 24 377607158 ps
T395 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4051461819 Jun 06 12:27:38 PM PDT 24 Jun 06 12:27:44 PM PDT 24 789553694 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2899591662 Jun 06 12:28:39 PM PDT 24 Jun 06 12:28:54 PM PDT 24 9545383763 ps
T396 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3537226168 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:26 PM PDT 24 357654323 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2349509844 Jun 06 12:26:30 PM PDT 24 Jun 06 12:26:46 PM PDT 24 1339047770 ps
T81 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1422479951 Jun 06 12:27:10 PM PDT 24 Jun 06 12:27:29 PM PDT 24 1434541732 ps
T398 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3168076139 Jun 06 12:27:51 PM PDT 24 Jun 06 12:28:07 PM PDT 24 1663122662 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2499098366 Jun 06 12:26:35 PM PDT 24 Jun 06 12:26:41 PM PDT 24 85400677 ps
T399 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1153267476 Jun 06 12:27:27 PM PDT 24 Jun 06 12:27:34 PM PDT 24 347019923 ps
T82 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.142114173 Jun 06 12:28:17 PM PDT 24 Jun 06 12:28:45 PM PDT 24 1986054675 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.354222323 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:35 PM PDT 24 5818350086 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1254438405 Jun 06 12:26:19 PM PDT 24 Jun 06 12:27:10 PM PDT 24 5853800486 ps
T80 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1883414322 Jun 06 12:27:05 PM PDT 24 Jun 06 12:27:18 PM PDT 24 2626934394 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3533075834 Jun 06 12:26:18 PM PDT 24 Jun 06 12:26:25 PM PDT 24 554627200 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3560173884 Jun 06 12:27:36 PM PDT 24 Jun 06 12:27:44 PM PDT 24 85592968 ps
T403 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2410412658 Jun 06 12:27:36 PM PDT 24 Jun 06 12:27:42 PM PDT 24 122961301 ps
T404 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4221441328 Jun 06 12:26:34 PM PDT 24 Jun 06 12:26:50 PM PDT 24 11956900184 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1050058387 Jun 06 12:27:57 PM PDT 24 Jun 06 12:28:16 PM PDT 24 2129035072 ps
T406 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1623023742 Jun 06 12:27:23 PM PDT 24 Jun 06 12:27:37 PM PDT 24 1590030325 ps
T109 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3287343152 Jun 06 12:26:29 PM PDT 24 Jun 06 12:27:46 PM PDT 24 11345836617 ps
T112 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2833326193 Jun 06 12:27:38 PM PDT 24 Jun 06 12:28:17 PM PDT 24 283018129 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1332900609 Jun 06 12:27:21 PM PDT 24 Jun 06 12:28:35 PM PDT 24 15218957896 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1750438685 Jun 06 12:26:16 PM PDT 24 Jun 06 12:26:27 PM PDT 24 1145724076 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1669381249 Jun 06 12:26:26 PM PDT 24 Jun 06 12:26:34 PM PDT 24 6609533439 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1770326295 Jun 06 12:26:39 PM PDT 24 Jun 06 12:27:16 PM PDT 24 174377639 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1147687185 Jun 06 12:27:27 PM PDT 24 Jun 06 12:28:00 PM PDT 24 2396948357 ps
T410 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.122442767 Jun 06 12:26:45 PM PDT 24 Jun 06 12:26:52 PM PDT 24 474580212 ps
T411 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.801973352 Jun 06 12:26:45 PM PDT 24 Jun 06 12:26:57 PM PDT 24 3807998832 ps
T412 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.689330369 Jun 06 12:27:06 PM PDT 24 Jun 06 12:27:21 PM PDT 24 12689126577 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1945345297 Jun 06 12:26:51 PM PDT 24 Jun 06 12:27:03 PM PDT 24 1157731893 ps
T414 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3264178713 Jun 06 12:26:39 PM PDT 24 Jun 06 12:26:55 PM PDT 24 3841243281 ps
T415 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3393536450 Jun 06 12:27:38 PM PDT 24 Jun 06 12:27:43 PM PDT 24 175437821 ps
T416 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3191101368 Jun 06 12:27:58 PM PDT 24 Jun 06 12:28:09 PM PDT 24 543113314 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4059962115 Jun 06 12:28:27 PM PDT 24 Jun 06 12:28:43 PM PDT 24 7509850721 ps
T418 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3277402291 Jun 06 12:27:35 PM PDT 24 Jun 06 12:27:41 PM PDT 24 326410182 ps
T419 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2998296290 Jun 06 12:27:38 PM PDT 24 Jun 06 12:28:18 PM PDT 24 535102966 ps
T420 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2666933340 Jun 06 12:27:52 PM PDT 24 Jun 06 12:27:59 PM PDT 24 429816209 ps
T117 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3988913448 Jun 06 12:28:21 PM PDT 24 Jun 06 12:28:58 PM PDT 24 198189246 ps
T421 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2910401344 Jun 06 12:27:35 PM PDT 24 Jun 06 12:27:53 PM PDT 24 7511002318 ps
T422 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1105689332 Jun 06 12:26:21 PM PDT 24 Jun 06 12:26:32 PM PDT 24 3258378283 ps
T423 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3629182980 Jun 06 12:26:21 PM PDT 24 Jun 06 12:26:33 PM PDT 24 172464949 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3643303288 Jun 06 12:24:00 PM PDT 24 Jun 06 12:24:16 PM PDT 24 3175809749 ps
T84 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.266890081 Jun 06 12:26:29 PM PDT 24 Jun 06 12:27:58 PM PDT 24 98729632681 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3490940272 Jun 06 12:27:26 PM PDT 24 Jun 06 12:27:44 PM PDT 24 8373981641 ps
T426 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1346137043 Jun 06 12:26:26 PM PDT 24 Jun 06 12:26:38 PM PDT 24 3813823278 ps
T427 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.483337611 Jun 06 12:26:35 PM PDT 24 Jun 06 12:26:47 PM PDT 24 4312474684 ps
T113 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1668621620 Jun 06 12:27:37 PM PDT 24 Jun 06 12:28:49 PM PDT 24 4351171492 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.414780802 Jun 06 12:27:35 PM PDT 24 Jun 06 12:27:49 PM PDT 24 2945049556 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4249050026 Jun 06 12:26:27 PM PDT 24 Jun 06 12:26:38 PM PDT 24 829388753 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1746760409 Jun 06 12:26:33 PM PDT 24 Jun 06 12:26:45 PM PDT 24 1321505482 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3862143610 Jun 06 12:27:56 PM PDT 24 Jun 06 12:28:02 PM PDT 24 261953699 ps
T432 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2559842137 Jun 06 12:26:18 PM PDT 24 Jun 06 12:27:14 PM PDT 24 6037145443 ps
T433 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3245972610 Jun 06 12:27:24 PM PDT 24 Jun 06 12:28:15 PM PDT 24 5752724753 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3978801214 Jun 06 12:28:03 PM PDT 24 Jun 06 12:28:45 PM PDT 24 4312427986 ps
T435 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1398174078 Jun 06 12:27:22 PM PDT 24 Jun 06 12:27:36 PM PDT 24 1597650902 ps
T118 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1356427613 Jun 06 12:26:15 PM PDT 24 Jun 06 12:26:51 PM PDT 24 602923034 ps
T436 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2954697162 Jun 06 12:26:29 PM PDT 24 Jun 06 12:26:42 PM PDT 24 648614667 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.463184948 Jun 06 12:27:51 PM PDT 24 Jun 06 12:28:07 PM PDT 24 9688411921 ps
T85 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3318324730 Jun 06 12:25:35 PM PDT 24 Jun 06 12:25:54 PM PDT 24 385329390 ps
T86 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.849010407 Jun 06 12:27:49 PM PDT 24 Jun 06 12:29:12 PM PDT 24 9114777478 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4052783298 Jun 06 12:27:15 PM PDT 24 Jun 06 12:27:28 PM PDT 24 1255379942 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.367736504 Jun 06 12:27:57 PM PDT 24 Jun 06 12:28:05 PM PDT 24 332716123 ps
T440 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3785361067 Jun 06 12:26:25 PM PDT 24 Jun 06 12:26:30 PM PDT 24 85627162 ps
T441 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1506409166 Jun 06 12:28:21 PM PDT 24 Jun 06 12:28:27 PM PDT 24 174854630 ps
T442 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3435238653 Jun 06 12:27:35 PM PDT 24 Jun 06 12:27:44 PM PDT 24 656376576 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2884721835 Jun 06 12:27:57 PM PDT 24 Jun 06 12:28:04 PM PDT 24 821028267 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3444545928 Jun 06 12:28:24 PM PDT 24 Jun 06 12:28:51 PM PDT 24 2502985405 ps
T445 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2784043753 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:30 PM PDT 24 2379399414 ps
T446 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2713617495 Jun 06 12:26:17 PM PDT 24 Jun 06 12:26:39 PM PDT 24 2103804631 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3300191833 Jun 06 12:28:21 PM PDT 24 Jun 06 12:28:37 PM PDT 24 10701816733 ps
T120 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1295323741 Jun 06 12:27:11 PM PDT 24 Jun 06 12:27:48 PM PDT 24 337303300 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.668455352 Jun 06 12:26:25 PM PDT 24 Jun 06 12:26:32 PM PDT 24 347152106 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3800704711 Jun 06 12:26:18 PM PDT 24 Jun 06 12:26:32 PM PDT 24 4937165993 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2594950454 Jun 06 12:27:44 PM PDT 24 Jun 06 12:27:49 PM PDT 24 378970935 ps
T451 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.508206208 Jun 06 12:22:32 PM PDT 24 Jun 06 12:22:48 PM PDT 24 4060975751 ps
T452 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1057868401 Jun 06 12:23:30 PM PDT 24 Jun 06 12:23:43 PM PDT 24 1679712426 ps
T119 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2673786292 Jun 06 12:26:25 PM PDT 24 Jun 06 12:27:35 PM PDT 24 279849045 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1898242732 Jun 06 12:24:21 PM PDT 24 Jun 06 12:24:34 PM PDT 24 4754161992 ps
T454 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.160948199 Jun 06 12:27:35 PM PDT 24 Jun 06 12:27:52 PM PDT 24 4122067242 ps
T455 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3589659060 Jun 06 12:27:38 PM PDT 24 Jun 06 12:29:01 PM PDT 24 35924984786 ps
T456 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1426423642 Jun 06 12:26:37 PM PDT 24 Jun 06 12:26:53 PM PDT 24 1688998133 ps
T457 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1241488965 Jun 06 12:26:18 PM PDT 24 Jun 06 12:27:04 PM PDT 24 1482773454 ps
T458 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3061587266 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:35 PM PDT 24 1653705134 ps
T459 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.371989038 Jun 06 12:28:15 PM PDT 24 Jun 06 12:28:25 PM PDT 24 864723108 ps
T460 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1934816932 Jun 06 12:26:29 PM PDT 24 Jun 06 12:26:46 PM PDT 24 9089880204 ps
T115 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1421496901 Jun 06 12:26:24 PM PDT 24 Jun 06 12:27:39 PM PDT 24 2942446711 ps
T461 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3973298117 Jun 06 12:27:21 PM PDT 24 Jun 06 12:28:34 PM PDT 24 138221251068 ps
T462 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.769623508 Jun 06 12:26:26 PM PDT 24 Jun 06 12:26:38 PM PDT 24 147621879 ps
T463 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3884475959 Jun 06 12:23:44 PM PDT 24 Jun 06 12:23:58 PM PDT 24 1441126115 ps
T464 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3275928211 Jun 06 12:27:23 PM PDT 24 Jun 06 12:27:29 PM PDT 24 201394406 ps
T465 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2660387612 Jun 06 12:25:07 PM PDT 24 Jun 06 12:25:20 PM PDT 24 16745921189 ps
T466 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.602687345 Jun 06 12:27:12 PM PDT 24 Jun 06 12:27:27 PM PDT 24 7879494913 ps
T467 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3670916598 Jun 06 12:27:37 PM PDT 24 Jun 06 12:27:57 PM PDT 24 11132269983 ps
T468 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.894916484 Jun 06 12:27:52 PM PDT 24 Jun 06 12:28:04 PM PDT 24 8695252633 ps
T469 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2538104649 Jun 06 12:26:20 PM PDT 24 Jun 06 12:26:29 PM PDT 24 992946288 ps
T470 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.859316498 Jun 06 12:26:24 PM PDT 24 Jun 06 12:26:38 PM PDT 24 1349794676 ps
T471 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2252716971 Jun 06 12:26:19 PM PDT 24 Jun 06 12:26:35 PM PDT 24 2926095772 ps
T472 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4129317690 Jun 06 12:27:35 PM PDT 24 Jun 06 12:27:47 PM PDT 24 905660008 ps

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.522676874
Short name T6
Test name
Test status
Simulation time 87069601576 ps
CPU time 458.53 seconds
Started Jun 06 12:24:30 PM PDT 24
Finished Jun 06 12:32:09 PM PDT 24
Peak memory 235272 kb
Host smart-a6b86142-0ada-4e4d-85d9-0640edbcddd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522676874 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.522676874
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2666557889
Short name T2
Test name
Test status
Simulation time 170030936352 ps
CPU time 392.29 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:34:57 PM PDT 24
Peak memory 235996 kb
Host smart-80d9b35d-85ad-4144-81ca-3b1a6a7c9cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666557889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2666557889
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2297044272
Short name T54
Test name
Test status
Simulation time 5563586125 ps
CPU time 74.21 seconds
Started Jun 06 12:27:24 PM PDT 24
Finished Jun 06 12:28:40 PM PDT 24
Peak memory 219160 kb
Host smart-4f6744d7-e39e-40d2-a7a9-0ef0ad74c1d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297044272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2297044272
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1673333701
Short name T40
Test name
Test status
Simulation time 222847464286 ps
CPU time 266.23 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:30:49 PM PDT 24
Peak memory 224324 kb
Host smart-1b21f787-2d1b-43a5-b97a-7ef829c62ab2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673333701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1673333701
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.675364048
Short name T10
Test name
Test status
Simulation time 65357161076 ps
CPU time 155.36 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:30:30 PM PDT 24
Peak memory 218712 kb
Host smart-f2e4bff9-202b-4872-b14a-678c9d1ae909
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675364048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.675364048
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3806667171
Short name T16
Test name
Test status
Simulation time 237794216 ps
CPU time 98.67 seconds
Started Jun 06 12:26:16 PM PDT 24
Finished Jun 06 12:27:56 PM PDT 24
Peak memory 237404 kb
Host smart-b3ab0d10-ede4-48cc-a00e-3c3596aebab3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806667171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3806667171
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1944629403
Short name T66
Test name
Test status
Simulation time 5864497486 ps
CPU time 12.09 seconds
Started Jun 06 12:26:37 PM PDT 24
Finished Jun 06 12:26:50 PM PDT 24
Peak memory 219024 kb
Host smart-a198a559-43fb-46ee-ada7-acc0757532cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944629403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1944629403
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3214504635
Short name T111
Test name
Test status
Simulation time 4645199626 ps
CPU time 42.82 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:27:03 PM PDT 24
Peak memory 218528 kb
Host smart-96bc1890-1abb-427e-ba23-ed78317d8068
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214504635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3214504635
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1521529292
Short name T75
Test name
Test status
Simulation time 414260046 ps
CPU time 18.23 seconds
Started Jun 06 12:27:38 PM PDT 24
Finished Jun 06 12:27:57 PM PDT 24
Peak memory 210904 kb
Host smart-90035f1b-5550-4432-b81f-10cbd922f55e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521529292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1521529292
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3679052632
Short name T22
Test name
Test status
Simulation time 1975258958 ps
CPU time 9.91 seconds
Started Jun 06 12:25:43 PM PDT 24
Finished Jun 06 12:25:54 PM PDT 24
Peak memory 210572 kb
Host smart-732196ab-7a12-44c7-a71c-9ca644a4e84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679052632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3679052632
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3641658960
Short name T45
Test name
Test status
Simulation time 1378630156 ps
CPU time 11.12 seconds
Started Jun 06 12:25:36 PM PDT 24
Finished Jun 06 12:25:47 PM PDT 24
Peak memory 211880 kb
Host smart-e7543f89-83e9-4504-968c-20e11f2603fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641658960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3641658960
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2807555888
Short name T13
Test name
Test status
Simulation time 7162799201 ps
CPU time 30.7 seconds
Started Jun 06 12:22:35 PM PDT 24
Finished Jun 06 12:23:06 PM PDT 24
Peak memory 212188 kb
Host smart-7aa97c52-3230-45e9-b7d2-197643a83d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807555888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2807555888
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4192357743
Short name T44
Test name
Test status
Simulation time 5862665442 ps
CPU time 26.08 seconds
Started Jun 06 12:27:56 PM PDT 24
Finished Jun 06 12:28:24 PM PDT 24
Peak memory 211356 kb
Host smart-abf13f87-0701-4140-a10d-0e566cefbafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192357743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4192357743
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2673786292
Short name T119
Test name
Test status
Simulation time 279849045 ps
CPU time 67.72 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:27:35 PM PDT 24
Peak memory 212532 kb
Host smart-f6e16cc5-d449-406f-833e-bb6c00b99657
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673786292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2673786292
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3083180210
Short name T12
Test name
Test status
Simulation time 173887208909 ps
CPU time 1531.78 seconds
Started Jun 06 12:26:23 PM PDT 24
Finished Jun 06 12:51:57 PM PDT 24
Peak memory 234324 kb
Host smart-776cb406-b28e-48ac-8ad6-bc7f52c23134
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083180210 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3083180210
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.411284031
Short name T88
Test name
Test status
Simulation time 1333570762 ps
CPU time 12.74 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:28:07 PM PDT 24
Peak memory 210604 kb
Host smart-685a83c8-eb2b-4063-99fe-8ac5d9d6a2d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411284031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.411284031
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2633676649
Short name T48
Test name
Test status
Simulation time 250946890739 ps
CPU time 4552.19 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 01:42:20 PM PDT 24
Peak memory 251168 kb
Host smart-041e5258-8fd9-48a1-bb96-e206416b8b45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633676649 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2633676649
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.602687345
Short name T466
Test name
Test status
Simulation time 7879494913 ps
CPU time 14.23 seconds
Started Jun 06 12:27:12 PM PDT 24
Finished Jun 06 12:27:27 PM PDT 24
Peak memory 219040 kb
Host smart-3e918d42-3096-4f10-8588-82b092d402a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602687345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.602687345
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4052783298
Short name T438
Test name
Test status
Simulation time 1255379942 ps
CPU time 12.17 seconds
Started Jun 06 12:27:15 PM PDT 24
Finished Jun 06 12:27:28 PM PDT 24
Peak memory 218356 kb
Host smart-3b447dd1-100f-415c-941f-0a5758095ae6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052783298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4052783298
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2934627947
Short name T380
Test name
Test status
Simulation time 292170646 ps
CPU time 7.52 seconds
Started Jun 06 12:27:28 PM PDT 24
Finished Jun 06 12:27:37 PM PDT 24
Peak memory 210064 kb
Host smart-2262f4a4-2c14-4fa1-8557-394e5a86df24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934627947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2934627947
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4249050026
Short name T429
Test name
Test status
Simulation time 829388753 ps
CPU time 10.31 seconds
Started Jun 06 12:26:27 PM PDT 24
Finished Jun 06 12:26:38 PM PDT 24
Peak memory 219200 kb
Host smart-0a1fb884-ba8e-41eb-81c0-7e8fc0e91dc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249050026 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4249050026
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.668455352
Short name T448
Test name
Test status
Simulation time 347152106 ps
CPU time 4.19 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 210124 kb
Host smart-40e7e337-26ee-429b-8047-db36e4b4881e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668455352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.668455352
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1945345297
Short name T413
Test name
Test status
Simulation time 1157731893 ps
CPU time 10.95 seconds
Started Jun 06 12:26:51 PM PDT 24
Finished Jun 06 12:27:03 PM PDT 24
Peak memory 210752 kb
Host smart-1d5221d1-220d-4497-ad02-940d02ebd81b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945345297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1945345297
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2594950454
Short name T450
Test name
Test status
Simulation time 378970935 ps
CPU time 4.03 seconds
Started Jun 06 12:27:44 PM PDT 24
Finished Jun 06 12:27:49 PM PDT 24
Peak memory 210612 kb
Host smart-942198f7-acff-4459-868a-4d7711b82e5f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594950454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2594950454
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1422479951
Short name T81
Test name
Test status
Simulation time 1434541732 ps
CPU time 18.11 seconds
Started Jun 06 12:27:10 PM PDT 24
Finished Jun 06 12:27:29 PM PDT 24
Peak memory 210856 kb
Host smart-d216bd2a-76eb-4ed9-8efe-762b588f0cff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422479951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1422479951
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.367736504
Short name T439
Test name
Test status
Simulation time 332716123 ps
CPU time 6.3 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:05 PM PDT 24
Peak memory 218076 kb
Host smart-1868b07a-2d85-40de-9ef7-dc2d7662070e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367736504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.367736504
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3560173884
Short name T402
Test name
Test status
Simulation time 85592968 ps
CPU time 6.7 seconds
Started Jun 06 12:27:36 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 218808 kb
Host smart-ce8d251e-c8e7-4d70-8422-faca472542d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560173884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3560173884
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1295323741
Short name T120
Test name
Test status
Simulation time 337303300 ps
CPU time 36 seconds
Started Jun 06 12:27:11 PM PDT 24
Finished Jun 06 12:27:48 PM PDT 24
Peak memory 218980 kb
Host smart-043bb517-4ad7-4d90-8c64-d30cdadd048d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295323741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1295323741
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4114465350
Short name T391
Test name
Test status
Simulation time 1358432823 ps
CPU time 6.77 seconds
Started Jun 06 12:22:30 PM PDT 24
Finished Jun 06 12:22:38 PM PDT 24
Peak memory 217760 kb
Host smart-39ba9981-dba4-4a8c-ad9d-8de5b80d5369
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114465350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4114465350
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1050058387
Short name T405
Test name
Test status
Simulation time 2129035072 ps
CPU time 16.85 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:16 PM PDT 24
Peak memory 210760 kb
Host smart-6d6b1115-6955-49f0-b01b-e74da039f3c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050058387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1050058387
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4192400828
Short name T78
Test name
Test status
Simulation time 347716833 ps
CPU time 8.09 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:07 PM PDT 24
Peak memory 210760 kb
Host smart-6d085295-0f2d-4381-9bad-315b08f3b06f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192400828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4192400828
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.9379457
Short name T383
Test name
Test status
Simulation time 13927088546 ps
CPU time 11.97 seconds
Started Jun 06 12:27:05 PM PDT 24
Finished Jun 06 12:27:18 PM PDT 24
Peak memory 219136 kb
Host smart-91c188a6-ea8d-49e3-ba2f-be6c15cfa8c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9379457 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.9379457
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3884475959
Short name T463
Test name
Test status
Simulation time 1441126115 ps
CPU time 12.86 seconds
Started Jun 06 12:23:44 PM PDT 24
Finished Jun 06 12:23:58 PM PDT 24
Peak memory 210940 kb
Host smart-ddae8231-5320-46c0-a8d7-130797d1ef8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884475959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3884475959
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2884721835
Short name T443
Test name
Test status
Simulation time 821028267 ps
CPU time 5.54 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:04 PM PDT 24
Peak memory 210500 kb
Host smart-a799db8a-3ca8-4d66-bca5-7664fa24854c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884721835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2884721835
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2938754461
Short name T376
Test name
Test status
Simulation time 1928129773 ps
CPU time 14.62 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:42 PM PDT 24
Peak memory 210048 kb
Host smart-1302af35-8bd1-4146-a133-e537cc605bef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938754461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2938754461
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3444545928
Short name T444
Test name
Test status
Simulation time 2502985405 ps
CPU time 25.49 seconds
Started Jun 06 12:28:24 PM PDT 24
Finished Jun 06 12:28:51 PM PDT 24
Peak memory 210712 kb
Host smart-81000f13-d989-45ab-bbb8-2f81674af2de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444545928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3444545928
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3300191833
Short name T447
Test name
Test status
Simulation time 10701816733 ps
CPU time 14.53 seconds
Started Jun 06 12:28:21 PM PDT 24
Finished Jun 06 12:28:37 PM PDT 24
Peak memory 219096 kb
Host smart-837b6df6-98af-45fc-842a-1b47988185ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300191833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3300191833
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4090230841
Short name T375
Test name
Test status
Simulation time 1585967558 ps
CPU time 10.95 seconds
Started Jun 06 12:27:45 PM PDT 24
Finished Jun 06 12:27:58 PM PDT 24
Peak memory 218184 kb
Host smart-d40e487e-5929-48be-a959-ce98afb60763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090230841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4090230841
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2436324077
Short name T108
Test name
Test status
Simulation time 411231350 ps
CPU time 66.28 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:29:05 PM PDT 24
Peak memory 218900 kb
Host smart-97fc2625-f971-4724-b0fb-fa467f5c967b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436324077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2436324077
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4115482704
Short name T381
Test name
Test status
Simulation time 390308813 ps
CPU time 4.37 seconds
Started Jun 06 12:27:50 PM PDT 24
Finished Jun 06 12:27:56 PM PDT 24
Peak memory 218800 kb
Host smart-df6cbe29-786c-4f42-b484-93912ccd3b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115482704 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4115482704
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1105689332
Short name T422
Test name
Test status
Simulation time 3258378283 ps
CPU time 8.79 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 218388 kb
Host smart-4f141a97-6634-4fe1-abac-8a046723a477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105689332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1105689332
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2886211096
Short name T102
Test name
Test status
Simulation time 14543187902 ps
CPU time 39.87 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:27:06 PM PDT 24
Peak memory 209804 kb
Host smart-7170abb6-18d8-4e56-a849-2b7635d1bea4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886211096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2886211096
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2660387612
Short name T465
Test name
Test status
Simulation time 16745921189 ps
CPU time 13.2 seconds
Started Jun 06 12:25:07 PM PDT 24
Finished Jun 06 12:25:20 PM PDT 24
Peak memory 218192 kb
Host smart-ed030f7a-30c0-43d9-b390-663ba6a88766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660387612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2660387612
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.769623508
Short name T462
Test name
Test status
Simulation time 147621879 ps
CPU time 9.65 seconds
Started Jun 06 12:26:26 PM PDT 24
Finished Jun 06 12:26:38 PM PDT 24
Peak memory 218644 kb
Host smart-f718b6cd-2251-45d8-9cab-0ec077392b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769623508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.769623508
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2666933340
Short name T420
Test name
Test status
Simulation time 429816209 ps
CPU time 5.08 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:27:59 PM PDT 24
Peak memory 217848 kb
Host smart-4de9e967-d46b-48d1-a156-45a223f575da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666933340 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2666933340
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3264178713
Short name T414
Test name
Test status
Simulation time 3841243281 ps
CPU time 15.17 seconds
Started Jun 06 12:26:39 PM PDT 24
Finished Jun 06 12:26:55 PM PDT 24
Peak memory 219056 kb
Host smart-50bad6c0-c399-47f6-8290-00596ea29f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264178713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3264178713
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.849010407
Short name T86
Test name
Test status
Simulation time 9114777478 ps
CPU time 81.45 seconds
Started Jun 06 12:27:49 PM PDT 24
Finished Jun 06 12:29:12 PM PDT 24
Peak memory 209900 kb
Host smart-7712dc49-708b-4e42-9176-316c084f4c18
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849010407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.849010407
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1426423642
Short name T456
Test name
Test status
Simulation time 1688998133 ps
CPU time 15 seconds
Started Jun 06 12:26:37 PM PDT 24
Finished Jun 06 12:26:53 PM PDT 24
Peak memory 210860 kb
Host smart-c46efd9a-051f-4b9c-9084-ba246ef295e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426423642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1426423642
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2235877383
Short name T379
Test name
Test status
Simulation time 6945356371 ps
CPU time 16.68 seconds
Started Jun 06 12:26:37 PM PDT 24
Finished Jun 06 12:26:55 PM PDT 24
Peak memory 218920 kb
Host smart-592004a0-f4ef-4186-bfda-1945ceb42baa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235877383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2235877383
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1241488965
Short name T457
Test name
Test status
Simulation time 1482773454 ps
CPU time 43.16 seconds
Started Jun 06 12:26:18 PM PDT 24
Finished Jun 06 12:27:04 PM PDT 24
Peak memory 217716 kb
Host smart-9efd9284-e792-4bf1-a6be-fe71396878e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241488965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1241488965
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3537226168
Short name T396
Test name
Test status
Simulation time 357654323 ps
CPU time 4.24 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:26 PM PDT 24
Peak memory 218916 kb
Host smart-2f40daeb-8d25-4382-bcab-0742b5c31f40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537226168 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3537226168
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4221441328
Short name T404
Test name
Test status
Simulation time 11956900184 ps
CPU time 14.82 seconds
Started Jun 06 12:26:34 PM PDT 24
Finished Jun 06 12:26:50 PM PDT 24
Peak memory 219024 kb
Host smart-c9a4e56b-3491-4a26-b8be-b1d887e1f026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221441328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4221441328
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1999317430
Short name T68
Test name
Test status
Simulation time 8748259922 ps
CPU time 44.64 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:27:07 PM PDT 24
Peak memory 209276 kb
Host smart-d8db36db-170c-470e-a13c-985092a0b97a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999317430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1999317430
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2784043753
Short name T445
Test name
Test status
Simulation time 2379399414 ps
CPU time 7.32 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:30 PM PDT 24
Peak memory 209844 kb
Host smart-9bbc9066-8bf5-48e4-9a4e-de8e063567f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784043753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2784043753
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3629182980
Short name T423
Test name
Test status
Simulation time 172464949 ps
CPU time 10.01 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:33 PM PDT 24
Peak memory 216280 kb
Host smart-0709c661-fbfe-4487-b1f7-ac6c4bc6346f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629182980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3629182980
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1770326295
Short name T409
Test name
Test status
Simulation time 174377639 ps
CPU time 36.18 seconds
Started Jun 06 12:26:39 PM PDT 24
Finished Jun 06 12:27:16 PM PDT 24
Peak memory 219048 kb
Host smart-1905b734-03b4-43bd-9af6-4f59359847ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770326295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1770326295
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3435238653
Short name T442
Test name
Test status
Simulation time 656376576 ps
CPU time 8.02 seconds
Started Jun 06 12:27:35 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 212800 kb
Host smart-a2675747-56bf-4689-946b-63d5897c52d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435238653 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3435238653
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2899591662
Short name T100
Test name
Test status
Simulation time 9545383763 ps
CPU time 13.26 seconds
Started Jun 06 12:28:39 PM PDT 24
Finished Jun 06 12:28:54 PM PDT 24
Peak memory 217384 kb
Host smart-349aacd9-a7fa-499a-adad-93ff0d50fb05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899591662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2899591662
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2559842137
Short name T432
Test name
Test status
Simulation time 6037145443 ps
CPU time 53.65 seconds
Started Jun 06 12:26:18 PM PDT 24
Finished Jun 06 12:27:14 PM PDT 24
Peak memory 210664 kb
Host smart-b252b2e9-6730-47f0-9aba-8f7f209a7565
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559842137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2559842137
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1398174078
Short name T435
Test name
Test status
Simulation time 1597650902 ps
CPU time 13.13 seconds
Started Jun 06 12:27:22 PM PDT 24
Finished Jun 06 12:27:36 PM PDT 24
Peak memory 210788 kb
Host smart-17b667fe-1dc9-412b-abd1-168c5c6754e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398174078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1398174078
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2713617495
Short name T446
Test name
Test status
Simulation time 2103804631 ps
CPU time 19.89 seconds
Started Jun 06 12:26:17 PM PDT 24
Finished Jun 06 12:26:39 PM PDT 24
Peak memory 217188 kb
Host smart-edd8b73d-acf8-4caf-939e-174e23533b85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713617495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2713617495
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3071584502
Short name T52
Test name
Test status
Simulation time 700960661 ps
CPU time 35.97 seconds
Started Jun 06 12:27:27 PM PDT 24
Finished Jun 06 12:28:04 PM PDT 24
Peak memory 219052 kb
Host smart-bdb07507-5f1e-49cf-a0fa-6df92d6da9f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071584502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3071584502
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1811038338
Short name T386
Test name
Test status
Simulation time 14188485424 ps
CPU time 14.21 seconds
Started Jun 06 12:27:20 PM PDT 24
Finished Jun 06 12:27:35 PM PDT 24
Peak memory 219336 kb
Host smart-be13fded-e825-4227-b898-7e6836fcb01c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811038338 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1811038338
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3490940272
Short name T425
Test name
Test status
Simulation time 8373981641 ps
CPU time 16.37 seconds
Started Jun 06 12:27:26 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 210908 kb
Host smart-5e90220d-fa45-419a-9d78-a7b28d6396f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490940272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3490940272
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3589659060
Short name T455
Test name
Test status
Simulation time 35924984786 ps
CPU time 81.98 seconds
Started Jun 06 12:27:38 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 210964 kb
Host smart-819d7c22-690d-44df-9666-d3f98289506d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589659060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3589659060
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1106743858
Short name T57
Test name
Test status
Simulation time 333490077 ps
CPU time 4.32 seconds
Started Jun 06 12:27:24 PM PDT 24
Finished Jun 06 12:27:30 PM PDT 24
Peak memory 218480 kb
Host smart-aaf98776-3547-4652-91b6-08eaea76a16a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106743858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1106743858
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1028075311
Short name T389
Test name
Test status
Simulation time 797656344 ps
CPU time 13.02 seconds
Started Jun 06 12:27:38 PM PDT 24
Finished Jun 06 12:27:52 PM PDT 24
Peak memory 218928 kb
Host smart-0c8a7097-06cf-473a-a07e-04d5e1fcaa64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028075311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1028075311
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.453745660
Short name T116
Test name
Test status
Simulation time 10574170981 ps
CPU time 73.39 seconds
Started Jun 06 12:27:25 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 219124 kb
Host smart-0f857d31-42b4-4117-aedf-266df48d3a18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453745660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.453745660
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3275928211
Short name T464
Test name
Test status
Simulation time 201394406 ps
CPU time 5.31 seconds
Started Jun 06 12:27:23 PM PDT 24
Finished Jun 06 12:27:29 PM PDT 24
Peak memory 212420 kb
Host smart-05772052-44ec-4868-a938-cd54c3b785d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275928211 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3275928211
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3393536450
Short name T415
Test name
Test status
Simulation time 175437821 ps
CPU time 4.16 seconds
Started Jun 06 12:27:38 PM PDT 24
Finished Jun 06 12:27:43 PM PDT 24
Peak memory 218228 kb
Host smart-e26d3d3c-b033-47ab-b13a-ccb4f791d1e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393536450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3393536450
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3973298117
Short name T461
Test name
Test status
Simulation time 138221251068 ps
CPU time 72.14 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 211100 kb
Host smart-a0b172fb-90f0-4c81-b4d7-3684cdeda373
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973298117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3973298117
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2305908753
Short name T99
Test name
Test status
Simulation time 1473491498 ps
CPU time 13.38 seconds
Started Jun 06 12:27:26 PM PDT 24
Finished Jun 06 12:27:41 PM PDT 24
Peak memory 210848 kb
Host smart-3f4c47be-0207-44e3-9c2b-661fa29947ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305908753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2305908753
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3612160331
Short name T394
Test name
Test status
Simulation time 377607158 ps
CPU time 6.69 seconds
Started Jun 06 12:27:24 PM PDT 24
Finished Jun 06 12:27:32 PM PDT 24
Peak memory 218880 kb
Host smart-c6b4586d-b122-4b9e-8701-db71f2eb544f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612160331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3612160331
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4236305359
Short name T392
Test name
Test status
Simulation time 2881578150 ps
CPU time 12.24 seconds
Started Jun 06 12:27:23 PM PDT 24
Finished Jun 06 12:27:36 PM PDT 24
Peak memory 219264 kb
Host smart-ef4b94e3-0086-416a-9bf9-9240cbf21745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236305359 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4236305359
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1623023742
Short name T406
Test name
Test status
Simulation time 1590030325 ps
CPU time 13.05 seconds
Started Jun 06 12:27:23 PM PDT 24
Finished Jun 06 12:27:37 PM PDT 24
Peak memory 210768 kb
Host smart-3f4514d9-699a-4534-ba67-6872573122fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623023742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1623023742
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1332900609
Short name T107
Test name
Test status
Simulation time 15218957896 ps
CPU time 72.17 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:28:35 PM PDT 24
Peak memory 210992 kb
Host smart-a6e44470-894f-4c77-b2d0-58ad741c2693
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332900609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1332900609
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2777178552
Short name T63
Test name
Test status
Simulation time 1081008408 ps
CPU time 10.46 seconds
Started Jun 06 12:27:20 PM PDT 24
Finished Jun 06 12:27:32 PM PDT 24
Peak memory 210916 kb
Host smart-063489cf-e42c-440e-b6c1-080dc09ca1a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777178552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2777178552
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2910401344
Short name T421
Test name
Test status
Simulation time 7511002318 ps
CPU time 16.67 seconds
Started Jun 06 12:27:35 PM PDT 24
Finished Jun 06 12:27:53 PM PDT 24
Peak memory 218748 kb
Host smart-8e834d7f-9ed8-4ad7-968b-0209da54a739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910401344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2910401344
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1668621620
Short name T113
Test name
Test status
Simulation time 4351171492 ps
CPU time 71.37 seconds
Started Jun 06 12:27:37 PM PDT 24
Finished Jun 06 12:28:49 PM PDT 24
Peak memory 219144 kb
Host smart-caa1f2a1-9f58-4def-ab26-14c1906d9ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668621620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1668621620
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4051461819
Short name T395
Test name
Test status
Simulation time 789553694 ps
CPU time 4.76 seconds
Started Jun 06 12:27:38 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 219060 kb
Host smart-6aec420b-d061-4cd1-a95e-8784dab54fd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051461819 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4051461819
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1153267476
Short name T399
Test name
Test status
Simulation time 347019923 ps
CPU time 6.39 seconds
Started Jun 06 12:27:27 PM PDT 24
Finished Jun 06 12:27:34 PM PDT 24
Peak memory 217780 kb
Host smart-f75886c9-ea5f-4136-855a-b04154f64073
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153267476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1153267476
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1276531813
Short name T98
Test name
Test status
Simulation time 5424290289 ps
CPU time 11.88 seconds
Started Jun 06 12:27:37 PM PDT 24
Finished Jun 06 12:27:50 PM PDT 24
Peak memory 219056 kb
Host smart-80c15b72-352f-46e8-8f42-8c6fbc94e1d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276531813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1276531813
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.656353980
Short name T384
Test name
Test status
Simulation time 3131060360 ps
CPU time 16.91 seconds
Started Jun 06 12:27:23 PM PDT 24
Finished Jun 06 12:27:41 PM PDT 24
Peak memory 215472 kb
Host smart-8cd87952-acee-4854-9d2b-fb8cac0befc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656353980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.656353980
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2998296290
Short name T419
Test name
Test status
Simulation time 535102966 ps
CPU time 38.74 seconds
Started Jun 06 12:27:38 PM PDT 24
Finished Jun 06 12:28:18 PM PDT 24
Peak memory 219028 kb
Host smart-c3001358-d9c8-41d9-aaed-ae91ab56091b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998296290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2998296290
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3277402291
Short name T418
Test name
Test status
Simulation time 326410182 ps
CPU time 4.53 seconds
Started Jun 06 12:27:35 PM PDT 24
Finished Jun 06 12:27:41 PM PDT 24
Peak memory 219020 kb
Host smart-40a45d7d-bde0-44d1-9aa2-037634d9adb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277402291 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3277402291
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.160948199
Short name T454
Test name
Test status
Simulation time 4122067242 ps
CPU time 15.57 seconds
Started Jun 06 12:27:35 PM PDT 24
Finished Jun 06 12:27:52 PM PDT 24
Peak memory 210788 kb
Host smart-0b3ef541-a5e3-4a3d-bf03-ade8930c89b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160948199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.160948199
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3245972610
Short name T433
Test name
Test status
Simulation time 5752724753 ps
CPU time 49.91 seconds
Started Jun 06 12:27:24 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 210944 kb
Host smart-40650a7c-4963-4ff3-b246-a478213b805a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245972610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3245972610
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.414780802
Short name T428
Test name
Test status
Simulation time 2945049556 ps
CPU time 13.12 seconds
Started Jun 06 12:27:35 PM PDT 24
Finished Jun 06 12:27:49 PM PDT 24
Peak memory 210964 kb
Host smart-55ed5c54-47c0-44c8-829d-0b123a91c135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414780802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.414780802
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4129317690
Short name T472
Test name
Test status
Simulation time 905660008 ps
CPU time 10.6 seconds
Started Jun 06 12:27:35 PM PDT 24
Finished Jun 06 12:27:47 PM PDT 24
Peak memory 218948 kb
Host smart-f2e49a73-c3b5-42f2-b618-36c1c98098a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129317690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4129317690
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2885686937
Short name T53
Test name
Test status
Simulation time 2223558600 ps
CPU time 77.97 seconds
Started Jun 06 12:27:27 PM PDT 24
Finished Jun 06 12:28:46 PM PDT 24
Peak memory 212444 kb
Host smart-01efddd5-0be9-4dbd-9256-d506507b64c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885686937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2885686937
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2410412658
Short name T403
Test name
Test status
Simulation time 122961301 ps
CPU time 5.49 seconds
Started Jun 06 12:27:36 PM PDT 24
Finished Jun 06 12:27:42 PM PDT 24
Peak memory 219084 kb
Host smart-0127c695-2acf-44d3-8360-aaab7dd25e05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410412658 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2410412658
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2012349380
Short name T388
Test name
Test status
Simulation time 87238682 ps
CPU time 4.12 seconds
Started Jun 06 12:27:34 PM PDT 24
Finished Jun 06 12:27:39 PM PDT 24
Peak memory 210852 kb
Host smart-e341882a-d522-4135-9e20-791694ce4b71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012349380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2012349380
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1147687185
Short name T83
Test name
Test status
Simulation time 2396948357 ps
CPU time 32.47 seconds
Started Jun 06 12:27:27 PM PDT 24
Finished Jun 06 12:28:00 PM PDT 24
Peak memory 210960 kb
Host smart-43ea982b-9cb6-4aa2-8902-74acc606ea8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147687185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1147687185
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3670916598
Short name T467
Test name
Test status
Simulation time 11132269983 ps
CPU time 18.91 seconds
Started Jun 06 12:27:37 PM PDT 24
Finished Jun 06 12:27:57 PM PDT 24
Peak memory 211244 kb
Host smart-4cb14d0c-f10a-4f6c-8146-df74760a9305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670916598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3670916598
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4196818103
Short name T390
Test name
Test status
Simulation time 333493410 ps
CPU time 6.18 seconds
Started Jun 06 12:27:26 PM PDT 24
Finished Jun 06 12:27:34 PM PDT 24
Peak memory 218900 kb
Host smart-b66f52c1-12e7-46c1-8dcc-f8868873990c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196818103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4196818103
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2833326193
Short name T112
Test name
Test status
Simulation time 283018129 ps
CPU time 37.9 seconds
Started Jun 06 12:27:38 PM PDT 24
Finished Jun 06 12:28:17 PM PDT 24
Peak memory 211952 kb
Host smart-2a088fe8-44a8-4c9a-a2e3-e74b5bff4cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833326193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2833326193
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.371989038
Short name T459
Test name
Test status
Simulation time 864723108 ps
CPU time 8.99 seconds
Started Jun 06 12:28:15 PM PDT 24
Finished Jun 06 12:28:25 PM PDT 24
Peak memory 218280 kb
Host smart-23d69bb7-cf07-43a8-96d7-daa97f2d57d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371989038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.371989038
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2223772997
Short name T385
Test name
Test status
Simulation time 303498598 ps
CPU time 6.1 seconds
Started Jun 06 12:26:26 PM PDT 24
Finished Jun 06 12:26:34 PM PDT 24
Peak memory 210608 kb
Host smart-ff5c044c-f867-4ad1-9df1-abc56f65d2b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223772997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2223772997
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.354222323
Short name T400
Test name
Test status
Simulation time 5818350086 ps
CPU time 14.12 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:35 PM PDT 24
Peak memory 217648 kb
Host smart-6d693712-fdd3-41d7-be2e-82429b35446e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354222323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.354222323
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4059962115
Short name T417
Test name
Test status
Simulation time 7509850721 ps
CPU time 15.45 seconds
Started Jun 06 12:28:27 PM PDT 24
Finished Jun 06 12:28:43 PM PDT 24
Peak memory 219148 kb
Host smart-fd8f2c90-b7c0-46d8-bcb1-8ce23782cdee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059962115 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4059962115
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2972930452
Short name T61
Test name
Test status
Simulation time 785438987 ps
CPU time 8.4 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:35 PM PDT 24
Peak memory 210448 kb
Host smart-cf80a6aa-7873-47fc-8e6d-9ba71092284c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972930452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2972930452
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2516164750
Short name T377
Test name
Test status
Simulation time 333865647 ps
CPU time 4.08 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:27:58 PM PDT 24
Peak memory 210100 kb
Host smart-d4f25b4f-613e-4b99-b395-07cf3966acbc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516164750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2516164750
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.894916484
Short name T468
Test name
Test status
Simulation time 8695252633 ps
CPU time 9.93 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:28:04 PM PDT 24
Peak memory 209544 kb
Host smart-bb9297cf-11a3-42af-9d93-a92ab6f92967
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894916484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
894916484
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.896234992
Short name T77
Test name
Test status
Simulation time 80742675232 ps
CPU time 64.33 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:28:59 PM PDT 24
Peak memory 209928 kb
Host smart-6931fa12-8948-4f6c-91f5-2758846fda9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896234992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.896234992
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1669381249
Short name T408
Test name
Test status
Simulation time 6609533439 ps
CPU time 6.15 seconds
Started Jun 06 12:26:26 PM PDT 24
Finished Jun 06 12:26:34 PM PDT 24
Peak memory 210596 kb
Host smart-b619f007-00dd-4d69-82fb-96b6c3d21569
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669381249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1669381249
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3592372658
Short name T382
Test name
Test status
Simulation time 2278515847 ps
CPU time 14.38 seconds
Started Jun 06 12:26:29 PM PDT 24
Finished Jun 06 12:26:45 PM PDT 24
Peak memory 215484 kb
Host smart-937e158a-f1f5-4247-840c-7b532c0739fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592372658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3592372658
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3978801214
Short name T434
Test name
Test status
Simulation time 4312427986 ps
CPU time 40.58 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:28:45 PM PDT 24
Peak memory 212180 kb
Host smart-356b8105-75b6-494c-bd38-6ae4e011f589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978801214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3978801214
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3533075834
Short name T401
Test name
Test status
Simulation time 554627200 ps
CPU time 4.23 seconds
Started Jun 06 12:26:18 PM PDT 24
Finished Jun 06 12:26:25 PM PDT 24
Peak memory 209508 kb
Host smart-33866c0b-990d-4355-88ba-bd49ec82e14e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533075834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3533075834
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1608197658
Short name T79
Test name
Test status
Simulation time 1557906294 ps
CPU time 16.18 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:39 PM PDT 24
Peak memory 209556 kb
Host smart-b22932bf-e7ac-4b58-957c-455b498c8848
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608197658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1608197658
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3061587266
Short name T458
Test name
Test status
Simulation time 1653705134 ps
CPU time 13.6 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:35 PM PDT 24
Peak memory 218716 kb
Host smart-8f69a36a-3c41-41cf-8922-dcda62f6ed00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061587266 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3061587266
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3800704711
Short name T449
Test name
Test status
Simulation time 4937165993 ps
CPU time 11.26 seconds
Started Jun 06 12:26:18 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 217128 kb
Host smart-f04b9bda-72b2-4c04-8626-9c808655d253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800704711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3800704711
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1750438685
Short name T407
Test name
Test status
Simulation time 1145724076 ps
CPU time 10.64 seconds
Started Jun 06 12:26:16 PM PDT 24
Finished Jun 06 12:26:27 PM PDT 24
Peak memory 210284 kb
Host smart-1eba18f1-5bc9-4877-8d4a-2e0e27ac04c1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750438685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1750438685
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3785361067
Short name T440
Test name
Test status
Simulation time 85627162 ps
CPU time 3.92 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:30 PM PDT 24
Peak memory 210184 kb
Host smart-07d0f2b7-5476-4484-bace-1c252902f9ce
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785361067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3785361067
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1126065363
Short name T64
Test name
Test status
Simulation time 7190446428 ps
CPU time 67.67 seconds
Started Jun 06 12:24:40 PM PDT 24
Finished Jun 06 12:25:48 PM PDT 24
Peak memory 210996 kb
Host smart-1ac1522c-f166-465a-bd32-87d8ad039b53
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126065363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1126065363
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1898242732
Short name T453
Test name
Test status
Simulation time 4754161992 ps
CPU time 12.7 seconds
Started Jun 06 12:24:21 PM PDT 24
Finished Jun 06 12:24:34 PM PDT 24
Peak memory 211220 kb
Host smart-dc0cacbb-37dd-40cc-8ac5-0d6623fdca97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898242732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1898242732
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2252716971
Short name T471
Test name
Test status
Simulation time 2926095772 ps
CPU time 14.02 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:35 PM PDT 24
Peak memory 218632 kb
Host smart-a563f2dc-7e16-4a5b-bef1-b21617e6a69d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252716971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2252716971
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1356427613
Short name T118
Test name
Test status
Simulation time 602923034 ps
CPU time 35.2 seconds
Started Jun 06 12:26:15 PM PDT 24
Finished Jun 06 12:26:51 PM PDT 24
Peak memory 217880 kb
Host smart-3923860f-2083-40dd-845b-cbc9672050ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356427613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1356427613
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3149323861
Short name T62
Test name
Test status
Simulation time 15551315804 ps
CPU time 15.31 seconds
Started Jun 06 12:26:35 PM PDT 24
Finished Jun 06 12:26:52 PM PDT 24
Peak memory 218676 kb
Host smart-1c653e0a-6181-469a-9953-9ef145aaadcd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149323861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3149323861
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.463184948
Short name T437
Test name
Test status
Simulation time 9688411921 ps
CPU time 15.78 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:28:07 PM PDT 24
Peak memory 210740 kb
Host smart-712fa4a9-6e72-4e9f-8dd2-73d206ae35ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463184948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.463184948
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3643303288
Short name T424
Test name
Test status
Simulation time 3175809749 ps
CPU time 14.51 seconds
Started Jun 06 12:24:00 PM PDT 24
Finished Jun 06 12:24:16 PM PDT 24
Peak memory 210940 kb
Host smart-09fb1567-1481-40dc-a8bd-41abbd6a2612
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643303288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3643303288
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2538104649
Short name T469
Test name
Test status
Simulation time 992946288 ps
CPU time 6.4 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:29 PM PDT 24
Peak memory 210208 kb
Host smart-3aa85c03-76bc-4c82-851d-bcfcf853fbca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538104649 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2538104649
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1746760409
Short name T430
Test name
Test status
Simulation time 1321505482 ps
CPU time 10.2 seconds
Started Jun 06 12:26:33 PM PDT 24
Finished Jun 06 12:26:45 PM PDT 24
Peak memory 218120 kb
Host smart-30a9b9fe-5fd4-424e-9a8f-f55d0f741abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746760409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1746760409
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2461079533
Short name T374
Test name
Test status
Simulation time 2536879945 ps
CPU time 11.07 seconds
Started Jun 06 12:26:17 PM PDT 24
Finished Jun 06 12:26:30 PM PDT 24
Peak memory 208912 kb
Host smart-1f628f3b-fcbf-40d8-bad0-f8db70a5e720
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461079533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2461079533
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3862143610
Short name T431
Test name
Test status
Simulation time 261953699 ps
CPU time 4.71 seconds
Started Jun 06 12:27:56 PM PDT 24
Finished Jun 06 12:28:02 PM PDT 24
Peak memory 210540 kb
Host smart-b194762d-99be-4507-a0c4-e944e45ff98c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862143610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3862143610
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1254438405
Short name T87
Test name
Test status
Simulation time 5853800486 ps
CPU time 48.81 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:27:10 PM PDT 24
Peak memory 209788 kb
Host smart-491ca990-cc17-4df5-86d2-be9556bac64f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254438405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1254438405
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2499098366
Short name T101
Test name
Test status
Simulation time 85400677 ps
CPU time 4.32 seconds
Started Jun 06 12:26:35 PM PDT 24
Finished Jun 06 12:26:41 PM PDT 24
Peak memory 210500 kb
Host smart-6f896cd9-836b-4bc1-ae93-6935b4142848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499098366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2499098366
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.171447309
Short name T378
Test name
Test status
Simulation time 1426253443 ps
CPU time 14.5 seconds
Started Jun 06 12:26:32 PM PDT 24
Finished Jun 06 12:26:48 PM PDT 24
Peak memory 218920 kb
Host smart-a713ffd5-c23e-4400-baaa-048d2d8f7f60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171447309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.171447309
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3359382711
Short name T110
Test name
Test status
Simulation time 1892868395 ps
CPU time 67.32 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:27:30 PM PDT 24
Peak memory 217880 kb
Host smart-e35cd2be-c125-41df-b831-446bddf0481f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359382711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3359382711
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1545901862
Short name T55
Test name
Test status
Simulation time 1655219737 ps
CPU time 13.25 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:13 PM PDT 24
Peak memory 218004 kb
Host smart-fdee4773-1d1a-429a-bb35-d5b276de3971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545901862 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1545901862
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.122442767
Short name T410
Test name
Test status
Simulation time 474580212 ps
CPU time 7.1 seconds
Started Jun 06 12:26:45 PM PDT 24
Finished Jun 06 12:26:52 PM PDT 24
Peak memory 217292 kb
Host smart-e88bf995-9b6e-4501-aa46-0ac693363690
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122442767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.122442767
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.142114173
Short name T82
Test name
Test status
Simulation time 1986054675 ps
CPU time 26.59 seconds
Started Jun 06 12:28:17 PM PDT 24
Finished Jun 06 12:28:45 PM PDT 24
Peak memory 210040 kb
Host smart-c99654af-e6ca-46c5-8a63-22688f626ce8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142114173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.142114173
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.762024340
Short name T65
Test name
Test status
Simulation time 493109740 ps
CPU time 7.31 seconds
Started Jun 06 12:27:54 PM PDT 24
Finished Jun 06 12:28:03 PM PDT 24
Peak memory 210104 kb
Host smart-02e6e78b-b33b-48fd-bc33-9ae1959fc91a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762024340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.762024340
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2855801723
Short name T393
Test name
Test status
Simulation time 8172800763 ps
CPU time 19.04 seconds
Started Jun 06 12:25:19 PM PDT 24
Finished Jun 06 12:25:39 PM PDT 24
Peak memory 219056 kb
Host smart-09d0ce23-3eed-4015-9563-709e9de2fd74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855801723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2855801723
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4217719381
Short name T114
Test name
Test status
Simulation time 288726830 ps
CPU time 69.2 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:29:09 PM PDT 24
Peak memory 211484 kb
Host smart-841680ba-3558-4cea-a26d-a901c7dd2e04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217719381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4217719381
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3168076139
Short name T398
Test name
Test status
Simulation time 1663122662 ps
CPU time 13.69 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:28:07 PM PDT 24
Peak memory 211788 kb
Host smart-012d521a-5ab0-4df5-9696-3fdcb72a3abd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168076139 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3168076139
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.801973352
Short name T411
Test name
Test status
Simulation time 3807998832 ps
CPU time 11.35 seconds
Started Jun 06 12:26:45 PM PDT 24
Finished Jun 06 12:26:57 PM PDT 24
Peak memory 218780 kb
Host smart-9a32182c-bc66-47b5-97e1-d2f171bef9fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801973352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.801973352
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1964327561
Short name T56
Test name
Test status
Simulation time 12322374721 ps
CPU time 93.67 seconds
Started Jun 06 12:28:09 PM PDT 24
Finished Jun 06 12:29:44 PM PDT 24
Peak memory 218060 kb
Host smart-0cc1d83b-e76b-489e-8a6f-30aa23563108
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964327561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1964327561
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.483337611
Short name T427
Test name
Test status
Simulation time 4312474684 ps
CPU time 10.64 seconds
Started Jun 06 12:26:35 PM PDT 24
Finished Jun 06 12:26:47 PM PDT 24
Peak memory 219144 kb
Host smart-c9abf78e-84df-4977-9153-0dbfc8bdfb3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483337611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.483337611
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3191101368
Short name T416
Test name
Test status
Simulation time 543113314 ps
CPU time 8.78 seconds
Started Jun 06 12:27:58 PM PDT 24
Finished Jun 06 12:28:09 PM PDT 24
Peak memory 218568 kb
Host smart-31ebfc41-725d-45d5-8d43-abeb4b57d8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191101368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3191101368
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.689330369
Short name T412
Test name
Test status
Simulation time 12689126577 ps
CPU time 14.5 seconds
Started Jun 06 12:27:06 PM PDT 24
Finished Jun 06 12:27:21 PM PDT 24
Peak memory 219060 kb
Host smart-da92ccf3-8ca3-4893-a7d0-8e8c174aefee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689330369 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.689330369
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1883414322
Short name T80
Test name
Test status
Simulation time 2626934394 ps
CPU time 11.85 seconds
Started Jun 06 12:27:05 PM PDT 24
Finished Jun 06 12:27:18 PM PDT 24
Peak memory 210896 kb
Host smart-83e9a2ea-6df2-4b08-abda-a1696c8b2779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883414322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1883414322
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3318324730
Short name T85
Test name
Test status
Simulation time 385329390 ps
CPU time 18.21 seconds
Started Jun 06 12:25:35 PM PDT 24
Finished Jun 06 12:25:54 PM PDT 24
Peak memory 209192 kb
Host smart-74ed2b3b-dea1-4f9d-90b9-c18cb9f576a6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318324730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3318324730
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1506409166
Short name T441
Test name
Test status
Simulation time 174854630 ps
CPU time 4.09 seconds
Started Jun 06 12:28:21 PM PDT 24
Finished Jun 06 12:28:27 PM PDT 24
Peak memory 210900 kb
Host smart-3cba43d6-fadc-43ee-887d-2abc9a8446a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506409166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1506409166
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1188891186
Short name T387
Test name
Test status
Simulation time 7246591645 ps
CPU time 18.4 seconds
Started Jun 06 12:28:21 PM PDT 24
Finished Jun 06 12:28:40 PM PDT 24
Peak memory 219004 kb
Host smart-5ce08020-45ff-4c5a-af13-b55624be4d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188891186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1188891186
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3988913448
Short name T117
Test name
Test status
Simulation time 198189246 ps
CPU time 36.65 seconds
Started Jun 06 12:28:21 PM PDT 24
Finished Jun 06 12:28:58 PM PDT 24
Peak memory 212356 kb
Host smart-37394565-c3c4-4d92-849c-f5909ad1a199
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988913448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3988913448
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1346137043
Short name T426
Test name
Test status
Simulation time 3813823278 ps
CPU time 10.3 seconds
Started Jun 06 12:26:26 PM PDT 24
Finished Jun 06 12:26:38 PM PDT 24
Peak memory 218888 kb
Host smart-863d6888-c843-4e85-bf3c-848f5c46af9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346137043 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1346137043
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3538096448
Short name T67
Test name
Test status
Simulation time 25080597039 ps
CPU time 16.04 seconds
Started Jun 06 12:23:44 PM PDT 24
Finished Jun 06 12:24:01 PM PDT 24
Peak memory 219108 kb
Host smart-80c14aa4-6908-41cc-acb6-f3313c6db72c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538096448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3538096448
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.396352213
Short name T76
Test name
Test status
Simulation time 8594190759 ps
CPU time 72.52 seconds
Started Jun 06 12:27:34 PM PDT 24
Finished Jun 06 12:28:47 PM PDT 24
Peak memory 210980 kb
Host smart-c67edfc9-1c60-491b-a206-b17d5d3f9b07
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396352213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.396352213
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.508206208
Short name T451
Test name
Test status
Simulation time 4060975751 ps
CPU time 15.63 seconds
Started Jun 06 12:22:32 PM PDT 24
Finished Jun 06 12:22:48 PM PDT 24
Peak memory 218948 kb
Host smart-3f6fa977-1cde-459e-b9d5-fde60ac2e086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508206208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.508206208
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2954697162
Short name T436
Test name
Test status
Simulation time 648614667 ps
CPU time 11.97 seconds
Started Jun 06 12:26:29 PM PDT 24
Finished Jun 06 12:26:42 PM PDT 24
Peak memory 214692 kb
Host smart-84105ff1-37c6-4c81-b159-9e1f746bcfcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954697162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2954697162
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3287343152
Short name T109
Test name
Test status
Simulation time 11345836617 ps
CPU time 75.82 seconds
Started Jun 06 12:26:29 PM PDT 24
Finished Jun 06 12:27:46 PM PDT 24
Peak memory 217652 kb
Host smart-1c9eec2d-168b-4fbb-ad5d-cf7812630494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287343152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3287343152
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2349509844
Short name T397
Test name
Test status
Simulation time 1339047770 ps
CPU time 13.44 seconds
Started Jun 06 12:26:30 PM PDT 24
Finished Jun 06 12:26:46 PM PDT 24
Peak memory 218924 kb
Host smart-34e59324-f24f-4b31-aad4-e53519b75026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349509844 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2349509844
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.859316498
Short name T470
Test name
Test status
Simulation time 1349794676 ps
CPU time 11.9 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:26:38 PM PDT 24
Peak memory 217640 kb
Host smart-21bf4541-011c-4936-8641-4e57b82c82ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859316498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.859316498
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.266890081
Short name T84
Test name
Test status
Simulation time 98729632681 ps
CPU time 87.76 seconds
Started Jun 06 12:26:29 PM PDT 24
Finished Jun 06 12:27:58 PM PDT 24
Peak memory 210228 kb
Host smart-022eaa29-e214-4dff-9b8e-dd830bb627fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266890081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.266890081
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1934816932
Short name T460
Test name
Test status
Simulation time 9089880204 ps
CPU time 15.7 seconds
Started Jun 06 12:26:29 PM PDT 24
Finished Jun 06 12:26:46 PM PDT 24
Peak memory 211044 kb
Host smart-154ac530-96d9-4f7e-a22c-04c4913851b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934816932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1934816932
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1057868401
Short name T452
Test name
Test status
Simulation time 1679712426 ps
CPU time 12.82 seconds
Started Jun 06 12:23:30 PM PDT 24
Finished Jun 06 12:23:43 PM PDT 24
Peak memory 219312 kb
Host smart-6ea9350f-a615-4f97-a3a6-b05739fb0e41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057868401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1057868401
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1421496901
Short name T115
Test name
Test status
Simulation time 2942446711 ps
CPU time 72.31 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:27:39 PM PDT 24
Peak memory 217832 kb
Host smart-57fa5a75-aa1f-4eec-a2c0-cef31c4c5e18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421496901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1421496901
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2882971432
Short name T355
Test name
Test status
Simulation time 85560629 ps
CPU time 4.22 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 210472 kb
Host smart-83eb181b-f8ef-4ccb-a173-122c6a73e887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882971432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2882971432
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1900324726
Short name T247
Test name
Test status
Simulation time 6388887283 ps
CPU time 27.81 seconds
Started Jun 06 12:27:10 PM PDT 24
Finished Jun 06 12:27:39 PM PDT 24
Peak memory 212260 kb
Host smart-ea796bcb-509b-4c69-9b73-3e560031bfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900324726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1900324726
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.492898557
Short name T106
Test name
Test status
Simulation time 182635118 ps
CPU time 5.62 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:26 PM PDT 24
Peak memory 209848 kb
Host smart-f01a343e-9ea5-48aa-be27-603c9868ff57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492898557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.492898557
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.862817736
Short name T25
Test name
Test status
Simulation time 4002793267 ps
CPU time 57.37 seconds
Started Jun 06 12:26:23 PM PDT 24
Finished Jun 06 12:27:23 PM PDT 24
Peak memory 232340 kb
Host smart-6aff4582-270d-4116-8d97-cda8c85527fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862817736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.862817736
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4123136560
Short name T333
Test name
Test status
Simulation time 3852535372 ps
CPU time 33.24 seconds
Started Jun 06 12:23:58 PM PDT 24
Finished Jun 06 12:24:32 PM PDT 24
Peak memory 213180 kb
Host smart-fe8dd797-daa7-405e-b670-6d57ecd5969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123136560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4123136560
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1354515850
Short name T258
Test name
Test status
Simulation time 7202395525 ps
CPU time 62.09 seconds
Started Jun 06 12:27:10 PM PDT 24
Finished Jun 06 12:28:13 PM PDT 24
Peak memory 213296 kb
Host smart-3c72c1d4-ee0e-4816-9831-d88d51373930
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354515850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1354515850
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2537203480
Short name T298
Test name
Test status
Simulation time 1366934955 ps
CPU time 12.44 seconds
Started Jun 06 12:26:05 PM PDT 24
Finished Jun 06 12:26:19 PM PDT 24
Peak memory 209132 kb
Host smart-6d9ca95d-d700-4302-9e5d-556d0a21adc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537203480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2537203480
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3446614550
Short name T185
Test name
Test status
Simulation time 176272310428 ps
CPU time 168.12 seconds
Started Jun 06 12:24:33 PM PDT 24
Finished Jun 06 12:27:21 PM PDT 24
Peak memory 235936 kb
Host smart-94bb95d8-e40c-412d-a3eb-be869b046c94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446614550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3446614550
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1870113405
Short name T372
Test name
Test status
Simulation time 3452652200 ps
CPU time 19.46 seconds
Started Jun 06 12:25:43 PM PDT 24
Finished Jun 06 12:26:03 PM PDT 24
Peak memory 211324 kb
Host smart-da26dacf-ef3f-4776-b14d-e5c7bba1d39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870113405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1870113405
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4000971117
Short name T310
Test name
Test status
Simulation time 2067861314 ps
CPU time 16.39 seconds
Started Jun 06 12:26:27 PM PDT 24
Finished Jun 06 12:26:45 PM PDT 24
Peak memory 210788 kb
Host smart-b5d39362-6283-468f-8097-28d18dc2c66e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4000971117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4000971117
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.609113541
Short name T17
Test name
Test status
Simulation time 767219762 ps
CPU time 96.08 seconds
Started Jun 06 12:24:00 PM PDT 24
Finished Jun 06 12:25:37 PM PDT 24
Peak memory 235024 kb
Host smart-bf4c9490-95de-40f0-b412-9e0563098475
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609113541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.609113541
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2919191038
Short name T215
Test name
Test status
Simulation time 3032213384 ps
CPU time 31.93 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:53 PM PDT 24
Peak memory 211996 kb
Host smart-4cf1f62a-34d9-49ed-9469-15d8e871924e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919191038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2919191038
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1607476280
Short name T315
Test name
Test status
Simulation time 17454399957 ps
CPU time 34.56 seconds
Started Jun 06 12:22:13 PM PDT 24
Finished Jun 06 12:22:48 PM PDT 24
Peak memory 214724 kb
Host smart-1f0d8364-efa3-46ae-a919-da28a2dc3a9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607476280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1607476280
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3223652267
Short name T51
Test name
Test status
Simulation time 7603717679 ps
CPU time 869.21 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:42:24 PM PDT 24
Peak memory 218824 kb
Host smart-720e21be-44b6-43e7-9a1a-0232eb771668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223652267 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3223652267
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3710551008
Short name T271
Test name
Test status
Simulation time 947905455 ps
CPU time 10.12 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:28:04 PM PDT 24
Peak memory 209900 kb
Host smart-08657767-b825-447d-b400-8cc10e541648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710551008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3710551008
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2194667443
Short name T194
Test name
Test status
Simulation time 11081078809 ps
CPU time 201.26 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:31:16 PM PDT 24
Peak memory 228020 kb
Host smart-13484fe2-017e-4d7b-9e58-8e9ce69f07ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194667443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2194667443
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.698891435
Short name T27
Test name
Test status
Simulation time 3223801105 ps
CPU time 29.27 seconds
Started Jun 06 12:26:18 PM PDT 24
Finished Jun 06 12:26:50 PM PDT 24
Peak memory 210640 kb
Host smart-cd1b6c6a-85c5-4512-8f80-592f1868ba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698891435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.698891435
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1943602626
Short name T210
Test name
Test status
Simulation time 3120465441 ps
CPU time 13.87 seconds
Started Jun 06 12:27:58 PM PDT 24
Finished Jun 06 12:28:14 PM PDT 24
Peak memory 211004 kb
Host smart-8cd7bb90-11ea-44ca-b3b7-8f7963b4c2df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943602626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1943602626
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3433657101
Short name T316
Test name
Test status
Simulation time 191208235 ps
CPU time 9.99 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:26:36 PM PDT 24
Peak memory 212984 kb
Host smart-3cad9aca-ce8b-4d7f-b847-0365473426c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433657101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3433657101
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.453907591
Short name T43
Test name
Test status
Simulation time 20675143811 ps
CPU time 57.23 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:27:25 PM PDT 24
Peak memory 218772 kb
Host smart-dea39957-00c9-461a-9b5b-77bc563334b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453907591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.453907591
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1165742829
Short name T246
Test name
Test status
Simulation time 1550554657 ps
CPU time 13.27 seconds
Started Jun 06 12:27:58 PM PDT 24
Finished Jun 06 12:28:14 PM PDT 24
Peak memory 210468 kb
Host smart-06e4b1cf-ba9c-4d2c-a9b9-55ca78e5e851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165742829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1165742829
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1023487441
Short name T5
Test name
Test status
Simulation time 14587044801 ps
CPU time 98.24 seconds
Started Jun 06 12:27:58 PM PDT 24
Finished Jun 06 12:29:39 PM PDT 24
Peak memory 236204 kb
Host smart-a68226c6-5f9d-4308-9458-612e50244424
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023487441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1023487441
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2656409564
Short name T201
Test name
Test status
Simulation time 435090749 ps
CPU time 11.86 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:39 PM PDT 24
Peak memory 211488 kb
Host smart-b59b5962-5187-4c54-b059-45b62af11d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656409564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2656409564
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.246941096
Short name T226
Test name
Test status
Simulation time 27645794590 ps
CPU time 13.8 seconds
Started Jun 06 12:27:58 PM PDT 24
Finished Jun 06 12:28:14 PM PDT 24
Peak memory 210768 kb
Host smart-c5ffa0eb-752a-4ae0-bad7-01c7b41432f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246941096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.246941096
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.978179789
Short name T8
Test name
Test status
Simulation time 21383147416 ps
CPU time 35.78 seconds
Started Jun 06 12:26:45 PM PDT 24
Finished Jun 06 12:27:21 PM PDT 24
Peak memory 213748 kb
Host smart-6f5a7aaa-5ef9-444a-8e78-86ddc2b4e4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978179789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.978179789
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2051011256
Short name T354
Test name
Test status
Simulation time 5826637853 ps
CPU time 35.89 seconds
Started Jun 06 12:27:59 PM PDT 24
Finished Jun 06 12:28:37 PM PDT 24
Peak memory 213788 kb
Host smart-7d0baa93-4069-4196-ae68-0fdf3f72abca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051011256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2051011256
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2353209696
Short name T350
Test name
Test status
Simulation time 63125270375 ps
CPU time 557.22 seconds
Started Jun 06 12:26:37 PM PDT 24
Finished Jun 06 12:35:56 PM PDT 24
Peak memory 235568 kb
Host smart-e2d1a899-5de8-4fb5-b04c-676535b83014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353209696 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2353209696
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3449109163
Short name T288
Test name
Test status
Simulation time 2761819361 ps
CPU time 14.63 seconds
Started Jun 06 12:27:34 PM PDT 24
Finished Jun 06 12:27:49 PM PDT 24
Peak memory 210768 kb
Host smart-75a59b9f-dd78-4a66-96f5-d5ca0517caf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449109163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3449109163
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1300328221
Short name T338
Test name
Test status
Simulation time 8674507673 ps
CPU time 132.3 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:30:04 PM PDT 24
Peak memory 236764 kb
Host smart-d02fb201-6bee-44c6-bc80-254368687796
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300328221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1300328221
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3802435468
Short name T214
Test name
Test status
Simulation time 8412703746 ps
CPU time 13.25 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:28:22 PM PDT 24
Peak memory 209452 kb
Host smart-f29ca909-7b45-4460-b39e-3b62bf4620b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3802435468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3802435468
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3980060196
Short name T176
Test name
Test status
Simulation time 12563808309 ps
CPU time 27.58 seconds
Started Jun 06 12:28:02 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 213004 kb
Host smart-b68e1609-2249-4c96-8c7a-1030ee0f2b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980060196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3980060196
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2972682350
Short name T105
Test name
Test status
Simulation time 471862721 ps
CPU time 7.27 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:28:16 PM PDT 24
Peak memory 210832 kb
Host smart-82ae442c-02f2-4fce-92b8-d620f77c601d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972682350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2972682350
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3439212549
Short name T268
Test name
Test status
Simulation time 2615908274 ps
CPU time 8.51 seconds
Started Jun 06 12:27:45 PM PDT 24
Finished Jun 06 12:27:56 PM PDT 24
Peak memory 209116 kb
Host smart-6f3cff97-f180-4efd-a3dd-cc773a276c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439212549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3439212549
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3393762256
Short name T163
Test name
Test status
Simulation time 2663592377 ps
CPU time 79.97 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:29:12 PM PDT 24
Peak memory 227432 kb
Host smart-79c166d0-3ec5-4729-aab2-8209f572c50e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393762256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3393762256
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3729110640
Short name T266
Test name
Test status
Simulation time 136145360 ps
CPU time 5.54 seconds
Started Jun 06 12:27:34 PM PDT 24
Finished Jun 06 12:27:41 PM PDT 24
Peak memory 210896 kb
Host smart-fa858d03-2a91-44ec-a0a2-ed5cb4b39e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729110640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3729110640
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2086493102
Short name T249
Test name
Test status
Simulation time 3682025102 ps
CPU time 35.23 seconds
Started Jun 06 12:28:09 PM PDT 24
Finished Jun 06 12:28:45 PM PDT 24
Peak memory 213164 kb
Host smart-c400567b-5137-4667-87e8-8db3d8af4ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086493102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2086493102
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4103354851
Short name T125
Test name
Test status
Simulation time 601178842 ps
CPU time 10.23 seconds
Started Jun 06 12:28:21 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 210684 kb
Host smart-c2487013-abaa-41b2-b1a1-7789b00bad7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103354851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4103354851
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2817366572
Short name T159
Test name
Test status
Simulation time 2905059755 ps
CPU time 8.96 seconds
Started Jun 06 12:22:58 PM PDT 24
Finished Jun 06 12:23:07 PM PDT 24
Peak memory 210796 kb
Host smart-b2861224-4a9a-4036-b319-c4b2a96cabc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817366572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2817366572
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.630934789
Short name T39
Test name
Test status
Simulation time 103081126934 ps
CPU time 479.84 seconds
Started Jun 06 12:23:09 PM PDT 24
Finished Jun 06 12:31:10 PM PDT 24
Peak memory 213552 kb
Host smart-9b3e9fa8-30c6-48da-889c-0440ca2ee6a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630934789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.630934789
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2592606122
Short name T368
Test name
Test status
Simulation time 38733732356 ps
CPU time 34.38 seconds
Started Jun 06 12:27:46 PM PDT 24
Finished Jun 06 12:28:22 PM PDT 24
Peak memory 211688 kb
Host smart-66d4aa85-ff98-4b69-b6b7-435b4dfa7a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592606122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2592606122
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.128473236
Short name T340
Test name
Test status
Simulation time 8437752913 ps
CPU time 17.65 seconds
Started Jun 06 12:27:46 PM PDT 24
Finished Jun 06 12:28:05 PM PDT 24
Peak memory 210320 kb
Host smart-f1654a60-a8e9-4f4b-a979-fdbeaddf7846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128473236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.128473236
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.624522947
Short name T142
Test name
Test status
Simulation time 16082203929 ps
CPU time 29.19 seconds
Started Jun 06 12:22:50 PM PDT 24
Finished Jun 06 12:23:19 PM PDT 24
Peak memory 213816 kb
Host smart-dbf8e100-fda2-4bd1-af49-12d2ce846bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624522947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.624522947
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3195359167
Short name T174
Test name
Test status
Simulation time 57078820346 ps
CPU time 139.68 seconds
Started Jun 06 12:27:45 PM PDT 24
Finished Jun 06 12:30:07 PM PDT 24
Peak memory 214676 kb
Host smart-ecc35783-3782-4d59-b2a7-27c6201a98d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195359167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3195359167
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.805583414
Short name T276
Test name
Test status
Simulation time 434527237 ps
CPU time 6.62 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:28:02 PM PDT 24
Peak memory 210432 kb
Host smart-e01fc3c2-00f7-4283-9b3b-51653800c6b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805583414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.805583414
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.588964788
Short name T359
Test name
Test status
Simulation time 85864434526 ps
CPU time 289 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:32:44 PM PDT 24
Peak memory 237120 kb
Host smart-e3f147e0-9f94-47bf-b4af-115de669ac23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588964788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.588964788
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2449568226
Short name T296
Test name
Test status
Simulation time 15692877394 ps
CPU time 21.43 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:28:16 PM PDT 24
Peak memory 210024 kb
Host smart-8afc63d2-717f-4c8d-a57a-4707205227b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449568226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2449568226
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.931698837
Short name T346
Test name
Test status
Simulation time 4288191004 ps
CPU time 12.52 seconds
Started Jun 06 12:23:01 PM PDT 24
Finished Jun 06 12:23:14 PM PDT 24
Peak memory 210972 kb
Host smart-4a4c2ed3-dea5-4997-9d7e-c313c9184335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931698837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.931698837
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2610003329
Short name T363
Test name
Test status
Simulation time 20699113338 ps
CPU time 21.51 seconds
Started Jun 06 12:27:45 PM PDT 24
Finished Jun 06 12:28:09 PM PDT 24
Peak memory 212600 kb
Host smart-2997b5d6-1a69-4e87-8993-2d9a91692356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610003329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2610003329
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4244686482
Short name T351
Test name
Test status
Simulation time 1902518832 ps
CPU time 34.73 seconds
Started Jun 06 12:27:45 PM PDT 24
Finished Jun 06 12:28:22 PM PDT 24
Peak memory 214220 kb
Host smart-d6d4938a-15bf-49b2-818b-8c90221570a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244686482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4244686482
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.480534314
Short name T281
Test name
Test status
Simulation time 1913899790 ps
CPU time 15.32 seconds
Started Jun 06 12:28:15 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 210424 kb
Host smart-c8996fec-b089-44a4-9a60-badb2b68b230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480534314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.480534314
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3707531274
Short name T172
Test name
Test status
Simulation time 31317053897 ps
CPU time 30.37 seconds
Started Jun 06 12:26:30 PM PDT 24
Finished Jun 06 12:27:02 PM PDT 24
Peak memory 211620 kb
Host smart-96dd338b-83fe-4bdf-ac50-acb9477e2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707531274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3707531274
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3124574140
Short name T319
Test name
Test status
Simulation time 3027697707 ps
CPU time 10.41 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:33 PM PDT 24
Peak memory 210032 kb
Host smart-d4e04f50-d9ff-4fcb-a0d8-e4a53061e5c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124574140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3124574140
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1749289681
Short name T135
Test name
Test status
Simulation time 1862343355 ps
CPU time 21.46 seconds
Started Jun 06 12:25:22 PM PDT 24
Finished Jun 06 12:25:44 PM PDT 24
Peak memory 213184 kb
Host smart-e6785788-e105-4dd7-9b8e-ece10ee2359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749289681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1749289681
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1628041782
Short name T240
Test name
Test status
Simulation time 5542317469 ps
CPU time 29.63 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:28:24 PM PDT 24
Peak memory 213760 kb
Host smart-124f14a0-ef38-4328-8e40-497e0583c9f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628041782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1628041782
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2066931629
Short name T343
Test name
Test status
Simulation time 332839610 ps
CPU time 4.36 seconds
Started Jun 06 12:24:39 PM PDT 24
Finished Jun 06 12:24:44 PM PDT 24
Peak memory 211056 kb
Host smart-bb6e14d0-379a-49fe-9398-f4323f8b5e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066931629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2066931629
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2813924769
Short name T192
Test name
Test status
Simulation time 82315036001 ps
CPU time 177.08 seconds
Started Jun 06 12:26:01 PM PDT 24
Finished Jun 06 12:28:59 PM PDT 24
Peak memory 224728 kb
Host smart-20ed6433-c318-4aed-a5c4-f7b06ab32c87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813924769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2813924769
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1875478882
Short name T188
Test name
Test status
Simulation time 1026383421 ps
CPU time 15.44 seconds
Started Jun 06 12:27:13 PM PDT 24
Finished Jun 06 12:27:29 PM PDT 24
Peak memory 211720 kb
Host smart-f344f2e2-b3bc-4802-ba04-30924fb3bcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875478882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1875478882
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.522548379
Short name T28
Test name
Test status
Simulation time 268193369 ps
CPU time 6.5 seconds
Started Jun 06 12:24:23 PM PDT 24
Finished Jun 06 12:24:30 PM PDT 24
Peak memory 211224 kb
Host smart-38c81eda-439b-45d0-8075-691553e5bfe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522548379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.522548379
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3649503419
Short name T337
Test name
Test status
Simulation time 27298671849 ps
CPU time 35.68 seconds
Started Jun 06 12:28:14 PM PDT 24
Finished Jun 06 12:28:52 PM PDT 24
Peak memory 211964 kb
Host smart-a3ed48dc-d49c-4ceb-b522-9700480e6424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649503419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3649503419
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1264503350
Short name T70
Test name
Test status
Simulation time 8388413129 ps
CPU time 79.46 seconds
Started Jun 06 12:23:26 PM PDT 24
Finished Jun 06 12:24:46 PM PDT 24
Peak memory 216644 kb
Host smart-f8233324-e650-4235-8b5e-376d05e3d92c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264503350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1264503350
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3773574012
Short name T297
Test name
Test status
Simulation time 70485557079 ps
CPU time 8233.97 seconds
Started Jun 06 12:25:45 PM PDT 24
Finished Jun 06 02:43:00 PM PDT 24
Peak memory 235344 kb
Host smart-36f7be8b-0869-4650-8fbe-6f67889c7b39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773574012 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3773574012
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1081491544
Short name T251
Test name
Test status
Simulation time 1501940603 ps
CPU time 12.92 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:28:06 PM PDT 24
Peak memory 210456 kb
Host smart-3a6585e4-9abb-4ae3-b175-e895be6a7712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081491544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1081491544
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.261181260
Short name T200
Test name
Test status
Simulation time 3074132369 ps
CPU time 58.66 seconds
Started Jun 06 12:26:01 PM PDT 24
Finished Jun 06 12:27:00 PM PDT 24
Peak memory 236704 kb
Host smart-5cb273bf-3136-4c38-ac30-f0691a952a4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261181260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.261181260
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3540665544
Short name T357
Test name
Test status
Simulation time 9541015426 ps
CPU time 20.57 seconds
Started Jun 06 12:27:11 PM PDT 24
Finished Jun 06 12:27:33 PM PDT 24
Peak memory 211912 kb
Host smart-5026d269-d005-48cd-a8a4-73617ab9db16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540665544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3540665544
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1420481994
Short name T209
Test name
Test status
Simulation time 992055002 ps
CPU time 9.73 seconds
Started Jun 06 12:26:37 PM PDT 24
Finished Jun 06 12:26:48 PM PDT 24
Peak memory 210752 kb
Host smart-c1f056df-9101-4bc1-a874-f2a5b8589435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420481994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1420481994
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.972465007
Short name T3
Test name
Test status
Simulation time 6718552751 ps
CPU time 29.19 seconds
Started Jun 06 12:26:35 PM PDT 24
Finished Jun 06 12:27:06 PM PDT 24
Peak memory 213896 kb
Host smart-21abb1a0-6c2e-48ab-8971-41184cc8104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972465007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.972465007
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4221053767
Short name T290
Test name
Test status
Simulation time 14024972881 ps
CPU time 49.12 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:27:10 PM PDT 24
Peak memory 215616 kb
Host smart-d502be0a-5b70-4cd6-b7be-258ea4631cb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221053767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4221053767
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.833829231
Short name T256
Test name
Test status
Simulation time 12429678188 ps
CPU time 111.91 seconds
Started Jun 06 12:25:33 PM PDT 24
Finished Jun 06 12:27:26 PM PDT 24
Peak memory 229980 kb
Host smart-e2825583-13c9-4474-863b-4ab9feae72d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833829231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.833829231
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3991169685
Short name T137
Test name
Test status
Simulation time 10832272855 ps
CPU time 25.68 seconds
Started Jun 06 12:25:33 PM PDT 24
Finished Jun 06 12:26:00 PM PDT 24
Peak memory 209772 kb
Host smart-a8e46af9-fc64-45de-a4fa-5e171919ced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991169685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3991169685
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2596348825
Short name T96
Test name
Test status
Simulation time 7854024697 ps
CPU time 17.02 seconds
Started Jun 06 12:27:15 PM PDT 24
Finished Jun 06 12:27:32 PM PDT 24
Peak memory 211012 kb
Host smart-edce608a-bfa3-4f3f-b27f-de3a9c240ebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2596348825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2596348825
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1128915782
Short name T229
Test name
Test status
Simulation time 1741027662 ps
CPU time 20.81 seconds
Started Jun 06 12:27:15 PM PDT 24
Finished Jun 06 12:27:36 PM PDT 24
Peak memory 213036 kb
Host smart-bf4517cb-5029-48a4-97fd-0dbfdcff5d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128915782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1128915782
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2362661273
Short name T71
Test name
Test status
Simulation time 28328493845 ps
CPU time 76.98 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:29:09 PM PDT 24
Peak memory 218060 kb
Host smart-2f3592e2-ff0e-47a7-b0da-69d556da4159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362661273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2362661273
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1578263277
Short name T326
Test name
Test status
Simulation time 24177260459 ps
CPU time 861.3 seconds
Started Jun 06 12:25:33 PM PDT 24
Finished Jun 06 12:39:56 PM PDT 24
Peak memory 232828 kb
Host smart-7a4c234b-1e3a-4ba8-b70b-4df185252eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578263277 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1578263277
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2196166361
Short name T278
Test name
Test status
Simulation time 4128862437 ps
CPU time 10.26 seconds
Started Jun 06 12:26:05 PM PDT 24
Finished Jun 06 12:26:17 PM PDT 24
Peak memory 209328 kb
Host smart-6d8ec829-4e01-4bcd-9a69-1251b3dda4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196166361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2196166361
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2389832690
Short name T171
Test name
Test status
Simulation time 128560396339 ps
CPU time 131.21 seconds
Started Jun 06 12:22:40 PM PDT 24
Finished Jun 06 12:24:51 PM PDT 24
Peak memory 238208 kb
Host smart-201080ce-24dc-4010-8073-28a15ff960b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389832690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2389832690
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.369875372
Short name T161
Test name
Test status
Simulation time 7508691253 ps
CPU time 29.15 seconds
Started Jun 06 12:26:26 PM PDT 24
Finished Jun 06 12:26:57 PM PDT 24
Peak memory 212104 kb
Host smart-5b4f1fc9-7f32-4de3-9fe6-799e3831dd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369875372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.369875372
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.378582786
Short name T206
Test name
Test status
Simulation time 188601269 ps
CPU time 5.48 seconds
Started Jun 06 12:23:12 PM PDT 24
Finished Jun 06 12:23:18 PM PDT 24
Peak memory 210896 kb
Host smart-57b29e21-5387-4857-a11d-bc82f253424e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378582786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.378582786
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.320874765
Short name T24
Test name
Test status
Simulation time 420877949 ps
CPU time 101.07 seconds
Started Jun 06 12:24:00 PM PDT 24
Finished Jun 06 12:25:42 PM PDT 24
Peak memory 237336 kb
Host smart-708866aa-39bd-47df-8e63-96ee515c9415
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320874765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.320874765
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2820417755
Short name T274
Test name
Test status
Simulation time 4147245214 ps
CPU time 24.96 seconds
Started Jun 06 12:22:53 PM PDT 24
Finished Jun 06 12:23:19 PM PDT 24
Peak memory 212728 kb
Host smart-dc67b2dd-b356-479c-8cd1-299c57f080af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820417755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2820417755
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3037433691
Short name T250
Test name
Test status
Simulation time 89047941 ps
CPU time 4.22 seconds
Started Jun 06 12:27:53 PM PDT 24
Finished Jun 06 12:27:59 PM PDT 24
Peak memory 210432 kb
Host smart-f1cd3a99-e3fd-49c3-880b-bf8bc798c496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037433691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3037433691
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4065943956
Short name T46
Test name
Test status
Simulation time 17623448904 ps
CPU time 158.83 seconds
Started Jun 06 12:25:33 PM PDT 24
Finished Jun 06 12:28:13 PM PDT 24
Peak memory 225708 kb
Host smart-094c94a8-766f-4571-9f7e-5e526f2628e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065943956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4065943956
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2402285054
Short name T151
Test name
Test status
Simulation time 341164060 ps
CPU time 9.12 seconds
Started Jun 06 12:26:05 PM PDT 24
Finished Jun 06 12:26:16 PM PDT 24
Peak memory 209828 kb
Host smart-ed267913-3ffe-4d7f-a78f-dbe13a489422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402285054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2402285054
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3167772863
Short name T143
Test name
Test status
Simulation time 2087019723 ps
CPU time 16.56 seconds
Started Jun 06 12:25:45 PM PDT 24
Finished Jun 06 12:26:02 PM PDT 24
Peak memory 210756 kb
Host smart-c24a03f0-036d-4b19-9af5-a650f4350a91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167772863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3167772863
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2518139627
Short name T233
Test name
Test status
Simulation time 3828474966 ps
CPU time 28.17 seconds
Started Jun 06 12:27:54 PM PDT 24
Finished Jun 06 12:28:24 PM PDT 24
Peak memory 212952 kb
Host smart-7cb911bc-7066-43c1-8a63-ec81464a810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518139627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2518139627
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.700788765
Short name T373
Test name
Test status
Simulation time 8932473985 ps
CPU time 19.65 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:28:13 PM PDT 24
Peak memory 210240 kb
Host smart-e7938f41-b242-4d88-9e24-73ef5e89c1ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700788765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.700788765
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3764555980
Short name T49
Test name
Test status
Simulation time 384158290606 ps
CPU time 3870.79 seconds
Started Jun 06 12:24:37 PM PDT 24
Finished Jun 06 01:29:09 PM PDT 24
Peak memory 254560 kb
Host smart-196f645c-5740-4e81-a448-7c9827d37c01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764555980 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3764555980
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3514104400
Short name T243
Test name
Test status
Simulation time 5095044484 ps
CPU time 12.63 seconds
Started Jun 06 12:24:44 PM PDT 24
Finished Jun 06 12:24:57 PM PDT 24
Peak memory 210832 kb
Host smart-08897de2-853d-493c-b14d-cecba19183e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514104400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3514104400
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2061470798
Short name T322
Test name
Test status
Simulation time 96476040605 ps
CPU time 276.24 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:31:03 PM PDT 24
Peak memory 227724 kb
Host smart-2962cc7c-1a45-45f2-bb84-5eb085a8117a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061470798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2061470798
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.646762634
Short name T34
Test name
Test status
Simulation time 5890946160 ps
CPU time 19.59 seconds
Started Jun 06 12:26:30 PM PDT 24
Finished Jun 06 12:26:52 PM PDT 24
Peak memory 211840 kb
Host smart-a7282c18-6cb3-4f24-ab7f-aa5b957b97ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646762634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.646762634
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1562213226
Short name T173
Test name
Test status
Simulation time 5741109095 ps
CPU time 13.61 seconds
Started Jun 06 12:26:06 PM PDT 24
Finished Jun 06 12:26:20 PM PDT 24
Peak memory 210720 kb
Host smart-6cccef84-63c6-4270-8cbc-4c96937c463f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562213226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1562213226
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3433213700
Short name T317
Test name
Test status
Simulation time 3723956639 ps
CPU time 35.25 seconds
Started Jun 06 12:28:23 PM PDT 24
Finished Jun 06 12:29:00 PM PDT 24
Peak memory 212168 kb
Host smart-133c252c-7f66-455d-8917-857697395820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433213700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3433213700
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.676811172
Short name T308
Test name
Test status
Simulation time 4247297773 ps
CPU time 37.78 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:28:32 PM PDT 24
Peak memory 212928 kb
Host smart-6d95a53f-0f33-4eec-afa6-dd9db20f21b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676811172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.676811172
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.177304566
Short name T252
Test name
Test status
Simulation time 33066452982 ps
CPU time 963.85 seconds
Started Jun 06 12:26:05 PM PDT 24
Finished Jun 06 12:42:10 PM PDT 24
Peak memory 233728 kb
Host smart-ce7c1c84-3170-48d4-9128-8966bb0e0cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177304566 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.177304566
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4143557144
Short name T254
Test name
Test status
Simulation time 2255790301 ps
CPU time 11.1 seconds
Started Jun 06 12:26:10 PM PDT 24
Finished Jun 06 12:26:22 PM PDT 24
Peak memory 209476 kb
Host smart-5a1f7c20-e90a-4ad3-9cff-51d7a539a91d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143557144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4143557144
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.174770657
Short name T15
Test name
Test status
Simulation time 72892456222 ps
CPU time 224.48 seconds
Started Jun 06 12:24:50 PM PDT 24
Finished Jun 06 12:28:35 PM PDT 24
Peak memory 214024 kb
Host smart-c3994fc6-4cda-4415-b94a-d23fcf6a341d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174770657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.174770657
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4080629425
Short name T358
Test name
Test status
Simulation time 675586713 ps
CPU time 14.38 seconds
Started Jun 06 12:24:53 PM PDT 24
Finished Jun 06 12:25:08 PM PDT 24
Peak memory 211536 kb
Host smart-fc110157-c065-44d1-9980-1d089a312d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080629425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4080629425
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.890588968
Short name T14
Test name
Test status
Simulation time 867635555 ps
CPU time 10.55 seconds
Started Jun 06 12:26:05 PM PDT 24
Finished Jun 06 12:26:17 PM PDT 24
Peak memory 209372 kb
Host smart-0d642399-8e8f-465a-a04a-c716a1efc3c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890588968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.890588968
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.475497594
Short name T307
Test name
Test status
Simulation time 10874171321 ps
CPU time 26.66 seconds
Started Jun 06 12:24:48 PM PDT 24
Finished Jun 06 12:25:16 PM PDT 24
Peak memory 213488 kb
Host smart-0fef21be-74a3-4380-b554-5181c71d90f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475497594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.475497594
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3768687050
Short name T139
Test name
Test status
Simulation time 469414731 ps
CPU time 6.71 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:26:33 PM PDT 24
Peak memory 209404 kb
Host smart-8c772ca3-ca7e-4b5e-b1a5-232fe880aff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768687050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3768687050
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2094639923
Short name T146
Test name
Test status
Simulation time 5798449215 ps
CPU time 12.57 seconds
Started Jun 06 12:26:44 PM PDT 24
Finished Jun 06 12:26:58 PM PDT 24
Peak memory 210036 kb
Host smart-f518de52-d06d-4498-8cf2-e765e7e108d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094639923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2094639923
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2343881707
Short name T131
Test name
Test status
Simulation time 6030879869 ps
CPU time 80.56 seconds
Started Jun 06 12:26:22 PM PDT 24
Finished Jun 06 12:27:45 PM PDT 24
Peak memory 236580 kb
Host smart-1a06f2bb-4fc9-4f68-aeaa-587a7c1d44f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343881707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2343881707
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.396043970
Short name T156
Test name
Test status
Simulation time 21665989778 ps
CPU time 29.89 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:53 PM PDT 24
Peak memory 210028 kb
Host smart-2ee6831c-2c5e-4e8a-8e9f-ab3a855b004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396043970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.396043970
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1979212272
Short name T312
Test name
Test status
Simulation time 1346963648 ps
CPU time 6.58 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:30 PM PDT 24
Peak memory 208572 kb
Host smart-547633b6-e351-4f7d-819b-97da24cd1aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979212272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1979212272
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2222862036
Short name T325
Test name
Test status
Simulation time 747986653 ps
CPU time 9.27 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:31 PM PDT 24
Peak memory 212896 kb
Host smart-6855d11c-08cf-4321-8db9-b645df7540cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222862036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2222862036
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.697074916
Short name T241
Test name
Test status
Simulation time 7978600676 ps
CPU time 28.36 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:52 PM PDT 24
Peak memory 212432 kb
Host smart-7654abb0-cb21-4e7f-9b74-bca005a5e88b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697074916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.697074916
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.103284231
Short name T50
Test name
Test status
Simulation time 22499870218 ps
CPU time 3890.71 seconds
Started Jun 06 12:25:10 PM PDT 24
Finished Jun 06 01:30:02 PM PDT 24
Peak memory 227320 kb
Host smart-2e7758b9-67b7-463e-b4fb-bf5165f3e25c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103284231 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.103284231
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4165893294
Short name T167
Test name
Test status
Simulation time 5584746728 ps
CPU time 12.74 seconds
Started Jun 06 12:25:45 PM PDT 24
Finished Jun 06 12:25:59 PM PDT 24
Peak memory 210864 kb
Host smart-2a7394b8-f2e8-4807-afdd-4f466ea4b6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165893294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4165893294
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.593768053
Short name T165
Test name
Test status
Simulation time 14637003667 ps
CPU time 142.12 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:30:14 PM PDT 24
Peak memory 232184 kb
Host smart-c9730874-c817-4211-9523-8c9f5e094939
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593768053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.593768053
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2774164650
Short name T152
Test name
Test status
Simulation time 505065424 ps
CPU time 9.16 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:36 PM PDT 24
Peak memory 211272 kb
Host smart-3127e0f2-fdf4-449d-a044-f56f6ccf44cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774164650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2774164650
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3354943550
Short name T97
Test name
Test status
Simulation time 10398841740 ps
CPU time 17.4 seconds
Started Jun 06 12:25:34 PM PDT 24
Finished Jun 06 12:25:52 PM PDT 24
Peak memory 211348 kb
Host smart-3aa7c8fb-82bc-4b92-b4e4-8aa329d24ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354943550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3354943550
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3419760044
Short name T90
Test name
Test status
Simulation time 744340335 ps
CPU time 14.46 seconds
Started Jun 06 12:25:23 PM PDT 24
Finished Jun 06 12:25:37 PM PDT 24
Peak memory 214648 kb
Host smart-88a8dbd7-9d4f-47b8-b917-dea78a983373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419760044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3419760044
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3424971419
Short name T223
Test name
Test status
Simulation time 3094613723 ps
CPU time 38.33 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 12:28:31 PM PDT 24
Peak memory 213080 kb
Host smart-f4bdc2c8-2b41-4b74-97e3-344d5d064b72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424971419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3424971419
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2282041162
Short name T32
Test name
Test status
Simulation time 59626646012 ps
CPU time 5397.03 seconds
Started Jun 06 12:25:19 PM PDT 24
Finished Jun 06 01:55:17 PM PDT 24
Peak memory 236180 kb
Host smart-d976aac7-f766-4dd0-a846-21728e72bae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282041162 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2282041162
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2662018743
Short name T219
Test name
Test status
Simulation time 347484633 ps
CPU time 4.08 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:27:58 PM PDT 24
Peak memory 210448 kb
Host smart-8b3fb032-e04b-475b-b237-bbf0bc107e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662018743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2662018743
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1784397641
Short name T187
Test name
Test status
Simulation time 3147664741 ps
CPU time 91.84 seconds
Started Jun 06 12:25:59 PM PDT 24
Finished Jun 06 12:27:31 PM PDT 24
Peak memory 236404 kb
Host smart-e7f002af-350c-4623-8954-5c764920f48a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784397641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1784397641
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1364283834
Short name T305
Test name
Test status
Simulation time 3546584399 ps
CPU time 15.38 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 210944 kb
Host smart-5b601082-9ad5-4b88-93b8-c0129fd5c4f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364283834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1364283834
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2157291461
Short name T330
Test name
Test status
Simulation time 186782743 ps
CPU time 10.36 seconds
Started Jun 06 12:25:36 PM PDT 24
Finished Jun 06 12:25:47 PM PDT 24
Peak memory 213540 kb
Host smart-e75665a2-d406-4411-a633-d602a88adfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157291461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2157291461
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3832869486
Short name T136
Test name
Test status
Simulation time 377206832 ps
CPU time 9.8 seconds
Started Jun 06 12:25:34 PM PDT 24
Finished Jun 06 12:25:44 PM PDT 24
Peak memory 210848 kb
Host smart-e21e7c05-8a3c-40d0-9f53-13a8944fd2bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832869486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3832869486
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3042081008
Short name T160
Test name
Test status
Simulation time 33211259721 ps
CPU time 16.05 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:43 PM PDT 24
Peak memory 210692 kb
Host smart-eae33a1e-ee8a-4015-9436-042648b3cefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042081008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3042081008
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4248330124
Short name T218
Test name
Test status
Simulation time 17205512394 ps
CPU time 169.39 seconds
Started Jun 06 12:26:11 PM PDT 24
Finished Jun 06 12:29:01 PM PDT 24
Peak memory 228180 kb
Host smart-12554b7e-811f-4feb-a43f-856a1356aefc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248330124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4248330124
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3842156943
Short name T23
Test name
Test status
Simulation time 2571175911 ps
CPU time 24.86 seconds
Started Jun 06 12:27:56 PM PDT 24
Finished Jun 06 12:28:23 PM PDT 24
Peak memory 211468 kb
Host smart-29235bca-f58d-4ea3-82a1-82e49c983eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842156943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3842156943
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1639854881
Short name T277
Test name
Test status
Simulation time 8212363362 ps
CPU time 16.92 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:16 PM PDT 24
Peak memory 210936 kb
Host smart-83b53144-4adf-4d91-93c5-e539021692a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1639854881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1639854881
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.342389466
Short name T33
Test name
Test status
Simulation time 10599412004 ps
CPU time 38.19 seconds
Started Jun 06 12:25:59 PM PDT 24
Finished Jun 06 12:26:37 PM PDT 24
Peak memory 214080 kb
Host smart-a9bb1d2f-0883-4183-8a01-c6b10cb6c800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342389466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.342389466
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4105203635
Short name T147
Test name
Test status
Simulation time 110568309 ps
CPU time 8.72 seconds
Started Jun 06 12:26:08 PM PDT 24
Finished Jun 06 12:26:17 PM PDT 24
Peak memory 210768 kb
Host smart-2a4de58c-657e-404e-b84d-316e6c3c09e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105203635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4105203635
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.336641964
Short name T1
Test name
Test status
Simulation time 56590252013 ps
CPU time 531.2 seconds
Started Jun 06 12:28:16 PM PDT 24
Finished Jun 06 12:37:09 PM PDT 24
Peak memory 231760 kb
Host smart-3f266fd5-2dfa-4b34-b1b2-32982d00d753
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336641964 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.336641964
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3163558469
Short name T20
Test name
Test status
Simulation time 1149431260 ps
CPU time 10.79 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:38 PM PDT 24
Peak memory 210620 kb
Host smart-be4d0ab4-e8c0-47b4-b668-f5167f2d932e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163558469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3163558469
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.530595056
Short name T284
Test name
Test status
Simulation time 6128684184 ps
CPU time 93.26 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:28:00 PM PDT 24
Peak memory 233576 kb
Host smart-1f84c79c-8e3e-49d8-9475-b3d62b795be1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530595056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.530595056
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3313510890
Short name T127
Test name
Test status
Simulation time 1824992181 ps
CPU time 20.6 seconds
Started Jun 06 12:26:36 PM PDT 24
Finished Jun 06 12:26:58 PM PDT 24
Peak memory 211440 kb
Host smart-40b4baaa-862f-47ea-b13a-114b4c0cd493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313510890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3313510890
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3429360253
Short name T4
Test name
Test status
Simulation time 8772072486 ps
CPU time 16.27 seconds
Started Jun 06 12:28:26 PM PDT 24
Finished Jun 06 12:28:43 PM PDT 24
Peak memory 210872 kb
Host smart-bd00fec1-8629-47ed-8f19-1036691cb93f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3429360253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3429360253
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.805794776
Short name T314
Test name
Test status
Simulation time 6206343444 ps
CPU time 18.21 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:40 PM PDT 24
Peak memory 213112 kb
Host smart-6691fa26-6d6f-4f16-98c5-571e6f3f8e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805794776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.805794776
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3050977454
Short name T227
Test name
Test status
Simulation time 9337242697 ps
CPU time 41.94 seconds
Started Jun 06 12:28:25 PM PDT 24
Finished Jun 06 12:29:08 PM PDT 24
Peak memory 217472 kb
Host smart-eaa3fc40-235d-4fe5-8f61-22b73c4cce43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050977454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3050977454
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.308735197
Short name T232
Test name
Test status
Simulation time 638255192 ps
CPU time 5.2 seconds
Started Jun 06 12:27:49 PM PDT 24
Finished Jun 06 12:27:55 PM PDT 24
Peak memory 209304 kb
Host smart-c7af50d2-c1fb-4bb2-9b13-fd756da3b9d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308735197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.308735197
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1121955043
Short name T231
Test name
Test status
Simulation time 43200969440 ps
CPU time 149.49 seconds
Started Jun 06 12:26:26 PM PDT 24
Finished Jun 06 12:28:57 PM PDT 24
Peak memory 233400 kb
Host smart-7a446a2d-b14f-43c6-a157-9b050337b874
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121955043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1121955043
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2847419446
Short name T328
Test name
Test status
Simulation time 1545703091 ps
CPU time 14.09 seconds
Started Jun 06 12:27:45 PM PDT 24
Finished Jun 06 12:28:01 PM PDT 24
Peak memory 211264 kb
Host smart-3733b473-81b8-4e6a-9c9c-6470eabdeea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847419446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2847419446
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.29952860
Short name T211
Test name
Test status
Simulation time 198152746 ps
CPU time 5.61 seconds
Started Jun 06 12:26:20 PM PDT 24
Finished Jun 06 12:26:28 PM PDT 24
Peak memory 210908 kb
Host smart-34d19737-c7a3-4abf-bcfd-3bd06f3fd621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29952860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.29952860
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3934212039
Short name T72
Test name
Test status
Simulation time 185611541 ps
CPU time 9.94 seconds
Started Jun 06 12:26:35 PM PDT 24
Finished Jun 06 12:26:47 PM PDT 24
Peak memory 213080 kb
Host smart-8c02ea7e-26c5-471a-bc80-d2327dcc9487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934212039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3934212039
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.309023828
Short name T95
Test name
Test status
Simulation time 6403383516 ps
CPU time 59.76 seconds
Started Jun 06 12:28:17 PM PDT 24
Finished Jun 06 12:29:18 PM PDT 24
Peak memory 216508 kb
Host smart-b369eff1-98cc-46fe-b8fe-f2ac55d5a5a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309023828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.309023828
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.272273991
Short name T221
Test name
Test status
Simulation time 11205006905 ps
CPU time 479.53 seconds
Started Jun 06 12:26:35 PM PDT 24
Finished Jun 06 12:34:36 PM PDT 24
Peak memory 227388 kb
Host smart-96a38577-d3e7-499c-a136-0f68cec8d231
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272273991 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.272273991
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3544296852
Short name T175
Test name
Test status
Simulation time 831395324 ps
CPU time 4.12 seconds
Started Jun 06 12:26:45 PM PDT 24
Finished Jun 06 12:26:49 PM PDT 24
Peak memory 210776 kb
Host smart-21d5cc46-91b3-4115-8ab1-add5c90ef8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544296852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3544296852
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3745398545
Short name T203
Test name
Test status
Simulation time 11243260227 ps
CPU time 230.63 seconds
Started Jun 06 12:26:37 PM PDT 24
Finished Jun 06 12:30:29 PM PDT 24
Peak memory 237404 kb
Host smart-3518c3d9-a497-4728-ab52-9b86ec8e8317
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745398545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3745398545
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3078543342
Short name T130
Test name
Test status
Simulation time 7592932814 ps
CPU time 23.04 seconds
Started Jun 06 12:26:30 PM PDT 24
Finished Jun 06 12:26:55 PM PDT 24
Peak memory 212528 kb
Host smart-09703385-b270-4a14-beb6-e2628dcf707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078543342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3078543342
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1221971045
Short name T371
Test name
Test status
Simulation time 5557471358 ps
CPU time 12.19 seconds
Started Jun 06 12:27:50 PM PDT 24
Finished Jun 06 12:28:03 PM PDT 24
Peak memory 210736 kb
Host smart-a6062ec5-d427-44b3-8c4f-7cbe26fa2d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221971045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1221971045
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2771886409
Short name T140
Test name
Test status
Simulation time 180501302 ps
CPU time 9.86 seconds
Started Jun 06 12:27:41 PM PDT 24
Finished Jun 06 12:27:52 PM PDT 24
Peak memory 212316 kb
Host smart-2b7ef4fa-a4b4-4f2f-a5c2-cc60689a885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771886409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2771886409
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1415687751
Short name T344
Test name
Test status
Simulation time 7551091424 ps
CPU time 34.76 seconds
Started Jun 06 12:27:49 PM PDT 24
Finished Jun 06 12:28:25 PM PDT 24
Peak memory 213928 kb
Host smart-da09073c-ef20-4e46-b902-0e6f024f948a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415687751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1415687751
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1878232946
Short name T294
Test name
Test status
Simulation time 159412506739 ps
CPU time 2815.45 seconds
Started Jun 06 12:27:51 PM PDT 24
Finished Jun 06 01:14:49 PM PDT 24
Peak memory 240728 kb
Host smart-c9c206f3-9b43-4fb3-aa9c-7cc421d5576f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878232946 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1878232946
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1971748955
Short name T59
Test name
Test status
Simulation time 361858795 ps
CPU time 4.15 seconds
Started Jun 06 12:23:59 PM PDT 24
Finished Jun 06 12:24:04 PM PDT 24
Peak memory 208832 kb
Host smart-d160caff-5f2d-4f1e-b8ef-c02e1a58812a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971748955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1971748955
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1155711301
Short name T37
Test name
Test status
Simulation time 1840314768 ps
CPU time 114.33 seconds
Started Jun 06 12:23:59 PM PDT 24
Finished Jun 06 12:25:55 PM PDT 24
Peak memory 230136 kb
Host smart-6d932e30-f04d-4cdc-aa93-0f9ceb4f4ce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155711301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1155711301
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4083281702
Short name T264
Test name
Test status
Simulation time 5873496130 ps
CPU time 25.94 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:46 PM PDT 24
Peak memory 211692 kb
Host smart-7fe907a6-db2f-47d4-9eb5-de03b8c6ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083281702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4083281702
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2844991331
Short name T336
Test name
Test status
Simulation time 2548975657 ps
CPU time 12.81 seconds
Started Jun 06 12:25:00 PM PDT 24
Finished Jun 06 12:25:14 PM PDT 24
Peak memory 210972 kb
Host smart-c28a46bf-8f92-49e3-ad70-c5be2672e5c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844991331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2844991331
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1484560346
Short name T18
Test name
Test status
Simulation time 1520128866 ps
CPU time 49.7 seconds
Started Jun 06 12:26:26 PM PDT 24
Finished Jun 06 12:27:17 PM PDT 24
Peak memory 235736 kb
Host smart-b8ddafd2-c992-46c2-a7c3-08ebf30b1480
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484560346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1484560346
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1096401940
Short name T198
Test name
Test status
Simulation time 3989588546 ps
CPU time 17.04 seconds
Started Jun 06 12:26:27 PM PDT 24
Finished Jun 06 12:26:45 PM PDT 24
Peak memory 213596 kb
Host smart-2937d136-ce7c-4e49-b3df-75be34a223fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096401940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1096401940
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1480905896
Short name T208
Test name
Test status
Simulation time 2526487830 ps
CPU time 45.84 seconds
Started Jun 06 12:23:03 PM PDT 24
Finished Jun 06 12:23:50 PM PDT 24
Peak memory 215608 kb
Host smart-ef25a58f-33d6-4a07-9635-3587244cc577
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480905896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1480905896
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2136704754
Short name T193
Test name
Test status
Simulation time 89011553 ps
CPU time 4.06 seconds
Started Jun 06 12:28:04 PM PDT 24
Finished Jun 06 12:28:09 PM PDT 24
Peak memory 210456 kb
Host smart-7e66fcb4-33e6-48bb-8241-57b545cf0996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136704754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2136704754
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2000745282
Short name T287
Test name
Test status
Simulation time 31482339473 ps
CPU time 314.19 seconds
Started Jun 06 12:28:04 PM PDT 24
Finished Jun 06 12:33:19 PM PDT 24
Peak memory 212364 kb
Host smart-41bdae58-364e-480d-b479-896d58198712
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000745282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2000745282
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2862658941
Short name T220
Test name
Test status
Simulation time 3029190873 ps
CPU time 28.17 seconds
Started Jun 06 12:26:45 PM PDT 24
Finished Jun 06 12:27:13 PM PDT 24
Peak memory 210956 kb
Host smart-f7afb9c9-640d-40fd-891f-90627570bfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862658941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2862658941
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1153778132
Short name T132
Test name
Test status
Simulation time 19781273380 ps
CPU time 15.23 seconds
Started Jun 06 12:27:57 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 210804 kb
Host smart-2bb60ba8-3b8a-4f7b-9ee9-5e5793bcc3af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153778132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1153778132
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.389574719
Short name T362
Test name
Test status
Simulation time 12613169483 ps
CPU time 31.24 seconds
Started Jun 06 12:26:45 PM PDT 24
Finished Jun 06 12:27:17 PM PDT 24
Peak memory 213464 kb
Host smart-ece9402e-8f41-41fd-b5c6-327416b4d426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389574719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.389574719
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1656464424
Short name T224
Test name
Test status
Simulation time 3658593527 ps
CPU time 14.88 seconds
Started Jun 06 12:28:02 PM PDT 24
Finished Jun 06 12:28:19 PM PDT 24
Peak memory 209184 kb
Host smart-3bd226bc-76f2-4078-a022-044258091a60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656464424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1656464424
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1340022128
Short name T280
Test name
Test status
Simulation time 52758980933 ps
CPU time 1308.62 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:49:57 PM PDT 24
Peak memory 233184 kb
Host smart-71d1325b-2a1e-46c8-8f8a-bcc1a9aa89b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340022128 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1340022128
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.175082472
Short name T184
Test name
Test status
Simulation time 3997950546 ps
CPU time 15.83 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:28:21 PM PDT 24
Peak memory 209304 kb
Host smart-3f78b25c-e556-4dd6-89fd-23126ca60d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175082472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.175082472
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2968178127
Short name T300
Test name
Test status
Simulation time 13473387176 ps
CPU time 128.94 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:30:13 PM PDT 24
Peak memory 233952 kb
Host smart-0c9f2233-d3a7-4468-ad5b-26aa15fe7863
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968178127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2968178127
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4114777912
Short name T191
Test name
Test status
Simulation time 1633580668 ps
CPU time 18.91 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:28:24 PM PDT 24
Peak memory 210592 kb
Host smart-7ddd7fd0-3e53-423d-99c2-7bdb7613e378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114777912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4114777912
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1551317445
Short name T141
Test name
Test status
Simulation time 3814997603 ps
CPU time 15.76 seconds
Started Jun 06 12:28:04 PM PDT 24
Finished Jun 06 12:28:21 PM PDT 24
Peak memory 210668 kb
Host smart-4647b826-d1df-4000-9766-6519688a2499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551317445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1551317445
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4098942695
Short name T133
Test name
Test status
Simulation time 7251678804 ps
CPU time 20.43 seconds
Started Jun 06 12:28:04 PM PDT 24
Finished Jun 06 12:28:26 PM PDT 24
Peak memory 213436 kb
Host smart-966339cb-2151-4bd8-b6cb-ae49dbdb80e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098942695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4098942695
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.556915884
Short name T275
Test name
Test status
Simulation time 42074945299 ps
CPU time 91.47 seconds
Started Jun 06 12:26:41 PM PDT 24
Finished Jun 06 12:28:13 PM PDT 24
Peak memory 219000 kb
Host smart-c47b9c98-03bb-48be-af9c-cf0b117fddb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556915884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.556915884
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2705960987
Short name T302
Test name
Test status
Simulation time 126468042 ps
CPU time 4.91 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:28:10 PM PDT 24
Peak memory 209576 kb
Host smart-5f424ed6-92f9-4476-a8f6-1aa87c5ffd61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705960987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2705960987
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.967840195
Short name T197
Test name
Test status
Simulation time 6354170480 ps
CPU time 157.5 seconds
Started Jun 06 12:27:59 PM PDT 24
Finished Jun 06 12:30:38 PM PDT 24
Peak memory 225252 kb
Host smart-38e6b916-2bfc-49a6-862b-4efd3744efd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967840195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.967840195
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.134456431
Short name T370
Test name
Test status
Simulation time 692515985 ps
CPU time 9.41 seconds
Started Jun 06 12:26:49 PM PDT 24
Finished Jun 06 12:26:59 PM PDT 24
Peak memory 211352 kb
Host smart-8d8c1bb9-ba3f-4572-89ae-2074178262a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134456431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.134456431
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1395452803
Short name T26
Test name
Test status
Simulation time 1585011740 ps
CPU time 14.05 seconds
Started Jun 06 12:28:10 PM PDT 24
Finished Jun 06 12:28:25 PM PDT 24
Peak memory 210904 kb
Host smart-44c4e1b7-8747-4a22-8820-3e59e8146f41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395452803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1395452803
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.294129968
Short name T257
Test name
Test status
Simulation time 3183813886 ps
CPU time 15.32 seconds
Started Jun 06 12:28:09 PM PDT 24
Finished Jun 06 12:28:25 PM PDT 24
Peak memory 212980 kb
Host smart-a57fe97f-76f4-4bb6-bf7e-113ac4655d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294129968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.294129968
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4211145083
Short name T291
Test name
Test status
Simulation time 20624846641 ps
CPU time 68.8 seconds
Started Jun 06 12:26:42 PM PDT 24
Finished Jun 06 12:27:51 PM PDT 24
Peak memory 218992 kb
Host smart-230bb3f2-8b25-4b21-adb0-ce93058c11e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211145083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4211145083
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3200752313
Short name T222
Test name
Test status
Simulation time 8024480621 ps
CPU time 15.91 seconds
Started Jun 06 12:26:54 PM PDT 24
Finished Jun 06 12:27:10 PM PDT 24
Peak memory 210900 kb
Host smart-2bf4b23b-12ba-4e83-8d3b-aae377a0e2cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200752313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3200752313
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2103641669
Short name T318
Test name
Test status
Simulation time 7934937078 ps
CPU time 188.11 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:31:13 PM PDT 24
Peak memory 238020 kb
Host smart-ea65107e-738b-4d16-97cb-e033716d43ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103641669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2103641669
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3080738637
Short name T202
Test name
Test status
Simulation time 1562741581 ps
CPU time 18.6 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:28:23 PM PDT 24
Peak memory 210028 kb
Host smart-3b36fa20-5d95-4ce5-a79d-e8e81491bb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080738637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3080738637
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2141071988
Short name T366
Test name
Test status
Simulation time 1099481970 ps
CPU time 8.58 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:28:17 PM PDT 24
Peak memory 209340 kb
Host smart-bd1ee76b-0521-4295-834a-8c825a686e8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141071988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2141071988
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2783713896
Short name T267
Test name
Test status
Simulation time 12844840150 ps
CPU time 31.78 seconds
Started Jun 06 12:28:02 PM PDT 24
Finished Jun 06 12:28:35 PM PDT 24
Peak memory 212608 kb
Host smart-8d00f4c5-a4ae-49d2-917c-d6f2654eedfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783713896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2783713896
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1739026475
Short name T306
Test name
Test status
Simulation time 6459460736 ps
CPU time 84.92 seconds
Started Jun 06 12:26:55 PM PDT 24
Finished Jun 06 12:28:20 PM PDT 24
Peak memory 215340 kb
Host smart-6198bdc8-4d1d-41b0-a7ef-15491eda002a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739026475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1739026475
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.397019499
Short name T11
Test name
Test status
Simulation time 25649312026 ps
CPU time 522.62 seconds
Started Jun 06 12:28:04 PM PDT 24
Finished Jun 06 12:36:48 PM PDT 24
Peak memory 233820 kb
Host smart-02a36237-f92c-4ead-a4ec-b450fef5afe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397019499 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.397019499
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3626408884
Short name T21
Test name
Test status
Simulation time 3537050792 ps
CPU time 14.66 seconds
Started Jun 06 12:26:50 PM PDT 24
Finished Jun 06 12:27:05 PM PDT 24
Peak memory 210804 kb
Host smart-44a8182b-f745-4ac6-865f-82fbd4eaf3c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626408884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3626408884
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3768531029
Short name T270
Test name
Test status
Simulation time 18388161874 ps
CPU time 105.27 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:29:54 PM PDT 24
Peak memory 211180 kb
Host smart-8b52459c-f518-42e8-afed-a765622347c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768531029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3768531029
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3295584123
Short name T128
Test name
Test status
Simulation time 188080788 ps
CPU time 9.09 seconds
Started Jun 06 12:28:04 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 211588 kb
Host smart-60aab2ac-cbc6-493e-9167-3fc7575219d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295584123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3295584123
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1878274166
Short name T180
Test name
Test status
Simulation time 11014209748 ps
CPU time 12.79 seconds
Started Jun 06 12:28:03 PM PDT 24
Finished Jun 06 12:28:18 PM PDT 24
Peak memory 210396 kb
Host smart-fe6784cd-ff07-45af-94b1-a2d67c158a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878274166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1878274166
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.803086124
Short name T186
Test name
Test status
Simulation time 251702484 ps
CPU time 9.74 seconds
Started Jun 06 12:28:04 PM PDT 24
Finished Jun 06 12:28:15 PM PDT 24
Peak memory 212820 kb
Host smart-5d95fa29-8d34-48e9-a1f4-11a3750da853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803086124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.803086124
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2981364380
Short name T236
Test name
Test status
Simulation time 58833793975 ps
CPU time 54.07 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:29:03 PM PDT 24
Peak memory 214604 kb
Host smart-cef02d2c-6c04-414a-8231-a921d0c21ee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981364380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2981364380
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.585437543
Short name T19
Test name
Test status
Simulation time 5550427292 ps
CPU time 11.94 seconds
Started Jun 06 12:28:16 PM PDT 24
Finished Jun 06 12:28:29 PM PDT 24
Peak memory 210544 kb
Host smart-b41be70b-c390-47c9-a970-fb02868c44b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585437543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.585437543
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1262188390
Short name T121
Test name
Test status
Simulation time 50306880395 ps
CPU time 144.46 seconds
Started Jun 06 12:27:08 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 228152 kb
Host smart-39bbd6a1-3664-4630-8c2d-a8f3c86f1939
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262188390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1262188390
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.527242648
Short name T273
Test name
Test status
Simulation time 724625413 ps
CPU time 9.47 seconds
Started Jun 06 12:27:00 PM PDT 24
Finished Jun 06 12:27:10 PM PDT 24
Peak memory 211744 kb
Host smart-905bbc75-2690-4a1b-8147-311f5cff5e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527242648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.527242648
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4110636235
Short name T329
Test name
Test status
Simulation time 1249051249 ps
CPU time 6.56 seconds
Started Jun 06 12:27:08 PM PDT 24
Finished Jun 06 12:27:15 PM PDT 24
Peak memory 210852 kb
Host smart-5dcfe80b-78a7-4c3a-a6d8-0401b9883b3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4110636235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4110636235
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3788687986
Short name T199
Test name
Test status
Simulation time 2920824993 ps
CPU time 27.91 seconds
Started Jun 06 12:28:08 PM PDT 24
Finished Jun 06 12:28:37 PM PDT 24
Peak memory 212480 kb
Host smart-6619cd42-7a4e-4b44-983e-b72e97d9a81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788687986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3788687986
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.576661691
Short name T91
Test name
Test status
Simulation time 1856922501 ps
CPU time 24.42 seconds
Started Jun 06 12:28:14 PM PDT 24
Finished Jun 06 12:28:40 PM PDT 24
Peak memory 212440 kb
Host smart-fd7ad184-7afb-4deb-99bd-31df082b2af4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576661691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.576661691
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1442568787
Short name T235
Test name
Test status
Simulation time 32571781041 ps
CPU time 2551.08 seconds
Started Jun 06 12:27:06 PM PDT 24
Finished Jun 06 01:09:38 PM PDT 24
Peak memory 227552 kb
Host smart-05d9656d-53fa-41da-ba8b-ae64089649c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442568787 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1442568787
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.446417421
Short name T349
Test name
Test status
Simulation time 85616949 ps
CPU time 4.06 seconds
Started Jun 06 12:28:15 PM PDT 24
Finished Jun 06 12:28:20 PM PDT 24
Peak memory 209464 kb
Host smart-23141966-20ca-4a74-b967-aa2333d98c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446417421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.446417421
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1817037836
Short name T134
Test name
Test status
Simulation time 7741768746 ps
CPU time 68.29 seconds
Started Jun 06 12:27:08 PM PDT 24
Finished Jun 06 12:28:17 PM PDT 24
Peak memory 212120 kb
Host smart-8f2016d2-3767-4811-886b-d693ef0029e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817037836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1817037836
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2706213919
Short name T293
Test name
Test status
Simulation time 4474502960 ps
CPU time 25.62 seconds
Started Jun 06 12:27:01 PM PDT 24
Finished Jun 06 12:27:27 PM PDT 24
Peak memory 212156 kb
Host smart-42580b1a-0541-420a-b641-8e7bcb7ae1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706213919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2706213919
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1727366733
Short name T212
Test name
Test status
Simulation time 7585572594 ps
CPU time 15.79 seconds
Started Jun 06 12:27:08 PM PDT 24
Finished Jun 06 12:27:25 PM PDT 24
Peak memory 210916 kb
Host smart-abb7aa10-c5ea-41c7-a070-9f69245cf70a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1727366733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1727366733
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2659322143
Short name T289
Test name
Test status
Simulation time 1133497353 ps
CPU time 10.07 seconds
Started Jun 06 12:27:08 PM PDT 24
Finished Jun 06 12:27:19 PM PDT 24
Peak memory 213508 kb
Host smart-b82be58a-3b15-422e-a84e-10f22bd8a1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659322143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2659322143
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2408486754
Short name T332
Test name
Test status
Simulation time 13303530925 ps
CPU time 49.72 seconds
Started Jun 06 12:27:12 PM PDT 24
Finished Jun 06 12:28:03 PM PDT 24
Peak memory 218948 kb
Host smart-d0513309-d6c1-4af2-923c-f7310b322254
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408486754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2408486754
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.4059393749
Short name T47
Test name
Test status
Simulation time 51325163875 ps
CPU time 1990.58 seconds
Started Jun 06 12:27:08 PM PDT 24
Finished Jun 06 01:00:20 PM PDT 24
Peak memory 233292 kb
Host smart-14d19581-f08e-41be-9290-63452eef4e2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059393749 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.4059393749
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1260097975
Short name T58
Test name
Test status
Simulation time 5549860734 ps
CPU time 14.95 seconds
Started Jun 06 12:27:33 PM PDT 24
Finished Jun 06 12:27:48 PM PDT 24
Peak memory 210772 kb
Host smart-10f3a8e9-122c-4ac7-8b5f-2cd6f3d88174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260097975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1260097975
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1392778589
Short name T248
Test name
Test status
Simulation time 64433050376 ps
CPU time 256.3 seconds
Started Jun 06 12:27:02 PM PDT 24
Finished Jun 06 12:31:19 PM PDT 24
Peak memory 238024 kb
Host smart-871cb257-fab0-4715-a1b2-487a1a7cc00b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392778589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1392778589
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2326266189
Short name T144
Test name
Test status
Simulation time 693013404 ps
CPU time 11.97 seconds
Started Jun 06 12:27:18 PM PDT 24
Finished Jun 06 12:27:32 PM PDT 24
Peak memory 210576 kb
Host smart-ff8ed84d-d9ce-41f2-8fc7-1de819473d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326266189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2326266189
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3189073746
Short name T262
Test name
Test status
Simulation time 466789856 ps
CPU time 8.3 seconds
Started Jun 06 12:27:10 PM PDT 24
Finished Jun 06 12:27:19 PM PDT 24
Peak memory 210804 kb
Host smart-50bc94ba-7f27-4c03-a4a6-fb380b2e35d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189073746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3189073746
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2515804455
Short name T154
Test name
Test status
Simulation time 712032742 ps
CPU time 9.98 seconds
Started Jun 06 12:27:18 PM PDT 24
Finished Jun 06 12:27:30 PM PDT 24
Peak memory 211560 kb
Host smart-e8788291-2d44-4df2-8a6b-48ab758b392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515804455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2515804455
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4120514906
Short name T361
Test name
Test status
Simulation time 1527396933 ps
CPU time 15.51 seconds
Started Jun 06 12:28:15 PM PDT 24
Finished Jun 06 12:28:31 PM PDT 24
Peak memory 211428 kb
Host smart-0c4abe35-9f73-4c39-87ac-db334b58beb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120514906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4120514906
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1886034628
Short name T285
Test name
Test status
Simulation time 102618605242 ps
CPU time 2786.67 seconds
Started Jun 06 12:27:11 PM PDT 24
Finished Jun 06 01:13:38 PM PDT 24
Peak memory 230152 kb
Host smart-ce05b296-7925-47de-bfa8-62281cb64570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886034628 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1886034628
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3212608077
Short name T260
Test name
Test status
Simulation time 1188564319 ps
CPU time 11.64 seconds
Started Jun 06 12:27:20 PM PDT 24
Finished Jun 06 12:27:33 PM PDT 24
Peak memory 210692 kb
Host smart-488a9827-8fc4-482c-b446-42572d7710f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212608077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3212608077
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2918676138
Short name T341
Test name
Test status
Simulation time 41757189489 ps
CPU time 245.42 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:31:24 PM PDT 24
Peak memory 211300 kb
Host smart-53993e1a-55dd-484e-bdd9-0769b0274376
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918676138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2918676138
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3920945314
Short name T124
Test name
Test status
Simulation time 3122566222 ps
CPU time 19.17 seconds
Started Jun 06 12:28:34 PM PDT 24
Finished Jun 06 12:28:55 PM PDT 24
Peak memory 211584 kb
Host smart-798d4bcd-33b7-4e2f-92ec-81772795f928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920945314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3920945314
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4012871726
Short name T178
Test name
Test status
Simulation time 9503775743 ps
CPU time 13.73 seconds
Started Jun 06 12:27:14 PM PDT 24
Finished Jun 06 12:27:28 PM PDT 24
Peak memory 210968 kb
Host smart-e078788f-7930-4ae6-9000-5a87e249af01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4012871726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4012871726
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1119115722
Short name T122
Test name
Test status
Simulation time 3688208053 ps
CPU time 30.28 seconds
Started Jun 06 12:27:13 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 212332 kb
Host smart-fd2c7ba7-4fd7-495f-a5d1-ed87a3cea8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119115722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1119115722
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1829176103
Short name T145
Test name
Test status
Simulation time 8817950177 ps
CPU time 19.94 seconds
Started Jun 06 12:27:11 PM PDT 24
Finished Jun 06 12:27:32 PM PDT 24
Peak memory 210892 kb
Host smart-eaa46f8f-2f64-4b18-b827-1dad1e430993
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829176103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1829176103
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2538176437
Short name T177
Test name
Test status
Simulation time 772005691 ps
CPU time 6.9 seconds
Started Jun 06 12:28:33 PM PDT 24
Finished Jun 06 12:28:41 PM PDT 24
Peak memory 210724 kb
Host smart-f107ec3a-fac7-4d3c-b544-89445d7f38ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538176437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2538176437
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3900790080
Short name T35
Test name
Test status
Simulation time 57284706379 ps
CPU time 388.89 seconds
Started Jun 06 12:27:18 PM PDT 24
Finished Jun 06 12:33:48 PM PDT 24
Peak memory 212148 kb
Host smart-1dfda1c5-8f72-4fb1-95e0-09657d49b8cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900790080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3900790080
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3266784328
Short name T356
Test name
Test status
Simulation time 348226898 ps
CPU time 9.06 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:27:27 PM PDT 24
Peak memory 211836 kb
Host smart-894dc06d-95f3-4801-a744-bda6ab0b773c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266784328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3266784328
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3126829294
Short name T104
Test name
Test status
Simulation time 4196091493 ps
CPU time 8.72 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:27:27 PM PDT 24
Peak memory 210928 kb
Host smart-4c686b26-9af8-4058-8182-cc1e55148402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126829294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3126829294
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.912442872
Short name T342
Test name
Test status
Simulation time 705705801 ps
CPU time 14.6 seconds
Started Jun 06 12:27:19 PM PDT 24
Finished Jun 06 12:27:35 PM PDT 24
Peak memory 212852 kb
Host smart-fc1c634e-b8e8-411e-a015-aae80dc3f11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912442872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.912442872
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2722775329
Short name T103
Test name
Test status
Simulation time 67213580506 ps
CPU time 71.8 seconds
Started Jun 06 12:27:12 PM PDT 24
Finished Jun 06 12:28:24 PM PDT 24
Peak memory 217280 kb
Host smart-755718d0-64d3-4743-bb85-b675b97bfed6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722775329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2722775329
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2629071321
Short name T162
Test name
Test status
Simulation time 248969481 ps
CPU time 5.75 seconds
Started Jun 06 12:26:27 PM PDT 24
Finished Jun 06 12:26:34 PM PDT 24
Peak memory 210596 kb
Host smart-a82c5794-7674-446c-9deb-318bec608438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629071321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2629071321
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1697511079
Short name T126
Test name
Test status
Simulation time 323126964497 ps
CPU time 188.4 seconds
Started Jun 06 12:26:26 PM PDT 24
Finished Jun 06 12:29:36 PM PDT 24
Peak memory 212036 kb
Host smart-9626efd9-910b-48d4-b6c5-b208730b6956
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697511079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1697511079
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1522275998
Short name T364
Test name
Test status
Simulation time 9651653776 ps
CPU time 29.45 seconds
Started Jun 06 12:28:15 PM PDT 24
Finished Jun 06 12:28:46 PM PDT 24
Peak memory 211672 kb
Host smart-288f1eea-72c9-409a-98b5-7a4df8239161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522275998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1522275998
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.130610537
Short name T149
Test name
Test status
Simulation time 1745287932 ps
CPU time 14.76 seconds
Started Jun 06 12:26:15 PM PDT 24
Finished Jun 06 12:26:31 PM PDT 24
Peak memory 210240 kb
Host smart-d9052f05-687b-47bc-bd61-e17d6dd6e21d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130610537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.130610537
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3964165576
Short name T94
Test name
Test status
Simulation time 1273221012 ps
CPU time 15.71 seconds
Started Jun 06 12:24:00 PM PDT 24
Finished Jun 06 12:24:17 PM PDT 24
Peak memory 212680 kb
Host smart-2abb6516-d129-4877-98ea-224f9b17c479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964165576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3964165576
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3459914546
Short name T299
Test name
Test status
Simulation time 18401245694 ps
CPU time 35.88 seconds
Started Jun 06 12:24:00 PM PDT 24
Finished Jun 06 12:24:37 PM PDT 24
Peak memory 213164 kb
Host smart-e7029236-e4dd-4268-bb36-aa3b5c333c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459914546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3459914546
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1624971859
Short name T148
Test name
Test status
Simulation time 475955520 ps
CPU time 7.69 seconds
Started Jun 06 12:28:34 PM PDT 24
Finished Jun 06 12:28:43 PM PDT 24
Peak memory 210724 kb
Host smart-ed525665-32da-4b84-85e3-7b8aeae4db1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624971859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1624971859
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3785614085
Short name T353
Test name
Test status
Simulation time 249900861112 ps
CPU time 530.53 seconds
Started Jun 06 12:27:18 PM PDT 24
Finished Jun 06 12:36:10 PM PDT 24
Peak memory 224900 kb
Host smart-52f964d3-bc41-4101-a5da-c651bb0ba3d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785614085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3785614085
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1910316505
Short name T29
Test name
Test status
Simulation time 665573535 ps
CPU time 9.75 seconds
Started Jun 06 12:27:15 PM PDT 24
Finished Jun 06 12:27:25 PM PDT 24
Peak memory 211932 kb
Host smart-9f38cea3-34c2-47c7-aa5d-37c1592cdfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910316505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1910316505
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2476302471
Short name T242
Test name
Test status
Simulation time 1852946176 ps
CPU time 5.48 seconds
Started Jun 06 12:27:11 PM PDT 24
Finished Jun 06 12:27:17 PM PDT 24
Peak memory 210836 kb
Host smart-8a0bc3ce-3da3-41a7-9668-8856ee33ac71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2476302471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2476302471
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3743599326
Short name T311
Test name
Test status
Simulation time 6159786385 ps
CPU time 30.7 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:27:49 PM PDT 24
Peak memory 213316 kb
Host smart-acaefe38-1ec4-42a2-840e-21d57b16925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743599326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3743599326
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4182945305
Short name T179
Test name
Test status
Simulation time 37917882734 ps
CPU time 34.1 seconds
Started Jun 06 12:27:18 PM PDT 24
Finished Jun 06 12:27:53 PM PDT 24
Peak memory 215224 kb
Host smart-93fb62a4-58b0-4eae-bb32-b615ab143410
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182945305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4182945305
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1662992705
Short name T282
Test name
Test status
Simulation time 1485508763 ps
CPU time 12.47 seconds
Started Jun 06 12:27:13 PM PDT 24
Finished Jun 06 12:27:26 PM PDT 24
Peak memory 210692 kb
Host smart-72888b84-9166-4ede-9638-d26c77b832d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662992705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1662992705
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.786390428
Short name T265
Test name
Test status
Simulation time 205323578230 ps
CPU time 333.18 seconds
Started Jun 06 12:27:14 PM PDT 24
Finished Jun 06 12:32:48 PM PDT 24
Peak memory 237816 kb
Host smart-9e4e38f3-8276-457d-ac7e-2d94925996c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786390428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.786390428
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1629727733
Short name T207
Test name
Test status
Simulation time 15171610444 ps
CPU time 31.83 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:27:55 PM PDT 24
Peak memory 211672 kb
Host smart-92a236ea-0945-4522-8ccc-59d249ddea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629727733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1629727733
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2386566147
Short name T183
Test name
Test status
Simulation time 303398467 ps
CPU time 7.66 seconds
Started Jun 06 12:27:13 PM PDT 24
Finished Jun 06 12:27:21 PM PDT 24
Peak memory 210804 kb
Host smart-93182078-14c7-4b61-934f-215e892e6d6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386566147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2386566147
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.692308126
Short name T228
Test name
Test status
Simulation time 373506130 ps
CPU time 9.94 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:27:28 PM PDT 24
Peak memory 212824 kb
Host smart-230828db-1192-4a75-b211-849b56bcc09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692308126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.692308126
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1702383836
Short name T31
Test name
Test status
Simulation time 18884351708 ps
CPU time 53.1 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:28:16 PM PDT 24
Peak memory 216872 kb
Host smart-c1c9f999-c47d-4813-9fe6-d83f34b2d539
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702383836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1702383836
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.298641436
Short name T303
Test name
Test status
Simulation time 3406354104 ps
CPU time 13.68 seconds
Started Jun 06 12:27:19 PM PDT 24
Finished Jun 06 12:27:34 PM PDT 24
Peak memory 210840 kb
Host smart-26994152-e3bc-4a9a-8f44-422fcc75b86c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298641436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.298641436
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.315388626
Short name T321
Test name
Test status
Simulation time 1932581415 ps
CPU time 119.16 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:29:22 PM PDT 24
Peak memory 237220 kb
Host smart-31572492-79b8-4d42-bc98-01c2ac0c5a04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315388626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.315388626
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2428101439
Short name T304
Test name
Test status
Simulation time 500797767 ps
CPU time 12.66 seconds
Started Jun 06 12:27:16 PM PDT 24
Finished Jun 06 12:27:30 PM PDT 24
Peak memory 211504 kb
Host smart-c49bba57-3e28-43d3-a12e-39adf15e6507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428101439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2428101439
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2856761852
Short name T352
Test name
Test status
Simulation time 7007170281 ps
CPU time 13.93 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:27:32 PM PDT 24
Peak memory 210988 kb
Host smart-04d283a9-4602-4780-aa78-65fe95062ac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856761852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2856761852
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2329192726
Short name T74
Test name
Test status
Simulation time 185171710 ps
CPU time 9.81 seconds
Started Jun 06 12:27:19 PM PDT 24
Finished Jun 06 12:27:30 PM PDT 24
Peak memory 212900 kb
Host smart-83cc93da-f6af-4997-a292-a5e63d8d2ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329192726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2329192726
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.46578885
Short name T138
Test name
Test status
Simulation time 6613445932 ps
CPU time 29.68 seconds
Started Jun 06 12:27:10 PM PDT 24
Finished Jun 06 12:27:40 PM PDT 24
Peak memory 216632 kb
Host smart-7899e13e-0292-498b-b9dc-ab7addc92dbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46578885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 42.rom_ctrl_stress_all.46578885
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2866289853
Short name T261
Test name
Test status
Simulation time 121223258144 ps
CPU time 1019.43 seconds
Started Jun 06 12:27:19 PM PDT 24
Finished Jun 06 12:44:19 PM PDT 24
Peak memory 229852 kb
Host smart-a082a62e-31d8-41b5-a6bd-b471d99e018a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866289853 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2866289853
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1599789907
Short name T259
Test name
Test status
Simulation time 3206304111 ps
CPU time 9.45 seconds
Started Jun 06 12:27:19 PM PDT 24
Finished Jun 06 12:27:30 PM PDT 24
Peak memory 210816 kb
Host smart-ec3e4fbf-a577-40e4-863d-cdca752e7818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599789907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1599789907
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3589939696
Short name T323
Test name
Test status
Simulation time 27073035714 ps
CPU time 130.64 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:29:29 PM PDT 24
Peak memory 236484 kb
Host smart-4d8ee181-a66b-45d9-ad08-7888263496f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589939696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3589939696
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3861137396
Short name T41
Test name
Test status
Simulation time 1238682095 ps
CPU time 17.36 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:27:36 PM PDT 24
Peak memory 211476 kb
Host smart-907fe946-db9d-48d9-9ec4-17d8b9b3b8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861137396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3861137396
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2095051127
Short name T244
Test name
Test status
Simulation time 101038366 ps
CPU time 5.7 seconds
Started Jun 06 12:27:18 PM PDT 24
Finished Jun 06 12:27:25 PM PDT 24
Peak memory 210968 kb
Host smart-281c41ba-d66e-46e9-963d-9be57760b1d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095051127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2095051127
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2870867281
Short name T369
Test name
Test status
Simulation time 1200385874 ps
CPU time 13.95 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:27:36 PM PDT 24
Peak memory 213292 kb
Host smart-a085255c-0dc1-4406-ba8d-a0e690625511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870867281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2870867281
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2233277219
Short name T181
Test name
Test status
Simulation time 489137451 ps
CPU time 7.47 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:27:30 PM PDT 24
Peak memory 210808 kb
Host smart-b22f1eb5-0371-4363-b321-24936d35819b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233277219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2233277219
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1475979085
Short name T153
Test name
Test status
Simulation time 3918094415 ps
CPU time 10.53 seconds
Started Jun 06 12:27:16 PM PDT 24
Finished Jun 06 12:27:27 PM PDT 24
Peak memory 210756 kb
Host smart-1d588018-da4c-47fc-bbb8-9a4d2f967a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475979085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1475979085
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4112134791
Short name T150
Test name
Test status
Simulation time 2101939959 ps
CPU time 134.11 seconds
Started Jun 06 12:27:18 PM PDT 24
Finished Jun 06 12:29:33 PM PDT 24
Peak memory 212152 kb
Host smart-08954517-43c4-4163-979d-28a3338645cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112134791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.4112134791
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.4262657900
Short name T253
Test name
Test status
Simulation time 1610121115 ps
CPU time 18.93 seconds
Started Jun 06 12:27:20 PM PDT 24
Finished Jun 06 12:27:40 PM PDT 24
Peak memory 213968 kb
Host smart-ccb2a082-7fc0-46e6-a417-5afa100e3de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262657900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.4262657900
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.755728995
Short name T230
Test name
Test status
Simulation time 11071668378 ps
CPU time 9.51 seconds
Started Jun 06 12:27:22 PM PDT 24
Finished Jun 06 12:27:33 PM PDT 24
Peak memory 211004 kb
Host smart-999afd22-4432-430f-9186-59d002a6d02c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755728995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.755728995
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.228470541
Short name T69
Test name
Test status
Simulation time 4455953311 ps
CPU time 24.02 seconds
Started Jun 06 12:27:18 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 212900 kb
Host smart-c8d0fdbc-8da5-4cc2-b636-85ffd3c91b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228470541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.228470541
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1384575155
Short name T234
Test name
Test status
Simulation time 1561999190 ps
CPU time 16.9 seconds
Started Jun 06 12:27:19 PM PDT 24
Finished Jun 06 12:27:37 PM PDT 24
Peak memory 214692 kb
Host smart-fb7344c8-a015-4570-b7b2-50aad328906e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384575155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1384575155
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.976708795
Short name T309
Test name
Test status
Simulation time 14633920986 ps
CPU time 12.51 seconds
Started Jun 06 12:27:23 PM PDT 24
Finished Jun 06 12:27:37 PM PDT 24
Peak memory 210792 kb
Host smart-09e16a3d-2944-4c05-a8f0-99602ff4fbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976708795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.976708795
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1253500032
Short name T38
Test name
Test status
Simulation time 11407796515 ps
CPU time 140.27 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:29:43 PM PDT 24
Peak memory 233384 kb
Host smart-75c12c44-ff27-4939-b0f5-fcc399a62d97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253500032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1253500032
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1794838656
Short name T169
Test name
Test status
Simulation time 2363260685 ps
CPU time 9.2 seconds
Started Jun 06 12:27:16 PM PDT 24
Finished Jun 06 12:27:26 PM PDT 24
Peak memory 211600 kb
Host smart-8b4833e9-4452-44cf-8159-32de63b3f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794838656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1794838656
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.989115772
Short name T157
Test name
Test status
Simulation time 1333840849 ps
CPU time 12.55 seconds
Started Jun 06 12:27:20 PM PDT 24
Finished Jun 06 12:27:34 PM PDT 24
Peak memory 210880 kb
Host smart-0891d4dc-407f-496f-b904-105319fbdfb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=989115772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.989115772
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2797076540
Short name T216
Test name
Test status
Simulation time 4654293916 ps
CPU time 20.99 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:27:43 PM PDT 24
Peak memory 214632 kb
Host smart-46d1152f-0a24-4b8f-a75e-08dfae88acac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797076540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2797076540
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2189510685
Short name T129
Test name
Test status
Simulation time 1042298973 ps
CPU time 31.5 seconds
Started Jun 06 12:27:13 PM PDT 24
Finished Jun 06 12:27:45 PM PDT 24
Peak memory 215920 kb
Host smart-bd00ca9c-07d9-4c34-9108-b4b243655f5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189510685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2189510685
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2708632991
Short name T204
Test name
Test status
Simulation time 7299950097 ps
CPU time 15.44 seconds
Started Jun 06 12:27:31 PM PDT 24
Finished Jun 06 12:27:47 PM PDT 24
Peak memory 210860 kb
Host smart-029229c3-2e99-4e37-8146-f3b3ac2836fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708632991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2708632991
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3910853585
Short name T36
Test name
Test status
Simulation time 16110774337 ps
CPU time 196.42 seconds
Started Jun 06 12:27:20 PM PDT 24
Finished Jun 06 12:30:38 PM PDT 24
Peak memory 236696 kb
Host smart-69548ed8-e1a6-4efe-aa2f-dc70a3717967
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910853585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3910853585
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2508517182
Short name T263
Test name
Test status
Simulation time 4589008978 ps
CPU time 27.51 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:27:45 PM PDT 24
Peak memory 211812 kb
Host smart-b605062e-663b-4d7a-8c82-ac9ae72364e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508517182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2508517182
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1289755545
Short name T360
Test name
Test status
Simulation time 2599836891 ps
CPU time 8.91 seconds
Started Jun 06 12:27:20 PM PDT 24
Finished Jun 06 12:27:31 PM PDT 24
Peak memory 210944 kb
Host smart-bff0857e-ac18-40ed-8826-3a4ccdfd19a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289755545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1289755545
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.415600603
Short name T195
Test name
Test status
Simulation time 6247236805 ps
CPU time 27.48 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:27:50 PM PDT 24
Peak memory 213156 kb
Host smart-179d4575-4af4-4a37-a87f-04750892cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415600603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.415600603
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3969016528
Short name T89
Test name
Test status
Simulation time 4838565945 ps
CPU time 20.47 seconds
Started Jun 06 12:27:19 PM PDT 24
Finished Jun 06 12:27:41 PM PDT 24
Peak memory 212564 kb
Host smart-62a640af-cf84-46a0-bead-2117b02cc745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969016528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3969016528
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.336153148
Short name T313
Test name
Test status
Simulation time 28029836186 ps
CPU time 1056.1 seconds
Started Jun 06 12:27:22 PM PDT 24
Finished Jun 06 12:44:59 PM PDT 24
Peak memory 235464 kb
Host smart-cad5199d-87b1-4e5b-9de5-596111409440
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336153148 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.336153148
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1082417341
Short name T331
Test name
Test status
Simulation time 8596552819 ps
CPU time 15.85 seconds
Started Jun 06 12:27:24 PM PDT 24
Finished Jun 06 12:27:41 PM PDT 24
Peak memory 210820 kb
Host smart-c6b0856d-3b13-4020-bf6e-1603f16b7b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082417341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1082417341
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4266492141
Short name T334
Test name
Test status
Simulation time 4766217784 ps
CPU time 74.35 seconds
Started Jun 06 12:27:17 PM PDT 24
Finished Jun 06 12:28:33 PM PDT 24
Peak memory 237364 kb
Host smart-a6a7d139-e42c-4cc8-945b-988c0174e25a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266492141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4266492141
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1162838170
Short name T123
Test name
Test status
Simulation time 4106964539 ps
CPU time 22.6 seconds
Started Jun 06 12:27:14 PM PDT 24
Finished Jun 06 12:27:37 PM PDT 24
Peak memory 211484 kb
Host smart-cd0e1bd2-30f1-4352-b537-9505af82c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162838170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1162838170
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1166384959
Short name T60
Test name
Test status
Simulation time 774730497 ps
CPU time 7.99 seconds
Started Jun 06 12:27:13 PM PDT 24
Finished Jun 06 12:27:22 PM PDT 24
Peak memory 210956 kb
Host smart-c47b034c-d01f-46ae-9293-add6b13eaca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166384959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1166384959
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.701320639
Short name T269
Test name
Test status
Simulation time 5021568102 ps
CPU time 18.59 seconds
Started Jun 06 12:27:24 PM PDT 24
Finished Jun 06 12:27:44 PM PDT 24
Peak memory 213768 kb
Host smart-eff82ece-dee1-4b96-b74b-fe6ea0587153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701320639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.701320639
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.974999018
Short name T367
Test name
Test status
Simulation time 486064604 ps
CPU time 27.97 seconds
Started Jun 06 12:27:24 PM PDT 24
Finished Jun 06 12:27:53 PM PDT 24
Peak memory 218864 kb
Host smart-59f5edf8-00f2-404b-9c55-342cd3412a4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974999018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.974999018
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.752131347
Short name T164
Test name
Test status
Simulation time 1375189661 ps
CPU time 11.68 seconds
Started Jun 06 12:27:35 PM PDT 24
Finished Jun 06 12:27:48 PM PDT 24
Peak memory 210716 kb
Host smart-fe85ac25-6f4c-4559-9900-58834a073801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752131347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.752131347
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1550245021
Short name T166
Test name
Test status
Simulation time 20397099286 ps
CPU time 291.33 seconds
Started Jun 06 12:27:19 PM PDT 24
Finished Jun 06 12:32:11 PM PDT 24
Peak memory 238120 kb
Host smart-b6699e27-2de8-48bf-a932-de5d38cc9490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550245021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1550245021
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1572862828
Short name T42
Test name
Test status
Simulation time 175556520 ps
CPU time 9.2 seconds
Started Jun 06 12:27:23 PM PDT 24
Finished Jun 06 12:27:33 PM PDT 24
Peak memory 211556 kb
Host smart-776edc1b-5c50-40a5-b3b0-9e33c4f7afe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572862828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1572862828
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1194394343
Short name T347
Test name
Test status
Simulation time 3916658669 ps
CPU time 9.54 seconds
Started Jun 06 12:27:19 PM PDT 24
Finished Jun 06 12:27:30 PM PDT 24
Peak memory 211032 kb
Host smart-d002bbe6-d44e-44c2-9e33-60b99f1644cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194394343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1194394343
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1984770541
Short name T7
Test name
Test status
Simulation time 3238981619 ps
CPU time 33.91 seconds
Started Jun 06 12:27:18 PM PDT 24
Finished Jun 06 12:27:53 PM PDT 24
Peak memory 212696 kb
Host smart-85f4e150-29a5-451c-985b-c51c1f806a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984770541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1984770541
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1028413601
Short name T283
Test name
Test status
Simulation time 3251565177 ps
CPU time 34.23 seconds
Started Jun 06 12:27:38 PM PDT 24
Finished Jun 06 12:28:14 PM PDT 24
Peak memory 214460 kb
Host smart-8191f168-508a-42e9-8e7e-268d4850f36e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028413601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1028413601
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2558787028
Short name T189
Test name
Test status
Simulation time 22022182395 ps
CPU time 16.84 seconds
Started Jun 06 12:27:38 PM PDT 24
Finished Jun 06 12:27:56 PM PDT 24
Peak memory 210840 kb
Host smart-bc9a54dc-b451-4022-9e27-6e4f48386be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558787028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2558787028
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.375163784
Short name T348
Test name
Test status
Simulation time 46765908051 ps
CPU time 251.62 seconds
Started Jun 06 12:27:37 PM PDT 24
Finished Jun 06 12:31:50 PM PDT 24
Peak memory 237376 kb
Host smart-f12d8d7e-7af6-4e9f-b7ca-01e4c5ee4b08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375163784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.375163784
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1006265707
Short name T217
Test name
Test status
Simulation time 6836649688 ps
CPU time 28.85 seconds
Started Jun 06 12:27:37 PM PDT 24
Finished Jun 06 12:28:07 PM PDT 24
Peak memory 212444 kb
Host smart-256ada76-b1d5-42c4-8883-e8f4b18192e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006265707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1006265707
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1525942929
Short name T365
Test name
Test status
Simulation time 596381708 ps
CPU time 5.67 seconds
Started Jun 06 12:27:37 PM PDT 24
Finished Jun 06 12:27:43 PM PDT 24
Peak memory 210908 kb
Host smart-4c26d540-bd60-413a-8e93-53170a57be8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525942929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1525942929
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2881005465
Short name T196
Test name
Test status
Simulation time 182623361 ps
CPU time 9.34 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:27:32 PM PDT 24
Peak memory 213092 kb
Host smart-16bc19b9-ac20-498a-b48b-5d39e432058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881005465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2881005465
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.321441994
Short name T320
Test name
Test status
Simulation time 8406391304 ps
CPU time 40.69 seconds
Started Jun 06 12:27:24 PM PDT 24
Finished Jun 06 12:28:06 PM PDT 24
Peak memory 214508 kb
Host smart-2a4ab3af-f579-4b7d-b8f8-5aae3ced1bed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321441994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.321441994
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.287405778
Short name T93
Test name
Test status
Simulation time 74223152657 ps
CPU time 738.13 seconds
Started Jun 06 12:27:21 PM PDT 24
Finished Jun 06 12:39:41 PM PDT 24
Peak memory 235096 kb
Host smart-e0977f30-44f3-47b8-a2ff-027bbb75486e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287405778 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.287405778
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2224419107
Short name T295
Test name
Test status
Simulation time 8942467662 ps
CPU time 10.25 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:37 PM PDT 24
Peak memory 210672 kb
Host smart-7dbdf882-ff51-48ba-9fe7-8827dee787fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224419107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2224419107
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3665481385
Short name T324
Test name
Test status
Simulation time 43237943711 ps
CPU time 269.76 seconds
Started Jun 06 12:23:59 PM PDT 24
Finished Jun 06 12:28:30 PM PDT 24
Peak memory 229780 kb
Host smart-8d94a329-53a9-4f10-901c-b4c53ac51e7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665481385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3665481385
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3259335626
Short name T182
Test name
Test status
Simulation time 25715794572 ps
CPU time 23.1 seconds
Started Jun 06 12:26:27 PM PDT 24
Finished Jun 06 12:26:51 PM PDT 24
Peak memory 211724 kb
Host smart-1089b25d-989c-457c-847b-9f76bbc17194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259335626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3259335626
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3222370276
Short name T205
Test name
Test status
Simulation time 4833538383 ps
CPU time 11.7 seconds
Started Jun 06 12:28:14 PM PDT 24
Finished Jun 06 12:28:28 PM PDT 24
Peak memory 209104 kb
Host smart-b992c9c8-e59c-4cf8-9541-73ebc7350820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222370276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3222370276
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1062660169
Short name T73
Test name
Test status
Simulation time 2864996025 ps
CPU time 32.45 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:53 PM PDT 24
Peak memory 213440 kb
Host smart-7d4e3a09-42a8-4eea-b64c-170d6529e2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062660169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1062660169
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2323745052
Short name T301
Test name
Test status
Simulation time 280850335 ps
CPU time 15.67 seconds
Started Jun 06 12:26:19 PM PDT 24
Finished Jun 06 12:26:37 PM PDT 24
Peak memory 213564 kb
Host smart-53897ac2-cea5-483b-8767-c3a63975a547
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323745052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2323745052
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1707293895
Short name T155
Test name
Test status
Simulation time 3294257107 ps
CPU time 9.47 seconds
Started Jun 06 12:23:59 PM PDT 24
Finished Jun 06 12:24:10 PM PDT 24
Peak memory 208492 kb
Host smart-821365e0-4d07-4ce4-9bf4-06edf851f4b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707293895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1707293895
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.570973005
Short name T158
Test name
Test status
Simulation time 76093229397 ps
CPU time 355.04 seconds
Started Jun 06 12:24:00 PM PDT 24
Finished Jun 06 12:29:56 PM PDT 24
Peak memory 237164 kb
Host smart-02bc4f49-41fa-454e-b79b-ac138b11d9a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570973005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.570973005
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.475966645
Short name T213
Test name
Test status
Simulation time 640210850 ps
CPU time 9.06 seconds
Started Jun 06 12:27:52 PM PDT 24
Finished Jun 06 12:28:03 PM PDT 24
Peak memory 209848 kb
Host smart-383ed67c-3c4c-44c7-aa61-a627dc162aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475966645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.475966645
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.301624020
Short name T170
Test name
Test status
Simulation time 11265203296 ps
CPU time 17.52 seconds
Started Jun 06 12:28:15 PM PDT 24
Finished Jun 06 12:28:34 PM PDT 24
Peak memory 210732 kb
Host smart-6f5ebab9-bd21-4417-a605-196a6d5d3440
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301624020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.301624020
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4212193431
Short name T255
Test name
Test status
Simulation time 11233036443 ps
CPU time 28.49 seconds
Started Jun 06 12:26:27 PM PDT 24
Finished Jun 06 12:26:57 PM PDT 24
Peak memory 213284 kb
Host smart-6b8984a6-034c-4386-8349-a56d6198cb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212193431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4212193431
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2095639286
Short name T292
Test name
Test status
Simulation time 3462615355 ps
CPU time 34.52 seconds
Started Jun 06 12:23:59 PM PDT 24
Finished Jun 06 12:24:35 PM PDT 24
Peak memory 211840 kb
Host smart-ccde07e8-45df-408d-84c9-5f989dbcfac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095639286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2095639286
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2258343750
Short name T245
Test name
Test status
Simulation time 88242245 ps
CPU time 4.14 seconds
Started Jun 06 12:26:30 PM PDT 24
Finished Jun 06 12:26:36 PM PDT 24
Peak memory 210588 kb
Host smart-def3272f-1029-4975-8e2c-9e189ee09e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258343750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2258343750
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1464517963
Short name T345
Test name
Test status
Simulation time 9120946274 ps
CPU time 156.61 seconds
Started Jun 06 12:26:02 PM PDT 24
Finished Jun 06 12:28:39 PM PDT 24
Peak memory 224532 kb
Host smart-a6f0fdcf-722e-4c98-9c0e-8641f0027fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464517963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1464517963
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2165540708
Short name T237
Test name
Test status
Simulation time 13797898958 ps
CPU time 21.33 seconds
Started Jun 06 12:26:25 PM PDT 24
Finished Jun 06 12:26:48 PM PDT 24
Peak memory 211848 kb
Host smart-34fb9d41-aadc-4f8e-ab79-8b5210c92d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165540708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2165540708
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2452906493
Short name T92
Test name
Test status
Simulation time 17228021541 ps
CPU time 31.09 seconds
Started Jun 06 12:26:26 PM PDT 24
Finished Jun 06 12:26:59 PM PDT 24
Peak memory 213716 kb
Host smart-523a342e-b911-46c0-9401-f1fc974b061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452906493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2452906493
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.239572538
Short name T168
Test name
Test status
Simulation time 1161562384 ps
CPU time 14.79 seconds
Started Jun 06 12:23:59 PM PDT 24
Finished Jun 06 12:24:15 PM PDT 24
Peak memory 212532 kb
Host smart-fe55bcc3-0693-4d37-ab40-d2aa4fee8443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239572538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.239572538
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.896547290
Short name T279
Test name
Test status
Simulation time 1861931366 ps
CPU time 15.2 seconds
Started Jun 06 12:24:34 PM PDT 24
Finished Jun 06 12:24:49 PM PDT 24
Peak memory 210712 kb
Host smart-9f306903-cc28-49f2-94ff-d42cb4e3bdaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896547290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.896547290
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2675439171
Short name T239
Test name
Test status
Simulation time 43184381677 ps
CPU time 433.51 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:33:40 PM PDT 24
Peak memory 235044 kb
Host smart-7729e84d-defa-4ff2-8e3b-be0a915f7d92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675439171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2675439171
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1707660792
Short name T9
Test name
Test status
Simulation time 5183316838 ps
CPU time 24.65 seconds
Started Jun 06 12:26:15 PM PDT 24
Finished Jun 06 12:26:41 PM PDT 24
Peak memory 210660 kb
Host smart-67b59dff-16c6-4a88-b158-378090b248f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707660792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1707660792
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2388925627
Short name T339
Test name
Test status
Simulation time 96026401 ps
CPU time 5.14 seconds
Started Jun 06 12:26:24 PM PDT 24
Finished Jun 06 12:26:32 PM PDT 24
Peak memory 210368 kb
Host smart-6d767107-74f4-47b4-b4b5-3d7247c5dbf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388925627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2388925627
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1306050088
Short name T238
Test name
Test status
Simulation time 3177135661 ps
CPU time 32.39 seconds
Started Jun 06 12:26:30 PM PDT 24
Finished Jun 06 12:27:05 PM PDT 24
Peak memory 212416 kb
Host smart-a825cd25-71cf-4948-8315-2ec58d790c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306050088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1306050088
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.58871588
Short name T272
Test name
Test status
Simulation time 28044529255 ps
CPU time 33.17 seconds
Started Jun 06 12:26:02 PM PDT 24
Finished Jun 06 12:26:36 PM PDT 24
Peak memory 214404 kb
Host smart-0e380a8e-15c3-4444-bb36-26415a4866f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58871588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.rom_ctrl_stress_all.58871588
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2438444702
Short name T327
Test name
Test status
Simulation time 580539454 ps
CPU time 7.31 seconds
Started Jun 06 12:27:49 PM PDT 24
Finished Jun 06 12:27:58 PM PDT 24
Peak memory 209684 kb
Host smart-c00e6efe-82e4-49e3-ae9b-0dc459f7bb2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438444702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2438444702
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.11340628
Short name T30
Test name
Test status
Simulation time 81216216139 ps
CPU time 254.98 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:30:39 PM PDT 24
Peak memory 227908 kb
Host smart-8ae2c0ad-dbca-4fd8-b95b-892269a9bf68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11340628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_cor
rupt_sig_fatal_chk.11340628
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3070388676
Short name T286
Test name
Test status
Simulation time 3414794921 ps
CPU time 28.14 seconds
Started Jun 06 12:26:37 PM PDT 24
Finished Jun 06 12:27:06 PM PDT 24
Peak memory 211576 kb
Host smart-83c37fe3-3d52-48ca-9d88-f75e0d416151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070388676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3070388676
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1343541763
Short name T190
Test name
Test status
Simulation time 9442883926 ps
CPU time 17.32 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:41 PM PDT 24
Peak memory 208860 kb
Host smart-673f7106-154d-4a5c-90e1-583398783e69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1343541763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1343541763
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3611092596
Short name T225
Test name
Test status
Simulation time 438937186 ps
CPU time 13.15 seconds
Started Jun 06 12:26:21 PM PDT 24
Finished Jun 06 12:26:36 PM PDT 24
Peak memory 210060 kb
Host smart-dcd234bb-0355-49ff-8b32-dbc4330f09dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611092596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3611092596
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2453998595
Short name T335
Test name
Test status
Simulation time 6400891208 ps
CPU time 34.59 seconds
Started Jun 06 12:24:55 PM PDT 24
Finished Jun 06 12:25:30 PM PDT 24
Peak memory 215192 kb
Host smart-899276fc-774d-490a-bdc1-db6f2b376f93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453998595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2453998595
Directory /workspace/9.rom_ctrl_stress_all/latest
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