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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.31 96.89 92.13 97.72 100.00 98.62 97.45 98.37


Total test records in report: 469
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T303 /workspace/coverage/default/23.rom_ctrl_stress_all.2913185962 Jun 07 06:16:11 PM PDT 24 Jun 07 06:16:29 PM PDT 24 290088688 ps
T304 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2026806513 Jun 07 06:15:52 PM PDT 24 Jun 07 06:16:06 PM PDT 24 2541017463 ps
T305 /workspace/coverage/default/6.rom_ctrl_stress_all.2598780126 Jun 07 06:15:52 PM PDT 24 Jun 07 06:16:01 PM PDT 24 891024556 ps
T306 /workspace/coverage/default/40.rom_ctrl_stress_all.2948997868 Jun 07 06:16:15 PM PDT 24 Jun 07 06:16:27 PM PDT 24 1034045021 ps
T307 /workspace/coverage/default/21.rom_ctrl_alert_test.2155424495 Jun 07 06:16:04 PM PDT 24 Jun 07 06:16:19 PM PDT 24 1803030433 ps
T308 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3544533981 Jun 07 06:15:40 PM PDT 24 Jun 07 06:15:56 PM PDT 24 7847442232 ps
T309 /workspace/coverage/default/18.rom_ctrl_alert_test.3009174030 Jun 07 06:15:50 PM PDT 24 Jun 07 06:16:03 PM PDT 24 2547399695 ps
T310 /workspace/coverage/default/38.rom_ctrl_stress_all.3913411829 Jun 07 06:16:16 PM PDT 24 Jun 07 06:17:26 PM PDT 24 6712673555 ps
T311 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1088978791 Jun 07 06:15:42 PM PDT 24 Jun 07 06:15:48 PM PDT 24 508586188 ps
T312 /workspace/coverage/default/34.rom_ctrl_alert_test.3867221933 Jun 07 06:15:51 PM PDT 24 Jun 07 06:16:08 PM PDT 24 6767453749 ps
T313 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2828129292 Jun 07 06:15:16 PM PDT 24 Jun 07 06:19:14 PM PDT 24 21656844207 ps
T314 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2480660617 Jun 07 06:16:05 PM PDT 24 Jun 07 06:16:24 PM PDT 24 2171532299 ps
T315 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.70433835 Jun 07 06:16:42 PM PDT 24 Jun 07 06:33:29 PM PDT 24 24042381504 ps
T316 /workspace/coverage/default/4.rom_ctrl_smoke.3575761908 Jun 07 06:15:31 PM PDT 24 Jun 07 06:15:55 PM PDT 24 19589103069 ps
T317 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1658185120 Jun 07 06:16:04 PM PDT 24 Jun 07 06:20:09 PM PDT 24 93702580985 ps
T318 /workspace/coverage/default/33.rom_ctrl_alert_test.790043232 Jun 07 06:15:51 PM PDT 24 Jun 07 06:16:01 PM PDT 24 786450355 ps
T319 /workspace/coverage/default/22.rom_ctrl_smoke.3646123112 Jun 07 06:15:43 PM PDT 24 Jun 07 06:16:17 PM PDT 24 11917187481 ps
T320 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1881255668 Jun 07 06:15:33 PM PDT 24 Jun 07 06:17:42 PM PDT 24 15679752993 ps
T321 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4196122819 Jun 07 06:15:58 PM PDT 24 Jun 07 06:16:11 PM PDT 24 1208286207 ps
T322 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2741634212 Jun 07 06:15:50 PM PDT 24 Jun 07 06:17:00 PM PDT 24 2145188284 ps
T323 /workspace/coverage/default/49.rom_ctrl_smoke.1992468190 Jun 07 06:16:06 PM PDT 24 Jun 07 06:16:41 PM PDT 24 5213181079 ps
T324 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3907664577 Jun 07 06:16:07 PM PDT 24 Jun 07 06:16:19 PM PDT 24 3962709922 ps
T325 /workspace/coverage/default/29.rom_ctrl_alert_test.1321907166 Jun 07 06:15:49 PM PDT 24 Jun 07 06:15:59 PM PDT 24 928500990 ps
T326 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2616775983 Jun 07 06:16:04 PM PDT 24 Jun 07 06:16:19 PM PDT 24 7339162259 ps
T327 /workspace/coverage/default/47.rom_ctrl_stress_all.1238978567 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:40 PM PDT 24 11959460801 ps
T328 /workspace/coverage/default/26.rom_ctrl_alert_test.545175599 Jun 07 06:15:48 PM PDT 24 Jun 07 06:16:03 PM PDT 24 1746783273 ps
T329 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2878103258 Jun 07 06:15:42 PM PDT 24 Jun 07 06:15:52 PM PDT 24 693534644 ps
T330 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4022027100 Jun 07 06:15:19 PM PDT 24 Jun 07 06:15:28 PM PDT 24 341141044 ps
T331 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3218112040 Jun 07 06:15:50 PM PDT 24 Jun 07 06:16:02 PM PDT 24 990967514 ps
T332 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3668875175 Jun 07 06:15:45 PM PDT 24 Jun 07 06:15:59 PM PDT 24 2693953540 ps
T333 /workspace/coverage/default/46.rom_ctrl_smoke.4277853920 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:34 PM PDT 24 3775294931 ps
T334 /workspace/coverage/default/25.rom_ctrl_smoke.3177446348 Jun 07 06:15:48 PM PDT 24 Jun 07 06:15:58 PM PDT 24 191215213 ps
T335 /workspace/coverage/default/31.rom_ctrl_alert_test.763595779 Jun 07 06:16:04 PM PDT 24 Jun 07 06:16:19 PM PDT 24 6990681194 ps
T336 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4273536783 Jun 07 06:16:06 PM PDT 24 Jun 07 06:16:21 PM PDT 24 3388308912 ps
T337 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3985910988 Jun 07 06:15:51 PM PDT 24 Jun 07 06:16:13 PM PDT 24 3699894200 ps
T338 /workspace/coverage/default/39.rom_ctrl_smoke.2504100241 Jun 07 06:16:16 PM PDT 24 Jun 07 06:16:55 PM PDT 24 16775049796 ps
T339 /workspace/coverage/default/20.rom_ctrl_stress_all.882207690 Jun 07 06:15:43 PM PDT 24 Jun 07 06:15:53 PM PDT 24 799112532 ps
T340 /workspace/coverage/default/36.rom_ctrl_alert_test.3793288131 Jun 07 06:16:08 PM PDT 24 Jun 07 06:16:23 PM PDT 24 1832053674 ps
T16 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.145859003 Jun 07 06:15:17 PM PDT 24 Jun 07 06:26:02 PM PDT 24 62777909229 ps
T341 /workspace/coverage/default/31.rom_ctrl_smoke.4114682376 Jun 07 06:16:04 PM PDT 24 Jun 07 06:16:26 PM PDT 24 6915564442 ps
T342 /workspace/coverage/default/43.rom_ctrl_smoke.2723915406 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:33 PM PDT 24 3124648259 ps
T343 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2181929483 Jun 07 06:15:19 PM PDT 24 Jun 07 06:15:45 PM PDT 24 2635320320 ps
T344 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2008659606 Jun 07 06:15:46 PM PDT 24 Jun 07 07:54:57 PM PDT 24 79195007314 ps
T345 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1452701440 Jun 07 06:15:47 PM PDT 24 Jun 07 06:16:05 PM PDT 24 1615808517 ps
T346 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2345549524 Jun 07 06:16:44 PM PDT 24 Jun 07 06:17:19 PM PDT 24 4227526873 ps
T347 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2647981627 Jun 07 06:15:42 PM PDT 24 Jun 07 06:15:52 PM PDT 24 671077312 ps
T348 /workspace/coverage/default/29.rom_ctrl_smoke.1844326291 Jun 07 06:16:04 PM PDT 24 Jun 07 06:16:40 PM PDT 24 15559449016 ps
T349 /workspace/coverage/default/43.rom_ctrl_alert_test.2386728149 Jun 07 06:16:16 PM PDT 24 Jun 07 06:16:21 PM PDT 24 85491485 ps
T350 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.845472701 Jun 07 06:15:37 PM PDT 24 Jun 07 06:17:42 PM PDT 24 48139218709 ps
T351 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1887354041 Jun 07 06:16:07 PM PDT 24 Jun 07 06:16:14 PM PDT 24 95054685 ps
T352 /workspace/coverage/default/16.rom_ctrl_stress_all.1874575419 Jun 07 06:15:57 PM PDT 24 Jun 07 06:16:12 PM PDT 24 2846509308 ps
T353 /workspace/coverage/default/33.rom_ctrl_smoke.700519657 Jun 07 06:16:03 PM PDT 24 Jun 07 06:16:38 PM PDT 24 12384678016 ps
T354 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3947885084 Jun 07 06:15:52 PM PDT 24 Jun 07 06:16:17 PM PDT 24 2506257676 ps
T355 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.589502089 Jun 07 06:16:05 PM PDT 24 Jun 07 06:18:07 PM PDT 24 4341912846 ps
T356 /workspace/coverage/default/30.rom_ctrl_alert_test.897985246 Jun 07 06:16:06 PM PDT 24 Jun 07 06:16:18 PM PDT 24 1425697109 ps
T357 /workspace/coverage/default/30.rom_ctrl_stress_all.1190154988 Jun 07 06:15:47 PM PDT 24 Jun 07 06:16:23 PM PDT 24 44189189853 ps
T358 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3669656403 Jun 07 06:15:26 PM PDT 24 Jun 07 06:16:27 PM PDT 24 3883395413 ps
T359 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2580558178 Jun 07 06:16:07 PM PDT 24 Jun 07 06:22:55 PM PDT 24 44814122448 ps
T360 /workspace/coverage/default/7.rom_ctrl_stress_all.1569480128 Jun 07 06:15:18 PM PDT 24 Jun 07 06:16:23 PM PDT 24 5442515598 ps
T361 /workspace/coverage/default/5.rom_ctrl_smoke.2717441518 Jun 07 06:15:40 PM PDT 24 Jun 07 06:16:01 PM PDT 24 2569705608 ps
T362 /workspace/coverage/default/26.rom_ctrl_stress_all.643242155 Jun 07 06:16:06 PM PDT 24 Jun 07 06:17:17 PM PDT 24 7941429598 ps
T363 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3898784979 Jun 07 06:16:09 PM PDT 24 Jun 07 06:16:40 PM PDT 24 7170214890 ps
T364 /workspace/coverage/default/12.rom_ctrl_alert_test.3139952782 Jun 07 06:15:41 PM PDT 24 Jun 07 06:15:52 PM PDT 24 4679765241 ps
T365 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4037758884 Jun 07 06:15:43 PM PDT 24 Jun 07 07:01:43 PM PDT 24 70091479466 ps
T366 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2267318128 Jun 07 06:15:28 PM PDT 24 Jun 07 06:15:41 PM PDT 24 840260312 ps
T367 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2421757910 Jun 07 06:16:08 PM PDT 24 Jun 07 06:16:31 PM PDT 24 1310487945 ps
T368 /workspace/coverage/default/0.rom_ctrl_alert_test.954357230 Jun 07 06:15:37 PM PDT 24 Jun 07 06:15:42 PM PDT 24 214683858 ps
T369 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2089586998 Jun 07 06:15:44 PM PDT 24 Jun 07 06:18:14 PM PDT 24 16791738141 ps
T370 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1350405094 Jun 07 06:15:49 PM PDT 24 Jun 07 06:34:45 PM PDT 24 25128510820 ps
T371 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.616257888 Jun 07 06:16:42 PM PDT 24 Jun 07 06:16:56 PM PDT 24 1381692778 ps
T372 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2583033338 Jun 07 06:16:38 PM PDT 24 Jun 07 06:24:52 PM PDT 24 239708123183 ps
T373 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1926664352 Jun 07 06:15:18 PM PDT 24 Jun 07 06:15:44 PM PDT 24 2704215214 ps
T374 /workspace/coverage/default/47.rom_ctrl_smoke.2650377346 Jun 07 06:16:09 PM PDT 24 Jun 07 06:16:46 PM PDT 24 12431676868 ps
T375 /workspace/coverage/default/6.rom_ctrl_smoke.2338407742 Jun 07 06:15:57 PM PDT 24 Jun 07 06:16:16 PM PDT 24 2978911054 ps
T62 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3703853680 Jun 07 06:16:15 PM PDT 24 Jun 07 06:16:26 PM PDT 24 1836331930 ps
T376 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1844233836 Jun 07 06:16:04 PM PDT 24 Jun 07 06:16:16 PM PDT 24 1487235531 ps
T63 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3140627114 Jun 07 06:16:23 PM PDT 24 Jun 07 06:16:38 PM PDT 24 3404417207 ps
T64 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2170607174 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:28 PM PDT 24 8738205465 ps
T66 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1734509715 Jun 07 06:16:15 PM PDT 24 Jun 07 06:16:24 PM PDT 24 1189334622 ps
T377 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.323074577 Jun 07 06:16:37 PM PDT 24 Jun 07 06:16:43 PM PDT 24 387022807 ps
T59 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3620780348 Jun 07 06:16:07 PM PDT 24 Jun 07 06:16:47 PM PDT 24 845547590 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3840941367 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:19 PM PDT 24 182752588 ps
T67 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2473079969 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:20 PM PDT 24 3426402282 ps
T378 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.622270165 Jun 07 06:16:34 PM PDT 24 Jun 07 06:16:43 PM PDT 24 984659587 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1711791018 Jun 07 06:16:37 PM PDT 24 Jun 07 06:16:43 PM PDT 24 106233389 ps
T93 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3269669416 Jun 07 06:16:21 PM PDT 24 Jun 07 06:16:26 PM PDT 24 332965606 ps
T60 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1620087629 Jun 07 06:16:45 PM PDT 24 Jun 07 06:17:53 PM PDT 24 1673559302 ps
T100 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2380190200 Jun 07 06:16:31 PM PDT 24 Jun 07 06:18:10 PM PDT 24 13834315815 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4028800068 Jun 07 06:16:21 PM PDT 24 Jun 07 06:16:25 PM PDT 24 85596701 ps
T381 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.228827738 Jun 07 06:16:27 PM PDT 24 Jun 07 06:16:38 PM PDT 24 1346020967 ps
T382 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1322893052 Jun 07 06:16:32 PM PDT 24 Jun 07 06:16:53 PM PDT 24 7852547076 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1036898708 Jun 07 06:16:17 PM PDT 24 Jun 07 06:16:34 PM PDT 24 8366920934 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1630882221 Jun 07 06:16:45 PM PDT 24 Jun 07 06:16:57 PM PDT 24 643837949 ps
T61 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.944475701 Jun 07 06:16:24 PM PDT 24 Jun 07 06:17:41 PM PDT 24 18369943555 ps
T94 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3725597735 Jun 07 06:16:21 PM PDT 24 Jun 07 06:16:38 PM PDT 24 16647428822 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1206917234 Jun 07 06:16:24 PM PDT 24 Jun 07 06:17:02 PM PDT 24 187478554 ps
T385 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2749853593 Jun 07 06:16:15 PM PDT 24 Jun 07 06:16:25 PM PDT 24 2810315051 ps
T120 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3742424032 Jun 07 06:16:33 PM PDT 24 Jun 07 06:17:43 PM PDT 24 2484713137 ps
T68 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3748430796 Jun 07 06:16:19 PM PDT 24 Jun 07 06:17:22 PM PDT 24 41945820682 ps
T386 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4177129271 Jun 07 06:16:32 PM PDT 24 Jun 07 06:16:44 PM PDT 24 854295814 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1994142394 Jun 07 06:16:07 PM PDT 24 Jun 07 06:16:40 PM PDT 24 1382249969 ps
T111 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3475147301 Jun 07 06:16:29 PM PDT 24 Jun 07 06:17:15 PM PDT 24 2010363495 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4168823915 Jun 07 06:16:08 PM PDT 24 Jun 07 06:16:15 PM PDT 24 517490350 ps
T70 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1858159083 Jun 07 06:16:23 PM PDT 24 Jun 07 06:16:36 PM PDT 24 2772401618 ps
T71 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.603338638 Jun 07 06:16:35 PM PDT 24 Jun 07 06:16:39 PM PDT 24 167961776 ps
T72 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.781586479 Jun 07 06:16:06 PM PDT 24 Jun 07 06:16:21 PM PDT 24 3258781540 ps
T388 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3786915817 Jun 07 06:16:23 PM PDT 24 Jun 07 06:16:33 PM PDT 24 1146253539 ps
T389 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.21274180 Jun 07 06:16:33 PM PDT 24 Jun 07 06:16:52 PM PDT 24 1533249375 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1082918879 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:32 PM PDT 24 4012310059 ps
T123 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2858366974 Jun 07 06:16:13 PM PDT 24 Jun 07 06:16:59 PM PDT 24 1733335495 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2331355511 Jun 07 06:16:18 PM PDT 24 Jun 07 06:17:33 PM PDT 24 3573573810 ps
T391 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3816387662 Jun 07 06:16:25 PM PDT 24 Jun 07 06:16:37 PM PDT 24 2889404332 ps
T73 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.466232929 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:23 PM PDT 24 1050367950 ps
T115 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3768587616 Jun 07 06:16:09 PM PDT 24 Jun 07 06:16:51 PM PDT 24 1034633849 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3412631947 Jun 07 06:16:11 PM PDT 24 Jun 07 06:16:27 PM PDT 24 1757585206 ps
T393 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1525665739 Jun 07 06:16:17 PM PDT 24 Jun 07 06:16:28 PM PDT 24 1166250387 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2523449246 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:22 PM PDT 24 4546024705 ps
T395 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4270980045 Jun 07 06:16:23 PM PDT 24 Jun 07 06:16:35 PM PDT 24 1191793842 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3162312021 Jun 07 06:16:24 PM PDT 24 Jun 07 06:16:32 PM PDT 24 1196521519 ps
T106 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.128229411 Jun 07 06:16:17 PM PDT 24 Jun 07 06:16:57 PM PDT 24 3610905998 ps
T74 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2162456842 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:29 PM PDT 24 2040777320 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3927107030 Jun 07 06:16:07 PM PDT 24 Jun 07 06:16:14 PM PDT 24 864914499 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4218159379 Jun 07 06:16:15 PM PDT 24 Jun 07 06:16:23 PM PDT 24 1163631646 ps
T107 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.992296230 Jun 07 06:16:43 PM PDT 24 Jun 07 06:17:48 PM PDT 24 15775142175 ps
T113 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3337316310 Jun 07 06:16:16 PM PDT 24 Jun 07 06:17:02 PM PDT 24 1626842406 ps
T108 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3476344745 Jun 07 06:16:15 PM PDT 24 Jun 07 06:16:42 PM PDT 24 2266629285 ps
T398 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.855620817 Jun 07 06:16:22 PM PDT 24 Jun 07 06:17:39 PM PDT 24 8178935888 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.443771889 Jun 07 06:16:04 PM PDT 24 Jun 07 06:16:16 PM PDT 24 1157387825 ps
T121 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3248019121 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:51 PM PDT 24 391344342 ps
T400 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.589424737 Jun 07 06:16:31 PM PDT 24 Jun 07 06:16:36 PM PDT 24 408269737 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.672256264 Jun 07 06:16:17 PM PDT 24 Jun 07 06:16:22 PM PDT 24 111221122 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2420926367 Jun 07 06:16:05 PM PDT 24 Jun 07 06:16:24 PM PDT 24 8784076934 ps
T76 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2009605543 Jun 07 06:16:09 PM PDT 24 Jun 07 06:16:14 PM PDT 24 88908956 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3086280606 Jun 07 06:16:13 PM PDT 24 Jun 07 06:17:15 PM PDT 24 21794076721 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3091535639 Jun 07 06:16:05 PM PDT 24 Jun 07 06:16:19 PM PDT 24 13044261665 ps
T96 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3519290288 Jun 07 06:16:13 PM PDT 24 Jun 07 06:16:18 PM PDT 24 85638132 ps
T404 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2990472141 Jun 07 06:16:14 PM PDT 24 Jun 07 06:16:28 PM PDT 24 6938149294 ps
T97 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1095519292 Jun 07 06:16:35 PM PDT 24 Jun 07 06:16:52 PM PDT 24 10269415879 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3107009487 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:24 PM PDT 24 872286996 ps
T406 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1886468014 Jun 07 06:16:16 PM PDT 24 Jun 07 06:16:35 PM PDT 24 8344642584 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3148433148 Jun 07 06:16:39 PM PDT 24 Jun 07 06:16:55 PM PDT 24 7805607371 ps
T98 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.551751842 Jun 07 06:16:19 PM PDT 24 Jun 07 06:16:36 PM PDT 24 2946873529 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1028397304 Jun 07 06:16:22 PM PDT 24 Jun 07 06:16:34 PM PDT 24 2552541796 ps
T118 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3170883815 Jun 07 06:16:29 PM PDT 24 Jun 07 06:17:46 PM PDT 24 3792684699 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1390442953 Jun 07 06:16:11 PM PDT 24 Jun 07 06:16:16 PM PDT 24 85668482 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4133357096 Jun 07 06:16:19 PM PDT 24 Jun 07 06:16:24 PM PDT 24 91094443 ps
T78 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.700596845 Jun 07 06:16:35 PM PDT 24 Jun 07 06:16:48 PM PDT 24 5283545072 ps
T116 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4052643942 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:51 PM PDT 24 1401478941 ps
T411 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2598474504 Jun 07 06:16:35 PM PDT 24 Jun 07 06:16:51 PM PDT 24 6116099971 ps
T412 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1307956998 Jun 07 06:16:44 PM PDT 24 Jun 07 06:17:01 PM PDT 24 1338043146 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.158501597 Jun 07 06:16:09 PM PDT 24 Jun 07 06:16:15 PM PDT 24 89148958 ps
T99 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1478712960 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:22 PM PDT 24 1250121252 ps
T414 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.941236361 Jun 07 06:16:05 PM PDT 24 Jun 07 06:17:42 PM PDT 24 19884384644 ps
T415 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1699450015 Jun 07 06:16:16 PM PDT 24 Jun 07 06:16:20 PM PDT 24 85636434 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1972304884 Jun 07 06:16:41 PM PDT 24 Jun 07 06:17:49 PM PDT 24 32536206187 ps
T82 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2098596355 Jun 07 06:16:46 PM PDT 24 Jun 07 06:17:25 PM PDT 24 3299984698 ps
T416 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2008493111 Jun 07 06:16:19 PM PDT 24 Jun 07 06:16:31 PM PDT 24 2593649393 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1299676397 Jun 07 06:16:11 PM PDT 24 Jun 07 06:16:28 PM PDT 24 5628327581 ps
T418 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1349421037 Jun 07 06:16:36 PM PDT 24 Jun 07 06:16:48 PM PDT 24 2922782539 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4034178822 Jun 07 06:16:06 PM PDT 24 Jun 07 06:16:17 PM PDT 24 979722386 ps
T119 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3050915481 Jun 07 06:16:32 PM PDT 24 Jun 07 06:17:17 PM PDT 24 1574582889 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.768785973 Jun 07 06:16:04 PM PDT 24 Jun 07 06:16:16 PM PDT 24 1343880509 ps
T421 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1523412398 Jun 07 06:16:06 PM PDT 24 Jun 07 06:16:27 PM PDT 24 1443077409 ps
T422 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2040767426 Jun 07 06:16:26 PM PDT 24 Jun 07 06:16:41 PM PDT 24 6568496889 ps
T423 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2639401193 Jun 07 06:16:18 PM PDT 24 Jun 07 06:16:37 PM PDT 24 2223543371 ps
T424 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1374921984 Jun 07 06:16:08 PM PDT 24 Jun 07 06:16:26 PM PDT 24 18225103924 ps
T83 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1558097455 Jun 07 06:16:11 PM PDT 24 Jun 07 06:16:40 PM PDT 24 12208131799 ps
T425 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3811484733 Jun 07 06:16:26 PM PDT 24 Jun 07 06:16:38 PM PDT 24 981404769 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.973359 Jun 07 06:16:17 PM PDT 24 Jun 07 06:16:27 PM PDT 24 3452297564 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3902182724 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:16 PM PDT 24 379357401 ps
T79 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1542842592 Jun 07 06:16:16 PM PDT 24 Jun 07 06:16:35 PM PDT 24 722970064 ps
T428 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1776297320 Jun 07 06:16:23 PM PDT 24 Jun 07 06:16:29 PM PDT 24 565355594 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2103326485 Jun 07 06:16:19 PM PDT 24 Jun 07 06:16:29 PM PDT 24 2143338847 ps
T117 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4029399553 Jun 07 06:16:17 PM PDT 24 Jun 07 06:17:31 PM PDT 24 1380754933 ps
T430 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.338513418 Jun 07 06:16:09 PM PDT 24 Jun 07 06:16:15 PM PDT 24 91589433 ps
T431 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4040474737 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:22 PM PDT 24 3839733781 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4206990459 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:38 PM PDT 24 4920933889 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3484363437 Jun 07 06:16:11 PM PDT 24 Jun 07 06:16:20 PM PDT 24 2622653969 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3835676222 Jun 07 06:16:06 PM PDT 24 Jun 07 06:16:19 PM PDT 24 3122890123 ps
T435 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3329616467 Jun 07 06:16:26 PM PDT 24 Jun 07 06:16:32 PM PDT 24 451421520 ps
T436 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.72121819 Jun 07 06:16:18 PM PDT 24 Jun 07 06:16:29 PM PDT 24 2341366856 ps
T124 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3513542111 Jun 07 06:16:31 PM PDT 24 Jun 07 06:17:13 PM PDT 24 1876281766 ps
T437 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.737058224 Jun 07 06:16:42 PM PDT 24 Jun 07 06:17:50 PM PDT 24 1939001485 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3206249741 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:23 PM PDT 24 5446381971 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2016214251 Jun 07 06:16:09 PM PDT 24 Jun 07 06:16:14 PM PDT 24 172022974 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.415845368 Jun 07 06:16:44 PM PDT 24 Jun 07 06:17:04 PM PDT 24 2135968482 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3020371322 Jun 07 06:16:07 PM PDT 24 Jun 07 06:16:20 PM PDT 24 1155678716 ps
T442 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4110624662 Jun 07 06:16:34 PM PDT 24 Jun 07 06:16:49 PM PDT 24 13050439783 ps
T443 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2481278088 Jun 07 06:16:08 PM PDT 24 Jun 07 06:16:16 PM PDT 24 346370128 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1784703701 Jun 07 06:16:11 PM PDT 24 Jun 07 06:16:16 PM PDT 24 278241974 ps
T445 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1686312966 Jun 07 06:16:15 PM PDT 24 Jun 07 06:16:30 PM PDT 24 1204821147 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1288666289 Jun 07 06:16:08 PM PDT 24 Jun 07 06:16:22 PM PDT 24 1384995931 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3300048857 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:21 PM PDT 24 1169667434 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2409407126 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:24 PM PDT 24 13698158886 ps
T449 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4115465399 Jun 07 06:16:26 PM PDT 24 Jun 07 06:16:40 PM PDT 24 7038620406 ps
T450 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1534903400 Jun 07 06:16:22 PM PDT 24 Jun 07 06:16:43 PM PDT 24 2102792309 ps
T451 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2739402680 Jun 07 06:16:11 PM PDT 24 Jun 07 06:17:04 PM PDT 24 12032944801 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3994585476 Jun 07 06:16:07 PM PDT 24 Jun 07 06:16:13 PM PDT 24 100388994 ps
T453 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.736485514 Jun 07 06:16:09 PM PDT 24 Jun 07 06:16:18 PM PDT 24 8221249035 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2816674705 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:19 PM PDT 24 2296497543 ps
T455 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1204645940 Jun 07 06:16:44 PM PDT 24 Jun 07 06:16:57 PM PDT 24 5757766176 ps
T456 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2634293302 Jun 07 06:16:20 PM PDT 24 Jun 07 06:16:30 PM PDT 24 149213799 ps
T109 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1600232238 Jun 07 06:16:24 PM PDT 24 Jun 07 06:17:39 PM PDT 24 8216131310 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.439273938 Jun 07 06:16:17 PM PDT 24 Jun 07 06:17:30 PM PDT 24 1339286919 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3712888489 Jun 07 06:16:29 PM PDT 24 Jun 07 06:16:41 PM PDT 24 2093268860 ps
T458 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3207239017 Jun 07 06:16:08 PM PDT 24 Jun 07 06:16:28 PM PDT 24 1726656994 ps
T459 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.96441681 Jun 07 06:16:24 PM PDT 24 Jun 07 06:17:14 PM PDT 24 9623188514 ps
T460 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1393129259 Jun 07 06:16:09 PM PDT 24 Jun 07 06:16:19 PM PDT 24 161484168 ps
T461 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2256513507 Jun 07 06:16:17 PM PDT 24 Jun 07 06:16:22 PM PDT 24 85419942 ps
T462 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.785022345 Jun 07 06:16:10 PM PDT 24 Jun 07 06:16:25 PM PDT 24 986727846 ps
T463 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1316299572 Jun 07 06:16:11 PM PDT 24 Jun 07 06:16:39 PM PDT 24 2223856049 ps
T464 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.970755202 Jun 07 06:16:07 PM PDT 24 Jun 07 06:16:25 PM PDT 24 6296825044 ps
T465 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3580735647 Jun 07 06:16:13 PM PDT 24 Jun 07 06:16:22 PM PDT 24 735131941 ps
T122 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1358154158 Jun 07 06:16:05 PM PDT 24 Jun 07 06:16:52 PM PDT 24 3176050864 ps
T466 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1150974004 Jun 07 06:16:13 PM PDT 24 Jun 07 06:16:24 PM PDT 24 4242010178 ps
T467 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.135990607 Jun 07 06:16:06 PM PDT 24 Jun 07 06:16:51 PM PDT 24 6217455839 ps
T468 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3553189181 Jun 07 06:16:11 PM PDT 24 Jun 07 06:16:30 PM PDT 24 1882891516 ps
T80 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2026251150 Jun 07 06:16:46 PM PDT 24 Jun 07 06:17:29 PM PDT 24 4182297343 ps
T469 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.948901208 Jun 07 06:16:12 PM PDT 24 Jun 07 06:16:25 PM PDT 24 4277712766 ps

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4140112081
Short name T10
Test name
Test status
Simulation time 129746404342 ps
CPU time 311.86 seconds
Started Jun 07 06:16:02 PM PDT 24
Finished Jun 07 06:21:14 PM PDT 24
Peak memory 233356 kb
Host smart-20f13261-99c5-43db-9c59-ff9738dbda57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140112081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4140112081
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1830105503
Short name T11
Test name
Test status
Simulation time 60452126128 ps
CPU time 558.69 seconds
Started Jun 07 06:15:54 PM PDT 24
Finished Jun 07 06:25:13 PM PDT 24
Peak memory 234424 kb
Host smart-f076f089-5108-4488-9a8c-0d38964dbeda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830105503 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1830105503
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3704595221
Short name T225
Test name
Test status
Simulation time 228279771037 ps
CPU time 393.32 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:22:42 PM PDT 24
Peak memory 237480 kb
Host smart-8855e981-2f5a-491e-b40c-5706814e4551
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704595221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3704595221
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.40497610
Short name T19
Test name
Test status
Simulation time 2766416473 ps
CPU time 30.7 seconds
Started Jun 07 06:16:13 PM PDT 24
Finished Jun 07 06:16:44 PM PDT 24
Peak memory 213012 kb
Host smart-5b51f8f0-ae59-4ff1-95c0-b4e1f268428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40497610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.40497610
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3620780348
Short name T59
Test name
Test status
Simulation time 845547590 ps
CPU time 39.17 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:47 PM PDT 24
Peak memory 211220 kb
Host smart-1481e25a-97b3-45a0-88cf-151efc44cb0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620780348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3620780348
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4074658476
Short name T22
Test name
Test status
Simulation time 2230257376 ps
CPU time 111.18 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:17:57 PM PDT 24
Peak memory 238424 kb
Host smart-4f29f799-a2d9-4a53-b3ec-6f56e710ff36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074658476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4074658476
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1994142394
Short name T69
Test name
Test status
Simulation time 1382249969 ps
CPU time 27.4 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:40 PM PDT 24
Peak memory 210836 kb
Host smart-69d49a74-81fa-46a6-a873-9f17d0da0033
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994142394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1994142394
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.439273938
Short name T114
Test name
Test status
Simulation time 1339286919 ps
CPU time 72.32 seconds
Started Jun 07 06:16:17 PM PDT 24
Finished Jun 07 06:17:30 PM PDT 24
Peak memory 219068 kb
Host smart-340bef81-0841-4ce6-bfed-f99ba2ad5e49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439273938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.439273938
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1263901116
Short name T48
Test name
Test status
Simulation time 27298713786 ps
CPU time 1021.04 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:33:07 PM PDT 24
Peak memory 235476 kb
Host smart-fd658d00-412a-4bf2-8b71-d640746e5150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263901116 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1263901116
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3479510118
Short name T58
Test name
Test status
Simulation time 19026191753 ps
CPU time 12.41 seconds
Started Jun 07 06:15:27 PM PDT 24
Finished Jun 07 06:15:45 PM PDT 24
Peak memory 210204 kb
Host smart-0696b680-a575-45ea-b659-406ba4509010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479510118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3479510118
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2043671720
Short name T1
Test name
Test status
Simulation time 663671027 ps
CPU time 9.13 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:02 PM PDT 24
Peak memory 211544 kb
Host smart-01d53640-00a5-45bf-9c2b-af278efe2e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043671720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2043671720
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.444933935
Short name T135
Test name
Test status
Simulation time 5159660715 ps
CPU time 18.36 seconds
Started Jun 07 06:15:56 PM PDT 24
Finished Jun 07 06:16:15 PM PDT 24
Peak memory 212084 kb
Host smart-100c9808-a03e-4cf5-b032-e8dbf964f1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444933935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.444933935
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1860018731
Short name T45
Test name
Test status
Simulation time 1794852584 ps
CPU time 20.2 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:07 PM PDT 24
Peak memory 211672 kb
Host smart-ac758b5d-695c-4715-979e-aa16938d7bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860018731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1860018731
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2691249518
Short name T173
Test name
Test status
Simulation time 128345826775 ps
CPU time 315.48 seconds
Started Jun 07 06:15:44 PM PDT 24
Finished Jun 07 06:20:59 PM PDT 24
Peak memory 237348 kb
Host smart-7d92ceb2-8eea-48de-92b1-184023eed4a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691249518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2691249518
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.96441681
Short name T459
Test name
Test status
Simulation time 9623188514 ps
CPU time 49.38 seconds
Started Jun 07 06:16:24 PM PDT 24
Finished Jun 07 06:17:14 PM PDT 24
Peak memory 211988 kb
Host smart-fff8083b-b5ea-487e-b763-830d166bf3ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96441681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pass
thru_mem_tl_intg_err.96441681
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.944475701
Short name T61
Test name
Test status
Simulation time 18369943555 ps
CPU time 76.52 seconds
Started Jun 07 06:16:24 PM PDT 24
Finished Jun 07 06:17:41 PM PDT 24
Peak memory 219160 kb
Host smart-9769eb8c-6495-475b-b91b-b25fe5ca6213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944475701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.944475701
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4052643942
Short name T116
Test name
Test status
Simulation time 1401478941 ps
CPU time 38.48 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:51 PM PDT 24
Peak memory 219068 kb
Host smart-34df3f21-395f-41b2-a7dd-6a83611fa875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052643942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4052643942
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3337316310
Short name T113
Test name
Test status
Simulation time 1626842406 ps
CPU time 45.19 seconds
Started Jun 07 06:16:16 PM PDT 24
Finished Jun 07 06:17:02 PM PDT 24
Peak memory 219040 kb
Host smart-47d8df7d-5047-4622-a4dd-54a143f023c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337316310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3337316310
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.781586479
Short name T72
Test name
Test status
Simulation time 3258781540 ps
CPU time 14.02 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:21 PM PDT 24
Peak memory 218468 kb
Host smart-ea1463c3-2983-461d-b16c-98fc4820e171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781586479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.781586479
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1570284598
Short name T84
Test name
Test status
Simulation time 1983112898 ps
CPU time 17.27 seconds
Started Jun 07 06:15:56 PM PDT 24
Finished Jun 07 06:16:14 PM PDT 24
Peak memory 210852 kb
Host smart-20c6db49-ed44-4d17-9df9-ef09cf5bb27d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570284598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1570284598
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1309342779
Short name T15
Test name
Test status
Simulation time 5455777600 ps
CPU time 185.39 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:19:16 PM PDT 24
Peak memory 219360 kb
Host smart-1914d33f-466c-43af-a1db-5ba467490011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309342779 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1309342779
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2170607174
Short name T64
Test name
Test status
Simulation time 8738205465 ps
CPU time 15.68 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:28 PM PDT 24
Peak memory 210884 kb
Host smart-d70e96f5-26e5-49a5-9824-bbebf7998f02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170607174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2170607174
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4168823915
Short name T387
Test name
Test status
Simulation time 517490350 ps
CPU time 6.29 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:15 PM PDT 24
Peak memory 217880 kb
Host smart-12c5c9dd-fca7-4138-a837-54a717e6c6fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168823915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4168823915
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1082918879
Short name T390
Test name
Test status
Simulation time 4012310059 ps
CPU time 19.55 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:32 PM PDT 24
Peak memory 218984 kb
Host smart-ca02b99a-5500-4364-8585-05515ddaec19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082918879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1082918879
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3412631947
Short name T392
Test name
Test status
Simulation time 1757585206 ps
CPU time 14.59 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:27 PM PDT 24
Peak memory 218932 kb
Host smart-559d49b8-503e-4c38-a3a6-13a419504f07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412631947 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3412631947
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.158501597
Short name T413
Test name
Test status
Simulation time 89148958 ps
CPU time 4.16 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:15 PM PDT 24
Peak memory 210896 kb
Host smart-64d73728-a91b-4310-89f9-338b8d63d3e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158501597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.158501597
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.338513418
Short name T430
Test name
Test status
Simulation time 91589433 ps
CPU time 4.28 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:15 PM PDT 24
Peak memory 210640 kb
Host smart-b41f2288-52b5-4450-a7b0-2200a6a6ef06
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338513418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.338513418
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3994585476
Short name T452
Test name
Test status
Simulation time 100388994 ps
CPU time 4.19 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:13 PM PDT 24
Peak memory 210692 kb
Host smart-b80cbd98-1d91-4660-85ee-56a54fa23937
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994585476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3994585476
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2098596355
Short name T82
Test name
Test status
Simulation time 3299984698 ps
CPU time 38.13 seconds
Started Jun 07 06:16:46 PM PDT 24
Finished Jun 07 06:17:25 PM PDT 24
Peak memory 211000 kb
Host smart-832e7ee4-4d16-4cbc-984c-ffc7de714fdc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098596355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2098596355
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1299676397
Short name T417
Test name
Test status
Simulation time 5628327581 ps
CPU time 15.6 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:28 PM PDT 24
Peak memory 219020 kb
Host smart-6613d966-6573-42be-9a65-c5223d779662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299676397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1299676397
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3091535639
Short name T403
Test name
Test status
Simulation time 13044261665 ps
CPU time 13.14 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 211064 kb
Host smart-d156327f-1e6c-4cd9-be1f-8a3cb71a8198
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091535639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3091535639
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2103326485
Short name T429
Test name
Test status
Simulation time 2143338847 ps
CPU time 9.53 seconds
Started Jun 07 06:16:19 PM PDT 24
Finished Jun 07 06:16:29 PM PDT 24
Peak memory 210928 kb
Host smart-c66a8ce9-b361-4cd6-9b5c-6c33729657b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103326485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2103326485
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.466232929
Short name T73
Test name
Test status
Simulation time 1050367950 ps
CPU time 11.98 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 218428 kb
Host smart-a99c8b5a-31f0-4eaa-b566-2de08aa0aecc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466232929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.466232929
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.672256264
Short name T401
Test name
Test status
Simulation time 111221122 ps
CPU time 5.06 seconds
Started Jun 07 06:16:17 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 219064 kb
Host smart-3828b4a7-3cf7-4035-911d-f852d37d5c13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672256264 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.672256264
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4034178822
Short name T419
Test name
Test status
Simulation time 979722386 ps
CPU time 9.72 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:17 PM PDT 24
Peak memory 210844 kb
Host smart-5cc284eb-e27c-4d72-a9c9-059b87d32434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034178822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4034178822
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2409407126
Short name T448
Test name
Test status
Simulation time 13698158886 ps
CPU time 11.36 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 210688 kb
Host smart-888702d9-a043-4804-83ff-064a4605469a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409407126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2409407126
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3206249741
Short name T438
Test name
Test status
Simulation time 5446381971 ps
CPU time 11.89 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 210640 kb
Host smart-cbda74dd-2088-4897-85a8-fbb6cd95dd3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206249741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3206249741
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.948901208
Short name T469
Test name
Test status
Simulation time 4277712766 ps
CPU time 11.43 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:25 PM PDT 24
Peak memory 219088 kb
Host smart-49852c55-a1a1-45c0-82c5-03a77835aa3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948901208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.948901208
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.768785973
Short name T420
Test name
Test status
Simulation time 1343880509 ps
CPU time 12.13 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 218680 kb
Host smart-b98128da-376e-4620-bd07-939265e3220c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768785973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.768785973
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2990472141
Short name T404
Test name
Test status
Simulation time 6938149294 ps
CPU time 13.31 seconds
Started Jun 07 06:16:14 PM PDT 24
Finished Jun 07 06:16:28 PM PDT 24
Peak memory 219084 kb
Host smart-d61c646a-6fa8-43ed-a475-2776b7b04225
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990472141 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2990472141
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.970755202
Short name T464
Test name
Test status
Simulation time 6296825044 ps
CPU time 16.19 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:25 PM PDT 24
Peak memory 219032 kb
Host smart-5feeb518-e4fc-42dc-bc55-f84e37349ead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970755202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.970755202
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3476344745
Short name T108
Test name
Test status
Simulation time 2266629285 ps
CPU time 27.44 seconds
Started Jun 07 06:16:15 PM PDT 24
Finished Jun 07 06:16:42 PM PDT 24
Peak memory 210964 kb
Host smart-1e32b45c-4d47-4bb7-9b9a-ca229c045118
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476344745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3476344745
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.736485514
Short name T453
Test name
Test status
Simulation time 8221249035 ps
CPU time 7.7 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:18 PM PDT 24
Peak memory 210964 kb
Host smart-6ddbe220-99e3-4b68-a8ed-13b541250e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736485514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.736485514
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2481278088
Short name T443
Test name
Test status
Simulation time 346370128 ps
CPU time 6.88 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 218928 kb
Host smart-a5e70f87-31a0-4fb4-b7e1-11074b8eb2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481278088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2481278088
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.737058224
Short name T437
Test name
Test status
Simulation time 1939001485 ps
CPU time 67.25 seconds
Started Jun 07 06:16:42 PM PDT 24
Finished Jun 07 06:17:50 PM PDT 24
Peak memory 219044 kb
Host smart-ceb1fc57-035f-4f92-a69c-3c09c93c0faa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737058224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.737058224
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1711791018
Short name T379
Test name
Test status
Simulation time 106233389 ps
CPU time 5.2 seconds
Started Jun 07 06:16:37 PM PDT 24
Finished Jun 07 06:16:43 PM PDT 24
Peak memory 219124 kb
Host smart-beb4e4ab-e4d6-4860-bd3f-e0b68f87183f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711791018 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1711791018
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4270980045
Short name T395
Test name
Test status
Simulation time 1191793842 ps
CPU time 11.93 seconds
Started Jun 07 06:16:23 PM PDT 24
Finished Jun 07 06:16:35 PM PDT 24
Peak memory 211012 kb
Host smart-17994c95-dec7-4c4d-b5e6-d95cbf86fcc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270980045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4270980045
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2739402680
Short name T451
Test name
Test status
Simulation time 12032944801 ps
CPU time 52.31 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:17:04 PM PDT 24
Peak memory 210948 kb
Host smart-0248cc4c-9157-4c19-a468-4e1d57bc13ae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739402680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2739402680
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4115465399
Short name T449
Test name
Test status
Simulation time 7038620406 ps
CPU time 13.58 seconds
Started Jun 07 06:16:26 PM PDT 24
Finished Jun 07 06:16:40 PM PDT 24
Peak memory 219084 kb
Host smart-420b43c2-0ee2-4bab-8e0d-22e86f49d216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115465399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4115465399
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2634293302
Short name T456
Test name
Test status
Simulation time 149213799 ps
CPU time 10.17 seconds
Started Jun 07 06:16:20 PM PDT 24
Finished Jun 07 06:16:30 PM PDT 24
Peak memory 218924 kb
Host smart-24a2a9de-0890-47df-ad13-3f9b8e2b264c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634293302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2634293302
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.589424737
Short name T400
Test name
Test status
Simulation time 408269737 ps
CPU time 4.9 seconds
Started Jun 07 06:16:31 PM PDT 24
Finished Jun 07 06:16:36 PM PDT 24
Peak memory 219104 kb
Host smart-fe4a2294-8112-45e8-90e0-55fcf4624b4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589424737 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.589424737
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1699450015
Short name T415
Test name
Test status
Simulation time 85636434 ps
CPU time 4.1 seconds
Started Jun 07 06:16:16 PM PDT 24
Finished Jun 07 06:16:20 PM PDT 24
Peak memory 210812 kb
Host smart-f0b7ed4f-782a-4093-9d13-3d74c3b32f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699450015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1699450015
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1523412398
Short name T421
Test name
Test status
Simulation time 1443077409 ps
CPU time 19.47 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:27 PM PDT 24
Peak memory 211040 kb
Host smart-71832444-e2b6-4333-9e97-84fa0534bad7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523412398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1523412398
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.72121819
Short name T436
Test name
Test status
Simulation time 2341366856 ps
CPU time 9.88 seconds
Started Jun 07 06:16:18 PM PDT 24
Finished Jun 07 06:16:29 PM PDT 24
Peak memory 219016 kb
Host smart-e67035fd-1eb4-4e5c-9eb9-984fb4dd9120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72121819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ct
rl_same_csr_outstanding.72121819
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4177129271
Short name T386
Test name
Test status
Simulation time 854295814 ps
CPU time 11.34 seconds
Started Jun 07 06:16:32 PM PDT 24
Finished Jun 07 06:16:44 PM PDT 24
Peak memory 218908 kb
Host smart-0271b247-06fc-4797-9545-3fa4322022f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177129271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4177129271
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3703853680
Short name T62
Test name
Test status
Simulation time 1836331930 ps
CPU time 10.35 seconds
Started Jun 07 06:16:15 PM PDT 24
Finished Jun 07 06:16:26 PM PDT 24
Peak memory 218844 kb
Host smart-abc20bf3-0953-401a-b24c-9dec71c4987b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703853680 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3703853680
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2009605543
Short name T76
Test name
Test status
Simulation time 88908956 ps
CPU time 4.13 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:14 PM PDT 24
Peak memory 217448 kb
Host smart-d8e5f00c-a5b2-4626-878e-a2a50bb30380
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009605543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2009605543
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1972304884
Short name T81
Test name
Test status
Simulation time 32536206187 ps
CPU time 67.88 seconds
Started Jun 07 06:16:41 PM PDT 24
Finished Jun 07 06:17:49 PM PDT 24
Peak memory 210972 kb
Host smart-cedf38ee-d18a-4da1-aaf5-bda4b8434bbf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972304884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1972304884
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3725597735
Short name T94
Test name
Test status
Simulation time 16647428822 ps
CPU time 16.45 seconds
Started Jun 07 06:16:21 PM PDT 24
Finished Jun 07 06:16:38 PM PDT 24
Peak memory 219148 kb
Host smart-41a614b9-00ea-4e3d-9a85-3667f9807389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725597735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3725597735
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2639401193
Short name T423
Test name
Test status
Simulation time 2223543371 ps
CPU time 13.5 seconds
Started Jun 07 06:16:18 PM PDT 24
Finished Jun 07 06:16:37 PM PDT 24
Peak memory 218980 kb
Host smart-3f9d9bcf-3d07-4ac5-9af0-6dcffb2ba030
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639401193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2639401193
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3170883815
Short name T118
Test name
Test status
Simulation time 3792684699 ps
CPU time 76.71 seconds
Started Jun 07 06:16:29 PM PDT 24
Finished Jun 07 06:17:46 PM PDT 24
Peak memory 212504 kb
Host smart-eef7738e-1946-4223-ab39-597f742c08d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170883815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3170883815
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.228827738
Short name T381
Test name
Test status
Simulation time 1346020967 ps
CPU time 9.97 seconds
Started Jun 07 06:16:27 PM PDT 24
Finished Jun 07 06:16:38 PM PDT 24
Peak memory 219128 kb
Host smart-656a28c8-2360-4caf-bae3-fb4a27bc2a6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228827738 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.228827738
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2008493111
Short name T416
Test name
Test status
Simulation time 2593649393 ps
CPU time 11.52 seconds
Started Jun 07 06:16:19 PM PDT 24
Finished Jun 07 06:16:31 PM PDT 24
Peak memory 210924 kb
Host smart-3a40f4ef-880a-4ff1-bb8d-58835576c73f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008493111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2008493111
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3748430796
Short name T68
Test name
Test status
Simulation time 41945820682 ps
CPU time 62.51 seconds
Started Jun 07 06:16:19 PM PDT 24
Finished Jun 07 06:17:22 PM PDT 24
Peak memory 210992 kb
Host smart-377b1389-4569-4fe1-aa88-5959590b7c6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748430796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3748430796
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3269669416
Short name T93
Test name
Test status
Simulation time 332965606 ps
CPU time 4.6 seconds
Started Jun 07 06:16:21 PM PDT 24
Finished Jun 07 06:16:26 PM PDT 24
Peak memory 218452 kb
Host smart-fc46ff5a-827e-48e4-a0b4-3d828dc2eda0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269669416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3269669416
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1630882221
Short name T384
Test name
Test status
Simulation time 643837949 ps
CPU time 11.47 seconds
Started Jun 07 06:16:45 PM PDT 24
Finished Jun 07 06:16:57 PM PDT 24
Peak memory 218964 kb
Host smart-983094bd-00aa-4dc7-b4a5-9044c719cc20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630882221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1630882221
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3050915481
Short name T119
Test name
Test status
Simulation time 1574582889 ps
CPU time 44.47 seconds
Started Jun 07 06:16:32 PM PDT 24
Finished Jun 07 06:17:17 PM PDT 24
Peak memory 211852 kb
Host smart-e55c2913-99e2-46a9-bbb1-cc2f4c685eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050915481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3050915481
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1776297320
Short name T428
Test name
Test status
Simulation time 565355594 ps
CPU time 5.33 seconds
Started Jun 07 06:16:23 PM PDT 24
Finished Jun 07 06:16:29 PM PDT 24
Peak memory 219132 kb
Host smart-f3e50140-ebff-4bdc-b045-ff449e218ff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776297320 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1776297320
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3162312021
Short name T396
Test name
Test status
Simulation time 1196521519 ps
CPU time 6.99 seconds
Started Jun 07 06:16:24 PM PDT 24
Finished Jun 07 06:16:32 PM PDT 24
Peak memory 210804 kb
Host smart-8af053c6-1fe8-4c2d-a619-70f46b9358a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162312021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3162312021
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1600232238
Short name T109
Test name
Test status
Simulation time 8216131310 ps
CPU time 74.61 seconds
Started Jun 07 06:16:24 PM PDT 24
Finished Jun 07 06:17:39 PM PDT 24
Peak memory 210992 kb
Host smart-814c9404-f7d2-4962-aede-831b873043d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600232238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1600232238
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3902182724
Short name T427
Test name
Test status
Simulation time 379357401 ps
CPU time 4.79 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 218496 kb
Host smart-3bc0a3e1-1a72-47b0-b5b4-6985eb443722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902182724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3902182724
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.21274180
Short name T389
Test name
Test status
Simulation time 1533249375 ps
CPU time 18.25 seconds
Started Jun 07 06:16:33 PM PDT 24
Finished Jun 07 06:16:52 PM PDT 24
Peak memory 218924 kb
Host smart-c0a42d74-5b8d-4f58-b101-7e841eb7a31b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21274180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.21274180
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2331355511
Short name T112
Test name
Test status
Simulation time 3573573810 ps
CPU time 73.76 seconds
Started Jun 07 06:16:18 PM PDT 24
Finished Jun 07 06:17:33 PM PDT 24
Peak memory 219084 kb
Host smart-d85aef07-c975-4ad4-83b5-48435c292164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331355511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2331355511
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2040767426
Short name T422
Test name
Test status
Simulation time 6568496889 ps
CPU time 14.31 seconds
Started Jun 07 06:16:26 PM PDT 24
Finished Jun 07 06:16:41 PM PDT 24
Peak memory 219084 kb
Host smart-eff8e166-5bff-4abf-aba4-46ca8bce1da7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040767426 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2040767426
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.700596845
Short name T78
Test name
Test status
Simulation time 5283545072 ps
CPU time 12.15 seconds
Started Jun 07 06:16:35 PM PDT 24
Finished Jun 07 06:16:48 PM PDT 24
Peak memory 219100 kb
Host smart-36eb9fe5-8f3d-486c-baf5-21e1066a693e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700596845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.700596845
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2380190200
Short name T100
Test name
Test status
Simulation time 13834315815 ps
CPU time 99.02 seconds
Started Jun 07 06:16:31 PM PDT 24
Finished Jun 07 06:18:10 PM PDT 24
Peak memory 211044 kb
Host smart-93ec983e-a9d0-4eac-91d7-ecfdb109063d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380190200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2380190200
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1095519292
Short name T97
Test name
Test status
Simulation time 10269415879 ps
CPU time 15.56 seconds
Started Jun 07 06:16:35 PM PDT 24
Finished Jun 07 06:16:52 PM PDT 24
Peak memory 219084 kb
Host smart-770ddbe2-05b6-4a71-884f-366df30dbbf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095519292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1095519292
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1028397304
Short name T408
Test name
Test status
Simulation time 2552541796 ps
CPU time 10.98 seconds
Started Jun 07 06:16:22 PM PDT 24
Finished Jun 07 06:16:34 PM PDT 24
Peak memory 219008 kb
Host smart-800b5166-67a4-4731-89db-50e4d44d6ab4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028397304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1028397304
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1206917234
Short name T110
Test name
Test status
Simulation time 187478554 ps
CPU time 37.27 seconds
Started Jun 07 06:16:24 PM PDT 24
Finished Jun 07 06:17:02 PM PDT 24
Peak memory 219072 kb
Host smart-2fa2b39b-de35-43ff-9b16-6356f90d8393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206917234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1206917234
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.323074577
Short name T377
Test name
Test status
Simulation time 387022807 ps
CPU time 6.19 seconds
Started Jun 07 06:16:37 PM PDT 24
Finished Jun 07 06:16:43 PM PDT 24
Peak memory 219136 kb
Host smart-a3cefd23-0e6f-4c88-a160-678510d86d7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323074577 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.323074577
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3816387662
Short name T391
Test name
Test status
Simulation time 2889404332 ps
CPU time 12.24 seconds
Started Jun 07 06:16:25 PM PDT 24
Finished Jun 07 06:16:37 PM PDT 24
Peak memory 217568 kb
Host smart-5dcfd445-6c2b-4371-b94b-e41d0b1eabea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816387662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3816387662
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.855620817
Short name T398
Test name
Test status
Simulation time 8178935888 ps
CPU time 76.31 seconds
Started Jun 07 06:16:22 PM PDT 24
Finished Jun 07 06:17:39 PM PDT 24
Peak memory 211040 kb
Host smart-908d9488-2c49-4c28-9c7e-37804e290083
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855620817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.855620817
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1858159083
Short name T70
Test name
Test status
Simulation time 2772401618 ps
CPU time 12.47 seconds
Started Jun 07 06:16:23 PM PDT 24
Finished Jun 07 06:16:36 PM PDT 24
Peak memory 219116 kb
Host smart-1894eac0-582b-4ed2-81c1-875ce52e5b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858159083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1858159083
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1322893052
Short name T382
Test name
Test status
Simulation time 7852547076 ps
CPU time 20.2 seconds
Started Jun 07 06:16:32 PM PDT 24
Finished Jun 07 06:16:53 PM PDT 24
Peak memory 219004 kb
Host smart-dba488de-6392-4d8d-9da6-076182fc9687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322893052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1322893052
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3513542111
Short name T124
Test name
Test status
Simulation time 1876281766 ps
CPU time 40.86 seconds
Started Jun 07 06:16:31 PM PDT 24
Finished Jun 07 06:17:13 PM PDT 24
Peak memory 219168 kb
Host smart-d6059b45-b29b-4921-8c6f-8afafe22800b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513542111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3513542111
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1349421037
Short name T418
Test name
Test status
Simulation time 2922782539 ps
CPU time 11.99 seconds
Started Jun 07 06:16:36 PM PDT 24
Finished Jun 07 06:16:48 PM PDT 24
Peak memory 219176 kb
Host smart-6ed85be4-42a0-4043-88f2-953944d59bfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349421037 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1349421037
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1204645940
Short name T455
Test name
Test status
Simulation time 5757766176 ps
CPU time 12.65 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:16:57 PM PDT 24
Peak memory 219080 kb
Host smart-68d1bb74-2320-4cc1-ae81-00716678fce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204645940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1204645940
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.992296230
Short name T107
Test name
Test status
Simulation time 15775142175 ps
CPU time 63.92 seconds
Started Jun 07 06:16:43 PM PDT 24
Finished Jun 07 06:17:48 PM PDT 24
Peak memory 210940 kb
Host smart-c6c29314-c6fb-44dd-a369-4ea93be17c62
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992296230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.992296230
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4110624662
Short name T442
Test name
Test status
Simulation time 13050439783 ps
CPU time 14.5 seconds
Started Jun 07 06:16:34 PM PDT 24
Finished Jun 07 06:16:49 PM PDT 24
Peak memory 211252 kb
Host smart-9e35775c-94ab-48bb-9b7b-82ae3ddd4d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110624662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.4110624662
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1307956998
Short name T412
Test name
Test status
Simulation time 1338043146 ps
CPU time 16.81 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:17:01 PM PDT 24
Peak memory 219172 kb
Host smart-5353e4b7-e0df-4cf3-8a2f-3a922be61ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307956998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1307956998
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3475147301
Short name T111
Test name
Test status
Simulation time 2010363495 ps
CPU time 45.76 seconds
Started Jun 07 06:16:29 PM PDT 24
Finished Jun 07 06:17:15 PM PDT 24
Peak memory 212204 kb
Host smart-9d29a0ae-86be-46b1-bc4e-4ccd9c139a03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475147301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3475147301
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3329616467
Short name T435
Test name
Test status
Simulation time 451421520 ps
CPU time 5.99 seconds
Started Jun 07 06:16:26 PM PDT 24
Finished Jun 07 06:16:32 PM PDT 24
Peak memory 219044 kb
Host smart-556baa31-ece2-45c6-ba4c-c27dd1c48793
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329616467 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3329616467
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3786915817
Short name T388
Test name
Test status
Simulation time 1146253539 ps
CPU time 8.86 seconds
Started Jun 07 06:16:23 PM PDT 24
Finished Jun 07 06:16:33 PM PDT 24
Peak memory 217952 kb
Host smart-30040d33-0fdb-49fb-9667-2bb261971a1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786915817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3786915817
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2026251150
Short name T80
Test name
Test status
Simulation time 4182297343 ps
CPU time 42.25 seconds
Started Jun 07 06:16:46 PM PDT 24
Finished Jun 07 06:17:29 PM PDT 24
Peak memory 211268 kb
Host smart-b17d8ef3-0b8a-4bec-b457-d6fd1a658fef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026251150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2026251150
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3811484733
Short name T425
Test name
Test status
Simulation time 981404769 ps
CPU time 11.86 seconds
Started Jun 07 06:16:26 PM PDT 24
Finished Jun 07 06:16:38 PM PDT 24
Peak memory 210960 kb
Host smart-19fc00d3-9183-45d9-b0f0-267e0ce834cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811484733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3811484733
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1534903400
Short name T450
Test name
Test status
Simulation time 2102792309 ps
CPU time 20.27 seconds
Started Jun 07 06:16:22 PM PDT 24
Finished Jun 07 06:16:43 PM PDT 24
Peak memory 219060 kb
Host smart-04558d92-22a6-4ce3-8ff9-481b1e1b08ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534903400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1534903400
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3742424032
Short name T120
Test name
Test status
Simulation time 2484713137 ps
CPU time 70.21 seconds
Started Jun 07 06:16:33 PM PDT 24
Finished Jun 07 06:17:43 PM PDT 24
Peak memory 212484 kb
Host smart-bee950bb-938b-4687-939b-fc13cd1476c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742424032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3742424032
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3835676222
Short name T434
Test name
Test status
Simulation time 3122890123 ps
CPU time 11.85 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 218652 kb
Host smart-4e40eaf6-5a29-4c50-b173-5488d056d67f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835676222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3835676222
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2749853593
Short name T385
Test name
Test status
Simulation time 2810315051 ps
CPU time 8.96 seconds
Started Jun 07 06:16:15 PM PDT 24
Finished Jun 07 06:16:25 PM PDT 24
Peak memory 217808 kb
Host smart-a2867e71-0fef-435e-9b27-101570b46aec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749853593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2749853593
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3553189181
Short name T468
Test name
Test status
Simulation time 1882891516 ps
CPU time 17.62 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:30 PM PDT 24
Peak memory 218784 kb
Host smart-8f2ea723-f7f6-4b66-b784-f770c48663b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553189181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3553189181
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.443771889
Short name T399
Test name
Test status
Simulation time 1157387825 ps
CPU time 11.26 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 215000 kb
Host smart-438c565c-adeb-487a-bd4c-5c135bc4297c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443771889 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.443771889
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3020371322
Short name T441
Test name
Test status
Simulation time 1155678716 ps
CPU time 11.11 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:20 PM PDT 24
Peak memory 210944 kb
Host smart-93f395d6-ab84-4f20-9dc0-5cb902c1385a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020371322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3020371322
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3300048857
Short name T447
Test name
Test status
Simulation time 1169667434 ps
CPU time 10.35 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:21 PM PDT 24
Peak memory 210664 kb
Host smart-33e80b55-b6d3-4196-944c-1230c680fe69
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300048857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3300048857
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.973359
Short name T426
Test name
Test status
Simulation time 3452297564 ps
CPU time 9.36 seconds
Started Jun 07 06:16:17 PM PDT 24
Finished Jun 07 06:16:27 PM PDT 24
Peak memory 210732 kb
Host smart-8d7bc5ff-d7bd-453d-b8a0-c5cd52f17112
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.973359
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.128229411
Short name T106
Test name
Test status
Simulation time 3610905998 ps
CPU time 39.69 seconds
Started Jun 07 06:16:17 PM PDT 24
Finished Jun 07 06:16:57 PM PDT 24
Peak memory 210976 kb
Host smart-ca602417-77b7-4151-a5a1-e70a90d9ac81
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128229411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.128229411
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3840941367
Short name T92
Test name
Test status
Simulation time 182752588 ps
CPU time 5.92 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 210888 kb
Host smart-be825e5f-fc81-41a2-b45e-9ea54fe5573c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840941367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3840941367
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3207239017
Short name T458
Test name
Test status
Simulation time 1726656994 ps
CPU time 19.03 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:28 PM PDT 24
Peak memory 218984 kb
Host smart-066d942d-78c5-43a2-982d-89682d79964a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207239017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3207239017
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4029399553
Short name T117
Test name
Test status
Simulation time 1380754933 ps
CPU time 73.14 seconds
Started Jun 07 06:16:17 PM PDT 24
Finished Jun 07 06:17:31 PM PDT 24
Peak memory 212376 kb
Host smart-218c5da2-7c17-466f-a7c2-0bf344f4b15e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029399553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4029399553
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.603338638
Short name T71
Test name
Test status
Simulation time 167961776 ps
CPU time 4.28 seconds
Started Jun 07 06:16:35 PM PDT 24
Finished Jun 07 06:16:39 PM PDT 24
Peak memory 210916 kb
Host smart-6f7138da-420c-41ad-b5a1-84f199229800
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603338638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.603338638
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4028800068
Short name T380
Test name
Test status
Simulation time 85596701 ps
CPU time 4.33 seconds
Started Jun 07 06:16:21 PM PDT 24
Finished Jun 07 06:16:25 PM PDT 24
Peak memory 210896 kb
Host smart-3c85604a-b6bd-4ada-9121-9c6b7d92209b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028800068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4028800068
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2420926367
Short name T402
Test name
Test status
Simulation time 8784076934 ps
CPU time 18.25 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 211056 kb
Host smart-d59b1e4a-9bc1-4eb0-9dcf-bcf8e8e2efe0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420926367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2420926367
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3148433148
Short name T407
Test name
Test status
Simulation time 7805607371 ps
CPU time 14.78 seconds
Started Jun 07 06:16:39 PM PDT 24
Finished Jun 07 06:16:55 PM PDT 24
Peak memory 219168 kb
Host smart-d00e6c75-633f-4631-a798-30094c60f716
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148433148 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3148433148
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1374921984
Short name T424
Test name
Test status
Simulation time 18225103924 ps
CPU time 16.51 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:26 PM PDT 24
Peak memory 210748 kb
Host smart-575b941c-f2c4-4e23-b2e0-cd4edc7bdb42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374921984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1374921984
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1390442953
Short name T409
Test name
Test status
Simulation time 85668482 ps
CPU time 4.15 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 210648 kb
Host smart-906aaa87-cc5e-471e-b62b-f9dfbd08aaae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390442953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1390442953
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2256513507
Short name T461
Test name
Test status
Simulation time 85419942 ps
CPU time 4.08 seconds
Started Jun 07 06:16:17 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 210648 kb
Host smart-9b622f32-04a8-497a-b4e4-017adf7f5a16
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256513507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2256513507
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3927107030
Short name T95
Test name
Test status
Simulation time 864914499 ps
CPU time 5.72 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:14 PM PDT 24
Peak memory 218412 kb
Host smart-966a381b-cd36-4526-bf13-2ed1a540510d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927107030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3927107030
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3107009487
Short name T405
Test name
Test status
Simulation time 872286996 ps
CPU time 13.21 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 218980 kb
Host smart-1f976b15-46ef-4757-a707-ae6f80384089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107009487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3107009487
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2858366974
Short name T123
Test name
Test status
Simulation time 1733335495 ps
CPU time 44.81 seconds
Started Jun 07 06:16:13 PM PDT 24
Finished Jun 07 06:16:59 PM PDT 24
Peak memory 219092 kb
Host smart-01ed69e9-7978-4e54-830f-5936fbd773cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858366974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2858366974
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1150974004
Short name T466
Test name
Test status
Simulation time 4242010178 ps
CPU time 10.48 seconds
Started Jun 07 06:16:13 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 210916 kb
Host smart-73b6b020-515a-477e-86e0-0b74d8ff945d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150974004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1150974004
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1036898708
Short name T383
Test name
Test status
Simulation time 8366920934 ps
CPU time 16.49 seconds
Started Jun 07 06:16:17 PM PDT 24
Finished Jun 07 06:16:34 PM PDT 24
Peak memory 210988 kb
Host smart-64f327ec-24fd-4c82-9099-280e83c22d08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036898708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1036898708
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2523449246
Short name T394
Test name
Test status
Simulation time 4546024705 ps
CPU time 11.38 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 210992 kb
Host smart-238917e5-e97f-4ec1-b6a8-674811477e5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523449246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2523449246
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4133357096
Short name T410
Test name
Test status
Simulation time 91094443 ps
CPU time 4.3 seconds
Started Jun 07 06:16:19 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 212172 kb
Host smart-a19609af-ab2f-4239-bc0d-a10bfd1b5323
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133357096 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4133357096
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3484363437
Short name T433
Test name
Test status
Simulation time 2622653969 ps
CPU time 8.1 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:20 PM PDT 24
Peak memory 210960 kb
Host smart-e7c8f2e3-f70a-40af-bb46-1f3ff9f26f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484363437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3484363437
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2016214251
Short name T439
Test name
Test status
Simulation time 172022974 ps
CPU time 4.09 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:14 PM PDT 24
Peak memory 210616 kb
Host smart-7c6ec122-e953-4d95-bf85-a3eda5119631
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016214251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2016214251
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4218159379
Short name T397
Test name
Test status
Simulation time 1163631646 ps
CPU time 7.67 seconds
Started Jun 07 06:16:15 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 210312 kb
Host smart-ea1ebb83-cf32-4a3d-a0f2-d4055a88827c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218159379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4218159379
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3086280606
Short name T77
Test name
Test status
Simulation time 21794076721 ps
CPU time 61.42 seconds
Started Jun 07 06:16:13 PM PDT 24
Finished Jun 07 06:17:15 PM PDT 24
Peak memory 211208 kb
Host smart-930ecbb1-c66b-4731-9b33-ca8d91ddd0cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086280606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3086280606
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2816674705
Short name T454
Test name
Test status
Simulation time 2296497543 ps
CPU time 8.19 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 219204 kb
Host smart-ed985ac7-2bf9-4351-9735-6d6f2e53b728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816674705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2816674705
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.415845368
Short name T440
Test name
Test status
Simulation time 2135968482 ps
CPU time 19.42 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:17:04 PM PDT 24
Peak memory 219040 kb
Host smart-65afd9cd-5157-473e-b27b-073a30ceb15a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415845368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.415845368
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.135990607
Short name T467
Test name
Test status
Simulation time 6217455839 ps
CPU time 43.81 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:51 PM PDT 24
Peak memory 212316 kb
Host smart-60507f17-bebe-47ee-8717-baf89e903a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135990607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.135990607
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1525665739
Short name T393
Test name
Test status
Simulation time 1166250387 ps
CPU time 10.8 seconds
Started Jun 07 06:16:17 PM PDT 24
Finished Jun 07 06:16:28 PM PDT 24
Peak memory 219092 kb
Host smart-91c2d6d5-37d1-4437-b611-27a64abb63e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525665739 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1525665739
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3140627114
Short name T63
Test name
Test status
Simulation time 3404417207 ps
CPU time 14.23 seconds
Started Jun 07 06:16:23 PM PDT 24
Finished Jun 07 06:16:38 PM PDT 24
Peak memory 210916 kb
Host smart-6515ce74-fd2e-4335-ad9b-1d8a84a57e63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140627114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3140627114
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.941236361
Short name T414
Test name
Test status
Simulation time 19884384644 ps
CPU time 96.33 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:17:42 PM PDT 24
Peak memory 210984 kb
Host smart-17138d5c-3755-4532-ae75-11ec85d820f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941236361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.941236361
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1478712960
Short name T99
Test name
Test status
Simulation time 1250121252 ps
CPU time 11.53 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 210864 kb
Host smart-f3427ea0-fded-401f-be0f-f017d2bb2f60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478712960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1478712960
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4040474737
Short name T431
Test name
Test status
Simulation time 3839733781 ps
CPU time 9.96 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 219000 kb
Host smart-2087360e-3f4d-48bd-a134-482dfa25c3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040474737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4040474737
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1358154158
Short name T122
Test name
Test status
Simulation time 3176050864 ps
CPU time 46.45 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:16:52 PM PDT 24
Peak memory 212408 kb
Host smart-f91c9b20-941a-470f-ba6c-a7311de6fcd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358154158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1358154158
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2598474504
Short name T411
Test name
Test status
Simulation time 6116099971 ps
CPU time 14.74 seconds
Started Jun 07 06:16:35 PM PDT 24
Finished Jun 07 06:16:51 PM PDT 24
Peak memory 219164 kb
Host smart-cf562b98-d525-4a23-89f2-83562df244a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598474504 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2598474504
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2162456842
Short name T74
Test name
Test status
Simulation time 2040777320 ps
CPU time 16.51 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:29 PM PDT 24
Peak memory 219264 kb
Host smart-1621cef5-b617-4058-87c2-6659eebb756f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162456842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2162456842
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1558097455
Short name T83
Test name
Test status
Simulation time 12208131799 ps
CPU time 28.1 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:40 PM PDT 24
Peak memory 210980 kb
Host smart-f210c6e7-bc8f-4c4d-81c5-e6f824238206
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558097455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1558097455
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1288666289
Short name T446
Test name
Test status
Simulation time 1384995931 ps
CPU time 12.87 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 219004 kb
Host smart-5eafe840-319a-4131-a6fe-1e7aa5d9a4a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288666289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1288666289
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1686312966
Short name T445
Test name
Test status
Simulation time 1204821147 ps
CPU time 14.61 seconds
Started Jun 07 06:16:15 PM PDT 24
Finished Jun 07 06:16:30 PM PDT 24
Peak memory 219056 kb
Host smart-ee00a968-7c2e-4aaf-ab49-2d8f0785c7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686312966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1686312966
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3248019121
Short name T121
Test name
Test status
Simulation time 391344342 ps
CPU time 38.24 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:51 PM PDT 24
Peak memory 211968 kb
Host smart-aa011e20-82c0-4bd7-8058-ee5f6258f7ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248019121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3248019121
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3580735647
Short name T465
Test name
Test status
Simulation time 735131941 ps
CPU time 9.09 seconds
Started Jun 07 06:16:13 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 219128 kb
Host smart-4da5c9ec-4e0e-4f96-9cd9-f7026e3a9846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580735647 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3580735647
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2473079969
Short name T67
Test name
Test status
Simulation time 3426402282 ps
CPU time 7 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:20 PM PDT 24
Peak memory 218260 kb
Host smart-6bff0c23-bcf1-46b5-9c64-7673e0ef55f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473079969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2473079969
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1316299572
Short name T463
Test name
Test status
Simulation time 2223856049 ps
CPU time 27.27 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:39 PM PDT 24
Peak memory 210832 kb
Host smart-f373e620-c753-41e1-ade3-646ea85fede6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316299572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1316299572
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3519290288
Short name T96
Test name
Test status
Simulation time 85638132 ps
CPU time 4.17 seconds
Started Jun 07 06:16:13 PM PDT 24
Finished Jun 07 06:16:18 PM PDT 24
Peak memory 218440 kb
Host smart-f0a40041-c9e7-4f14-8c44-39a7408102e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519290288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3519290288
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.785022345
Short name T462
Test name
Test status
Simulation time 986727846 ps
CPU time 13.45 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:25 PM PDT 24
Peak memory 218900 kb
Host smart-bbe3ee0a-87d8-41f8-b7b5-39fa1362741c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785022345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.785022345
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1620087629
Short name T60
Test name
Test status
Simulation time 1673559302 ps
CPU time 68.08 seconds
Started Jun 07 06:16:45 PM PDT 24
Finished Jun 07 06:17:53 PM PDT 24
Peak memory 219044 kb
Host smart-3eeb7312-f128-46de-8c1f-26a0563f939d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620087629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1620087629
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3712888489
Short name T457
Test name
Test status
Simulation time 2093268860 ps
CPU time 11.25 seconds
Started Jun 07 06:16:29 PM PDT 24
Finished Jun 07 06:16:41 PM PDT 24
Peak memory 219244 kb
Host smart-e8bd4ce0-08f0-4395-b743-428894c032ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712888489 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3712888489
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1734509715
Short name T66
Test name
Test status
Simulation time 1189334622 ps
CPU time 7.75 seconds
Started Jun 07 06:16:15 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 218064 kb
Host smart-f7663cf3-6f08-4c5b-8927-08a60770805d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734509715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1734509715
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4206990459
Short name T432
Test name
Test status
Simulation time 4920933889 ps
CPU time 27.76 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:38 PM PDT 24
Peak memory 211904 kb
Host smart-8b59343c-e061-4dbd-bada-d560733ec6c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206990459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4206990459
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1784703701
Short name T444
Test name
Test status
Simulation time 278241974 ps
CPU time 4.15 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 210900 kb
Host smart-689c860b-fd06-4a05-bfe7-8f281b0345fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784703701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1784703701
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1844233836
Short name T376
Test name
Test status
Simulation time 1487235531 ps
CPU time 10.82 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 218976 kb
Host smart-805789b2-abe4-44b9-a50e-07ff2be3e8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844233836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1844233836
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.622270165
Short name T378
Test name
Test status
Simulation time 984659587 ps
CPU time 8.16 seconds
Started Jun 07 06:16:34 PM PDT 24
Finished Jun 07 06:16:43 PM PDT 24
Peak memory 219064 kb
Host smart-bad96964-3791-4aa9-bdee-931508f84839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622270165 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.622270165
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1393129259
Short name T460
Test name
Test status
Simulation time 161484168 ps
CPU time 4.3 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 218328 kb
Host smart-a329313b-17fc-4d79-869d-87e0e46c315b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393129259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1393129259
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1542842592
Short name T79
Test name
Test status
Simulation time 722970064 ps
CPU time 18.77 seconds
Started Jun 07 06:16:16 PM PDT 24
Finished Jun 07 06:16:35 PM PDT 24
Peak memory 210888 kb
Host smart-0c5d5de9-e99f-429b-a2ff-986f190bb4b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542842592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1542842592
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.551751842
Short name T98
Test name
Test status
Simulation time 2946873529 ps
CPU time 16 seconds
Started Jun 07 06:16:19 PM PDT 24
Finished Jun 07 06:16:36 PM PDT 24
Peak memory 210952 kb
Host smart-ed477821-e94d-4833-964c-f45bfa7bb468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551751842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.551751842
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1886468014
Short name T406
Test name
Test status
Simulation time 8344642584 ps
CPU time 18.98 seconds
Started Jun 07 06:16:16 PM PDT 24
Finished Jun 07 06:16:35 PM PDT 24
Peak memory 219040 kb
Host smart-516ea5b8-23bb-43c2-b806-0076062221f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886468014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1886468014
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3768587616
Short name T115
Test name
Test status
Simulation time 1034633849 ps
CPU time 41.44 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:51 PM PDT 24
Peak memory 219052 kb
Host smart-b12055f7-97e1-411a-99d9-76f9cb2bcc84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768587616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3768587616
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.954357230
Short name T368
Test name
Test status
Simulation time 214683858 ps
CPU time 4.36 seconds
Started Jun 07 06:15:37 PM PDT 24
Finished Jun 07 06:15:42 PM PDT 24
Peak memory 210628 kb
Host smart-e7a18098-714b-4bce-9460-f9ff2196feac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954357230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.954357230
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3544533981
Short name T308
Test name
Test status
Simulation time 7847442232 ps
CPU time 15.69 seconds
Started Jun 07 06:15:40 PM PDT 24
Finished Jun 07 06:15:56 PM PDT 24
Peak memory 210960 kb
Host smart-bae388cc-c1c9-4dfe-aaea-4c89aac87041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3544533981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3544533981
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.724322546
Short name T299
Test name
Test status
Simulation time 10057167357 ps
CPU time 22.19 seconds
Started Jun 07 06:15:30 PM PDT 24
Finished Jun 07 06:15:54 PM PDT 24
Peak memory 213116 kb
Host smart-ea7bcd36-d36e-43d4-8046-84024bab7ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724322546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.724322546
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1038859029
Short name T191
Test name
Test status
Simulation time 6688844369 ps
CPU time 66.62 seconds
Started Jun 07 06:15:17 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 216360 kb
Host smart-2b7bccd7-e0fa-479a-8078-db59ebd22e68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038859029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1038859029
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.461849343
Short name T13
Test name
Test status
Simulation time 21830135702 ps
CPU time 2923.36 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 07:04:33 PM PDT 24
Peak memory 233536 kb
Host smart-24f48c88-1390-4a2e-97ca-9b273595d1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461849343 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.461849343
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3971004082
Short name T183
Test name
Test status
Simulation time 1185153777 ps
CPU time 11.68 seconds
Started Jun 07 06:15:33 PM PDT 24
Finished Jun 07 06:15:45 PM PDT 24
Peak memory 210724 kb
Host smart-2eba8ec2-d816-44ea-b9d8-46325b7872d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971004082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3971004082
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2828129292
Short name T313
Test name
Test status
Simulation time 21656844207 ps
CPU time 222.31 seconds
Started Jun 07 06:15:16 PM PDT 24
Finished Jun 07 06:19:14 PM PDT 24
Peak memory 237516 kb
Host smart-77b59baf-be52-4a2d-9b62-352a47b847b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828129292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2828129292
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2181929483
Short name T343
Test name
Test status
Simulation time 2635320320 ps
CPU time 25.88 seconds
Started Jun 07 06:15:19 PM PDT 24
Finished Jun 07 06:15:45 PM PDT 24
Peak memory 211492 kb
Host smart-152ce12a-1c65-45af-949c-81bfae18b759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181929483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2181929483
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2580261831
Short name T23
Test name
Test status
Simulation time 370141511 ps
CPU time 55.54 seconds
Started Jun 07 06:15:34 PM PDT 24
Finished Jun 07 06:16:30 PM PDT 24
Peak memory 235964 kb
Host smart-ad89aab7-9b29-404f-bc57-643d31850180
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580261831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2580261831
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2301292275
Short name T188
Test name
Test status
Simulation time 1804626844 ps
CPU time 10.16 seconds
Started Jun 07 06:15:14 PM PDT 24
Finished Jun 07 06:15:24 PM PDT 24
Peak memory 212992 kb
Host smart-3ba38672-c089-4ec3-a173-babdbd539260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301292275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2301292275
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1742714372
Short name T223
Test name
Test status
Simulation time 10362999949 ps
CPU time 26.61 seconds
Started Jun 07 06:15:20 PM PDT 24
Finished Jun 07 06:15:47 PM PDT 24
Peak memory 216848 kb
Host smart-b5afa349-0d79-44fd-ad78-b9fa503c1f35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742714372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1742714372
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2279069404
Short name T297
Test name
Test status
Simulation time 454385993656 ps
CPU time 7058.68 seconds
Started Jun 07 06:15:39 PM PDT 24
Finished Jun 07 08:13:19 PM PDT 24
Peak memory 233348 kb
Host smart-9d9bda33-54bd-435e-bb7c-c00f02cc2aa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279069404 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2279069404
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3793214904
Short name T89
Test name
Test status
Simulation time 499160499 ps
CPU time 7.59 seconds
Started Jun 07 06:16:01 PM PDT 24
Finished Jun 07 06:16:09 PM PDT 24
Peak memory 210748 kb
Host smart-7158846f-9ec0-4e77-ab0a-65705b37d083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793214904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3793214904
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2841523007
Short name T197
Test name
Test status
Simulation time 20588946169 ps
CPU time 198.65 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:19:06 PM PDT 24
Peak memory 237372 kb
Host smart-78011aca-0425-49fa-a00e-452da274736c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841523007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2841523007
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3736584500
Short name T179
Test name
Test status
Simulation time 31499088083 ps
CPU time 24 seconds
Started Jun 07 06:15:43 PM PDT 24
Finished Jun 07 06:16:07 PM PDT 24
Peak memory 211972 kb
Host smart-6a82701d-a1e0-4712-a4c5-fd06eac97d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736584500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3736584500
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4196122819
Short name T321
Test name
Test status
Simulation time 1208286207 ps
CPU time 12.37 seconds
Started Jun 07 06:15:58 PM PDT 24
Finished Jun 07 06:16:11 PM PDT 24
Peak memory 210036 kb
Host smart-83f7b7f8-0f67-4ba3-80b6-bd7987987811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4196122819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4196122819
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2375800543
Short name T133
Test name
Test status
Simulation time 4401091864 ps
CPU time 15.56 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:03 PM PDT 24
Peak memory 213892 kb
Host smart-08338598-98c8-41db-80a4-8495d8fe1959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375800543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2375800543
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1500662409
Short name T164
Test name
Test status
Simulation time 1920878192 ps
CPU time 21.17 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:09 PM PDT 24
Peak memory 210728 kb
Host smart-50dd36a7-25a5-4993-8f5e-321d9c1f8beb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500662409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1500662409
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.609836773
Short name T49
Test name
Test status
Simulation time 17926573960 ps
CPU time 671.97 seconds
Started Jun 07 06:15:46 PM PDT 24
Finished Jun 07 06:26:58 PM PDT 24
Peak memory 227296 kb
Host smart-871e671c-1800-4fa5-8d55-57c81fa2ab17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609836773 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.609836773
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3594863350
Short name T277
Test name
Test status
Simulation time 923838482 ps
CPU time 7.16 seconds
Started Jun 07 06:15:37 PM PDT 24
Finished Jun 07 06:15:45 PM PDT 24
Peak memory 210724 kb
Host smart-8dc3b6b0-b230-481b-8177-142aa388b320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594863350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3594863350
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3616053773
Short name T195
Test name
Test status
Simulation time 64284688373 ps
CPU time 329.29 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:21:37 PM PDT 24
Peak memory 225312 kb
Host smart-f4134e80-3103-429a-8fce-f67ebecc2460
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616053773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3616053773
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4243265473
Short name T224
Test name
Test status
Simulation time 686511926 ps
CPU time 13.63 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:01 PM PDT 24
Peak memory 211204 kb
Host smart-fc70487a-8b2a-48e1-9987-0de70c29f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243265473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4243265473
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.809480853
Short name T146
Test name
Test status
Simulation time 1938120761 ps
CPU time 16.17 seconds
Started Jun 07 06:15:45 PM PDT 24
Finished Jun 07 06:16:01 PM PDT 24
Peak memory 210912 kb
Host smart-4d6ce9ac-1529-409b-ab18-4f4a86f94ba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809480853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.809480853
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1017547813
Short name T149
Test name
Test status
Simulation time 2627374363 ps
CPU time 31.57 seconds
Started Jun 07 06:15:48 PM PDT 24
Finished Jun 07 06:16:20 PM PDT 24
Peak memory 213268 kb
Host smart-9361fffa-6651-4cfe-a4af-7c6fff2e8d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017547813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1017547813
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1017276588
Short name T207
Test name
Test status
Simulation time 1392226589 ps
CPU time 35.07 seconds
Started Jun 07 06:15:40 PM PDT 24
Finished Jun 07 06:16:15 PM PDT 24
Peak memory 214540 kb
Host smart-832171ff-1923-4971-a66c-991f5f74bbe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017276588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1017276588
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3139952782
Short name T364
Test name
Test status
Simulation time 4679765241 ps
CPU time 10.54 seconds
Started Jun 07 06:15:41 PM PDT 24
Finished Jun 07 06:15:52 PM PDT 24
Peak memory 210836 kb
Host smart-616ec12a-9dc6-4263-8116-eaa06a1051d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139952782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3139952782
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1881255668
Short name T320
Test name
Test status
Simulation time 15679752993 ps
CPU time 128.37 seconds
Started Jun 07 06:15:33 PM PDT 24
Finished Jun 07 06:17:42 PM PDT 24
Peak memory 238652 kb
Host smart-0fd38dde-2f62-4903-a80c-65d99a0830ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881255668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1881255668
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.998535040
Short name T90
Test name
Test status
Simulation time 23491500351 ps
CPU time 32.04 seconds
Started Jun 07 06:15:37 PM PDT 24
Finished Jun 07 06:16:09 PM PDT 24
Peak memory 211968 kb
Host smart-7b6499d1-78d3-49c1-a5d1-d56c09b09e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998535040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.998535040
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1088978791
Short name T311
Test name
Test status
Simulation time 508586188 ps
CPU time 5.58 seconds
Started Jun 07 06:15:42 PM PDT 24
Finished Jun 07 06:15:48 PM PDT 24
Peak memory 210880 kb
Host smart-57dbfe4a-11bd-4a5a-a0d8-9f920f032e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088978791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1088978791
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4091660618
Short name T160
Test name
Test status
Simulation time 989652454 ps
CPU time 10.08 seconds
Started Jun 07 06:15:45 PM PDT 24
Finished Jun 07 06:15:55 PM PDT 24
Peak memory 212948 kb
Host smart-a440b90c-b113-4571-befd-a20357895bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091660618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4091660618
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1377990266
Short name T216
Test name
Test status
Simulation time 251629759 ps
CPU time 7.54 seconds
Started Jun 07 06:15:50 PM PDT 24
Finished Jun 07 06:15:58 PM PDT 24
Peak memory 210052 kb
Host smart-86d90b4c-6bf4-4194-8a14-58858b3830d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377990266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1377990266
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3552771066
Short name T256
Test name
Test status
Simulation time 3024236237 ps
CPU time 13.55 seconds
Started Jun 07 06:15:43 PM PDT 24
Finished Jun 07 06:15:57 PM PDT 24
Peak memory 210948 kb
Host smart-ec7994f9-5f84-4f0e-9cc3-0d4bbd98fe48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552771066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3552771066
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4059434971
Short name T292
Test name
Test status
Simulation time 34902966019 ps
CPU time 170.91 seconds
Started Jun 07 06:15:52 PM PDT 24
Finished Jun 07 06:18:43 PM PDT 24
Peak memory 225252 kb
Host smart-2b489b12-e900-4bab-a64b-095871453f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059434971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4059434971
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.276456553
Short name T257
Test name
Test status
Simulation time 333873059 ps
CPU time 9.57 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:15:57 PM PDT 24
Peak memory 211428 kb
Host smart-03833719-117f-4969-8739-b4d0884b52c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276456553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.276456553
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1455420514
Short name T102
Test name
Test status
Simulation time 690670789 ps
CPU time 10 seconds
Started Jun 07 06:15:54 PM PDT 24
Finished Jun 07 06:16:04 PM PDT 24
Peak memory 210760 kb
Host smart-9052b0d6-d0da-4c8f-ad9a-d0eaea7ef389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455420514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1455420514
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2696702289
Short name T85
Test name
Test status
Simulation time 397497668 ps
CPU time 10.5 seconds
Started Jun 07 06:16:00 PM PDT 24
Finished Jun 07 06:16:12 PM PDT 24
Peak memory 213044 kb
Host smart-ac2d1d8f-74c3-41a8-ad7b-a28a558a4206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696702289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2696702289
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1573971863
Short name T206
Test name
Test status
Simulation time 979707260 ps
CPU time 10.27 seconds
Started Jun 07 06:15:36 PM PDT 24
Finished Jun 07 06:15:46 PM PDT 24
Peak memory 214408 kb
Host smart-4d5e38e6-543b-4f02-9ac6-90ee06727dfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573971863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1573971863
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.76286848
Short name T253
Test name
Test status
Simulation time 85681533 ps
CPU time 4.41 seconds
Started Jun 07 06:15:42 PM PDT 24
Finished Jun 07 06:15:47 PM PDT 24
Peak memory 210664 kb
Host smart-74a68c4e-232f-4a13-9b5e-cd84e96c150e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76286848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.76286848
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2089586998
Short name T369
Test name
Test status
Simulation time 16791738141 ps
CPU time 148.98 seconds
Started Jun 07 06:15:44 PM PDT 24
Finished Jun 07 06:18:14 PM PDT 24
Peak memory 225332 kb
Host smart-2b0dd23a-d477-41f7-9c23-ea429210edf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089586998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2089586998
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1482269055
Short name T233
Test name
Test status
Simulation time 3359633041 ps
CPU time 28.65 seconds
Started Jun 07 06:15:59 PM PDT 24
Finished Jun 07 06:16:28 PM PDT 24
Peak memory 211476 kb
Host smart-84c2b18d-712b-4af4-aaa4-0d0c9f52641c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482269055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1482269055
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2647981627
Short name T347
Test name
Test status
Simulation time 671077312 ps
CPU time 9.55 seconds
Started Jun 07 06:15:42 PM PDT 24
Finished Jun 07 06:15:52 PM PDT 24
Peak memory 210856 kb
Host smart-7335fc98-e88c-4719-b118-65c32f216454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647981627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2647981627
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2466264628
Short name T126
Test name
Test status
Simulation time 11777171070 ps
CPU time 22.28 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:16:12 PM PDT 24
Peak memory 213908 kb
Host smart-4e172ae5-478d-49a5-831f-b5cd1a8b37cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466264628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2466264628
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2222785714
Short name T284
Test name
Test status
Simulation time 8339574958 ps
CPU time 41.68 seconds
Started Jun 07 06:15:53 PM PDT 24
Finished Jun 07 06:16:35 PM PDT 24
Peak memory 216596 kb
Host smart-a650e164-d04e-4b0f-ac5d-cb0f72e4fda1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222785714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2222785714
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1738166820
Short name T289
Test name
Test status
Simulation time 741197298 ps
CPU time 9.12 seconds
Started Jun 07 06:16:02 PM PDT 24
Finished Jun 07 06:16:12 PM PDT 24
Peak memory 210720 kb
Host smart-9b9b5ce6-3871-44c5-be5a-e9a545fe1412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738166820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1738166820
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3040184481
Short name T203
Test name
Test status
Simulation time 2727905625 ps
CPU time 114.52 seconds
Started Jun 07 06:15:55 PM PDT 24
Finished Jun 07 06:17:50 PM PDT 24
Peak memory 228160 kb
Host smart-c65f843e-e7b2-474f-a18e-4a6d609737e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040184481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3040184481
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.810252026
Short name T43
Test name
Test status
Simulation time 41942266482 ps
CPU time 31.17 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:16:21 PM PDT 24
Peak memory 211944 kb
Host smart-8eda158d-48fc-4d13-a3ac-262a877cdc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810252026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.810252026
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2026806513
Short name T304
Test name
Test status
Simulation time 2541017463 ps
CPU time 13.2 seconds
Started Jun 07 06:15:52 PM PDT 24
Finished Jun 07 06:16:06 PM PDT 24
Peak memory 210948 kb
Host smart-d47eeff4-f9c8-4709-b28d-1f6a1a92a16f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026806513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2026806513
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3861804518
Short name T161
Test name
Test status
Simulation time 792411439 ps
CPU time 14.59 seconds
Started Jun 07 06:15:56 PM PDT 24
Finished Jun 07 06:16:11 PM PDT 24
Peak memory 212760 kb
Host smart-71ecfa06-270e-4478-884c-a0f11ef83c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861804518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3861804518
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3771951614
Short name T153
Test name
Test status
Simulation time 12516684254 ps
CPU time 40.76 seconds
Started Jun 07 06:15:37 PM PDT 24
Finished Jun 07 06:16:18 PM PDT 24
Peak memory 215872 kb
Host smart-a12659d9-b27e-4124-9930-5be34ad73456
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771951614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3771951614
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1853675712
Short name T247
Test name
Test status
Simulation time 338690419 ps
CPU time 5.47 seconds
Started Jun 07 06:15:46 PM PDT 24
Finished Jun 07 06:15:52 PM PDT 24
Peak memory 210688 kb
Host smart-75c89c77-3d72-4e07-ba18-769a34aedf9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853675712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1853675712
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3025044161
Short name T198
Test name
Test status
Simulation time 108803736250 ps
CPU time 201.06 seconds
Started Jun 07 06:15:33 PM PDT 24
Finished Jun 07 06:18:54 PM PDT 24
Peak memory 236392 kb
Host smart-ebeed874-2212-44a5-b7d2-bfa802d9f71e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025044161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3025044161
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3218112040
Short name T331
Test name
Test status
Simulation time 990967514 ps
CPU time 11.92 seconds
Started Jun 07 06:15:50 PM PDT 24
Finished Jun 07 06:16:02 PM PDT 24
Peak memory 210912 kb
Host smart-731cb1a8-887c-4008-bcd0-34ded0929beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218112040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3218112040
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2345335227
Short name T193
Test name
Test status
Simulation time 12026074063 ps
CPU time 33.56 seconds
Started Jun 07 06:15:58 PM PDT 24
Finished Jun 07 06:16:33 PM PDT 24
Peak memory 212964 kb
Host smart-dccc5016-6ab1-4579-aa04-25030de9a8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345335227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2345335227
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1874575419
Short name T352
Test name
Test status
Simulation time 2846509308 ps
CPU time 14.82 seconds
Started Jun 07 06:15:57 PM PDT 24
Finished Jun 07 06:16:12 PM PDT 24
Peak memory 210916 kb
Host smart-7d789078-1a27-43c3-ba28-902ccf052e35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874575419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1874575419
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3643595006
Short name T278
Test name
Test status
Simulation time 1251631688 ps
CPU time 12.52 seconds
Started Jun 07 06:15:50 PM PDT 24
Finished Jun 07 06:16:03 PM PDT 24
Peak memory 210720 kb
Host smart-5952ec4f-c07e-4d0b-9a83-42f17d0eeed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643595006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3643595006
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2206495099
Short name T254
Test name
Test status
Simulation time 89300916031 ps
CPU time 201.9 seconds
Started Jun 07 06:15:52 PM PDT 24
Finished Jun 07 06:19:14 PM PDT 24
Peak memory 236336 kb
Host smart-3f45728b-ad84-4073-b050-bd230a06c129
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206495099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2206495099
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3649294723
Short name T28
Test name
Test status
Simulation time 3768708823 ps
CPU time 31.49 seconds
Started Jun 07 06:15:41 PM PDT 24
Finished Jun 07 06:16:14 PM PDT 24
Peak memory 210820 kb
Host smart-a1f5a0a6-cac5-4584-9bf6-19ea9b50bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649294723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3649294723
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1370124280
Short name T105
Test name
Test status
Simulation time 1474300060 ps
CPU time 13.89 seconds
Started Jun 07 06:15:39 PM PDT 24
Finished Jun 07 06:15:53 PM PDT 24
Peak memory 210880 kb
Host smart-1c2cc6ac-6d04-40b0-a633-26b4a1bcc9d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370124280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1370124280
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3801982809
Short name T42
Test name
Test status
Simulation time 4961151810 ps
CPU time 27.07 seconds
Started Jun 07 06:15:45 PM PDT 24
Finished Jun 07 06:16:13 PM PDT 24
Peak memory 213928 kb
Host smart-da4cda39-07c0-45f4-8695-4e58d77d1c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801982809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3801982809
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4251240966
Short name T136
Test name
Test status
Simulation time 2863618825 ps
CPU time 21.42 seconds
Started Jun 07 06:15:42 PM PDT 24
Finished Jun 07 06:16:04 PM PDT 24
Peak memory 210800 kb
Host smart-4a530ffe-9020-47fc-9128-b4863b7ac05d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251240966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4251240966
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3009174030
Short name T309
Test name
Test status
Simulation time 2547399695 ps
CPU time 13.04 seconds
Started Jun 07 06:15:50 PM PDT 24
Finished Jun 07 06:16:03 PM PDT 24
Peak memory 210788 kb
Host smart-d397e5da-26b6-45c5-a2ee-f9eb9970e764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009174030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3009174030
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.388992623
Short name T215
Test name
Test status
Simulation time 26474772450 ps
CPU time 260.39 seconds
Started Jun 07 06:16:02 PM PDT 24
Finished Jun 07 06:20:23 PM PDT 24
Peak memory 237488 kb
Host smart-f2877fd1-2fc8-48ec-8a9f-83c966da772d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388992623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.388992623
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1491163833
Short name T148
Test name
Test status
Simulation time 1040262907 ps
CPU time 10.97 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:15 PM PDT 24
Peak memory 211560 kb
Host smart-a461efa3-3982-44e2-89da-b372c060be66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491163833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1491163833
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1426410192
Short name T221
Test name
Test status
Simulation time 2929247643 ps
CPU time 10.49 seconds
Started Jun 07 06:15:48 PM PDT 24
Finished Jun 07 06:15:59 PM PDT 24
Peak memory 210952 kb
Host smart-3e645387-4a0a-4a17-ad49-3138aac6987f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426410192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1426410192
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3499596367
Short name T152
Test name
Test status
Simulation time 4271583400 ps
CPU time 23.14 seconds
Started Jun 07 06:15:45 PM PDT 24
Finished Jun 07 06:16:09 PM PDT 24
Peak memory 212488 kb
Host smart-f2f64264-bfa9-4b64-832c-642bb0d709e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499596367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3499596367
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3607740124
Short name T296
Test name
Test status
Simulation time 78867498452 ps
CPU time 39.57 seconds
Started Jun 07 06:15:58 PM PDT 24
Finished Jun 07 06:16:38 PM PDT 24
Peak memory 219000 kb
Host smart-8d9eb5c2-5a9b-435b-9a7c-49e2b02accee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607740124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3607740124
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3892918607
Short name T52
Test name
Test status
Simulation time 52013333671 ps
CPU time 496.14 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:24:24 PM PDT 24
Peak memory 227256 kb
Host smart-6e7b0df9-ef43-43ef-927c-83ac4f9890c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892918607 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3892918607
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4174760466
Short name T266
Test name
Test status
Simulation time 856571025 ps
CPU time 5.84 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:15:53 PM PDT 24
Peak memory 210708 kb
Host smart-fc975583-5f24-426f-9114-bf3fda6b3c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174760466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4174760466
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4035221707
Short name T39
Test name
Test status
Simulation time 28966994011 ps
CPU time 288.26 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:20:54 PM PDT 24
Peak memory 236492 kb
Host smart-bd845691-edb6-4d1d-aafc-5881919e05fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035221707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4035221707
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.461219680
Short name T211
Test name
Test status
Simulation time 462562216 ps
CPU time 10.71 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 211712 kb
Host smart-39a6a5b9-4afd-4f66-870a-ee19f8e607cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461219680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.461219680
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4273536783
Short name T336
Test name
Test status
Simulation time 3388308912 ps
CPU time 14.81 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:21 PM PDT 24
Peak memory 210972 kb
Host smart-e196c406-6c5c-4863-b058-f0097a5f8f27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4273536783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4273536783
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3448081911
Short name T228
Test name
Test status
Simulation time 3142088653 ps
CPU time 26.52 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:33 PM PDT 24
Peak memory 212944 kb
Host smart-3004012a-f145-4be3-8691-461979d55722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448081911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3448081911
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.471841550
Short name T255
Test name
Test status
Simulation time 5774265924 ps
CPU time 65.03 seconds
Started Jun 07 06:15:53 PM PDT 24
Finished Jun 07 06:16:59 PM PDT 24
Peak memory 216104 kb
Host smart-a09d65d3-9877-412b-856d-5ee4e706b291
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471841550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.471841550
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3544485942
Short name T182
Test name
Test status
Simulation time 174715678 ps
CPU time 4.24 seconds
Started Jun 07 06:15:35 PM PDT 24
Finished Jun 07 06:15:40 PM PDT 24
Peak memory 210604 kb
Host smart-8241a2b6-07f5-4d9e-b1b3-5a398888d652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544485942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3544485942
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1323714197
Short name T263
Test name
Test status
Simulation time 13798511271 ps
CPU time 161.61 seconds
Started Jun 07 06:15:43 PM PDT 24
Finished Jun 07 06:18:25 PM PDT 24
Peak memory 237476 kb
Host smart-951a32a4-7887-4b13-8dc8-b23caf8e60de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323714197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1323714197
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2267318128
Short name T366
Test name
Test status
Simulation time 840260312 ps
CPU time 12.85 seconds
Started Jun 07 06:15:28 PM PDT 24
Finished Jun 07 06:15:41 PM PDT 24
Peak memory 211300 kb
Host smart-e77d2d32-8a3c-49d6-b214-20eaf98ad207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267318128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2267318128
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3845736130
Short name T276
Test name
Test status
Simulation time 1796882512 ps
CPU time 15.99 seconds
Started Jun 07 06:15:28 PM PDT 24
Finished Jun 07 06:15:44 PM PDT 24
Peak memory 210880 kb
Host smart-7c201cfb-f86a-4077-bf6b-6464b279fb68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845736130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3845736130
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.189893091
Short name T30
Test name
Test status
Simulation time 297647890 ps
CPU time 52.18 seconds
Started Jun 07 06:15:55 PM PDT 24
Finished Jun 07 06:16:48 PM PDT 24
Peak memory 235088 kb
Host smart-9f27f921-027a-4651-813e-8d1c61229234
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189893091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.189893091
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1558758819
Short name T184
Test name
Test status
Simulation time 745256294 ps
CPU time 9.97 seconds
Started Jun 07 06:15:56 PM PDT 24
Finished Jun 07 06:16:06 PM PDT 24
Peak memory 212976 kb
Host smart-bd5a7881-8e32-4a0f-97e6-d4e68b822871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558758819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1558758819
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1149441945
Short name T137
Test name
Test status
Simulation time 13271005413 ps
CPU time 34.14 seconds
Started Jun 07 06:15:27 PM PDT 24
Finished Jun 07 06:16:01 PM PDT 24
Peak memory 213968 kb
Host smart-464af2aa-e29b-455f-8fa3-93ad9bfc2a34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149441945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1149441945
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4174375030
Short name T180
Test name
Test status
Simulation time 29868593121 ps
CPU time 17.9 seconds
Started Jun 07 06:15:50 PM PDT 24
Finished Jun 07 06:16:09 PM PDT 24
Peak memory 209888 kb
Host smart-076eb268-b79d-4df3-842c-aeceb617d427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174375030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4174375030
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2169771893
Short name T47
Test name
Test status
Simulation time 1213697410 ps
CPU time 76.86 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:17:07 PM PDT 24
Peak memory 236320 kb
Host smart-08ff9a30-658c-409f-8f86-a8a8bca478a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169771893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2169771893
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.562417374
Short name T170
Test name
Test status
Simulation time 914075182 ps
CPU time 15.46 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 211552 kb
Host smart-60726a0f-ae7d-45e2-9dc3-656b7bcbc8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562417374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.562417374
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1990560302
Short name T293
Test name
Test status
Simulation time 2235883909 ps
CPU time 16.61 seconds
Started Jun 07 06:15:42 PM PDT 24
Finished Jun 07 06:16:00 PM PDT 24
Peak memory 210960 kb
Host smart-73f879b2-856c-4efe-a12b-c66bbe9b7595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990560302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1990560302
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2979132952
Short name T243
Test name
Test status
Simulation time 2366851980 ps
CPU time 14.69 seconds
Started Jun 07 06:15:50 PM PDT 24
Finished Jun 07 06:16:05 PM PDT 24
Peak memory 213468 kb
Host smart-cfd5b1ad-b890-4e42-8d41-8c62be91babe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979132952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2979132952
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.882207690
Short name T339
Test name
Test status
Simulation time 799112532 ps
CPU time 9.28 seconds
Started Jun 07 06:15:43 PM PDT 24
Finished Jun 07 06:15:53 PM PDT 24
Peak memory 210824 kb
Host smart-8c6d6d12-df09-4e3c-b0ee-3d00b59029f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882207690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.882207690
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.593590088
Short name T12
Test name
Test status
Simulation time 51973898635 ps
CPU time 1182.09 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:35:30 PM PDT 24
Peak memory 234980 kb
Host smart-96487a8d-0d00-496d-b61a-153292368c70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593590088 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.593590088
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2155424495
Short name T307
Test name
Test status
Simulation time 1803030433 ps
CPU time 14.77 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 210684 kb
Host smart-45cc3ad1-726c-4774-847c-45c07aba3880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155424495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2155424495
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3010839301
Short name T190
Test name
Test status
Simulation time 20837078497 ps
CPU time 182.25 seconds
Started Jun 07 06:15:41 PM PDT 24
Finished Jun 07 06:18:44 PM PDT 24
Peak memory 212688 kb
Host smart-0ea7f87b-fa30-42d8-b54d-161a5fee3494
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010839301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3010839301
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3622063597
Short name T44
Test name
Test status
Simulation time 1177440394 ps
CPU time 13.52 seconds
Started Jun 07 06:15:53 PM PDT 24
Finished Jun 07 06:16:07 PM PDT 24
Peak memory 211692 kb
Host smart-72c69295-f417-41bd-8928-b2c912880f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622063597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3622063597
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2616775983
Short name T326
Test name
Test status
Simulation time 7339162259 ps
CPU time 14.98 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 211000 kb
Host smart-8a30fad0-0098-433b-9d6f-b3cd7ad96f32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2616775983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2616775983
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3704300652
Short name T139
Test name
Test status
Simulation time 2954536628 ps
CPU time 10.83 seconds
Started Jun 07 06:15:56 PM PDT 24
Finished Jun 07 06:16:07 PM PDT 24
Peak memory 213380 kb
Host smart-8e0bd56f-35e2-403c-8d05-8a905f619204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704300652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3704300652
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2178861344
Short name T129
Test name
Test status
Simulation time 302008446 ps
CPU time 18.05 seconds
Started Jun 07 06:16:01 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 212780 kb
Host smart-b6500936-95e0-438a-aa43-cd8dcd6b6aa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178861344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2178861344
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1350405094
Short name T370
Test name
Test status
Simulation time 25128510820 ps
CPU time 1135.5 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:34:45 PM PDT 24
Peak memory 227276 kb
Host smart-f7f3194f-9a01-4f1c-940b-1e0886c13ddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350405094 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1350405094
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2832358549
Short name T145
Test name
Test status
Simulation time 4762205204 ps
CPU time 11.91 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:20 PM PDT 24
Peak memory 210800 kb
Host smart-2039e536-5576-47b6-be18-fb293d6f7dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832358549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2832358549
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1415694066
Short name T38
Test name
Test status
Simulation time 55741869314 ps
CPU time 205.72 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:19:32 PM PDT 24
Peak memory 237432 kb
Host smart-373b887c-6fa4-4ecc-bcef-c49d35fd27b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415694066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1415694066
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3733109053
Short name T268
Test name
Test status
Simulation time 11871379393 ps
CPU time 27.64 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:35 PM PDT 24
Peak memory 211796 kb
Host smart-b2f4a39a-7565-40b1-a20a-8e03eaa51201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733109053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3733109053
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1101148195
Short name T242
Test name
Test status
Simulation time 384623276 ps
CPU time 5.77 seconds
Started Jun 07 06:15:44 PM PDT 24
Finished Jun 07 06:15:51 PM PDT 24
Peak memory 210916 kb
Host smart-f09c2eba-6e3a-43a6-be09-711f8b8fa7cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101148195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1101148195
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3646123112
Short name T319
Test name
Test status
Simulation time 11917187481 ps
CPU time 33.03 seconds
Started Jun 07 06:15:43 PM PDT 24
Finished Jun 07 06:16:17 PM PDT 24
Peak memory 213972 kb
Host smart-b2edc3ec-1ae6-45cf-a05d-60db4181af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646123112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3646123112
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.4042795015
Short name T55
Test name
Test status
Simulation time 1933219801 ps
CPU time 22.1 seconds
Started Jun 07 06:15:45 PM PDT 24
Finished Jun 07 06:16:07 PM PDT 24
Peak memory 210748 kb
Host smart-be6081e7-44c2-4105-ae27-3c784deac891
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042795015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.4042795015
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2448582766
Short name T54
Test name
Test status
Simulation time 132940166776 ps
CPU time 5459.22 seconds
Started Jun 07 06:15:59 PM PDT 24
Finished Jun 07 07:46:59 PM PDT 24
Peak memory 235484 kb
Host smart-c55eb636-1436-4e5c-b333-f8936e178420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448582766 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2448582766
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4058195572
Short name T285
Test name
Test status
Simulation time 1480686158 ps
CPU time 13.02 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:01 PM PDT 24
Peak memory 210804 kb
Host smart-e9b6cb37-6c0d-4b3b-99e2-c8780d009fa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058195572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4058195572
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4077377320
Short name T229
Test name
Test status
Simulation time 3791159445 ps
CPU time 57.99 seconds
Started Jun 07 06:15:48 PM PDT 24
Finished Jun 07 06:16:47 PM PDT 24
Peak memory 238444 kb
Host smart-8b486f37-aa5e-4255-b230-e3599648fe02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077377320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4077377320
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1504388213
Short name T46
Test name
Test status
Simulation time 6118801172 ps
CPU time 28.64 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:35 PM PDT 24
Peak memory 212148 kb
Host smart-96ce991e-5c6d-4ca5-9aad-1d4720f8d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504388213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1504388213
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.47369401
Short name T2
Test name
Test status
Simulation time 5264731216 ps
CPU time 13.25 seconds
Started Jun 07 06:16:00 PM PDT 24
Finished Jun 07 06:16:14 PM PDT 24
Peak memory 211036 kb
Host smart-b705a94e-4e67-4ab2-9e4d-ae98ff07668a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47369401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.47369401
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.725103925
Short name T202
Test name
Test status
Simulation time 2092566461 ps
CPU time 22.37 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:10 PM PDT 24
Peak memory 213324 kb
Host smart-7d77b595-5d0c-4b1c-86f0-5e53fae8878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725103925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.725103925
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2913185962
Short name T303
Test name
Test status
Simulation time 290088688 ps
CPU time 17.13 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:29 PM PDT 24
Peak memory 214292 kb
Host smart-6e6f2c76-96a4-4e51-a418-395d486900f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913185962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2913185962
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2441314756
Short name T51
Test name
Test status
Simulation time 106707748922 ps
CPU time 2014.12 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:49:50 PM PDT 24
Peak memory 234620 kb
Host smart-649ae682-643f-4aaf-96ad-d1d631586129
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441314756 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2441314756
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1942307423
Short name T252
Test name
Test status
Simulation time 321264931 ps
CPU time 4.36 seconds
Started Jun 07 06:15:55 PM PDT 24
Finished Jun 07 06:16:00 PM PDT 24
Peak memory 210560 kb
Host smart-ad2d47a7-08cf-4372-8f92-5ed02646d4b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942307423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1942307423
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3093506550
Short name T21
Test name
Test status
Simulation time 1301421841 ps
CPU time 85.23 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:17:34 PM PDT 24
Peak memory 227652 kb
Host smart-89dd0fd0-8b82-40b4-a0d9-42488cfda461
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093506550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3093506550
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1079686115
Short name T162
Test name
Test status
Simulation time 15656403526 ps
CPU time 32.94 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:38 PM PDT 24
Peak memory 211812 kb
Host smart-0f571ad8-151d-4f28-a6c8-79051fc9fe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079686115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1079686115
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2923260592
Short name T264
Test name
Test status
Simulation time 1524549759 ps
CPU time 14.15 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 210920 kb
Host smart-10e8aab2-cdff-47fa-a8e1-b422100010fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923260592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2923260592
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2444707938
Short name T32
Test name
Test status
Simulation time 190153679 ps
CPU time 10.05 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:20 PM PDT 24
Peak memory 212540 kb
Host smart-76f0c15e-7b07-47a5-863a-bf548a580671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444707938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2444707938
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2210335880
Short name T240
Test name
Test status
Simulation time 40667418693 ps
CPU time 44.99 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:53 PM PDT 24
Peak memory 219008 kb
Host smart-78e1fe1f-5beb-412c-9997-feb3d73924fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210335880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2210335880
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3319195756
Short name T186
Test name
Test status
Simulation time 515953060 ps
CPU time 7.73 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:15:57 PM PDT 24
Peak memory 210720 kb
Host smart-78c7a0ce-3eca-4e68-98ef-89943fb3c8ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319195756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3319195756
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3074697446
Short name T86
Test name
Test status
Simulation time 20265059425 ps
CPU time 110.37 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:17:39 PM PDT 24
Peak memory 233316 kb
Host smart-a0405392-5806-4d7b-b4a6-72af46e2e039
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074697446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3074697446
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4020657215
Short name T157
Test name
Test status
Simulation time 381025254 ps
CPU time 5.41 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:12 PM PDT 24
Peak memory 210916 kb
Host smart-2e93fee7-8d60-447b-8ff7-4d1f30c04050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020657215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4020657215
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3177446348
Short name T334
Test name
Test status
Simulation time 191215213 ps
CPU time 9.97 seconds
Started Jun 07 06:15:48 PM PDT 24
Finished Jun 07 06:15:58 PM PDT 24
Peak memory 211684 kb
Host smart-b78acf10-2855-4f22-b138-fd0d988e6a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177446348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3177446348
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1134137389
Short name T209
Test name
Test status
Simulation time 18082798815 ps
CPU time 44.47 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:52 PM PDT 24
Peak memory 216212 kb
Host smart-ebc3348d-e872-4ad0-aa29-38b34fb9c7aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134137389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1134137389
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.545175599
Short name T328
Test name
Test status
Simulation time 1746783273 ps
CPU time 14.86 seconds
Started Jun 07 06:15:48 PM PDT 24
Finished Jun 07 06:16:03 PM PDT 24
Peak memory 210704 kb
Host smart-c8b3efef-3cae-41a0-8d95-8c096fcaf6d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545175599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.545175599
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3153007214
Short name T286
Test name
Test status
Simulation time 28496633047 ps
CPU time 98.4 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:17:51 PM PDT 24
Peak memory 234400 kb
Host smart-954fb8b0-48ea-4987-b695-80018c1731f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153007214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3153007214
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3985910988
Short name T337
Test name
Test status
Simulation time 3699894200 ps
CPU time 21 seconds
Started Jun 07 06:15:51 PM PDT 24
Finished Jun 07 06:16:13 PM PDT 24
Peak memory 211512 kb
Host smart-91abbd16-92e1-4d36-ac6d-44a7637b5593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985910988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3985910988
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.249125945
Short name T274
Test name
Test status
Simulation time 10942320849 ps
CPU time 14.53 seconds
Started Jun 07 06:15:46 PM PDT 24
Finished Jun 07 06:16:01 PM PDT 24
Peak memory 211044 kb
Host smart-f758c706-399c-4229-84aa-7f1da58ccf66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249125945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.249125945
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3690897091
Short name T75
Test name
Test status
Simulation time 7544892877 ps
CPU time 38.23 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:26 PM PDT 24
Peak memory 213904 kb
Host smart-624c1cb8-5f32-4b68-bea8-bb514d9507d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690897091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3690897091
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.643242155
Short name T362
Test name
Test status
Simulation time 7941429598 ps
CPU time 69.3 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:17:17 PM PDT 24
Peak memory 215544 kb
Host smart-b0c6bf66-a381-4724-90f7-41399a8e3a29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643242155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.643242155
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.929329752
Short name T220
Test name
Test status
Simulation time 1475779284 ps
CPU time 7.1 seconds
Started Jun 07 06:15:51 PM PDT 24
Finished Jun 07 06:15:59 PM PDT 24
Peak memory 210744 kb
Host smart-a93b08e2-d04d-4272-a38e-70d58f1a746c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929329752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.929329752
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2580558178
Short name T359
Test name
Test status
Simulation time 44814122448 ps
CPU time 406.95 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:22:55 PM PDT 24
Peak memory 236368 kb
Host smart-e90b5ba8-010f-49f4-a438-4740b483a8fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580558178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2580558178
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2312738262
Short name T138
Test name
Test status
Simulation time 9736889988 ps
CPU time 29.77 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:37 PM PDT 24
Peak memory 212012 kb
Host smart-d1ad1ec9-5691-4672-94a3-4ebded11f2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312738262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2312738262
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4219730398
Short name T245
Test name
Test status
Simulation time 1789568524 ps
CPU time 15.5 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:16:05 PM PDT 24
Peak memory 210892 kb
Host smart-2739cfdc-f3aa-4a75-ad13-5af44400287d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219730398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4219730398
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1492127577
Short name T260
Test name
Test status
Simulation time 893314095 ps
CPU time 10.02 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:15 PM PDT 24
Peak memory 213184 kb
Host smart-cbdb111f-1849-4e4e-9608-f3129e33e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492127577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1492127577
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3272471151
Short name T217
Test name
Test status
Simulation time 25945039313 ps
CPU time 125.23 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:17:53 PM PDT 24
Peak memory 218960 kb
Host smart-886096ab-e9fe-4b28-abce-88b98cdd74ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272471151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3272471151
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3513225316
Short name T53
Test name
Test status
Simulation time 45640259592 ps
CPU time 1783.72 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:45:51 PM PDT 24
Peak memory 237272 kb
Host smart-5051ff7f-f4db-433c-8fcd-d89258df81fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513225316 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3513225316
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3892015720
Short name T298
Test name
Test status
Simulation time 332713310 ps
CPU time 4.19 seconds
Started Jun 07 06:15:53 PM PDT 24
Finished Jun 07 06:15:58 PM PDT 24
Peak memory 210696 kb
Host smart-f8a629d4-3401-4d66-8295-0f406a527193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892015720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3892015720
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1658185120
Short name T317
Test name
Test status
Simulation time 93702580985 ps
CPU time 244.73 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:20:09 PM PDT 24
Peak memory 239436 kb
Host smart-255f14c2-ab1e-4eae-b19c-916c546b64d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658185120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1658185120
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1852075254
Short name T291
Test name
Test status
Simulation time 25671432367 ps
CPU time 35.27 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:43 PM PDT 24
Peak memory 211940 kb
Host smart-b8662a24-924a-45bc-a295-317dcb04e220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852075254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1852075254
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1887354041
Short name T351
Test name
Test status
Simulation time 95054685 ps
CPU time 5.65 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:14 PM PDT 24
Peak memory 210884 kb
Host smart-9c7a5507-793c-4c3b-bf1a-8726721d7888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887354041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1887354041
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3580337994
Short name T156
Test name
Test status
Simulation time 936673627 ps
CPU time 16 seconds
Started Jun 07 06:15:52 PM PDT 24
Finished Jun 07 06:16:09 PM PDT 24
Peak memory 213024 kb
Host smart-957be054-c201-4904-a140-60280ac32381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580337994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3580337994
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3951819044
Short name T57
Test name
Test status
Simulation time 158301144 ps
CPU time 6.91 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:12 PM PDT 24
Peak memory 210756 kb
Host smart-f94b1a45-9f36-4f86-b5a7-6e6faa537b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951819044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3951819044
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1321907166
Short name T325
Test name
Test status
Simulation time 928500990 ps
CPU time 9.8 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:15:59 PM PDT 24
Peak memory 210696 kb
Host smart-07bc19d1-4085-4afe-89ba-8fb09d6a05dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321907166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1321907166
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2637338160
Short name T261
Test name
Test status
Simulation time 21590509177 ps
CPU time 217.9 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:19:28 PM PDT 24
Peak memory 224264 kb
Host smart-b4d89bdd-0c04-4528-a993-58e688b7be4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637338160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2637338160
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2421757910
Short name T367
Test name
Test status
Simulation time 1310487945 ps
CPU time 18.26 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:31 PM PDT 24
Peak memory 211468 kb
Host smart-54addc8f-7941-4f2b-8d70-3c15ca9be102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421757910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2421757910
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1995866342
Short name T103
Test name
Test status
Simulation time 7434673042 ps
CPU time 12.46 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 211040 kb
Host smart-0c2954f5-c426-43a3-b94a-3171b13eb749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995866342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1995866342
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1844326291
Short name T348
Test name
Test status
Simulation time 15559449016 ps
CPU time 34.63 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:40 PM PDT 24
Peak memory 212904 kb
Host smart-cad49604-f258-459b-9191-ce9663b46557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844326291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1844326291
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3179779411
Short name T218
Test name
Test status
Simulation time 4299881329 ps
CPU time 16.23 seconds
Started Jun 07 06:15:55 PM PDT 24
Finished Jun 07 06:16:11 PM PDT 24
Peak memory 212020 kb
Host smart-ea159284-914e-40c8-bee6-5dc389e2f06a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179779411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3179779411
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.284822551
Short name T201
Test name
Test status
Simulation time 20377323482 ps
CPU time 125.44 seconds
Started Jun 07 06:16:00 PM PDT 24
Finished Jun 07 06:18:06 PM PDT 24
Peak memory 234460 kb
Host smart-6cd60049-2fce-4845-9bc8-0f432c9fd8e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284822551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.284822551
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2878103258
Short name T329
Test name
Test status
Simulation time 693534644 ps
CPU time 9.69 seconds
Started Jun 07 06:15:42 PM PDT 24
Finished Jun 07 06:15:52 PM PDT 24
Peak memory 211508 kb
Host smart-13564760-b899-4f33-a19d-08a5f124edcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878103258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2878103258
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2786772253
Short name T140
Test name
Test status
Simulation time 2341093229 ps
CPU time 12.09 seconds
Started Jun 07 06:15:17 PM PDT 24
Finished Jun 07 06:15:30 PM PDT 24
Peak memory 210944 kb
Host smart-f605f39f-56ff-4f9f-af16-90b04214da13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786772253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2786772253
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3018153834
Short name T29
Test name
Test status
Simulation time 6448893753 ps
CPU time 60.15 seconds
Started Jun 07 06:15:21 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 236304 kb
Host smart-4c28d330-7f9e-4ff8-ba6f-a0ddace361ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018153834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3018153834
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3551767783
Short name T125
Test name
Test status
Simulation time 2068966831 ps
CPU time 22.97 seconds
Started Jun 07 06:15:23 PM PDT 24
Finished Jun 07 06:15:47 PM PDT 24
Peak memory 212848 kb
Host smart-2a85f8a8-4957-46ce-ae9d-dd6a710ee1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551767783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3551767783
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4289813159
Short name T134
Test name
Test status
Simulation time 1736352214 ps
CPU time 16.15 seconds
Started Jun 07 06:15:45 PM PDT 24
Finished Jun 07 06:16:01 PM PDT 24
Peak memory 215000 kb
Host smart-b8575fec-792c-441f-bb1a-119ad9f36dd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289813159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4289813159
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.145859003
Short name T16
Test name
Test status
Simulation time 62777909229 ps
CPU time 644.2 seconds
Started Jun 07 06:15:17 PM PDT 24
Finished Jun 07 06:26:02 PM PDT 24
Peak memory 234668 kb
Host smart-c06f6962-ef85-455a-9196-1efa9a34f92f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145859003 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.145859003
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.897985246
Short name T356
Test name
Test status
Simulation time 1425697109 ps
CPU time 11.81 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:18 PM PDT 24
Peak memory 210740 kb
Host smart-28c87ff1-37ad-4434-9bc6-1ba40d343820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897985246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.897985246
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1263229595
Short name T168
Test name
Test status
Simulation time 28270700597 ps
CPU time 152.85 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:18:42 PM PDT 24
Peak memory 232684 kb
Host smart-b2410181-2fe5-406f-8c37-e1db8fa3a285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263229595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1263229595
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.692395348
Short name T295
Test name
Test status
Simulation time 1704411026 ps
CPU time 20.49 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:28 PM PDT 24
Peak memory 211532 kb
Host smart-bb8ed5cd-ab67-46d6-89cd-d0c31dbf7db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692395348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.692395348
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3887021239
Short name T91
Test name
Test status
Simulation time 751080533 ps
CPU time 10.56 seconds
Started Jun 07 06:15:56 PM PDT 24
Finished Jun 07 06:16:07 PM PDT 24
Peak memory 211044 kb
Host smart-54869e3e-20bd-47e6-91f9-b6e9eb517cfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887021239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3887021239
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3393223097
Short name T174
Test name
Test status
Simulation time 3775974390 ps
CPU time 28.7 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:36 PM PDT 24
Peak memory 213148 kb
Host smart-c60be995-4f55-4e4f-bfa1-a8655ef7b35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393223097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3393223097
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1190154988
Short name T357
Test name
Test status
Simulation time 44189189853 ps
CPU time 35.26 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 216576 kb
Host smart-ca7c7781-c527-482f-9ce5-efeaa2c47f74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190154988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1190154988
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.763595779
Short name T335
Test name
Test status
Simulation time 6990681194 ps
CPU time 15.09 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 210792 kb
Host smart-7e3a6a60-8b31-4bd9-8800-221093284680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763595779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.763595779
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3614596470
Short name T279
Test name
Test status
Simulation time 20182720100 ps
CPU time 184.7 seconds
Started Jun 07 06:15:53 PM PDT 24
Finished Jun 07 06:18:58 PM PDT 24
Peak memory 212304 kb
Host smart-09d070c5-0fc1-46cb-b415-212e8f57de3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614596470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3614596470
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1452701440
Short name T345
Test name
Test status
Simulation time 1615808517 ps
CPU time 17.16 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:16:05 PM PDT 24
Peak memory 212032 kb
Host smart-79c75c8e-9359-4039-9c9e-7333880bbf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452701440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1452701440
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.39482414
Short name T131
Test name
Test status
Simulation time 2711899806 ps
CPU time 7.57 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 210920 kb
Host smart-dbe45f21-f325-4934-8ad3-0a82e1b83b16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39482414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.39482414
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4114682376
Short name T341
Test name
Test status
Simulation time 6915564442 ps
CPU time 21.4 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:26 PM PDT 24
Peak memory 213044 kb
Host smart-87306c5a-27fd-4ac4-976b-cbe8480d2588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114682376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4114682376
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.892868064
Short name T4
Test name
Test status
Simulation time 283569019 ps
CPU time 16.84 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 216092 kb
Host smart-7bed983e-5a5a-45ad-9aee-9d2d3f03357e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892868064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.892868064
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3970723945
Short name T6
Test name
Test status
Simulation time 3618275377 ps
CPU time 15.56 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:16:05 PM PDT 24
Peak memory 210684 kb
Host smart-db6c7463-0e63-4323-bbd8-e9215851d341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970723945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3970723945
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.702910628
Short name T166
Test name
Test status
Simulation time 60375509010 ps
CPU time 167.5 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:18:38 PM PDT 24
Peak memory 232764 kb
Host smart-feb2cc6c-7e02-4621-a479-ce19f79ad42d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702910628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.702910628
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3947885084
Short name T354
Test name
Test status
Simulation time 2506257676 ps
CPU time 24.87 seconds
Started Jun 07 06:15:52 PM PDT 24
Finished Jun 07 06:16:17 PM PDT 24
Peak memory 211444 kb
Host smart-6b4094ed-a8f8-4e92-8d3e-c6d77e674d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947885084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3947885084
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3668875175
Short name T332
Test name
Test status
Simulation time 2693953540 ps
CPU time 13.15 seconds
Started Jun 07 06:15:45 PM PDT 24
Finished Jun 07 06:15:59 PM PDT 24
Peak memory 210940 kb
Host smart-3c1a017d-e009-432f-b7e8-d3637b6c8bb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668875175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3668875175
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3553079731
Short name T142
Test name
Test status
Simulation time 16485192526 ps
CPU time 25.53 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:36 PM PDT 24
Peak memory 213800 kb
Host smart-55952a23-cfac-421c-bc9f-4f81d5993793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553079731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3553079731
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.654443622
Short name T163
Test name
Test status
Simulation time 2379732807 ps
CPU time 13.52 seconds
Started Jun 07 06:15:55 PM PDT 24
Finished Jun 07 06:16:09 PM PDT 24
Peak memory 210760 kb
Host smart-9ad37589-1eac-4f82-ac97-4153068b0acd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654443622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.654443622
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.383878807
Short name T294
Test name
Test status
Simulation time 58202451971 ps
CPU time 601.35 seconds
Started Jun 07 06:15:48 PM PDT 24
Finished Jun 07 06:25:50 PM PDT 24
Peak memory 227372 kb
Host smart-665cfcf5-a9c4-4371-8d65-46776544590d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383878807 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.383878807
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.790043232
Short name T318
Test name
Test status
Simulation time 786450355 ps
CPU time 9.29 seconds
Started Jun 07 06:15:51 PM PDT 24
Finished Jun 07 06:16:01 PM PDT 24
Peak memory 210716 kb
Host smart-7591345f-666d-43a8-a147-83cfe3501ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790043232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.790043232
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3515335164
Short name T205
Test name
Test status
Simulation time 6091054147 ps
CPU time 99.34 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:18:00 PM PDT 24
Peak memory 240064 kb
Host smart-6208d847-3d24-4133-b3ae-21bb1bc85d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515335164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3515335164
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1212481564
Short name T250
Test name
Test status
Simulation time 665241907 ps
CPU time 9.61 seconds
Started Jun 07 06:15:45 PM PDT 24
Finished Jun 07 06:15:55 PM PDT 24
Peak memory 211536 kb
Host smart-f96c0cc4-b4d2-46f6-b4b1-32c02242e97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212481564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1212481564
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2967832353
Short name T234
Test name
Test status
Simulation time 6716761568 ps
CPU time 15.57 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 211032 kb
Host smart-49feb1b9-5b7c-494b-9812-c8449c5c2dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967832353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2967832353
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.700519657
Short name T353
Test name
Test status
Simulation time 12384678016 ps
CPU time 34.37 seconds
Started Jun 07 06:16:03 PM PDT 24
Finished Jun 07 06:16:38 PM PDT 24
Peak memory 214448 kb
Host smart-dd757f00-6e8b-4c3f-ab8c-9721b7040044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700519657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.700519657
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1131664805
Short name T181
Test name
Test status
Simulation time 294461790 ps
CPU time 17.23 seconds
Started Jun 07 06:15:52 PM PDT 24
Finished Jun 07 06:16:10 PM PDT 24
Peak memory 212976 kb
Host smart-bc370216-3dd3-4b26-bdc4-0875f03f0ac0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131664805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1131664805
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3867221933
Short name T312
Test name
Test status
Simulation time 6767453749 ps
CPU time 15.81 seconds
Started Jun 07 06:15:51 PM PDT 24
Finished Jun 07 06:16:08 PM PDT 24
Peak memory 210824 kb
Host smart-e586aa96-e7e8-4800-8dbb-d0cc0c9d83d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867221933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3867221933
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3631466472
Short name T35
Test name
Test status
Simulation time 118943962007 ps
CPU time 286.72 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:20:55 PM PDT 24
Peak memory 236264 kb
Host smart-5e649246-1d50-45d9-8b87-5d9a8211d855
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631466472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3631466472
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3898784979
Short name T363
Test name
Test status
Simulation time 7170214890 ps
CPU time 29.59 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:40 PM PDT 24
Peak memory 211920 kb
Host smart-71580299-cfb0-478a-abdc-e127d635d15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898784979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3898784979
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3907664577
Short name T324
Test name
Test status
Simulation time 3962709922 ps
CPU time 11.3 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:19 PM PDT 24
Peak memory 210944 kb
Host smart-484fb69a-cfa1-4721-986a-58c7d7b8f053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907664577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3907664577
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2518227680
Short name T282
Test name
Test status
Simulation time 15534091158 ps
CPU time 32.79 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:37 PM PDT 24
Peak memory 214136 kb
Host smart-e45ecdf4-16a3-47a8-9637-7e12eb21ec8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518227680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2518227680
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1547535931
Short name T235
Test name
Test status
Simulation time 10370293422 ps
CPU time 86.62 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:17:40 PM PDT 24
Peak memory 216464 kb
Host smart-90e0d461-b5ec-45b4-83ec-6b108e9f272b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547535931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1547535931
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3337760796
Short name T25
Test name
Test status
Simulation time 16885657634 ps
CPU time 14.5 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:21 PM PDT 24
Peak memory 210844 kb
Host smart-4fccd034-2a28-479b-bb45-ad0ce36262de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337760796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3337760796
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3049788830
Short name T171
Test name
Test status
Simulation time 4214114061 ps
CPU time 100.99 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:17:51 PM PDT 24
Peak memory 227344 kb
Host smart-a63bc59a-1a75-4912-9aeb-ae996a735a1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049788830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3049788830
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1197891461
Short name T177
Test name
Test status
Simulation time 3520229550 ps
CPU time 30.64 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:40 PM PDT 24
Peak memory 211448 kb
Host smart-6993e715-6619-4ddd-af89-b463fc06ce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197891461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1197891461
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2033927503
Short name T300
Test name
Test status
Simulation time 5617293839 ps
CPU time 13.44 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 211016 kb
Host smart-10d78b8c-ca01-4342-8f0d-b7d856c0dba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033927503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2033927503
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1748766745
Short name T230
Test name
Test status
Simulation time 1037567879 ps
CPU time 15.95 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:25 PM PDT 24
Peak memory 213248 kb
Host smart-32144d31-cfb8-4620-8868-b058f25e7358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748766745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1748766745
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3856260172
Short name T8
Test name
Test status
Simulation time 347523358 ps
CPU time 9.89 seconds
Started Jun 07 06:16:03 PM PDT 24
Finished Jun 07 06:16:13 PM PDT 24
Peak memory 210720 kb
Host smart-3201e0c6-ee35-40c2-88da-cc04f4dd7582
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856260172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3856260172
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2159162923
Short name T272
Test name
Test status
Simulation time 24870046830 ps
CPU time 1076.73 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:34:05 PM PDT 24
Peak memory 235480 kb
Host smart-46a4f24a-5716-4f91-9977-715edc49b3d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159162923 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2159162923
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3793288131
Short name T340
Test name
Test status
Simulation time 1832053674 ps
CPU time 14.41 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 210688 kb
Host smart-7e90b7ac-a963-4fdd-bb24-1fa3250edce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793288131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3793288131
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1728881464
Short name T36
Test name
Test status
Simulation time 109049966930 ps
CPU time 296.28 seconds
Started Jun 07 06:16:26 PM PDT 24
Finished Jun 07 06:21:23 PM PDT 24
Peak memory 224648 kb
Host smart-b6fd0f8a-b698-4994-9cf9-975b9c89b9a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728881464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1728881464
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1369873984
Short name T236
Test name
Test status
Simulation time 7205617142 ps
CPU time 20.95 seconds
Started Jun 07 06:16:14 PM PDT 24
Finished Jun 07 06:16:35 PM PDT 24
Peak memory 211044 kb
Host smart-8119e69f-511d-4bec-b8f3-be35eb9bc225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369873984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1369873984
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1912754235
Short name T127
Test name
Test status
Simulation time 3471149837 ps
CPU time 10.64 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 210980 kb
Host smart-d53b2094-fad5-40a2-92dc-57c9df414853
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912754235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1912754235
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3433683584
Short name T31
Test name
Test status
Simulation time 1470861719 ps
CPU time 20.84 seconds
Started Jun 07 06:16:02 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 213200 kb
Host smart-1aa3065a-1322-44da-9e1c-715d336b1bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433683584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3433683584
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.582834984
Short name T165
Test name
Test status
Simulation time 12496662837 ps
CPU time 39.88 seconds
Started Jun 07 06:16:01 PM PDT 24
Finished Jun 07 06:16:41 PM PDT 24
Peak memory 217084 kb
Host smart-12c3c981-2786-42c5-9f55-668bca9020f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582834984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.582834984
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1663365230
Short name T176
Test name
Test status
Simulation time 7100717273 ps
CPU time 14.52 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 210672 kb
Host smart-4871ba67-73a4-43e9-a22a-47edcba46c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663365230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1663365230
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2063122196
Short name T231
Test name
Test status
Simulation time 38637599602 ps
CPU time 134.27 seconds
Started Jun 07 06:15:55 PM PDT 24
Finished Jun 07 06:18:10 PM PDT 24
Peak memory 236472 kb
Host smart-afb038f1-bfd6-4216-9926-46c24e11abb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063122196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2063122196
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.368632512
Short name T27
Test name
Test status
Simulation time 1381816415 ps
CPU time 14.2 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:27 PM PDT 24
Peak memory 211600 kb
Host smart-51497e05-4c7a-4277-b383-6aeb63e3bfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368632512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.368632512
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4083088959
Short name T104
Test name
Test status
Simulation time 2648441924 ps
CPU time 13.35 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 210932 kb
Host smart-ef24f1ae-7ea4-4fae-bc2b-ed76ed076f20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083088959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4083088959
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2836343326
Short name T128
Test name
Test status
Simulation time 561118110 ps
CPU time 29.67 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:40 PM PDT 24
Peak memory 215012 kb
Host smart-951eb081-f0fd-408c-85ff-a0afdb3f1e92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836343326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2836343326
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.315999711
Short name T14
Test name
Test status
Simulation time 85114511532 ps
CPU time 4772.85 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 07:35:21 PM PDT 24
Peak memory 235500 kb
Host smart-bae0c74f-99eb-43b8-8f84-a0f0e6848ec9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315999711 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.315999711
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.234234199
Short name T212
Test name
Test status
Simulation time 9328215644 ps
CPU time 17.14 seconds
Started Jun 07 06:15:49 PM PDT 24
Finished Jun 07 06:16:07 PM PDT 24
Peak memory 210864 kb
Host smart-5c4badd4-8f0f-4399-b0de-0d53e1f7312d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234234199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.234234199
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.179379029
Short name T262
Test name
Test status
Simulation time 664878674 ps
CPU time 9.54 seconds
Started Jun 07 06:16:33 PM PDT 24
Finished Jun 07 06:16:43 PM PDT 24
Peak memory 211624 kb
Host smart-2a50d26a-45bf-4a27-b2a5-4dedd480be18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179379029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.179379029
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3373806600
Short name T222
Test name
Test status
Simulation time 7736346134 ps
CPU time 16.51 seconds
Started Jun 07 06:15:59 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 211004 kb
Host smart-895ef4f6-b2b5-417d-8d13-e8eb21d6981e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373806600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3373806600
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1980109898
Short name T158
Test name
Test status
Simulation time 6735828219 ps
CPU time 33.8 seconds
Started Jun 07 06:16:02 PM PDT 24
Finished Jun 07 06:16:36 PM PDT 24
Peak memory 213484 kb
Host smart-12c3b90f-33f2-441e-a9e6-bebfadd4d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980109898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1980109898
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3913411829
Short name T310
Test name
Test status
Simulation time 6712673555 ps
CPU time 69.85 seconds
Started Jun 07 06:16:16 PM PDT 24
Finished Jun 07 06:17:26 PM PDT 24
Peak memory 216040 kb
Host smart-57cf665a-a83e-4b21-9ae3-7777aaff8413
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913411829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3913411829
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1610469367
Short name T154
Test name
Test status
Simulation time 168441413 ps
CPU time 4.2 seconds
Started Jun 07 06:15:54 PM PDT 24
Finished Jun 07 06:15:59 PM PDT 24
Peak memory 210724 kb
Host smart-73d8b590-1b97-4f60-8dda-8cd57d7cc638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610469367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1610469367
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1169225321
Short name T273
Test name
Test status
Simulation time 193626238124 ps
CPU time 458.64 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:23:55 PM PDT 24
Peak memory 213228 kb
Host smart-12ac307a-800e-4de4-b813-b4898d988bf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169225321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1169225321
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3202714561
Short name T150
Test name
Test status
Simulation time 32723740544 ps
CPU time 26.77 seconds
Started Jun 07 06:15:58 PM PDT 24
Finished Jun 07 06:16:25 PM PDT 24
Peak memory 211664 kb
Host smart-10d1cb10-3c10-4449-86f5-9db6e64044e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202714561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3202714561
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2480660617
Short name T314
Test name
Test status
Simulation time 2171532299 ps
CPU time 17.76 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:16:24 PM PDT 24
Peak memory 210972 kb
Host smart-e90dd0e2-8b89-465f-a391-8f7168c69bda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480660617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2480660617
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2504100241
Short name T338
Test name
Test status
Simulation time 16775049796 ps
CPU time 34.3 seconds
Started Jun 07 06:16:16 PM PDT 24
Finished Jun 07 06:16:55 PM PDT 24
Peak memory 213472 kb
Host smart-855a6b84-fdaf-47c0-bde5-37f0730cc87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504100241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2504100241
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3243979891
Short name T159
Test name
Test status
Simulation time 2752656569 ps
CPU time 28.81 seconds
Started Jun 07 06:16:34 PM PDT 24
Finished Jun 07 06:17:03 PM PDT 24
Peak memory 213412 kb
Host smart-aed24e77-dba8-4da1-b894-3d1b32a4b5fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243979891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3243979891
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1473230116
Short name T239
Test name
Test status
Simulation time 1522251409 ps
CPU time 12.99 seconds
Started Jun 07 06:16:00 PM PDT 24
Finished Jun 07 06:16:13 PM PDT 24
Peak memory 210708 kb
Host smart-23d2b095-07d1-4aad-8606-12bbfba5c246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473230116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1473230116
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.589502089
Short name T355
Test name
Test status
Simulation time 4341912846 ps
CPU time 121.19 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:18:07 PM PDT 24
Peak memory 237404 kb
Host smart-04129665-d8ab-4328-a75d-adbb9e01bada
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589502089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.589502089
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1926664352
Short name T373
Test name
Test status
Simulation time 2704215214 ps
CPU time 26.17 seconds
Started Jun 07 06:15:18 PM PDT 24
Finished Jun 07 06:15:44 PM PDT 24
Peak memory 211432 kb
Host smart-56cb8ede-a2e6-45c3-9704-e4031834c262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926664352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1926664352
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1857200320
Short name T155
Test name
Test status
Simulation time 3878328227 ps
CPU time 9.41 seconds
Started Jun 07 06:15:26 PM PDT 24
Finished Jun 07 06:15:36 PM PDT 24
Peak memory 211036 kb
Host smart-650d526f-4a82-4ff9-ba8d-8b8a012b0e92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857200320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1857200320
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1812423645
Short name T24
Test name
Test status
Simulation time 1296645798 ps
CPU time 102.67 seconds
Started Jun 07 06:15:53 PM PDT 24
Finished Jun 07 06:17:36 PM PDT 24
Peak memory 236244 kb
Host smart-1ce61e6f-7db1-4759-8efa-6fd274095be1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812423645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1812423645
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3575761908
Short name T316
Test name
Test status
Simulation time 19589103069 ps
CPU time 24.08 seconds
Started Jun 07 06:15:31 PM PDT 24
Finished Jun 07 06:15:55 PM PDT 24
Peak memory 214016 kb
Host smart-ebd10266-8043-4da6-a34a-7e21a5abc83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575761908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3575761908
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1412528450
Short name T189
Test name
Test status
Simulation time 1575364495 ps
CPU time 17.62 seconds
Started Jun 07 06:15:29 PM PDT 24
Finished Jun 07 06:15:47 PM PDT 24
Peak memory 211956 kb
Host smart-7427f7d7-73b1-4e4d-8643-4190e6d634c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412528450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1412528450
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4037758884
Short name T365
Test name
Test status
Simulation time 70091479466 ps
CPU time 2759.46 seconds
Started Jun 07 06:15:43 PM PDT 24
Finished Jun 07 07:01:43 PM PDT 24
Peak memory 240276 kb
Host smart-44939275-cd4b-483b-aa95-d930b6945dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037758884 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.4037758884
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2909334395
Short name T275
Test name
Test status
Simulation time 702552391 ps
CPU time 8.18 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:20 PM PDT 24
Peak memory 210720 kb
Host smart-770e3787-defe-43f1-adc1-19a5f7f6432c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909334395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2909334395
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.182155543
Short name T226
Test name
Test status
Simulation time 2134082418 ps
CPU time 23.41 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:37 PM PDT 24
Peak memory 211544 kb
Host smart-b7799dc8-2af6-4d35-aec4-c0b31b7037b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182155543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.182155543
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1351316810
Short name T258
Test name
Test status
Simulation time 1983877731 ps
CPU time 17.15 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:30 PM PDT 24
Peak memory 210880 kb
Host smart-6c7cec9d-904c-4129-a0a3-ed5c28f3226a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351316810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1351316810
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3010490142
Short name T130
Test name
Test status
Simulation time 710331043 ps
CPU time 10.32 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:15 PM PDT 24
Peak memory 213100 kb
Host smart-622549aa-bd28-4ba0-8f09-997da2de7e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010490142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3010490142
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2948997868
Short name T306
Test name
Test status
Simulation time 1034045021 ps
CPU time 11.13 seconds
Started Jun 07 06:16:15 PM PDT 24
Finished Jun 07 06:16:27 PM PDT 24
Peak memory 211584 kb
Host smart-65b90607-1f41-471a-ab98-69df90c1294d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948997868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2948997868
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.128099152
Short name T175
Test name
Test status
Simulation time 8374919941 ps
CPU time 16.24 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 210844 kb
Host smart-6e3fe29a-975f-4c9c-84bd-cd6bccda9a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128099152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.128099152
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.9124310
Short name T88
Test name
Test status
Simulation time 46296928379 ps
CPU time 215.7 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 234480 kb
Host smart-c8b4593c-341a-4a07-9e56-1464755599c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9124310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_cor
rupt_sig_fatal_chk.9124310
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3262535738
Short name T227
Test name
Test status
Simulation time 1620711924 ps
CPU time 19.01 seconds
Started Jun 07 06:16:17 PM PDT 24
Finished Jun 07 06:16:36 PM PDT 24
Peak memory 211544 kb
Host smart-6107f4e2-6afc-4092-a6eb-f654ce231277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262535738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3262535738
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.409079385
Short name T9
Test name
Test status
Simulation time 240532142 ps
CPU time 5.35 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:12 PM PDT 24
Peak memory 210908 kb
Host smart-563b9d13-fc54-4033-aa44-91dd47019aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409079385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.409079385
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.937059637
Short name T290
Test name
Test status
Simulation time 9508641260 ps
CPU time 20.94 seconds
Started Jun 07 06:16:00 PM PDT 24
Finished Jun 07 06:16:21 PM PDT 24
Peak memory 214052 kb
Host smart-ba0bfaa1-3b1a-49d0-99cf-4f847bb535b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937059637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.937059637
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1905399558
Short name T18
Test name
Test status
Simulation time 987764763 ps
CPU time 14.06 seconds
Started Jun 07 06:15:53 PM PDT 24
Finished Jun 07 06:16:08 PM PDT 24
Peak memory 212648 kb
Host smart-c90c7ab0-7f67-475c-8f30-193d94233491
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905399558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1905399558
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1111554799
Short name T213
Test name
Test status
Simulation time 665361169 ps
CPU time 5.61 seconds
Started Jun 07 06:16:39 PM PDT 24
Finished Jun 07 06:16:45 PM PDT 24
Peak memory 210784 kb
Host smart-6fb62887-3c01-4f26-92f3-09993afbaf27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111554799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1111554799
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2583033338
Short name T372
Test name
Test status
Simulation time 239708123183 ps
CPU time 493.2 seconds
Started Jun 07 06:16:38 PM PDT 24
Finished Jun 07 06:24:52 PM PDT 24
Peak memory 236488 kb
Host smart-94d1ddba-61c0-4ace-b224-805d45e2da5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583033338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2583033338
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2964070894
Short name T210
Test name
Test status
Simulation time 173821913 ps
CPU time 9.37 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:22 PM PDT 24
Peak memory 211428 kb
Host smart-512de832-d3fa-4bde-bef1-6317b741df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964070894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2964070894
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2241536740
Short name T288
Test name
Test status
Simulation time 2246145112 ps
CPU time 18.28 seconds
Started Jun 07 06:16:13 PM PDT 24
Finished Jun 07 06:16:32 PM PDT 24
Peak memory 210936 kb
Host smart-12e2b905-51c2-481e-b638-e3c20259b94c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241536740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2241536740
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4171964336
Short name T147
Test name
Test status
Simulation time 2842545300 ps
CPU time 26.74 seconds
Started Jun 07 06:16:04 PM PDT 24
Finished Jun 07 06:16:31 PM PDT 24
Peak memory 211616 kb
Host smart-4a8bb2fb-f268-4b3f-9e99-c670f50aa1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171964336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4171964336
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2690582759
Short name T187
Test name
Test status
Simulation time 547391685 ps
CPU time 16.6 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 213388 kb
Host smart-4806c3d4-45b0-44dd-a598-3b4816d11bce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690582759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2690582759
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2386728149
Short name T349
Test name
Test status
Simulation time 85491485 ps
CPU time 4.37 seconds
Started Jun 07 06:16:16 PM PDT 24
Finished Jun 07 06:16:21 PM PDT 24
Peak memory 210680 kb
Host smart-d929b41e-4eeb-4879-b8f4-92ae7288d336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386728149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2386728149
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.514411522
Short name T167
Test name
Test status
Simulation time 87598905176 ps
CPU time 258.72 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 228220 kb
Host smart-d7543f8b-98bc-445e-9245-232141d464c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514411522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.514411522
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.620732825
Short name T41
Test name
Test status
Simulation time 347566637 ps
CPU time 9.29 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:17 PM PDT 24
Peak memory 211432 kb
Host smart-03d0f185-a7d0-48ad-9833-186b52c62ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620732825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.620732825
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2538035760
Short name T214
Test name
Test status
Simulation time 95420171 ps
CPU time 5.44 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:15 PM PDT 24
Peak memory 210912 kb
Host smart-899d3970-579c-4d5f-9f47-d8d0983c5f33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2538035760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2538035760
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2723915406
Short name T342
Test name
Test status
Simulation time 3124648259 ps
CPU time 22.48 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:33 PM PDT 24
Peak memory 212792 kb
Host smart-66894825-74b8-4c29-8e6d-4b2175c203cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723915406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2723915406
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2713426153
Short name T17
Test name
Test status
Simulation time 5691369564 ps
CPU time 35.26 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:44 PM PDT 24
Peak memory 219004 kb
Host smart-fcbb1c60-adbd-4297-a175-5ebefe9ba189
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713426153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2713426153
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3471546857
Short name T280
Test name
Test status
Simulation time 265377584 ps
CPU time 6.19 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:18 PM PDT 24
Peak memory 210788 kb
Host smart-b36b45d9-8ea3-40bf-bdfa-a557519cc508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471546857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3471546857
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2289428626
Short name T238
Test name
Test status
Simulation time 91554940307 ps
CPU time 459.43 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:23:46 PM PDT 24
Peak memory 237532 kb
Host smart-430390f6-8b02-4865-bf26-2fe401fad3b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289428626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2289428626
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2345549524
Short name T346
Test name
Test status
Simulation time 4227526873 ps
CPU time 34.03 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:17:19 PM PDT 24
Peak memory 211492 kb
Host smart-6789e70e-1e3f-4f87-8f6f-c532084e6fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345549524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2345549524
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2403013709
Short name T269
Test name
Test status
Simulation time 255006600 ps
CPU time 5.82 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:16:14 PM PDT 24
Peak memory 210916 kb
Host smart-fe8e31ca-e875-41d3-8cde-04d3d179daff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403013709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2403013709
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3705206668
Short name T143
Test name
Test status
Simulation time 3537975169 ps
CPU time 29.08 seconds
Started Jun 07 06:16:02 PM PDT 24
Finished Jun 07 06:16:31 PM PDT 24
Peak memory 212872 kb
Host smart-73cd0eb5-1377-4da3-8730-ab90b190f5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705206668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3705206668
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1036981943
Short name T194
Test name
Test status
Simulation time 13749869378 ps
CPU time 58.21 seconds
Started Jun 07 06:16:02 PM PDT 24
Finished Jun 07 06:17:01 PM PDT 24
Peak memory 215772 kb
Host smart-ab49dcd1-510b-437f-9340-e57955838d0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036981943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1036981943
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.4042008953
Short name T34
Test name
Test status
Simulation time 3431603138 ps
CPU time 8.76 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:18 PM PDT 24
Peak memory 210792 kb
Host smart-7bf93bb8-e8b6-4c53-8246-53e298f401f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042008953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.4042008953
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4036983209
Short name T37
Test name
Test status
Simulation time 2460400487 ps
CPU time 142.19 seconds
Started Jun 07 06:16:07 PM PDT 24
Finished Jun 07 06:18:30 PM PDT 24
Peak memory 212560 kb
Host smart-83dc8ca6-cb43-4246-9e95-0acdea003a5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036983209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4036983209
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.616257888
Short name T371
Test name
Test status
Simulation time 1381692778 ps
CPU time 13.72 seconds
Started Jun 07 06:16:42 PM PDT 24
Finished Jun 07 06:16:56 PM PDT 24
Peak memory 211692 kb
Host smart-df703566-cf2a-44f8-9e76-5738a57747b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616257888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.616257888
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.625668224
Short name T249
Test name
Test status
Simulation time 98275779 ps
CPU time 5.86 seconds
Started Jun 07 06:16:19 PM PDT 24
Finished Jun 07 06:16:26 PM PDT 24
Peak memory 210916 kb
Host smart-5ce1687d-a772-41e0-8554-a964ebaa7e63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625668224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.625668224
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3564560589
Short name T196
Test name
Test status
Simulation time 183974693 ps
CPU time 10.47 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:17 PM PDT 24
Peak memory 212908 kb
Host smart-bab3a408-c186-43cb-9e09-0a19b37b7576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564560589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3564560589
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.509478232
Short name T301
Test name
Test status
Simulation time 731670843 ps
CPU time 23.13 seconds
Started Jun 07 06:16:30 PM PDT 24
Finished Jun 07 06:16:53 PM PDT 24
Peak memory 214648 kb
Host smart-f957f787-800f-4f7a-91f9-1295aea25853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509478232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.509478232
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3806082323
Short name T267
Test name
Test status
Simulation time 664394942 ps
CPU time 5.57 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:13 PM PDT 24
Peak memory 210712 kb
Host smart-eb1ed5c1-4eae-421b-abba-c8d7c2256ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806082323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3806082323
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2887041330
Short name T185
Test name
Test status
Simulation time 1745565025 ps
CPU time 92.29 seconds
Started Jun 07 06:16:35 PM PDT 24
Finished Jun 07 06:18:08 PM PDT 24
Peak memory 236796 kb
Host smart-a7d94f91-491f-40fd-9296-dbc3dc519eab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887041330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2887041330
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1428738024
Short name T244
Test name
Test status
Simulation time 5238795702 ps
CPU time 18.55 seconds
Started Jun 07 06:16:41 PM PDT 24
Finished Jun 07 06:17:01 PM PDT 24
Peak memory 211884 kb
Host smart-0f062cb5-ceeb-4fd6-b99c-7199971ea407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428738024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1428738024
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4186464188
Short name T287
Test name
Test status
Simulation time 421728188 ps
CPU time 5.56 seconds
Started Jun 07 06:16:43 PM PDT 24
Finished Jun 07 06:16:49 PM PDT 24
Peak memory 210900 kb
Host smart-46c30b39-f969-48b2-8187-cb9b37f82262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186464188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4186464188
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4277853920
Short name T333
Test name
Test status
Simulation time 3775294931 ps
CPU time 20.88 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:16:34 PM PDT 24
Peak memory 212976 kb
Host smart-c01bfa1f-04c0-4f83-a8f3-1b73cc84a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277853920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4277853920
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1653895261
Short name T20
Test name
Test status
Simulation time 35430121267 ps
CPU time 92.22 seconds
Started Jun 07 06:16:03 PM PDT 24
Finished Jun 07 06:17:36 PM PDT 24
Peak memory 218936 kb
Host smart-aa6e0453-45e5-48c5-8e13-b586f7339738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653895261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1653895261
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.70433835
Short name T315
Test name
Test status
Simulation time 24042381504 ps
CPU time 1005.83 seconds
Started Jun 07 06:16:42 PM PDT 24
Finished Jun 07 06:33:29 PM PDT 24
Peak memory 228044 kb
Host smart-8b3a4a0d-4b22-47cd-807e-71b180a0961c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70433835 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.70433835
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.526542081
Short name T87
Test name
Test status
Simulation time 3363564225 ps
CPU time 8.26 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:16:14 PM PDT 24
Peak memory 210692 kb
Host smart-bf232a8c-e184-49a1-88eb-e3dc5e5e9218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526542081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.526542081
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.162164098
Short name T259
Test name
Test status
Simulation time 15705732868 ps
CPU time 145.53 seconds
Started Jun 07 06:16:03 PM PDT 24
Finished Jun 07 06:18:29 PM PDT 24
Peak memory 225368 kb
Host smart-7a177f52-9190-45be-9a78-671e72f6d3e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162164098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.162164098
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1325549020
Short name T192
Test name
Test status
Simulation time 50402572062 ps
CPU time 29.28 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:37 PM PDT 24
Peak memory 211800 kb
Host smart-49f1704b-9dd4-497a-a55c-b56ab31bfa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325549020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1325549020
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.820155689
Short name T219
Test name
Test status
Simulation time 362024177 ps
CPU time 6.49 seconds
Started Jun 07 06:16:03 PM PDT 24
Finished Jun 07 06:16:10 PM PDT 24
Peak memory 210972 kb
Host smart-e771094e-c971-4bab-9f43-ea820bc3dc92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820155689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.820155689
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2650377346
Short name T374
Test name
Test status
Simulation time 12431676868 ps
CPU time 35.77 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:46 PM PDT 24
Peak memory 213684 kb
Host smart-7fc963e1-3e9d-4ee5-b15c-0d85eca1c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650377346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2650377346
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1238978567
Short name T327
Test name
Test status
Simulation time 11959460801 ps
CPU time 29.28 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:40 PM PDT 24
Peak memory 214676 kb
Host smart-0a2d38eb-00ee-4db1-87fa-aa5bbe71a964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238978567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1238978567
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2234658167
Short name T199
Test name
Test status
Simulation time 3408322545 ps
CPU time 9.64 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:16:21 PM PDT 24
Peak memory 210788 kb
Host smart-c17f79ac-12ed-489c-a070-f3d9159f2151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234658167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2234658167
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3679666114
Short name T271
Test name
Test status
Simulation time 17337049072 ps
CPU time 220.1 seconds
Started Jun 07 06:16:10 PM PDT 24
Finished Jun 07 06:19:51 PM PDT 24
Peak memory 228128 kb
Host smart-50ae4ca2-866a-4f3c-9525-a52fc02cc6b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679666114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3679666114
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.527774294
Short name T204
Test name
Test status
Simulation time 10783388691 ps
CPU time 24.37 seconds
Started Jun 07 06:16:11 PM PDT 24
Finished Jun 07 06:16:36 PM PDT 24
Peak memory 211928 kb
Host smart-41fbdfe2-3df8-4a3c-a158-284a05ba04d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527774294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.527774294
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.947996424
Short name T56
Test name
Test status
Simulation time 1202351228 ps
CPU time 9.6 seconds
Started Jun 07 06:16:43 PM PDT 24
Finished Jun 07 06:16:53 PM PDT 24
Peak memory 210964 kb
Host smart-d0539de2-7b49-4904-a609-b91c10a4f401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947996424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.947996424
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2725007745
Short name T281
Test name
Test status
Simulation time 738293150 ps
CPU time 9.86 seconds
Started Jun 07 06:16:22 PM PDT 24
Finished Jun 07 06:16:32 PM PDT 24
Peak memory 213080 kb
Host smart-52bd51fb-b9a1-4fe1-a34b-afdde089be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725007745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2725007745
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3953802584
Short name T5
Test name
Test status
Simulation time 11141664496 ps
CPU time 101.39 seconds
Started Jun 07 06:16:12 PM PDT 24
Finished Jun 07 06:17:54 PM PDT 24
Peak memory 219012 kb
Host smart-3ee235f0-e698-4036-a6ee-fc6f338da051
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953802584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3953802584
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1235009882
Short name T302
Test name
Test status
Simulation time 3529182588 ps
CPU time 7.53 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:16:17 PM PDT 24
Peak memory 210784 kb
Host smart-07a5ea5c-9757-40f0-80b4-1e10a615d3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235009882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1235009882
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.814382899
Short name T33
Test name
Test status
Simulation time 6456695408 ps
CPU time 120 seconds
Started Jun 07 06:16:15 PM PDT 24
Finished Jun 07 06:18:15 PM PDT 24
Peak memory 212160 kb
Host smart-82043291-2afc-4a8f-a3bd-cc727fec765c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814382899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.814382899
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1422630738
Short name T200
Test name
Test status
Simulation time 65294555259 ps
CPU time 31.43 seconds
Started Jun 07 06:16:08 PM PDT 24
Finished Jun 07 06:16:41 PM PDT 24
Peak memory 212128 kb
Host smart-3bcca975-5f46-4f7a-a652-800990e399d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422630738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1422630738
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2499273151
Short name T178
Test name
Test status
Simulation time 178457669 ps
CPU time 6.85 seconds
Started Jun 07 06:16:05 PM PDT 24
Finished Jun 07 06:16:13 PM PDT 24
Peak memory 210912 kb
Host smart-1853e9c7-083a-4b46-8494-e6c4d8e2fd16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499273151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2499273151
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1992468190
Short name T323
Test name
Test status
Simulation time 5213181079 ps
CPU time 34.27 seconds
Started Jun 07 06:16:06 PM PDT 24
Finished Jun 07 06:16:41 PM PDT 24
Peak memory 213552 kb
Host smart-ce76ad25-800d-47e6-b4f3-b434d66771e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992468190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1992468190
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2062944935
Short name T246
Test name
Test status
Simulation time 10190218187 ps
CPU time 89.84 seconds
Started Jun 07 06:16:22 PM PDT 24
Finished Jun 07 06:17:52 PM PDT 24
Peak memory 216220 kb
Host smart-d2aaef47-836f-4384-89d1-092e3b329cac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062944935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2062944935
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2518336767
Short name T50
Test name
Test status
Simulation time 122185275287 ps
CPU time 1239.4 seconds
Started Jun 07 06:16:09 PM PDT 24
Finished Jun 07 06:36:50 PM PDT 24
Peak memory 235552 kb
Host smart-73c9def1-7840-4bec-b194-8c6b0b7cbbf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518336767 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2518336767
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.561036757
Short name T283
Test name
Test status
Simulation time 1386957477 ps
CPU time 12.94 seconds
Started Jun 07 06:15:24 PM PDT 24
Finished Jun 07 06:15:37 PM PDT 24
Peak memory 210648 kb
Host smart-a7212061-1350-44a6-bec5-cf1b298a1ea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561036757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.561036757
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.845472701
Short name T350
Test name
Test status
Simulation time 48139218709 ps
CPU time 124.32 seconds
Started Jun 07 06:15:37 PM PDT 24
Finished Jun 07 06:17:42 PM PDT 24
Peak memory 228280 kb
Host smart-a17f7ba6-398a-44cb-8c45-c54c4bb45afd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845472701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.845472701
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2007499814
Short name T141
Test name
Test status
Simulation time 8751400376 ps
CPU time 25.9 seconds
Started Jun 07 06:15:54 PM PDT 24
Finished Jun 07 06:16:20 PM PDT 24
Peak memory 211816 kb
Host smart-a60bfd83-297d-4972-ad8c-21aee2d66b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007499814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2007499814
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3927444266
Short name T241
Test name
Test status
Simulation time 102410019 ps
CPU time 5.99 seconds
Started Jun 07 06:15:30 PM PDT 24
Finished Jun 07 06:15:36 PM PDT 24
Peak memory 210880 kb
Host smart-dd751a73-c816-4f3a-b151-eaa29aec183a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927444266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3927444266
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2717441518
Short name T361
Test name
Test status
Simulation time 2569705608 ps
CPU time 15.35 seconds
Started Jun 07 06:15:40 PM PDT 24
Finished Jun 07 06:16:01 PM PDT 24
Peak memory 213164 kb
Host smart-af035beb-1780-4ab8-ae53-c756f611c1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717441518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2717441518
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1161760741
Short name T265
Test name
Test status
Simulation time 19828299868 ps
CPU time 28.68 seconds
Started Jun 07 06:15:26 PM PDT 24
Finished Jun 07 06:15:55 PM PDT 24
Peak memory 214036 kb
Host smart-5d406f0b-a7b2-4595-b21c-02695ec9ce52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161760741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1161760741
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2008659606
Short name T344
Test name
Test status
Simulation time 79195007314 ps
CPU time 5949.94 seconds
Started Jun 07 06:15:46 PM PDT 24
Finished Jun 07 07:54:57 PM PDT 24
Peak memory 231084 kb
Host smart-f27b9b2f-8681-4c6b-b66b-05876de58ba7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008659606 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2008659606
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1868275437
Short name T237
Test name
Test status
Simulation time 690730650 ps
CPU time 4.26 seconds
Started Jun 07 06:15:38 PM PDT 24
Finished Jun 07 06:15:43 PM PDT 24
Peak memory 210680 kb
Host smart-1129838a-e7d8-41a8-b42c-84350c3be526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868275437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1868275437
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3829134292
Short name T3
Test name
Test status
Simulation time 28527079632 ps
CPU time 333.51 seconds
Started Jun 07 06:15:20 PM PDT 24
Finished Jun 07 06:20:59 PM PDT 24
Peak memory 225204 kb
Host smart-02b654bb-2083-4859-8e5e-eb169c0311d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829134292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3829134292
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2407880380
Short name T208
Test name
Test status
Simulation time 168716691 ps
CPU time 9.68 seconds
Started Jun 07 06:15:58 PM PDT 24
Finished Jun 07 06:16:08 PM PDT 24
Peak memory 211832 kb
Host smart-0aacfc21-79ff-4b7c-a51c-a780d78c5b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407880380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2407880380
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3710985559
Short name T151
Test name
Test status
Simulation time 1102297118 ps
CPU time 6.22 seconds
Started Jun 07 06:15:42 PM PDT 24
Finished Jun 07 06:15:48 PM PDT 24
Peak memory 210848 kb
Host smart-a5557f40-6c3d-42de-9de5-b775be91a7e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710985559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3710985559
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2338407742
Short name T375
Test name
Test status
Simulation time 2978911054 ps
CPU time 18.95 seconds
Started Jun 07 06:15:57 PM PDT 24
Finished Jun 07 06:16:16 PM PDT 24
Peak memory 212956 kb
Host smart-9f6b2564-3ec2-4fd0-8252-8448857ea28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338407742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2338407742
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2598780126
Short name T305
Test name
Test status
Simulation time 891024556 ps
CPU time 8.85 seconds
Started Jun 07 06:15:52 PM PDT 24
Finished Jun 07 06:16:01 PM PDT 24
Peak memory 210688 kb
Host smart-80db2c92-f8a9-443a-a34a-1b9bcd9c6ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598780126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2598780126
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.889088250
Short name T251
Test name
Test status
Simulation time 56318953424 ps
CPU time 1773.36 seconds
Started Jun 07 06:15:55 PM PDT 24
Finished Jun 07 06:45:29 PM PDT 24
Peak memory 235496 kb
Host smart-43129cc3-d49f-4861-8e65-1dbfd302788a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889088250 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.889088250
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3583262718
Short name T65
Test name
Test status
Simulation time 1467600252 ps
CPU time 14.04 seconds
Started Jun 07 06:15:52 PM PDT 24
Finished Jun 07 06:16:06 PM PDT 24
Peak memory 210580 kb
Host smart-b7bd4296-7512-4e5a-b2c8-55677649f9b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583262718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3583262718
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4022027100
Short name T330
Test name
Test status
Simulation time 341141044 ps
CPU time 9.28 seconds
Started Jun 07 06:15:19 PM PDT 24
Finished Jun 07 06:15:28 PM PDT 24
Peak memory 211572 kb
Host smart-6944526f-4ab9-4f8e-8ce7-da18e284365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022027100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4022027100
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.988797561
Short name T248
Test name
Test status
Simulation time 111408724 ps
CPU time 5.83 seconds
Started Jun 07 06:15:51 PM PDT 24
Finished Jun 07 06:15:57 PM PDT 24
Peak memory 210728 kb
Host smart-942e69c1-c8fd-48f7-bbe4-6d4f5d094b4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988797561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.988797561
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2451239167
Short name T7
Test name
Test status
Simulation time 3884034006 ps
CPU time 37.66 seconds
Started Jun 07 06:15:24 PM PDT 24
Finished Jun 07 06:16:02 PM PDT 24
Peak memory 212712 kb
Host smart-8f358227-352d-42fb-bfbb-09024c09aebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451239167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2451239167
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1569480128
Short name T360
Test name
Test status
Simulation time 5442515598 ps
CPU time 64.53 seconds
Started Jun 07 06:15:18 PM PDT 24
Finished Jun 07 06:16:23 PM PDT 24
Peak memory 219064 kb
Host smart-3ef44bf4-1f88-4591-82fe-bbdfe62bf83f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569480128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1569480128
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3218210837
Short name T172
Test name
Test status
Simulation time 7578307812 ps
CPU time 15.83 seconds
Started Jun 07 06:15:39 PM PDT 24
Finished Jun 07 06:15:55 PM PDT 24
Peak memory 210836 kb
Host smart-189dd487-0517-4559-9f57-9f11d0dc313f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218210837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3218210837
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3669656403
Short name T358
Test name
Test status
Simulation time 3883395413 ps
CPU time 60.93 seconds
Started Jun 07 06:15:26 PM PDT 24
Finished Jun 07 06:16:27 PM PDT 24
Peak memory 227040 kb
Host smart-0614df77-e556-4cb2-9bf8-b345d055d632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669656403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3669656403
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2948228575
Short name T40
Test name
Test status
Simulation time 2369202227 ps
CPU time 9.61 seconds
Started Jun 07 06:15:48 PM PDT 24
Finished Jun 07 06:15:58 PM PDT 24
Peak memory 211600 kb
Host smart-05a716c6-0bda-4b81-b448-ff416dd5182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948228575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2948228575
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.383864828
Short name T144
Test name
Test status
Simulation time 6437451388 ps
CPU time 15.58 seconds
Started Jun 07 06:15:31 PM PDT 24
Finished Jun 07 06:15:47 PM PDT 24
Peak memory 211036 kb
Host smart-5c8711d1-6da4-4f17-a915-786aebbac3db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383864828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.383864828
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2546477688
Short name T232
Test name
Test status
Simulation time 7729211182 ps
CPU time 40.31 seconds
Started Jun 07 06:16:02 PM PDT 24
Finished Jun 07 06:16:42 PM PDT 24
Peak memory 213092 kb
Host smart-8313c728-db66-4b5e-96a3-bf859796fe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546477688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2546477688
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2691796335
Short name T270
Test name
Test status
Simulation time 102930352771 ps
CPU time 85.21 seconds
Started Jun 07 06:15:34 PM PDT 24
Finished Jun 07 06:17:00 PM PDT 24
Peak memory 219008 kb
Host smart-a90a3bfe-635a-4245-8d57-97f803d0e89d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691796335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2691796335
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2033746935
Short name T26
Test name
Test status
Simulation time 1118047302 ps
CPU time 7.95 seconds
Started Jun 07 06:15:47 PM PDT 24
Finished Jun 07 06:15:55 PM PDT 24
Peak memory 210740 kb
Host smart-c4d30345-106c-44e0-b5a7-717ac81b368f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033746935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2033746935
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2741634212
Short name T322
Test name
Test status
Simulation time 2145188284 ps
CPU time 69.59 seconds
Started Jun 07 06:15:50 PM PDT 24
Finished Jun 07 06:17:00 PM PDT 24
Peak memory 226080 kb
Host smart-48d775b4-dcd7-4734-ba13-f981b065da2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741634212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2741634212
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3163857943
Short name T101
Test name
Test status
Simulation time 386910298 ps
CPU time 5.68 seconds
Started Jun 07 06:15:19 PM PDT 24
Finished Jun 07 06:15:25 PM PDT 24
Peak memory 210732 kb
Host smart-b670beac-66f1-4435-b01b-b0c1778c9847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163857943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3163857943
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3892437318
Short name T169
Test name
Test status
Simulation time 727318863 ps
CPU time 10.06 seconds
Started Jun 07 06:15:39 PM PDT 24
Finished Jun 07 06:15:50 PM PDT 24
Peak memory 213720 kb
Host smart-266c504b-bd28-4ee6-a48a-bc43bcb00632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892437318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3892437318
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.246379793
Short name T132
Test name
Test status
Simulation time 11122325633 ps
CPU time 102.6 seconds
Started Jun 07 06:15:23 PM PDT 24
Finished Jun 07 06:17:06 PM PDT 24
Peak memory 218952 kb
Host smart-a41afbc9-97e0-4df6-aa18-706590b0f5af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246379793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.246379793
Directory /workspace/9.rom_ctrl_stress_all/latest
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