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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.72 100.00 98.28 97.45 98.37


Total test records in report: 469
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T292 /workspace/coverage/default/3.rom_ctrl_alert_test.3207060820 Jun 09 12:28:22 PM PDT 24 Jun 09 12:28:31 PM PDT 24 3640626859 ps
T293 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1074966965 Jun 09 12:27:59 PM PDT 24 Jun 09 12:28:11 PM PDT 24 3881580124 ps
T294 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1534864001 Jun 09 12:28:03 PM PDT 24 Jun 09 12:28:16 PM PDT 24 997537980 ps
T295 /workspace/coverage/default/11.rom_ctrl_stress_all.2079355402 Jun 09 12:28:02 PM PDT 24 Jun 09 12:29:21 PM PDT 24 6437949869 ps
T296 /workspace/coverage/default/47.rom_ctrl_smoke.2569758 Jun 09 12:28:03 PM PDT 24 Jun 09 12:28:35 PM PDT 24 6155423413 ps
T23 /workspace/coverage/default/0.rom_ctrl_sec_cm.343252056 Jun 09 12:27:53 PM PDT 24 Jun 09 12:28:46 PM PDT 24 274399906 ps
T297 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2559446684 Jun 09 12:28:03 PM PDT 24 Jun 09 12:28:10 PM PDT 24 838575284 ps
T298 /workspace/coverage/default/38.rom_ctrl_smoke.265766635 Jun 09 12:27:57 PM PDT 24 Jun 09 12:28:19 PM PDT 24 9542076369 ps
T299 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3320021021 Jun 09 12:28:31 PM PDT 24 Jun 09 12:28:55 PM PDT 24 21365543605 ps
T300 /workspace/coverage/default/12.rom_ctrl_smoke.3121137411 Jun 09 12:27:58 PM PDT 24 Jun 09 12:28:24 PM PDT 24 11259516537 ps
T301 /workspace/coverage/default/21.rom_ctrl_alert_test.1793984221 Jun 09 12:28:24 PM PDT 24 Jun 09 12:28:37 PM PDT 24 5547823535 ps
T24 /workspace/coverage/default/1.rom_ctrl_sec_cm.3636470125 Jun 09 12:27:52 PM PDT 24 Jun 09 12:28:50 PM PDT 24 2740070395 ps
T302 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1791715166 Jun 09 12:28:05 PM PDT 24 Jun 09 12:28:18 PM PDT 24 2467352104 ps
T303 /workspace/coverage/default/28.rom_ctrl_smoke.1731365221 Jun 09 12:28:34 PM PDT 24 Jun 09 12:28:45 PM PDT 24 856070899 ps
T304 /workspace/coverage/default/43.rom_ctrl_stress_all.1848698319 Jun 09 12:28:09 PM PDT 24 Jun 09 12:28:19 PM PDT 24 106788397 ps
T305 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4045091133 Jun 09 12:28:01 PM PDT 24 Jun 09 12:30:24 PM PDT 24 8613154550 ps
T306 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3719253502 Jun 09 12:27:59 PM PDT 24 Jun 09 12:29:30 PM PDT 24 2447532443 ps
T307 /workspace/coverage/default/24.rom_ctrl_stress_all.3853251059 Jun 09 12:27:58 PM PDT 24 Jun 09 12:29:39 PM PDT 24 42034317679 ps
T308 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2920941780 Jun 09 12:28:23 PM PDT 24 Jun 09 12:28:37 PM PDT 24 489928232 ps
T309 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.709112017 Jun 09 12:27:57 PM PDT 24 Jun 09 12:34:11 PM PDT 24 34680915571 ps
T310 /workspace/coverage/default/34.rom_ctrl_stress_all.235714764 Jun 09 12:28:08 PM PDT 24 Jun 09 12:28:50 PM PDT 24 770012707 ps
T311 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3378267782 Jun 09 12:28:03 PM PDT 24 Jun 09 01:51:52 PM PDT 24 41407012268 ps
T312 /workspace/coverage/default/35.rom_ctrl_stress_all.2088588548 Jun 09 12:28:04 PM PDT 24 Jun 09 12:29:03 PM PDT 24 25346805881 ps
T313 /workspace/coverage/default/41.rom_ctrl_stress_all.2397125010 Jun 09 12:28:10 PM PDT 24 Jun 09 12:28:39 PM PDT 24 1268609655 ps
T314 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3093338839 Jun 09 12:28:02 PM PDT 24 Jun 09 12:28:13 PM PDT 24 340745641 ps
T315 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2376486148 Jun 09 12:28:34 PM PDT 24 Jun 09 12:28:44 PM PDT 24 466201486 ps
T316 /workspace/coverage/default/19.rom_ctrl_stress_all.4253118497 Jun 09 12:27:57 PM PDT 24 Jun 09 12:28:18 PM PDT 24 555504411 ps
T317 /workspace/coverage/default/22.rom_ctrl_alert_test.623236047 Jun 09 12:27:58 PM PDT 24 Jun 09 12:28:14 PM PDT 24 9501409115 ps
T318 /workspace/coverage/default/10.rom_ctrl_smoke.3978908421 Jun 09 12:27:56 PM PDT 24 Jun 09 12:28:31 PM PDT 24 65276184800 ps
T319 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4140959054 Jun 09 12:27:52 PM PDT 24 Jun 09 12:29:47 PM PDT 24 59843573870 ps
T320 /workspace/coverage/default/27.rom_ctrl_stress_all.3630064204 Jun 09 12:28:03 PM PDT 24 Jun 09 12:28:22 PM PDT 24 3377925079 ps
T321 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.255033038 Jun 09 12:28:02 PM PDT 24 Jun 09 12:28:11 PM PDT 24 872204975 ps
T322 /workspace/coverage/default/9.rom_ctrl_stress_all.4121382688 Jun 09 12:27:54 PM PDT 24 Jun 09 12:28:41 PM PDT 24 7299922759 ps
T323 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.222570189 Jun 09 12:29:01 PM PDT 24 Jun 09 12:29:11 PM PDT 24 664714492 ps
T324 /workspace/coverage/default/35.rom_ctrl_alert_test.3627670524 Jun 09 12:28:36 PM PDT 24 Jun 09 12:28:55 PM PDT 24 7964530326 ps
T325 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1383009725 Jun 09 12:28:03 PM PDT 24 Jun 09 12:28:15 PM PDT 24 6588297269 ps
T326 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2418788291 Jun 09 12:29:01 PM PDT 24 Jun 09 01:14:30 PM PDT 24 156711209122 ps
T327 /workspace/coverage/default/18.rom_ctrl_stress_all.2055457061 Jun 09 12:28:00 PM PDT 24 Jun 09 12:28:22 PM PDT 24 1698115849 ps
T328 /workspace/coverage/default/11.rom_ctrl_smoke.4247978274 Jun 09 12:27:55 PM PDT 24 Jun 09 12:28:24 PM PDT 24 23302503460 ps
T329 /workspace/coverage/default/2.rom_ctrl_stress_all.2264452126 Jun 09 12:27:49 PM PDT 24 Jun 09 12:28:16 PM PDT 24 1322413764 ps
T330 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.920970877 Jun 09 12:28:00 PM PDT 24 Jun 09 12:30:18 PM PDT 24 9332985176 ps
T331 /workspace/coverage/default/43.rom_ctrl_smoke.591525502 Jun 09 12:28:24 PM PDT 24 Jun 09 12:28:47 PM PDT 24 1939438788 ps
T332 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4147746961 Jun 09 12:27:49 PM PDT 24 Jun 09 12:28:24 PM PDT 24 18636454084 ps
T333 /workspace/coverage/default/21.rom_ctrl_smoke.3269112978 Jun 09 12:28:01 PM PDT 24 Jun 09 12:28:17 PM PDT 24 1399833736 ps
T334 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4038108059 Jun 09 12:27:58 PM PDT 24 Jun 09 12:45:22 PM PDT 24 109455272018 ps
T335 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3843988857 Jun 09 12:27:59 PM PDT 24 Jun 09 12:28:09 PM PDT 24 664987198 ps
T336 /workspace/coverage/default/35.rom_ctrl_smoke.2432271485 Jun 09 12:28:09 PM PDT 24 Jun 09 12:28:34 PM PDT 24 4720447360 ps
T337 /workspace/coverage/default/24.rom_ctrl_alert_test.3788063291 Jun 09 12:28:19 PM PDT 24 Jun 09 12:28:37 PM PDT 24 6117697448 ps
T338 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.469649213 Jun 09 12:28:27 PM PDT 24 Jun 09 12:32:39 PM PDT 24 41366988264 ps
T339 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.277936734 Jun 09 12:28:03 PM PDT 24 Jun 09 12:28:40 PM PDT 24 7346528690 ps
T340 /workspace/coverage/default/20.rom_ctrl_stress_all.2705325647 Jun 09 12:28:03 PM PDT 24 Jun 09 12:28:32 PM PDT 24 554039945 ps
T341 /workspace/coverage/default/40.rom_ctrl_stress_all.696345553 Jun 09 12:28:02 PM PDT 24 Jun 09 12:29:05 PM PDT 24 5091942275 ps
T342 /workspace/coverage/default/34.rom_ctrl_smoke.893202180 Jun 09 12:28:02 PM PDT 24 Jun 09 12:28:34 PM PDT 24 2642381546 ps
T343 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.484840440 Jun 09 12:27:58 PM PDT 24 Jun 09 12:28:32 PM PDT 24 8782067495 ps
T344 /workspace/coverage/default/0.rom_ctrl_smoke.2947328933 Jun 09 12:28:12 PM PDT 24 Jun 09 12:28:22 PM PDT 24 423346857 ps
T345 /workspace/coverage/default/16.rom_ctrl_alert_test.4219495457 Jun 09 12:27:51 PM PDT 24 Jun 09 12:28:08 PM PDT 24 8936049314 ps
T346 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.94418384 Jun 09 12:28:18 PM PDT 24 Jun 09 12:33:26 PM PDT 24 93613929623 ps
T347 /workspace/coverage/default/21.rom_ctrl_stress_all.925346705 Jun 09 12:28:24 PM PDT 24 Jun 09 12:28:46 PM PDT 24 752073694 ps
T348 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2891066249 Jun 09 12:28:09 PM PDT 24 Jun 09 12:31:37 PM PDT 24 194359881873 ps
T349 /workspace/coverage/default/4.rom_ctrl_alert_test.2701855894 Jun 09 12:27:57 PM PDT 24 Jun 09 12:28:08 PM PDT 24 4440711584 ps
T350 /workspace/coverage/default/48.rom_ctrl_smoke.504469717 Jun 09 12:28:18 PM PDT 24 Jun 09 12:28:29 PM PDT 24 733573012 ps
T351 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2237523444 Jun 09 12:28:15 PM PDT 24 Jun 09 12:28:27 PM PDT 24 4149730765 ps
T352 /workspace/coverage/default/5.rom_ctrl_smoke.672367055 Jun 09 12:27:53 PM PDT 24 Jun 09 12:28:04 PM PDT 24 357713076 ps
T353 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2500811742 Jun 09 12:28:03 PM PDT 24 Jun 09 12:28:14 PM PDT 24 171808848 ps
T354 /workspace/coverage/default/4.rom_ctrl_smoke.2372033180 Jun 09 12:28:05 PM PDT 24 Jun 09 12:28:32 PM PDT 24 9922672313 ps
T355 /workspace/coverage/default/22.rom_ctrl_stress_all.22699597 Jun 09 12:28:01 PM PDT 24 Jun 09 12:28:29 PM PDT 24 9993121046 ps
T356 /workspace/coverage/default/17.rom_ctrl_alert_test.4206622653 Jun 09 12:28:02 PM PDT 24 Jun 09 12:28:15 PM PDT 24 4834667908 ps
T357 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3175259057 Jun 09 12:27:59 PM PDT 24 Jun 09 12:29:51 PM PDT 24 14246471955 ps
T358 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2145874403 Jun 09 12:28:03 PM PDT 24 Jun 09 12:29:10 PM PDT 24 2257103525 ps
T359 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1253024599 Jun 09 12:28:27 PM PDT 24 Jun 09 12:29:01 PM PDT 24 3980404253 ps
T360 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.163017318 Jun 09 12:28:01 PM PDT 24 Jun 09 12:28:33 PM PDT 24 14046233635 ps
T361 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3263938900 Jun 09 12:27:53 PM PDT 24 Jun 09 12:31:59 PM PDT 24 27253865707 ps
T362 /workspace/coverage/default/45.rom_ctrl_alert_test.3632935507 Jun 09 12:28:30 PM PDT 24 Jun 09 12:28:47 PM PDT 24 2093049945 ps
T363 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2088670507 Jun 09 12:28:00 PM PDT 24 Jun 09 12:33:43 PM PDT 24 33356775239 ps
T54 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3674170087 Jun 09 12:24:08 PM PDT 24 Jun 09 12:24:28 PM PDT 24 364489487 ps
T55 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.992047278 Jun 09 12:24:09 PM PDT 24 Jun 09 12:24:20 PM PDT 24 4821038284 ps
T56 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1455878238 Jun 09 12:23:47 PM PDT 24 Jun 09 12:24:04 PM PDT 24 4150483403 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1466592720 Jun 09 12:23:56 PM PDT 24 Jun 09 12:24:04 PM PDT 24 768384394 ps
T93 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2609693912 Jun 09 12:24:20 PM PDT 24 Jun 09 12:24:32 PM PDT 24 6793968901 ps
T59 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.434527595 Jun 09 12:23:54 PM PDT 24 Jun 09 12:25:03 PM PDT 24 14321670555 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1975717602 Jun 09 12:23:48 PM PDT 24 Jun 09 12:24:01 PM PDT 24 4193176161 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.267615175 Jun 09 12:24:04 PM PDT 24 Jun 09 12:24:15 PM PDT 24 2943624765 ps
T60 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3383425167 Jun 09 12:23:58 PM PDT 24 Jun 09 12:24:07 PM PDT 24 945526887 ps
T61 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1271846747 Jun 09 12:24:21 PM PDT 24 Jun 09 12:25:26 PM PDT 24 20668409177 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3057356936 Jun 09 12:24:04 PM PDT 24 Jun 09 12:24:17 PM PDT 24 1528512250 ps
T366 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2299824536 Jun 09 12:23:58 PM PDT 24 Jun 09 12:24:15 PM PDT 24 38094527037 ps
T51 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3822465432 Jun 09 12:24:18 PM PDT 24 Jun 09 12:25:34 PM PDT 24 2778570895 ps
T367 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2294925619 Jun 09 12:24:21 PM PDT 24 Jun 09 12:24:33 PM PDT 24 5153172557 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2515448297 Jun 09 12:23:48 PM PDT 24 Jun 09 12:24:04 PM PDT 24 4069428343 ps
T52 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2860377132 Jun 09 12:24:03 PM PDT 24 Jun 09 12:25:12 PM PDT 24 2636126387 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2254350541 Jun 09 12:24:16 PM PDT 24 Jun 09 12:24:29 PM PDT 24 5056968962 ps
T63 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1486440041 Jun 09 12:24:34 PM PDT 24 Jun 09 12:24:43 PM PDT 24 2919450099 ps
T94 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1065491855 Jun 09 12:24:07 PM PDT 24 Jun 09 12:24:25 PM PDT 24 2134699233 ps
T53 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2873848463 Jun 09 12:24:11 PM PDT 24 Jun 09 12:25:21 PM PDT 24 1273383921 ps
T64 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4072423209 Jun 09 12:23:58 PM PDT 24 Jun 09 12:24:12 PM PDT 24 2304134136 ps
T369 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4221823578 Jun 09 12:24:08 PM PDT 24 Jun 09 12:24:26 PM PDT 24 1489300642 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3479807822 Jun 09 12:23:48 PM PDT 24 Jun 09 12:24:03 PM PDT 24 1422252163 ps
T370 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2331862250 Jun 09 12:23:58 PM PDT 24 Jun 09 12:24:03 PM PDT 24 329617501 ps
T65 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.810859482 Jun 09 12:23:47 PM PDT 24 Jun 09 12:24:49 PM PDT 24 7406156852 ps
T66 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.809333245 Jun 09 12:23:44 PM PDT 24 Jun 09 12:23:59 PM PDT 24 1884540689 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1690378623 Jun 09 12:23:44 PM PDT 24 Jun 09 12:23:56 PM PDT 24 1128909854 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2759987039 Jun 09 12:24:02 PM PDT 24 Jun 09 12:24:08 PM PDT 24 87385296 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.247502353 Jun 09 12:24:03 PM PDT 24 Jun 09 12:25:14 PM PDT 24 751349172 ps
T113 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2890064316 Jun 09 12:23:59 PM PDT 24 Jun 09 12:25:08 PM PDT 24 3050343097 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2044365386 Jun 09 12:23:54 PM PDT 24 Jun 09 12:24:32 PM PDT 24 284691309 ps
T373 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2977300179 Jun 09 12:24:17 PM PDT 24 Jun 09 12:24:33 PM PDT 24 7933536544 ps
T67 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.895498436 Jun 09 12:24:33 PM PDT 24 Jun 09 12:24:51 PM PDT 24 7716598041 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3056592531 Jun 09 12:23:56 PM PDT 24 Jun 09 12:24:05 PM PDT 24 3155394795 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1628853562 Jun 09 12:24:03 PM PDT 24 Jun 09 12:24:12 PM PDT 24 743323944 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1088862865 Jun 09 12:23:49 PM PDT 24 Jun 09 12:24:05 PM PDT 24 1821796069 ps
T107 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3107209476 Jun 09 12:24:08 PM PDT 24 Jun 09 12:25:43 PM PDT 24 47502763325 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.96782421 Jun 09 12:24:04 PM PDT 24 Jun 09 12:24:08 PM PDT 24 89122296 ps
T378 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.680121506 Jun 09 12:24:04 PM PDT 24 Jun 09 12:24:37 PM PDT 24 792529036 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2948754956 Jun 09 12:23:55 PM PDT 24 Jun 09 12:24:01 PM PDT 24 498596386 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1570401869 Jun 09 12:23:44 PM PDT 24 Jun 09 12:24:25 PM PDT 24 3915552464 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4245683130 Jun 09 12:24:07 PM PDT 24 Jun 09 12:25:29 PM PDT 24 2722893230 ps
T379 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2527728388 Jun 09 12:24:28 PM PDT 24 Jun 09 12:25:46 PM PDT 24 17607451818 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1793047291 Jun 09 12:24:07 PM PDT 24 Jun 09 12:24:24 PM PDT 24 4197548686 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.778151439 Jun 09 12:23:43 PM PDT 24 Jun 09 12:24:30 PM PDT 24 20008232134 ps
T77 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3657644117 Jun 09 12:24:08 PM PDT 24 Jun 09 12:24:24 PM PDT 24 2078619985 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.392255767 Jun 09 12:23:48 PM PDT 24 Jun 09 12:24:09 PM PDT 24 4284320924 ps
T383 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2447455703 Jun 09 12:24:04 PM PDT 24 Jun 09 12:25:21 PM PDT 24 7786541387 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2545614139 Jun 09 12:24:08 PM PDT 24 Jun 09 12:24:23 PM PDT 24 2078616316 ps
T78 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1139272314 Jun 09 12:23:50 PM PDT 24 Jun 09 12:24:05 PM PDT 24 1872610330 ps
T117 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3153030153 Jun 09 12:23:47 PM PDT 24 Jun 09 12:24:59 PM PDT 24 3400877130 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.821511968 Jun 09 12:23:42 PM PDT 24 Jun 09 12:23:49 PM PDT 24 332548352 ps
T79 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2782413138 Jun 09 12:24:31 PM PDT 24 Jun 09 12:25:56 PM PDT 24 42223007051 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2711763720 Jun 09 12:24:10 PM PDT 24 Jun 09 12:24:21 PM PDT 24 4123203683 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.606789617 Jun 09 12:24:02 PM PDT 24 Jun 09 12:24:18 PM PDT 24 1905170688 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3068029665 Jun 09 12:23:52 PM PDT 24 Jun 09 12:24:05 PM PDT 24 1315246398 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2338613355 Jun 09 12:23:48 PM PDT 24 Jun 09 12:23:53 PM PDT 24 168500038 ps
T390 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3575110535 Jun 09 12:23:59 PM PDT 24 Jun 09 12:24:17 PM PDT 24 8420186795 ps
T391 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1171519339 Jun 09 12:23:53 PM PDT 24 Jun 09 12:24:10 PM PDT 24 2086812540 ps
T392 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.744627527 Jun 09 12:24:10 PM PDT 24 Jun 09 12:24:55 PM PDT 24 10032169352 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2534172703 Jun 09 12:23:44 PM PDT 24 Jun 09 12:24:02 PM PDT 24 1441548801 ps
T394 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3327810166 Jun 09 12:23:57 PM PDT 24 Jun 09 12:24:12 PM PDT 24 1041569597 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1717954097 Jun 09 12:23:45 PM PDT 24 Jun 09 12:23:52 PM PDT 24 2866801350 ps
T396 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1756785820 Jun 09 12:24:02 PM PDT 24 Jun 09 12:24:16 PM PDT 24 891198828 ps
T397 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.182219923 Jun 09 12:24:00 PM PDT 24 Jun 09 12:24:16 PM PDT 24 1814923068 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.47848833 Jun 09 12:23:45 PM PDT 24 Jun 09 12:23:53 PM PDT 24 343485277 ps
T398 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1268362129 Jun 09 12:24:06 PM PDT 24 Jun 09 12:24:19 PM PDT 24 1453062412 ps
T111 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3720948594 Jun 09 12:24:07 PM PDT 24 Jun 09 12:24:48 PM PDT 24 536174525 ps
T399 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1111638896 Jun 09 12:24:11 PM PDT 24 Jun 09 12:24:16 PM PDT 24 355744691 ps
T400 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3737448552 Jun 09 12:23:57 PM PDT 24 Jun 09 12:24:34 PM PDT 24 647096565 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3517919498 Jun 09 12:23:53 PM PDT 24 Jun 09 12:24:11 PM PDT 24 7433778723 ps
T81 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4154866877 Jun 09 12:23:52 PM PDT 24 Jun 09 12:24:11 PM PDT 24 1509915779 ps
T402 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2916766379 Jun 09 12:24:08 PM PDT 24 Jun 09 12:24:16 PM PDT 24 2236871996 ps
T403 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3721328574 Jun 09 12:24:27 PM PDT 24 Jun 09 12:24:41 PM PDT 24 6195995815 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3132160788 Jun 09 12:23:55 PM PDT 24 Jun 09 12:24:03 PM PDT 24 572725987 ps
T405 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1908367045 Jun 09 12:24:10 PM PDT 24 Jun 09 12:24:24 PM PDT 24 2330168872 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3267994381 Jun 09 12:23:44 PM PDT 24 Jun 09 12:24:13 PM PDT 24 3587098559 ps
T114 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1063721402 Jun 09 12:24:12 PM PDT 24 Jun 09 12:25:22 PM PDT 24 1121454829 ps
T112 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3265658024 Jun 09 12:24:09 PM PDT 24 Jun 09 12:25:27 PM PDT 24 3628871411 ps
T406 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1217486982 Jun 09 12:24:08 PM PDT 24 Jun 09 12:24:19 PM PDT 24 307010716 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.987167169 Jun 09 12:23:47 PM PDT 24 Jun 09 12:23:58 PM PDT 24 4236892928 ps
T115 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2786204960 Jun 09 12:23:58 PM PDT 24 Jun 09 12:25:14 PM PDT 24 1662843201 ps
T408 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.699758739 Jun 09 12:24:05 PM PDT 24 Jun 09 12:24:23 PM PDT 24 4255785080 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.750743989 Jun 09 12:24:05 PM PDT 24 Jun 09 12:24:14 PM PDT 24 335278404 ps
T410 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2816516145 Jun 09 12:24:09 PM PDT 24 Jun 09 12:24:28 PM PDT 24 380214883 ps
T411 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1159143986 Jun 09 12:24:00 PM PDT 24 Jun 09 12:24:06 PM PDT 24 89032573 ps
T412 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2420449361 Jun 09 12:23:59 PM PDT 24 Jun 09 12:24:04 PM PDT 24 175311240 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2765495604 Jun 09 12:23:49 PM PDT 24 Jun 09 12:23:58 PM PDT 24 2722024755 ps
T414 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2628192332 Jun 09 12:24:02 PM PDT 24 Jun 09 12:24:06 PM PDT 24 216910146 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4183209248 Jun 09 12:24:06 PM PDT 24 Jun 09 12:24:16 PM PDT 24 733250069 ps
T416 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1152870095 Jun 09 12:24:06 PM PDT 24 Jun 09 12:24:11 PM PDT 24 85580723 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.28229240 Jun 09 12:23:52 PM PDT 24 Jun 09 12:24:02 PM PDT 24 1122526694 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.460600478 Jun 09 12:23:47 PM PDT 24 Jun 09 12:23:58 PM PDT 24 2139332263 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2054435606 Jun 09 12:23:49 PM PDT 24 Jun 09 12:24:07 PM PDT 24 6751819590 ps
T420 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.818949513 Jun 09 12:24:05 PM PDT 24 Jun 09 12:24:15 PM PDT 24 5244568650 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.837939742 Jun 09 12:23:59 PM PDT 24 Jun 09 12:24:44 PM PDT 24 15853460993 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.650270750 Jun 09 12:23:47 PM PDT 24 Jun 09 12:23:58 PM PDT 24 1258111474 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1950244112 Jun 09 12:23:46 PM PDT 24 Jun 09 12:23:52 PM PDT 24 93871355 ps
T424 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2732847620 Jun 09 12:23:58 PM PDT 24 Jun 09 12:24:04 PM PDT 24 100133107 ps
T425 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.974346288 Jun 09 12:24:13 PM PDT 24 Jun 09 12:24:29 PM PDT 24 5971681063 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3363526185 Jun 09 12:24:01 PM PDT 24 Jun 09 12:24:18 PM PDT 24 6056572637 ps
T427 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3296694419 Jun 09 12:23:55 PM PDT 24 Jun 09 12:24:29 PM PDT 24 1606723127 ps
T428 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1516098603 Jun 09 12:23:59 PM PDT 24 Jun 09 12:24:09 PM PDT 24 4120303651 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1865129526 Jun 09 12:23:46 PM PDT 24 Jun 09 12:24:05 PM PDT 24 979943559 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3631729468 Jun 09 12:23:45 PM PDT 24 Jun 09 12:23:58 PM PDT 24 2911152612 ps
T118 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1354494622 Jun 09 12:24:02 PM PDT 24 Jun 09 12:25:20 PM PDT 24 2048136817 ps
T431 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.677632098 Jun 09 12:24:03 PM PDT 24 Jun 09 12:24:12 PM PDT 24 602411923 ps
T432 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2516716932 Jun 09 12:23:45 PM PDT 24 Jun 09 12:24:53 PM PDT 24 3217571718 ps
T433 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1360662714 Jun 09 12:24:08 PM PDT 24 Jun 09 12:24:13 PM PDT 24 88859069 ps
T434 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1755793939 Jun 09 12:24:08 PM PDT 24 Jun 09 12:24:17 PM PDT 24 4349076751 ps
T435 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3543668355 Jun 09 12:24:21 PM PDT 24 Jun 09 12:24:34 PM PDT 24 2720090910 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.770150882 Jun 09 12:23:59 PM PDT 24 Jun 09 12:24:12 PM PDT 24 5784320628 ps
T437 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2837978718 Jun 09 12:24:07 PM PDT 24 Jun 09 12:24:12 PM PDT 24 346555009 ps
T438 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.601533824 Jun 09 12:23:43 PM PDT 24 Jun 09 12:23:58 PM PDT 24 3470196691 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4043255750 Jun 09 12:24:09 PM PDT 24 Jun 09 12:24:21 PM PDT 24 7926753288 ps
T440 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1619989583 Jun 09 12:24:09 PM PDT 24 Jun 09 12:25:28 PM PDT 24 2082002807 ps
T441 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.156048443 Jun 09 12:24:07 PM PDT 24 Jun 09 12:24:22 PM PDT 24 17423437092 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1045922115 Jun 09 12:23:57 PM PDT 24 Jun 09 12:24:04 PM PDT 24 343730035 ps
T443 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2082151694 Jun 09 12:24:11 PM PDT 24 Jun 09 12:25:33 PM PDT 24 40651011757 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1349391175 Jun 09 12:23:42 PM PDT 24 Jun 09 12:23:57 PM PDT 24 3572552565 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1527327763 Jun 09 12:23:54 PM PDT 24 Jun 09 12:24:02 PM PDT 24 692901578 ps
T446 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1461596889 Jun 09 12:23:55 PM PDT 24 Jun 09 12:24:04 PM PDT 24 2445229487 ps
T447 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4229108071 Jun 09 12:24:03 PM PDT 24 Jun 09 12:24:19 PM PDT 24 7996152151 ps
T448 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1307833250 Jun 09 12:24:30 PM PDT 24 Jun 09 12:24:38 PM PDT 24 520702343 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3235337551 Jun 09 12:23:44 PM PDT 24 Jun 09 12:23:56 PM PDT 24 959811670 ps
T450 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4003227007 Jun 09 12:24:08 PM PDT 24 Jun 09 12:24:13 PM PDT 24 321113864 ps
T451 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1615732297 Jun 09 12:23:58 PM PDT 24 Jun 09 12:24:43 PM PDT 24 4326422882 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3107494607 Jun 09 12:24:02 PM PDT 24 Jun 09 12:24:21 PM PDT 24 767374220 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.214823980 Jun 09 12:24:12 PM PDT 24 Jun 09 12:24:26 PM PDT 24 21203851953 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4017258486 Jun 09 12:23:58 PM PDT 24 Jun 09 12:24:20 PM PDT 24 4114782000 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3535170757 Jun 09 12:24:00 PM PDT 24 Jun 09 12:24:06 PM PDT 24 1385004923 ps
T456 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4138418445 Jun 09 12:23:51 PM PDT 24 Jun 09 12:24:08 PM PDT 24 6295927259 ps
T457 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.27770926 Jun 09 12:23:52 PM PDT 24 Jun 09 12:24:13 PM PDT 24 2161493817 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3098537262 Jun 09 12:23:44 PM PDT 24 Jun 09 12:23:57 PM PDT 24 5420940162 ps
T459 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1976121751 Jun 09 12:23:51 PM PDT 24 Jun 09 12:24:03 PM PDT 24 4460472469 ps
T460 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2517793074 Jun 09 12:24:06 PM PDT 24 Jun 09 12:24:20 PM PDT 24 5946225581 ps
T461 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3954592535 Jun 09 12:24:10 PM PDT 24 Jun 09 12:24:29 PM PDT 24 2010090652 ps
T462 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1602050689 Jun 09 12:24:11 PM PDT 24 Jun 09 12:24:25 PM PDT 24 1464777281 ps
T463 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.17187971 Jun 09 12:23:53 PM PDT 24 Jun 09 12:24:12 PM PDT 24 1496441388 ps
T464 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2129249625 Jun 09 12:24:05 PM PDT 24 Jun 09 12:24:52 PM PDT 24 19849195715 ps
T465 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1418912987 Jun 09 12:23:59 PM PDT 24 Jun 09 12:24:09 PM PDT 24 3021545363 ps
T466 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1385524336 Jun 09 12:24:07 PM PDT 24 Jun 09 12:24:22 PM PDT 24 7125560932 ps
T467 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3376321101 Jun 09 12:23:48 PM PDT 24 Jun 09 12:24:30 PM PDT 24 5737678720 ps
T468 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.810601240 Jun 09 12:23:59 PM PDT 24 Jun 09 12:24:04 PM PDT 24 347714635 ps
T469 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.838463198 Jun 09 12:23:54 PM PDT 24 Jun 09 12:24:08 PM PDT 24 5802338786 ps

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1620680540
Short name T3
Test name
Test status
Simulation time 48414973112 ps
CPU time 3757.44 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 01:30:41 PM PDT 24
Peak memory 235500 kb
Host smart-5af28178-5dbb-4297-aef6-91776c735cb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620680540 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1620680540
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.63132741
Short name T7
Test name
Test status
Simulation time 25667236268 ps
CPU time 157.97 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:31:40 PM PDT 24
Peak memory 234224 kb
Host smart-32aaf226-473b-4695-b55c-5f7c98a0b790
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63132741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_co
rrupt_sig_fatal_chk.63132741
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.595382668
Short name T38
Test name
Test status
Simulation time 24401903295 ps
CPU time 268.07 seconds
Started Jun 09 12:28:22 PM PDT 24
Finished Jun 09 12:32:51 PM PDT 24
Peak memory 236624 kb
Host smart-b24356f2-b480-4ba1-a410-242805965574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595382668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.595382668
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2890064316
Short name T113
Test name
Test status
Simulation time 3050343097 ps
CPU time 68.11 seconds
Started Jun 09 12:23:59 PM PDT 24
Finished Jun 09 12:25:08 PM PDT 24
Peak memory 219092 kb
Host smart-21a45491-91b1-4fb3-a786-3eac83cc9344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890064316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2890064316
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2930010331
Short name T16
Test name
Test status
Simulation time 16877759634 ps
CPU time 59.47 seconds
Started Jun 09 12:27:51 PM PDT 24
Finished Jun 09 12:28:51 PM PDT 24
Peak memory 235424 kb
Host smart-28a8949b-da90-474c-93a1-7cea8919f762
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930010331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2930010331
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.434527595
Short name T59
Test name
Test status
Simulation time 14321670555 ps
CPU time 68.03 seconds
Started Jun 09 12:23:54 PM PDT 24
Finished Jun 09 12:25:03 PM PDT 24
Peak memory 211032 kb
Host smart-a5bacbd2-6f67-4528-aed6-6fb46dee6979
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434527595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.434527595
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3051857018
Short name T6
Test name
Test status
Simulation time 3697316247 ps
CPU time 7.33 seconds
Started Jun 09 12:28:40 PM PDT 24
Finished Jun 09 12:28:48 PM PDT 24
Peak memory 210796 kb
Host smart-f807e835-589a-4106-9af7-98bc4ba5d25b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051857018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3051857018
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3822465432
Short name T51
Test name
Test status
Simulation time 2778570895 ps
CPU time 75.9 seconds
Started Jun 09 12:24:18 PM PDT 24
Finished Jun 09 12:25:34 PM PDT 24
Peak memory 219116 kb
Host smart-e8b25d56-a78c-40ef-93e5-b79db9a52508
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822465432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3822465432
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4049175089
Short name T148
Test name
Test status
Simulation time 14559643602 ps
CPU time 31.42 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:33 PM PDT 24
Peak memory 211976 kb
Host smart-1dfc92a7-443c-4db8-a20d-56c64b0019bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049175089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4049175089
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1261455740
Short name T252
Test name
Test status
Simulation time 340446483 ps
CPU time 9.21 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:13 PM PDT 24
Peak memory 211516 kb
Host smart-42837cdd-d24c-492d-8e0a-ceae3e23e06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261455740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1261455740
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1619989583
Short name T440
Test name
Test status
Simulation time 2082002807 ps
CPU time 78.4 seconds
Started Jun 09 12:24:09 PM PDT 24
Finished Jun 09 12:25:28 PM PDT 24
Peak memory 219060 kb
Host smart-a4b6181b-e6e7-4d67-a5c5-109d3f97c85f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619989583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1619989583
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3267994381
Short name T82
Test name
Test status
Simulation time 3587098559 ps
CPU time 27.97 seconds
Started Jun 09 12:23:44 PM PDT 24
Finished Jun 09 12:24:13 PM PDT 24
Peak memory 211016 kb
Host smart-167ef84a-aabe-489d-8dd6-405bdebcf9c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267994381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3267994381
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1683816471
Short name T8
Test name
Test status
Simulation time 222462476 ps
CPU time 5.27 seconds
Started Jun 09 12:27:52 PM PDT 24
Finished Jun 09 12:27:58 PM PDT 24
Peak memory 210916 kb
Host smart-1f29916f-c714-4db6-8184-d4f0e2c88341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683816471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1683816471
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.381209141
Short name T75
Test name
Test status
Simulation time 4896735983 ps
CPU time 12.02 seconds
Started Jun 09 12:28:25 PM PDT 24
Finished Jun 09 12:28:38 PM PDT 24
Peak memory 214004 kb
Host smart-5b5433fd-dff1-42ae-aa20-0954155ce16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381209141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.381209141
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3295983921
Short name T12
Test name
Test status
Simulation time 161804354307 ps
CPU time 8839.35 seconds
Started Jun 09 12:28:19 PM PDT 24
Finished Jun 09 02:55:40 PM PDT 24
Peak memory 238616 kb
Host smart-2a2f4a33-432a-4473-9da3-19415b1f235a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295983921 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3295983921
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.809333245
Short name T66
Test name
Test status
Simulation time 1884540689 ps
CPU time 14.87 seconds
Started Jun 09 12:23:44 PM PDT 24
Finished Jun 09 12:23:59 PM PDT 24
Peak memory 218508 kb
Host smart-de62c0b1-6fb8-4dd0-a77a-016ff9032c99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809333245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.809333245
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2167401099
Short name T96
Test name
Test status
Simulation time 6122411424 ps
CPU time 14 seconds
Started Jun 09 12:27:55 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 211072 kb
Host smart-d581c812-be8b-4586-9f3d-c1c15a16b37e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167401099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2167401099
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1340159521
Short name T48
Test name
Test status
Simulation time 133896985343 ps
CPU time 1429.49 seconds
Started Jun 09 12:28:30 PM PDT 24
Finished Jun 09 12:52:20 PM PDT 24
Peak memory 235512 kb
Host smart-0e054451-d562-4626-86d3-d0f42c5fc873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340159521 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1340159521
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1139272314
Short name T78
Test name
Test status
Simulation time 1872610330 ps
CPU time 14.94 seconds
Started Jun 09 12:23:50 PM PDT 24
Finished Jun 09 12:24:05 PM PDT 24
Peak memory 218880 kb
Host smart-91c6968f-8217-4ecf-b3f4-db98870d6107
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139272314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1139272314
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.47848833
Short name T80
Test name
Test status
Simulation time 343485277 ps
CPU time 7.31 seconds
Started Jun 09 12:23:45 PM PDT 24
Finished Jun 09 12:23:53 PM PDT 24
Peak memory 218052 kb
Host smart-4e09bd90-4db3-436a-83d3-04c47875e14c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47848833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_res
et.47848833
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1975717602
Short name T364
Test name
Test status
Simulation time 4193176161 ps
CPU time 11.9 seconds
Started Jun 09 12:23:48 PM PDT 24
Finished Jun 09 12:24:01 PM PDT 24
Peak memory 219524 kb
Host smart-82554fc2-08f9-44ba-a0ee-5b039573110f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975717602 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1975717602
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1717954097
Short name T395
Test name
Test status
Simulation time 2866801350 ps
CPU time 6.9 seconds
Started Jun 09 12:23:45 PM PDT 24
Finished Jun 09 12:23:52 PM PDT 24
Peak memory 217888 kb
Host smart-7ab4e4a0-741b-4915-bd5f-528828571bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717954097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1717954097
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.601533824
Short name T438
Test name
Test status
Simulation time 3470196691 ps
CPU time 14.4 seconds
Started Jun 09 12:23:43 PM PDT 24
Finished Jun 09 12:23:58 PM PDT 24
Peak memory 210716 kb
Host smart-5878561a-8630-4bb5-b58c-90e24f677ed8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601533824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.601533824
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.821511968
Short name T385
Test name
Test status
Simulation time 332548352 ps
CPU time 6.47 seconds
Started Jun 09 12:23:42 PM PDT 24
Finished Jun 09 12:23:49 PM PDT 24
Peak memory 210592 kb
Host smart-59f3219e-68fa-4aee-9205-f1d7266b117c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821511968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
821511968
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1865129526
Short name T429
Test name
Test status
Simulation time 979943559 ps
CPU time 18.4 seconds
Started Jun 09 12:23:46 PM PDT 24
Finished Jun 09 12:24:05 PM PDT 24
Peak memory 210876 kb
Host smart-2fd1f1f1-d76f-40b1-8800-d1dae5ab5c94
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865129526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1865129526
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1349391175
Short name T444
Test name
Test status
Simulation time 3572552565 ps
CPU time 14.94 seconds
Started Jun 09 12:23:42 PM PDT 24
Finished Jun 09 12:23:57 PM PDT 24
Peak memory 219384 kb
Host smart-ecfba100-76b3-461e-8de4-74ff1b0e5d2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349391175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1349391175
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3235337551
Short name T449
Test name
Test status
Simulation time 959811670 ps
CPU time 11.34 seconds
Started Jun 09 12:23:44 PM PDT 24
Finished Jun 09 12:23:56 PM PDT 24
Peak memory 218932 kb
Host smart-3897187f-f5e3-4691-b879-73cac6a7be11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235337551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3235337551
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1570401869
Short name T116
Test name
Test status
Simulation time 3915552464 ps
CPU time 40.48 seconds
Started Jun 09 12:23:44 PM PDT 24
Finished Jun 09 12:24:25 PM PDT 24
Peak memory 218684 kb
Host smart-31a492df-2962-4dc6-bbcc-3e9b8e92e75b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570401869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1570401869
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1455878238
Short name T56
Test name
Test status
Simulation time 4150483403 ps
CPU time 16.51 seconds
Started Jun 09 12:23:47 PM PDT 24
Finished Jun 09 12:24:04 PM PDT 24
Peak memory 210924 kb
Host smart-0be3751e-c736-401d-8ce5-402ddab27c8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455878238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1455878238
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3098537262
Short name T458
Test name
Test status
Simulation time 5420940162 ps
CPU time 12 seconds
Started Jun 09 12:23:44 PM PDT 24
Finished Jun 09 12:23:57 PM PDT 24
Peak memory 210948 kb
Host smart-09a40165-8252-4a34-8a62-b94365b797cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098537262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3098537262
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4138418445
Short name T456
Test name
Test status
Simulation time 6295927259 ps
CPU time 15.63 seconds
Started Jun 09 12:23:51 PM PDT 24
Finished Jun 09 12:24:08 PM PDT 24
Peak memory 219064 kb
Host smart-f42d9736-ce04-4399-9508-d7468941badd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138418445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4138418445
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1690378623
Short name T371
Test name
Test status
Simulation time 1128909854 ps
CPU time 11.31 seconds
Started Jun 09 12:23:44 PM PDT 24
Finished Jun 09 12:23:56 PM PDT 24
Peak memory 219032 kb
Host smart-67542b7f-5caa-4aa3-b4bd-c789b5d19713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690378623 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1690378623
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.650270750
Short name T422
Test name
Test status
Simulation time 1258111474 ps
CPU time 11.04 seconds
Started Jun 09 12:23:47 PM PDT 24
Finished Jun 09 12:23:58 PM PDT 24
Peak memory 210876 kb
Host smart-94ea432e-02e8-4ca6-8fe7-be6c8c2bee84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650270750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.650270750
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.28229240
Short name T417
Test name
Test status
Simulation time 1122526694 ps
CPU time 9.54 seconds
Started Jun 09 12:23:52 PM PDT 24
Finished Jun 09 12:24:02 PM PDT 24
Peak memory 210576 kb
Host smart-c5242e2d-f1f0-4677-934b-72410d728dbe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28229240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_
mem_partial_access.28229240
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.987167169
Short name T407
Test name
Test status
Simulation time 4236892928 ps
CPU time 10.52 seconds
Started Jun 09 12:23:47 PM PDT 24
Finished Jun 09 12:23:58 PM PDT 24
Peak memory 210724 kb
Host smart-33e725f5-df90-441e-940a-723ad561f556
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987167169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
987167169
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1950244112
Short name T423
Test name
Test status
Simulation time 93871355 ps
CPU time 6.14 seconds
Started Jun 09 12:23:46 PM PDT 24
Finished Jun 09 12:23:52 PM PDT 24
Peak memory 210932 kb
Host smart-417b36fc-03c9-44f7-a99a-0ff5e54e782b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950244112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1950244112
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2534172703
Short name T393
Test name
Test status
Simulation time 1441548801 ps
CPU time 16.87 seconds
Started Jun 09 12:23:44 PM PDT 24
Finished Jun 09 12:24:02 PM PDT 24
Peak memory 218952 kb
Host smart-7935a0a8-5b1c-4825-b20a-1a9c2c8efeb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534172703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2534172703
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2516716932
Short name T432
Test name
Test status
Simulation time 3217571718 ps
CPU time 68.16 seconds
Started Jun 09 12:23:45 PM PDT 24
Finished Jun 09 12:24:53 PM PDT 24
Peak memory 219120 kb
Host smart-d8e59cf2-e1d4-49d5-aaca-516a404d8219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516716932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2516716932
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2331862250
Short name T370
Test name
Test status
Simulation time 329617501 ps
CPU time 4.45 seconds
Started Jun 09 12:23:58 PM PDT 24
Finished Jun 09 12:24:03 PM PDT 24
Peak memory 219084 kb
Host smart-e2661899-980d-43a9-b22b-17589940aec5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331862250 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2331862250
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.606789617
Short name T387
Test name
Test status
Simulation time 1905170688 ps
CPU time 15.08 seconds
Started Jun 09 12:24:02 PM PDT 24
Finished Jun 09 12:24:18 PM PDT 24
Peak memory 210816 kb
Host smart-c528e115-286d-4c6f-890b-d4218ee1454c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606789617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.606789617
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3674170087
Short name T54
Test name
Test status
Simulation time 364489487 ps
CPU time 19.06 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:24:28 PM PDT 24
Peak memory 210896 kb
Host smart-6148b81e-d201-4245-93a1-9a414cb51126
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674170087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3674170087
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2517793074
Short name T460
Test name
Test status
Simulation time 5946225581 ps
CPU time 13.4 seconds
Started Jun 09 12:24:06 PM PDT 24
Finished Jun 09 12:24:20 PM PDT 24
Peak memory 211072 kb
Host smart-3cec2256-9b7b-4e6f-89c9-d106911c246a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517793074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2517793074
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.677632098
Short name T431
Test name
Test status
Simulation time 602411923 ps
CPU time 8.86 seconds
Started Jun 09 12:24:03 PM PDT 24
Finished Jun 09 12:24:12 PM PDT 24
Peak memory 219256 kb
Host smart-26135891-6efb-4d63-956e-379e5eade80b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677632098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.677632098
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2786204960
Short name T115
Test name
Test status
Simulation time 1662843201 ps
CPU time 74.54 seconds
Started Jun 09 12:23:58 PM PDT 24
Finished Jun 09 12:25:14 PM PDT 24
Peak memory 211316 kb
Host smart-b988d3c4-b89d-4035-9cd9-5bffe4c41208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786204960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2786204960
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2628192332
Short name T414
Test name
Test status
Simulation time 216910146 ps
CPU time 4.44 seconds
Started Jun 09 12:24:02 PM PDT 24
Finished Jun 09 12:24:06 PM PDT 24
Peak memory 211908 kb
Host smart-76117b9a-6681-4274-8df2-66495f80bccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628192332 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2628192332
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4229108071
Short name T447
Test name
Test status
Simulation time 7996152151 ps
CPU time 15.74 seconds
Started Jun 09 12:24:03 PM PDT 24
Finished Jun 09 12:24:19 PM PDT 24
Peak memory 219072 kb
Host smart-b91bd2f7-ff60-493b-bd36-52fcd9c70561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229108071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4229108071
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1615732297
Short name T451
Test name
Test status
Simulation time 4326422882 ps
CPU time 43.98 seconds
Started Jun 09 12:23:58 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 219108 kb
Host smart-4080577a-1ef9-4200-87dd-742043f7fc86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615732297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1615732297
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1908367045
Short name T405
Test name
Test status
Simulation time 2330168872 ps
CPU time 13.21 seconds
Started Jun 09 12:24:10 PM PDT 24
Finished Jun 09 12:24:24 PM PDT 24
Peak memory 210944 kb
Host smart-6bdad9ad-5229-4806-a21d-4080d51dc519
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908367045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1908367045
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1516098603
Short name T428
Test name
Test status
Simulation time 4120303651 ps
CPU time 9.35 seconds
Started Jun 09 12:23:59 PM PDT 24
Finished Jun 09 12:24:09 PM PDT 24
Peak memory 219028 kb
Host smart-d065fffb-4d59-4ebe-8f40-bdd1464d3aef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516098603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1516098603
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1268362129
Short name T398
Test name
Test status
Simulation time 1453062412 ps
CPU time 13.34 seconds
Started Jun 09 12:24:06 PM PDT 24
Finished Jun 09 12:24:19 PM PDT 24
Peak memory 219100 kb
Host smart-03dcedf4-1d87-4d32-a07d-d9dcad2531cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268362129 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1268362129
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.810601240
Short name T468
Test name
Test status
Simulation time 347714635 ps
CPU time 4.25 seconds
Started Jun 09 12:23:59 PM PDT 24
Finished Jun 09 12:24:04 PM PDT 24
Peak memory 210916 kb
Host smart-9ed7780a-2fad-4864-8880-618578673d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810601240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.810601240
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.744627527
Short name T392
Test name
Test status
Simulation time 10032169352 ps
CPU time 43.78 seconds
Started Jun 09 12:24:10 PM PDT 24
Finished Jun 09 12:24:55 PM PDT 24
Peak memory 210932 kb
Host smart-814bd1b2-8ae8-4ec8-9754-ef9e8afefd5e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744627527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.744627527
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2420449361
Short name T412
Test name
Test status
Simulation time 175311240 ps
CPU time 4.44 seconds
Started Jun 09 12:23:59 PM PDT 24
Finished Jun 09 12:24:04 PM PDT 24
Peak memory 210880 kb
Host smart-dda06921-8507-4472-813e-370ae7e9324b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420449361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2420449361
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3954592535
Short name T461
Test name
Test status
Simulation time 2010090652 ps
CPU time 18.18 seconds
Started Jun 09 12:24:10 PM PDT 24
Finished Jun 09 12:24:29 PM PDT 24
Peak memory 218908 kb
Host smart-552e910e-a0ef-4171-bce2-23a51463e45b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954592535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3954592535
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1385524336
Short name T466
Test name
Test status
Simulation time 7125560932 ps
CPU time 14.57 seconds
Started Jun 09 12:24:07 PM PDT 24
Finished Jun 09 12:24:22 PM PDT 24
Peak memory 219160 kb
Host smart-82570da6-1ccb-4ef1-8dd2-41064b09d282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385524336 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1385524336
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2837978718
Short name T437
Test name
Test status
Simulation time 346555009 ps
CPU time 5.29 seconds
Started Jun 09 12:24:07 PM PDT 24
Finished Jun 09 12:24:12 PM PDT 24
Peak memory 218020 kb
Host smart-5e107422-0289-4eb6-872a-2e3aebfc6116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837978718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2837978718
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2527728388
Short name T379
Test name
Test status
Simulation time 17607451818 ps
CPU time 77.37 seconds
Started Jun 09 12:24:28 PM PDT 24
Finished Jun 09 12:25:46 PM PDT 24
Peak memory 211960 kb
Host smart-b980f5b4-97f3-4dd6-b542-7d530c3def2b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527728388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2527728388
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.156048443
Short name T441
Test name
Test status
Simulation time 17423437092 ps
CPU time 14.06 seconds
Started Jun 09 12:24:07 PM PDT 24
Finished Jun 09 12:24:22 PM PDT 24
Peak memory 219088 kb
Host smart-9be12da0-460e-405f-b457-e64423cf10c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156048443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.156048443
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4043255750
Short name T439
Test name
Test status
Simulation time 7926753288 ps
CPU time 11.5 seconds
Started Jun 09 12:24:09 PM PDT 24
Finished Jun 09 12:24:21 PM PDT 24
Peak memory 218980 kb
Host smart-db3fa194-8cd3-4f84-9bc9-1aa0499795ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043255750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4043255750
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2873848463
Short name T53
Test name
Test status
Simulation time 1273383921 ps
CPU time 69.66 seconds
Started Jun 09 12:24:11 PM PDT 24
Finished Jun 09 12:25:21 PM PDT 24
Peak memory 219032 kb
Host smart-75c4b208-a679-4d10-8ee3-5421c3746ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873848463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2873848463
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2916766379
Short name T402
Test name
Test status
Simulation time 2236871996 ps
CPU time 8 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:24:16 PM PDT 24
Peak memory 219192 kb
Host smart-cf3f706a-56c0-4999-8a76-0370475857c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916766379 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2916766379
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1793047291
Short name T380
Test name
Test status
Simulation time 4197548686 ps
CPU time 16.77 seconds
Started Jun 09 12:24:07 PM PDT 24
Finished Jun 09 12:24:24 PM PDT 24
Peak memory 210948 kb
Host smart-9351f33c-a156-4586-bdb8-ce89854d7916
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793047291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1793047291
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3107209476
Short name T107
Test name
Test status
Simulation time 47502763325 ps
CPU time 94.02 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:25:43 PM PDT 24
Peak memory 210904 kb
Host smart-58d34173-413e-4b0c-99a8-eb0953c73374
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107209476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3107209476
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1360662714
Short name T433
Test name
Test status
Simulation time 88859069 ps
CPU time 4.42 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:24:13 PM PDT 24
Peak memory 210916 kb
Host smart-4c8a43f2-1e18-4665-885b-1014a97dd4b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360662714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1360662714
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2545614139
Short name T384
Test name
Test status
Simulation time 2078616316 ps
CPU time 14.5 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:24:23 PM PDT 24
Peak memory 218944 kb
Host smart-b22a0e2c-b97d-4226-8db7-cfc7370970b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545614139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2545614139
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2447455703
Short name T383
Test name
Test status
Simulation time 7786541387 ps
CPU time 76.01 seconds
Started Jun 09 12:24:04 PM PDT 24
Finished Jun 09 12:25:21 PM PDT 24
Peak memory 212660 kb
Host smart-af4f142c-19ba-4436-ae57-1a34a07cb354
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447455703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2447455703
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2294925619
Short name T367
Test name
Test status
Simulation time 5153172557 ps
CPU time 11.14 seconds
Started Jun 09 12:24:21 PM PDT 24
Finished Jun 09 12:24:33 PM PDT 24
Peak memory 219128 kb
Host smart-ddd8664b-8fd9-4c7b-a84d-ceffc9173703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294925619 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2294925619
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4003227007
Short name T450
Test name
Test status
Simulation time 321113864 ps
CPU time 4.13 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:24:13 PM PDT 24
Peak memory 210892 kb
Host smart-dc4c3eb7-f7c1-4d47-8c5f-237a50e8ec82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003227007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4003227007
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2816516145
Short name T410
Test name
Test status
Simulation time 380214883 ps
CPU time 18.53 seconds
Started Jun 09 12:24:09 PM PDT 24
Finished Jun 09 12:24:28 PM PDT 24
Peak memory 210940 kb
Host smart-bf7be4bb-5abb-484c-93eb-aaf1f431966e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816516145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2816516145
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1486440041
Short name T63
Test name
Test status
Simulation time 2919450099 ps
CPU time 8.73 seconds
Started Jun 09 12:24:34 PM PDT 24
Finished Jun 09 12:24:43 PM PDT 24
Peak memory 218348 kb
Host smart-4f9d8b94-297f-454d-8908-ba33535effdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486440041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1486440041
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.750743989
Short name T409
Test name
Test status
Simulation time 335278404 ps
CPU time 8.9 seconds
Started Jun 09 12:24:05 PM PDT 24
Finished Jun 09 12:24:14 PM PDT 24
Peak memory 218948 kb
Host smart-6f73e6d4-902a-4151-b0f0-659f9b7657d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750743989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.750743989
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2711763720
Short name T386
Test name
Test status
Simulation time 4123203683 ps
CPU time 10.55 seconds
Started Jun 09 12:24:10 PM PDT 24
Finished Jun 09 12:24:21 PM PDT 24
Peak memory 219152 kb
Host smart-27cf32e6-d07e-4d5e-8be3-823ae89c2f6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711763720 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2711763720
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1152870095
Short name T416
Test name
Test status
Simulation time 85580723 ps
CPU time 4.14 seconds
Started Jun 09 12:24:06 PM PDT 24
Finished Jun 09 12:24:11 PM PDT 24
Peak memory 210828 kb
Host smart-338756d1-fa06-4217-8cdd-aedeaaaef9dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152870095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1152870095
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.680121506
Short name T378
Test name
Test status
Simulation time 792529036 ps
CPU time 32.53 seconds
Started Jun 09 12:24:04 PM PDT 24
Finished Jun 09 12:24:37 PM PDT 24
Peak memory 210896 kb
Host smart-cc0185a4-7029-478d-99a6-9ff502808e88
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680121506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.680121506
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.895498436
Short name T67
Test name
Test status
Simulation time 7716598041 ps
CPU time 17.37 seconds
Started Jun 09 12:24:33 PM PDT 24
Finished Jun 09 12:24:51 PM PDT 24
Peak memory 211360 kb
Host smart-3b8ba72a-eb22-400c-bf19-092a4c4d4b69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895498436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.895498436
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1217486982
Short name T406
Test name
Test status
Simulation time 307010716 ps
CPU time 10.18 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:24:19 PM PDT 24
Peak memory 218980 kb
Host smart-e46410f1-90e3-4a06-827e-23705d1bc5fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217486982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1217486982
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4245683130
Short name T110
Test name
Test status
Simulation time 2722893230 ps
CPU time 81.06 seconds
Started Jun 09 12:24:07 PM PDT 24
Finished Jun 09 12:25:29 PM PDT 24
Peak memory 212376 kb
Host smart-849ef647-b86e-4716-99b4-242008bfc4b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245683130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4245683130
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.214823980
Short name T453
Test name
Test status
Simulation time 21203851953 ps
CPU time 13.34 seconds
Started Jun 09 12:24:12 PM PDT 24
Finished Jun 09 12:24:26 PM PDT 24
Peak memory 219156 kb
Host smart-77da30d3-c319-4077-bb64-860ec58584ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214823980 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.214823980
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1602050689
Short name T462
Test name
Test status
Simulation time 1464777281 ps
CPU time 13.36 seconds
Started Jun 09 12:24:11 PM PDT 24
Finished Jun 09 12:24:25 PM PDT 24
Peak memory 210880 kb
Host smart-54e96d13-171d-487b-9474-9c26e12b1061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602050689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1602050689
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2782413138
Short name T79
Test name
Test status
Simulation time 42223007051 ps
CPU time 84.33 seconds
Started Jun 09 12:24:31 PM PDT 24
Finished Jun 09 12:25:56 PM PDT 24
Peak memory 210964 kb
Host smart-49f901df-22ad-45b5-a429-976fc0d56db0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782413138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2782413138
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1307833250
Short name T448
Test name
Test status
Simulation time 520702343 ps
CPU time 7.54 seconds
Started Jun 09 12:24:30 PM PDT 24
Finished Jun 09 12:24:38 PM PDT 24
Peak memory 210920 kb
Host smart-5138ec1f-3549-4d8c-b446-10ab70444ff2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307833250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1307833250
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.818949513
Short name T420
Test name
Test status
Simulation time 5244568650 ps
CPU time 10.16 seconds
Started Jun 09 12:24:05 PM PDT 24
Finished Jun 09 12:24:15 PM PDT 24
Peak memory 218988 kb
Host smart-7a1e6ddb-cb44-48a1-9187-048e88add6be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818949513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.818949513
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3720948594
Short name T111
Test name
Test status
Simulation time 536174525 ps
CPU time 40 seconds
Started Jun 09 12:24:07 PM PDT 24
Finished Jun 09 12:24:48 PM PDT 24
Peak memory 213356 kb
Host smart-544cbe32-0f19-496e-9292-3847939496ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720948594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3720948594
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2977300179
Short name T373
Test name
Test status
Simulation time 7933536544 ps
CPU time 15.79 seconds
Started Jun 09 12:24:17 PM PDT 24
Finished Jun 09 12:24:33 PM PDT 24
Peak memory 219100 kb
Host smart-02f8e29c-cb38-4a26-82c0-1e9b387a865b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977300179 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2977300179
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2609693912
Short name T93
Test name
Test status
Simulation time 6793968901 ps
CPU time 11.89 seconds
Started Jun 09 12:24:20 PM PDT 24
Finished Jun 09 12:24:32 PM PDT 24
Peak memory 210888 kb
Host smart-8c646508-cc3c-4792-b642-a9d033729ae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609693912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2609693912
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1271846747
Short name T61
Test name
Test status
Simulation time 20668409177 ps
CPU time 64.32 seconds
Started Jun 09 12:24:21 PM PDT 24
Finished Jun 09 12:25:26 PM PDT 24
Peak memory 210936 kb
Host smart-ac1884ff-2999-420f-8862-bf81f4711245
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271846747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1271846747
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1065491855
Short name T94
Test name
Test status
Simulation time 2134699233 ps
CPU time 18.22 seconds
Started Jun 09 12:24:07 PM PDT 24
Finished Jun 09 12:24:25 PM PDT 24
Peak memory 211220 kb
Host smart-cc938821-eb3b-4aee-b694-6224c3487e73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065491855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1065491855
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.974346288
Short name T425
Test name
Test status
Simulation time 5971681063 ps
CPU time 15.7 seconds
Started Jun 09 12:24:13 PM PDT 24
Finished Jun 09 12:24:29 PM PDT 24
Peak memory 218992 kb
Host smart-a09404cc-f63e-46ff-9395-028f07d893b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974346288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.974346288
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3265658024
Short name T112
Test name
Test status
Simulation time 3628871411 ps
CPU time 76.72 seconds
Started Jun 09 12:24:09 PM PDT 24
Finished Jun 09 12:25:27 PM PDT 24
Peak memory 212296 kb
Host smart-94455722-8831-4083-83b9-497ad13543f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265658024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3265658024
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1111638896
Short name T399
Test name
Test status
Simulation time 355744691 ps
CPU time 4.34 seconds
Started Jun 09 12:24:11 PM PDT 24
Finished Jun 09 12:24:16 PM PDT 24
Peak memory 219036 kb
Host smart-5286b93f-ee8b-4a4c-b666-d0349ccd76b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111638896 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1111638896
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3543668355
Short name T435
Test name
Test status
Simulation time 2720090910 ps
CPU time 12.24 seconds
Started Jun 09 12:24:21 PM PDT 24
Finished Jun 09 12:24:34 PM PDT 24
Peak memory 210944 kb
Host smart-df783ae4-f286-4cd8-a546-59773147caee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543668355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3543668355
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2082151694
Short name T443
Test name
Test status
Simulation time 40651011757 ps
CPU time 81.56 seconds
Started Jun 09 12:24:11 PM PDT 24
Finished Jun 09 12:25:33 PM PDT 24
Peak memory 210964 kb
Host smart-fbdaf440-551b-498b-a09f-a1bf0ee62150
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082151694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2082151694
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3721328574
Short name T403
Test name
Test status
Simulation time 6195995815 ps
CPU time 13.61 seconds
Started Jun 09 12:24:27 PM PDT 24
Finished Jun 09 12:24:41 PM PDT 24
Peak memory 210884 kb
Host smart-330caf31-6978-4269-9176-5bd14e4c17c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721328574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3721328574
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4221823578
Short name T369
Test name
Test status
Simulation time 1489300642 ps
CPU time 16.76 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:24:26 PM PDT 24
Peak memory 218972 kb
Host smart-a1b35bf6-7e93-4363-a2cf-d68f62dc53e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221823578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4221823578
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1063721402
Short name T114
Test name
Test status
Simulation time 1121454829 ps
CPU time 69.04 seconds
Started Jun 09 12:24:12 PM PDT 24
Finished Jun 09 12:25:22 PM PDT 24
Peak memory 211564 kb
Host smart-9515fda9-ba06-4e14-9a40-4764fc86e0f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063721402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1063721402
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1045922115
Short name T442
Test name
Test status
Simulation time 343730035 ps
CPU time 6.37 seconds
Started Jun 09 12:23:57 PM PDT 24
Finished Jun 09 12:24:04 PM PDT 24
Peak memory 210888 kb
Host smart-cc641919-b738-4dd1-9ce3-83819c2dc1dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045922115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1045922115
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2254350541
Short name T368
Test name
Test status
Simulation time 5056968962 ps
CPU time 12.34 seconds
Started Jun 09 12:24:16 PM PDT 24
Finished Jun 09 12:24:29 PM PDT 24
Peak memory 218796 kb
Host smart-e8467fd8-62b6-4728-827b-660395421de4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254350541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2254350541
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2054435606
Short name T419
Test name
Test status
Simulation time 6751819590 ps
CPU time 17.08 seconds
Started Jun 09 12:23:49 PM PDT 24
Finished Jun 09 12:24:07 PM PDT 24
Peak memory 211288 kb
Host smart-38eafccf-fcb4-478f-96de-f55f0bd09966
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054435606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2054435606
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.460600478
Short name T418
Test name
Test status
Simulation time 2139332263 ps
CPU time 11.07 seconds
Started Jun 09 12:23:47 PM PDT 24
Finished Jun 09 12:23:58 PM PDT 24
Peak memory 219040 kb
Host smart-90f78383-2bb9-4ca1-a9f8-23b6f7414ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460600478 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.460600478
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2948754956
Short name T76
Test name
Test status
Simulation time 498596386 ps
CPU time 4.99 seconds
Started Jun 09 12:23:55 PM PDT 24
Finished Jun 09 12:24:01 PM PDT 24
Peak memory 217744 kb
Host smart-4eddc8c6-5973-478b-91eb-7e81f51a6704
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948754956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2948754956
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3631729468
Short name T430
Test name
Test status
Simulation time 2911152612 ps
CPU time 12.35 seconds
Started Jun 09 12:23:45 PM PDT 24
Finished Jun 09 12:23:58 PM PDT 24
Peak memory 210652 kb
Host smart-6d7abd27-1d60-4400-9680-ead77cb5a0d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631729468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3631729468
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3057356936
Short name T365
Test name
Test status
Simulation time 1528512250 ps
CPU time 12.97 seconds
Started Jun 09 12:24:04 PM PDT 24
Finished Jun 09 12:24:17 PM PDT 24
Peak memory 210580 kb
Host smart-6917ec9d-36d5-41ad-b25f-f7f338310eb4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057356936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3057356936
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.778151439
Short name T381
Test name
Test status
Simulation time 20008232134 ps
CPU time 46.94 seconds
Started Jun 09 12:23:43 PM PDT 24
Finished Jun 09 12:24:30 PM PDT 24
Peak memory 210916 kb
Host smart-049153e4-40b8-4ea2-b19d-fec7d88fff07
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778151439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.778151439
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1418912987
Short name T465
Test name
Test status
Simulation time 3021545363 ps
CPU time 9.34 seconds
Started Jun 09 12:23:59 PM PDT 24
Finished Jun 09 12:24:09 PM PDT 24
Peak memory 218420 kb
Host smart-9d8e422b-4983-4889-a2ff-4e723308ad4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418912987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1418912987
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2759987039
Short name T372
Test name
Test status
Simulation time 87385296 ps
CPU time 6.22 seconds
Started Jun 09 12:24:02 PM PDT 24
Finished Jun 09 12:24:08 PM PDT 24
Peak memory 215116 kb
Host smart-fe1f5710-34bb-4c47-97ed-38898eaecd7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759987039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2759987039
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3153030153
Short name T117
Test name
Test status
Simulation time 3400877130 ps
CPU time 71.16 seconds
Started Jun 09 12:23:47 PM PDT 24
Finished Jun 09 12:24:59 PM PDT 24
Peak memory 212272 kb
Host smart-abfc0000-0b63-4d0b-8b06-952cd20d2720
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153030153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3153030153
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2338613355
Short name T389
Test name
Test status
Simulation time 168500038 ps
CPU time 4.33 seconds
Started Jun 09 12:23:48 PM PDT 24
Finished Jun 09 12:23:53 PM PDT 24
Peak memory 210804 kb
Host smart-c0c571b6-9972-45b5-b2bf-1835790b1ec7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338613355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2338613355
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3535170757
Short name T455
Test name
Test status
Simulation time 1385004923 ps
CPU time 5.3 seconds
Started Jun 09 12:24:00 PM PDT 24
Finished Jun 09 12:24:06 PM PDT 24
Peak memory 217880 kb
Host smart-09a31689-556b-4e64-82b9-1fdb0b499fd8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535170757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3535170757
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3517919498
Short name T401
Test name
Test status
Simulation time 7433778723 ps
CPU time 17.08 seconds
Started Jun 09 12:23:53 PM PDT 24
Finished Jun 09 12:24:11 PM PDT 24
Peak memory 219024 kb
Host smart-a8067c8f-0d27-4b8a-895d-908e7e21ec96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517919498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3517919498
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1976121751
Short name T459
Test name
Test status
Simulation time 4460472469 ps
CPU time 11.91 seconds
Started Jun 09 12:23:51 PM PDT 24
Finished Jun 09 12:24:03 PM PDT 24
Peak memory 216592 kb
Host smart-728d3680-6efc-4270-a3eb-ee31fc5612e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976121751 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1976121751
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2515448297
Short name T62
Test name
Test status
Simulation time 4069428343 ps
CPU time 16.19 seconds
Started Jun 09 12:23:48 PM PDT 24
Finished Jun 09 12:24:04 PM PDT 24
Peak memory 218516 kb
Host smart-976d5b7d-0b84-4527-9b05-1137d44a8988
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515448297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2515448297
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2765495604
Short name T413
Test name
Test status
Simulation time 2722024755 ps
CPU time 8.07 seconds
Started Jun 09 12:23:49 PM PDT 24
Finished Jun 09 12:23:58 PM PDT 24
Peak memory 210644 kb
Host smart-1758bdf2-6499-49a6-b170-97e95cf460a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765495604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2765495604
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1088862865
Short name T376
Test name
Test status
Simulation time 1821796069 ps
CPU time 15.3 seconds
Started Jun 09 12:23:49 PM PDT 24
Finished Jun 09 12:24:05 PM PDT 24
Peak memory 210556 kb
Host smart-7056956d-15ab-4b42-afca-28a58555871b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088862865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1088862865
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.810859482
Short name T65
Test name
Test status
Simulation time 7406156852 ps
CPU time 61.49 seconds
Started Jun 09 12:23:47 PM PDT 24
Finished Jun 09 12:24:49 PM PDT 24
Peak memory 219064 kb
Host smart-8b44e18a-6fe1-4b40-8dbf-3c5377731baf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810859482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.810859482
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3479807822
Short name T95
Test name
Test status
Simulation time 1422252163 ps
CPU time 14.4 seconds
Started Jun 09 12:23:48 PM PDT 24
Finished Jun 09 12:24:03 PM PDT 24
Peak memory 218976 kb
Host smart-4f63c5b2-9b11-4772-9c97-f7da12ca6cb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479807822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3479807822
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.392255767
Short name T382
Test name
Test status
Simulation time 4284320924 ps
CPU time 20.3 seconds
Started Jun 09 12:23:48 PM PDT 24
Finished Jun 09 12:24:09 PM PDT 24
Peak memory 219028 kb
Host smart-71fcbdfb-b03c-4ed9-9f3b-3541c9dd746d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392255767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.392255767
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.247502353
Short name T108
Test name
Test status
Simulation time 751349172 ps
CPU time 71.25 seconds
Started Jun 09 12:24:03 PM PDT 24
Finished Jun 09 12:25:14 PM PDT 24
Peak memory 212352 kb
Host smart-d5644ec7-9961-4eb3-b5e4-a0056bc2979a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247502353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.247502353
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3383425167
Short name T60
Test name
Test status
Simulation time 945526887 ps
CPU time 7.69 seconds
Started Jun 09 12:23:58 PM PDT 24
Finished Jun 09 12:24:07 PM PDT 24
Peak memory 210820 kb
Host smart-09ad6e79-ecf3-45ee-af55-fbaa63073fa6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383425167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3383425167
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3056592531
Short name T374
Test name
Test status
Simulation time 3155394795 ps
CPU time 7.76 seconds
Started Jun 09 12:23:56 PM PDT 24
Finished Jun 09 12:24:05 PM PDT 24
Peak memory 210968 kb
Host smart-e05a4674-704f-4037-871a-6c30cf5a974d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056592531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3056592531
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.267615175
Short name T98
Test name
Test status
Simulation time 2943624765 ps
CPU time 11.49 seconds
Started Jun 09 12:24:04 PM PDT 24
Finished Jun 09 12:24:15 PM PDT 24
Peak memory 218096 kb
Host smart-dd3d57d0-9095-4939-8f57-8ede26276a78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267615175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.267615175
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3068029665
Short name T388
Test name
Test status
Simulation time 1315246398 ps
CPU time 12.29 seconds
Started Jun 09 12:23:52 PM PDT 24
Finished Jun 09 12:24:05 PM PDT 24
Peak memory 219084 kb
Host smart-965a21d5-9b82-4971-ad4c-ed264a0ddcb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068029665 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3068029665
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.770150882
Short name T436
Test name
Test status
Simulation time 5784320628 ps
CPU time 12.45 seconds
Started Jun 09 12:23:59 PM PDT 24
Finished Jun 09 12:24:12 PM PDT 24
Peak memory 210900 kb
Host smart-ebf40ee8-0b44-4b5f-9e18-066d3448d86f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770150882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.770150882
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.96782421
Short name T377
Test name
Test status
Simulation time 89122296 ps
CPU time 4.07 seconds
Started Jun 09 12:24:04 PM PDT 24
Finished Jun 09 12:24:08 PM PDT 24
Peak memory 210584 kb
Host smart-b8659e60-a6d5-4f61-b967-772a6ce54eb3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96782421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_
mem_partial_access.96782421
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1628853562
Short name T375
Test name
Test status
Simulation time 743323944 ps
CPU time 8.82 seconds
Started Jun 09 12:24:03 PM PDT 24
Finished Jun 09 12:24:12 PM PDT 24
Peak memory 210612 kb
Host smart-d2453dcc-298c-420f-9410-b3331a52a315
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628853562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1628853562
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3107494607
Short name T452
Test name
Test status
Simulation time 767374220 ps
CPU time 19.11 seconds
Started Jun 09 12:24:02 PM PDT 24
Finished Jun 09 12:24:21 PM PDT 24
Peak memory 210896 kb
Host smart-b9ad29e4-c59e-4003-a171-86c6d3c8f704
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107494607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3107494607
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4183209248
Short name T415
Test name
Test status
Simulation time 733250069 ps
CPU time 9.28 seconds
Started Jun 09 12:24:06 PM PDT 24
Finished Jun 09 12:24:16 PM PDT 24
Peak memory 219016 kb
Host smart-440a06fc-685b-4216-ac37-22d549904267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183209248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4183209248
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4017258486
Short name T454
Test name
Test status
Simulation time 4114782000 ps
CPU time 20.3 seconds
Started Jun 09 12:23:58 PM PDT 24
Finished Jun 09 12:24:20 PM PDT 24
Peak memory 218992 kb
Host smart-2cc3ae42-1504-4333-b71a-b6ad7a08e209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017258486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4017258486
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3376321101
Short name T467
Test name
Test status
Simulation time 5737678720 ps
CPU time 41.55 seconds
Started Jun 09 12:23:48 PM PDT 24
Finished Jun 09 12:24:30 PM PDT 24
Peak memory 219092 kb
Host smart-00f4781c-ed82-48b3-abef-e8de319faee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376321101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3376321101
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1461596889
Short name T446
Test name
Test status
Simulation time 2445229487 ps
CPU time 8.4 seconds
Started Jun 09 12:23:55 PM PDT 24
Finished Jun 09 12:24:04 PM PDT 24
Peak memory 219120 kb
Host smart-234775f1-db3a-4a3f-8064-bbc472bec354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461596889 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1461596889
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1466592720
Short name T97
Test name
Test status
Simulation time 768384394 ps
CPU time 7.02 seconds
Started Jun 09 12:23:56 PM PDT 24
Finished Jun 09 12:24:04 PM PDT 24
Peak memory 217868 kb
Host smart-04e29631-01e3-41f6-9eaa-ed13227611f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466592720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1466592720
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4154866877
Short name T81
Test name
Test status
Simulation time 1509915779 ps
CPU time 17.88 seconds
Started Jun 09 12:23:52 PM PDT 24
Finished Jun 09 12:24:11 PM PDT 24
Peak memory 210868 kb
Host smart-cd9f56d1-07e6-40b1-beba-75467401f196
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154866877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4154866877
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1159143986
Short name T411
Test name
Test status
Simulation time 89032573 ps
CPU time 5.68 seconds
Started Jun 09 12:24:00 PM PDT 24
Finished Jun 09 12:24:06 PM PDT 24
Peak memory 219044 kb
Host smart-f52b8674-a4b7-48ef-ab05-6d41c538c608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159143986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1159143986
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.27770926
Short name T457
Test name
Test status
Simulation time 2161493817 ps
CPU time 20.56 seconds
Started Jun 09 12:23:52 PM PDT 24
Finished Jun 09 12:24:13 PM PDT 24
Peak memory 218996 kb
Host smart-72339145-77bb-45d1-9bb0-da927eb8d0f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27770926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.27770926
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1354494622
Short name T118
Test name
Test status
Simulation time 2048136817 ps
CPU time 77.63 seconds
Started Jun 09 12:24:02 PM PDT 24
Finished Jun 09 12:25:20 PM PDT 24
Peak memory 219036 kb
Host smart-08927853-34f7-4895-8a96-28333b4dcf81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354494622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1354494622
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2299824536
Short name T366
Test name
Test status
Simulation time 38094527037 ps
CPU time 15.85 seconds
Started Jun 09 12:23:58 PM PDT 24
Finished Jun 09 12:24:15 PM PDT 24
Peak memory 219184 kb
Host smart-9100babb-4b4b-425f-904a-ce73b8c868e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299824536 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2299824536
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.838463198
Short name T469
Test name
Test status
Simulation time 5802338786 ps
CPU time 13.12 seconds
Started Jun 09 12:23:54 PM PDT 24
Finished Jun 09 12:24:08 PM PDT 24
Peak memory 210920 kb
Host smart-be4c804a-4c11-4ac0-91dc-b5b7dceb64e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838463198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.838463198
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1171519339
Short name T391
Test name
Test status
Simulation time 2086812540 ps
CPU time 15.86 seconds
Started Jun 09 12:23:53 PM PDT 24
Finished Jun 09 12:24:10 PM PDT 24
Peak memory 210860 kb
Host smart-7e8389dc-c1b3-49e0-be22-f36065873851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171519339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1171519339
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3363526185
Short name T426
Test name
Test status
Simulation time 6056572637 ps
CPU time 16.7 seconds
Started Jun 09 12:24:01 PM PDT 24
Finished Jun 09 12:24:18 PM PDT 24
Peak memory 219372 kb
Host smart-81cd40fa-8008-46fd-a676-efc626c7147c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363526185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3363526185
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2044365386
Short name T109
Test name
Test status
Simulation time 284691309 ps
CPU time 37.64 seconds
Started Jun 09 12:23:54 PM PDT 24
Finished Jun 09 12:24:32 PM PDT 24
Peak memory 211072 kb
Host smart-0c8f5096-2b1a-41ee-afd1-0dc0b9124ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044365386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2044365386
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.182219923
Short name T397
Test name
Test status
Simulation time 1814923068 ps
CPU time 14.8 seconds
Started Jun 09 12:24:00 PM PDT 24
Finished Jun 09 12:24:16 PM PDT 24
Peak memory 219124 kb
Host smart-f6c4d49a-1391-4e8f-a728-b2e5b7ecc3ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182219923 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.182219923
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3132160788
Short name T404
Test name
Test status
Simulation time 572725987 ps
CPU time 7.55 seconds
Started Jun 09 12:23:55 PM PDT 24
Finished Jun 09 12:24:03 PM PDT 24
Peak memory 217816 kb
Host smart-40108d17-b9f3-4e6b-b280-f7db07b3f559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132160788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3132160788
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.17187971
Short name T463
Test name
Test status
Simulation time 1496441388 ps
CPU time 18.69 seconds
Started Jun 09 12:23:53 PM PDT 24
Finished Jun 09 12:24:12 PM PDT 24
Peak memory 210864 kb
Host smart-897a49c5-9908-4e40-88ba-2b76f4b034fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17187971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pass
thru_mem_tl_intg_err.17187971
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.992047278
Short name T55
Test name
Test status
Simulation time 4821038284 ps
CPU time 10.93 seconds
Started Jun 09 12:24:09 PM PDT 24
Finished Jun 09 12:24:20 PM PDT 24
Peak memory 210968 kb
Host smart-fe7eaba8-be77-4c1d-948b-61c5cc0ab2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992047278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.992047278
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1527327763
Short name T445
Test name
Test status
Simulation time 692901578 ps
CPU time 6.69 seconds
Started Jun 09 12:23:54 PM PDT 24
Finished Jun 09 12:24:02 PM PDT 24
Peak memory 218916 kb
Host smart-9ea98e40-1257-434b-af08-fa3612511def
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527327763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1527327763
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2860377132
Short name T52
Test name
Test status
Simulation time 2636126387 ps
CPU time 68.57 seconds
Started Jun 09 12:24:03 PM PDT 24
Finished Jun 09 12:25:12 PM PDT 24
Peak memory 211416 kb
Host smart-e3048bca-e013-40bb-b453-50008b6ef2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860377132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2860377132
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3575110535
Short name T390
Test name
Test status
Simulation time 8420186795 ps
CPU time 16.62 seconds
Started Jun 09 12:23:59 PM PDT 24
Finished Jun 09 12:24:17 PM PDT 24
Peak memory 219132 kb
Host smart-99381cb9-2e46-430c-ba61-edc5057004a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575110535 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3575110535
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3657644117
Short name T77
Test name
Test status
Simulation time 2078619985 ps
CPU time 16.07 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:24:24 PM PDT 24
Peak memory 210916 kb
Host smart-5d7a3d7e-5f49-4e55-b159-c32c3adde890
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657644117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3657644117
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3296694419
Short name T427
Test name
Test status
Simulation time 1606723127 ps
CPU time 32.51 seconds
Started Jun 09 12:23:55 PM PDT 24
Finished Jun 09 12:24:29 PM PDT 24
Peak memory 210848 kb
Host smart-14e4dc81-b330-4b34-9010-78e5af375535
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296694419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3296694419
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4072423209
Short name T64
Test name
Test status
Simulation time 2304134136 ps
CPU time 13.26 seconds
Started Jun 09 12:23:58 PM PDT 24
Finished Jun 09 12:24:12 PM PDT 24
Peak memory 210944 kb
Host smart-a8b2036a-6193-43fa-8586-7d22cdbea36e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072423209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4072423209
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1756785820
Short name T396
Test name
Test status
Simulation time 891198828 ps
CPU time 13.62 seconds
Started Jun 09 12:24:02 PM PDT 24
Finished Jun 09 12:24:16 PM PDT 24
Peak memory 218960 kb
Host smart-ed25b517-e8d7-43a0-ac32-d1d597b0c145
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756785820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1756785820
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3737448552
Short name T400
Test name
Test status
Simulation time 647096565 ps
CPU time 36.07 seconds
Started Jun 09 12:23:57 PM PDT 24
Finished Jun 09 12:24:34 PM PDT 24
Peak memory 212268 kb
Host smart-df99f4a3-c216-4096-b069-0375cbb90aab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737448552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3737448552
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2732847620
Short name T424
Test name
Test status
Simulation time 100133107 ps
CPU time 5.2 seconds
Started Jun 09 12:23:58 PM PDT 24
Finished Jun 09 12:24:04 PM PDT 24
Peak memory 215460 kb
Host smart-adea96e8-72df-452e-8b89-fa0b88c9ae33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732847620 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2732847620
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1755793939
Short name T434
Test name
Test status
Simulation time 4349076751 ps
CPU time 8.94 seconds
Started Jun 09 12:24:08 PM PDT 24
Finished Jun 09 12:24:17 PM PDT 24
Peak memory 219072 kb
Host smart-9bdb1174-6414-477f-a239-c1a62dce2649
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755793939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1755793939
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.837939742
Short name T421
Test name
Test status
Simulation time 15853460993 ps
CPU time 44.3 seconds
Started Jun 09 12:23:59 PM PDT 24
Finished Jun 09 12:24:44 PM PDT 24
Peak memory 210928 kb
Host smart-399c2cb9-bc88-4ffe-9ef3-8fabac4925c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837939742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.837939742
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.699758739
Short name T408
Test name
Test status
Simulation time 4255785080 ps
CPU time 17.09 seconds
Started Jun 09 12:24:05 PM PDT 24
Finished Jun 09 12:24:23 PM PDT 24
Peak memory 211008 kb
Host smart-7e32aa06-36d8-4f55-adc1-f9083485c89b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699758739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.699758739
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3327810166
Short name T394
Test name
Test status
Simulation time 1041569597 ps
CPU time 13.51 seconds
Started Jun 09 12:23:57 PM PDT 24
Finished Jun 09 12:24:12 PM PDT 24
Peak memory 218932 kb
Host smart-f9123448-5117-4460-b527-de9bebc3fc96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327810166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3327810166
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2129249625
Short name T464
Test name
Test status
Simulation time 19849195715 ps
CPU time 46.2 seconds
Started Jun 09 12:24:05 PM PDT 24
Finished Jun 09 12:24:52 PM PDT 24
Peak memory 219124 kb
Host smart-1ff537ce-4b61-4397-aa78-29163f93e222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129249625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2129249625
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2562876314
Short name T281
Test name
Test status
Simulation time 1001757141 ps
CPU time 7.69 seconds
Started Jun 09 12:27:48 PM PDT 24
Finished Jun 09 12:27:57 PM PDT 24
Peak memory 210756 kb
Host smart-29ccfc2c-7b87-4442-a182-2fd1484d8c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562876314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2562876314
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4140959054
Short name T319
Test name
Test status
Simulation time 59843573870 ps
CPU time 115.15 seconds
Started Jun 09 12:27:52 PM PDT 24
Finished Jun 09 12:29:47 PM PDT 24
Peak memory 237168 kb
Host smart-0c46442e-d681-4aba-af5e-c7e98bc10db6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140959054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4140959054
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2040681220
Short name T31
Test name
Test status
Simulation time 866790422 ps
CPU time 14.61 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:17 PM PDT 24
Peak memory 211608 kb
Host smart-4aa4e159-0853-4179-b635-b266e373ab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040681220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2040681220
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.343252056
Short name T23
Test name
Test status
Simulation time 274399906 ps
CPU time 52.06 seconds
Started Jun 09 12:27:53 PM PDT 24
Finished Jun 09 12:28:46 PM PDT 24
Peak memory 237092 kb
Host smart-39502c21-de93-43a9-92de-d340b62e2d48
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343252056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.343252056
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2947328933
Short name T344
Test name
Test status
Simulation time 423346857 ps
CPU time 10.13 seconds
Started Jun 09 12:28:12 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 212916 kb
Host smart-58044102-16a4-47bc-b082-2a970397c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947328933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2947328933
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4218061784
Short name T34
Test name
Test status
Simulation time 144640601 ps
CPU time 7.19 seconds
Started Jun 09 12:27:51 PM PDT 24
Finished Jun 09 12:27:58 PM PDT 24
Peak memory 210880 kb
Host smart-86e61101-01fe-4314-97de-badc0abc9675
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218061784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4218061784
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.718961742
Short name T151
Test name
Test status
Simulation time 1828827711 ps
CPU time 14.45 seconds
Started Jun 09 12:27:39 PM PDT 24
Finished Jun 09 12:27:54 PM PDT 24
Peak memory 210728 kb
Host smart-bb5b2d8d-8bbb-490e-ae62-b1057de13ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718961742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.718961742
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.329178690
Short name T270
Test name
Test status
Simulation time 27549184374 ps
CPU time 115.63 seconds
Started Jun 09 12:27:52 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 228088 kb
Host smart-fb76a7bb-6a70-4ffe-8581-583d0fbed13c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329178690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.329178690
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.336657425
Short name T45
Test name
Test status
Simulation time 6997950371 ps
CPU time 29.27 seconds
Started Jun 09 12:27:52 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 212816 kb
Host smart-d5442c58-0d00-4bd4-8ee5-4e7449cbbc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336657425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.336657425
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2436423172
Short name T161
Test name
Test status
Simulation time 1140150633 ps
CPU time 12.52 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 210928 kb
Host smart-19907bdc-23ea-4d42-b0bd-be0901afa741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436423172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2436423172
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3636470125
Short name T24
Test name
Test status
Simulation time 2740070395 ps
CPU time 57.34 seconds
Started Jun 09 12:27:52 PM PDT 24
Finished Jun 09 12:28:50 PM PDT 24
Peak memory 235000 kb
Host smart-ffc4e620-2775-4a66-aa34-6ad7bbe8bb32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636470125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3636470125
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2322489934
Short name T32
Test name
Test status
Simulation time 7724545936 ps
CPU time 32.09 seconds
Started Jun 09 12:28:21 PM PDT 24
Finished Jun 09 12:28:54 PM PDT 24
Peak memory 214720 kb
Host smart-0c11b0b5-18da-4c93-9dab-06349f683955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322489934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2322489934
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.316684619
Short name T166
Test name
Test status
Simulation time 128587411 ps
CPU time 6.36 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 210848 kb
Host smart-191dcd2b-b2ed-4259-8dd5-8a4b3d95887b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316684619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.316684619
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1862171532
Short name T280
Test name
Test status
Simulation time 7726321652 ps
CPU time 15.12 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:15 PM PDT 24
Peak memory 210852 kb
Host smart-39ed4e45-1dd0-4985-a8f0-647c573d08e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862171532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1862171532
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1235834250
Short name T221
Test name
Test status
Simulation time 8281113838 ps
CPU time 119.89 seconds
Started Jun 09 12:27:55 PM PDT 24
Finished Jun 09 12:29:55 PM PDT 24
Peak memory 224640 kb
Host smart-606fac55-dd5a-44e9-80c9-abc23ef1f211
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235834250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1235834250
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1024886642
Short name T28
Test name
Test status
Simulation time 1436194391 ps
CPU time 17.93 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:17 PM PDT 24
Peak memory 212756 kb
Host smart-3201d57f-1905-414e-a612-2251d810c52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024886642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1024886642
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.255033038
Short name T321
Test name
Test status
Simulation time 872204975 ps
CPU time 7.3 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:11 PM PDT 24
Peak memory 210876 kb
Host smart-af475af0-3e62-4c0b-830a-b15748ce8f9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255033038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.255033038
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3978908421
Short name T318
Test name
Test status
Simulation time 65276184800 ps
CPU time 33.84 seconds
Started Jun 09 12:27:56 PM PDT 24
Finished Jun 09 12:28:31 PM PDT 24
Peak memory 212656 kb
Host smart-be69cce9-89e7-4bdc-9f14-1f1bfed8b702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978908421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3978908421
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1630712271
Short name T240
Test name
Test status
Simulation time 2205378854 ps
CPU time 44.9 seconds
Started Jun 09 12:27:51 PM PDT 24
Finished Jun 09 12:28:36 PM PDT 24
Peak memory 214020 kb
Host smart-bf0f90e0-768d-4bc0-ba60-b2cdca65920f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630712271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1630712271
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.905636163
Short name T181
Test name
Test status
Simulation time 9227623970 ps
CPU time 11.12 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:11 PM PDT 24
Peak memory 210868 kb
Host smart-412e0751-cc2f-4c9d-9e31-44947a77e940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905636163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.905636163
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1999322199
Short name T119
Test name
Test status
Simulation time 221211223906 ps
CPU time 496.89 seconds
Started Jun 09 12:27:55 PM PDT 24
Finished Jun 09 12:36:13 PM PDT 24
Peak memory 212408 kb
Host smart-8dc6cb1c-ac3f-4ca6-98f8-ddb43414712f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999322199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1999322199
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2237909785
Short name T178
Test name
Test status
Simulation time 5883874575 ps
CPU time 26.89 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 211792 kb
Host smart-5b4856cc-f2f5-4813-be70-3de0211f63d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237909785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2237909785
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.521157248
Short name T209
Test name
Test status
Simulation time 1110861805 ps
CPU time 11.56 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:28:07 PM PDT 24
Peak memory 210920 kb
Host smart-2cfd81b3-a656-46bf-9f88-25945e4aeca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521157248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.521157248
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4247978274
Short name T328
Test name
Test status
Simulation time 23302503460 ps
CPU time 28.58 seconds
Started Jun 09 12:27:55 PM PDT 24
Finished Jun 09 12:28:24 PM PDT 24
Peak memory 213980 kb
Host smart-cd43fcc7-0c39-4657-b8b2-6366100e35be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247978274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4247978274
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2079355402
Short name T295
Test name
Test status
Simulation time 6437949869 ps
CPU time 77.63 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:29:21 PM PDT 24
Peak memory 216384 kb
Host smart-4632aed9-5116-4216-9002-a8945352539b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079355402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2079355402
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1963031508
Short name T154
Test name
Test status
Simulation time 347651924 ps
CPU time 4.2 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:04 PM PDT 24
Peak memory 210720 kb
Host smart-786df119-5c3a-4758-9c9e-b2fe0bed426d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963031508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1963031508
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2811655273
Short name T152
Test name
Test status
Simulation time 251729926 ps
CPU time 11.2 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:12 PM PDT 24
Peak memory 211556 kb
Host smart-d19ea924-0128-457f-93e9-956948db56b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811655273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2811655273
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3634729987
Short name T138
Test name
Test status
Simulation time 98147354 ps
CPU time 5.37 seconds
Started Jun 09 12:27:56 PM PDT 24
Finished Jun 09 12:28:02 PM PDT 24
Peak memory 210920 kb
Host smart-28885093-71c7-4cd8-ac73-08a2eddfa9fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634729987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3634729987
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3121137411
Short name T300
Test name
Test status
Simulation time 11259516537 ps
CPU time 25.49 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:24 PM PDT 24
Peak memory 213400 kb
Host smart-1791a0ff-0bad-4d88-aa94-cd465725b188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121137411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3121137411
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.262485976
Short name T125
Test name
Test status
Simulation time 14783824884 ps
CPU time 34.73 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:33 PM PDT 24
Peak memory 213768 kb
Host smart-0d059dbf-525a-4970-b2b1-5bda728eb9a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262485976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.262485976
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1936335874
Short name T256
Test name
Test status
Simulation time 7907578800 ps
CPU time 11.82 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:15 PM PDT 24
Peak memory 210792 kb
Host smart-e55f2c60-b1e8-4047-937a-a2033e974f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936335874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1936335874
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.565942701
Short name T89
Test name
Test status
Simulation time 16586649009 ps
CPU time 217.67 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:31:36 PM PDT 24
Peak memory 234552 kb
Host smart-93a71dd4-f916-44d8-964d-6ced7e71b8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565942701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.565942701
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1791715166
Short name T302
Test name
Test status
Simulation time 2467352104 ps
CPU time 12.51 seconds
Started Jun 09 12:28:05 PM PDT 24
Finished Jun 09 12:28:18 PM PDT 24
Peak memory 210984 kb
Host smart-f5f736d9-db2d-4ef8-a018-03e5122d3a53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791715166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1791715166
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2543430072
Short name T68
Test name
Test status
Simulation time 17182727736 ps
CPU time 34.76 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:37 PM PDT 24
Peak memory 213568 kb
Host smart-d1923804-d75a-4126-adde-478bb09bf655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543430072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2543430072
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2267133312
Short name T277
Test name
Test status
Simulation time 3854998648 ps
CPU time 33.71 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:35 PM PDT 24
Peak memory 216296 kb
Host smart-2a49df93-396a-4650-b188-5bf71f244a0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267133312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2267133312
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.1986609389
Short name T265
Test name
Test status
Simulation time 28679493869 ps
CPU time 1074.49 seconds
Started Jun 09 12:28:05 PM PDT 24
Finished Jun 09 12:46:00 PM PDT 24
Peak memory 228888 kb
Host smart-68eb041e-64a9-4030-9468-13e8f99170cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986609389 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.1986609389
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.339035868
Short name T243
Test name
Test status
Simulation time 781072869 ps
CPU time 9.02 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:12 PM PDT 24
Peak memory 210744 kb
Host smart-b0cb23a5-4b22-4fe6-80a9-d17538058cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339035868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.339035868
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.315985841
Short name T40
Test name
Test status
Simulation time 7327230186 ps
CPU time 101.92 seconds
Started Jun 09 12:28:33 PM PDT 24
Finished Jun 09 12:30:16 PM PDT 24
Peak memory 238548 kb
Host smart-9e6428c8-ca10-4525-be49-43c61dab0680
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315985841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.315985841
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3538202550
Short name T250
Test name
Test status
Simulation time 6868433188 ps
CPU time 19.79 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 211200 kb
Host smart-ab461310-6169-4dc8-8567-76ca2573d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538202550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3538202550
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1817500638
Short name T272
Test name
Test status
Simulation time 4999924917 ps
CPU time 9.83 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:12 PM PDT 24
Peak memory 211016 kb
Host smart-04018b32-0e44-4569-993c-603f3f146677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817500638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1817500638
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1374298666
Short name T74
Test name
Test status
Simulation time 14659126355 ps
CPU time 37.27 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:40 PM PDT 24
Peak memory 213888 kb
Host smart-4671d40b-22c3-4a52-97eb-b833aefc091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374298666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1374298666
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3396538987
Short name T213
Test name
Test status
Simulation time 3013455215 ps
CPU time 33.88 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:32 PM PDT 24
Peak memory 213432 kb
Host smart-f4d7cc69-658f-43b4-a929-82f06b3b9d18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396538987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3396538987
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2311662861
Short name T46
Test name
Test status
Simulation time 46613075137 ps
CPU time 1079.5 seconds
Started Jun 09 12:27:50 PM PDT 24
Finished Jun 09 12:45:50 PM PDT 24
Peak memory 234956 kb
Host smart-7e4265da-9fce-47ef-89b9-7fbdbff40d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311662861 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2311662861
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.857344265
Short name T187
Test name
Test status
Simulation time 430611712 ps
CPU time 5.61 seconds
Started Jun 09 12:28:22 PM PDT 24
Finished Jun 09 12:28:28 PM PDT 24
Peak memory 210748 kb
Host smart-0285ce3d-d005-4947-af53-ec13049f3e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857344265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.857344265
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.424741358
Short name T168
Test name
Test status
Simulation time 10641164603 ps
CPU time 153.06 seconds
Started Jun 09 12:28:35 PM PDT 24
Finished Jun 09 12:31:09 PM PDT 24
Peak memory 234560 kb
Host smart-c5ad96d2-fa7f-4845-baa0-cc83078b9622
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424741358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.424741358
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.177818573
Short name T282
Test name
Test status
Simulation time 1641967997 ps
CPU time 19.06 seconds
Started Jun 09 12:29:19 PM PDT 24
Finished Jun 09 12:29:38 PM PDT 24
Peak memory 211496 kb
Host smart-b15915ac-0fee-4945-bbb1-67028d3f1d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177818573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.177818573
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1091959009
Short name T128
Test name
Test status
Simulation time 2188170660 ps
CPU time 17.81 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 210984 kb
Host smart-ceece638-5439-4a5b-a397-7f3382330f7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091959009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1091959009
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1811634252
Short name T159
Test name
Test status
Simulation time 4778107243 ps
CPU time 28.69 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:31 PM PDT 24
Peak memory 213648 kb
Host smart-981b176e-c72e-4edb-9776-3750a6c3a8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811634252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1811634252
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1692555823
Short name T135
Test name
Test status
Simulation time 173631923 ps
CPU time 5.96 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:08 PM PDT 24
Peak memory 210428 kb
Host smart-b2de895b-55a4-4a16-9644-b5a10811b3b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692555823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1692555823
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1687187172
Short name T106
Test name
Test status
Simulation time 88864536076 ps
CPU time 672.99 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:39:11 PM PDT 24
Peak memory 230080 kb
Host smart-2e2e4d5a-a2ac-4c49-93f5-44efaa27450f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687187172 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1687187172
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4219495457
Short name T345
Test name
Test status
Simulation time 8936049314 ps
CPU time 15.65 seconds
Started Jun 09 12:27:51 PM PDT 24
Finished Jun 09 12:28:08 PM PDT 24
Peak memory 210860 kb
Host smart-a1fbcb1d-f84f-4f9e-9f01-52d67fec89e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219495457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4219495457
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2373163021
Short name T191
Test name
Test status
Simulation time 13655057684 ps
CPU time 147.03 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:31:28 PM PDT 24
Peak memory 236456 kb
Host smart-72ce62f5-f7f0-4eab-8fce-184713c76d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373163021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2373163021
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3145784679
Short name T215
Test name
Test status
Simulation time 7498803861 ps
CPU time 15.11 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:19 PM PDT 24
Peak memory 212124 kb
Host smart-3d32562c-993b-4b84-8c88-967469c2dc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145784679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3145784679
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1421996323
Short name T25
Test name
Test status
Simulation time 4062509927 ps
CPU time 13.95 seconds
Started Jun 09 12:28:07 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 210992 kb
Host smart-997518ea-8efa-4684-9dbd-34abf626d993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421996323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1421996323
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.785422809
Short name T105
Test name
Test status
Simulation time 3309862126 ps
CPU time 29.14 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:28:24 PM PDT 24
Peak memory 213004 kb
Host smart-4f798be3-9427-4878-b01b-b5d00114a86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785422809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.785422809
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2841070307
Short name T212
Test name
Test status
Simulation time 40277874054 ps
CPU time 96.29 seconds
Started Jun 09 12:28:34 PM PDT 24
Finished Jun 09 12:30:12 PM PDT 24
Peak memory 217104 kb
Host smart-013943b8-611d-4da5-b28c-d32472d4e751
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841070307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2841070307
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4206622653
Short name T356
Test name
Test status
Simulation time 4834667908 ps
CPU time 12.39 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:15 PM PDT 24
Peak memory 210824 kb
Host smart-11177988-e512-4502-a960-e0c41243fe77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206622653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4206622653
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1041713793
Short name T290
Test name
Test status
Simulation time 137598607555 ps
CPU time 342.18 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:33:42 PM PDT 24
Peak memory 237848 kb
Host smart-f5ef6c1b-4d57-4508-956a-cabe6a4d47a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041713793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1041713793
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.163017318
Short name T360
Test name
Test status
Simulation time 14046233635 ps
CPU time 31.32 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:33 PM PDT 24
Peak memory 211940 kb
Host smart-0a9a0e86-9827-456a-a031-0fb123765906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163017318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.163017318
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1534864001
Short name T294
Test name
Test status
Simulation time 997537980 ps
CPU time 11.31 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:16 PM PDT 24
Peak memory 210960 kb
Host smart-6d854188-070a-4445-9cb5-d10bc06bdc97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534864001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1534864001
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2751735853
Short name T72
Test name
Test status
Simulation time 3070190342 ps
CPU time 32.4 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:34 PM PDT 24
Peak memory 212196 kb
Host smart-168557a9-22bb-4731-acbd-a0aac4f4655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751735853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2751735853
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2825522620
Short name T130
Test name
Test status
Simulation time 6050873608 ps
CPU time 57.87 seconds
Started Jun 09 12:28:26 PM PDT 24
Finished Jun 09 12:29:25 PM PDT 24
Peak memory 216588 kb
Host smart-bc3f9341-900b-41dc-b128-0bfd667e23b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825522620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2825522620
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3502991292
Short name T131
Test name
Test status
Simulation time 2701812514 ps
CPU time 12.89 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:14 PM PDT 24
Peak memory 209544 kb
Host smart-3d9cd600-bf53-44dd-b8dc-4d8841d39156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502991292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3502991292
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4177476444
Short name T186
Test name
Test status
Simulation time 37678496740 ps
CPU time 345.82 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:33:49 PM PDT 24
Peak memory 213256 kb
Host smart-5ab1a0dd-c1cf-4d30-91ec-4111b8afb95c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177476444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4177476444
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2191970318
Short name T42
Test name
Test status
Simulation time 2368872063 ps
CPU time 9.13 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:10 PM PDT 24
Peak memory 210168 kb
Host smart-7319ae8f-8a98-4819-afec-52cda20957d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191970318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2191970318
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2804915844
Short name T202
Test name
Test status
Simulation time 9751132861 ps
CPU time 16.58 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:18 PM PDT 24
Peak memory 210452 kb
Host smart-58f5e7eb-0d94-4687-b266-257470df08a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804915844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2804915844
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4028144069
Short name T267
Test name
Test status
Simulation time 3948373713 ps
CPU time 30.65 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:32 PM PDT 24
Peak memory 211724 kb
Host smart-7c740523-bf79-454d-9b1c-f8ce830110f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028144069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4028144069
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2055457061
Short name T327
Test name
Test status
Simulation time 1698115849 ps
CPU time 20.82 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 214748 kb
Host smart-c0e1b949-8c62-4004-8e4d-ffb1e771501d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055457061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2055457061
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2418788291
Short name T326
Test name
Test status
Simulation time 156711209122 ps
CPU time 2728.31 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 01:14:30 PM PDT 24
Peak memory 248012 kb
Host smart-f6b3e90a-a6da-48e8-b11a-5474da596b31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418788291 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2418788291
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2978332484
Short name T201
Test name
Test status
Simulation time 173693372 ps
CPU time 5.44 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 210728 kb
Host smart-26a88ef4-4434-4033-9856-9eb35d0aa787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978332484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2978332484
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4031781609
Short name T162
Test name
Test status
Simulation time 42660781710 ps
CPU time 428.3 seconds
Started Jun 09 12:28:27 PM PDT 24
Finished Jun 09 12:35:36 PM PDT 24
Peak memory 235744 kb
Host smart-3e1d71dc-5844-46f4-846f-33241ddbcbff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031781609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4031781609
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.222570189
Short name T323
Test name
Test status
Simulation time 664714492 ps
CPU time 9.01 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:11 PM PDT 24
Peak memory 211212 kb
Host smart-20eda736-1db6-45cf-a204-fd24d5713ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222570189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.222570189
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1311232637
Short name T137
Test name
Test status
Simulation time 94503060 ps
CPU time 5.36 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:04 PM PDT 24
Peak memory 210920 kb
Host smart-db1d9799-1926-4b78-b6e3-e6eeba0273e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1311232637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1311232637
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.533110027
Short name T211
Test name
Test status
Simulation time 723040860 ps
CPU time 9.98 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:13 PM PDT 24
Peak memory 213008 kb
Host smart-4d8fdc02-9a0f-47ea-8e5b-4587895b9960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533110027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.533110027
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4253118497
Short name T316
Test name
Test status
Simulation time 555504411 ps
CPU time 20.12 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:18 PM PDT 24
Peak memory 213516 kb
Host smart-16d7cd6b-a0b4-4244-ac81-6db612a164aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253118497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4253118497
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2186611785
Short name T143
Test name
Test status
Simulation time 2230405419 ps
CPU time 10.89 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:08 PM PDT 24
Peak memory 210248 kb
Host smart-2dba929f-c49d-4146-a20a-56898f1114ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186611785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2186611785
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.93887962
Short name T188
Test name
Test status
Simulation time 9517624168 ps
CPU time 140.88 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:30:16 PM PDT 24
Peak memory 237536 kb
Host smart-b205659d-90f1-4361-9a93-d52ce213bf14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93887962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_cor
rupt_sig_fatal_chk.93887962
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.484840440
Short name T343
Test name
Test status
Simulation time 8782067495 ps
CPU time 32.74 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:32 PM PDT 24
Peak memory 212124 kb
Host smart-0c3bbdce-ebc1-4f80-9ef0-467da20f76d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484840440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.484840440
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3518245521
Short name T170
Test name
Test status
Simulation time 1735401988 ps
CPU time 14.99 seconds
Started Jun 09 12:27:52 PM PDT 24
Finished Jun 09 12:28:08 PM PDT 24
Peak memory 210916 kb
Host smart-e7a39022-a81f-4052-a1d7-f6934aa630a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518245521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3518245521
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1096321456
Short name T15
Test name
Test status
Simulation time 7097856499 ps
CPU time 55.16 seconds
Started Jun 09 12:28:10 PM PDT 24
Finished Jun 09 12:29:06 PM PDT 24
Peak memory 237428 kb
Host smart-57559545-3150-4fdf-8fc2-54c80aefbf9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096321456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1096321456
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.606909091
Short name T219
Test name
Test status
Simulation time 648905075 ps
CPU time 10.14 seconds
Started Jun 09 12:27:52 PM PDT 24
Finished Jun 09 12:28:03 PM PDT 24
Peak memory 213616 kb
Host smart-0e45a92a-6846-4afe-8507-8c7a8a5eeaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606909091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.606909091
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2264452126
Short name T329
Test name
Test status
Simulation time 1322413764 ps
CPU time 26.15 seconds
Started Jun 09 12:27:49 PM PDT 24
Finished Jun 09 12:28:16 PM PDT 24
Peak memory 216180 kb
Host smart-2591c118-b993-45c3-9a3a-a39a0584ad75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264452126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2264452126
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.469649213
Short name T338
Test name
Test status
Simulation time 41366988264 ps
CPU time 251.21 seconds
Started Jun 09 12:28:27 PM PDT 24
Finished Jun 09 12:32:39 PM PDT 24
Peak memory 237452 kb
Host smart-fbf4db79-cd92-4edd-9db7-7615d79f5722
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469649213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.469649213
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2892848072
Short name T279
Test name
Test status
Simulation time 4296513604 ps
CPU time 33.33 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:36 PM PDT 24
Peak memory 211712 kb
Host smart-34132cf1-fef1-4a06-afde-521f49e44578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892848072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2892848072
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1809258278
Short name T101
Test name
Test status
Simulation time 413598038 ps
CPU time 5.66 seconds
Started Jun 09 12:28:23 PM PDT 24
Finished Jun 09 12:28:29 PM PDT 24
Peak memory 210924 kb
Host smart-c88f50ce-af4b-4197-8d6e-dbe580979610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809258278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1809258278
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.245463897
Short name T132
Test name
Test status
Simulation time 748399543 ps
CPU time 10.11 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 213036 kb
Host smart-422bfa01-2777-40e4-8962-9bdfbaafb734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245463897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.245463897
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2705325647
Short name T340
Test name
Test status
Simulation time 554039945 ps
CPU time 28.08 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:32 PM PDT 24
Peak memory 213856 kb
Host smart-6e236f57-8a06-4a8f-8e3d-16db4a93bfce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705325647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2705325647
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.808996390
Short name T276
Test name
Test status
Simulation time 61097280659 ps
CPU time 1167.6 seconds
Started Jun 09 12:27:53 PM PDT 24
Finished Jun 09 12:47:22 PM PDT 24
Peak memory 231768 kb
Host smart-86752b6b-6f43-4110-be37-1c06b54ae155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808996390 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.808996390
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1793984221
Short name T301
Test name
Test status
Simulation time 5547823535 ps
CPU time 12.71 seconds
Started Jun 09 12:28:24 PM PDT 24
Finished Jun 09 12:28:37 PM PDT 24
Peak memory 210872 kb
Host smart-38efb42c-9b2c-4898-95bd-e1ee94fa8127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793984221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1793984221
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2087555658
Short name T220
Test name
Test status
Simulation time 108444102353 ps
CPU time 174.55 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:30:58 PM PDT 24
Peak memory 225336 kb
Host smart-7a3a1c78-6fc6-43c6-8038-9da3a716a047
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087555658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2087555658
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2500811742
Short name T353
Test name
Test status
Simulation time 171808848 ps
CPU time 9.32 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:14 PM PDT 24
Peak memory 211648 kb
Host smart-715f09ad-52b8-44be-a5a5-9c9f2296022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500811742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2500811742
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3269112978
Short name T333
Test name
Test status
Simulation time 1399833736 ps
CPU time 14.69 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:17 PM PDT 24
Peak memory 212020 kb
Host smart-0437dcfc-929c-4765-92d2-6729fcadd644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269112978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3269112978
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.925346705
Short name T347
Test name
Test status
Simulation time 752073694 ps
CPU time 21.98 seconds
Started Jun 09 12:28:24 PM PDT 24
Finished Jun 09 12:28:46 PM PDT 24
Peak memory 215340 kb
Host smart-9db53268-93a7-480f-9587-955c1bd6a2ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925346705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.925346705
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.623236047
Short name T317
Test name
Test status
Simulation time 9501409115 ps
CPU time 14.56 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:14 PM PDT 24
Peak memory 210868 kb
Host smart-1a4418a6-c41d-4281-9198-852eec59975f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623236047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.623236047
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.709112017
Short name T309
Test name
Test status
Simulation time 34680915571 ps
CPU time 373.66 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:34:11 PM PDT 24
Peak memory 237524 kb
Host smart-306b5586-b2e9-46a4-874a-c08cafeb8ef0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709112017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.709112017
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1475649341
Short name T21
Test name
Test status
Simulation time 168802965 ps
CPU time 9.53 seconds
Started Jun 09 12:28:35 PM PDT 24
Finished Jun 09 12:28:46 PM PDT 24
Peak memory 211584 kb
Host smart-e18bc010-e6f8-4c5a-b905-9e08ba6eb01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475649341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1475649341
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1074966965
Short name T293
Test name
Test status
Simulation time 3881580124 ps
CPU time 11.63 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:11 PM PDT 24
Peak memory 210960 kb
Host smart-644301d6-ccb4-46c9-8b21-581941908004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074966965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1074966965
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1345312696
Short name T264
Test name
Test status
Simulation time 941372891 ps
CPU time 10.29 seconds
Started Jun 09 12:27:52 PM PDT 24
Finished Jun 09 12:28:03 PM PDT 24
Peak memory 213764 kb
Host smart-362f2899-d325-4bf5-bff9-d1ba937ef09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345312696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1345312696
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.22699597
Short name T355
Test name
Test status
Simulation time 9993121046 ps
CPU time 26.98 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:29 PM PDT 24
Peak memory 215096 kb
Host smart-b87a882d-0fbe-4bea-bc53-621f47e505fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22699597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 22.rom_ctrl_stress_all.22699597
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2514370818
Short name T266
Test name
Test status
Simulation time 348319128 ps
CPU time 4.34 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:04 PM PDT 24
Peak memory 211052 kb
Host smart-aff499f4-bf05-4689-8d7e-b5d4ffaad903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514370818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2514370818
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.575740510
Short name T195
Test name
Test status
Simulation time 14712880987 ps
CPU time 163.04 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:30:43 PM PDT 24
Peak memory 224372 kb
Host smart-aea20e7e-7e75-45bd-90c8-65a97994b072
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575740510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.575740510
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2514119441
Short name T140
Test name
Test status
Simulation time 4134648223 ps
CPU time 32.76 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:33 PM PDT 24
Peak memory 212640 kb
Host smart-57860f92-d88d-47e8-9bd6-52f9fdc9eb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514119441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2514119441
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2633219028
Short name T172
Test name
Test status
Simulation time 430974217 ps
CPU time 8.38 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:07 PM PDT 24
Peak memory 210920 kb
Host smart-f315f33b-c1a6-40b6-a6a8-f7895a058884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633219028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2633219028
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1844677702
Short name T169
Test name
Test status
Simulation time 4359470613 ps
CPU time 38.33 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:39 PM PDT 24
Peak memory 213276 kb
Host smart-af163cec-4d66-4c0f-a121-857ce98ddfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844677702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1844677702
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1457473349
Short name T103
Test name
Test status
Simulation time 10720595061 ps
CPU time 29.34 seconds
Started Jun 09 12:28:14 PM PDT 24
Finished Jun 09 12:28:43 PM PDT 24
Peak memory 213628 kb
Host smart-7a8682d6-9716-40a2-8d98-d87bffe90ec1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457473349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1457473349
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2094678844
Short name T258
Test name
Test status
Simulation time 6628698560 ps
CPU time 256.26 seconds
Started Jun 09 12:27:51 PM PDT 24
Finished Jun 09 12:32:08 PM PDT 24
Peak memory 220592 kb
Host smart-7a0ff0d4-0c3d-4609-8431-b36c09880512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094678844 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2094678844
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3788063291
Short name T337
Test name
Test status
Simulation time 6117697448 ps
CPU time 16.8 seconds
Started Jun 09 12:28:19 PM PDT 24
Finished Jun 09 12:28:37 PM PDT 24
Peak memory 210856 kb
Host smart-436931b2-cd0d-448b-bc5b-55f5ed44b581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788063291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3788063291
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1295764619
Short name T120
Test name
Test status
Simulation time 94787872971 ps
CPU time 225.61 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:31:47 PM PDT 24
Peak memory 225324 kb
Host smart-0973a9de-7268-47a7-b220-f69c00dd957e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295764619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1295764619
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3756097798
Short name T234
Test name
Test status
Simulation time 2051041209 ps
CPU time 22.4 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:27 PM PDT 24
Peak memory 211520 kb
Host smart-c64f0d0f-5d09-4490-ab6c-43df1a21f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756097798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3756097798
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.779254798
Short name T165
Test name
Test status
Simulation time 367818712 ps
CPU time 5.63 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:11 PM PDT 24
Peak memory 210920 kb
Host smart-40e9af7c-fbd6-4c06-a5b1-e1ad61e11b24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=779254798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.779254798
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.720343920
Short name T71
Test name
Test status
Simulation time 189214982 ps
CPU time 10.25 seconds
Started Jun 09 12:28:26 PM PDT 24
Finished Jun 09 12:28:37 PM PDT 24
Peak memory 211788 kb
Host smart-4de537b5-d722-456e-b13f-385f982088cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720343920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.720343920
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3853251059
Short name T307
Test name
Test status
Simulation time 42034317679 ps
CPU time 99.07 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:29:39 PM PDT 24
Peak memory 219020 kb
Host smart-50862300-47da-40b2-b565-f71828a2b4c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853251059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3853251059
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.941403999
Short name T146
Test name
Test status
Simulation time 88887092 ps
CPU time 4.19 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:07 PM PDT 24
Peak memory 210744 kb
Host smart-53eef58f-5ecf-4a62-a866-22b277b35670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941403999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.941403999
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3997550624
Short name T269
Test name
Test status
Simulation time 16963381628 ps
CPU time 113.34 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:29:56 PM PDT 24
Peak memory 238336 kb
Host smart-98acdff0-fb73-4a75-a524-b53e1e596503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997550624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3997550624
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4084547384
Short name T274
Test name
Test status
Simulation time 183666289 ps
CPU time 5.51 seconds
Started Jun 09 12:28:11 PM PDT 24
Finished Jun 09 12:28:17 PM PDT 24
Peak memory 210928 kb
Host smart-62fd877e-1574-487e-bbbf-93d28e1d0e61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084547384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4084547384
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3431746342
Short name T29
Test name
Test status
Simulation time 711883759 ps
CPU time 10.28 seconds
Started Jun 09 12:27:56 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 213396 kb
Host smart-5069c82e-67ae-4f1b-bf4b-6b29e0ce06f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431746342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3431746342
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.74433125
Short name T124
Test name
Test status
Simulation time 3142265163 ps
CPU time 15.57 seconds
Started Jun 09 12:28:12 PM PDT 24
Finished Jun 09 12:28:28 PM PDT 24
Peak memory 210796 kb
Host smart-dcac1273-9608-47b5-8d8d-5d2e5d0b2115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74433125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.rom_ctrl_stress_all.74433125
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2720344550
Short name T19
Test name
Test status
Simulation time 6179329479 ps
CPU time 13.89 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:17 PM PDT 24
Peak memory 210860 kb
Host smart-b9ab9797-ae12-419e-ad57-5ab0c26144ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720344550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2720344550
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4017376328
Short name T37
Test name
Test status
Simulation time 43613767251 ps
CPU time 431.95 seconds
Started Jun 09 12:28:22 PM PDT 24
Finished Jun 09 12:35:34 PM PDT 24
Peak memory 211620 kb
Host smart-92e848e8-6b88-41ad-963e-615cd13534c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017376328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4017376328
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3093338839
Short name T314
Test name
Test status
Simulation time 340745641 ps
CPU time 9.6 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:13 PM PDT 24
Peak memory 211528 kb
Host smart-028839ec-2500-406f-b15a-2ab05e6647ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093338839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3093338839
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3139372767
Short name T197
Test name
Test status
Simulation time 7079086314 ps
CPU time 15.55 seconds
Started Jun 09 12:27:55 PM PDT 24
Finished Jun 09 12:28:11 PM PDT 24
Peak memory 211068 kb
Host smart-3f07d5a3-7c88-4399-b73e-a9f969cf24d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139372767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3139372767
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2140763802
Short name T284
Test name
Test status
Simulation time 3164337941 ps
CPU time 19.53 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:21 PM PDT 24
Peak memory 212904 kb
Host smart-7555189d-7107-4216-827e-289afdd6d52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140763802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2140763802
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3380552877
Short name T205
Test name
Test status
Simulation time 5966747955 ps
CPU time 39.35 seconds
Started Jun 09 12:27:56 PM PDT 24
Finished Jun 09 12:28:36 PM PDT 24
Peak memory 216736 kb
Host smart-503caddc-c587-44f1-93dc-b05852065d94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380552877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3380552877
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2207036168
Short name T275
Test name
Test status
Simulation time 216754848 ps
CPU time 5.3 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 210696 kb
Host smart-d5fa5a63-bf84-4aec-8133-b17dbde6aa98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207036168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2207036168
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.155450103
Short name T36
Test name
Test status
Simulation time 8434920975 ps
CPU time 214.99 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:31:37 PM PDT 24
Peak memory 212136 kb
Host smart-3757649f-a2ff-4738-bfb0-3a3a99f60b94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155450103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.155450103
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1556643296
Short name T144
Test name
Test status
Simulation time 12830961835 ps
CPU time 28.57 seconds
Started Jun 09 12:28:18 PM PDT 24
Finished Jun 09 12:28:47 PM PDT 24
Peak memory 211036 kb
Host smart-88131cfd-9ed8-4fb8-8527-a7e4dfd5e1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556643296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1556643296
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2737364593
Short name T83
Test name
Test status
Simulation time 3790697288 ps
CPU time 11.17 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:28:43 PM PDT 24
Peak memory 210984 kb
Host smart-25cf4633-e0c5-4dba-ad39-210067c2b876
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737364593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2737364593
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2046129200
Short name T182
Test name
Test status
Simulation time 41359439520 ps
CPU time 29.26 seconds
Started Jun 09 12:28:27 PM PDT 24
Finished Jun 09 12:28:57 PM PDT 24
Peak memory 214360 kb
Host smart-6094be24-a521-47b8-b1da-36e67a5e5285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046129200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2046129200
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3630064204
Short name T320
Test name
Test status
Simulation time 3377925079 ps
CPU time 17.68 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 214340 kb
Host smart-5c318348-35cf-4030-adef-9c13db1934bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630064204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3630064204
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4038108059
Short name T334
Test name
Test status
Simulation time 109455272018 ps
CPU time 1042.66 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:45:22 PM PDT 24
Peak memory 235492 kb
Host smart-cf86ef15-2af5-4f3e-8671-3026673d84a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038108059 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.4038108059
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1668143408
Short name T242
Test name
Test status
Simulation time 713508019 ps
CPU time 8.63 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:11 PM PDT 24
Peak memory 210728 kb
Host smart-898b3153-c0f2-4894-91b9-006c11a5a73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668143408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1668143408
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2891066249
Short name T348
Test name
Test status
Simulation time 194359881873 ps
CPU time 207.2 seconds
Started Jun 09 12:28:09 PM PDT 24
Finished Jun 09 12:31:37 PM PDT 24
Peak memory 212236 kb
Host smart-2b770d27-5709-4193-8953-a543dd041afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891066249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2891066249
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2509218710
Short name T251
Test name
Test status
Simulation time 3849234003 ps
CPU time 21.18 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 211560 kb
Host smart-6d7d04e8-641b-480c-9395-525d6d622d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509218710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2509218710
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2376486148
Short name T315
Test name
Test status
Simulation time 466201486 ps
CPU time 8.73 seconds
Started Jun 09 12:28:34 PM PDT 24
Finished Jun 09 12:28:44 PM PDT 24
Peak memory 210920 kb
Host smart-72c57cf6-6099-4d75-8cf2-179eb88e6e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376486148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2376486148
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1731365221
Short name T303
Test name
Test status
Simulation time 856070899 ps
CPU time 10.07 seconds
Started Jun 09 12:28:34 PM PDT 24
Finished Jun 09 12:28:45 PM PDT 24
Peak memory 213052 kb
Host smart-70b23247-6440-4455-8a15-4a8b56579378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731365221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1731365221
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1096288806
Short name T199
Test name
Test status
Simulation time 2424360507 ps
CPU time 35.79 seconds
Started Jun 09 12:28:26 PM PDT 24
Finished Jun 09 12:29:02 PM PDT 24
Peak memory 215156 kb
Host smart-be6b91b1-b5d6-4f64-82b7-5c3b2645e22b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096288806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1096288806
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.392835147
Short name T183
Test name
Test status
Simulation time 166555626943 ps
CPU time 1850.92 seconds
Started Jun 09 12:28:19 PM PDT 24
Finished Jun 09 12:59:11 PM PDT 24
Peak memory 235788 kb
Host smart-75eadeed-a73f-4cff-bf1c-29cb9958cf8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392835147 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.392835147
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1657151184
Short name T174
Test name
Test status
Simulation time 866776299 ps
CPU time 9.28 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:07 PM PDT 24
Peak memory 210728 kb
Host smart-2944470a-ee5d-4747-9dc9-05e82be1a0c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657151184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1657151184
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3984576671
Short name T203
Test name
Test status
Simulation time 25449992368 ps
CPU time 110.01 seconds
Started Jun 09 12:28:24 PM PDT 24
Finished Jun 09 12:30:15 PM PDT 24
Peak memory 228212 kb
Host smart-341c60f0-320b-414c-9048-4f51158a6aa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984576671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3984576671
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1612485051
Short name T164
Test name
Test status
Simulation time 12791208750 ps
CPU time 28.99 seconds
Started Jun 09 12:28:18 PM PDT 24
Finished Jun 09 12:28:48 PM PDT 24
Peak memory 217084 kb
Host smart-f71e2e87-324d-4124-9511-ee9217b374d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612485051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1612485051
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3208171847
Short name T123
Test name
Test status
Simulation time 102794863 ps
CPU time 5.72 seconds
Started Jun 09 12:28:25 PM PDT 24
Finished Jun 09 12:28:31 PM PDT 24
Peak memory 210916 kb
Host smart-50389b8b-b6f7-43fe-a2db-f1ac8f777cb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208171847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3208171847
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.143831256
Short name T163
Test name
Test status
Simulation time 496227117 ps
CPU time 12.39 seconds
Started Jun 09 12:28:34 PM PDT 24
Finished Jun 09 12:28:47 PM PDT 24
Peak memory 213292 kb
Host smart-a00dd848-9766-438d-889e-0679d52ffa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143831256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.143831256
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3631597367
Short name T27
Test name
Test status
Simulation time 111797852 ps
CPU time 7.36 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:11 PM PDT 24
Peak memory 210868 kb
Host smart-062bb36d-c685-473d-9bdb-7aa959ccc5ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631597367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3631597367
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3207060820
Short name T292
Test name
Test status
Simulation time 3640626859 ps
CPU time 8.77 seconds
Started Jun 09 12:28:22 PM PDT 24
Finished Jun 09 12:28:31 PM PDT 24
Peak memory 210828 kb
Host smart-e333d3e4-3606-4db8-88cc-0595d647f3ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207060820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3207060820
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4171839114
Short name T198
Test name
Test status
Simulation time 144114708748 ps
CPU time 285.6 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:32:41 PM PDT 24
Peak memory 212652 kb
Host smart-7e6b580d-0438-4dc8-80d3-cb4ba444491d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171839114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4171839114
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2389260246
Short name T20
Test name
Test status
Simulation time 5217154426 ps
CPU time 18.1 seconds
Started Jun 09 12:28:19 PM PDT 24
Finished Jun 09 12:28:38 PM PDT 24
Peak memory 211940 kb
Host smart-68bdf022-b48d-4206-92ed-80c8684601e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389260246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2389260246
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3053253930
Short name T263
Test name
Test status
Simulation time 3921581239 ps
CPU time 16.26 seconds
Started Jun 09 12:27:53 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 210984 kb
Host smart-d66247a0-f1be-4b6c-9d4f-b51f5c0a3d23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053253930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3053253930
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2184437348
Short name T225
Test name
Test status
Simulation time 8387618169 ps
CPU time 33.01 seconds
Started Jun 09 12:27:56 PM PDT 24
Finished Jun 09 12:28:29 PM PDT 24
Peak memory 214156 kb
Host smart-92d10dbd-0333-4069-8ee8-7147d63ce213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184437348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2184437348
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.879437114
Short name T253
Test name
Test status
Simulation time 62103859995 ps
CPU time 48.4 seconds
Started Jun 09 12:28:06 PM PDT 24
Finished Jun 09 12:28:54 PM PDT 24
Peak memory 219016 kb
Host smart-bcd90c24-cef8-4328-a8f5-4e843e16582c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879437114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.879437114
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3144275710
Short name T85
Test name
Test status
Simulation time 1179851550 ps
CPU time 4.24 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:08 PM PDT 24
Peak memory 210740 kb
Host smart-3dd60d5d-9373-4aaa-953c-fac1c4957353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144275710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3144275710
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2837063442
Short name T214
Test name
Test status
Simulation time 162168565727 ps
CPU time 390.49 seconds
Started Jun 09 12:28:39 PM PDT 24
Finished Jun 09 12:35:10 PM PDT 24
Peak memory 236732 kb
Host smart-cde6e07d-4867-4cfd-b95e-65af30949f0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837063442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2837063442
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3906319856
Short name T147
Test name
Test status
Simulation time 3305573411 ps
CPU time 29.89 seconds
Started Jun 09 12:27:53 PM PDT 24
Finished Jun 09 12:28:25 PM PDT 24
Peak memory 211456 kb
Host smart-3e5d5500-bdf2-45a1-92fa-5bd4e4ef73d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906319856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3906319856
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2542290082
Short name T122
Test name
Test status
Simulation time 137221026 ps
CPU time 6.43 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:05 PM PDT 24
Peak memory 210896 kb
Host smart-09c96ea0-b9b9-4973-920a-697518afc4ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542290082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2542290082
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1013066716
Short name T14
Test name
Test status
Simulation time 22650928929 ps
CPU time 28.17 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:32 PM PDT 24
Peak memory 214160 kb
Host smart-45c3d3b8-cddd-48e2-b12b-169d8af70e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013066716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1013066716
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.277126574
Short name T92
Test name
Test status
Simulation time 1139072547 ps
CPU time 30.94 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:31 PM PDT 24
Peak memory 215100 kb
Host smart-dd2b1562-f35b-407c-b25a-a730d115ac5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277126574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.277126574
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2840230382
Short name T90
Test name
Test status
Simulation time 4085838608 ps
CPU time 10.89 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 210788 kb
Host smart-4a6627ef-497f-46ff-86cd-88d22643ed30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840230382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2840230382
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2088670507
Short name T363
Test name
Test status
Simulation time 33356775239 ps
CPU time 341.46 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:33:43 PM PDT 24
Peak memory 212624 kb
Host smart-b66f821d-4540-43ba-b26f-4eca2a513fe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088670507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2088670507
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1460875300
Short name T43
Test name
Test status
Simulation time 341235264 ps
CPU time 9.46 seconds
Started Jun 09 12:28:38 PM PDT 24
Finished Jun 09 12:28:48 PM PDT 24
Peak memory 211284 kb
Host smart-ed08357b-9c26-4df8-b0b4-002cbe9cdeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460875300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1460875300
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2107614271
Short name T155
Test name
Test status
Simulation time 1686339598 ps
CPU time 15.84 seconds
Started Jun 09 12:27:50 PM PDT 24
Finished Jun 09 12:28:07 PM PDT 24
Peak memory 210896 kb
Host smart-b7ec217d-ce4a-4768-856b-1ba60a6ed91a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2107614271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2107614271
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3337207763
Short name T206
Test name
Test status
Simulation time 6417711136 ps
CPU time 16.77 seconds
Started Jun 09 12:28:35 PM PDT 24
Finished Jun 09 12:28:53 PM PDT 24
Peak memory 214056 kb
Host smart-bb51e1fe-682f-46fa-81d9-c8c5dcb548e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337207763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3337207763
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2544773192
Short name T104
Test name
Test status
Simulation time 14193773950 ps
CPU time 63.12 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:28:58 PM PDT 24
Peak memory 218996 kb
Host smart-75e303dc-6876-47cb-9e1f-9f418ef43fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544773192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2544773192
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2633233766
Short name T249
Test name
Test status
Simulation time 1841116520 ps
CPU time 14.68 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:18 PM PDT 24
Peak memory 210728 kb
Host smart-f8e31f3f-3c41-4ac4-92d5-47607c2da4f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633233766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2633233766
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1746601315
Short name T283
Test name
Test status
Simulation time 2199401862 ps
CPU time 128.95 seconds
Started Jun 09 12:28:18 PM PDT 24
Finished Jun 09 12:30:27 PM PDT 24
Peak memory 212376 kb
Host smart-4ff5ce8a-2e16-4ff6-bd56-167de3290b04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746601315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1746601315
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.994545509
Short name T189
Test name
Test status
Simulation time 2382558921 ps
CPU time 13.41 seconds
Started Jun 09 12:27:56 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 211632 kb
Host smart-8fad9ecc-a85e-4cee-b3a9-d1efc95f23d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994545509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.994545509
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4220513290
Short name T121
Test name
Test status
Simulation time 8195859208 ps
CPU time 17.88 seconds
Started Jun 09 12:28:17 PM PDT 24
Finished Jun 09 12:28:35 PM PDT 24
Peak memory 211024 kb
Host smart-b8af194d-2d57-4dc3-b553-a17df0200dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220513290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4220513290
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2107629836
Short name T196
Test name
Test status
Simulation time 2567825910 ps
CPU time 28.67 seconds
Started Jun 09 12:28:26 PM PDT 24
Finished Jun 09 12:28:55 PM PDT 24
Peak memory 213080 kb
Host smart-51cf9999-c09f-42fb-82ef-6e0a29a45060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107629836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2107629836
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3717259486
Short name T288
Test name
Test status
Simulation time 1253466153 ps
CPU time 12.13 seconds
Started Jun 09 12:28:14 PM PDT 24
Finished Jun 09 12:28:27 PM PDT 24
Peak memory 210736 kb
Host smart-142372fb-15af-4087-8deb-b92b9239e09d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717259486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3717259486
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3235851115
Short name T231
Test name
Test status
Simulation time 1398856040 ps
CPU time 12.95 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:14 PM PDT 24
Peak memory 210628 kb
Host smart-b9746a9d-fd38-4820-8107-82fe4250b633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235851115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3235851115
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.920970877
Short name T330
Test name
Test status
Simulation time 9332985176 ps
CPU time 135.93 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:30:18 PM PDT 24
Peak memory 232436 kb
Host smart-a1b44bfc-427d-49d8-b603-39e106403dc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920970877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.920970877
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2183703960
Short name T260
Test name
Test status
Simulation time 1526725483 ps
CPU time 18.81 seconds
Started Jun 09 12:27:56 PM PDT 24
Finished Jun 09 12:28:15 PM PDT 24
Peak memory 211636 kb
Host smart-410efab3-6a90-4c62-9669-ab7f9295b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183703960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2183703960
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3086827240
Short name T223
Test name
Test status
Simulation time 7364828844 ps
CPU time 14.9 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:19 PM PDT 24
Peak memory 211044 kb
Host smart-aabb6ebd-cecb-4c1a-8ca1-d126b40799f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086827240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3086827240
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1844819390
Short name T70
Test name
Test status
Simulation time 2545459992 ps
CPU time 21.38 seconds
Started Jun 09 12:28:34 PM PDT 24
Finished Jun 09 12:28:57 PM PDT 24
Peak memory 213256 kb
Host smart-4550299c-124e-4a91-8cdf-d93eed87582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844819390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1844819390
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3271691897
Short name T245
Test name
Test status
Simulation time 628462010 ps
CPU time 39.78 seconds
Started Jun 09 12:28:35 PM PDT 24
Finished Jun 09 12:29:16 PM PDT 24
Peak memory 214672 kb
Host smart-1a301826-1ee9-4c6e-9ac7-301b42faef96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271691897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3271691897
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2461706233
Short name T50
Test name
Test status
Simulation time 45805474228 ps
CPU time 1725.09 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:56:49 PM PDT 24
Peak memory 235492 kb
Host smart-9cc1f471-4f50-4886-9078-1f5699cb8e2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461706233 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2461706233
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1131649018
Short name T88
Test name
Test status
Simulation time 3480989724 ps
CPU time 9.79 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:14 PM PDT 24
Peak memory 210772 kb
Host smart-9b249bed-2ecf-4a8e-a3e9-54b3cc6f46af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131649018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1131649018
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4014616286
Short name T236
Test name
Test status
Simulation time 75951730538 ps
CPU time 393.11 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:35:05 PM PDT 24
Peak memory 228284 kb
Host smart-3b85276d-a593-44b6-87da-821816a3f57a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014616286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4014616286
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.879902988
Short name T247
Test name
Test status
Simulation time 723606826 ps
CPU time 9.4 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:14 PM PDT 24
Peak memory 211532 kb
Host smart-44cebee7-c08f-4c49-a09d-af956e349cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879902988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.879902988
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1383009725
Short name T325
Test name
Test status
Simulation time 6588297269 ps
CPU time 10.64 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:15 PM PDT 24
Peak memory 211044 kb
Host smart-e8eea0a6-a469-4b36-b6f8-56e527ca0df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383009725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1383009725
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.893202180
Short name T342
Test name
Test status
Simulation time 2642381546 ps
CPU time 30.28 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:34 PM PDT 24
Peak memory 213180 kb
Host smart-bbf32224-9ab7-45b2-92ce-08063c6da03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893202180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.893202180
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.235714764
Short name T310
Test name
Test status
Simulation time 770012707 ps
CPU time 41.58 seconds
Started Jun 09 12:28:08 PM PDT 24
Finished Jun 09 12:28:50 PM PDT 24
Peak memory 214780 kb
Host smart-ee6f57bb-5593-4f6e-b79e-687bf51f7671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235714764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.235714764
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3627670524
Short name T324
Test name
Test status
Simulation time 7964530326 ps
CPU time 18.18 seconds
Started Jun 09 12:28:36 PM PDT 24
Finished Jun 09 12:28:55 PM PDT 24
Peak memory 210880 kb
Host smart-fe2244ee-56c4-4c07-9a93-85abbbf15fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627670524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3627670524
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3719253502
Short name T306
Test name
Test status
Simulation time 2447532443 ps
CPU time 89.39 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:29:30 PM PDT 24
Peak memory 237440 kb
Host smart-57710a4e-95c3-4f9b-a916-dffe71b73338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719253502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3719253502
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3320021021
Short name T299
Test name
Test status
Simulation time 21365543605 ps
CPU time 23.25 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:28:55 PM PDT 24
Peak memory 211856 kb
Host smart-1b856fc9-a019-4eda-8148-e1e6905f6065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320021021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3320021021
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4190941658
Short name T241
Test name
Test status
Simulation time 363987302 ps
CPU time 5.56 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:08 PM PDT 24
Peak memory 210900 kb
Host smart-47bb5bb0-bfea-4662-b611-1fd79297abf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190941658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4190941658
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2432271485
Short name T336
Test name
Test status
Simulation time 4720447360 ps
CPU time 24.77 seconds
Started Jun 09 12:28:09 PM PDT 24
Finished Jun 09 12:28:34 PM PDT 24
Peak memory 213096 kb
Host smart-5b882cd6-bf83-4737-ab28-cd053ce18609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432271485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2432271485
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2088588548
Short name T312
Test name
Test status
Simulation time 25346805881 ps
CPU time 57.87 seconds
Started Jun 09 12:28:04 PM PDT 24
Finished Jun 09 12:29:03 PM PDT 24
Peak memory 213920 kb
Host smart-5bcfab32-04ba-44b4-9e9c-5d207fe97a29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088588548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2088588548
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3087381890
Short name T176
Test name
Test status
Simulation time 18546910448 ps
CPU time 16.42 seconds
Started Jun 09 12:28:05 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 210860 kb
Host smart-45859606-b439-45ad-94f5-4dc46920c010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087381890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3087381890
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2480201688
Short name T233
Test name
Test status
Simulation time 111634121339 ps
CPU time 287.89 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:32:54 PM PDT 24
Peak memory 240568 kb
Host smart-45508b3c-65c9-425f-a188-60a9c93d8ec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480201688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2480201688
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.834383325
Short name T259
Test name
Test status
Simulation time 26939518654 ps
CPU time 26.35 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:27 PM PDT 24
Peak memory 211864 kb
Host smart-db91798e-a67e-4b17-aef0-fca667ea05c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834383325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.834383325
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1797063200
Short name T139
Test name
Test status
Simulation time 137284822 ps
CPU time 6.33 seconds
Started Jun 09 12:28:20 PM PDT 24
Finished Jun 09 12:28:26 PM PDT 24
Peak memory 210892 kb
Host smart-5dc8d2d2-5b6f-4fa0-88c8-fd72b333b240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797063200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1797063200
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2134126244
Short name T271
Test name
Test status
Simulation time 652987076 ps
CPU time 10.23 seconds
Started Jun 09 12:28:34 PM PDT 24
Finished Jun 09 12:28:45 PM PDT 24
Peak memory 212988 kb
Host smart-08fe3f6f-b46e-456e-b529-062dd8805b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134126244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2134126244
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2036462087
Short name T87
Test name
Test status
Simulation time 4911833604 ps
CPU time 33.22 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:31 PM PDT 24
Peak memory 213660 kb
Host smart-dd6129a4-7f5f-4cba-8a01-dceed49db640
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036462087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2036462087
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.285400695
Short name T232
Test name
Test status
Simulation time 7600846662 ps
CPU time 14.23 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:28:46 PM PDT 24
Peak memory 210868 kb
Host smart-5b221dd9-6c67-4880-9ea7-769776392180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285400695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.285400695
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1074501326
Short name T84
Test name
Test status
Simulation time 3738472698 ps
CPU time 95.63 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:29:40 PM PDT 24
Peak memory 237492 kb
Host smart-7b9d7404-fb06-4b54-90f4-a42a3be18b19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074501326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1074501326
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.86076725
Short name T261
Test name
Test status
Simulation time 12089780298 ps
CPU time 27.03 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:28 PM PDT 24
Peak memory 212028 kb
Host smart-d9b53e05-4407-43bd-99b2-78262a685c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86076725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.86076725
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2237523444
Short name T351
Test name
Test status
Simulation time 4149730765 ps
CPU time 12.26 seconds
Started Jun 09 12:28:15 PM PDT 24
Finished Jun 09 12:28:27 PM PDT 24
Peak memory 210984 kb
Host smart-50dc5b4b-196d-441e-9aa9-4aa23a291a5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237523444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2237523444
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1907481389
Short name T244
Test name
Test status
Simulation time 294847949 ps
CPU time 19.28 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:24 PM PDT 24
Peak memory 212704 kb
Host smart-5d96da14-51c1-4187-bde0-f62337165247
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907481389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1907481389
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1978620107
Short name T278
Test name
Test status
Simulation time 455867835 ps
CPU time 7.31 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:28:02 PM PDT 24
Peak memory 210712 kb
Host smart-436e0f7d-9e85-4f37-a551-d99df006a86e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978620107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1978620107
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3843988857
Short name T335
Test name
Test status
Simulation time 664987198 ps
CPU time 9.64 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:09 PM PDT 24
Peak memory 211440 kb
Host smart-58fdaaff-d8e7-4830-b768-b7d337f2933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843988857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3843988857
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2852364021
Short name T289
Test name
Test status
Simulation time 5208625685 ps
CPU time 13.1 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:13 PM PDT 24
Peak memory 211032 kb
Host smart-1aeaf9bc-c3c3-4fb3-83f1-9eb05bc8787c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2852364021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2852364021
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.265766635
Short name T298
Test name
Test status
Simulation time 9542076369 ps
CPU time 20.69 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:19 PM PDT 24
Peak memory 213724 kb
Host smart-c1125cd2-bfb4-4f0c-bccf-f74970571c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265766635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.265766635
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3712808735
Short name T102
Test name
Test status
Simulation time 282052765 ps
CPU time 17.14 seconds
Started Jun 09 12:28:12 PM PDT 24
Finished Jun 09 12:28:30 PM PDT 24
Peak memory 214820 kb
Host smart-f8b34ed9-8028-4014-b9cb-ff901964f640
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712808735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3712808735
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4005385559
Short name T49
Test name
Test status
Simulation time 35867571731 ps
CPU time 558.73 seconds
Started Jun 09 12:28:20 PM PDT 24
Finished Jun 09 12:37:39 PM PDT 24
Peak memory 235484 kb
Host smart-6f3aef3b-b77f-44de-a873-362cf9280ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005385559 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4005385559
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1026361591
Short name T149
Test name
Test status
Simulation time 1331373604 ps
CPU time 12.21 seconds
Started Jun 09 12:28:20 PM PDT 24
Finished Jun 09 12:28:32 PM PDT 24
Peak memory 210728 kb
Host smart-1e4fc212-30e6-4afa-87d8-b8d98df6e1ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026361591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1026361591
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3450629734
Short name T13
Test name
Test status
Simulation time 2394977904 ps
CPU time 100.96 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:29:43 PM PDT 24
Peak memory 224264 kb
Host smart-65bc8b41-fba8-4529-b9f9-8a70eb8202cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450629734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3450629734
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4187250523
Short name T30
Test name
Test status
Simulation time 35503098095 ps
CPU time 29.83 seconds
Started Jun 09 12:28:35 PM PDT 24
Finished Jun 09 12:29:06 PM PDT 24
Peak memory 211820 kb
Host smart-3350b4d4-5dcd-4018-b0cd-7951b0980576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187250523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4187250523
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4287658293
Short name T208
Test name
Test status
Simulation time 4653694874 ps
CPU time 12.25 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:11 PM PDT 24
Peak memory 211044 kb
Host smart-6315630a-6fcf-492b-8605-a1218c7a67c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287658293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4287658293
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3041130673
Short name T193
Test name
Test status
Simulation time 3130374671 ps
CPU time 15.37 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:18 PM PDT 24
Peak memory 213152 kb
Host smart-5c8abe31-34b5-4c56-ba5e-7c6f503c85df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041130673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3041130673
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2854353683
Short name T204
Test name
Test status
Simulation time 5001303343 ps
CPU time 30.96 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:34 PM PDT 24
Peak memory 213968 kb
Host smart-12bacebb-c77b-4cbb-aa1f-e909d63ae388
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854353683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2854353683
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2701855894
Short name T349
Test name
Test status
Simulation time 4440711584 ps
CPU time 10.74 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:08 PM PDT 24
Peak memory 210248 kb
Host smart-ab94aaf0-7126-42ea-a917-6ba946e8e50f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701855894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2701855894
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.94418384
Short name T346
Test name
Test status
Simulation time 93613929623 ps
CPU time 306.78 seconds
Started Jun 09 12:28:18 PM PDT 24
Finished Jun 09 12:33:26 PM PDT 24
Peak memory 233664 kb
Host smart-c7fb7b7f-1d5b-4d4f-bc4d-11bcf0566411
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94418384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_cor
rupt_sig_fatal_chk.94418384
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1221088719
Short name T180
Test name
Test status
Simulation time 10085031444 ps
CPU time 22.73 seconds
Started Jun 09 12:27:53 PM PDT 24
Finished Jun 09 12:28:16 PM PDT 24
Peak memory 212228 kb
Host smart-bec092cd-d117-430d-971e-2c380a10fcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221088719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1221088719
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3623115773
Short name T99
Test name
Test status
Simulation time 1788219346 ps
CPU time 14.89 seconds
Started Jun 09 12:28:22 PM PDT 24
Finished Jun 09 12:28:37 PM PDT 24
Peak memory 210968 kb
Host smart-62046857-2ccd-44fb-9350-f793573ed6c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3623115773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3623115773
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1577868195
Short name T17
Test name
Test status
Simulation time 1174755781 ps
CPU time 59.49 seconds
Started Jun 09 12:27:53 PM PDT 24
Finished Jun 09 12:28:59 PM PDT 24
Peak memory 234960 kb
Host smart-3f7fca45-734c-43fb-a16e-0ea6c76c9b3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577868195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1577868195
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2372033180
Short name T354
Test name
Test status
Simulation time 9922672313 ps
CPU time 26.54 seconds
Started Jun 09 12:28:05 PM PDT 24
Finished Jun 09 12:28:32 PM PDT 24
Peak memory 213948 kb
Host smart-e7c00881-c1f1-4ee7-9e0b-16f9a12a91f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372033180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2372033180
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.234307182
Short name T142
Test name
Test status
Simulation time 24162207009 ps
CPU time 49.39 seconds
Started Jun 09 12:27:53 PM PDT 24
Finished Jun 09 12:28:43 PM PDT 24
Peak memory 216376 kb
Host smart-8f3a12f3-8c0b-4cf7-9b0c-83c58f083ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234307182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.234307182
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1072217162
Short name T200
Test name
Test status
Simulation time 78143925634 ps
CPU time 1140.35 seconds
Started Jun 09 12:28:04 PM PDT 24
Finished Jun 09 12:47:06 PM PDT 24
Peak memory 235492 kb
Host smart-4d093e28-cdf8-4976-99f3-08351076fce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072217162 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1072217162
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3543608911
Short name T173
Test name
Test status
Simulation time 6823869904 ps
CPU time 13.06 seconds
Started Jun 09 12:28:05 PM PDT 24
Finished Jun 09 12:28:19 PM PDT 24
Peak memory 210852 kb
Host smart-6fbc5202-6b19-495e-8ca8-9bb6b3eb1cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543608911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3543608911
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3670991928
Short name T39
Test name
Test status
Simulation time 5376026526 ps
CPU time 91.27 seconds
Started Jun 09 12:28:16 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 237180 kb
Host smart-c97cb6de-c910-481e-8239-ec3329cd32cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670991928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3670991928
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4206858666
Short name T255
Test name
Test status
Simulation time 1199981395 ps
CPU time 17.38 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:22 PM PDT 24
Peak memory 211472 kb
Host smart-ac7f617a-02cb-43e8-93d6-66479f973a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206858666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4206858666
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3074122515
Short name T238
Test name
Test status
Simulation time 7389924464 ps
CPU time 11.92 seconds
Started Jun 09 12:28:16 PM PDT 24
Finished Jun 09 12:28:29 PM PDT 24
Peak memory 211084 kb
Host smart-1f466e9d-4a2a-4829-b440-7dbce4b2d2f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074122515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3074122515
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1223752491
Short name T239
Test name
Test status
Simulation time 186754182 ps
CPU time 10.56 seconds
Started Jun 09 12:28:30 PM PDT 24
Finished Jun 09 12:28:41 PM PDT 24
Peak memory 213040 kb
Host smart-3a894873-ee7c-40b3-bcb2-aa65b91206e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223752491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1223752491
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.696345553
Short name T341
Test name
Test status
Simulation time 5091942275 ps
CPU time 61.28 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:29:05 PM PDT 24
Peak memory 219024 kb
Host smart-ba4e7ac4-e9e9-42b2-9d1c-65d9dd88d877
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696345553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.696345553
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.32288562
Short name T1
Test name
Test status
Simulation time 102655771443 ps
CPU time 876.74 seconds
Started Jun 09 12:28:35 PM PDT 24
Finished Jun 09 12:43:13 PM PDT 24
Peak memory 235516 kb
Host smart-1d34cbaa-8f70-497a-bef1-c9eea531c89a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32288562 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.32288562
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.14191260
Short name T262
Test name
Test status
Simulation time 3413818512 ps
CPU time 9.88 seconds
Started Jun 09 12:28:25 PM PDT 24
Finished Jun 09 12:28:35 PM PDT 24
Peak memory 210808 kb
Host smart-86676477-ac2b-4884-a234-f4bc29e18267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14191260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.14191260
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2530041580
Short name T207
Test name
Test status
Simulation time 169698361567 ps
CPU time 429.69 seconds
Started Jun 09 12:28:15 PM PDT 24
Finished Jun 09 12:35:26 PM PDT 24
Peak memory 233360 kb
Host smart-8b504b70-6b7c-477f-bd53-41771bd24a42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530041580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2530041580
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1837527508
Short name T226
Test name
Test status
Simulation time 35701862981 ps
CPU time 27.82 seconds
Started Jun 09 12:28:12 PM PDT 24
Finished Jun 09 12:28:41 PM PDT 24
Peak memory 212056 kb
Host smart-6d27615b-519e-4fd0-b0ad-eac4df5c2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837527508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1837527508
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1143821390
Short name T287
Test name
Test status
Simulation time 186479379 ps
CPU time 5.77 seconds
Started Jun 09 12:28:38 PM PDT 24
Finished Jun 09 12:28:44 PM PDT 24
Peak memory 210520 kb
Host smart-9d880f5b-d804-45ac-accd-5d0fe029777f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143821390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1143821390
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2452912823
Short name T73
Test name
Test status
Simulation time 185020504 ps
CPU time 10 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:13 PM PDT 24
Peak memory 213124 kb
Host smart-60c374be-16fd-4803-b316-897331a689b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452912823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2452912823
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2397125010
Short name T313
Test name
Test status
Simulation time 1268609655 ps
CPU time 27.97 seconds
Started Jun 09 12:28:10 PM PDT 24
Finished Jun 09 12:28:39 PM PDT 24
Peak memory 212920 kb
Host smart-44e7ed5e-b2b9-4221-b3d5-f2b8f1f9e2b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397125010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2397125010
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2572809435
Short name T145
Test name
Test status
Simulation time 7443618189 ps
CPU time 14.91 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:16 PM PDT 24
Peak memory 210664 kb
Host smart-2b72a4c0-30c4-4adc-bb2a-b7d8249658f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572809435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2572809435
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.499117305
Short name T190
Test name
Test status
Simulation time 102734185714 ps
CPU time 222.63 seconds
Started Jun 09 12:28:04 PM PDT 24
Finished Jun 09 12:31:48 PM PDT 24
Peak memory 232360 kb
Host smart-524948b9-2c33-4328-9d63-aeeb2f76b840
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499117305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.499117305
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.737422263
Short name T235
Test name
Test status
Simulation time 14348653237 ps
CPU time 28.07 seconds
Started Jun 09 12:28:18 PM PDT 24
Finished Jun 09 12:28:47 PM PDT 24
Peak memory 211936 kb
Host smart-67bc29cf-f5a8-4a57-81bd-3caafcdaae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737422263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.737422263
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3039190376
Short name T126
Test name
Test status
Simulation time 2611260949 ps
CPU time 13.34 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:18 PM PDT 24
Peak memory 210992 kb
Host smart-a3a4163e-0afe-4a0d-b236-298cb91b357d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3039190376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3039190376
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4090411803
Short name T58
Test name
Test status
Simulation time 15037948999 ps
CPU time 30.82 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:35 PM PDT 24
Peak memory 213996 kb
Host smart-5d3767e6-0b89-4e9c-8a52-fce3f90d6133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090411803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4090411803
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2253359101
Short name T156
Test name
Test status
Simulation time 9579667195 ps
CPU time 49.66 seconds
Started Jun 09 12:28:09 PM PDT 24
Finished Jun 09 12:28:59 PM PDT 24
Peak memory 219060 kb
Host smart-8e1562f3-01d0-4a4b-a391-a7daf2c44214
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253359101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2253359101
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3378267782
Short name T311
Test name
Test status
Simulation time 41407012268 ps
CPU time 5026.65 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 01:51:52 PM PDT 24
Peak memory 227316 kb
Host smart-ed4d9d3a-7a05-4b1e-aada-06832ff5b905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378267782 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3378267782
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3382924550
Short name T171
Test name
Test status
Simulation time 4393466271 ps
CPU time 11.36 seconds
Started Jun 09 12:28:13 PM PDT 24
Finished Jun 09 12:28:24 PM PDT 24
Peak memory 210852 kb
Host smart-16e28758-f7b8-45f5-9321-47fa66088a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382924550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3382924550
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4045091133
Short name T305
Test name
Test status
Simulation time 8613154550 ps
CPU time 141.07 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:30:24 PM PDT 24
Peak memory 237832 kb
Host smart-653c2f51-de43-4d76-8cca-146aa2aa5b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045091133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4045091133
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2920941780
Short name T308
Test name
Test status
Simulation time 489928232 ps
CPU time 13.07 seconds
Started Jun 09 12:28:23 PM PDT 24
Finished Jun 09 12:28:37 PM PDT 24
Peak memory 211564 kb
Host smart-ad939d90-7a1c-4727-b9ae-5933734a552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920941780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2920941780
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3730889399
Short name T237
Test name
Test status
Simulation time 369981001 ps
CPU time 5.46 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:05 PM PDT 24
Peak memory 210920 kb
Host smart-387a943f-c6b5-421b-8fbc-2d0a3aee9773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730889399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3730889399
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.591525502
Short name T331
Test name
Test status
Simulation time 1939438788 ps
CPU time 22.49 seconds
Started Jun 09 12:28:24 PM PDT 24
Finished Jun 09 12:28:47 PM PDT 24
Peak memory 213564 kb
Host smart-b35bc7c3-ebe8-48d3-bdf7-7db6b439a960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591525502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.591525502
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1848698319
Short name T304
Test name
Test status
Simulation time 106788397 ps
CPU time 8.69 seconds
Started Jun 09 12:28:09 PM PDT 24
Finished Jun 09 12:28:19 PM PDT 24
Peak memory 210728 kb
Host smart-63b90b4c-ab8d-4c7c-afa1-41e265e73b02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848698319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1848698319
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1612580406
Short name T175
Test name
Test status
Simulation time 2044286835 ps
CPU time 16.67 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:15 PM PDT 24
Peak memory 210728 kb
Host smart-ba2cf7c0-7d36-4c83-8537-03f7e7b106c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612580406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1612580406
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2642246179
Short name T268
Test name
Test status
Simulation time 29135543196 ps
CPU time 355.04 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:33:58 PM PDT 24
Peak memory 234836 kb
Host smart-042dafd7-94a0-40bc-8861-0b8d6e46af56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642246179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2642246179
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.277936734
Short name T339
Test name
Test status
Simulation time 7346528690 ps
CPU time 35.47 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:40 PM PDT 24
Peak memory 211940 kb
Host smart-84b29db9-8bc8-4826-9ced-67c8fd075931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277936734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.277936734
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1339292086
Short name T129
Test name
Test status
Simulation time 5059592038 ps
CPU time 13.32 seconds
Started Jun 09 12:28:35 PM PDT 24
Finished Jun 09 12:28:49 PM PDT 24
Peak memory 211052 kb
Host smart-d11d0fe1-247b-4f65-906c-b69db56f2809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339292086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1339292086
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2965853124
Short name T86
Test name
Test status
Simulation time 6688556290 ps
CPU time 19.36 seconds
Started Jun 09 12:28:06 PM PDT 24
Finished Jun 09 12:28:26 PM PDT 24
Peak memory 213232 kb
Host smart-4ce9d30f-04af-41a5-952c-920a64aaf639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965853124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2965853124
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2522722980
Short name T218
Test name
Test status
Simulation time 11991164938 ps
CPU time 34.83 seconds
Started Jun 09 12:28:02 PM PDT 24
Finished Jun 09 12:28:39 PM PDT 24
Peak memory 216604 kb
Host smart-edea1dce-adc0-430c-aa1f-ec4a1a16d4d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522722980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2522722980
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3632935507
Short name T362
Test name
Test status
Simulation time 2093049945 ps
CPU time 16.56 seconds
Started Jun 09 12:28:30 PM PDT 24
Finished Jun 09 12:28:47 PM PDT 24
Peak memory 210728 kb
Host smart-ad169db5-1f50-4e35-ba0f-719c2bdb2081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632935507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3632935507
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2145874403
Short name T358
Test name
Test status
Simulation time 2257103525 ps
CPU time 65.49 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:29:10 PM PDT 24
Peak memory 212148 kb
Host smart-8644815d-591e-4f66-a0f8-ff8b943cd4d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145874403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2145874403
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.53879396
Short name T26
Test name
Test status
Simulation time 32709644894 ps
CPU time 26.92 seconds
Started Jun 09 12:28:18 PM PDT 24
Finished Jun 09 12:28:45 PM PDT 24
Peak memory 212496 kb
Host smart-5c3fb292-1c1f-4f5d-8600-6d8408a9243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53879396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.53879396
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3109572671
Short name T136
Test name
Test status
Simulation time 1736623218 ps
CPU time 11.03 seconds
Started Jun 09 12:28:16 PM PDT 24
Finished Jun 09 12:28:28 PM PDT 24
Peak memory 210900 kb
Host smart-2689f1c0-4d32-43fd-addc-36af228ac504
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109572671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3109572671
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2374501943
Short name T133
Test name
Test status
Simulation time 9356847886 ps
CPU time 23.44 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:24 PM PDT 24
Peak memory 214280 kb
Host smart-226108b7-1dab-4b21-acd0-ac4e840126e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374501943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2374501943
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3735159760
Short name T9
Test name
Test status
Simulation time 10730471132 ps
CPU time 19.49 seconds
Started Jun 09 12:28:14 PM PDT 24
Finished Jun 09 12:28:34 PM PDT 24
Peak memory 210796 kb
Host smart-1e4f9a3d-834a-40e4-ba2f-aaefe819757c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735159760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3735159760
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1520865844
Short name T134
Test name
Test status
Simulation time 1940010221 ps
CPU time 15.01 seconds
Started Jun 09 12:28:07 PM PDT 24
Finished Jun 09 12:28:23 PM PDT 24
Peak memory 210768 kb
Host smart-ccd05732-4a57-41b6-b9c2-695318353609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520865844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1520865844
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.844464642
Short name T273
Test name
Test status
Simulation time 18692744998 ps
CPU time 125.88 seconds
Started Jun 09 12:28:16 PM PDT 24
Finished Jun 09 12:30:23 PM PDT 24
Peak memory 228280 kb
Host smart-5551a9be-4c76-4936-b240-0b8f1b1eeb27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844464642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.844464642
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2506918411
Short name T22
Test name
Test status
Simulation time 1454226326 ps
CPU time 18.5 seconds
Started Jun 09 12:28:20 PM PDT 24
Finished Jun 09 12:28:39 PM PDT 24
Peak memory 211532 kb
Host smart-63dfef43-ae74-4b49-a69c-415c11b13f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506918411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2506918411
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.371015703
Short name T150
Test name
Test status
Simulation time 4334727137 ps
CPU time 16.17 seconds
Started Jun 09 12:28:04 PM PDT 24
Finished Jun 09 12:28:21 PM PDT 24
Peak memory 211036 kb
Host smart-0fd2962d-732d-49f3-8c4f-7e835a467676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371015703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.371015703
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1323354493
Short name T216
Test name
Test status
Simulation time 7634139345 ps
CPU time 18.19 seconds
Started Jun 09 12:28:21 PM PDT 24
Finished Jun 09 12:28:40 PM PDT 24
Peak memory 214584 kb
Host smart-a5a3d43a-7037-430f-bd66-ccc9dde2ce58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323354493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1323354493
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2925519189
Short name T194
Test name
Test status
Simulation time 2327649687 ps
CPU time 30.88 seconds
Started Jun 09 12:28:22 PM PDT 24
Finished Jun 09 12:28:53 PM PDT 24
Peak memory 215516 kb
Host smart-9acd72ac-2539-483f-ac6e-d2c7055ccfd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925519189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2925519189
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3747769593
Short name T141
Test name
Test status
Simulation time 728887776 ps
CPU time 9.41 seconds
Started Jun 09 12:28:33 PM PDT 24
Finished Jun 09 12:28:44 PM PDT 24
Peak memory 210748 kb
Host smart-2ee7ed2c-0c33-452a-9ef0-210e37dd8fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747769593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3747769593
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2159375164
Short name T35
Test name
Test status
Simulation time 13272142542 ps
CPU time 252.52 seconds
Started Jun 09 12:28:27 PM PDT 24
Finished Jun 09 12:32:40 PM PDT 24
Peak memory 236488 kb
Host smart-72429d87-fa8a-445d-8f7b-ba3f6818f265
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159375164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2159375164
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2093984031
Short name T160
Test name
Test status
Simulation time 13000573738 ps
CPU time 28.55 seconds
Started Jun 09 12:28:23 PM PDT 24
Finished Jun 09 12:28:52 PM PDT 24
Peak memory 210976 kb
Host smart-dd3bedca-8a86-4aca-a897-4254f6a11c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093984031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2093984031
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1298107290
Short name T41
Test name
Test status
Simulation time 8662947678 ps
CPU time 11.29 seconds
Started Jun 09 12:28:30 PM PDT 24
Finished Jun 09 12:28:42 PM PDT 24
Peak memory 211044 kb
Host smart-471413c2-7773-44fc-8d5d-354df77429f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1298107290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1298107290
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2569758
Short name T296
Test name
Test status
Simulation time 6155423413 ps
CPU time 30.74 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:35 PM PDT 24
Peak memory 214252 kb
Host smart-a77ce4c3-1195-41dd-b39a-61e20bfc6db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2569758
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3835759927
Short name T222
Test name
Test status
Simulation time 10059526713 ps
CPU time 15.51 seconds
Started Jun 09 12:28:34 PM PDT 24
Finished Jun 09 12:28:51 PM PDT 24
Peak memory 210996 kb
Host smart-6e41b33e-dad1-48c0-bc14-a67e2b7087fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835759927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3835759927
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.488251137
Short name T18
Test name
Test status
Simulation time 346973684 ps
CPU time 5.39 seconds
Started Jun 09 12:28:34 PM PDT 24
Finished Jun 09 12:28:41 PM PDT 24
Peak memory 210720 kb
Host smart-9780c5a5-64bf-4671-a626-c69282804d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488251137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.488251137
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.718834962
Short name T33
Test name
Test status
Simulation time 144432885231 ps
CPU time 421.08 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:35:33 PM PDT 24
Peak memory 233508 kb
Host smart-3524181f-c2e2-4e53-9346-d18d436c7515
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718834962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.718834962
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1253024599
Short name T359
Test name
Test status
Simulation time 3980404253 ps
CPU time 33.49 seconds
Started Jun 09 12:28:27 PM PDT 24
Finished Jun 09 12:29:01 PM PDT 24
Peak memory 211480 kb
Host smart-968f992c-ae34-45d7-a891-0cc092d6d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253024599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1253024599
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.497932870
Short name T291
Test name
Test status
Simulation time 159196839 ps
CPU time 5.81 seconds
Started Jun 09 12:28:27 PM PDT 24
Finished Jun 09 12:28:33 PM PDT 24
Peak memory 210904 kb
Host smart-c3904944-d9fc-4281-a9fc-65ea3e75ca30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497932870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.497932870
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.504469717
Short name T350
Test name
Test status
Simulation time 733573012 ps
CPU time 10.06 seconds
Started Jun 09 12:28:18 PM PDT 24
Finished Jun 09 12:28:29 PM PDT 24
Peak memory 213692 kb
Host smart-ebee4b5c-7d98-4a1f-b060-443d664bee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504469717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.504469717
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3591645678
Short name T228
Test name
Test status
Simulation time 1611157709 ps
CPU time 21.92 seconds
Started Jun 09 12:28:09 PM PDT 24
Finished Jun 09 12:28:32 PM PDT 24
Peak memory 215104 kb
Host smart-88de5b66-5f07-4203-86f3-27c9190ee676
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591645678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3591645678
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2914909254
Short name T47
Test name
Test status
Simulation time 164886757870 ps
CPU time 6532.72 seconds
Started Jun 09 12:28:28 PM PDT 24
Finished Jun 09 02:17:22 PM PDT 24
Peak memory 260076 kb
Host smart-00966b50-ea87-45b3-a2a3-3651fae16375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914909254 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2914909254
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3434774695
Short name T229
Test name
Test status
Simulation time 4198717521 ps
CPU time 16.97 seconds
Started Jun 09 12:28:13 PM PDT 24
Finished Jun 09 12:28:31 PM PDT 24
Peak memory 210784 kb
Host smart-be504018-a7ee-4a68-97b8-bcef25155374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434774695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3434774695
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1279421170
Short name T285
Test name
Test status
Simulation time 2313604266 ps
CPU time 149.17 seconds
Started Jun 09 12:28:29 PM PDT 24
Finished Jun 09 12:30:59 PM PDT 24
Peak memory 236760 kb
Host smart-ca189a21-8f49-4593-90ef-6e772767feb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279421170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1279421170
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4018086041
Short name T254
Test name
Test status
Simulation time 12574733774 ps
CPU time 28.68 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:29:00 PM PDT 24
Peak memory 212012 kb
Host smart-1e3bec9f-294b-4ac1-b884-5a419d21a1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018086041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4018086041
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1270270823
Short name T248
Test name
Test status
Simulation time 2018821411 ps
CPU time 17.11 seconds
Started Jun 09 12:28:32 PM PDT 24
Finished Jun 09 12:28:50 PM PDT 24
Peak memory 210948 kb
Host smart-a38a5f6d-6da7-4c96-9d78-2d12f265bb20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1270270823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1270270823
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2408828755
Short name T192
Test name
Test status
Simulation time 5680369651 ps
CPU time 27.33 seconds
Started Jun 09 12:28:30 PM PDT 24
Finished Jun 09 12:28:58 PM PDT 24
Peak memory 213688 kb
Host smart-08b5fd24-f923-48c3-b4de-d5c8675ad344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408828755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2408828755
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3495663171
Short name T179
Test name
Test status
Simulation time 280674551 ps
CPU time 16.45 seconds
Started Jun 09 12:28:28 PM PDT 24
Finished Jun 09 12:28:45 PM PDT 24
Peak memory 213420 kb
Host smart-3e948f0d-3636-4bba-9ab6-95a0b65b45b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495663171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3495663171
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2235053340
Short name T153
Test name
Test status
Simulation time 174995122 ps
CPU time 4.22 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:28:01 PM PDT 24
Peak memory 210720 kb
Host smart-204a83ee-1ca7-4688-992a-5be683110263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235053340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2235053340
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3263938900
Short name T361
Test name
Test status
Simulation time 27253865707 ps
CPU time 245.54 seconds
Started Jun 09 12:27:53 PM PDT 24
Finished Jun 09 12:31:59 PM PDT 24
Peak memory 212232 kb
Host smart-3b136065-9593-4edf-9b16-e6f09b039a84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263938900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3263938900
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3790144696
Short name T286
Test name
Test status
Simulation time 1274547244 ps
CPU time 9.5 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 211712 kb
Host smart-8adefe58-4abf-4ab8-8ebb-2165d51498d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790144696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3790144696
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.18555423
Short name T158
Test name
Test status
Simulation time 766466498 ps
CPU time 5.25 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:04 PM PDT 24
Peak memory 210868 kb
Host smart-e93913d5-8893-486c-a0da-f9d9c40afb8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18555423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.18555423
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.672367055
Short name T352
Test name
Test status
Simulation time 357713076 ps
CPU time 10.13 seconds
Started Jun 09 12:27:53 PM PDT 24
Finished Jun 09 12:28:04 PM PDT 24
Peak memory 213604 kb
Host smart-a826dab0-123a-459d-b197-8bcd233c9f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672367055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.672367055
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.71061814
Short name T157
Test name
Test status
Simulation time 2431248958 ps
CPU time 15.51 seconds
Started Jun 09 12:27:55 PM PDT 24
Finished Jun 09 12:28:15 PM PDT 24
Peak memory 210780 kb
Host smart-fa51a272-d432-447e-a667-565a39cb3bbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71061814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.rom_ctrl_stress_all.71061814
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4285066876
Short name T184
Test name
Test status
Simulation time 2079527850 ps
CPU time 7.69 seconds
Started Jun 09 12:28:05 PM PDT 24
Finished Jun 09 12:28:13 PM PDT 24
Peak memory 210612 kb
Host smart-1326051c-aed2-436b-9670-52c233550604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285066876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4285066876
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1101725256
Short name T217
Test name
Test status
Simulation time 23348092387 ps
CPU time 213.62 seconds
Started Jun 09 12:27:56 PM PDT 24
Finished Jun 09 12:31:30 PM PDT 24
Peak memory 239304 kb
Host smart-4d7df702-d62e-4012-b70c-3bb353348e5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101725256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1101725256
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4147746961
Short name T332
Test name
Test status
Simulation time 18636454084 ps
CPU time 34.56 seconds
Started Jun 09 12:27:49 PM PDT 24
Finished Jun 09 12:28:24 PM PDT 24
Peak memory 210968 kb
Host smart-4f646a3c-05ae-4df4-988c-04ca497ed7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147746961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4147746961
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3903110515
Short name T2
Test name
Test status
Simulation time 1984604900 ps
CPU time 16.56 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:17 PM PDT 24
Peak memory 210920 kb
Host smart-e8130e76-1ac9-468d-b251-eafc8ec34fbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903110515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3903110515
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4240944227
Short name T5
Test name
Test status
Simulation time 830593613 ps
CPU time 10.3 seconds
Started Jun 09 12:28:31 PM PDT 24
Finished Jun 09 12:28:42 PM PDT 24
Peak memory 212572 kb
Host smart-4f0921d2-7ff8-48f9-952a-a7a60ef88731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240944227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4240944227
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3958911823
Short name T91
Test name
Test status
Simulation time 1783362873 ps
CPU time 19.52 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:28:19 PM PDT 24
Peak memory 211520 kb
Host smart-ae02086d-b554-42ea-9206-5874bc55cae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958911823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3958911823
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3658841569
Short name T44
Test name
Test status
Simulation time 33421266959 ps
CPU time 4009.4 seconds
Started Jun 09 12:28:04 PM PDT 24
Finished Jun 09 01:34:55 PM PDT 24
Peak memory 229396 kb
Host smart-d0773ad9-8954-41fa-b44c-9ed339950ffd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658841569 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3658841569
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.565677503
Short name T257
Test name
Test status
Simulation time 4272894245 ps
CPU time 11.25 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:16 PM PDT 24
Peak memory 210800 kb
Host smart-4a1aece6-ce7f-4b40-bfe1-9cc73ff245b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565677503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.565677503
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3175259057
Short name T357
Test name
Test status
Simulation time 14246471955 ps
CPU time 110.83 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:29:51 PM PDT 24
Peak memory 236468 kb
Host smart-b50153cc-c886-42f8-ae6f-917feb5f50a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175259057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3175259057
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1035760875
Short name T224
Test name
Test status
Simulation time 15423352622 ps
CPU time 31.71 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:28:27 PM PDT 24
Peak memory 211864 kb
Host smart-89451dde-7814-41fc-bf04-1f2992c83ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035760875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1035760875
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.467353535
Short name T4
Test name
Test status
Simulation time 104571442 ps
CPU time 5.66 seconds
Started Jun 09 12:28:12 PM PDT 24
Finished Jun 09 12:28:18 PM PDT 24
Peak memory 210920 kb
Host smart-8a7daee2-9c2e-4e73-aa7f-29aaa276f608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467353535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.467353535
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.592851517
Short name T167
Test name
Test status
Simulation time 1373602637 ps
CPU time 12.55 seconds
Started Jun 09 12:28:15 PM PDT 24
Finished Jun 09 12:28:29 PM PDT 24
Peak memory 213236 kb
Host smart-f67e06c4-2a89-4797-9099-a823899b2a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592851517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.592851517
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2356053189
Short name T227
Test name
Test status
Simulation time 4308988798 ps
CPU time 36.49 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 12:28:36 PM PDT 24
Peak memory 214244 kb
Host smart-2359e00b-0d75-40a5-aebf-02e9f71e42e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356053189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2356053189
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3916563418
Short name T11
Test name
Test status
Simulation time 389916115982 ps
CPU time 8334.14 seconds
Started Jun 09 12:27:59 PM PDT 24
Finished Jun 09 02:47:00 PM PDT 24
Peak memory 233292 kb
Host smart-b68a4375-d13e-4721-899a-0c36636cf864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916563418 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3916563418
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1163810008
Short name T57
Test name
Test status
Simulation time 340863130 ps
CPU time 6.68 seconds
Started Jun 09 12:28:13 PM PDT 24
Finished Jun 09 12:28:20 PM PDT 24
Peak memory 210700 kb
Host smart-ed45693f-07ca-493e-9961-52e64f6d6405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163810008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1163810008
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1752143979
Short name T10
Test name
Test status
Simulation time 1810449272 ps
CPU time 108.25 seconds
Started Jun 09 12:27:57 PM PDT 24
Finished Jun 09 12:29:46 PM PDT 24
Peak memory 233524 kb
Host smart-d8f65eff-b9ca-4432-8db9-eb5e3ba64e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752143979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1752143979
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1686024736
Short name T185
Test name
Test status
Simulation time 341599325 ps
CPU time 9.34 seconds
Started Jun 09 12:27:55 PM PDT 24
Finished Jun 09 12:28:05 PM PDT 24
Peak memory 211464 kb
Host smart-3b4e5ac5-73cf-47b2-928c-c6a84ccd4e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686024736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1686024736
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2559446684
Short name T297
Test name
Test status
Simulation time 838575284 ps
CPU time 5.69 seconds
Started Jun 09 12:28:03 PM PDT 24
Finished Jun 09 12:28:10 PM PDT 24
Peak memory 210876 kb
Host smart-fbfbf4c6-ac94-402c-9f80-32d2c6a5e30e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559446684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2559446684
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3738628395
Short name T127
Test name
Test status
Simulation time 2555431053 ps
CPU time 18.03 seconds
Started Jun 09 12:28:36 PM PDT 24
Finished Jun 09 12:28:55 PM PDT 24
Peak memory 213396 kb
Host smart-dd79c08c-6639-46f7-815e-2a34d190e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738628395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3738628395
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.707141914
Short name T246
Test name
Test status
Simulation time 13965632409 ps
CPU time 12.58 seconds
Started Jun 09 12:28:01 PM PDT 24
Finished Jun 09 12:28:15 PM PDT 24
Peak memory 211260 kb
Host smart-878ea9e5-c15c-488c-9231-74d3a8c74d26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707141914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.707141914
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2297197788
Short name T177
Test name
Test status
Simulation time 901991617 ps
CPU time 9.23 seconds
Started Jun 09 12:27:58 PM PDT 24
Finished Jun 09 12:28:09 PM PDT 24
Peak memory 210744 kb
Host smart-985d286b-5d1c-4230-bf12-9717cf50d5fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297197788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2297197788
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3344948185
Short name T210
Test name
Test status
Simulation time 120167222685 ps
CPU time 310.36 seconds
Started Jun 09 12:28:14 PM PDT 24
Finished Jun 09 12:33:25 PM PDT 24
Peak memory 224696 kb
Host smart-15bf40db-4e22-49fc-9264-d1e5278e0730
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344948185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3344948185
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.8680450
Short name T230
Test name
Test status
Simulation time 6736929158 ps
CPU time 28.76 seconds
Started Jun 09 12:27:45 PM PDT 24
Finished Jun 09 12:28:14 PM PDT 24
Peak memory 212348 kb
Host smart-be098b0c-bf17-4431-9276-7cf766a6ed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8680450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.8680450
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3384486585
Short name T100
Test name
Test status
Simulation time 1158894498 ps
CPU time 5.53 seconds
Started Jun 09 12:28:24 PM PDT 24
Finished Jun 09 12:28:30 PM PDT 24
Peak memory 210904 kb
Host smart-ec5204d7-24b9-4c6f-83ed-d5ebdc376184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384486585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3384486585
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.930747777
Short name T69
Test name
Test status
Simulation time 7747857820 ps
CPU time 35.62 seconds
Started Jun 09 12:28:00 PM PDT 24
Finished Jun 09 12:28:36 PM PDT 24
Peak memory 214084 kb
Host smart-48f01819-4243-458e-abb6-73ff1897879d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930747777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.930747777
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4121382688
Short name T322
Test name
Test status
Simulation time 7299922759 ps
CPU time 46.01 seconds
Started Jun 09 12:27:54 PM PDT 24
Finished Jun 09 12:28:41 PM PDT 24
Peak memory 218048 kb
Host smart-624431af-6013-4667-91f2-a728afcd71cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121382688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4121382688
Directory /workspace/9.rom_ctrl_stress_all/latest
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