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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.34 96.89 91.99 97.72 100.00 98.28 97.45 99.07


Total test records in report: 468
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T296 /workspace/coverage/default/44.rom_ctrl_stress_all.1490954251 Jun 10 05:10:48 PM PDT 24 Jun 10 05:11:00 PM PDT 24 722261203 ps
T297 /workspace/coverage/default/4.rom_ctrl_alert_test.4263924892 Jun 10 05:10:18 PM PDT 24 Jun 10 05:10:22 PM PDT 24 415692740 ps
T298 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2776042483 Jun 10 05:10:39 PM PDT 24 Jun 10 05:11:02 PM PDT 24 2214556392 ps
T299 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1876691109 Jun 10 05:10:20 PM PDT 24 Jun 10 05:14:49 PM PDT 24 108716897656 ps
T300 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3326747264 Jun 10 05:10:51 PM PDT 24 Jun 10 05:11:05 PM PDT 24 1428519846 ps
T301 /workspace/coverage/default/12.rom_ctrl_stress_all.1960753976 Jun 10 05:10:19 PM PDT 24 Jun 10 05:10:34 PM PDT 24 441556005 ps
T302 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3489930501 Jun 10 05:10:49 PM PDT 24 Jun 10 05:11:15 PM PDT 24 2386677176 ps
T303 /workspace/coverage/default/26.rom_ctrl_stress_all.1560336252 Jun 10 05:10:20 PM PDT 24 Jun 10 05:11:43 PM PDT 24 35775493794 ps
T304 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2228487564 Jun 10 05:10:47 PM PDT 24 Jun 10 05:11:22 PM PDT 24 19235073540 ps
T305 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.616754621 Jun 10 05:10:20 PM PDT 24 Jun 10 05:10:38 PM PDT 24 2084952370 ps
T306 /workspace/coverage/default/27.rom_ctrl_alert_test.1009413464 Jun 10 05:10:27 PM PDT 24 Jun 10 05:10:38 PM PDT 24 5305791794 ps
T307 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.754547524 Jun 10 05:10:25 PM PDT 24 Jun 10 05:10:34 PM PDT 24 383871726 ps
T308 /workspace/coverage/default/21.rom_ctrl_stress_all.2591729788 Jun 10 05:10:48 PM PDT 24 Jun 10 05:10:58 PM PDT 24 299746499 ps
T309 /workspace/coverage/default/13.rom_ctrl_smoke.1582358348 Jun 10 05:10:24 PM PDT 24 Jun 10 05:10:40 PM PDT 24 2811458802 ps
T310 /workspace/coverage/default/47.rom_ctrl_smoke.608462431 Jun 10 05:10:59 PM PDT 24 Jun 10 05:11:16 PM PDT 24 3660932076 ps
T311 /workspace/coverage/default/13.rom_ctrl_alert_test.2712021492 Jun 10 05:10:30 PM PDT 24 Jun 10 05:10:44 PM PDT 24 1661088872 ps
T312 /workspace/coverage/default/37.rom_ctrl_stress_all.2485131543 Jun 10 05:10:57 PM PDT 24 Jun 10 05:11:23 PM PDT 24 8942410849 ps
T313 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1921407480 Jun 10 05:10:19 PM PDT 24 Jun 10 06:28:07 PM PDT 24 143696131980 ps
T314 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2788524916 Jun 10 05:10:13 PM PDT 24 Jun 10 05:48:50 PM PDT 24 239783278032 ps
T315 /workspace/coverage/default/34.rom_ctrl_smoke.2962346119 Jun 10 05:10:50 PM PDT 24 Jun 10 05:11:29 PM PDT 24 3831585551 ps
T316 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3236208316 Jun 10 05:10:31 PM PDT 24 Jun 10 05:18:13 PM PDT 24 48694489442 ps
T317 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3296435926 Jun 10 05:10:27 PM PDT 24 Jun 10 05:11:56 PM PDT 24 6902124807 ps
T318 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2913967986 Jun 10 05:10:53 PM PDT 24 Jun 10 05:11:24 PM PDT 24 3355224186 ps
T319 /workspace/coverage/default/1.rom_ctrl_smoke.591947318 Jun 10 05:10:08 PM PDT 24 Jun 10 05:10:50 PM PDT 24 70701339434 ps
T320 /workspace/coverage/default/6.rom_ctrl_alert_test.3147998498 Jun 10 05:10:20 PM PDT 24 Jun 10 05:10:36 PM PDT 24 1853282875 ps
T321 /workspace/coverage/default/39.rom_ctrl_alert_test.2879719317 Jun 10 05:10:42 PM PDT 24 Jun 10 05:10:55 PM PDT 24 1397438484 ps
T322 /workspace/coverage/default/2.rom_ctrl_alert_test.1214977738 Jun 10 05:10:14 PM PDT 24 Jun 10 05:10:27 PM PDT 24 2672170307 ps
T323 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1297387544 Jun 10 05:11:00 PM PDT 24 Jun 10 05:11:26 PM PDT 24 2623513777 ps
T324 /workspace/coverage/default/10.rom_ctrl_smoke.2077439211 Jun 10 05:10:15 PM PDT 24 Jun 10 05:10:53 PM PDT 24 6900650990 ps
T325 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.657492615 Jun 10 05:10:45 PM PDT 24 Jun 10 05:10:59 PM PDT 24 4934899532 ps
T326 /workspace/coverage/default/15.rom_ctrl_stress_all.1752222648 Jun 10 05:10:31 PM PDT 24 Jun 10 05:11:42 PM PDT 24 136542495050 ps
T327 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2457975931 Jun 10 05:10:50 PM PDT 24 Jun 10 07:39:40 PM PDT 24 32239305126 ps
T328 /workspace/coverage/default/45.rom_ctrl_alert_test.3601078414 Jun 10 05:10:59 PM PDT 24 Jun 10 05:11:04 PM PDT 24 167965163 ps
T329 /workspace/coverage/default/46.rom_ctrl_smoke.2779132915 Jun 10 05:10:58 PM PDT 24 Jun 10 05:11:25 PM PDT 24 7532257148 ps
T330 /workspace/coverage/default/33.rom_ctrl_alert_test.2548753357 Jun 10 05:10:39 PM PDT 24 Jun 10 05:10:54 PM PDT 24 1926246773 ps
T331 /workspace/coverage/default/22.rom_ctrl_smoke.2886754305 Jun 10 05:10:55 PM PDT 24 Jun 10 05:11:05 PM PDT 24 352983610 ps
T332 /workspace/coverage/default/29.rom_ctrl_smoke.2371751385 Jun 10 05:10:50 PM PDT 24 Jun 10 05:11:21 PM PDT 24 3604243057 ps
T333 /workspace/coverage/default/49.rom_ctrl_alert_test.905488264 Jun 10 05:11:00 PM PDT 24 Jun 10 05:11:08 PM PDT 24 1890677019 ps
T334 /workspace/coverage/default/17.rom_ctrl_smoke.986649361 Jun 10 05:10:28 PM PDT 24 Jun 10 05:10:49 PM PDT 24 1318153027 ps
T335 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4065881249 Jun 10 05:10:26 PM PDT 24 Jun 10 05:10:53 PM PDT 24 5654728759 ps
T336 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1307458840 Jun 10 05:10:59 PM PDT 24 Jun 10 05:11:14 PM PDT 24 4983163031 ps
T337 /workspace/coverage/default/24.rom_ctrl_alert_test.1530438362 Jun 10 05:10:43 PM PDT 24 Jun 10 05:10:54 PM PDT 24 11433285513 ps
T338 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3055899882 Jun 10 05:10:26 PM PDT 24 Jun 10 05:10:46 PM PDT 24 1589661899 ps
T339 /workspace/coverage/default/19.rom_ctrl_smoke.423904701 Jun 10 05:10:26 PM PDT 24 Jun 10 05:10:50 PM PDT 24 6535572566 ps
T340 /workspace/coverage/default/10.rom_ctrl_stress_all.2475269710 Jun 10 05:10:15 PM PDT 24 Jun 10 05:10:33 PM PDT 24 627595080 ps
T341 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2859404033 Jun 10 05:10:40 PM PDT 24 Jun 10 05:10:50 PM PDT 24 348197820 ps
T342 /workspace/coverage/default/2.rom_ctrl_stress_all.2502926705 Jun 10 05:10:34 PM PDT 24 Jun 10 05:11:27 PM PDT 24 21645202197 ps
T343 /workspace/coverage/default/9.rom_ctrl_stress_all.2860118300 Jun 10 05:10:22 PM PDT 24 Jun 10 05:10:56 PM PDT 24 23045624844 ps
T344 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1981922262 Jun 10 05:10:27 PM PDT 24 Jun 10 05:54:14 PM PDT 24 66657890680 ps
T345 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.976092099 Jun 10 05:10:32 PM PDT 24 Jun 10 05:10:43 PM PDT 24 911755000 ps
T346 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1350767765 Jun 10 05:10:52 PM PDT 24 Jun 10 05:11:02 PM PDT 24 754145344 ps
T347 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3452649842 Jun 10 05:10:18 PM PDT 24 Jun 10 05:10:54 PM PDT 24 17120494579 ps
T348 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1156925692 Jun 10 05:10:28 PM PDT 24 Jun 10 06:02:16 PM PDT 24 116529575641 ps
T349 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1771797697 Jun 10 05:10:27 PM PDT 24 Jun 10 05:11:00 PM PDT 24 14985709394 ps
T350 /workspace/coverage/default/38.rom_ctrl_smoke.415791330 Jun 10 05:10:44 PM PDT 24 Jun 10 05:11:02 PM PDT 24 1014987898 ps
T351 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1124198404 Jun 10 05:10:30 PM PDT 24 Jun 10 05:44:58 PM PDT 24 212683701560 ps
T352 /workspace/coverage/default/16.rom_ctrl_stress_all.2129364256 Jun 10 05:10:24 PM PDT 24 Jun 10 05:10:57 PM PDT 24 11080589088 ps
T353 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2925271649 Jun 10 05:10:17 PM PDT 24 Jun 10 05:10:35 PM PDT 24 7800168084 ps
T354 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2843574459 Jun 10 05:10:56 PM PDT 24 Jun 10 05:41:21 PM PDT 24 47024881458 ps
T355 /workspace/coverage/default/41.rom_ctrl_stress_all.1630168371 Jun 10 05:10:53 PM PDT 24 Jun 10 05:11:11 PM PDT 24 1162398415 ps
T356 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2160331708 Jun 10 05:10:52 PM PDT 24 Jun 10 05:15:02 PM PDT 24 154030072856 ps
T357 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2936696999 Jun 10 05:10:36 PM PDT 24 Jun 10 05:10:48 PM PDT 24 1721901628 ps
T358 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1995201810 Jun 10 05:10:35 PM PDT 24 Jun 10 05:10:52 PM PDT 24 1832214241 ps
T359 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1656221040 Jun 10 05:10:21 PM PDT 24 Jun 10 05:14:26 PM PDT 24 71270790790 ps
T360 /workspace/coverage/default/28.rom_ctrl_alert_test.2423741145 Jun 10 05:10:45 PM PDT 24 Jun 10 05:10:56 PM PDT 24 4266921493 ps
T361 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.153096377 Jun 10 05:10:17 PM PDT 24 Jun 10 05:11:59 PM PDT 24 1742326899 ps
T16 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3352496102 Jun 10 05:10:27 PM PDT 24 Jun 10 06:38:55 PM PDT 24 95633320596 ps
T362 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1020916280 Jun 10 05:10:31 PM PDT 24 Jun 10 05:11:50 PM PDT 24 1048288241 ps
T363 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2950688593 Jun 10 05:10:37 PM PDT 24 Jun 10 05:13:02 PM PDT 24 4703812021 ps
T364 /workspace/coverage/default/43.rom_ctrl_alert_test.3087154483 Jun 10 05:10:59 PM PDT 24 Jun 10 05:11:13 PM PDT 24 4818576294 ps
T365 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2577823401 Jun 10 05:11:01 PM PDT 24 Jun 10 05:13:01 PM PDT 24 11907841837 ps
T366 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.494193520 Jun 10 05:10:33 PM PDT 24 Jun 10 05:10:46 PM PDT 24 5284093821 ps
T367 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.191271072 Jun 10 05:10:49 PM PDT 24 Jun 10 05:16:58 PM PDT 24 28281081669 ps
T47 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.992774529 Jun 10 05:09:42 PM PDT 24 Jun 10 05:10:58 PM PDT 24 2964124353 ps
T50 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1255518296 Jun 10 05:10:11 PM PDT 24 Jun 10 05:10:28 PM PDT 24 32869222380 ps
T51 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.551240608 Jun 10 05:09:57 PM PDT 24 Jun 10 05:10:02 PM PDT 24 96798097 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2543157429 Jun 10 05:09:54 PM PDT 24 Jun 10 05:10:03 PM PDT 24 1203047633 ps
T56 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.665554093 Jun 10 05:09:56 PM PDT 24 Jun 10 05:10:24 PM PDT 24 1137068235 ps
T369 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3984248429 Jun 10 05:09:52 PM PDT 24 Jun 10 05:10:01 PM PDT 24 1876289896 ps
T88 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1804323301 Jun 10 05:10:10 PM PDT 24 Jun 10 05:10:27 PM PDT 24 5191720334 ps
T93 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2693879852 Jun 10 05:10:14 PM PDT 24 Jun 10 05:11:01 PM PDT 24 5162365799 ps
T94 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.130297702 Jun 10 05:09:40 PM PDT 24 Jun 10 05:09:45 PM PDT 24 90167254 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3165067858 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:59 PM PDT 24 5589916149 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2323732282 Jun 10 05:10:11 PM PDT 24 Jun 10 05:10:22 PM PDT 24 1349732893 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2169397720 Jun 10 05:09:45 PM PDT 24 Jun 10 05:09:49 PM PDT 24 87503904 ps
T97 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3338861926 Jun 10 05:10:09 PM PDT 24 Jun 10 05:10:14 PM PDT 24 89147475 ps
T48 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2419462351 Jun 10 05:10:10 PM PDT 24 Jun 10 05:11:32 PM PDT 24 18833979711 ps
T371 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2091381585 Jun 10 05:10:09 PM PDT 24 Jun 10 05:10:17 PM PDT 24 94807823 ps
T57 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1889400370 Jun 10 05:10:04 PM PDT 24 Jun 10 05:11:05 PM PDT 24 20803682362 ps
T58 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2680712844 Jun 10 05:10:11 PM PDT 24 Jun 10 05:10:40 PM PDT 24 1863847181 ps
T372 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.700290202 Jun 10 05:10:05 PM PDT 24 Jun 10 05:10:20 PM PDT 24 1962174886 ps
T49 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3076201230 Jun 10 05:10:02 PM PDT 24 Jun 10 05:11:19 PM PDT 24 1589643651 ps
T373 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.493632687 Jun 10 05:10:14 PM PDT 24 Jun 10 05:10:19 PM PDT 24 335976655 ps
T107 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.999321774 Jun 10 05:10:07 PM PDT 24 Jun 10 05:11:20 PM PDT 24 4973541696 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3695485726 Jun 10 05:09:49 PM PDT 24 Jun 10 05:10:00 PM PDT 24 4114773212 ps
T375 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2126773015 Jun 10 05:10:07 PM PDT 24 Jun 10 05:10:16 PM PDT 24 450566998 ps
T376 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3508877994 Jun 10 05:10:16 PM PDT 24 Jun 10 05:10:23 PM PDT 24 89034540 ps
T109 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3492810910 Jun 10 05:09:45 PM PDT 24 Jun 10 05:11:12 PM PDT 24 1726740118 ps
T89 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2599537641 Jun 10 05:10:01 PM PDT 24 Jun 10 05:10:15 PM PDT 24 8954202752 ps
T377 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.456401 Jun 10 05:10:03 PM PDT 24 Jun 10 05:10:12 PM PDT 24 3517885344 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.831079242 Jun 10 05:10:04 PM PDT 24 Jun 10 05:10:09 PM PDT 24 164767264 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1088032257 Jun 10 05:09:52 PM PDT 24 Jun 10 05:10:10 PM PDT 24 18730913252 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2668185809 Jun 10 05:10:05 PM PDT 24 Jun 10 05:10:20 PM PDT 24 898679702 ps
T59 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2634525743 Jun 10 05:10:11 PM PDT 24 Jun 10 05:10:25 PM PDT 24 5953400272 ps
T381 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1527420592 Jun 10 05:10:05 PM PDT 24 Jun 10 05:10:24 PM PDT 24 3509093833 ps
T110 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.172324468 Jun 10 05:10:14 PM PDT 24 Jun 10 05:11:34 PM PDT 24 2023081226 ps
T382 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.262962225 Jun 10 05:10:15 PM PDT 24 Jun 10 05:10:30 PM PDT 24 11049655630 ps
T104 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1788850830 Jun 10 05:09:53 PM PDT 24 Jun 10 05:10:03 PM PDT 24 592300358 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1922808670 Jun 10 05:09:46 PM PDT 24 Jun 10 05:10:04 PM PDT 24 6821833653 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1654599757 Jun 10 05:09:46 PM PDT 24 Jun 10 05:10:03 PM PDT 24 1634001087 ps
T60 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.957189998 Jun 10 05:10:06 PM PDT 24 Jun 10 05:10:18 PM PDT 24 5760134826 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2518978599 Jun 10 05:10:06 PM PDT 24 Jun 10 05:10:21 PM PDT 24 1831871698 ps
T386 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3367468772 Jun 10 05:10:17 PM PDT 24 Jun 10 05:11:05 PM PDT 24 8220309791 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.371738550 Jun 10 05:10:08 PM PDT 24 Jun 10 05:10:25 PM PDT 24 2005126309 ps
T387 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4199671145 Jun 10 05:10:06 PM PDT 24 Jun 10 05:10:19 PM PDT 24 4375070395 ps
T91 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1143118164 Jun 10 05:10:18 PM PDT 24 Jun 10 05:10:25 PM PDT 24 393778040 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3401050491 Jun 10 05:09:52 PM PDT 24 Jun 10 05:10:06 PM PDT 24 1609753709 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.826523511 Jun 10 05:09:57 PM PDT 24 Jun 10 05:10:38 PM PDT 24 807751415 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4261791070 Jun 10 05:10:12 PM PDT 24 Jun 10 05:10:21 PM PDT 24 770264217 ps
T92 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1876020274 Jun 10 05:10:02 PM PDT 24 Jun 10 05:10:38 PM PDT 24 2924248815 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2866029504 Jun 10 05:10:00 PM PDT 24 Jun 10 05:10:14 PM PDT 24 20041805587 ps
T392 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2198287759 Jun 10 05:10:10 PM PDT 24 Jun 10 05:10:29 PM PDT 24 1793349104 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2921397499 Jun 10 05:10:10 PM PDT 24 Jun 10 05:10:28 PM PDT 24 7203943316 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.789118373 Jun 10 05:10:05 PM PDT 24 Jun 10 05:10:21 PM PDT 24 7732138852 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3038798293 Jun 10 05:09:57 PM PDT 24 Jun 10 05:11:24 PM PDT 24 40953160426 ps
T63 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3597653040 Jun 10 05:10:07 PM PDT 24 Jun 10 05:10:20 PM PDT 24 5849479201 ps
T394 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1529820172 Jun 10 05:10:07 PM PDT 24 Jun 10 05:10:19 PM PDT 24 2506158015 ps
T395 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1717375733 Jun 10 05:10:04 PM PDT 24 Jun 10 05:10:11 PM PDT 24 347378805 ps
T396 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1522604953 Jun 10 05:10:01 PM PDT 24 Jun 10 05:10:17 PM PDT 24 7729856401 ps
T71 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.334984152 Jun 10 05:10:01 PM PDT 24 Jun 10 05:10:14 PM PDT 24 1397282610 ps
T397 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1888470662 Jun 10 05:09:59 PM PDT 24 Jun 10 05:10:18 PM PDT 24 1428040393 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1475257813 Jun 10 05:09:52 PM PDT 24 Jun 10 05:10:09 PM PDT 24 12340012697 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.440514625 Jun 10 05:09:52 PM PDT 24 Jun 10 05:09:59 PM PDT 24 1671052879 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1646868311 Jun 10 05:10:03 PM PDT 24 Jun 10 05:10:22 PM PDT 24 2746189533 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3159909209 Jun 10 05:09:54 PM PDT 24 Jun 10 05:10:03 PM PDT 24 3872298126 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3884832472 Jun 10 05:09:53 PM PDT 24 Jun 10 05:10:05 PM PDT 24 1217563733 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1442002172 Jun 10 05:10:04 PM PDT 24 Jun 10 05:10:13 PM PDT 24 1412911167 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.504361692 Jun 10 05:10:05 PM PDT 24 Jun 10 05:10:19 PM PDT 24 948205798 ps
T405 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2564888248 Jun 10 05:10:11 PM PDT 24 Jun 10 05:10:26 PM PDT 24 1765138028 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.848085969 Jun 10 05:10:00 PM PDT 24 Jun 10 05:10:14 PM PDT 24 1028905900 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3235066823 Jun 10 05:10:05 PM PDT 24 Jun 10 05:10:15 PM PDT 24 853179549 ps
T112 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1554749024 Jun 10 05:10:07 PM PDT 24 Jun 10 05:10:52 PM PDT 24 10508259593 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3326910854 Jun 10 05:09:44 PM PDT 24 Jun 10 05:10:02 PM PDT 24 8860368408 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2665408458 Jun 10 05:10:12 PM PDT 24 Jun 10 05:10:23 PM PDT 24 4291610126 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.333258876 Jun 10 05:09:41 PM PDT 24 Jun 10 05:09:57 PM PDT 24 1749345963 ps
T411 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.195647346 Jun 10 05:10:12 PM PDT 24 Jun 10 05:10:28 PM PDT 24 7540783545 ps
T113 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1131150071 Jun 10 05:10:08 PM PDT 24 Jun 10 05:10:48 PM PDT 24 1442871140 ps
T72 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2003187694 Jun 10 05:10:08 PM PDT 24 Jun 10 05:10:17 PM PDT 24 829882061 ps
T412 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3448872936 Jun 10 05:10:05 PM PDT 24 Jun 10 05:10:20 PM PDT 24 1200000273 ps
T413 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2035353067 Jun 10 05:10:02 PM PDT 24 Jun 10 05:10:39 PM PDT 24 591636080 ps
T414 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1199554813 Jun 10 05:09:43 PM PDT 24 Jun 10 05:09:51 PM PDT 24 3235510154 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.714652005 Jun 10 05:09:52 PM PDT 24 Jun 10 05:10:07 PM PDT 24 23884139464 ps
T416 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2689855845 Jun 10 05:10:02 PM PDT 24 Jun 10 05:10:16 PM PDT 24 6561804150 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2356455138 Jun 10 05:10:07 PM PDT 24 Jun 10 05:10:17 PM PDT 24 1099146035 ps
T105 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2135923233 Jun 10 05:10:01 PM PDT 24 Jun 10 05:10:38 PM PDT 24 704052810 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1003602430 Jun 10 05:09:42 PM PDT 24 Jun 10 05:09:50 PM PDT 24 347381735 ps
T419 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.818206791 Jun 10 05:10:09 PM PDT 24 Jun 10 05:10:25 PM PDT 24 2035731661 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.28816043 Jun 10 05:10:08 PM PDT 24 Jun 10 05:10:23 PM PDT 24 1778976763 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2207397797 Jun 10 05:10:02 PM PDT 24 Jun 10 05:10:20 PM PDT 24 10445005922 ps
T422 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.5336480 Jun 10 05:10:04 PM PDT 24 Jun 10 05:10:14 PM PDT 24 3370037538 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2473502174 Jun 10 05:09:59 PM PDT 24 Jun 10 05:10:15 PM PDT 24 1803898703 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2368736168 Jun 10 05:10:01 PM PDT 24 Jun 10 05:10:13 PM PDT 24 2308382905 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3937985993 Jun 10 05:09:56 PM PDT 24 Jun 10 05:10:00 PM PDT 24 85713150 ps
T426 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.989430597 Jun 10 05:10:09 PM PDT 24 Jun 10 05:10:26 PM PDT 24 8053372368 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3569235372 Jun 10 05:09:45 PM PDT 24 Jun 10 05:09:49 PM PDT 24 308236179 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2005159120 Jun 10 05:09:55 PM PDT 24 Jun 10 05:10:05 PM PDT 24 3214266751 ps
T429 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.22322418 Jun 10 05:10:03 PM PDT 24 Jun 10 05:10:17 PM PDT 24 3234602045 ps
T430 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1873018789 Jun 10 05:10:01 PM PDT 24 Jun 10 05:10:15 PM PDT 24 1571397366 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1316471946 Jun 10 05:10:02 PM PDT 24 Jun 10 05:10:16 PM PDT 24 2969755106 ps
T73 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1025389870 Jun 10 05:09:51 PM PDT 24 Jun 10 05:10:39 PM PDT 24 11914567602 ps
T76 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4134406434 Jun 10 05:09:48 PM PDT 24 Jun 10 05:10:04 PM PDT 24 7544364103 ps
T102 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2131634241 Jun 10 05:10:06 PM PDT 24 Jun 10 05:11:08 PM PDT 24 10832137445 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.596933372 Jun 10 05:10:10 PM PDT 24 Jun 10 05:10:15 PM PDT 24 94615935 ps
T75 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1919591459 Jun 10 05:10:11 PM PDT 24 Jun 10 05:10:22 PM PDT 24 4650877315 ps
T433 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2844730178 Jun 10 05:10:03 PM PDT 24 Jun 10 05:10:14 PM PDT 24 21353543268 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1635573766 Jun 10 05:09:57 PM PDT 24 Jun 10 05:10:08 PM PDT 24 4396736172 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.730012591 Jun 10 05:10:04 PM PDT 24 Jun 10 05:10:09 PM PDT 24 85734455 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1689291232 Jun 10 05:09:44 PM PDT 24 Jun 10 05:09:56 PM PDT 24 2936963157 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2726094028 Jun 10 05:10:09 PM PDT 24 Jun 10 05:10:28 PM PDT 24 1443713749 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2204396386 Jun 10 05:09:54 PM PDT 24 Jun 10 05:10:01 PM PDT 24 430755921 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1660102309 Jun 10 05:10:01 PM PDT 24 Jun 10 05:10:19 PM PDT 24 10105995440 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1419672389 Jun 10 05:10:01 PM PDT 24 Jun 10 05:11:18 PM PDT 24 3919656350 ps
T111 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2669817460 Jun 10 05:10:03 PM PDT 24 Jun 10 05:11:22 PM PDT 24 2206733177 ps
T441 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.869577577 Jun 10 05:10:03 PM PDT 24 Jun 10 05:11:09 PM PDT 24 12556045196 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.747243097 Jun 10 05:09:49 PM PDT 24 Jun 10 05:10:08 PM PDT 24 2098037720 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3517503201 Jun 10 05:09:42 PM PDT 24 Jun 10 05:09:48 PM PDT 24 99705602 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1447774659 Jun 10 05:09:58 PM PDT 24 Jun 10 05:10:03 PM PDT 24 86462693 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1862910630 Jun 10 05:10:21 PM PDT 24 Jun 10 05:10:35 PM PDT 24 1434546158 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4133114189 Jun 10 05:10:10 PM PDT 24 Jun 10 05:11:12 PM PDT 24 15750269927 ps
T446 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1727193367 Jun 10 05:10:11 PM PDT 24 Jun 10 05:10:18 PM PDT 24 103991231 ps
T74 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1791628058 Jun 10 05:10:11 PM PDT 24 Jun 10 05:11:11 PM PDT 24 34342324469 ps
T77 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1259431090 Jun 10 05:10:08 PM PDT 24 Jun 10 05:11:38 PM PDT 24 21119520530 ps
T447 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1835698026 Jun 10 05:10:03 PM PDT 24 Jun 10 05:10:08 PM PDT 24 1377906057 ps
T448 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4020573008 Jun 10 05:10:07 PM PDT 24 Jun 10 05:10:36 PM PDT 24 2010087528 ps
T449 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.675804676 Jun 10 05:10:16 PM PDT 24 Jun 10 05:10:33 PM PDT 24 1631668311 ps
T114 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1052456305 Jun 10 05:10:07 PM PDT 24 Jun 10 05:11:24 PM PDT 24 1805979273 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3931576080 Jun 10 05:10:07 PM PDT 24 Jun 10 05:10:50 PM PDT 24 1342921669 ps
T451 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.685649485 Jun 10 05:10:04 PM PDT 24 Jun 10 05:10:21 PM PDT 24 2089789166 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3997570707 Jun 10 05:10:09 PM PDT 24 Jun 10 05:10:15 PM PDT 24 361490794 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3077933888 Jun 10 05:10:03 PM PDT 24 Jun 10 05:11:25 PM PDT 24 38404669466 ps
T453 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1631997786 Jun 10 05:10:09 PM PDT 24 Jun 10 05:10:20 PM PDT 24 3473402214 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.262321465 Jun 10 05:09:56 PM PDT 24 Jun 10 05:10:08 PM PDT 24 4536424195 ps
T455 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1866427100 Jun 10 05:10:09 PM PDT 24 Jun 10 05:10:47 PM PDT 24 2974252577 ps
T456 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1847464518 Jun 10 05:09:56 PM PDT 24 Jun 10 05:10:07 PM PDT 24 1039716451 ps
T457 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.210889637 Jun 10 05:10:00 PM PDT 24 Jun 10 05:10:41 PM PDT 24 1023564285 ps
T458 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.818907981 Jun 10 05:10:07 PM PDT 24 Jun 10 05:10:12 PM PDT 24 346776306 ps
T459 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1742151956 Jun 10 05:09:54 PM PDT 24 Jun 10 05:10:15 PM PDT 24 2135214828 ps
T460 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4136432317 Jun 10 05:10:04 PM PDT 24 Jun 10 05:10:22 PM PDT 24 1619981361 ps
T461 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1955637027 Jun 10 05:10:22 PM PDT 24 Jun 10 05:10:35 PM PDT 24 10926197723 ps
T462 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1843183415 Jun 10 05:10:23 PM PDT 24 Jun 10 05:10:31 PM PDT 24 606928668 ps
T106 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.616974127 Jun 10 05:10:06 PM PDT 24 Jun 10 05:11:24 PM PDT 24 8479797038 ps
T463 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3299103959 Jun 10 05:10:02 PM PDT 24 Jun 10 05:10:15 PM PDT 24 2323555673 ps
T464 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.715892438 Jun 10 05:10:21 PM PDT 24 Jun 10 05:10:29 PM PDT 24 1195671291 ps
T465 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1560027483 Jun 10 05:10:03 PM PDT 24 Jun 10 05:10:49 PM PDT 24 4381747564 ps
T466 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.833853309 Jun 10 05:09:57 PM PDT 24 Jun 10 05:10:05 PM PDT 24 3339520568 ps
T467 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2627175535 Jun 10 05:10:01 PM PDT 24 Jun 10 05:10:37 PM PDT 24 578819522 ps
T468 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.845476579 Jun 10 05:10:06 PM PDT 24 Jun 10 05:10:11 PM PDT 24 396801103 ps
T108 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2089066534 Jun 10 05:09:55 PM PDT 24 Jun 10 05:11:10 PM PDT 24 5415646137 ps

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4272155302
Short name T8
Test name
Test status
Simulation time 22216778556 ps
CPU time 239.46 seconds
Started Jun 10 05:10:57 PM PDT 24
Finished Jun 10 05:14:57 PM PDT 24
Peak memory 213188 kb
Host smart-0a5bbfba-ad4f-4bf2-8a8d-7f2a81846bfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272155302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4272155302
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4002401723
Short name T11
Test name
Test status
Simulation time 65800281004 ps
CPU time 606.92 seconds
Started Jun 10 05:10:31 PM PDT 24
Finished Jun 10 05:20:38 PM PDT 24
Peak memory 235568 kb
Host smart-67b83465-758d-4b10-ada0-b16fc1a97a56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002401723 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.4002401723
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3219480865
Short name T34
Test name
Test status
Simulation time 6952890835 ps
CPU time 114.85 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:12:18 PM PDT 24
Peak memory 237452 kb
Host smart-4425e104-0c96-428e-9c2b-e3de9023a105
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219480865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3219480865
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.992774529
Short name T47
Test name
Test status
Simulation time 2964124353 ps
CPU time 74.77 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:10:58 PM PDT 24
Peak memory 212576 kb
Host smart-dde6100e-6d7e-4df2-a61c-f3a951046c26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992774529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.992774529
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.894289655
Short name T28
Test name
Test status
Simulation time 8433270700 ps
CPU time 110.43 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:12:11 PM PDT 24
Peak memory 235920 kb
Host smart-f6da174f-a023-4904-ae59-2b9cacbe8b6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894289655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.894289655
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4153414303
Short name T64
Test name
Test status
Simulation time 7109975412 ps
CPU time 19.45 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:42 PM PDT 24
Peak memory 212588 kb
Host smart-07fca930-ebba-4c29-879b-535329f9e18c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153414303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4153414303
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1025389870
Short name T73
Test name
Test status
Simulation time 11914567602 ps
CPU time 47.85 seconds
Started Jun 10 05:09:51 PM PDT 24
Finished Jun 10 05:10:39 PM PDT 24
Peak memory 210984 kb
Host smart-c52f66c9-138c-4420-b24c-afe85e7c585e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025389870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1025389870
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2311422946
Short name T1
Test name
Test status
Simulation time 5919502480 ps
CPU time 13.55 seconds
Started Jun 10 05:10:23 PM PDT 24
Finished Jun 10 05:10:37 PM PDT 24
Peak memory 210868 kb
Host smart-4576ee8b-439e-495b-993d-7355e40b5afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311422946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2311422946
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3076201230
Short name T49
Test name
Test status
Simulation time 1589643651 ps
CPU time 76.79 seconds
Started Jun 10 05:10:02 PM PDT 24
Finished Jun 10 05:11:19 PM PDT 24
Peak memory 213528 kb
Host smart-16502592-9264-43ee-8489-13cdccb7ccd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076201230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3076201230
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.71981194
Short name T14
Test name
Test status
Simulation time 140915532877 ps
CPU time 5947.85 seconds
Started Jun 10 05:10:30 PM PDT 24
Finished Jun 10 06:49:39 PM PDT 24
Peak memory 238888 kb
Host smart-ae61f17d-df3d-4b00-b1ed-55dce153e26d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71981194 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.71981194
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2680712844
Short name T58
Test name
Test status
Simulation time 1863847181 ps
CPU time 28.31 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:40 PM PDT 24
Peak memory 210924 kb
Host smart-c6323ed5-5135-45ac-89c5-dd59a77d7cd5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680712844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2680712844
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.907913729
Short name T6
Test name
Test status
Simulation time 10808865165 ps
CPU time 26.98 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:50 PM PDT 24
Peak memory 211948 kb
Host smart-9925e669-acc8-48bc-a001-26505cd5a5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907913729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.907913729
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3871842009
Short name T279
Test name
Test status
Simulation time 170248701 ps
CPU time 9.3 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:10:31 PM PDT 24
Peak memory 211772 kb
Host smart-abb9313a-08a2-42ef-bc7b-d6d5c565efeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871842009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3871842009
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.616974127
Short name T106
Test name
Test status
Simulation time 8479797038 ps
CPU time 77.16 seconds
Started Jun 10 05:10:06 PM PDT 24
Finished Jun 10 05:11:24 PM PDT 24
Peak memory 219112 kb
Host smart-ff5537f7-7365-4613-bd2f-073b935d2a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616974127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.616974127
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1204658216
Short name T12
Test name
Test status
Simulation time 1294612543 ps
CPU time 9.41 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:10:28 PM PDT 24
Peak memory 210920 kb
Host smart-499e030d-65da-4c01-886e-2dd66d858ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204658216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1204658216
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3478284214
Short name T116
Test name
Test status
Simulation time 67447412277 ps
CPU time 304.73 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:15:24 PM PDT 24
Peak memory 237732 kb
Host smart-48d409a3-7a0c-4f47-9e68-b99428966b52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478284214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3478284214
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.999321774
Short name T107
Test name
Test status
Simulation time 4973541696 ps
CPU time 72.64 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:11:20 PM PDT 24
Peak memory 219096 kb
Host smart-71f69561-a3a5-4d35-b279-8460c0130c41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999321774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.999321774
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3165067858
Short name T95
Test name
Test status
Simulation time 5589916149 ps
CPU time 15.79 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:59 PM PDT 24
Peak memory 210988 kb
Host smart-81cf1c27-396c-4170-9b68-62564de2f64b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165067858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3165067858
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1124623172
Short name T79
Test name
Test status
Simulation time 421099103 ps
CPU time 8.57 seconds
Started Jun 10 05:10:54 PM PDT 24
Finished Jun 10 05:11:03 PM PDT 24
Peak memory 210912 kb
Host smart-971a78ec-c158-43c6-8413-c6a717ce461e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1124623172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1124623172
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3352496102
Short name T16
Test name
Test status
Simulation time 95633320596 ps
CPU time 5307.19 seconds
Started Jun 10 05:10:27 PM PDT 24
Finished Jun 10 06:38:55 PM PDT 24
Peak memory 235516 kb
Host smart-cf2db847-2800-4898-b52c-9ee28c12bded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352496102 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3352496102
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4214263372
Short name T41
Test name
Test status
Simulation time 335042718734 ps
CPU time 3419.64 seconds
Started Jun 10 05:10:39 PM PDT 24
Finished Jun 10 06:07:39 PM PDT 24
Peak memory 251868 kb
Host smart-64524e9e-21aa-437b-b5dd-fe7acf6f93bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214263372 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4214263372
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.789118373
Short name T61
Test name
Test status
Simulation time 7732138852 ps
CPU time 15.94 seconds
Started Jun 10 05:10:05 PM PDT 24
Finished Jun 10 05:10:21 PM PDT 24
Peak memory 219332 kb
Host smart-a9c37bdb-273e-40ae-b939-8fe9d75da9a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789118373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.789118373
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3695485726
Short name T374
Test name
Test status
Simulation time 4114773212 ps
CPU time 10.84 seconds
Started Jun 10 05:09:49 PM PDT 24
Finished Jun 10 05:10:00 PM PDT 24
Peak memory 218876 kb
Host smart-ab67af31-8786-418b-8910-cadecc620c4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695485726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3695485726
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1689291232
Short name T436
Test name
Test status
Simulation time 2936963157 ps
CPU time 11.88 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:09:56 PM PDT 24
Peak memory 219204 kb
Host smart-267d2e0d-a039-40ed-af1c-5d86c775c757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689291232 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1689291232
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.130297702
Short name T94
Test name
Test status
Simulation time 90167254 ps
CPU time 4.35 seconds
Started Jun 10 05:09:40 PM PDT 24
Finished Jun 10 05:09:45 PM PDT 24
Peak memory 210884 kb
Host smart-7955862a-9fc1-432d-a39c-5d7a1fa61c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130297702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.130297702
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.262321465
Short name T454
Test name
Test status
Simulation time 4536424195 ps
CPU time 12.17 seconds
Started Jun 10 05:09:56 PM PDT 24
Finished Jun 10 05:10:08 PM PDT 24
Peak memory 210764 kb
Host smart-ebb77462-8c33-4f02-8334-46b2d1e88404
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262321465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.262321465
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3569235372
Short name T427
Test name
Test status
Simulation time 308236179 ps
CPU time 4.13 seconds
Started Jun 10 05:09:45 PM PDT 24
Finished Jun 10 05:09:49 PM PDT 24
Peak memory 210596 kb
Host smart-beef02bd-e31e-4802-99f3-2bd6abe306c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569235372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3569235372
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.665554093
Short name T56
Test name
Test status
Simulation time 1137068235 ps
CPU time 28.23 seconds
Started Jun 10 05:09:56 PM PDT 24
Finished Jun 10 05:10:24 PM PDT 24
Peak memory 210948 kb
Host smart-f496e238-94d8-4b28-b2f7-04bd3763e3fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665554093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.665554093
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1873018789
Short name T430
Test name
Test status
Simulation time 1571397366 ps
CPU time 13.63 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:10:15 PM PDT 24
Peak memory 219000 kb
Host smart-6d77124c-0b49-4c42-a9cb-35e361ca08f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873018789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1873018789
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1003602430
Short name T418
Test name
Test status
Simulation time 347381735 ps
CPU time 6.83 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:09:50 PM PDT 24
Peak memory 218976 kb
Host smart-834702c0-e7ff-48a4-a541-519f242fda4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003602430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1003602430
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.826523511
Short name T389
Test name
Test status
Simulation time 807751415 ps
CPU time 40.84 seconds
Started Jun 10 05:09:57 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 219140 kb
Host smart-3eaa6a9a-d9df-4594-96c3-fc858e465ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826523511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.826523511
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4134406434
Short name T76
Test name
Test status
Simulation time 7544364103 ps
CPU time 15.79 seconds
Started Jun 10 05:09:48 PM PDT 24
Finished Jun 10 05:10:04 PM PDT 24
Peak memory 219036 kb
Host smart-3b24b3d7-814b-4184-b3ac-c408360cbfe2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134406434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4134406434
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1316471946
Short name T431
Test name
Test status
Simulation time 2969755106 ps
CPU time 14.39 seconds
Started Jun 10 05:10:02 PM PDT 24
Finished Jun 10 05:10:16 PM PDT 24
Peak memory 218708 kb
Host smart-ce584c1d-7f12-430b-9da8-e6711d3f73e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316471946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1316471946
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.333258876
Short name T410
Test name
Test status
Simulation time 1749345963 ps
CPU time 15.36 seconds
Started Jun 10 05:09:41 PM PDT 24
Finished Jun 10 05:09:57 PM PDT 24
Peak memory 210936 kb
Host smart-af211fba-4352-4eb2-a89a-9299aa56002e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333258876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.333258876
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.440514625
Short name T399
Test name
Test status
Simulation time 1671052879 ps
CPU time 7.2 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:09:59 PM PDT 24
Peak memory 219092 kb
Host smart-5d632b35-2f08-4ffd-8835-671b641ff1c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440514625 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.440514625
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1475257813
Short name T398
Test name
Test status
Simulation time 12340012697 ps
CPU time 16.46 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:10:09 PM PDT 24
Peak memory 210988 kb
Host smart-202c09e7-ce4d-466b-a7df-a76cfb175f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475257813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1475257813
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4261791070
Short name T390
Test name
Test status
Simulation time 770264217 ps
CPU time 8.66 seconds
Started Jun 10 05:10:12 PM PDT 24
Finished Jun 10 05:10:21 PM PDT 24
Peak memory 210640 kb
Host smart-0d226cfe-160e-4328-8c92-fb0ea3d8ec35
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261791070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4261791070
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2204396386
Short name T438
Test name
Test status
Simulation time 430755921 ps
CPU time 6.96 seconds
Started Jun 10 05:09:54 PM PDT 24
Finished Jun 10 05:10:01 PM PDT 24
Peak memory 210628 kb
Host smart-b90fe1e5-6b90-4391-ad0d-5bcdb321e8ab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204396386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2204396386
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1876020274
Short name T92
Test name
Test status
Simulation time 2924248815 ps
CPU time 35.93 seconds
Started Jun 10 05:10:02 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 210960 kb
Host smart-51405654-e8ec-4d2e-aed0-28cf7cfc60e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876020274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1876020274
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2473502174
Short name T423
Test name
Test status
Simulation time 1803898703 ps
CPU time 15.65 seconds
Started Jun 10 05:09:59 PM PDT 24
Finished Jun 10 05:10:15 PM PDT 24
Peak memory 210916 kb
Host smart-93f3a147-ae79-4bca-a316-c0435cdd9a2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473502174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2473502174
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.504361692
Short name T404
Test name
Test status
Simulation time 948205798 ps
CPU time 12.96 seconds
Started Jun 10 05:10:05 PM PDT 24
Finished Jun 10 05:10:19 PM PDT 24
Peak memory 218956 kb
Host smart-b6c5f264-152e-49e7-9619-c261a58d671a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504361692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.504361692
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.210889637
Short name T457
Test name
Test status
Simulation time 1023564285 ps
CPU time 41.11 seconds
Started Jun 10 05:10:00 PM PDT 24
Finished Jun 10 05:10:41 PM PDT 24
Peak memory 219268 kb
Host smart-78cb5241-9ef5-4568-8288-60a1e827f8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210889637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.210889637
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.5336480
Short name T422
Test name
Test status
Simulation time 3370037538 ps
CPU time 10.17 seconds
Started Jun 10 05:10:04 PM PDT 24
Finished Jun 10 05:10:14 PM PDT 24
Peak memory 219184 kb
Host smart-c1ae4e45-db64-4998-8f9d-b78eb1e3015b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5336480 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.5336480
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.334984152
Short name T71
Test name
Test status
Simulation time 1397282610 ps
CPU time 12.31 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:10:14 PM PDT 24
Peak memory 210892 kb
Host smart-28c7991c-b9f3-436e-be55-d794e931a3c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334984152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.334984152
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4020573008
Short name T448
Test name
Test status
Simulation time 2010087528 ps
CPU time 27.87 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:10:36 PM PDT 24
Peak memory 210912 kb
Host smart-4d329314-c2cd-43aa-8abd-6c4b7a99390c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020573008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4020573008
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2634525743
Short name T59
Test name
Test status
Simulation time 5953400272 ps
CPU time 13.4 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:25 PM PDT 24
Peak memory 211020 kb
Host smart-14528164-7afa-4414-889d-f1b625c29425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634525743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2634525743
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2198287759
Short name T392
Test name
Test status
Simulation time 1793349104 ps
CPU time 17.84 seconds
Started Jun 10 05:10:10 PM PDT 24
Finished Jun 10 05:10:29 PM PDT 24
Peak memory 218984 kb
Host smart-1097549f-e532-475d-95ca-cbaf05299386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198287759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2198287759
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1955637027
Short name T461
Test name
Test status
Simulation time 10926197723 ps
CPU time 13.03 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:35 PM PDT 24
Peak memory 219052 kb
Host smart-0fd63c23-1502-4aae-b55d-05adc8f30ac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955637027 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1955637027
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1522604953
Short name T396
Test name
Test status
Simulation time 7729856401 ps
CPU time 15.84 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:10:17 PM PDT 24
Peak memory 218124 kb
Host smart-bee63fb9-58d0-4abe-9429-25e4f7b73a4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522604953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1522604953
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1889400370
Short name T57
Test name
Test status
Simulation time 20803682362 ps
CPU time 60.2 seconds
Started Jun 10 05:10:04 PM PDT 24
Finished Jun 10 05:11:05 PM PDT 24
Peak memory 210944 kb
Host smart-0028cc0e-bbc9-4264-9992-b82d1535e45c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889400370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1889400370
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2599537641
Short name T89
Test name
Test status
Simulation time 8954202752 ps
CPU time 13.37 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:10:15 PM PDT 24
Peak memory 218824 kb
Host smart-cc1e4241-34be-4bc2-82ec-f2fd93b26b53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599537641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2599537641
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4136432317
Short name T460
Test name
Test status
Simulation time 1619981361 ps
CPU time 17.08 seconds
Started Jun 10 05:10:04 PM PDT 24
Finished Jun 10 05:10:22 PM PDT 24
Peak memory 218988 kb
Host smart-85dcf1ae-b6f9-48a4-b2ea-376200f22871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136432317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4136432317
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1631997786
Short name T453
Test name
Test status
Simulation time 3473402214 ps
CPU time 10.06 seconds
Started Jun 10 05:10:09 PM PDT 24
Finished Jun 10 05:10:20 PM PDT 24
Peak memory 219204 kb
Host smart-1e65439e-0962-4311-822b-3c5bb8689b3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631997786 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1631997786
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.831079242
Short name T378
Test name
Test status
Simulation time 164767264 ps
CPU time 4.29 seconds
Started Jun 10 05:10:04 PM PDT 24
Finished Jun 10 05:10:09 PM PDT 24
Peak memory 210932 kb
Host smart-1298c436-4af3-4909-9c9a-7711bd7569b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831079242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.831079242
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3077933888
Short name T78
Test name
Test status
Simulation time 38404669466 ps
CPU time 82.16 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:11:25 PM PDT 24
Peak memory 210984 kb
Host smart-0cdc1cb2-e496-4479-9aa6-8ee5b9ac8e07
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077933888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3077933888
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1847464518
Short name T456
Test name
Test status
Simulation time 1039716451 ps
CPU time 10.66 seconds
Started Jun 10 05:09:56 PM PDT 24
Finished Jun 10 05:10:07 PM PDT 24
Peak memory 210916 kb
Host smart-6d86c7d9-f2de-4319-ab73-ed75fda44faa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847464518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1847464518
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3984248429
Short name T369
Test name
Test status
Simulation time 1876289896 ps
CPU time 9.29 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:10:01 PM PDT 24
Peak memory 218964 kb
Host smart-567a68da-8571-4d58-b48c-3850e39418b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984248429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3984248429
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2627175535
Short name T467
Test name
Test status
Simulation time 578819522 ps
CPU time 36.05 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:10:37 PM PDT 24
Peak memory 219036 kb
Host smart-a09c7344-d627-48b8-9337-44aa60cb21be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627175535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2627175535
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2921397499
Short name T393
Test name
Test status
Simulation time 7203943316 ps
CPU time 17.46 seconds
Started Jun 10 05:10:10 PM PDT 24
Finished Jun 10 05:10:28 PM PDT 24
Peak memory 219120 kb
Host smart-3af3fa42-c352-48fa-837a-33ba415b184f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921397499 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2921397499
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1919591459
Short name T75
Test name
Test status
Simulation time 4650877315 ps
CPU time 11.14 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:22 PM PDT 24
Peak memory 210996 kb
Host smart-4184eaec-e73e-419f-ba16-ad7479badcbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919591459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1919591459
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.869577577
Short name T441
Test name
Test status
Simulation time 12556045196 ps
CPU time 65.31 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:11:09 PM PDT 24
Peak memory 218056 kb
Host smart-38ef6413-b40e-4b98-afdc-272915981fd7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869577577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.869577577
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1727193367
Short name T446
Test name
Test status
Simulation time 103991231 ps
CPU time 6.24 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:18 PM PDT 24
Peak memory 211020 kb
Host smart-38fd7c0f-c285-43ee-9893-894f2392a248
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727193367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1727193367
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1527420592
Short name T381
Test name
Test status
Simulation time 3509093833 ps
CPU time 18.98 seconds
Started Jun 10 05:10:05 PM PDT 24
Finished Jun 10 05:10:24 PM PDT 24
Peak memory 219052 kb
Host smart-8013f82c-f5bf-4ad6-96ff-262e29092afa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527420592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1527420592
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2669817460
Short name T111
Test name
Test status
Simulation time 2206733177 ps
CPU time 78.69 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:11:22 PM PDT 24
Peak memory 212392 kb
Host smart-6f4bb90e-6a2f-4f16-a9a4-306feb2c364f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669817460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2669817460
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2126773015
Short name T375
Test name
Test status
Simulation time 450566998 ps
CPU time 8.1 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:10:16 PM PDT 24
Peak memory 219040 kb
Host smart-e0d6f826-7d30-4241-ab19-43305ef21105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126773015 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2126773015
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1804323301
Short name T88
Test name
Test status
Simulation time 5191720334 ps
CPU time 16.63 seconds
Started Jun 10 05:10:10 PM PDT 24
Finished Jun 10 05:10:27 PM PDT 24
Peak memory 210932 kb
Host smart-6638dac0-31e5-4560-95c3-f88adf6f4d2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804323301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1804323301
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1447774659
Short name T444
Test name
Test status
Simulation time 86462693 ps
CPU time 4.42 seconds
Started Jun 10 05:09:58 PM PDT 24
Finished Jun 10 05:10:03 PM PDT 24
Peak memory 210896 kb
Host smart-4d5e2429-93a0-4b4e-872e-5f80d9610a89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447774659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1447774659
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1788850830
Short name T104
Test name
Test status
Simulation time 592300358 ps
CPU time 9.3 seconds
Started Jun 10 05:09:53 PM PDT 24
Finished Jun 10 05:10:03 PM PDT 24
Peak memory 219052 kb
Host smart-04a49986-7546-4908-9e33-89eb0d816cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788850830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1788850830
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3367468772
Short name T386
Test name
Test status
Simulation time 8220309791 ps
CPU time 46.73 seconds
Started Jun 10 05:10:17 PM PDT 24
Finished Jun 10 05:11:05 PM PDT 24
Peak memory 211620 kb
Host smart-029b2bb5-1aff-4630-89b3-cc0481c3debc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367468772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3367468772
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2564888248
Short name T405
Test name
Test status
Simulation time 1765138028 ps
CPU time 14.43 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:26 PM PDT 24
Peak memory 219064 kb
Host smart-5c18341d-fd25-4b48-814f-9e21f4ba2f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564888248 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2564888248
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2665408458
Short name T409
Test name
Test status
Simulation time 4291610126 ps
CPU time 10.73 seconds
Started Jun 10 05:10:12 PM PDT 24
Finished Jun 10 05:10:23 PM PDT 24
Peak memory 219108 kb
Host smart-8b5616fe-7b7b-417b-8242-31f49fdcb2cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665408458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2665408458
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1866427100
Short name T455
Test name
Test status
Simulation time 2974252577 ps
CPU time 37.88 seconds
Started Jun 10 05:10:09 PM PDT 24
Finished Jun 10 05:10:47 PM PDT 24
Peak memory 211012 kb
Host smart-7176edc9-0c39-4e6e-beb2-188961476fbc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866427100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1866427100
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.195647346
Short name T411
Test name
Test status
Simulation time 7540783545 ps
CPU time 15.38 seconds
Started Jun 10 05:10:12 PM PDT 24
Finished Jun 10 05:10:28 PM PDT 24
Peak memory 210992 kb
Host smart-93f26124-9470-4f15-81d6-d9848a16f039
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195647346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.195647346
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2207397797
Short name T421
Test name
Test status
Simulation time 10445005922 ps
CPU time 17.4 seconds
Started Jun 10 05:10:02 PM PDT 24
Finished Jun 10 05:10:20 PM PDT 24
Peak memory 219036 kb
Host smart-24611a12-d467-4328-b279-e545424dd501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207397797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2207397797
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2135923233
Short name T105
Test name
Test status
Simulation time 704052810 ps
CPU time 36.62 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 219108 kb
Host smart-641bf483-339e-4507-80dd-3de4d215b3ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135923233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2135923233
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.989430597
Short name T426
Test name
Test status
Simulation time 8053372368 ps
CPU time 16.81 seconds
Started Jun 10 05:10:09 PM PDT 24
Finished Jun 10 05:10:26 PM PDT 24
Peak memory 219160 kb
Host smart-e0e2ce88-5c47-4c31-8b11-7988323776ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989430597 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.989430597
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.818907981
Short name T458
Test name
Test status
Simulation time 346776306 ps
CPU time 4.29 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:10:12 PM PDT 24
Peak memory 210892 kb
Host smart-ee98234e-d592-453c-af52-b96a71cfa361
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818907981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.818907981
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1646868311
Short name T400
Test name
Test status
Simulation time 2746189533 ps
CPU time 18.59 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:10:22 PM PDT 24
Peak memory 210984 kb
Host smart-c4711428-6771-4946-8187-c9f32e1ae521
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646868311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1646868311
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.957189998
Short name T60
Test name
Test status
Simulation time 5760134826 ps
CPU time 11.22 seconds
Started Jun 10 05:10:06 PM PDT 24
Finished Jun 10 05:10:18 PM PDT 24
Peak memory 211112 kb
Host smart-993f6472-06f5-4fe3-957f-61723dbf1c34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957189998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.957189998
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2091381585
Short name T371
Test name
Test status
Simulation time 94807823 ps
CPU time 7.33 seconds
Started Jun 10 05:10:09 PM PDT 24
Finished Jun 10 05:10:17 PM PDT 24
Peak memory 218984 kb
Host smart-a3298515-7880-4253-bb7a-289aa61fa143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091381585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2091381585
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1131150071
Short name T113
Test name
Test status
Simulation time 1442871140 ps
CPU time 40.01 seconds
Started Jun 10 05:10:08 PM PDT 24
Finished Jun 10 05:10:48 PM PDT 24
Peak memory 219072 kb
Host smart-c55c3b4a-9e4c-41ce-a8c6-d836330b196e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131150071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1131150071
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.596933372
Short name T432
Test name
Test status
Simulation time 94615935 ps
CPU time 4.36 seconds
Started Jun 10 05:10:10 PM PDT 24
Finished Jun 10 05:10:15 PM PDT 24
Peak memory 212064 kb
Host smart-e793e1b9-2b04-4c97-9364-72e8aca37005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596933372 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.596933372
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1843183415
Short name T462
Test name
Test status
Simulation time 606928668 ps
CPU time 7.96 seconds
Started Jun 10 05:10:23 PM PDT 24
Finished Jun 10 05:10:31 PM PDT 24
Peak memory 217976 kb
Host smart-97d5666b-4921-4682-bb6b-33269c98a472
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843183415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1843183415
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4133114189
Short name T103
Test name
Test status
Simulation time 15750269927 ps
CPU time 61.44 seconds
Started Jun 10 05:10:10 PM PDT 24
Finished Jun 10 05:11:12 PM PDT 24
Peak memory 211016 kb
Host smart-fa1e5c48-b5e8-4497-b459-7620ce3c2eb0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133114189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4133114189
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.818206791
Short name T419
Test name
Test status
Simulation time 2035731661 ps
CPU time 15.78 seconds
Started Jun 10 05:10:09 PM PDT 24
Finished Jun 10 05:10:25 PM PDT 24
Peak memory 210832 kb
Host smart-0c621f5b-3e5e-45f0-a61b-de96b39ecb69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818206791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.818206791
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2323732282
Short name T370
Test name
Test status
Simulation time 1349732893 ps
CPU time 10.38 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:22 PM PDT 24
Peak memory 218976 kb
Host smart-f63aebe9-df4b-4744-a2ac-90fe9684cf09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323732282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2323732282
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.172324468
Short name T110
Test name
Test status
Simulation time 2023081226 ps
CPU time 79.48 seconds
Started Jun 10 05:10:14 PM PDT 24
Finished Jun 10 05:11:34 PM PDT 24
Peak memory 211456 kb
Host smart-6b9adaf7-15cd-4a35-a3d8-826185bc9283
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172324468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.172324468
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3997570707
Short name T452
Test name
Test status
Simulation time 361490794 ps
CPU time 4.77 seconds
Started Jun 10 05:10:09 PM PDT 24
Finished Jun 10 05:10:15 PM PDT 24
Peak memory 219292 kb
Host smart-0d212f92-0db9-4575-9486-1dd345d2f172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997570707 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3997570707
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1835698026
Short name T447
Test name
Test status
Simulation time 1377906057 ps
CPU time 4.6 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:10:08 PM PDT 24
Peak memory 218280 kb
Host smart-638deaef-0a0b-45f8-9422-4f3ba0e463e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835698026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1835698026
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1791628058
Short name T74
Test name
Test status
Simulation time 34342324469 ps
CPU time 59.69 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:11:11 PM PDT 24
Peak memory 211000 kb
Host smart-fab3f21b-47cc-4bfe-b916-8001a0ec5817
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791628058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1791628058
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2689855845
Short name T416
Test name
Test status
Simulation time 6561804150 ps
CPU time 13.63 seconds
Started Jun 10 05:10:02 PM PDT 24
Finished Jun 10 05:10:16 PM PDT 24
Peak memory 211088 kb
Host smart-2f100eb7-bbc6-457f-8fd8-cebdbbb2cee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689855845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2689855845
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4199671145
Short name T387
Test name
Test status
Simulation time 4375070395 ps
CPU time 13.13 seconds
Started Jun 10 05:10:06 PM PDT 24
Finished Jun 10 05:10:19 PM PDT 24
Peak memory 219036 kb
Host smart-aa979dc0-3f7c-454f-b103-2a4a6f58f622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199671145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4199671145
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3931576080
Short name T450
Test name
Test status
Simulation time 1342921669 ps
CPU time 43.2 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:10:50 PM PDT 24
Peak memory 212324 kb
Host smart-20a51100-7f39-47a4-ba8c-3b7b553a5da7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931576080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3931576080
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.262962225
Short name T382
Test name
Test status
Simulation time 11049655630 ps
CPU time 15.33 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 05:10:30 PM PDT 24
Peak memory 219416 kb
Host smart-75127263-191e-4804-9704-50769a92cc04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262962225 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.262962225
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.715892438
Short name T464
Test name
Test status
Simulation time 1195671291 ps
CPU time 8.15 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:10:29 PM PDT 24
Peak memory 210928 kb
Host smart-d3fa2c1d-ef4f-4c34-9fe8-1f552fc0b3d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715892438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.715892438
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2726094028
Short name T437
Test name
Test status
Simulation time 1443713749 ps
CPU time 18.66 seconds
Started Jun 10 05:10:09 PM PDT 24
Finished Jun 10 05:10:28 PM PDT 24
Peak memory 210956 kb
Host smart-29f7d33e-2b3f-491f-b7f7-08957e35a902
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726094028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2726094028
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1143118164
Short name T91
Test name
Test status
Simulation time 393778040 ps
CPU time 6 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:10:25 PM PDT 24
Peak memory 219072 kb
Host smart-702001a9-0e47-491e-8463-ad61dab5a87d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143118164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1143118164
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.675804676
Short name T449
Test name
Test status
Simulation time 1631668311 ps
CPU time 17.46 seconds
Started Jun 10 05:10:16 PM PDT 24
Finished Jun 10 05:10:33 PM PDT 24
Peak memory 218924 kb
Host smart-c63e83e0-52ce-4548-b914-6ce06e808dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675804676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.675804676
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1052456305
Short name T114
Test name
Test status
Simulation time 1805979273 ps
CPU time 76.89 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:11:24 PM PDT 24
Peak memory 210896 kb
Host smart-bbf4f0b1-3b8a-4b63-8bf8-b6d130c4a466
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052456305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1052456305
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2169397720
Short name T96
Test name
Test status
Simulation time 87503904 ps
CPU time 4.31 seconds
Started Jun 10 05:09:45 PM PDT 24
Finished Jun 10 05:09:49 PM PDT 24
Peak memory 210908 kb
Host smart-9dce081b-fdd9-4f5b-a260-56af8c08417b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169397720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2169397720
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1088032257
Short name T379
Test name
Test status
Simulation time 18730913252 ps
CPU time 17.08 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:10:10 PM PDT 24
Peak memory 219100 kb
Host smart-5d91d756-5834-4b45-a36f-d7f9b7f4de75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088032257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1088032257
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.848085969
Short name T406
Test name
Test status
Simulation time 1028905900 ps
CPU time 13.71 seconds
Started Jun 10 05:10:00 PM PDT 24
Finished Jun 10 05:10:14 PM PDT 24
Peak memory 210912 kb
Host smart-a21f9ad0-0e20-4351-8410-d5978f7c3ea5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848085969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.848085969
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3517503201
Short name T443
Test name
Test status
Simulation time 99705602 ps
CPU time 4.92 seconds
Started Jun 10 05:09:42 PM PDT 24
Finished Jun 10 05:09:48 PM PDT 24
Peak memory 219156 kb
Host smart-cf0ac959-2e89-4c79-bef6-4c09dcb38f5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517503201 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3517503201
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1199554813
Short name T414
Test name
Test status
Simulation time 3235510154 ps
CPU time 7.43 seconds
Started Jun 10 05:09:43 PM PDT 24
Finished Jun 10 05:09:51 PM PDT 24
Peak memory 210980 kb
Host smart-29dab645-3f7d-49a5-8a84-a63f85de62d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199554813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1199554813
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2543157429
Short name T368
Test name
Test status
Simulation time 1203047633 ps
CPU time 7.92 seconds
Started Jun 10 05:09:54 PM PDT 24
Finished Jun 10 05:10:03 PM PDT 24
Peak memory 210612 kb
Host smart-8a8a14fc-b6f7-47c0-a0d3-5d651854c031
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543157429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2543157429
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2368736168
Short name T424
Test name
Test status
Simulation time 2308382905 ps
CPU time 11.61 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:10:13 PM PDT 24
Peak memory 210724 kb
Host smart-41cc3437-a7ef-4361-a070-e677e3e18f47
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368736168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2368736168
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1742151956
Short name T459
Test name
Test status
Simulation time 2135214828 ps
CPU time 19.79 seconds
Started Jun 10 05:09:54 PM PDT 24
Finished Jun 10 05:10:15 PM PDT 24
Peak memory 211016 kb
Host smart-e37b8ae4-7b5b-42dc-9fad-aadc9314066c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742151956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1742151956
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2356455138
Short name T417
Test name
Test status
Simulation time 1099146035 ps
CPU time 9.35 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:10:17 PM PDT 24
Peak memory 211000 kb
Host smart-6190e664-49ef-4787-b044-4340f3cd5d25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356455138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2356455138
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1654599757
Short name T384
Test name
Test status
Simulation time 1634001087 ps
CPU time 16.52 seconds
Started Jun 10 05:09:46 PM PDT 24
Finished Jun 10 05:10:03 PM PDT 24
Peak memory 218956 kb
Host smart-d617f8dd-4ff1-4057-be26-e4a1096b8ead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654599757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1654599757
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3492810910
Short name T109
Test name
Test status
Simulation time 1726740118 ps
CPU time 87.12 seconds
Started Jun 10 05:09:45 PM PDT 24
Finished Jun 10 05:11:12 PM PDT 24
Peak memory 219288 kb
Host smart-498ca75e-5c97-4e85-a27c-9b06f88744c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492810910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3492810910
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3597653040
Short name T63
Test name
Test status
Simulation time 5849479201 ps
CPU time 12.61 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:10:20 PM PDT 24
Peak memory 211044 kb
Host smart-cb0608ab-120b-4d5a-b6de-0bc23d6dca3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597653040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3597653040
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3884832472
Short name T402
Test name
Test status
Simulation time 1217563733 ps
CPU time 12.39 seconds
Started Jun 10 05:09:53 PM PDT 24
Finished Jun 10 05:10:05 PM PDT 24
Peak memory 210968 kb
Host smart-6228c163-710f-4779-a9eb-9fb02cd22906
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884832472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3884832472
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2003187694
Short name T72
Test name
Test status
Simulation time 829882061 ps
CPU time 8.92 seconds
Started Jun 10 05:10:08 PM PDT 24
Finished Jun 10 05:10:17 PM PDT 24
Peak memory 217748 kb
Host smart-f5a426e5-fb2c-4e80-8e62-bceae4ef87fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003187694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2003187694
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1660102309
Short name T439
Test name
Test status
Simulation time 10105995440 ps
CPU time 17.25 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:10:19 PM PDT 24
Peak memory 219112 kb
Host smart-ed559c5d-ca26-4a8f-a4b0-aba9d4e57cab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660102309 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1660102309
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3159909209
Short name T401
Test name
Test status
Simulation time 3872298126 ps
CPU time 8.29 seconds
Started Jun 10 05:09:54 PM PDT 24
Finished Jun 10 05:10:03 PM PDT 24
Peak memory 210900 kb
Host smart-94b5e1ae-8b2d-4e7b-900e-8a95b987a122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159909209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3159909209
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.714652005
Short name T415
Test name
Test status
Simulation time 23884139464 ps
CPU time 15.08 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:10:07 PM PDT 24
Peak memory 210688 kb
Host smart-034c30b9-705a-415f-9f87-850ac551d904
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714652005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.714652005
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3326910854
Short name T408
Test name
Test status
Simulation time 8860368408 ps
CPU time 18.08 seconds
Started Jun 10 05:09:44 PM PDT 24
Finished Jun 10 05:10:02 PM PDT 24
Peak memory 210712 kb
Host smart-dcdfdd4e-92ba-4722-883a-8a98d023847e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326910854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3326910854
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3038798293
Short name T62
Test name
Test status
Simulation time 40953160426 ps
CPU time 87.03 seconds
Started Jun 10 05:09:57 PM PDT 24
Finished Jun 10 05:11:24 PM PDT 24
Peak memory 210984 kb
Host smart-36e7c248-5f41-43af-9741-db87023817eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038798293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3038798293
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2005159120
Short name T428
Test name
Test status
Simulation time 3214266751 ps
CPU time 9.1 seconds
Started Jun 10 05:09:55 PM PDT 24
Finished Jun 10 05:10:05 PM PDT 24
Peak memory 219028 kb
Host smart-c632bb4a-a9a9-44ba-90b2-3ac41573de42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005159120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2005159120
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1922808670
Short name T383
Test name
Test status
Simulation time 6821833653 ps
CPU time 17.65 seconds
Started Jun 10 05:09:46 PM PDT 24
Finished Jun 10 05:10:04 PM PDT 24
Peak memory 219032 kb
Host smart-f74a5f60-b239-46fe-9fea-722c4be910ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922808670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1922808670
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.551240608
Short name T51
Test name
Test status
Simulation time 96798097 ps
CPU time 4.44 seconds
Started Jun 10 05:09:57 PM PDT 24
Finished Jun 10 05:10:02 PM PDT 24
Peak memory 210912 kb
Host smart-f87dea77-99ed-4c6b-ae54-6c1e36ac7e30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551240608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.551240608
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2866029504
Short name T391
Test name
Test status
Simulation time 20041805587 ps
CPU time 14.2 seconds
Started Jun 10 05:10:00 PM PDT 24
Finished Jun 10 05:10:14 PM PDT 24
Peak memory 210968 kb
Host smart-bd08a144-e47d-4b98-955d-ce6f895d0dda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866029504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2866029504
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3401050491
Short name T388
Test name
Test status
Simulation time 1609753709 ps
CPU time 13.54 seconds
Started Jun 10 05:09:52 PM PDT 24
Finished Jun 10 05:10:06 PM PDT 24
Peak memory 218396 kb
Host smart-6cd580ee-1bcc-4f84-a601-8c7fe8d81140
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401050491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3401050491
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.28816043
Short name T420
Test name
Test status
Simulation time 1778976763 ps
CPU time 14.61 seconds
Started Jun 10 05:10:08 PM PDT 24
Finished Jun 10 05:10:23 PM PDT 24
Peak memory 219100 kb
Host smart-bde760b3-e57d-44b8-abcb-15c2809268fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28816043 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.28816043
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.747243097
Short name T442
Test name
Test status
Simulation time 2098037720 ps
CPU time 17.51 seconds
Started Jun 10 05:09:49 PM PDT 24
Finished Jun 10 05:10:08 PM PDT 24
Peak memory 211108 kb
Host smart-4d866f45-b8ee-4b96-96c0-09d6382128a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747243097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.747243097
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3937985993
Short name T425
Test name
Test status
Simulation time 85713150 ps
CPU time 4.22 seconds
Started Jun 10 05:09:56 PM PDT 24
Finished Jun 10 05:10:00 PM PDT 24
Peak memory 210628 kb
Host smart-2b5aee66-28cc-4f44-92e7-7cac1a73c9b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937985993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3937985993
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2518978599
Short name T385
Test name
Test status
Simulation time 1831871698 ps
CPU time 14.52 seconds
Started Jun 10 05:10:06 PM PDT 24
Finished Jun 10 05:10:21 PM PDT 24
Peak memory 210616 kb
Host smart-c38d4823-c038-4a00-b78f-cde93fc2c6fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518978599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2518978599
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1560027483
Short name T465
Test name
Test status
Simulation time 4381747564 ps
CPU time 45.12 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 210992 kb
Host smart-cc0e9aef-54db-4c36-8ff9-040b282f6278
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560027483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1560027483
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.371738550
Short name T90
Test name
Test status
Simulation time 2005126309 ps
CPU time 16.37 seconds
Started Jun 10 05:10:08 PM PDT 24
Finished Jun 10 05:10:25 PM PDT 24
Peak memory 211148 kb
Host smart-97ba047a-553e-470d-915d-508fbe4bc2ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371738550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.371738550
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2668185809
Short name T380
Test name
Test status
Simulation time 898679702 ps
CPU time 14.28 seconds
Started Jun 10 05:10:05 PM PDT 24
Finished Jun 10 05:10:20 PM PDT 24
Peak memory 218956 kb
Host smart-fcd89d9f-4735-4ae2-9398-323f3a8d51c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668185809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2668185809
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1419672389
Short name T440
Test name
Test status
Simulation time 3919656350 ps
CPU time 77.4 seconds
Started Jun 10 05:10:01 PM PDT 24
Finished Jun 10 05:11:18 PM PDT 24
Peak memory 219108 kb
Host smart-68e45e78-8683-4078-a934-1e61240b6042
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419672389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1419672389
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.845476579
Short name T468
Test name
Test status
Simulation time 396801103 ps
CPU time 5 seconds
Started Jun 10 05:10:06 PM PDT 24
Finished Jun 10 05:10:11 PM PDT 24
Peak memory 219120 kb
Host smart-1ab3d0d7-f60e-49e5-8a46-2bd304a40d44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845476579 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.845476579
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.456401
Short name T377
Test name
Test status
Simulation time 3517885344 ps
CPU time 8.74 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:10:12 PM PDT 24
Peak memory 219108 kb
Host smart-c943b191-d967-45c9-8c88-3e0c866544ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.456401
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2131634241
Short name T102
Test name
Test status
Simulation time 10832137445 ps
CPU time 61.94 seconds
Started Jun 10 05:10:06 PM PDT 24
Finished Jun 10 05:11:08 PM PDT 24
Peak memory 211000 kb
Host smart-e405d8c7-eb3d-4c38-84cc-6931cb350e43
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131634241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2131634241
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.685649485
Short name T451
Test name
Test status
Simulation time 2089789166 ps
CPU time 16.2 seconds
Started Jun 10 05:10:04 PM PDT 24
Finished Jun 10 05:10:21 PM PDT 24
Peak memory 219012 kb
Host smart-7f1bbb6b-9bab-471c-8385-7c9c8b3ef072
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685649485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.685649485
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.22322418
Short name T429
Test name
Test status
Simulation time 3234602045 ps
CPU time 13.53 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:10:17 PM PDT 24
Peak memory 218968 kb
Host smart-37683bdd-81ec-408b-9b8e-8aa60064ba4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.22322418
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2089066534
Short name T108
Test name
Test status
Simulation time 5415646137 ps
CPU time 74.62 seconds
Started Jun 10 05:09:55 PM PDT 24
Finished Jun 10 05:11:10 PM PDT 24
Peak memory 219160 kb
Host smart-40dbede0-6c56-415f-9018-98358fdabdbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089066534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2089066534
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.833853309
Short name T466
Test name
Test status
Simulation time 3339520568 ps
CPU time 8.26 seconds
Started Jun 10 05:09:57 PM PDT 24
Finished Jun 10 05:10:05 PM PDT 24
Peak memory 219164 kb
Host smart-8cdeece8-e3ce-4b99-ad58-aabea30e6abd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833853309 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.833853309
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3338861926
Short name T97
Test name
Test status
Simulation time 89147475 ps
CPU time 4.37 seconds
Started Jun 10 05:10:09 PM PDT 24
Finished Jun 10 05:10:14 PM PDT 24
Peak memory 210888 kb
Host smart-26fdd52e-ffee-44c1-8791-4c1932cc6062
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338861926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3338861926
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1888470662
Short name T397
Test name
Test status
Simulation time 1428040393 ps
CPU time 18.98 seconds
Started Jun 10 05:09:59 PM PDT 24
Finished Jun 10 05:10:18 PM PDT 24
Peak memory 210860 kb
Host smart-a523320f-9575-41e5-a3ba-ab9f839d45b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888470662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1888470662
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3299103959
Short name T463
Test name
Test status
Simulation time 2323555673 ps
CPU time 12.63 seconds
Started Jun 10 05:10:02 PM PDT 24
Finished Jun 10 05:10:15 PM PDT 24
Peak memory 219040 kb
Host smart-227b6ad3-1e6f-4fb8-a281-b1a9d8e738ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299103959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3299103959
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1717375733
Short name T395
Test name
Test status
Simulation time 347378805 ps
CPU time 6.68 seconds
Started Jun 10 05:10:04 PM PDT 24
Finished Jun 10 05:10:11 PM PDT 24
Peak memory 216712 kb
Host smart-218d4d1e-0c5b-4a3d-9560-9ec0f969bb7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717375733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1717375733
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1554749024
Short name T112
Test name
Test status
Simulation time 10508259593 ps
CPU time 44.67 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:10:52 PM PDT 24
Peak memory 219144 kb
Host smart-ae9a854a-ef51-4c3e-b7d7-c6b05c8a611c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554749024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1554749024
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1862910630
Short name T445
Test name
Test status
Simulation time 1434546158 ps
CPU time 13.44 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:10:35 PM PDT 24
Peak memory 219120 kb
Host smart-54d5e116-c2cd-457e-b002-56081f86b23f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862910630 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1862910630
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.493632687
Short name T373
Test name
Test status
Simulation time 335976655 ps
CPU time 5.4 seconds
Started Jun 10 05:10:14 PM PDT 24
Finished Jun 10 05:10:19 PM PDT 24
Peak memory 210872 kb
Host smart-9cd6d412-f005-4592-8555-ef9eb0503e68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493632687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.493632687
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1635573766
Short name T434
Test name
Test status
Simulation time 4396736172 ps
CPU time 10.86 seconds
Started Jun 10 05:09:57 PM PDT 24
Finished Jun 10 05:10:08 PM PDT 24
Peak memory 211008 kb
Host smart-7ecf914c-3c3f-41cb-a4f2-f050d13467df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635573766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1635573766
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1529820172
Short name T394
Test name
Test status
Simulation time 2506158015 ps
CPU time 11.49 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:10:19 PM PDT 24
Peak memory 218952 kb
Host smart-b242ecae-749d-407d-81c9-6bee5bb0ff74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529820172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1529820172
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.700290202
Short name T372
Test name
Test status
Simulation time 1962174886 ps
CPU time 15.2 seconds
Started Jun 10 05:10:05 PM PDT 24
Finished Jun 10 05:10:20 PM PDT 24
Peak memory 219044 kb
Host smart-a132d2ec-38ca-420a-bcda-57de550d88ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700290202 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.700290202
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3235066823
Short name T407
Test name
Test status
Simulation time 853179549 ps
CPU time 9.5 seconds
Started Jun 10 05:10:05 PM PDT 24
Finished Jun 10 05:10:15 PM PDT 24
Peak memory 219020 kb
Host smart-e3edd320-5a7d-4d11-9df7-627f48f7e378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235066823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3235066823
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1259431090
Short name T77
Test name
Test status
Simulation time 21119520530 ps
CPU time 88.8 seconds
Started Jun 10 05:10:08 PM PDT 24
Finished Jun 10 05:11:38 PM PDT 24
Peak memory 210960 kb
Host smart-414b2aca-2f88-4f75-bd2f-e7af2cf9cfe2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259431090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1259431090
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2844730178
Short name T433
Test name
Test status
Simulation time 21353543268 ps
CPU time 10.97 seconds
Started Jun 10 05:10:03 PM PDT 24
Finished Jun 10 05:10:14 PM PDT 24
Peak memory 219108 kb
Host smart-59765caf-f2ae-4f53-8d5a-2bcf11fa9d8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844730178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2844730178
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3508877994
Short name T376
Test name
Test status
Simulation time 89034540 ps
CPU time 6.39 seconds
Started Jun 10 05:10:16 PM PDT 24
Finished Jun 10 05:10:23 PM PDT 24
Peak memory 218948 kb
Host smart-9b6a316e-105c-4011-8a0a-2e8473a2e4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508877994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3508877994
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2419462351
Short name T48
Test name
Test status
Simulation time 18833979711 ps
CPU time 81.13 seconds
Started Jun 10 05:10:10 PM PDT 24
Finished Jun 10 05:11:32 PM PDT 24
Peak memory 219140 kb
Host smart-6e4da978-5a83-4f9b-b824-abc8bc795153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419462351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2419462351
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1442002172
Short name T403
Test name
Test status
Simulation time 1412911167 ps
CPU time 8.94 seconds
Started Jun 10 05:10:04 PM PDT 24
Finished Jun 10 05:10:13 PM PDT 24
Peak memory 219036 kb
Host smart-c07ba9bf-f8eb-43ce-a5c9-ca6f59f17530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442002172 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1442002172
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.730012591
Short name T435
Test name
Test status
Simulation time 85734455 ps
CPU time 4.35 seconds
Started Jun 10 05:10:04 PM PDT 24
Finished Jun 10 05:10:09 PM PDT 24
Peak memory 210912 kb
Host smart-22d99240-7ec0-409a-8b55-8e5293952461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730012591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.730012591
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2693879852
Short name T93
Test name
Test status
Simulation time 5162365799 ps
CPU time 47.12 seconds
Started Jun 10 05:10:14 PM PDT 24
Finished Jun 10 05:11:01 PM PDT 24
Peak memory 210956 kb
Host smart-32938613-91ab-48ae-bc9a-1588fe84979b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693879852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2693879852
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1255518296
Short name T50
Test name
Test status
Simulation time 32869222380 ps
CPU time 16.12 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:28 PM PDT 24
Peak memory 211136 kb
Host smart-ae39f3b4-c770-4071-881a-8b22e4444e9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255518296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1255518296
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3448872936
Short name T412
Test name
Test status
Simulation time 1200000273 ps
CPU time 13.98 seconds
Started Jun 10 05:10:05 PM PDT 24
Finished Jun 10 05:10:20 PM PDT 24
Peak memory 218936 kb
Host smart-006cb067-a769-4453-ad49-eb4951907f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448872936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3448872936
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2035353067
Short name T413
Test name
Test status
Simulation time 591636080 ps
CPU time 37.08 seconds
Started Jun 10 05:10:02 PM PDT 24
Finished Jun 10 05:10:39 PM PDT 24
Peak memory 211324 kb
Host smart-bebd6d56-5495-40a3-8b78-8f3f829c8647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035353067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2035353067
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.616754621
Short name T305
Test name
Test status
Simulation time 2084952370 ps
CPU time 17 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 210892 kb
Host smart-7d570fb0-b414-4e87-8da3-4cda6f38aa29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616754621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.616754621
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2312171030
Short name T5
Test name
Test status
Simulation time 605213162 ps
CPU time 102.88 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 05:11:58 PM PDT 24
Peak memory 237572 kb
Host smart-ca4852af-bb00-4de6-a7db-0163cb66c87e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312171030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2312171030
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.845024421
Short name T275
Test name
Test status
Simulation time 1633027153 ps
CPU time 24.88 seconds
Started Jun 10 05:10:25 PM PDT 24
Finished Jun 10 05:10:51 PM PDT 24
Peak memory 213144 kb
Host smart-fbc117c0-b318-46e0-9926-061257a156f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845024421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.845024421
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3463182329
Short name T163
Test name
Test status
Simulation time 4661993445 ps
CPU time 63.93 seconds
Started Jun 10 05:10:06 PM PDT 24
Finished Jun 10 05:11:10 PM PDT 24
Peak memory 215224 kb
Host smart-1a4f8b90-8f0f-4210-ad7b-84f93900b32d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463182329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3463182329
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2788524916
Short name T314
Test name
Test status
Simulation time 239783278032 ps
CPU time 2316.68 seconds
Started Jun 10 05:10:13 PM PDT 24
Finished Jun 10 05:48:50 PM PDT 24
Peak memory 237184 kb
Host smart-914ed196-bfc0-444d-b53e-5a441845fac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788524916 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2788524916
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.628285088
Short name T207
Test name
Test status
Simulation time 4290624253 ps
CPU time 10.6 seconds
Started Jun 10 05:10:12 PM PDT 24
Finished Jun 10 05:10:23 PM PDT 24
Peak memory 210732 kb
Host smart-82aedce6-c802-4688-9064-b37bb3bb0ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628285088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.628285088
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.153096377
Short name T361
Test name
Test status
Simulation time 1742326899 ps
CPU time 102.17 seconds
Started Jun 10 05:10:17 PM PDT 24
Finished Jun 10 05:11:59 PM PDT 24
Peak memory 236224 kb
Host smart-0e9f843c-aa47-4860-b7fe-e78ada7c84b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153096377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.153096377
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1084730109
Short name T217
Test name
Test status
Simulation time 3736111758 ps
CPU time 31.43 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:10:52 PM PDT 24
Peak memory 211668 kb
Host smart-9180ecd5-729b-4225-844e-f93e8d0f5189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084730109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1084730109
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.591947318
Short name T319
Test name
Test status
Simulation time 70701339434 ps
CPU time 41.39 seconds
Started Jun 10 05:10:08 PM PDT 24
Finished Jun 10 05:10:50 PM PDT 24
Peak memory 214104 kb
Host smart-199c222b-5d17-4c48-9d6f-b92b25491424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591947318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.591947318
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4024684801
Short name T293
Test name
Test status
Simulation time 626178056 ps
CPU time 17.71 seconds
Started Jun 10 05:10:12 PM PDT 24
Finished Jun 10 05:10:30 PM PDT 24
Peak memory 212436 kb
Host smart-abefcd8e-516a-4fcb-97d8-ee6eafd4560e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024684801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4024684801
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3870590355
Short name T155
Test name
Test status
Simulation time 698138201 ps
CPU time 8.52 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:31 PM PDT 24
Peak memory 210748 kb
Host smart-f6d9cd60-89ea-4f5c-a039-a9ae21ded61a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870590355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3870590355
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3335451964
Short name T135
Test name
Test status
Simulation time 12674540121 ps
CPU time 33.26 seconds
Started Jun 10 05:10:17 PM PDT 24
Finished Jun 10 05:10:51 PM PDT 24
Peak memory 211816 kb
Host smart-ad8e73b0-b7ff-43f9-bbef-03f5c5aa6824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335451964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3335451964
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.692204874
Short name T118
Test name
Test status
Simulation time 1090439400 ps
CPU time 11.84 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:10:33 PM PDT 24
Peak memory 210872 kb
Host smart-d89b7545-7c24-4a0b-8e42-6467f3eb8da5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692204874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.692204874
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2077439211
Short name T324
Test name
Test status
Simulation time 6900650990 ps
CPU time 37.34 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 05:10:53 PM PDT 24
Peak memory 213952 kb
Host smart-fb30a08e-422c-4a2f-aa00-d90d6a6de721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077439211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2077439211
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2475269710
Short name T340
Test name
Test status
Simulation time 627595080 ps
CPU time 17.92 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 05:10:33 PM PDT 24
Peak memory 214744 kb
Host smart-69d9dc99-cbd4-47c0-9dc9-2591415ba928
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475269710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2475269710
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1921407480
Short name T313
Test name
Test status
Simulation time 143696131980 ps
CPU time 4667.09 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 06:28:07 PM PDT 24
Peak memory 235492 kb
Host smart-ab6f01b1-21cd-4bd1-aafc-f87fec90f193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921407480 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1921407480
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3135780904
Short name T204
Test name
Test status
Simulation time 89090277 ps
CPU time 4.35 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:10:23 PM PDT 24
Peak memory 210944 kb
Host smart-c47b1ea0-8429-49f3-898f-121839fd5d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135780904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3135780904
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3945856123
Short name T33
Test name
Test status
Simulation time 3127507053 ps
CPU time 98.98 seconds
Started Jun 10 05:10:33 PM PDT 24
Finished Jun 10 05:12:13 PM PDT 24
Peak memory 237448 kb
Host smart-27936f88-8252-4d11-a936-7f5e16a1cd3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945856123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3945856123
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2446055765
Short name T122
Test name
Test status
Simulation time 578608822 ps
CPU time 13.93 seconds
Started Jun 10 05:10:16 PM PDT 24
Finished Jun 10 05:10:31 PM PDT 24
Peak memory 211460 kb
Host smart-2f428d0a-e49e-42a8-ae3e-08d3148ed923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446055765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2446055765
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1752297122
Short name T226
Test name
Test status
Simulation time 188907410 ps
CPU time 7.03 seconds
Started Jun 10 05:10:13 PM PDT 24
Finished Jun 10 05:10:21 PM PDT 24
Peak memory 210904 kb
Host smart-af197c5a-aa45-47ba-9dc2-dc7ff7a56a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1752297122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1752297122
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3462256417
Short name T130
Test name
Test status
Simulation time 2737738032 ps
CPU time 31.29 seconds
Started Jun 10 05:10:23 PM PDT 24
Finished Jun 10 05:10:54 PM PDT 24
Peak memory 213508 kb
Host smart-2eb9ee02-8a86-4450-8094-463e0ee5fe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462256417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3462256417
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4038260890
Short name T213
Test name
Test status
Simulation time 131531170 ps
CPU time 6.68 seconds
Started Jun 10 05:10:27 PM PDT 24
Finished Jun 10 05:10:34 PM PDT 24
Peak memory 210876 kb
Host smart-d8f22fd2-e426-4906-8f9b-c1ed740a1ae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038260890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4038260890
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.232370681
Short name T83
Test name
Test status
Simulation time 8643192536 ps
CPU time 15.49 seconds
Started Jun 10 05:10:41 PM PDT 24
Finished Jun 10 05:10:57 PM PDT 24
Peak memory 210876 kb
Host smart-39b950e4-5ff7-4fa4-b9bc-c3d44fa5b23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232370681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.232370681
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1108692159
Short name T115
Test name
Test status
Simulation time 14434771211 ps
CPU time 138.87 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:12:45 PM PDT 24
Peak memory 228212 kb
Host smart-c3c7fff8-1b25-4d37-a5ed-1a065aa30274
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108692159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1108692159
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1771797697
Short name T349
Test name
Test status
Simulation time 14985709394 ps
CPU time 32.17 seconds
Started Jun 10 05:10:27 PM PDT 24
Finished Jun 10 05:11:00 PM PDT 24
Peak memory 211888 kb
Host smart-48c592a4-2b19-4d63-82c9-10a21bc3976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771797697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1771797697
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.976092099
Short name T345
Test name
Test status
Simulation time 911755000 ps
CPU time 10.39 seconds
Started Jun 10 05:10:32 PM PDT 24
Finished Jun 10 05:10:43 PM PDT 24
Peak memory 210928 kb
Host smart-dcaf6db1-f205-4b97-ba6a-c6b65342ba48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976092099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.976092099
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2178717472
Short name T208
Test name
Test status
Simulation time 4015788271 ps
CPU time 34.35 seconds
Started Jun 10 05:10:40 PM PDT 24
Finished Jun 10 05:11:15 PM PDT 24
Peak memory 213472 kb
Host smart-fff14381-98c5-4745-8147-f261cbd124a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178717472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2178717472
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1960753976
Short name T301
Test name
Test status
Simulation time 441556005 ps
CPU time 13.92 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:10:34 PM PDT 24
Peak memory 213308 kb
Host smart-aa9de716-bcf4-4df8-895d-f99f171829e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960753976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1960753976
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2712021492
Short name T311
Test name
Test status
Simulation time 1661088872 ps
CPU time 13.71 seconds
Started Jun 10 05:10:30 PM PDT 24
Finished Jun 10 05:10:44 PM PDT 24
Peak memory 210728 kb
Host smart-b5983532-9004-47fb-abf8-9958d9bda804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712021492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2712021492
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3296435926
Short name T317
Test name
Test status
Simulation time 6902124807 ps
CPU time 83.75 seconds
Started Jun 10 05:10:27 PM PDT 24
Finished Jun 10 05:11:56 PM PDT 24
Peak memory 212388 kb
Host smart-04ab4e5d-6314-45a3-8c1a-3a57ba55674f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296435926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3296435926
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.234714793
Short name T143
Test name
Test status
Simulation time 3029302055 ps
CPU time 27.21 seconds
Started Jun 10 05:10:33 PM PDT 24
Finished Jun 10 05:11:01 PM PDT 24
Peak memory 211688 kb
Host smart-a23fe2de-c3d8-4e37-b858-7eb12513d89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234714793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.234714793
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.591422691
Short name T267
Test name
Test status
Simulation time 3282734369 ps
CPU time 14.79 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:10:35 PM PDT 24
Peak memory 210980 kb
Host smart-279ad7d7-d598-41d5-b73d-4806b2d33d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591422691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.591422691
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1582358348
Short name T309
Test name
Test status
Simulation time 2811458802 ps
CPU time 14.76 seconds
Started Jun 10 05:10:24 PM PDT 24
Finished Jun 10 05:10:40 PM PDT 24
Peak memory 212968 kb
Host smart-6e8c5525-ca8b-48ae-9ddb-74163939a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582358348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1582358348
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1821808272
Short name T271
Test name
Test status
Simulation time 370930552 ps
CPU time 19.77 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:10:39 PM PDT 24
Peak memory 214180 kb
Host smart-9213c424-02cb-4425-89c0-79c06a3e5fbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821808272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1821808272
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2674562763
Short name T139
Test name
Test status
Simulation time 426261198 ps
CPU time 7.16 seconds
Started Jun 10 05:10:50 PM PDT 24
Finished Jun 10 05:10:57 PM PDT 24
Peak memory 210736 kb
Host smart-8d95654f-5d59-4990-b33b-4d12127605ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674562763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2674562763
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3198145734
Short name T31
Test name
Test status
Simulation time 326207956386 ps
CPU time 465.46 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:18:07 PM PDT 24
Peak memory 236400 kb
Host smart-420ea90b-31ff-4548-81b9-c2d2c8dd894f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198145734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3198145734
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2510924196
Short name T285
Test name
Test status
Simulation time 2073610474 ps
CPU time 22.63 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:10:44 PM PDT 24
Peak memory 211984 kb
Host smart-d00e7b6e-976e-4b74-b573-435dd9489104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510924196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2510924196
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1645412828
Short name T20
Test name
Test status
Simulation time 98744426 ps
CPU time 5.43 seconds
Started Jun 10 05:10:28 PM PDT 24
Finished Jun 10 05:10:33 PM PDT 24
Peak memory 210872 kb
Host smart-2053d6c8-cfc2-4dcb-8539-013c4d30292f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645412828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1645412828
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2800467537
Short name T177
Test name
Test status
Simulation time 2496687409 ps
CPU time 27.66 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 212788 kb
Host smart-5f40414b-0c92-4ad8-a4bb-7c5a76ca128c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800467537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2800467537
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1111926077
Short name T184
Test name
Test status
Simulation time 1218260703 ps
CPU time 17.15 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:40 PM PDT 24
Peak memory 213216 kb
Host smart-17ca54d4-e33e-4e3e-995c-86fca35b2127
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111926077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1111926077
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3376877623
Short name T23
Test name
Test status
Simulation time 1723208624 ps
CPU time 14.07 seconds
Started Jun 10 05:10:46 PM PDT 24
Finished Jun 10 05:11:01 PM PDT 24
Peak memory 210720 kb
Host smart-f78d5af6-d798-4caf-804e-6ffa07d8def9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376877623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3376877623
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1656221040
Short name T359
Test name
Test status
Simulation time 71270790790 ps
CPU time 244.76 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:14:26 PM PDT 24
Peak memory 212236 kb
Host smart-cc896ae7-5a04-4f73-9834-65eb25ffcad8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656221040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1656221040
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.86928390
Short name T289
Test name
Test status
Simulation time 4144200459 ps
CPU time 33.87 seconds
Started Jun 10 05:10:36 PM PDT 24
Finished Jun 10 05:11:10 PM PDT 24
Peak memory 211588 kb
Host smart-7f01b5f0-f307-461c-b270-60f5da1dc1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86928390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.86928390
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4067446022
Short name T10
Test name
Test status
Simulation time 901943612 ps
CPU time 10.66 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:10:37 PM PDT 24
Peak memory 210924 kb
Host smart-10628161-02a1-475a-9991-64bda96ad830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067446022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4067446022
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2157179283
Short name T283
Test name
Test status
Simulation time 347823624 ps
CPU time 10.01 seconds
Started Jun 10 05:10:43 PM PDT 24
Finished Jun 10 05:10:54 PM PDT 24
Peak memory 213156 kb
Host smart-1e564a9f-93fc-454b-8278-23a54c755292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157179283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2157179283
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1752222648
Short name T326
Test name
Test status
Simulation time 136542495050 ps
CPU time 70.72 seconds
Started Jun 10 05:10:31 PM PDT 24
Finished Jun 10 05:11:42 PM PDT 24
Peak memory 219016 kb
Host smart-a934f6cb-ba14-4038-9e29-ae00279eb44e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752222648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1752222648
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1981922262
Short name T344
Test name
Test status
Simulation time 66657890680 ps
CPU time 2626.52 seconds
Started Jun 10 05:10:27 PM PDT 24
Finished Jun 10 05:54:14 PM PDT 24
Peak memory 230092 kb
Host smart-befecaec-7b3a-419a-878c-06028c65713a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981922262 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1981922262
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3578492377
Short name T255
Test name
Test status
Simulation time 4936678491 ps
CPU time 8.83 seconds
Started Jun 10 05:10:39 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 210768 kb
Host smart-fc7af3dd-6fb0-4866-b32e-a804a59ed28e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578492377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3578492377
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2682241175
Short name T192
Test name
Test status
Simulation time 18055024668 ps
CPU time 152.62 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:12:54 PM PDT 24
Peak memory 233532 kb
Host smart-b35c7642-e111-49d4-9807-b86ab1b94fdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682241175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2682241175
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.554496696
Short name T82
Test name
Test status
Simulation time 7900178984 ps
CPU time 22.59 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:10:43 PM PDT 24
Peak memory 211140 kb
Host smart-f2da5ab9-a775-4b19-95d3-5bdb1b03c86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554496696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.554496696
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3143754047
Short name T216
Test name
Test status
Simulation time 13503232292 ps
CPU time 15.73 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 211040 kb
Host smart-d0e9b66f-decf-4ddc-99b0-0443e40af4f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143754047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3143754047
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3012177582
Short name T250
Test name
Test status
Simulation time 12210345767 ps
CPU time 29.35 seconds
Started Jun 10 05:10:40 PM PDT 24
Finished Jun 10 05:11:10 PM PDT 24
Peak memory 213992 kb
Host smart-08688822-a6cd-4b39-9cc6-6dc9adda1669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012177582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3012177582
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2129364256
Short name T352
Test name
Test status
Simulation time 11080589088 ps
CPU time 33.29 seconds
Started Jun 10 05:10:24 PM PDT 24
Finished Jun 10 05:10:57 PM PDT 24
Peak memory 213676 kb
Host smart-65bb067e-4e1a-41c3-b6ca-8b29ee4a9a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129364256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2129364256
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2375246290
Short name T44
Test name
Test status
Simulation time 36847271412 ps
CPU time 1375.14 seconds
Started Jun 10 05:10:33 PM PDT 24
Finished Jun 10 05:33:29 PM PDT 24
Peak memory 235468 kb
Host smart-6a819016-2c1e-491a-a473-c190192cac95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375246290 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2375246290
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3860863716
Short name T190
Test name
Test status
Simulation time 593223969 ps
CPU time 4.13 seconds
Started Jun 10 05:10:52 PM PDT 24
Finished Jun 10 05:10:56 PM PDT 24
Peak memory 210736 kb
Host smart-61fb12d9-1443-498e-b9e1-a84cabb835b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860863716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3860863716
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1124724619
Short name T25
Test name
Test status
Simulation time 22579697643 ps
CPU time 252.3 seconds
Started Jun 10 05:10:41 PM PDT 24
Finished Jun 10 05:14:54 PM PDT 24
Peak memory 225244 kb
Host smart-b53a16b0-cde8-4cb1-baf1-de6fa8da46fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124724619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1124724619
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.364368315
Short name T81
Test name
Test status
Simulation time 421765825 ps
CPU time 8.6 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 05:10:30 PM PDT 24
Peak memory 210900 kb
Host smart-9f408347-1a22-4068-90f4-e66feda6c248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364368315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.364368315
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.986649361
Short name T334
Test name
Test status
Simulation time 1318153027 ps
CPU time 20.35 seconds
Started Jun 10 05:10:28 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 212828 kb
Host smart-7d153ade-ed58-4279-ba20-e08c22052987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986649361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.986649361
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.226627871
Short name T185
Test name
Test status
Simulation time 6396468538 ps
CPU time 55.96 seconds
Started Jun 10 05:10:33 PM PDT 24
Finished Jun 10 05:11:30 PM PDT 24
Peak memory 215924 kb
Host smart-cdb4cf79-03de-47ac-9782-6ec0dff83620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226627871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.226627871
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2191905856
Short name T189
Test name
Test status
Simulation time 3733096412 ps
CPU time 11.93 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:10:31 PM PDT 24
Peak memory 210792 kb
Host smart-6a718bc4-335a-4eaf-b36b-b4596470fed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191905856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2191905856
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2358489920
Short name T141
Test name
Test status
Simulation time 22564438266 ps
CPU time 208.5 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:13:48 PM PDT 24
Peak memory 212228 kb
Host smart-726c0314-a4e3-4ff3-80d1-638b1209feb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358489920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2358489920
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.158116546
Short name T134
Test name
Test status
Simulation time 3143175706 ps
CPU time 29.2 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 211800 kb
Host smart-a37ed421-b431-4145-8c1d-6a7b9039b024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158116546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.158116546
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2608551626
Short name T153
Test name
Test status
Simulation time 1485149884 ps
CPU time 14.01 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:10:41 PM PDT 24
Peak memory 210992 kb
Host smart-6e817302-ba73-41af-9548-cac845d1b685
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608551626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2608551626
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3308371878
Short name T117
Test name
Test status
Simulation time 7159578468 ps
CPU time 31.29 seconds
Started Jun 10 05:10:30 PM PDT 24
Finished Jun 10 05:11:02 PM PDT 24
Peak memory 214320 kb
Host smart-5f8f30c5-abe4-4272-aff2-a15ab667a271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308371878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3308371878
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.507813430
Short name T277
Test name
Test status
Simulation time 808240177 ps
CPU time 12.05 seconds
Started Jun 10 05:10:42 PM PDT 24
Finished Jun 10 05:10:54 PM PDT 24
Peak memory 214556 kb
Host smart-41446189-198e-4015-a594-960c1a4126ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507813430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.507813430
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2377813853
Short name T236
Test name
Test status
Simulation time 20426862112 ps
CPU time 14.48 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:10:34 PM PDT 24
Peak memory 210824 kb
Host smart-094e6f73-a318-4ef3-af6a-333342aaf885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377813853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2377813853
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3306801432
Short name T30
Test name
Test status
Simulation time 364916694658 ps
CPU time 413.13 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:17:20 PM PDT 24
Peak memory 212804 kb
Host smart-2adc79d2-8652-4a7a-ac6f-7a127373dc07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306801432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3306801432
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2776042483
Short name T298
Test name
Test status
Simulation time 2214556392 ps
CPU time 22.89 seconds
Started Jun 10 05:10:39 PM PDT 24
Finished Jun 10 05:11:02 PM PDT 24
Peak memory 211568 kb
Host smart-6419347b-06bd-4a63-9537-855239d1fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776042483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2776042483
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1307458840
Short name T336
Test name
Test status
Simulation time 4983163031 ps
CPU time 14.33 seconds
Started Jun 10 05:10:59 PM PDT 24
Finished Jun 10 05:11:14 PM PDT 24
Peak memory 211036 kb
Host smart-50b02d19-c0ac-4b53-a30a-898c4cb03245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307458840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1307458840
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.423904701
Short name T339
Test name
Test status
Simulation time 6535572566 ps
CPU time 22.87 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:10:50 PM PDT 24
Peak memory 214156 kb
Host smart-e5f0f6bf-1626-41c1-9150-37c57305aa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423904701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.423904701
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1142430496
Short name T247
Test name
Test status
Simulation time 392295572 ps
CPU time 24.51 seconds
Started Jun 10 05:10:36 PM PDT 24
Finished Jun 10 05:11:01 PM PDT 24
Peak memory 214968 kb
Host smart-2756bb10-46bb-4df7-a098-a4ee89660325
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142430496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1142430496
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1214977738
Short name T322
Test name
Test status
Simulation time 2672170307 ps
CPU time 12.42 seconds
Started Jun 10 05:10:14 PM PDT 24
Finished Jun 10 05:10:27 PM PDT 24
Peak memory 210804 kb
Host smart-1cdf30f9-5315-490a-add0-0583ceea4509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214977738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1214977738
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1311634031
Short name T147
Test name
Test status
Simulation time 5435395699 ps
CPU time 69.58 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:11:29 PM PDT 24
Peak memory 237476 kb
Host smart-368a6b45-d8af-4245-8265-7b29612983cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311634031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1311634031
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1419096205
Short name T170
Test name
Test status
Simulation time 1069009171 ps
CPU time 16.59 seconds
Started Jun 10 05:10:08 PM PDT 24
Finished Jun 10 05:10:25 PM PDT 24
Peak memory 211656 kb
Host smart-38b82984-649b-4d2c-be2f-0f547aeede8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419096205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1419096205
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2925271649
Short name T353
Test name
Test status
Simulation time 7800168084 ps
CPU time 17.52 seconds
Started Jun 10 05:10:17 PM PDT 24
Finished Jun 10 05:10:35 PM PDT 24
Peak memory 211012 kb
Host smart-8c996c5b-51c7-4c3f-b75b-7eb1a461b923
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925271649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2925271649
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3103401600
Short name T29
Test name
Test status
Simulation time 1573088231 ps
CPU time 104.54 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:12:03 PM PDT 24
Peak memory 236492 kb
Host smart-1be182a6-7967-46be-870a-31f79f7349fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103401600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3103401600
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1380318153
Short name T17
Test name
Test status
Simulation time 16794874765 ps
CPU time 35.12 seconds
Started Jun 10 05:10:12 PM PDT 24
Finished Jun 10 05:10:47 PM PDT 24
Peak memory 214536 kb
Host smart-fc93a146-ae29-4ddb-8db0-4fe61fec72d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380318153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1380318153
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2502926705
Short name T342
Test name
Test status
Simulation time 21645202197 ps
CPU time 52.19 seconds
Started Jun 10 05:10:34 PM PDT 24
Finished Jun 10 05:11:27 PM PDT 24
Peak memory 214908 kb
Host smart-4e624994-af19-4039-ae58-e24e5499e188
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502926705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2502926705
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2699392299
Short name T249
Test name
Test status
Simulation time 2152034564 ps
CPU time 10.65 seconds
Started Jun 10 05:10:59 PM PDT 24
Finished Jun 10 05:11:10 PM PDT 24
Peak memory 210776 kb
Host smart-7ea2a766-6055-4aac-8dfc-3708942d3b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699392299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2699392299
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1836852599
Short name T195
Test name
Test status
Simulation time 2110136098 ps
CPU time 93.4 seconds
Started Jun 10 05:10:57 PM PDT 24
Finished Jun 10 05:12:31 PM PDT 24
Peak memory 237276 kb
Host smart-54d6ceda-c3ac-4e89-8fc8-cc09ce363fb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836852599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1836852599
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2991735382
Short name T262
Test name
Test status
Simulation time 2429746054 ps
CPU time 24.35 seconds
Started Jun 10 05:10:40 PM PDT 24
Finished Jun 10 05:11:04 PM PDT 24
Peak memory 211780 kb
Host smart-d9016021-ed56-4809-a8f3-2485110e12a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991735382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2991735382
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1544929117
Short name T288
Test name
Test status
Simulation time 773509035 ps
CPU time 9.97 seconds
Started Jun 10 05:10:41 PM PDT 24
Finished Jun 10 05:10:52 PM PDT 24
Peak memory 210912 kb
Host smart-eef7e80a-4003-4434-b0f8-32e47facb35d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544929117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1544929117
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1207297101
Short name T173
Test name
Test status
Simulation time 28374953856 ps
CPU time 38.41 seconds
Started Jun 10 05:10:24 PM PDT 24
Finished Jun 10 05:11:03 PM PDT 24
Peak memory 214268 kb
Host smart-5d6571da-4a88-4079-967d-1b3a1dcc19fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207297101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1207297101
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3296280587
Short name T263
Test name
Test status
Simulation time 5907845914 ps
CPU time 56.09 seconds
Started Jun 10 05:10:28 PM PDT 24
Finished Jun 10 05:11:24 PM PDT 24
Peak memory 213488 kb
Host smart-2b4d772f-5160-4336-8d67-34460cb93531
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296280587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3296280587
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2144961240
Short name T169
Test name
Test status
Simulation time 3786053701 ps
CPU time 10.12 seconds
Started Jun 10 05:11:02 PM PDT 24
Finished Jun 10 05:11:12 PM PDT 24
Peak memory 210836 kb
Host smart-d71a3569-786c-4c4f-883e-0ad9c02d4237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144961240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2144961240
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4093518550
Short name T211
Test name
Test status
Simulation time 68127965411 ps
CPU time 251.14 seconds
Started Jun 10 05:10:25 PM PDT 24
Finished Jun 10 05:14:36 PM PDT 24
Peak memory 237440 kb
Host smart-e00ef239-8dcc-45ec-8961-8b72e7def33f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093518550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4093518550
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2859404033
Short name T341
Test name
Test status
Simulation time 348197820 ps
CPU time 9.33 seconds
Started Jun 10 05:10:40 PM PDT 24
Finished Jun 10 05:10:50 PM PDT 24
Peak memory 211676 kb
Host smart-5a9eea9e-ee20-4188-995a-a64be4c8fffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859404033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2859404033
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.754547524
Short name T307
Test name
Test status
Simulation time 383871726 ps
CPU time 8.68 seconds
Started Jun 10 05:10:25 PM PDT 24
Finished Jun 10 05:10:34 PM PDT 24
Peak memory 210920 kb
Host smart-2996bc87-c12d-4e23-bfe6-aac5b147d7ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754547524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.754547524
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1614533178
Short name T158
Test name
Test status
Simulation time 2872047688 ps
CPU time 24.63 seconds
Started Jun 10 05:10:43 PM PDT 24
Finished Jun 10 05:11:08 PM PDT 24
Peak memory 213636 kb
Host smart-2f6e49b7-2b60-4d81-8c83-43a65141c69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614533178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1614533178
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2591729788
Short name T308
Test name
Test status
Simulation time 299746499 ps
CPU time 9.39 seconds
Started Jun 10 05:10:48 PM PDT 24
Finished Jun 10 05:10:58 PM PDT 24
Peak memory 211564 kb
Host smart-a5f17834-57f4-49d8-a5a8-cddc29097075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591729788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2591729788
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3839771851
Short name T157
Test name
Test status
Simulation time 3014716484 ps
CPU time 8.56 seconds
Started Jun 10 05:10:30 PM PDT 24
Finished Jun 10 05:10:39 PM PDT 24
Peak memory 210812 kb
Host smart-4d6e784c-713f-4598-a027-542829a46253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839771851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3839771851
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2697599864
Short name T224
Test name
Test status
Simulation time 33240421106 ps
CPU time 101.01 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:12:08 PM PDT 24
Peak memory 212712 kb
Host smart-e663ce0d-676d-4e96-9a53-98eff6927ab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697599864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2697599864
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.799744126
Short name T121
Test name
Test status
Simulation time 678347728 ps
CPU time 11.31 seconds
Started Jun 10 05:10:23 PM PDT 24
Finished Jun 10 05:10:35 PM PDT 24
Peak memory 211592 kb
Host smart-fe2cbbe4-241a-4171-afeb-c17173f5c60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799744126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.799744126
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.280880353
Short name T125
Test name
Test status
Simulation time 6278737206 ps
CPU time 14.71 seconds
Started Jun 10 05:10:44 PM PDT 24
Finished Jun 10 05:10:59 PM PDT 24
Peak memory 211020 kb
Host smart-1de541e0-3ed7-499d-a445-55163fbe6a1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280880353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.280880353
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2886754305
Short name T331
Test name
Test status
Simulation time 352983610 ps
CPU time 10.22 seconds
Started Jun 10 05:10:55 PM PDT 24
Finished Jun 10 05:11:05 PM PDT 24
Peak memory 212152 kb
Host smart-2986e121-ca08-4442-8cc7-4f5e4a3f3f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886754305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2886754305
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2987281359
Short name T162
Test name
Test status
Simulation time 2921475459 ps
CPU time 16.5 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:10:43 PM PDT 24
Peak memory 211756 kb
Host smart-ddca5943-6072-4075-b564-7379848ee1da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987281359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2987281359
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1456787287
Short name T27
Test name
Test status
Simulation time 5103139216 ps
CPU time 11.99 seconds
Started Jun 10 05:10:50 PM PDT 24
Finished Jun 10 05:11:02 PM PDT 24
Peak memory 210836 kb
Host smart-e66b2363-5d42-4045-98e8-77feb96cf6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456787287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1456787287
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3047891168
Short name T201
Test name
Test status
Simulation time 2420389725 ps
CPU time 170.98 seconds
Started Jun 10 05:10:34 PM PDT 24
Finished Jun 10 05:13:25 PM PDT 24
Peak memory 237508 kb
Host smart-9d3100f0-431b-4c35-8935-d7dbb921ee4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047891168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3047891168
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3050931366
Short name T80
Test name
Test status
Simulation time 13190957650 ps
CPU time 30.54 seconds
Started Jun 10 05:10:30 PM PDT 24
Finished Jun 10 05:11:00 PM PDT 24
Peak memory 211824 kb
Host smart-23a26711-c1d7-4d65-9eb0-7c7970e6645b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050931366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3050931366
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1128087826
Short name T146
Test name
Test status
Simulation time 7609710342 ps
CPU time 16.02 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 211040 kb
Host smart-762e4754-2ac6-416d-b605-e9b2218b21d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128087826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1128087826
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4153801825
Short name T159
Test name
Test status
Simulation time 17508482446 ps
CPU time 22.15 seconds
Started Jun 10 05:10:28 PM PDT 24
Finished Jun 10 05:10:51 PM PDT 24
Peak memory 214064 kb
Host smart-fa1dbf3c-8243-4298-be21-10d766f622e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153801825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4153801825
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.472271613
Short name T264
Test name
Test status
Simulation time 446566333 ps
CPU time 25.66 seconds
Started Jun 10 05:11:01 PM PDT 24
Finished Jun 10 05:11:27 PM PDT 24
Peak memory 215152 kb
Host smart-f4c7f4a5-2ea7-4ee0-a33c-a7d066821118
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472271613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.472271613
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1124198404
Short name T351
Test name
Test status
Simulation time 212683701560 ps
CPU time 2064.23 seconds
Started Jun 10 05:10:30 PM PDT 24
Finished Jun 10 05:44:58 PM PDT 24
Peak memory 237660 kb
Host smart-1180ae49-2a62-4b02-9c63-656c5cc1e2cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124198404 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1124198404
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1530438362
Short name T337
Test name
Test status
Simulation time 11433285513 ps
CPU time 10.78 seconds
Started Jun 10 05:10:43 PM PDT 24
Finished Jun 10 05:10:54 PM PDT 24
Peak memory 210836 kb
Host smart-82610c98-aa6e-4b17-b61c-2f4ab14ae771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530438362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1530438362
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1819027259
Short name T281
Test name
Test status
Simulation time 18274532457 ps
CPU time 83.59 seconds
Started Jun 10 05:10:23 PM PDT 24
Finished Jun 10 05:11:47 PM PDT 24
Peak memory 227752 kb
Host smart-79b85bbe-32fb-4a79-a8b9-98281840bc5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819027259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1819027259
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1605068688
Short name T36
Test name
Test status
Simulation time 666166820 ps
CPU time 9.79 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:10:30 PM PDT 24
Peak memory 211560 kb
Host smart-8aa8ec4f-14df-4f3a-9c40-01b2cc0ea4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605068688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1605068688
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2254665345
Short name T197
Test name
Test status
Simulation time 12017443207 ps
CPU time 14.08 seconds
Started Jun 10 05:10:38 PM PDT 24
Finished Jun 10 05:10:53 PM PDT 24
Peak memory 210996 kb
Host smart-289e720f-0272-43ad-80ca-cea3bbefe554
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254665345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2254665345
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3375843384
Short name T140
Test name
Test status
Simulation time 2945932400 ps
CPU time 26.47 seconds
Started Jun 10 05:10:49 PM PDT 24
Finished Jun 10 05:11:16 PM PDT 24
Peak memory 213624 kb
Host smart-355f1b6e-4838-491c-a33a-8244fd08a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375843384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3375843384
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2940812382
Short name T119
Test name
Test status
Simulation time 3434243125 ps
CPU time 10.99 seconds
Started Jun 10 05:10:48 PM PDT 24
Finished Jun 10 05:10:59 PM PDT 24
Peak memory 210916 kb
Host smart-320fe001-778d-4c6c-ac55-e8778a9cf1a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940812382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2940812382
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2457975931
Short name T327
Test name
Test status
Simulation time 32239305126 ps
CPU time 8928.58 seconds
Started Jun 10 05:10:50 PM PDT 24
Finished Jun 10 07:39:40 PM PDT 24
Peak memory 235488 kb
Host smart-9338d447-6ec2-4557-858b-473b7df59f2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457975931 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2457975931
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2520897956
Short name T270
Test name
Test status
Simulation time 4733444077 ps
CPU time 12.07 seconds
Started Jun 10 05:10:25 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 210800 kb
Host smart-46be5b23-d794-4351-bc47-a69a5cf67e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520897956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2520897956
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2884455442
Short name T149
Test name
Test status
Simulation time 71605389569 ps
CPU time 176.04 seconds
Started Jun 10 05:10:40 PM PDT 24
Finished Jun 10 05:13:36 PM PDT 24
Peak memory 237444 kb
Host smart-a0a53137-750f-42d3-83c0-e596ae7a088a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884455442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2884455442
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.635286232
Short name T35
Test name
Test status
Simulation time 341682920 ps
CPU time 9.24 seconds
Started Jun 10 05:10:47 PM PDT 24
Finished Jun 10 05:10:57 PM PDT 24
Peak memory 211712 kb
Host smart-8ec929f3-f678-4f53-bc8a-8fa1b39e6392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635286232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.635286232
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3100143824
Short name T260
Test name
Test status
Simulation time 315168141 ps
CPU time 7.51 seconds
Started Jun 10 05:10:28 PM PDT 24
Finished Jun 10 05:10:36 PM PDT 24
Peak memory 210908 kb
Host smart-6d73a644-c55e-4205-9fea-ebd10b8658ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100143824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3100143824
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4254498166
Short name T45
Test name
Test status
Simulation time 183204636 ps
CPU time 10.45 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:33 PM PDT 24
Peak memory 211892 kb
Host smart-76115439-fc6f-478d-8eb0-4dd53c738c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254498166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4254498166
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2098346907
Short name T183
Test name
Test status
Simulation time 1107956573 ps
CPU time 15.99 seconds
Started Jun 10 05:10:28 PM PDT 24
Finished Jun 10 05:10:44 PM PDT 24
Peak memory 213536 kb
Host smart-235144d1-57ff-4862-9c0a-1758bc20ef73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098346907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2098346907
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1842433077
Short name T191
Test name
Test status
Simulation time 5824815857 ps
CPU time 14.84 seconds
Started Jun 10 05:10:23 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 210932 kb
Host smart-bd3552b7-99ff-4876-bb08-6c6e9627b8b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842433077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1842433077
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.706386628
Short name T32
Test name
Test status
Simulation time 9129399241 ps
CPU time 137.68 seconds
Started Jun 10 05:10:25 PM PDT 24
Finished Jun 10 05:12:43 PM PDT 24
Peak memory 228284 kb
Host smart-7def18a3-3dca-4a67-88eb-bbe36ba981d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706386628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.706386628
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2841151972
Short name T120
Test name
Test status
Simulation time 1094363481 ps
CPU time 16.62 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:10:43 PM PDT 24
Peak memory 211568 kb
Host smart-8b5fed24-6666-4526-9d3b-60a365d0b1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841151972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2841151972
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4205910885
Short name T214
Test name
Test status
Simulation time 1529676662 ps
CPU time 14.01 seconds
Started Jun 10 05:10:36 PM PDT 24
Finished Jun 10 05:10:50 PM PDT 24
Peak memory 210912 kb
Host smart-ce2f9d66-1274-461c-b42d-3d8193b929b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205910885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4205910885
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2483481525
Short name T123
Test name
Test status
Simulation time 24090854842 ps
CPU time 32.85 seconds
Started Jun 10 05:10:42 PM PDT 24
Finished Jun 10 05:11:16 PM PDT 24
Peak memory 213836 kb
Host smart-94d35744-82ac-4dd7-9168-3a263bea604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483481525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2483481525
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1560336252
Short name T303
Test name
Test status
Simulation time 35775493794 ps
CPU time 82.23 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:11:43 PM PDT 24
Peak memory 217076 kb
Host smart-20291a9c-768c-4755-bf42-eb50518b07b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560336252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1560336252
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1225724568
Short name T15
Test name
Test status
Simulation time 128503599026 ps
CPU time 2379.13 seconds
Started Jun 10 05:10:41 PM PDT 24
Finished Jun 10 05:50:21 PM PDT 24
Peak memory 243744 kb
Host smart-4139fdcc-b54f-4dd5-a034-23100470b320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225724568 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1225724568
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1009413464
Short name T306
Test name
Test status
Simulation time 5305791794 ps
CPU time 11.09 seconds
Started Jun 10 05:10:27 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 210832 kb
Host smart-c3985b24-62ab-479c-bd5b-f2136db8cd1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009413464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1009413464
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1198492086
Short name T138
Test name
Test status
Simulation time 15967880018 ps
CPU time 189.51 seconds
Started Jun 10 05:10:44 PM PDT 24
Finished Jun 10 05:13:54 PM PDT 24
Peak memory 237456 kb
Host smart-fae27e7b-bc9c-410c-b1e1-1f1bc2675fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198492086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1198492086
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4104887216
Short name T3
Test name
Test status
Simulation time 6840632746 ps
CPU time 19.37 seconds
Started Jun 10 05:10:48 PM PDT 24
Finished Jun 10 05:11:08 PM PDT 24
Peak memory 212088 kb
Host smart-37470799-8a90-4c6f-a29f-534baa3b1307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104887216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4104887216
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2935527593
Short name T13
Test name
Test status
Simulation time 2649862299 ps
CPU time 9.54 seconds
Started Jun 10 05:10:49 PM PDT 24
Finished Jun 10 05:10:59 PM PDT 24
Peak memory 210952 kb
Host smart-16445dfd-e4ed-4d4f-80fc-e4573768838e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2935527593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2935527593
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3411200391
Short name T150
Test name
Test status
Simulation time 51229836430 ps
CPU time 35.53 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:11:02 PM PDT 24
Peak memory 214024 kb
Host smart-82839891-1f49-41f5-8cb7-aba1117923c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411200391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3411200391
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.839136605
Short name T166
Test name
Test status
Simulation time 32224762348 ps
CPU time 77.68 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:11:40 PM PDT 24
Peak memory 215668 kb
Host smart-a22d6db5-99ce-454a-b1fe-dcee7bf82134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839136605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.839136605
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2423741145
Short name T360
Test name
Test status
Simulation time 4266921493 ps
CPU time 10.76 seconds
Started Jun 10 05:10:45 PM PDT 24
Finished Jun 10 05:10:56 PM PDT 24
Peak memory 210784 kb
Host smart-3cbdb9e0-d735-4a6a-9e06-6e4be118e462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423741145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2423741145
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2950688593
Short name T363
Test name
Test status
Simulation time 4703812021 ps
CPU time 144.93 seconds
Started Jun 10 05:10:37 PM PDT 24
Finished Jun 10 05:13:02 PM PDT 24
Peak memory 234592 kb
Host smart-865b1bfa-57b8-40fc-ba16-e91ea976bf36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950688593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2950688593
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4065881249
Short name T335
Test name
Test status
Simulation time 5654728759 ps
CPU time 26.7 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:10:53 PM PDT 24
Peak memory 212176 kb
Host smart-da21f86d-bd56-4f3e-8aaf-2bbd0f4a1848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065881249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4065881249
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3509927714
Short name T199
Test name
Test status
Simulation time 4177445316 ps
CPU time 17.91 seconds
Started Jun 10 05:10:33 PM PDT 24
Finished Jun 10 05:10:51 PM PDT 24
Peak memory 210972 kb
Host smart-a0703a63-002c-41a0-ab9c-dce25033cd4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509927714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3509927714
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1309620804
Short name T276
Test name
Test status
Simulation time 7724958282 ps
CPU time 33.51 seconds
Started Jun 10 05:10:44 PM PDT 24
Finished Jun 10 05:11:18 PM PDT 24
Peak memory 213744 kb
Host smart-1a798f53-57f5-4126-83f5-8361b99819fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309620804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1309620804
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3139642252
Short name T65
Test name
Test status
Simulation time 6053474387 ps
CPU time 71.83 seconds
Started Jun 10 05:10:35 PM PDT 24
Finished Jun 10 05:11:47 PM PDT 24
Peak memory 219004 kb
Host smart-aa3d3026-b944-41cf-9107-aeb9e3b9d2a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139642252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3139642252
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1156925692
Short name T348
Test name
Test status
Simulation time 116529575641 ps
CPU time 3107 seconds
Started Jun 10 05:10:28 PM PDT 24
Finished Jun 10 06:02:16 PM PDT 24
Peak memory 235436 kb
Host smart-90cda108-5708-4cdf-b562-5755e299b2d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156925692 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1156925692
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3828644490
Short name T220
Test name
Test status
Simulation time 4128045137 ps
CPU time 10.24 seconds
Started Jun 10 05:10:37 PM PDT 24
Finished Jun 10 05:10:47 PM PDT 24
Peak memory 210812 kb
Host smart-4a5002f9-bebf-4492-8c5e-845e90e5b80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828644490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3828644490
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.429263426
Short name T128
Test name
Test status
Simulation time 16997304858 ps
CPU time 95.16 seconds
Started Jun 10 05:10:29 PM PDT 24
Finished Jun 10 05:12:05 PM PDT 24
Peak memory 234904 kb
Host smart-10be1742-6167-4da2-814f-1a12036ac13e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429263426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.429263426
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3071495958
Short name T144
Test name
Test status
Simulation time 2397484947 ps
CPU time 13.5 seconds
Started Jun 10 05:10:47 PM PDT 24
Finished Jun 10 05:11:01 PM PDT 24
Peak memory 211504 kb
Host smart-d2401f2b-db56-418e-867f-c0a5416e5a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071495958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3071495958
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1580839113
Short name T98
Test name
Test status
Simulation time 2780740796 ps
CPU time 9.61 seconds
Started Jun 10 05:10:39 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 210976 kb
Host smart-f8a2a903-03b6-43cf-acde-46bbf6b87942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580839113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1580839113
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2371751385
Short name T332
Test name
Test status
Simulation time 3604243057 ps
CPU time 29.92 seconds
Started Jun 10 05:10:50 PM PDT 24
Finished Jun 10 05:11:21 PM PDT 24
Peak memory 212932 kb
Host smart-c394d801-fc50-44b3-920d-bc531f5d0c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371751385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2371751385
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3725779338
Short name T258
Test name
Test status
Simulation time 6511536535 ps
CPU time 30.37 seconds
Started Jun 10 05:10:51 PM PDT 24
Finished Jun 10 05:11:22 PM PDT 24
Peak memory 215232 kb
Host smart-9130286f-1648-4b8d-b6ba-6323c47c7be6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725779338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3725779338
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2536123675
Short name T53
Test name
Test status
Simulation time 2148259055 ps
CPU time 17.15 seconds
Started Jun 10 05:10:08 PM PDT 24
Finished Jun 10 05:10:25 PM PDT 24
Peak memory 210812 kb
Host smart-bff6d3ab-b117-43a6-89f7-eb939b17df64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536123675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2536123675
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1668648444
Short name T243
Test name
Test status
Simulation time 2229981565 ps
CPU time 141.45 seconds
Started Jun 10 05:10:16 PM PDT 24
Finished Jun 10 05:12:38 PM PDT 24
Peak memory 237388 kb
Host smart-4b73d9ab-0fbf-41fc-910f-b862f4fb99a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668648444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1668648444
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3452649842
Short name T347
Test name
Test status
Simulation time 17120494579 ps
CPU time 35.05 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:10:54 PM PDT 24
Peak memory 211028 kb
Host smart-54eff51d-8a26-45af-b079-8fef454c7856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452649842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3452649842
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1885996677
Short name T282
Test name
Test status
Simulation time 1403510385 ps
CPU time 8.15 seconds
Started Jun 10 05:10:16 PM PDT 24
Finished Jun 10 05:10:25 PM PDT 24
Peak memory 210928 kb
Host smart-53dae269-12a0-427c-884e-960485c77c2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885996677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1885996677
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.294921996
Short name T26
Test name
Test status
Simulation time 1103165710 ps
CPU time 59.84 seconds
Started Jun 10 05:10:27 PM PDT 24
Finished Jun 10 05:11:27 PM PDT 24
Peak memory 237228 kb
Host smart-52cd856f-dbe1-445f-86c9-9b18f0f80caa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294921996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.294921996
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1754527049
Short name T244
Test name
Test status
Simulation time 2401173847 ps
CPU time 29.36 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:41 PM PDT 24
Peak memory 212940 kb
Host smart-44129904-d7cb-4aa3-a788-518f98a84276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754527049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1754527049
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2778619512
Short name T19
Test name
Test status
Simulation time 4633682539 ps
CPU time 52 seconds
Started Jun 10 05:10:07 PM PDT 24
Finished Jun 10 05:10:59 PM PDT 24
Peak memory 215052 kb
Host smart-1fd22b7e-0d1d-428e-a5a1-cf3c964d8784
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778619512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2778619512
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.103221822
Short name T40
Test name
Test status
Simulation time 92953314884 ps
CPU time 794.89 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 05:23:30 PM PDT 24
Peak memory 235520 kb
Host smart-3d0144db-6b15-4c66-9ccc-e9dd8d467d9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103221822 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.103221822
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1305433124
Short name T178
Test name
Test status
Simulation time 1473636664 ps
CPU time 13.57 seconds
Started Jun 10 05:10:35 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 210724 kb
Host smart-c9f481b4-aaed-4006-9d1d-64d650fa891c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305433124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1305433124
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1020916280
Short name T362
Test name
Test status
Simulation time 1048288241 ps
CPU time 78.95 seconds
Started Jun 10 05:10:31 PM PDT 24
Finished Jun 10 05:11:50 PM PDT 24
Peak memory 228160 kb
Host smart-d7d0bd63-3e08-4594-beef-b8c1dee241ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020916280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1020916280
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3055899882
Short name T338
Test name
Test status
Simulation time 1589661899 ps
CPU time 19.92 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:10:46 PM PDT 24
Peak memory 211612 kb
Host smart-f94dbbc2-9c16-4d6c-af8f-5b87bb080da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055899882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3055899882
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.657492615
Short name T325
Test name
Test status
Simulation time 4934899532 ps
CPU time 13 seconds
Started Jun 10 05:10:45 PM PDT 24
Finished Jun 10 05:10:59 PM PDT 24
Peak memory 211036 kb
Host smart-fce8f4b1-7224-4110-bfb8-933700d5a9b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657492615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.657492615
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.4179313597
Short name T186
Test name
Test status
Simulation time 2632351250 ps
CPU time 31.61 seconds
Started Jun 10 05:10:32 PM PDT 24
Finished Jun 10 05:11:04 PM PDT 24
Peak memory 213708 kb
Host smart-ee68746d-988a-4985-aefe-219af3109e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179313597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.4179313597
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.763764785
Short name T221
Test name
Test status
Simulation time 8429937323 ps
CPU time 73.88 seconds
Started Jun 10 05:10:30 PM PDT 24
Finished Jun 10 05:11:44 PM PDT 24
Peak memory 217048 kb
Host smart-fe33266a-02fd-47a0-aaeb-3d2008437727
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763764785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.763764785
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2272365828
Short name T292
Test name
Test status
Simulation time 974998815 ps
CPU time 10.32 seconds
Started Jun 10 05:10:27 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 210748 kb
Host smart-0359d8c1-c9e8-47b4-9394-d3eb88323fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272365828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2272365828
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3664077583
Short name T24
Test name
Test status
Simulation time 7018300483 ps
CPU time 124.93 seconds
Started Jun 10 05:10:52 PM PDT 24
Finished Jun 10 05:12:58 PM PDT 24
Peak memory 237520 kb
Host smart-06d01925-b38a-4745-8e9d-cad319ab31e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664077583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3664077583
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2782211949
Short name T137
Test name
Test status
Simulation time 1798345621 ps
CPU time 21.75 seconds
Started Jun 10 05:10:27 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 211620 kb
Host smart-a61487a9-af8b-4105-a5c6-71b67ce63122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782211949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2782211949
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2936696999
Short name T357
Test name
Test status
Simulation time 1721901628 ps
CPU time 10.93 seconds
Started Jun 10 05:10:36 PM PDT 24
Finished Jun 10 05:10:48 PM PDT 24
Peak memory 210904 kb
Host smart-cb79a9c6-2608-4834-a195-8bd81a4a1a50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936696999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2936696999
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2705867953
Short name T278
Test name
Test status
Simulation time 2809089974 ps
CPU time 27.17 seconds
Started Jun 10 05:10:49 PM PDT 24
Finished Jun 10 05:11:17 PM PDT 24
Peak memory 213428 kb
Host smart-e43cea15-d97d-4bb6-b165-eb4a0fbbee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705867953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2705867953
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.421494434
Short name T240
Test name
Test status
Simulation time 3233205714 ps
CPU time 35.58 seconds
Started Jun 10 05:10:30 PM PDT 24
Finished Jun 10 05:11:06 PM PDT 24
Peak memory 214324 kb
Host smart-4fc274c9-3064-4cbd-b045-81ff23b8d834
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421494434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.421494434
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.711420897
Short name T294
Test name
Test status
Simulation time 85574273 ps
CPU time 4.35 seconds
Started Jun 10 05:10:28 PM PDT 24
Finished Jun 10 05:10:33 PM PDT 24
Peak memory 210732 kb
Host smart-f2202172-d3c9-47fb-a5c0-ec48a95bd408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711420897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.711420897
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3236208316
Short name T316
Test name
Test status
Simulation time 48694489442 ps
CPU time 461.67 seconds
Started Jun 10 05:10:31 PM PDT 24
Finished Jun 10 05:18:13 PM PDT 24
Peak memory 213272 kb
Host smart-310c4fac-dbbc-4a69-bfa9-fcc281f10b1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236208316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3236208316
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3070749881
Short name T233
Test name
Test status
Simulation time 8516302225 ps
CPU time 32.67 seconds
Started Jun 10 05:10:43 PM PDT 24
Finished Jun 10 05:11:16 PM PDT 24
Peak memory 212100 kb
Host smart-b80caeb5-cb73-4395-9afa-e5621be48313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070749881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3070749881
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3413779046
Short name T210
Test name
Test status
Simulation time 4356061322 ps
CPU time 11.05 seconds
Started Jun 10 05:10:32 PM PDT 24
Finished Jun 10 05:10:43 PM PDT 24
Peak memory 211040 kb
Host smart-643c70b7-0922-49e6-ae5e-c4349387ccf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413779046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3413779046
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1139893112
Short name T161
Test name
Test status
Simulation time 6073001501 ps
CPU time 27.92 seconds
Started Jun 10 05:10:26 PM PDT 24
Finished Jun 10 05:10:54 PM PDT 24
Peak memory 213116 kb
Host smart-2f62e197-9952-4692-86d4-355931ded127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139893112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1139893112
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1363110753
Short name T69
Test name
Test status
Simulation time 221170040 ps
CPU time 13.31 seconds
Started Jun 10 05:10:31 PM PDT 24
Finished Jun 10 05:10:46 PM PDT 24
Peak memory 214632 kb
Host smart-394f4f77-e03a-4e6c-91cc-f5d030c95fc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363110753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1363110753
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2548753357
Short name T330
Test name
Test status
Simulation time 1926246773 ps
CPU time 15.26 seconds
Started Jun 10 05:10:39 PM PDT 24
Finished Jun 10 05:10:54 PM PDT 24
Peak memory 210724 kb
Host smart-374258fa-5463-4b92-a360-79000dee3b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548753357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2548753357
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3708547131
Short name T230
Test name
Test status
Simulation time 12905849465 ps
CPU time 155.05 seconds
Started Jun 10 05:10:31 PM PDT 24
Finished Jun 10 05:13:06 PM PDT 24
Peak memory 227772 kb
Host smart-e3eac927-724c-498d-93d9-64651be9bd67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708547131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3708547131
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.718499764
Short name T132
Test name
Test status
Simulation time 50598894013 ps
CPU time 29.93 seconds
Started Jun 10 05:10:32 PM PDT 24
Finished Jun 10 05:11:03 PM PDT 24
Peak memory 212032 kb
Host smart-088fc7bd-b863-4510-8a6d-1a7cca07ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718499764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.718499764
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1995201810
Short name T358
Test name
Test status
Simulation time 1832214241 ps
CPU time 16.72 seconds
Started Jun 10 05:10:35 PM PDT 24
Finished Jun 10 05:10:52 PM PDT 24
Peak memory 210892 kb
Host smart-e68b5404-b250-40d8-b7c1-0f45323cd75b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995201810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1995201810
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1506038262
Short name T21
Test name
Test status
Simulation time 13009089051 ps
CPU time 31.54 seconds
Started Jun 10 05:10:42 PM PDT 24
Finished Jun 10 05:11:14 PM PDT 24
Peak memory 214228 kb
Host smart-a08ad7d7-84c2-4c71-996d-16b9d278868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506038262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1506038262
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2370406926
Short name T231
Test name
Test status
Simulation time 15153847573 ps
CPU time 32.25 seconds
Started Jun 10 05:10:28 PM PDT 24
Finished Jun 10 05:11:01 PM PDT 24
Peak memory 214276 kb
Host smart-41f2ebe4-65dd-4f50-9488-b1866fc54c22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370406926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2370406926
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3838684546
Short name T198
Test name
Test status
Simulation time 1603138248 ps
CPU time 14.12 seconds
Started Jun 10 05:10:44 PM PDT 24
Finished Jun 10 05:10:58 PM PDT 24
Peak memory 210676 kb
Host smart-2ab53024-b088-4a31-b6cb-7f16b285cf68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838684546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3838684546
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2061054557
Short name T124
Test name
Test status
Simulation time 5154867528 ps
CPU time 105.94 seconds
Started Jun 10 05:10:45 PM PDT 24
Finished Jun 10 05:12:31 PM PDT 24
Peak memory 212188 kb
Host smart-b5298f41-f036-4847-a809-80cb9e1d2adf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061054557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2061054557
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.481745767
Short name T133
Test name
Test status
Simulation time 1638492508 ps
CPU time 15.44 seconds
Started Jun 10 05:10:49 PM PDT 24
Finished Jun 10 05:11:05 PM PDT 24
Peak memory 211560 kb
Host smart-4b594a86-5aa2-4446-bdbb-a7548115561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481745767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.481745767
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3326747264
Short name T300
Test name
Test status
Simulation time 1428519846 ps
CPU time 13.91 seconds
Started Jun 10 05:10:51 PM PDT 24
Finished Jun 10 05:11:05 PM PDT 24
Peak memory 210960 kb
Host smart-aa7c5ca8-f50c-4e83-8b9a-8c167bcd8917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326747264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3326747264
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2962346119
Short name T315
Test name
Test status
Simulation time 3831585551 ps
CPU time 38.17 seconds
Started Jun 10 05:10:50 PM PDT 24
Finished Jun 10 05:11:29 PM PDT 24
Peak memory 213304 kb
Host smart-b81065d3-7584-4b18-aed5-98ba01059bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962346119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2962346119
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3702776213
Short name T273
Test name
Test status
Simulation time 5625044657 ps
CPU time 53.81 seconds
Started Jun 10 05:10:47 PM PDT 24
Finished Jun 10 05:11:41 PM PDT 24
Peak memory 216912 kb
Host smart-47e0e1f8-bd9e-45a1-8b1f-847fd4b8a5f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702776213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3702776213
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3181851268
Short name T209
Test name
Test status
Simulation time 3437118339 ps
CPU time 14.19 seconds
Started Jun 10 05:10:33 PM PDT 24
Finished Jun 10 05:10:47 PM PDT 24
Peak memory 210796 kb
Host smart-c97278ae-03e3-4ba4-bc38-91b26d719de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181851268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3181851268
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4140341266
Short name T171
Test name
Test status
Simulation time 5895398447 ps
CPU time 93.06 seconds
Started Jun 10 05:10:49 PM PDT 24
Finished Jun 10 05:12:23 PM PDT 24
Peak memory 213212 kb
Host smart-4906a3f6-673e-4656-a2d1-92320d2cc061
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140341266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4140341266
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1844163226
Short name T175
Test name
Test status
Simulation time 2312671875 ps
CPU time 22.67 seconds
Started Jun 10 05:10:31 PM PDT 24
Finished Jun 10 05:10:54 PM PDT 24
Peak memory 211684 kb
Host smart-7d025744-9ac8-4e1e-810a-050b4ec552c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844163226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1844163226
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1051188501
Short name T227
Test name
Test status
Simulation time 2067940634 ps
CPU time 8.49 seconds
Started Jun 10 05:10:31 PM PDT 24
Finished Jun 10 05:10:42 PM PDT 24
Peak memory 210916 kb
Host smart-2e035e41-db37-491f-a43f-a1edb3a4aa18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051188501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1051188501
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1345149923
Short name T70
Test name
Test status
Simulation time 3096539333 ps
CPU time 32.63 seconds
Started Jun 10 05:10:29 PM PDT 24
Finished Jun 10 05:11:02 PM PDT 24
Peak memory 213476 kb
Host smart-9cf540c2-08cb-48df-85b9-2a0fa5c04898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345149923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1345149923
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2992172658
Short name T238
Test name
Test status
Simulation time 1126782880 ps
CPU time 15.37 seconds
Started Jun 10 05:10:42 PM PDT 24
Finished Jun 10 05:10:57 PM PDT 24
Peak memory 211728 kb
Host smart-6eb537a4-a345-49db-8fb4-2713bbf0e453
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992172658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2992172658
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.593819603
Short name T84
Test name
Test status
Simulation time 686835048 ps
CPU time 8.72 seconds
Started Jun 10 05:10:39 PM PDT 24
Finished Jun 10 05:10:48 PM PDT 24
Peak memory 210764 kb
Host smart-76412b99-39a5-4024-9521-36ddc81e9fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593819603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.593819603
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3168016210
Short name T188
Test name
Test status
Simulation time 373422032304 ps
CPU time 528.73 seconds
Started Jun 10 05:10:33 PM PDT 24
Finished Jun 10 05:19:22 PM PDT 24
Peak memory 233368 kb
Host smart-a1543c29-b382-4ee7-a832-756c7c60fe54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168016210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3168016210
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2228487564
Short name T304
Test name
Test status
Simulation time 19235073540 ps
CPU time 34.47 seconds
Started Jun 10 05:10:47 PM PDT 24
Finished Jun 10 05:11:22 PM PDT 24
Peak memory 211844 kb
Host smart-d3600268-4866-4699-91c3-937534268d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228487564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2228487564
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3492953816
Short name T180
Test name
Test status
Simulation time 2055104451 ps
CPU time 14.08 seconds
Started Jun 10 05:10:33 PM PDT 24
Finished Jun 10 05:10:48 PM PDT 24
Peak memory 210920 kb
Host smart-2c8f5b1e-b7c4-4146-943f-fa7048885130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3492953816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3492953816
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1382112012
Short name T101
Test name
Test status
Simulation time 369893232 ps
CPU time 10.1 seconds
Started Jun 10 05:10:30 PM PDT 24
Finished Jun 10 05:10:41 PM PDT 24
Peak memory 212864 kb
Host smart-d671f4e2-947c-4623-8029-9ca8e5e6d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382112012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1382112012
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.823083215
Short name T66
Test name
Test status
Simulation time 98897868652 ps
CPU time 60.54 seconds
Started Jun 10 05:10:39 PM PDT 24
Finished Jun 10 05:11:40 PM PDT 24
Peak memory 216768 kb
Host smart-7be569b3-23a5-4101-8260-d396c872b1f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823083215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.823083215
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3240578013
Short name T152
Test name
Test status
Simulation time 94570706 ps
CPU time 4.23 seconds
Started Jun 10 05:10:37 PM PDT 24
Finished Jun 10 05:10:41 PM PDT 24
Peak memory 210728 kb
Host smart-f5bcfd8a-abb1-4ed9-87fa-a9d39d9694f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240578013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3240578013
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1778742535
Short name T287
Test name
Test status
Simulation time 347883920 ps
CPU time 9.39 seconds
Started Jun 10 05:10:52 PM PDT 24
Finished Jun 10 05:11:07 PM PDT 24
Peak memory 211496 kb
Host smart-914835be-0e56-4e07-a7f2-d2a4a89165ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778742535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1778742535
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.494193520
Short name T366
Test name
Test status
Simulation time 5284093821 ps
CPU time 13.16 seconds
Started Jun 10 05:10:33 PM PDT 24
Finished Jun 10 05:10:46 PM PDT 24
Peak memory 211044 kb
Host smart-248e0a5e-599b-434d-86bf-968b5e9c22a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494193520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.494193520
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2682512487
Short name T9
Test name
Test status
Simulation time 2550428403 ps
CPU time 10.58 seconds
Started Jun 10 05:10:39 PM PDT 24
Finished Jun 10 05:10:50 PM PDT 24
Peak memory 213132 kb
Host smart-65b17243-ee2c-4983-9200-e8290d7d33f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682512487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2682512487
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2485131543
Short name T312
Test name
Test status
Simulation time 8942410849 ps
CPU time 25.75 seconds
Started Jun 10 05:10:57 PM PDT 24
Finished Jun 10 05:11:23 PM PDT 24
Peak memory 219012 kb
Host smart-19d5d84b-e226-490d-93b9-726121706e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485131543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2485131543
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1974533532
Short name T54
Test name
Test status
Simulation time 1183901531 ps
CPU time 11.16 seconds
Started Jun 10 05:10:37 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 210748 kb
Host smart-3021db1a-d992-451b-9c66-3425e188f622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974533532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1974533532
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3714396896
Short name T291
Test name
Test status
Simulation time 31615591770 ps
CPU time 164.25 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:13:38 PM PDT 24
Peak memory 233916 kb
Host smart-445bb788-ad22-4fed-9e23-f9565c1e0511
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714396896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3714396896
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1835728934
Short name T2
Test name
Test status
Simulation time 2828027711 ps
CPU time 26.53 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:11:21 PM PDT 24
Peak memory 211524 kb
Host smart-db9d15c5-f25f-4ef5-b2cd-5adb1938e22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835728934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1835728934
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3977077856
Short name T254
Test name
Test status
Simulation time 179234152 ps
CPU time 6.88 seconds
Started Jun 10 05:10:38 PM PDT 24
Finished Jun 10 05:10:45 PM PDT 24
Peak memory 210924 kb
Host smart-310ff196-1b63-477b-8c60-edacfc919b54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977077856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3977077856
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.415791330
Short name T350
Test name
Test status
Simulation time 1014987898 ps
CPU time 17.52 seconds
Started Jun 10 05:10:44 PM PDT 24
Finished Jun 10 05:11:02 PM PDT 24
Peak memory 212816 kb
Host smart-19b6ca9b-ebb0-4b77-bf34-83a0902f7120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415791330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.415791330
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2749508337
Short name T182
Test name
Test status
Simulation time 6884240839 ps
CPU time 29.9 seconds
Started Jun 10 05:10:35 PM PDT 24
Finished Jun 10 05:11:05 PM PDT 24
Peak memory 214688 kb
Host smart-6fe3f6b1-1b6b-4cca-a133-154b6b55d4a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749508337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2749508337
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2879719317
Short name T321
Test name
Test status
Simulation time 1397438484 ps
CPU time 12.42 seconds
Started Jun 10 05:10:42 PM PDT 24
Finished Jun 10 05:10:55 PM PDT 24
Peak memory 210800 kb
Host smart-d8e47b42-c4c0-4c4b-979a-79c53f13cef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879719317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2879719317
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2302966936
Short name T179
Test name
Test status
Simulation time 1646697978 ps
CPU time 98.41 seconds
Started Jun 10 05:10:40 PM PDT 24
Finished Jun 10 05:12:19 PM PDT 24
Peak memory 212248 kb
Host smart-aa153f09-0946-4b1a-9858-8e10621c348f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302966936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2302966936
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3489930501
Short name T302
Test name
Test status
Simulation time 2386677176 ps
CPU time 24.85 seconds
Started Jun 10 05:10:49 PM PDT 24
Finished Jun 10 05:11:15 PM PDT 24
Peak memory 211632 kb
Host smart-a2e53e3d-d30d-4416-9587-216b7ade0b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489930501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3489930501
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2165857902
Short name T218
Test name
Test status
Simulation time 809149961 ps
CPU time 7.11 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:11:01 PM PDT 24
Peak memory 210968 kb
Host smart-a1b820f0-daad-4716-8433-33bfbe447ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165857902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2165857902
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2740797408
Short name T151
Test name
Test status
Simulation time 181747309 ps
CPU time 10.24 seconds
Started Jun 10 05:10:37 PM PDT 24
Finished Jun 10 05:10:52 PM PDT 24
Peak memory 213500 kb
Host smart-af4ca128-e1c3-490f-926d-25ce613106cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740797408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2740797408
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4255241498
Short name T18
Test name
Test status
Simulation time 1384264188 ps
CPU time 20.96 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:11:15 PM PDT 24
Peak memory 212868 kb
Host smart-ed526721-3911-4374-bddb-b158198b20d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255241498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4255241498
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1023680728
Short name T38
Test name
Test status
Simulation time 26328933090 ps
CPU time 1653.03 seconds
Started Jun 10 05:10:55 PM PDT 24
Finished Jun 10 05:38:29 PM PDT 24
Peak memory 227308 kb
Host smart-552a91e4-4d14-49f4-a76d-26d65e132f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023680728 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1023680728
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4263924892
Short name T297
Test name
Test status
Simulation time 415692740 ps
CPU time 4.33 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:10:22 PM PDT 24
Peak memory 210732 kb
Host smart-c8b6c926-6ba7-4c20-ab13-758acd57d9f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263924892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4263924892
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1705525525
Short name T205
Test name
Test status
Simulation time 20654717626 ps
CPU time 252.46 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 05:14:28 PM PDT 24
Peak memory 236380 kb
Host smart-0defc304-681c-4264-8b91-e64f7201a47d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705525525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1705525525
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.803365926
Short name T85
Test name
Test status
Simulation time 175552040 ps
CPU time 9.53 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:10:28 PM PDT 24
Peak memory 211536 kb
Host smart-3292d9c2-993d-49e1-8529-a5db5bd73fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803365926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.803365926
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3754306066
Short name T4
Test name
Test status
Simulation time 176904226 ps
CPU time 6.76 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:10:25 PM PDT 24
Peak memory 210920 kb
Host smart-dca6ffd5-0ced-4607-b732-a413c51c8d9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754306066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3754306066
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3687732170
Short name T22
Test name
Test status
Simulation time 2835701578 ps
CPU time 65.28 seconds
Started Jun 10 05:10:36 PM PDT 24
Finished Jun 10 05:11:42 PM PDT 24
Peak memory 236136 kb
Host smart-221d6e6d-bd08-4cea-bca2-61e24a285185
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687732170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3687732170
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4072895925
Short name T200
Test name
Test status
Simulation time 2798714085 ps
CPU time 29.06 seconds
Started Jun 10 05:10:17 PM PDT 24
Finished Jun 10 05:10:46 PM PDT 24
Peak memory 212972 kb
Host smart-c8bfe871-4d32-4a04-bc1f-66396645b31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072895925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4072895925
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.702626042
Short name T215
Test name
Test status
Simulation time 1774673965 ps
CPU time 38.48 seconds
Started Jun 10 05:10:17 PM PDT 24
Finished Jun 10 05:10:56 PM PDT 24
Peak memory 216288 kb
Host smart-99720118-2963-4245-8921-8f86dc93a9c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702626042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.702626042
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.471099530
Short name T55
Test name
Test status
Simulation time 2456471049 ps
CPU time 8.58 seconds
Started Jun 10 05:10:50 PM PDT 24
Finished Jun 10 05:10:59 PM PDT 24
Peak memory 210804 kb
Host smart-aa941b2a-54a3-4469-a7e7-9fc24ba24c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471099530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.471099530
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.90041101
Short name T168
Test name
Test status
Simulation time 8280338727 ps
CPU time 94.13 seconds
Started Jun 10 05:10:46 PM PDT 24
Finished Jun 10 05:12:20 PM PDT 24
Peak memory 234100 kb
Host smart-e5ce61b9-ed81-4556-93e6-e0e3e265c1ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90041101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_co
rrupt_sig_fatal_chk.90041101
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1274458496
Short name T176
Test name
Test status
Simulation time 2274049555 ps
CPU time 23.89 seconds
Started Jun 10 05:10:52 PM PDT 24
Finished Jun 10 05:11:17 PM PDT 24
Peak memory 210896 kb
Host smart-af8da179-4b3f-4c5a-ae9d-454d55de33ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274458496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1274458496
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2287635825
Short name T286
Test name
Test status
Simulation time 187065858 ps
CPU time 5.41 seconds
Started Jun 10 05:10:41 PM PDT 24
Finished Jun 10 05:10:47 PM PDT 24
Peak memory 210968 kb
Host smart-927beed4-474a-4d3f-a03b-dba902789a69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287635825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2287635825
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1925855716
Short name T266
Test name
Test status
Simulation time 1854934800 ps
CPU time 18.36 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:11:12 PM PDT 24
Peak memory 210904 kb
Host smart-f2119c54-4412-4bdd-a541-f85adba54865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925855716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1925855716
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3983459700
Short name T280
Test name
Test status
Simulation time 13133852304 ps
CPU time 52.28 seconds
Started Jun 10 05:10:44 PM PDT 24
Finished Jun 10 05:11:37 PM PDT 24
Peak memory 216704 kb
Host smart-9ef21a48-f0f0-4b0a-90f4-4900833cdefd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983459700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3983459700
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2843574459
Short name T354
Test name
Test status
Simulation time 47024881458 ps
CPU time 1824.54 seconds
Started Jun 10 05:10:56 PM PDT 24
Finished Jun 10 05:41:21 PM PDT 24
Peak memory 232468 kb
Host smart-deaf3c6d-50cd-48e9-8cdc-08576cfd563b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843574459 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2843574459
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2266382600
Short name T235
Test name
Test status
Simulation time 1129567618 ps
CPU time 11 seconds
Started Jun 10 05:10:46 PM PDT 24
Finished Jun 10 05:10:57 PM PDT 24
Peak memory 210752 kb
Host smart-c713d06f-6010-4fe9-b6a1-0eb31feb08e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266382600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2266382600
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1093645565
Short name T284
Test name
Test status
Simulation time 138075617743 ps
CPU time 343.05 seconds
Started Jun 10 05:10:56 PM PDT 24
Finished Jun 10 05:16:40 PM PDT 24
Peak memory 212208 kb
Host smart-7f405678-696e-4b24-8328-7f13705e6122
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093645565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1093645565
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.174332314
Short name T269
Test name
Test status
Simulation time 12018674020 ps
CPU time 27.07 seconds
Started Jun 10 05:10:51 PM PDT 24
Finished Jun 10 05:11:19 PM PDT 24
Peak memory 211208 kb
Host smart-68d75a0e-7b72-45b4-b0b9-9d25c28877d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174332314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.174332314
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2308463138
Short name T202
Test name
Test status
Simulation time 17531830857 ps
CPU time 35.86 seconds
Started Jun 10 05:10:44 PM PDT 24
Finished Jun 10 05:11:21 PM PDT 24
Peak memory 214044 kb
Host smart-d25d8b24-fc9b-41d4-b82f-36f783327378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308463138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2308463138
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1630168371
Short name T355
Test name
Test status
Simulation time 1162398415 ps
CPU time 17.05 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:11:11 PM PDT 24
Peak memory 216036 kb
Host smart-624aaa22-61a6-4c1b-8781-eda96c22b40a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630168371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1630168371
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1270449118
Short name T252
Test name
Test status
Simulation time 93551006 ps
CPU time 4.36 seconds
Started Jun 10 05:10:52 PM PDT 24
Finished Jun 10 05:10:57 PM PDT 24
Peak memory 210720 kb
Host smart-37d92980-2728-495e-a558-5a8c4fd4816c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270449118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1270449118
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1683174423
Short name T86
Test name
Test status
Simulation time 25040905251 ps
CPU time 332.17 seconds
Started Jun 10 05:10:55 PM PDT 24
Finished Jun 10 05:16:28 PM PDT 24
Peak memory 234556 kb
Host smart-c4f46f4f-b575-466f-8791-a8e027b810dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683174423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1683174423
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1350767765
Short name T346
Test name
Test status
Simulation time 754145344 ps
CPU time 9.65 seconds
Started Jun 10 05:10:52 PM PDT 24
Finished Jun 10 05:11:02 PM PDT 24
Peak memory 211548 kb
Host smart-3d128d49-210a-45ad-93a0-a755bb976524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350767765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1350767765
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1209242790
Short name T148
Test name
Test status
Simulation time 376841694 ps
CPU time 5.54 seconds
Started Jun 10 05:10:52 PM PDT 24
Finished Jun 10 05:10:59 PM PDT 24
Peak memory 210888 kb
Host smart-6085146e-0324-494a-997c-a7b453dd3315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1209242790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1209242790
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3979941389
Short name T181
Test name
Test status
Simulation time 4001867318 ps
CPU time 17.56 seconds
Started Jun 10 05:11:00 PM PDT 24
Finished Jun 10 05:11:17 PM PDT 24
Peak memory 213112 kb
Host smart-b79fea55-45ab-46ad-8c57-562561f46e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979941389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3979941389
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1162659951
Short name T229
Test name
Test status
Simulation time 8327706087 ps
CPU time 24.21 seconds
Started Jun 10 05:10:55 PM PDT 24
Finished Jun 10 05:11:19 PM PDT 24
Peak memory 212428 kb
Host smart-30cfdc74-db69-4ef6-b8e5-d6e56d0b7781
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162659951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1162659951
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3087154483
Short name T364
Test name
Test status
Simulation time 4818576294 ps
CPU time 13.64 seconds
Started Jun 10 05:10:59 PM PDT 24
Finished Jun 10 05:11:13 PM PDT 24
Peak memory 210892 kb
Host smart-37481d46-2645-4246-9ed7-4176b13a9a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087154483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3087154483
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.191271072
Short name T367
Test name
Test status
Simulation time 28281081669 ps
CPU time 367.94 seconds
Started Jun 10 05:10:49 PM PDT 24
Finished Jun 10 05:16:58 PM PDT 24
Peak memory 236704 kb
Host smart-f3b953c2-8e14-40d4-a1ba-3fc3a29759bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191271072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.191271072
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.713369080
Short name T228
Test name
Test status
Simulation time 13353737440 ps
CPU time 19.25 seconds
Started Jun 10 05:11:08 PM PDT 24
Finished Jun 10 05:11:27 PM PDT 24
Peak memory 211836 kb
Host smart-79bf4514-aa1c-4a5f-9a01-451880d8ce75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713369080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.713369080
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.782060989
Short name T172
Test name
Test status
Simulation time 683267400 ps
CPU time 9.99 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:11:04 PM PDT 24
Peak memory 210912 kb
Host smart-acba5bd3-c60f-41c4-99df-c9e9ea1f96bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=782060989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.782060989
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4020976315
Short name T136
Test name
Test status
Simulation time 8812500396 ps
CPU time 39.76 seconds
Started Jun 10 05:10:54 PM PDT 24
Finished Jun 10 05:11:34 PM PDT 24
Peak memory 214040 kb
Host smart-a46f163b-1b63-45c0-9c5a-008cc1c2ac09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020976315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4020976315
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1451221738
Short name T46
Test name
Test status
Simulation time 2168544609 ps
CPU time 20.92 seconds
Started Jun 10 05:10:48 PM PDT 24
Finished Jun 10 05:11:09 PM PDT 24
Peak memory 210856 kb
Host smart-8a51d1ef-d180-447f-ba99-03d89d1c43ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451221738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1451221738
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4163953749
Short name T164
Test name
Test status
Simulation time 87250187 ps
CPU time 4.41 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:10:57 PM PDT 24
Peak memory 210748 kb
Host smart-1c8531bf-ecd1-40f9-be32-6ac2fb403e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163953749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4163953749
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2160331708
Short name T356
Test name
Test status
Simulation time 154030072856 ps
CPU time 250.18 seconds
Started Jun 10 05:10:52 PM PDT 24
Finished Jun 10 05:15:02 PM PDT 24
Peak memory 233436 kb
Host smart-7b2844c1-d917-4fc5-b4cd-dc0018b9084f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160331708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2160331708
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1020697871
Short name T165
Test name
Test status
Simulation time 4819727665 ps
CPU time 17.66 seconds
Started Jun 10 05:10:57 PM PDT 24
Finished Jun 10 05:11:15 PM PDT 24
Peak memory 211992 kb
Host smart-9e56e246-2db4-4ba4-915d-d3f3aa4e265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020697871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1020697871
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.213413253
Short name T156
Test name
Test status
Simulation time 8621295510 ps
CPU time 17.17 seconds
Started Jun 10 05:10:57 PM PDT 24
Finished Jun 10 05:11:15 PM PDT 24
Peak memory 211092 kb
Host smart-8f23a96a-2102-4512-80ca-d419634c32e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213413253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.213413253
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2765113134
Short name T154
Test name
Test status
Simulation time 15035775735 ps
CPU time 29.25 seconds
Started Jun 10 05:10:54 PM PDT 24
Finished Jun 10 05:11:23 PM PDT 24
Peak memory 213804 kb
Host smart-bf97a8bb-47d2-4fbb-8d52-39f5e43d2722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765113134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2765113134
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1490954251
Short name T296
Test name
Test status
Simulation time 722261203 ps
CPU time 11.7 seconds
Started Jun 10 05:10:48 PM PDT 24
Finished Jun 10 05:11:00 PM PDT 24
Peak memory 214700 kb
Host smart-951532c4-adda-467e-8b03-798b4e6b1668
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490954251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1490954251
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3601078414
Short name T328
Test name
Test status
Simulation time 167965163 ps
CPU time 4.51 seconds
Started Jun 10 05:10:59 PM PDT 24
Finished Jun 10 05:11:04 PM PDT 24
Peak memory 210808 kb
Host smart-dde861ec-2b71-48a4-baf0-16d40774bc0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601078414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3601078414
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2577823401
Short name T365
Test name
Test status
Simulation time 11907841837 ps
CPU time 119.46 seconds
Started Jun 10 05:11:01 PM PDT 24
Finished Jun 10 05:13:01 PM PDT 24
Peak memory 233384 kb
Host smart-bec6f8aa-81e3-4940-b94c-7e6642b401c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577823401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2577823401
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2913967986
Short name T318
Test name
Test status
Simulation time 3355224186 ps
CPU time 29.58 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:11:24 PM PDT 24
Peak memory 212364 kb
Host smart-2d9402a2-303d-4432-905c-af2eb8413236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913967986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2913967986
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3261061124
Short name T100
Test name
Test status
Simulation time 1370626559 ps
CPU time 9.93 seconds
Started Jun 10 05:10:52 PM PDT 24
Finished Jun 10 05:11:02 PM PDT 24
Peak memory 210928 kb
Host smart-ebc6dd76-e26e-4bf0-b2b3-fb05ab5c3e34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261061124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3261061124
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3167098595
Short name T222
Test name
Test status
Simulation time 7566148740 ps
CPU time 23.97 seconds
Started Jun 10 05:10:48 PM PDT 24
Finished Jun 10 05:11:12 PM PDT 24
Peak memory 214480 kb
Host smart-8d723af1-dbe6-4c97-90a2-85c1e13fa449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167098595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3167098595
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1995911393
Short name T274
Test name
Test status
Simulation time 1080924530 ps
CPU time 35.06 seconds
Started Jun 10 05:10:53 PM PDT 24
Finished Jun 10 05:11:29 PM PDT 24
Peak memory 215232 kb
Host smart-758fc882-e2a9-4cba-bd8c-12e2b20d8bfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995911393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1995911393
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4040765777
Short name T206
Test name
Test status
Simulation time 7817564784 ps
CPU time 15.08 seconds
Started Jun 10 05:11:00 PM PDT 24
Finished Jun 10 05:11:15 PM PDT 24
Peak memory 210792 kb
Host smart-a0dacc80-8cc8-489a-a0f4-9b518d8e7975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040765777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4040765777
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.691810042
Short name T256
Test name
Test status
Simulation time 236839577550 ps
CPU time 329.81 seconds
Started Jun 10 05:10:57 PM PDT 24
Finished Jun 10 05:16:28 PM PDT 24
Peak memory 237336 kb
Host smart-36f2cb43-ed60-492e-9c02-8f0ba14598de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691810042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.691810042
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1297387544
Short name T323
Test name
Test status
Simulation time 2623513777 ps
CPU time 25.49 seconds
Started Jun 10 05:11:00 PM PDT 24
Finished Jun 10 05:11:26 PM PDT 24
Peak memory 211636 kb
Host smart-8041eef9-2027-4d6d-a2c1-ceefd4045e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297387544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1297387544
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2694557721
Short name T245
Test name
Test status
Simulation time 343379588 ps
CPU time 8.21 seconds
Started Jun 10 05:10:57 PM PDT 24
Finished Jun 10 05:11:05 PM PDT 24
Peak memory 210920 kb
Host smart-24a23a52-4462-49ef-8666-a09d8a802b41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694557721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2694557721
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2779132915
Short name T329
Test name
Test status
Simulation time 7532257148 ps
CPU time 26.89 seconds
Started Jun 10 05:10:58 PM PDT 24
Finished Jun 10 05:11:25 PM PDT 24
Peak memory 213728 kb
Host smart-1a22e93d-9ebb-4cae-ba3c-322db19d7f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779132915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2779132915
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.816535379
Short name T68
Test name
Test status
Simulation time 2222329482 ps
CPU time 32.66 seconds
Started Jun 10 05:11:09 PM PDT 24
Finished Jun 10 05:11:42 PM PDT 24
Peak memory 215228 kb
Host smart-62200cc9-dc96-4729-8043-db3c18e250ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816535379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.816535379
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3775693745
Short name T52
Test name
Test status
Simulation time 1366743891 ps
CPU time 12.31 seconds
Started Jun 10 05:10:58 PM PDT 24
Finished Jun 10 05:11:10 PM PDT 24
Peak memory 210784 kb
Host smart-c8439b4f-8831-4c9d-aa8d-1ae3c72d1661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775693745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3775693745
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.362939901
Short name T167
Test name
Test status
Simulation time 31358811025 ps
CPU time 275.21 seconds
Started Jun 10 05:11:13 PM PDT 24
Finished Jun 10 05:15:49 PM PDT 24
Peak memory 213264 kb
Host smart-0ead44e8-c48f-493b-a743-e0ee4a668f50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362939901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.362939901
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1792601514
Short name T251
Test name
Test status
Simulation time 1707236346 ps
CPU time 15.9 seconds
Started Jun 10 05:11:07 PM PDT 24
Finished Jun 10 05:11:23 PM PDT 24
Peak memory 211684 kb
Host smart-5fc723ce-7371-4b57-8b80-a7d951271606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792601514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1792601514
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2765669711
Short name T223
Test name
Test status
Simulation time 7292187858 ps
CPU time 15.08 seconds
Started Jun 10 05:11:03 PM PDT 24
Finished Jun 10 05:11:19 PM PDT 24
Peak memory 211052 kb
Host smart-a3fa7cf2-aa85-4ce5-b534-9066e8b80ed1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765669711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2765669711
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.608462431
Short name T310
Test name
Test status
Simulation time 3660932076 ps
CPU time 17.09 seconds
Started Jun 10 05:10:59 PM PDT 24
Finished Jun 10 05:11:16 PM PDT 24
Peak memory 213036 kb
Host smart-2a98d15d-f5f4-424f-a5ac-318daf803ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608462431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.608462431
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3541611963
Short name T237
Test name
Test status
Simulation time 26928976850 ps
CPU time 75.02 seconds
Started Jun 10 05:10:54 PM PDT 24
Finished Jun 10 05:12:09 PM PDT 24
Peak memory 219428 kb
Host smart-e0517ce0-839e-405c-bf3e-bf6a3dc4e76d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541611963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3541611963
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.367453296
Short name T131
Test name
Test status
Simulation time 1986655388 ps
CPU time 11.75 seconds
Started Jun 10 05:11:05 PM PDT 24
Finished Jun 10 05:11:17 PM PDT 24
Peak memory 210784 kb
Host smart-f13ef49b-6566-4a68-97bd-5339fcc22419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367453296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.367453296
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2453675465
Short name T239
Test name
Test status
Simulation time 251841612325 ps
CPU time 172.07 seconds
Started Jun 10 05:11:02 PM PDT 24
Finished Jun 10 05:13:55 PM PDT 24
Peak memory 235992 kb
Host smart-e98ffe4e-ec65-43fb-bbec-472777387d6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453675465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2453675465
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.728243750
Short name T160
Test name
Test status
Simulation time 4321860554 ps
CPU time 35.03 seconds
Started Jun 10 05:10:54 PM PDT 24
Finished Jun 10 05:11:30 PM PDT 24
Peak memory 211952 kb
Host smart-d0cb51c0-6c3e-4ade-ab71-0addb417be48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728243750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.728243750
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.925922099
Short name T193
Test name
Test status
Simulation time 4259636513 ps
CPU time 12.07 seconds
Started Jun 10 05:10:55 PM PDT 24
Finished Jun 10 05:11:08 PM PDT 24
Peak memory 210984 kb
Host smart-6a909696-d587-4f29-80ab-6171530bfd78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=925922099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.925922099
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3626150120
Short name T212
Test name
Test status
Simulation time 3148648206 ps
CPU time 28.62 seconds
Started Jun 10 05:11:00 PM PDT 24
Finished Jun 10 05:11:29 PM PDT 24
Peak memory 212884 kb
Host smart-847d89dd-512f-4c06-a455-36ef6f1bd1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626150120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3626150120
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1857965608
Short name T145
Test name
Test status
Simulation time 768487089 ps
CPU time 11.44 seconds
Started Jun 10 05:11:02 PM PDT 24
Finished Jun 10 05:11:13 PM PDT 24
Peak memory 210672 kb
Host smart-c87d1750-b258-44b7-b655-ed8974622b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857965608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1857965608
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.905488264
Short name T333
Test name
Test status
Simulation time 1890677019 ps
CPU time 7.37 seconds
Started Jun 10 05:11:00 PM PDT 24
Finished Jun 10 05:11:08 PM PDT 24
Peak memory 210748 kb
Host smart-4435a8b7-6f32-4232-8ca0-fac8459bf97f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905488264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.905488264
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2537749040
Short name T253
Test name
Test status
Simulation time 7928945954 ps
CPU time 163.93 seconds
Started Jun 10 05:10:58 PM PDT 24
Finished Jun 10 05:13:43 PM PDT 24
Peak memory 224272 kb
Host smart-02d114b6-f875-4a8a-9fed-83a3855e718f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537749040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2537749040
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1692597460
Short name T257
Test name
Test status
Simulation time 3352738044 ps
CPU time 19.87 seconds
Started Jun 10 05:10:57 PM PDT 24
Finished Jun 10 05:11:18 PM PDT 24
Peak memory 211624 kb
Host smart-baad6249-6ccb-49c8-8af1-5300492ca09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692597460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1692597460
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2180575084
Short name T295
Test name
Test status
Simulation time 601484720 ps
CPU time 7.57 seconds
Started Jun 10 05:11:01 PM PDT 24
Finished Jun 10 05:11:09 PM PDT 24
Peak memory 210892 kb
Host smart-e04ded74-e32c-4830-81ff-e2617da2a8b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180575084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2180575084
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1742651705
Short name T7
Test name
Test status
Simulation time 187492878 ps
CPU time 10.43 seconds
Started Jun 10 05:10:56 PM PDT 24
Finished Jun 10 05:11:07 PM PDT 24
Peak memory 212712 kb
Host smart-b1ea0f2b-36f4-49b3-a299-95d49ad43ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742651705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1742651705
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.523089583
Short name T242
Test name
Test status
Simulation time 2193009904 ps
CPU time 19.19 seconds
Started Jun 10 05:11:02 PM PDT 24
Finished Jun 10 05:11:22 PM PDT 24
Peak memory 210936 kb
Host smart-b3a90b62-5d22-4250-bc40-9ccc25d2f699
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523089583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.523089583
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.672173292
Short name T42
Test name
Test status
Simulation time 326320270203 ps
CPU time 3173.71 seconds
Started Jun 10 05:10:59 PM PDT 24
Finished Jun 10 06:03:53 PM PDT 24
Peak memory 250256 kb
Host smart-637cb95a-a1dd-40bf-8a93-6fcfe5b2ff07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672173292 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.672173292
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.222943285
Short name T234
Test name
Test status
Simulation time 4115192498 ps
CPU time 10.45 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:22 PM PDT 24
Peak memory 210788 kb
Host smart-7517a6e3-af75-4d6b-b926-3a43930d08e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222943285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.222943285
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2334002918
Short name T232
Test name
Test status
Simulation time 11623526377 ps
CPU time 148.66 seconds
Started Jun 10 05:10:16 PM PDT 24
Finished Jun 10 05:12:46 PM PDT 24
Peak memory 237508 kb
Host smart-0e4584f2-0e20-45f0-b6a1-faaba5950232
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334002918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2334002918
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1496919699
Short name T37
Test name
Test status
Simulation time 176146328 ps
CPU time 9.62 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:10:28 PM PDT 24
Peak memory 212100 kb
Host smart-2eff82f5-fc97-4b29-90d4-a7e8de1c9a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496919699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1496919699
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4244209162
Short name T126
Test name
Test status
Simulation time 187688852 ps
CPU time 5.89 seconds
Started Jun 10 05:10:25 PM PDT 24
Finished Jun 10 05:10:31 PM PDT 24
Peak memory 210908 kb
Host smart-569b9fec-873b-4501-9daa-504a12d9ae47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244209162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4244209162
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.642369458
Short name T196
Test name
Test status
Simulation time 176981423 ps
CPU time 10.04 seconds
Started Jun 10 05:10:11 PM PDT 24
Finished Jun 10 05:10:22 PM PDT 24
Peak memory 213048 kb
Host smart-e7824591-6d36-410b-8869-1e4db0bbf2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642369458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.642369458
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3839302471
Short name T203
Test name
Test status
Simulation time 2063097208 ps
CPU time 48.1 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 05:11:03 PM PDT 24
Peak memory 216340 kb
Host smart-dee4a56a-be53-43c7-81b9-d37c6c0d4fe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839302471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3839302471
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3147998498
Short name T320
Test name
Test status
Simulation time 1853282875 ps
CPU time 15.43 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:10:36 PM PDT 24
Peak memory 210772 kb
Host smart-d3fab547-2450-485b-a94f-cf031952428f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147998498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3147998498
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1870694663
Short name T127
Test name
Test status
Simulation time 55127712940 ps
CPU time 190.69 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:13:29 PM PDT 24
Peak memory 237476 kb
Host smart-7831ff1d-1d99-4494-be19-d684627d4ec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870694663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1870694663
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4168372739
Short name T290
Test name
Test status
Simulation time 18347838099 ps
CPU time 33.78 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:10:53 PM PDT 24
Peak memory 211888 kb
Host smart-e44f480b-03a3-4d1e-a501-f8a8f582035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168372739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4168372739
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2507298957
Short name T246
Test name
Test status
Simulation time 111226832 ps
CPU time 5.34 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:10:25 PM PDT 24
Peak memory 210944 kb
Host smart-a1511fda-82fb-4781-a90d-e89626255446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507298957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2507298957
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1000356668
Short name T259
Test name
Test status
Simulation time 5541836669 ps
CPU time 30.8 seconds
Started Jun 10 05:10:17 PM PDT 24
Finished Jun 10 05:10:49 PM PDT 24
Peak memory 213300 kb
Host smart-bf32ac46-233e-47b9-9d53-8725fe60b7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000356668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1000356668
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2870483334
Short name T129
Test name
Test status
Simulation time 7833447606 ps
CPU time 24.93 seconds
Started Jun 10 05:10:14 PM PDT 24
Finished Jun 10 05:10:39 PM PDT 24
Peak memory 212232 kb
Host smart-13bf184e-c06b-48b1-b17f-b58d9c1397a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870483334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2870483334
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.400158267
Short name T272
Test name
Test status
Simulation time 601846320 ps
CPU time 8.24 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 05:10:24 PM PDT 24
Peak memory 210992 kb
Host smart-54309e46-b8cd-46b4-8892-a27e9a05da56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400158267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.400158267
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2294676831
Short name T241
Test name
Test status
Simulation time 31573259706 ps
CPU time 128.08 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:12:28 PM PDT 24
Peak memory 227968 kb
Host smart-a6168e99-44ac-4965-92bb-a4c59af9e47a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294676831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2294676831
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3162230855
Short name T265
Test name
Test status
Simulation time 9623466232 ps
CPU time 25.33 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:10:45 PM PDT 24
Peak memory 211952 kb
Host smart-7dadbfe6-07f4-49d7-9155-0012850ada7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162230855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3162230855
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.781832833
Short name T174
Test name
Test status
Simulation time 1053742761 ps
CPU time 11.65 seconds
Started Jun 10 05:10:34 PM PDT 24
Finished Jun 10 05:10:46 PM PDT 24
Peak memory 210944 kb
Host smart-800b77fd-8be6-45fb-96cc-6a4cdbf05b97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781832833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.781832833
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3577335219
Short name T142
Test name
Test status
Simulation time 2358267243 ps
CPU time 22.6 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:10:41 PM PDT 24
Peak memory 213660 kb
Host smart-8f23ae02-369b-47dd-ad51-f9e9fe5c3601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577335219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3577335219
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3063550264
Short name T39
Test name
Test status
Simulation time 204741256285 ps
CPU time 4812.69 seconds
Started Jun 10 05:10:21 PM PDT 24
Finished Jun 10 06:30:35 PM PDT 24
Peak memory 235852 kb
Host smart-41e78ff4-ca6b-4bba-80be-bf253a0d72f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063550264 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3063550264
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3088155007
Short name T194
Test name
Test status
Simulation time 1932164988 ps
CPU time 16.29 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:38 PM PDT 24
Peak memory 210796 kb
Host smart-503833dd-267b-41d2-b882-ab84240a3a1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088155007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3088155007
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1656279382
Short name T219
Test name
Test status
Simulation time 5436147792 ps
CPU time 191.65 seconds
Started Jun 10 05:10:18 PM PDT 24
Finished Jun 10 05:13:30 PM PDT 24
Peak memory 236416 kb
Host smart-d03530b8-0d6b-4a86-b225-b16b43418f62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656279382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1656279382
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4229365562
Short name T187
Test name
Test status
Simulation time 8530012151 ps
CPU time 25.47 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:10:45 PM PDT 24
Peak memory 212108 kb
Host smart-3dadc0ac-2da2-46bc-adb0-8e603a89be15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229365562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4229365562
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4072197819
Short name T268
Test name
Test status
Simulation time 2427326730 ps
CPU time 13 seconds
Started Jun 10 05:10:34 PM PDT 24
Finished Jun 10 05:10:47 PM PDT 24
Peak memory 210972 kb
Host smart-d9afb60e-a645-42e5-bd3b-2a5c023cc981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072197819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4072197819
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.71912582
Short name T67
Test name
Test status
Simulation time 4791478024 ps
CPU time 24.05 seconds
Started Jun 10 05:10:23 PM PDT 24
Finished Jun 10 05:10:47 PM PDT 24
Peak memory 213820 kb
Host smart-535a8c53-4156-43cc-bbc7-ff27125dcdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71912582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.71912582
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2551999818
Short name T99
Test name
Test status
Simulation time 5186915919 ps
CPU time 46.3 seconds
Started Jun 10 05:10:45 PM PDT 24
Finished Jun 10 05:11:32 PM PDT 24
Peak memory 216376 kb
Host smart-65f89766-8655-4199-905b-521ce78f1c35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551999818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2551999818
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1815872158
Short name T43
Test name
Test status
Simulation time 154950960555 ps
CPU time 4658.06 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 06:27:54 PM PDT 24
Peak memory 235556 kb
Host smart-77112f2c-7d15-429c-8a45-6beb6ace73fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815872158 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1815872158
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3768568700
Short name T261
Test name
Test status
Simulation time 950780379 ps
CPU time 7.59 seconds
Started Jun 10 05:10:19 PM PDT 24
Finished Jun 10 05:10:27 PM PDT 24
Peak memory 210748 kb
Host smart-faed411f-d7f5-4108-a6eb-f0873bdd0e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768568700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3768568700
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1876691109
Short name T299
Test name
Test status
Simulation time 108716897656 ps
CPU time 267.9 seconds
Started Jun 10 05:10:20 PM PDT 24
Finished Jun 10 05:14:49 PM PDT 24
Peak memory 237404 kb
Host smart-bd46e81f-677a-4323-8c1c-f0c0975c7681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876691109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1876691109
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1628200512
Short name T87
Test name
Test status
Simulation time 3472291472 ps
CPU time 26.08 seconds
Started Jun 10 05:10:15 PM PDT 24
Finished Jun 10 05:10:41 PM PDT 24
Peak memory 211532 kb
Host smart-437d55c7-5d95-4573-a1a6-d88474ed1046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628200512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1628200512
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.972232887
Short name T225
Test name
Test status
Simulation time 2141862401 ps
CPU time 17.66 seconds
Started Jun 10 05:10:24 PM PDT 24
Finished Jun 10 05:10:42 PM PDT 24
Peak memory 210980 kb
Host smart-97828910-2828-48c0-8d90-8eeee2447390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972232887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.972232887
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2178522249
Short name T248
Test name
Test status
Simulation time 182168539 ps
CPU time 10.42 seconds
Started Jun 10 05:10:24 PM PDT 24
Finished Jun 10 05:10:35 PM PDT 24
Peak memory 213480 kb
Host smart-04f5a42d-43ef-4da6-acb1-0f8b6289a741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178522249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2178522249
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2860118300
Short name T343
Test name
Test status
Simulation time 23045624844 ps
CPU time 33.63 seconds
Started Jun 10 05:10:22 PM PDT 24
Finished Jun 10 05:10:56 PM PDT 24
Peak memory 218924 kb
Host smart-f1a1cc9e-7bd6-42af-a295-ebf010cb9340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860118300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2860118300
Directory /workspace/9.rom_ctrl_stress_all/latest
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