Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.42 96.89 92.56 97.72 100.00 98.97 97.45 98.37


Total test records in report: 462
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T299 /workspace/coverage/default/38.rom_ctrl_alert_test.1387394942 Jun 11 12:36:36 PM PDT 24 Jun 11 12:36:48 PM PDT 24 18764663935 ps
T300 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1591689920 Jun 11 12:36:48 PM PDT 24 Jun 11 12:37:04 PM PDT 24 1407555727 ps
T301 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2733450229 Jun 11 12:36:42 PM PDT 24 Jun 11 12:38:43 PM PDT 24 14380329737 ps
T302 /workspace/coverage/default/3.rom_ctrl_alert_test.4085400649 Jun 11 12:36:06 PM PDT 24 Jun 11 12:36:19 PM PDT 24 10047614104 ps
T303 /workspace/coverage/default/32.rom_ctrl_stress_all.486775601 Jun 11 12:36:37 PM PDT 24 Jun 11 12:37:08 PM PDT 24 498281586 ps
T304 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1035966139 Jun 11 12:36:31 PM PDT 24 Jun 11 12:43:07 PM PDT 24 39780368370 ps
T305 /workspace/coverage/default/19.rom_ctrl_stress_all.3412931957 Jun 11 12:36:28 PM PDT 24 Jun 11 12:37:37 PM PDT 24 33735048004 ps
T306 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2385445462 Jun 11 12:36:27 PM PDT 24 Jun 11 12:36:33 PM PDT 24 196360079 ps
T307 /workspace/coverage/default/40.rom_ctrl_stress_all.3414466426 Jun 11 12:36:48 PM PDT 24 Jun 11 12:37:22 PM PDT 24 39432270829 ps
T308 /workspace/coverage/default/34.rom_ctrl_alert_test.1887052137 Jun 11 12:36:38 PM PDT 24 Jun 11 12:36:53 PM PDT 24 1724698715 ps
T309 /workspace/coverage/default/11.rom_ctrl_stress_all.77694355 Jun 11 12:36:20 PM PDT 24 Jun 11 12:36:28 PM PDT 24 207552957 ps
T310 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2189838269 Jun 11 12:36:38 PM PDT 24 Jun 11 12:36:47 PM PDT 24 1812274809 ps
T311 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1177451814 Jun 11 12:36:07 PM PDT 24 Jun 11 12:36:27 PM PDT 24 3067741227 ps
T312 /workspace/coverage/default/31.rom_ctrl_stress_all.3658897997 Jun 11 12:36:28 PM PDT 24 Jun 11 12:36:49 PM PDT 24 3464116987 ps
T313 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2379708798 Jun 11 12:36:39 PM PDT 24 Jun 11 12:37:09 PM PDT 24 3230131029 ps
T314 /workspace/coverage/default/11.rom_ctrl_alert_test.1188907491 Jun 11 12:36:21 PM PDT 24 Jun 11 12:36:39 PM PDT 24 1912551025 ps
T315 /workspace/coverage/default/40.rom_ctrl_smoke.1833425561 Jun 11 12:36:48 PM PDT 24 Jun 11 12:37:08 PM PDT 24 3147119837 ps
T316 /workspace/coverage/default/16.rom_ctrl_alert_test.2503372710 Jun 11 12:36:20 PM PDT 24 Jun 11 12:36:26 PM PDT 24 88335912 ps
T317 /workspace/coverage/default/44.rom_ctrl_stress_all.2868300779 Jun 11 12:36:47 PM PDT 24 Jun 11 12:37:06 PM PDT 24 2152343160 ps
T318 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3614766733 Jun 11 12:36:39 PM PDT 24 Jun 11 12:38:54 PM PDT 24 45367141490 ps
T319 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2892719587 Jun 11 12:36:19 PM PDT 24 Jun 11 12:42:46 PM PDT 24 81646641820 ps
T320 /workspace/coverage/default/33.rom_ctrl_stress_all.3526639866 Jun 11 12:36:50 PM PDT 24 Jun 11 12:37:09 PM PDT 24 1188092989 ps
T321 /workspace/coverage/default/45.rom_ctrl_stress_all.1328879144 Jun 11 12:36:50 PM PDT 24 Jun 11 12:37:12 PM PDT 24 8185859272 ps
T322 /workspace/coverage/default/19.rom_ctrl_smoke.2531987255 Jun 11 12:36:29 PM PDT 24 Jun 11 12:37:00 PM PDT 24 11530274714 ps
T323 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.408375710 Jun 11 12:36:59 PM PDT 24 Jun 11 12:37:09 PM PDT 24 594799216 ps
T324 /workspace/coverage/default/2.rom_ctrl_stress_all.1873658407 Jun 11 12:36:03 PM PDT 24 Jun 11 12:37:14 PM PDT 24 87578734092 ps
T325 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2812505553 Jun 11 12:36:54 PM PDT 24 Jun 11 12:40:05 PM PDT 24 24588868491 ps
T326 /workspace/coverage/default/48.rom_ctrl_smoke.2976648148 Jun 11 12:37:01 PM PDT 24 Jun 11 12:37:27 PM PDT 24 3959184660 ps
T327 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1459971143 Jun 11 12:36:21 PM PDT 24 Jun 11 12:36:29 PM PDT 24 404107651 ps
T328 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3678476396 Jun 11 12:36:32 PM PDT 24 Jun 11 12:37:01 PM PDT 24 23822961420 ps
T329 /workspace/coverage/default/42.rom_ctrl_alert_test.1744784864 Jun 11 12:36:54 PM PDT 24 Jun 11 12:37:09 PM PDT 24 10419270535 ps
T330 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3827555734 Jun 11 12:36:19 PM PDT 24 Jun 11 12:36:29 PM PDT 24 880113369 ps
T331 /workspace/coverage/default/26.rom_ctrl_alert_test.2870002272 Jun 11 12:36:40 PM PDT 24 Jun 11 12:36:45 PM PDT 24 88820820 ps
T332 /workspace/coverage/default/30.rom_ctrl_stress_all.2136193557 Jun 11 12:36:30 PM PDT 24 Jun 11 12:36:38 PM PDT 24 885981360 ps
T333 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3490719847 Jun 11 12:36:53 PM PDT 24 Jun 11 12:37:00 PM PDT 24 374243792 ps
T334 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1979563486 Jun 11 12:36:47 PM PDT 24 Jun 11 12:40:50 PM PDT 24 94579796007 ps
T335 /workspace/coverage/default/13.rom_ctrl_stress_all.2623745752 Jun 11 12:36:20 PM PDT 24 Jun 11 12:36:33 PM PDT 24 4046710702 ps
T336 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4158520027 Jun 11 12:36:35 PM PDT 24 Jun 11 12:39:40 PM PDT 24 48378724284 ps
T337 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4164978217 Jun 11 12:36:39 PM PDT 24 Jun 11 12:36:51 PM PDT 24 8574895182 ps
T338 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.946297229 Jun 11 12:36:37 PM PDT 24 Jun 11 12:36:47 PM PDT 24 2272088233 ps
T339 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.231184451 Jun 11 12:36:35 PM PDT 24 Jun 11 12:38:31 PM PDT 24 7565123094 ps
T340 /workspace/coverage/default/27.rom_ctrl_smoke.2212455813 Jun 11 12:36:29 PM PDT 24 Jun 11 12:36:42 PM PDT 24 535988061 ps
T341 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.118810755 Jun 11 12:36:20 PM PDT 24 Jun 11 12:36:38 PM PDT 24 2029089244 ps
T342 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2690439793 Jun 11 12:36:39 PM PDT 24 Jun 11 12:38:16 PM PDT 24 13015671995 ps
T343 /workspace/coverage/default/35.rom_ctrl_smoke.3664044698 Jun 11 12:36:35 PM PDT 24 Jun 11 12:36:59 PM PDT 24 3359760696 ps
T344 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2484028315 Jun 11 12:36:05 PM PDT 24 Jun 11 12:36:20 PM PDT 24 1547757472 ps
T345 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.986159178 Jun 11 12:36:32 PM PDT 24 Jun 11 12:36:56 PM PDT 24 2189314052 ps
T346 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3197922637 Jun 11 12:36:32 PM PDT 24 Jun 11 12:36:44 PM PDT 24 718456415 ps
T347 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.409128195 Jun 11 12:36:35 PM PDT 24 Jun 11 12:47:04 PM PDT 24 60858800754 ps
T348 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3509014027 Jun 11 12:36:32 PM PDT 24 Jun 11 12:36:39 PM PDT 24 600502118 ps
T349 /workspace/coverage/default/29.rom_ctrl_alert_test.2105186495 Jun 11 12:36:39 PM PDT 24 Jun 11 12:36:45 PM PDT 24 828125290 ps
T350 /workspace/coverage/default/32.rom_ctrl_smoke.754793178 Jun 11 12:36:37 PM PDT 24 Jun 11 12:37:09 PM PDT 24 3012389367 ps
T351 /workspace/coverage/default/3.rom_ctrl_stress_all.1591944571 Jun 11 12:36:09 PM PDT 24 Jun 11 12:36:26 PM PDT 24 5680033140 ps
T352 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2460543197 Jun 11 12:36:38 PM PDT 24 Jun 11 12:36:49 PM PDT 24 667228730 ps
T353 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.600597970 Jun 11 12:36:28 PM PDT 24 Jun 11 12:36:38 PM PDT 24 397523209 ps
T354 /workspace/coverage/default/26.rom_ctrl_stress_all.2142019039 Jun 11 12:36:28 PM PDT 24 Jun 11 12:37:06 PM PDT 24 4194080440 ps
T355 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3023339189 Jun 11 12:36:21 PM PDT 24 Jun 11 12:40:20 PM PDT 24 50493055710 ps
T356 /workspace/coverage/default/22.rom_ctrl_stress_all.3510360665 Jun 11 12:36:32 PM PDT 24 Jun 11 12:37:21 PM PDT 24 4441677237 ps
T357 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4274471748 Jun 11 12:36:30 PM PDT 24 Jun 11 12:36:37 PM PDT 24 192203389 ps
T358 /workspace/coverage/default/3.rom_ctrl_smoke.3825939414 Jun 11 12:36:02 PM PDT 24 Jun 11 12:36:13 PM PDT 24 177935103 ps
T359 /workspace/coverage/default/22.rom_ctrl_alert_test.1675339317 Jun 11 12:36:31 PM PDT 24 Jun 11 12:36:43 PM PDT 24 1108012610 ps
T360 /workspace/coverage/default/12.rom_ctrl_smoke.1296185970 Jun 11 12:36:18 PM PDT 24 Jun 11 12:36:50 PM PDT 24 12002447878 ps
T361 /workspace/coverage/default/13.rom_ctrl_smoke.331019844 Jun 11 12:36:17 PM PDT 24 Jun 11 12:36:29 PM PDT 24 1186303647 ps
T362 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1407876780 Jun 11 12:36:06 PM PDT 24 Jun 11 12:36:33 PM PDT 24 2706169497 ps
T363 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3650177566 Jun 11 12:36:39 PM PDT 24 Jun 11 12:37:14 PM PDT 24 39271974903 ps
T364 /workspace/coverage/default/38.rom_ctrl_stress_all.1687187324 Jun 11 12:36:48 PM PDT 24 Jun 11 12:37:08 PM PDT 24 5733510022 ps
T365 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1218062578 Jun 11 12:36:31 PM PDT 24 Jun 11 12:38:02 PM PDT 24 1742974024 ps
T366 /workspace/coverage/default/16.rom_ctrl_smoke.369319379 Jun 11 12:36:21 PM PDT 24 Jun 11 12:36:33 PM PDT 24 783142812 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3425416686 Jun 11 12:35:39 PM PDT 24 Jun 11 12:35:53 PM PDT 24 6114599124 ps
T55 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1200126442 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:07 PM PDT 24 3777027740 ps
T56 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2962233379 Jun 11 12:35:51 PM PDT 24 Jun 11 12:36:02 PM PDT 24 977431981 ps
T57 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3395851448 Jun 11 12:35:40 PM PDT 24 Jun 11 12:35:52 PM PDT 24 1042720726 ps
T368 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.306828149 Jun 11 12:35:40 PM PDT 24 Jun 11 12:35:54 PM PDT 24 3123438630 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1330459511 Jun 11 12:35:44 PM PDT 24 Jun 11 12:36:01 PM PDT 24 1937701428 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.558681256 Jun 11 12:35:39 PM PDT 24 Jun 11 12:35:52 PM PDT 24 3858217092 ps
T62 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3522580370 Jun 11 12:35:35 PM PDT 24 Jun 11 12:35:45 PM PDT 24 613795400 ps
T371 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.534011201 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:11 PM PDT 24 1327359495 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3983658876 Jun 11 12:35:45 PM PDT 24 Jun 11 12:36:03 PM PDT 24 11383020725 ps
T63 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4293315268 Jun 11 12:36:03 PM PDT 24 Jun 11 12:36:08 PM PDT 24 334221503 ps
T64 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1610334462 Jun 11 12:35:50 PM PDT 24 Jun 11 12:37:07 PM PDT 24 8056186508 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3995504255 Jun 11 12:35:38 PM PDT 24 Jun 11 12:36:01 PM PDT 24 2210313973 ps
T65 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3986848905 Jun 11 12:35:45 PM PDT 24 Jun 11 12:36:35 PM PDT 24 15110957598 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4267801252 Jun 11 12:35:40 PM PDT 24 Jun 11 12:35:49 PM PDT 24 521712623 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2601503843 Jun 11 12:35:41 PM PDT 24 Jun 11 12:35:55 PM PDT 24 6150965365 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.716017958 Jun 11 12:35:54 PM PDT 24 Jun 11 12:36:09 PM PDT 24 2977070579 ps
T375 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.424147496 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:04 PM PDT 24 1328788418 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2425388297 Jun 11 12:35:42 PM PDT 24 Jun 11 12:35:52 PM PDT 24 668421935 ps
T99 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2749816363 Jun 11 12:35:54 PM PDT 24 Jun 11 12:36:09 PM PDT 24 2713724198 ps
T100 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1494039450 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:03 PM PDT 24 1209703878 ps
T67 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2665923760 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:09 PM PDT 24 4602944243 ps
T377 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3001707276 Jun 11 12:35:50 PM PDT 24 Jun 11 12:36:10 PM PDT 24 381183113 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3932163555 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:11 PM PDT 24 1380237451 ps
T379 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2928082993 Jun 11 12:35:42 PM PDT 24 Jun 11 12:36:02 PM PDT 24 5727373642 ps
T380 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1040525233 Jun 11 12:35:41 PM PDT 24 Jun 11 12:35:59 PM PDT 24 2224863095 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4078360281 Jun 11 12:35:58 PM PDT 24 Jun 11 12:36:11 PM PDT 24 10198260151 ps
T68 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3677020853 Jun 11 12:36:00 PM PDT 24 Jun 11 12:36:46 PM PDT 24 4845116400 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1191368520 Jun 11 12:35:39 PM PDT 24 Jun 11 12:35:56 PM PDT 24 6519928195 ps
T69 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2647626518 Jun 11 12:36:03 PM PDT 24 Jun 11 12:37:34 PM PDT 24 46116893498 ps
T70 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.252218888 Jun 11 12:35:42 PM PDT 24 Jun 11 12:35:55 PM PDT 24 5558078478 ps
T71 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2524750304 Jun 11 12:35:53 PM PDT 24 Jun 11 12:36:36 PM PDT 24 8075860611 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.354759482 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:06 PM PDT 24 386371358 ps
T101 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.651811999 Jun 11 12:35:31 PM PDT 24 Jun 11 12:35:43 PM PDT 24 8116398057 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2206307626 Jun 11 12:36:04 PM PDT 24 Jun 11 12:37:25 PM PDT 24 35996956029 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3000055151 Jun 11 12:35:51 PM PDT 24 Jun 11 12:36:09 PM PDT 24 7474729573 ps
T52 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1516168544 Jun 11 12:35:52 PM PDT 24 Jun 11 12:37:03 PM PDT 24 2766749631 ps
T385 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1949407848 Jun 11 12:35:45 PM PDT 24 Jun 11 12:35:59 PM PDT 24 1268456530 ps
T386 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1395317345 Jun 11 12:36:06 PM PDT 24 Jun 11 12:36:20 PM PDT 24 1331525802 ps
T104 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2237797443 Jun 11 12:35:42 PM PDT 24 Jun 11 12:37:13 PM PDT 24 23056598307 ps
T387 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3616101021 Jun 11 12:35:56 PM PDT 24 Jun 11 12:36:58 PM PDT 24 12432764811 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.859041281 Jun 11 12:35:41 PM PDT 24 Jun 11 12:35:50 PM PDT 24 91061191 ps
T102 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2175193259 Jun 11 12:35:44 PM PDT 24 Jun 11 12:36:01 PM PDT 24 14379595994 ps
T389 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4201201518 Jun 11 12:35:45 PM PDT 24 Jun 11 12:35:57 PM PDT 24 1533513312 ps
T53 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.578735803 Jun 11 12:35:41 PM PDT 24 Jun 11 12:36:22 PM PDT 24 1391398576 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2480872973 Jun 11 12:35:43 PM PDT 24 Jun 11 12:36:02 PM PDT 24 2120273041 ps
T391 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.226883223 Jun 11 12:35:52 PM PDT 24 Jun 11 12:35:59 PM PDT 24 385201728 ps
T103 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2781552521 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:02 PM PDT 24 616226876 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3778736754 Jun 11 12:35:35 PM PDT 24 Jun 11 12:35:42 PM PDT 24 90768371 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3713719397 Jun 11 12:35:46 PM PDT 24 Jun 11 12:36:38 PM PDT 24 27531812989 ps
T54 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2956173761 Jun 11 12:35:42 PM PDT 24 Jun 11 12:36:56 PM PDT 24 339635487 ps
T394 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2570918432 Jun 11 12:35:50 PM PDT 24 Jun 11 12:36:05 PM PDT 24 2126989012 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4200011156 Jun 11 12:35:35 PM PDT 24 Jun 11 12:35:41 PM PDT 24 346507081 ps
T396 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.749716074 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:21 PM PDT 24 2236958972 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3105905516 Jun 11 12:35:50 PM PDT 24 Jun 11 12:35:57 PM PDT 24 511652257 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4179913397 Jun 11 12:35:45 PM PDT 24 Jun 11 12:36:14 PM PDT 24 1108848571 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2991028213 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:11 PM PDT 24 1814167312 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1501373461 Jun 11 12:35:41 PM PDT 24 Jun 11 12:36:06 PM PDT 24 722065515 ps
T398 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.246150441 Jun 11 12:35:43 PM PDT 24 Jun 11 12:35:52 PM PDT 24 2072687545 ps
T399 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2447290858 Jun 11 12:37:21 PM PDT 24 Jun 11 12:37:28 PM PDT 24 138806143 ps
T400 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.484275037 Jun 11 12:36:02 PM PDT 24 Jun 11 12:36:15 PM PDT 24 5117707816 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2864387787 Jun 11 12:35:40 PM PDT 24 Jun 11 12:35:52 PM PDT 24 859279891 ps
T402 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1047674759 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:13 PM PDT 24 3858970352 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2648269614 Jun 11 12:35:41 PM PDT 24 Jun 11 12:35:53 PM PDT 24 15797882209 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4263949029 Jun 11 12:35:39 PM PDT 24 Jun 11 12:35:57 PM PDT 24 2185972715 ps
T405 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.150236759 Jun 11 12:35:43 PM PDT 24 Jun 11 12:35:49 PM PDT 24 261228985 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.30870704 Jun 11 12:35:43 PM PDT 24 Jun 11 12:35:49 PM PDT 24 334305244 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1285543816 Jun 11 12:35:40 PM PDT 24 Jun 11 12:35:49 PM PDT 24 587175106 ps
T108 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1505435937 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:33 PM PDT 24 188681113 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2369049845 Jun 11 12:35:45 PM PDT 24 Jun 11 12:35:59 PM PDT 24 7190939798 ps
T408 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.428979903 Jun 11 12:36:03 PM PDT 24 Jun 11 12:36:13 PM PDT 24 172159823 ps
T110 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4044608240 Jun 11 12:35:51 PM PDT 24 Jun 11 12:36:37 PM PDT 24 7672004673 ps
T409 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1558343273 Jun 11 12:35:43 PM PDT 24 Jun 11 12:35:49 PM PDT 24 85480931 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1975431826 Jun 11 12:36:00 PM PDT 24 Jun 11 12:36:07 PM PDT 24 333851027 ps
T112 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3825987163 Jun 11 12:35:55 PM PDT 24 Jun 11 12:37:09 PM PDT 24 1303028084 ps
T118 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3747380404 Jun 11 12:35:44 PM PDT 24 Jun 11 12:36:55 PM PDT 24 4772087391 ps
T109 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3182990877 Jun 11 12:35:56 PM PDT 24 Jun 11 12:37:14 PM PDT 24 1875106619 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.686408294 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:43 PM PDT 24 1662082129 ps
T412 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4182785926 Jun 11 12:35:41 PM PDT 24 Jun 11 12:35:53 PM PDT 24 16503251936 ps
T413 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1839411424 Jun 11 12:35:48 PM PDT 24 Jun 11 12:37:16 PM PDT 24 10453672760 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1492362725 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:06 PM PDT 24 1505335585 ps
T415 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.724330258 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:01 PM PDT 24 271914069 ps
T416 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3936185622 Jun 11 12:35:48 PM PDT 24 Jun 11 12:36:04 PM PDT 24 7038609918 ps
T82 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.743879900 Jun 11 12:35:32 PM PDT 24 Jun 11 12:37:14 PM PDT 24 13335126688 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3421524162 Jun 11 12:35:41 PM PDT 24 Jun 11 12:36:23 PM PDT 24 3799295768 ps
T418 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3414933290 Jun 11 12:35:44 PM PDT 24 Jun 11 12:36:04 PM PDT 24 1866692885 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.496933173 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:04 PM PDT 24 3204065312 ps
T420 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2649398398 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:07 PM PDT 24 536402366 ps
T87 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1142024932 Jun 11 12:35:51 PM PDT 24 Jun 11 12:37:07 PM PDT 24 15841961987 ps
T421 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3765387591 Jun 11 12:36:05 PM PDT 24 Jun 11 12:36:12 PM PDT 24 187294902 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3323567022 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:00 PM PDT 24 1411709733 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1353006037 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:02 PM PDT 24 256222926 ps
T117 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2933619971 Jun 11 12:35:38 PM PDT 24 Jun 11 12:36:54 PM PDT 24 5594712816 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1281358923 Jun 11 12:35:42 PM PDT 24 Jun 11 12:35:59 PM PDT 24 1269347359 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.801080020 Jun 11 12:35:44 PM PDT 24 Jun 11 12:36:02 PM PDT 24 2047396811 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.654838355 Jun 11 12:35:44 PM PDT 24 Jun 11 12:35:53 PM PDT 24 3211388530 ps
T111 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3036152811 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:36 PM PDT 24 4587045549 ps
T105 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2576346470 Jun 11 12:35:43 PM PDT 24 Jun 11 12:36:58 PM PDT 24 5261112008 ps
T88 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1553003497 Jun 11 12:35:57 PM PDT 24 Jun 11 12:36:02 PM PDT 24 922008273 ps
T427 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.215611086 Jun 11 12:35:59 PM PDT 24 Jun 11 12:36:07 PM PDT 24 714506843 ps
T428 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2856693544 Jun 11 12:35:53 PM PDT 24 Jun 11 12:35:59 PM PDT 24 332691502 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1035495872 Jun 11 12:35:40 PM PDT 24 Jun 11 12:36:21 PM PDT 24 300403572 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.97856072 Jun 11 12:35:39 PM PDT 24 Jun 11 12:35:59 PM PDT 24 3338820964 ps
T430 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1614358638 Jun 11 12:35:43 PM PDT 24 Jun 11 12:36:00 PM PDT 24 1950235737 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3273500667 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:09 PM PDT 24 6472241743 ps
T432 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3854459608 Jun 11 12:35:43 PM PDT 24 Jun 11 12:36:17 PM PDT 24 826297957 ps
T116 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1811047977 Jun 11 12:35:41 PM PDT 24 Jun 11 12:36:28 PM PDT 24 1737687944 ps
T433 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4037651663 Jun 11 12:36:04 PM PDT 24 Jun 11 12:36:18 PM PDT 24 3134587692 ps
T434 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2685629581 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:06 PM PDT 24 3461439221 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2093280016 Jun 11 12:35:37 PM PDT 24 Jun 11 12:35:44 PM PDT 24 1479431813 ps
T436 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2141962448 Jun 11 12:36:06 PM PDT 24 Jun 11 12:36:45 PM PDT 24 2698285511 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3362990624 Jun 11 12:35:44 PM PDT 24 Jun 11 12:36:05 PM PDT 24 8666923076 ps
T438 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1260891889 Jun 11 12:36:05 PM PDT 24 Jun 11 12:36:19 PM PDT 24 1440240057 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.399091967 Jun 11 12:35:56 PM PDT 24 Jun 11 12:37:07 PM PDT 24 546748142 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.163129297 Jun 11 12:35:56 PM PDT 24 Jun 11 12:36:13 PM PDT 24 8102722865 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2760179408 Jun 11 12:35:55 PM PDT 24 Jun 11 12:36:07 PM PDT 24 1330159486 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.772735075 Jun 11 12:36:09 PM PDT 24 Jun 11 12:36:49 PM PDT 24 798034393 ps
T441 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1408569940 Jun 11 12:35:45 PM PDT 24 Jun 11 12:36:00 PM PDT 24 2866599966 ps
T442 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3642263464 Jun 11 12:36:00 PM PDT 24 Jun 11 12:36:12 PM PDT 24 5060007647 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.814101962 Jun 11 12:35:52 PM PDT 24 Jun 11 12:35:59 PM PDT 24 88913513 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3834896248 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:13 PM PDT 24 7521394214 ps
T445 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.958811580 Jun 11 12:35:54 PM PDT 24 Jun 11 12:36:06 PM PDT 24 629571513 ps
T446 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.892438844 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:07 PM PDT 24 1262689809 ps
T447 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1560075932 Jun 11 12:35:42 PM PDT 24 Jun 11 12:35:54 PM PDT 24 989570933 ps
T448 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2762718981 Jun 11 12:35:44 PM PDT 24 Jun 11 12:36:30 PM PDT 24 5054166421 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1716249205 Jun 11 12:35:42 PM PDT 24 Jun 11 12:36:00 PM PDT 24 8246439571 ps
T450 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1292466929 Jun 11 12:35:56 PM PDT 24 Jun 11 12:36:12 PM PDT 24 6876376145 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2673332997 Jun 11 12:36:08 PM PDT 24 Jun 11 12:36:21 PM PDT 24 2913673339 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4192470005 Jun 11 12:35:56 PM PDT 24 Jun 11 12:37:15 PM PDT 24 1959753135 ps
T452 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1920646552 Jun 11 12:35:50 PM PDT 24 Jun 11 12:35:55 PM PDT 24 89265163 ps
T453 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3523774055 Jun 11 12:35:51 PM PDT 24 Jun 11 12:36:09 PM PDT 24 1957474363 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2896700117 Jun 11 12:35:44 PM PDT 24 Jun 11 12:36:01 PM PDT 24 9248465690 ps
T115 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3818402756 Jun 11 12:35:53 PM PDT 24 Jun 11 12:37:08 PM PDT 24 5435889208 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2560353590 Jun 11 12:35:45 PM PDT 24 Jun 11 12:35:51 PM PDT 24 378738241 ps
T454 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.540075380 Jun 11 12:35:54 PM PDT 24 Jun 11 12:36:07 PM PDT 24 1193030829 ps
T455 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.8050788 Jun 11 12:35:44 PM PDT 24 Jun 11 12:35:59 PM PDT 24 6015858569 ps
T456 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1427077532 Jun 11 12:35:43 PM PDT 24 Jun 11 12:36:21 PM PDT 24 3343459321 ps
T457 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.505143457 Jun 11 12:35:36 PM PDT 24 Jun 11 12:35:42 PM PDT 24 88315850 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.454722903 Jun 11 12:35:53 PM PDT 24 Jun 11 12:36:23 PM PDT 24 2225855677 ps
T458 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2252603400 Jun 11 12:35:50 PM PDT 24 Jun 11 12:35:59 PM PDT 24 4512267370 ps
T459 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1513159151 Jun 11 12:35:52 PM PDT 24 Jun 11 12:36:05 PM PDT 24 1984756929 ps
T460 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3802071664 Jun 11 12:35:42 PM PDT 24 Jun 11 12:35:57 PM PDT 24 1608686901 ps
T461 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1603526921 Jun 11 12:35:53 PM PDT 24 Jun 11 12:35:59 PM PDT 24 87083923 ps
T462 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3329527433 Jun 11 12:35:54 PM PDT 24 Jun 11 12:36:43 PM PDT 24 19648647199 ps

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2628633052
Short name T10
Test name
Test status
Simulation time 38110918650 ps
CPU time 369.82 seconds
Started Jun 11 12:36:26 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 212288 kb
Host smart-171c0b0b-641d-422a-841b-e5fdd346ff0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628633052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2628633052
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4090056247
Short name T21
Test name
Test status
Simulation time 322028368853 ps
CPU time 2916.58 seconds
Started Jun 11 12:36:26 PM PDT 24
Finished Jun 11 01:25:04 PM PDT 24
Peak memory 243720 kb
Host smart-892f4222-271a-4f2f-b777-49c215aa62be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090056247 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4090056247
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1809897697
Short name T1
Test name
Test status
Simulation time 1629512825 ps
CPU time 17.1 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:37 PM PDT 24
Peak memory 214920 kb
Host smart-44a1745c-3f27-40a6-bac5-cf4673039709
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809897697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1809897697
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1494700116
Short name T31
Test name
Test status
Simulation time 11580588461 ps
CPU time 143.19 seconds
Started Jun 11 12:36:36 PM PDT 24
Finished Jun 11 12:39:01 PM PDT 24
Peak memory 233508 kb
Host smart-033eeeed-1b76-4221-9fa5-ca037690fa7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494700116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1494700116
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1516168544
Short name T52
Test name
Test status
Simulation time 2766749631 ps
CPU time 68.99 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:37:03 PM PDT 24
Peak memory 212456 kb
Host smart-af9067c2-688f-48f8-8cc8-9cba5af86523
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516168544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1516168544
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4024495096
Short name T38
Test name
Test status
Simulation time 1302264443 ps
CPU time 16.91 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:36 PM PDT 24
Peak memory 211936 kb
Host smart-9fd6f225-2e7c-47a8-8954-fe5d62fde706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024495096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4024495096
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3395457209
Short name T16
Test name
Test status
Simulation time 1564240576 ps
CPU time 64.16 seconds
Started Jun 11 12:36:10 PM PDT 24
Finished Jun 11 12:37:16 PM PDT 24
Peak memory 240360 kb
Host smart-1bdee5f1-1e3a-4224-8262-39c84062f619
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395457209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3395457209
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1610334462
Short name T64
Test name
Test status
Simulation time 8056186508 ps
CPU time 75.96 seconds
Started Jun 11 12:35:50 PM PDT 24
Finished Jun 11 12:37:07 PM PDT 24
Peak memory 211052 kb
Host smart-d95ca7c4-7b7c-49ca-8a24-266cf25ab48a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610334462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1610334462
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3747380404
Short name T118
Test name
Test status
Simulation time 4772087391 ps
CPU time 69.57 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:36:55 PM PDT 24
Peak memory 219236 kb
Host smart-58b98c47-c28b-4c59-a636-6395c0d06f38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747380404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3747380404
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1729295241
Short name T19
Test name
Test status
Simulation time 10647278882 ps
CPU time 9.19 seconds
Started Jun 11 12:37:01 PM PDT 24
Finished Jun 11 12:37:12 PM PDT 24
Peak memory 210896 kb
Host smart-1967f87b-b147-44d9-8937-eba31a71bbdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729295241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1729295241
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3762418129
Short name T36
Test name
Test status
Simulation time 218391459 ps
CPU time 9.41 seconds
Started Jun 11 12:36:24 PM PDT 24
Finished Jun 11 12:36:35 PM PDT 24
Peak memory 211612 kb
Host smart-eeaa355d-08b1-4d67-b685-e146196098b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762418129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3762418129
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1172467455
Short name T25
Test name
Test status
Simulation time 3923282649 ps
CPU time 20.78 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:36:55 PM PDT 24
Peak memory 211648 kb
Host smart-8be95710-10ae-46be-8fec-1ce963c3df0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172467455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1172467455
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2331076372
Short name T76
Test name
Test status
Simulation time 7973149358 ps
CPU time 29.52 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:37:03 PM PDT 24
Peak memory 214292 kb
Host smart-1466a701-b063-44a0-a013-6126b5f4c767
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331076372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2331076372
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4192470005
Short name T107
Test name
Test status
Simulation time 1959753135 ps
CPU time 77.84 seconds
Started Jun 11 12:35:56 PM PDT 24
Finished Jun 11 12:37:15 PM PDT 24
Peak memory 211248 kb
Host smart-9ab4559b-3504-444f-a05e-9bba2daff68a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192470005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4192470005
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1501373461
Short name T81
Test name
Test status
Simulation time 722065515 ps
CPU time 23.06 seconds
Started Jun 11 12:35:41 PM PDT 24
Finished Jun 11 12:36:06 PM PDT 24
Peak memory 210968 kb
Host smart-3dc0e154-ff53-45b4-bf84-11ff4a5c88e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501373461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1501373461
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4044608240
Short name T110
Test name
Test status
Simulation time 7672004673 ps
CPU time 44.1 seconds
Started Jun 11 12:35:51 PM PDT 24
Finished Jun 11 12:36:37 PM PDT 24
Peak memory 219124 kb
Host smart-ec0e179f-cd47-492d-8547-edf935c6bc57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044608240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4044608240
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.651811999
Short name T101
Test name
Test status
Simulation time 8116398057 ps
CPU time 10.91 seconds
Started Jun 11 12:35:31 PM PDT 24
Finished Jun 11 12:35:43 PM PDT 24
Peak memory 211252 kb
Host smart-7f7927a2-0494-49fd-a40a-1477f6f10851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651811999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.651811999
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2634079970
Short name T89
Test name
Test status
Simulation time 1372270211 ps
CPU time 13.18 seconds
Started Jun 11 12:36:11 PM PDT 24
Finished Jun 11 12:36:25 PM PDT 24
Peak memory 210880 kb
Host smart-a7436e14-618b-4e0d-b984-afdaca243277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634079970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2634079970
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2771802573
Short name T35
Test name
Test status
Simulation time 23508693515 ps
CPU time 2464.55 seconds
Started Jun 11 12:36:40 PM PDT 24
Finished Jun 11 01:17:46 PM PDT 24
Peak memory 225876 kb
Host smart-4b743a8c-0351-4365-9df5-f2fd4d8bc0cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771802573 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2771802573
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4233119898
Short name T46
Test name
Test status
Simulation time 72378966974 ps
CPU time 1884.09 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 01:07:56 PM PDT 24
Peak memory 236164 kb
Host smart-c109cfc1-bd01-4f9f-8ccf-2a5c89b7170d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233119898 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.4233119898
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2093280016
Short name T435
Test name
Test status
Simulation time 1479431813 ps
CPU time 5.71 seconds
Started Jun 11 12:35:37 PM PDT 24
Finished Jun 11 12:35:44 PM PDT 24
Peak memory 218236 kb
Host smart-bcbe5dce-fd93-4141-919a-48d698c4badc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093280016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2093280016
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.505143457
Short name T457
Test name
Test status
Simulation time 88315850 ps
CPU time 4.57 seconds
Started Jun 11 12:35:36 PM PDT 24
Finished Jun 11 12:35:42 PM PDT 24
Peak memory 218152 kb
Host smart-e0b1a0bf-e0bc-44a7-84b5-e61b48b53186
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505143457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.505143457
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.686408294
Short name T411
Test name
Test status
Simulation time 1662082129 ps
CPU time 8.13 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:43 PM PDT 24
Peak memory 210932 kb
Host smart-dc7d4580-f1bf-4ee9-bec9-a7c8a4807282
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686408294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.686408294
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.558681256
Short name T370
Test name
Test status
Simulation time 3858217092 ps
CPU time 11.25 seconds
Started Jun 11 12:35:39 PM PDT 24
Finished Jun 11 12:35:52 PM PDT 24
Peak memory 219240 kb
Host smart-d1df40b5-e78c-4377-9543-fa4576d1d6be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558681256 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.558681256
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3522580370
Short name T62
Test name
Test status
Simulation time 613795400 ps
CPU time 8.36 seconds
Started Jun 11 12:35:35 PM PDT 24
Finished Jun 11 12:35:45 PM PDT 24
Peak memory 210944 kb
Host smart-ebcb029e-d2e2-4ae7-910e-2b1d19b32c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522580370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3522580370
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3778736754
Short name T392
Test name
Test status
Simulation time 90768371 ps
CPU time 4.12 seconds
Started Jun 11 12:35:35 PM PDT 24
Finished Jun 11 12:35:42 PM PDT 24
Peak memory 210612 kb
Host smart-44fa7f7e-8a9a-46d8-b24f-da3a5f03b2c5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778736754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3778736754
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4200011156
Short name T395
Test name
Test status
Simulation time 346507081 ps
CPU time 4.29 seconds
Started Jun 11 12:35:35 PM PDT 24
Finished Jun 11 12:35:41 PM PDT 24
Peak memory 210652 kb
Host smart-ba3692ad-4c1a-40e4-a996-26c29f0621f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200011156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4200011156
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.743879900
Short name T82
Test name
Test status
Simulation time 13335126688 ps
CPU time 99.52 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:37:14 PM PDT 24
Peak memory 211008 kb
Host smart-cda61610-f41e-4dab-b1ba-24650d356311
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743879900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.743879900
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3995504255
Short name T373
Test name
Test status
Simulation time 2210313973 ps
CPU time 20.58 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:36:01 PM PDT 24
Peak memory 219092 kb
Host smart-38f41d01-3afb-40df-9453-f141b4471fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995504255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3995504255
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2933619971
Short name T117
Test name
Test status
Simulation time 5594712816 ps
CPU time 73.71 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:36:54 PM PDT 24
Peak memory 212640 kb
Host smart-e6e8788a-3952-44a9-8106-d743e363c81b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933619971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2933619971
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.252218888
Short name T70
Test name
Test status
Simulation time 5558078478 ps
CPU time 11.01 seconds
Started Jun 11 12:35:42 PM PDT 24
Finished Jun 11 12:35:55 PM PDT 24
Peak memory 217980 kb
Host smart-ddf491ab-a5ad-4f9b-aa00-7e62edbe934d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252218888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.252218888
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3983658876
Short name T372
Test name
Test status
Simulation time 11383020725 ps
CPU time 16.62 seconds
Started Jun 11 12:35:45 PM PDT 24
Finished Jun 11 12:36:03 PM PDT 24
Peak memory 211060 kb
Host smart-03d7aec9-4234-4b5c-9efb-5b0e7ccdaea1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983658876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3983658876
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2480872973
Short name T390
Test name
Test status
Simulation time 2120273041 ps
CPU time 17.38 seconds
Started Jun 11 12:35:43 PM PDT 24
Finished Jun 11 12:36:02 PM PDT 24
Peak memory 219048 kb
Host smart-a49a6495-a03b-42eb-9d2a-7697015800c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480872973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2480872973
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3395851448
Short name T57
Test name
Test status
Simulation time 1042720726 ps
CPU time 10.38 seconds
Started Jun 11 12:35:40 PM PDT 24
Finished Jun 11 12:35:52 PM PDT 24
Peak memory 219192 kb
Host smart-ebbfc19d-2280-4f90-b705-1054e4b96d20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395851448 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3395851448
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3273500667
Short name T431
Test name
Test status
Simulation time 6472241743 ps
CPU time 13.03 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:09 PM PDT 24
Peak memory 210988 kb
Host smart-83a97e1a-d92e-4f43-b016-6cd9ec799ba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273500667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3273500667
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2425388297
Short name T376
Test name
Test status
Simulation time 668421935 ps
CPU time 8.6 seconds
Started Jun 11 12:35:42 PM PDT 24
Finished Jun 11 12:35:52 PM PDT 24
Peak memory 210708 kb
Host smart-e4644f3a-37ff-41a4-8406-d1095fef0f3d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425388297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2425388297
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1330459511
Short name T369
Test name
Test status
Simulation time 1937701428 ps
CPU time 15.09 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:36:01 PM PDT 24
Peak memory 210712 kb
Host smart-a4e58ad4-f126-484d-9b31-35f849fb7783
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330459511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1330459511
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2864387787
Short name T401
Test name
Test status
Simulation time 859279891 ps
CPU time 10.55 seconds
Started Jun 11 12:35:40 PM PDT 24
Finished Jun 11 12:35:52 PM PDT 24
Peak memory 210892 kb
Host smart-935654ab-032f-4081-9930-e707b62cb91a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864387787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2864387787
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.97856072
Short name T429
Test name
Test status
Simulation time 3338820964 ps
CPU time 17.8 seconds
Started Jun 11 12:35:39 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 219052 kb
Host smart-32df8d54-8ab2-4109-9c14-e5d017519ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97856072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.97856072
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1035495872
Short name T114
Test name
Test status
Simulation time 300403572 ps
CPU time 39.75 seconds
Started Jun 11 12:35:40 PM PDT 24
Finished Jun 11 12:36:21 PM PDT 24
Peak memory 213276 kb
Host smart-27b333bd-11c5-44c5-afdc-8a475ac72cad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035495872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1035495872
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2447290858
Short name T399
Test name
Test status
Simulation time 138806143 ps
CPU time 5.07 seconds
Started Jun 11 12:37:21 PM PDT 24
Finished Jun 11 12:37:28 PM PDT 24
Peak memory 219220 kb
Host smart-49d44d2a-3f54-48ab-b10a-702509015e51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447290858 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2447290858
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1949407848
Short name T385
Test name
Test status
Simulation time 1268456530 ps
CPU time 12.08 seconds
Started Jun 11 12:35:45 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 218896 kb
Host smart-3bb1fc77-45fd-47a5-9af1-c0e29f5e6a60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949407848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1949407848
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3001707276
Short name T377
Test name
Test status
Simulation time 381183113 ps
CPU time 18.7 seconds
Started Jun 11 12:35:50 PM PDT 24
Finished Jun 11 12:36:10 PM PDT 24
Peak memory 210996 kb
Host smart-6a4f81f9-2348-44e9-b417-466f01b5d6a6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001707276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3001707276
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1560075932
Short name T447
Test name
Test status
Simulation time 989570933 ps
CPU time 10.27 seconds
Started Jun 11 12:35:42 PM PDT 24
Finished Jun 11 12:35:54 PM PDT 24
Peak memory 210980 kb
Host smart-1cefbeee-3d66-41c1-94e1-79cc214657aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560075932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1560075932
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3523774055
Short name T453
Test name
Test status
Simulation time 1957474363 ps
CPU time 16.62 seconds
Started Jun 11 12:35:51 PM PDT 24
Finished Jun 11 12:36:09 PM PDT 24
Peak memory 218912 kb
Host smart-854378a9-63c7-4426-ae85-a6f0377d0d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523774055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3523774055
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2762718981
Short name T448
Test name
Test status
Simulation time 5054166421 ps
CPU time 45.05 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:36:30 PM PDT 24
Peak memory 210980 kb
Host smart-6f72c663-a82e-4baf-a40a-164d7838a7a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762718981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2762718981
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1513159151
Short name T459
Test name
Test status
Simulation time 1984756929 ps
CPU time 11.4 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:05 PM PDT 24
Peak memory 219176 kb
Host smart-a5a3828e-d259-4548-a93e-679a01ba295d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513159151 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1513159151
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1920646552
Short name T452
Test name
Test status
Simulation time 89265163 ps
CPU time 4.11 seconds
Started Jun 11 12:35:50 PM PDT 24
Finished Jun 11 12:35:55 PM PDT 24
Peak memory 210828 kb
Host smart-52b73349-be19-44fb-8bfd-0418cebf6d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920646552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1920646552
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3986848905
Short name T65
Test name
Test status
Simulation time 15110957598 ps
CPU time 48.49 seconds
Started Jun 11 12:35:45 PM PDT 24
Finished Jun 11 12:36:35 PM PDT 24
Peak memory 211024 kb
Host smart-cfe1101c-c33d-4fc7-a332-19e9aa5c71cf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986848905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3986848905
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1494039450
Short name T100
Test name
Test status
Simulation time 1209703878 ps
CPU time 8.17 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:03 PM PDT 24
Peak memory 210908 kb
Host smart-3143bf78-f70b-4ce0-8352-2f44dd13ecc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494039450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1494039450
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2685629581
Short name T434
Test name
Test status
Simulation time 3461439221 ps
CPU time 9.48 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:06 PM PDT 24
Peak memory 212212 kb
Host smart-6ec530c0-bb5a-4f21-891e-c1c88aa774ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685629581 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2685629581
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1603526921
Short name T461
Test name
Test status
Simulation time 87083923 ps
CPU time 4.06 seconds
Started Jun 11 12:35:53 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 210796 kb
Host smart-a7afcf87-ff2b-446a-9cdc-fc4cc5d4f207
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603526921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1603526921
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2524750304
Short name T71
Test name
Test status
Simulation time 8075860611 ps
CPU time 41.19 seconds
Started Jun 11 12:35:53 PM PDT 24
Finished Jun 11 12:36:36 PM PDT 24
Peak memory 210996 kb
Host smart-853cc417-5140-460b-9432-952b58862099
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524750304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2524750304
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2665923760
Short name T67
Test name
Test status
Simulation time 4602944243 ps
CPU time 12.55 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:09 PM PDT 24
Peak memory 219144 kb
Host smart-9bd9622f-89be-4ed3-9a03-d1059ba972a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665923760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2665923760
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1292466929
Short name T450
Test name
Test status
Simulation time 6876376145 ps
CPU time 15.04 seconds
Started Jun 11 12:35:56 PM PDT 24
Finished Jun 11 12:36:12 PM PDT 24
Peak memory 215368 kb
Host smart-1146f8a6-73ac-4f7d-bf0f-ab36427cd015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292466929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1292466929
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3818402756
Short name T115
Test name
Test status
Simulation time 5435889208 ps
CPU time 73.24 seconds
Started Jun 11 12:35:53 PM PDT 24
Finished Jun 11 12:37:08 PM PDT 24
Peak memory 212848 kb
Host smart-7e3142f1-0d05-495d-8167-ac317ca5a13d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818402756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3818402756
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.724330258
Short name T415
Test name
Test status
Simulation time 271914069 ps
CPU time 6.69 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:01 PM PDT 24
Peak memory 219148 kb
Host smart-1e15bb29-ad20-4f4d-b080-3cfe77a65a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724330258 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.724330258
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1553003497
Short name T88
Test name
Test status
Simulation time 922008273 ps
CPU time 4.08 seconds
Started Jun 11 12:35:57 PM PDT 24
Finished Jun 11 12:36:02 PM PDT 24
Peak memory 210928 kb
Host smart-707148f4-957e-4382-91a5-32d85ab4d4c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553003497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1553003497
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3677020853
Short name T68
Test name
Test status
Simulation time 4845116400 ps
CPU time 45.63 seconds
Started Jun 11 12:36:00 PM PDT 24
Finished Jun 11 12:36:46 PM PDT 24
Peak memory 219240 kb
Host smart-19114043-6a0d-4b73-b01d-be0801b5b4b4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677020853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3677020853
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.215611086
Short name T427
Test name
Test status
Simulation time 714506843 ps
CPU time 6.65 seconds
Started Jun 11 12:35:59 PM PDT 24
Finished Jun 11 12:36:07 PM PDT 24
Peak memory 211008 kb
Host smart-67bbc5d1-9bc0-4eef-a9a6-18ddec239579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215611086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.215611086
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.534011201
Short name T371
Test name
Test status
Simulation time 1327359495 ps
CPU time 14.72 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:11 PM PDT 24
Peak memory 218312 kb
Host smart-60def819-4a56-479f-8659-8eb284dc390f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534011201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.534011201
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1505435937
Short name T108
Test name
Test status
Simulation time 188681113 ps
CPU time 36.1 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 212376 kb
Host smart-0cf785b6-7c9a-418c-9613-5535012efb2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505435937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1505435937
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3000055151
Short name T384
Test name
Test status
Simulation time 7474729573 ps
CPU time 16.72 seconds
Started Jun 11 12:35:51 PM PDT 24
Finished Jun 11 12:36:09 PM PDT 24
Peak memory 219176 kb
Host smart-474975ee-3df1-42bb-a713-f380aaf6d1bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000055151 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3000055151
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.163129297
Short name T439
Test name
Test status
Simulation time 8102722865 ps
CPU time 15.83 seconds
Started Jun 11 12:35:56 PM PDT 24
Finished Jun 11 12:36:13 PM PDT 24
Peak memory 211016 kb
Host smart-96f073d6-fa62-435a-a710-11af87090c9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163129297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.163129297
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.749716074
Short name T396
Test name
Test status
Simulation time 2236958972 ps
CPU time 27.22 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:21 PM PDT 24
Peak memory 211068 kb
Host smart-4f7c8c91-5baa-4741-8eec-15d764d4674d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749716074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.749716074
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.892438844
Short name T446
Test name
Test status
Simulation time 1262689809 ps
CPU time 11.82 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:07 PM PDT 24
Peak memory 218400 kb
Host smart-510f64c7-ad06-40d0-8222-a127581f4b1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892438844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.892438844
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2649398398
Short name T420
Test name
Test status
Simulation time 536402366 ps
CPU time 12.03 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:07 PM PDT 24
Peak memory 219048 kb
Host smart-a7d2709d-b0c9-48b7-a979-acdc3edae333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649398398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2649398398
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.399091967
Short name T106
Test name
Test status
Simulation time 546748142 ps
CPU time 69.83 seconds
Started Jun 11 12:35:56 PM PDT 24
Finished Jun 11 12:37:07 PM PDT 24
Peak memory 212464 kb
Host smart-bd185c83-a013-418d-a608-f71020cd76f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399091967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.399091967
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.540075380
Short name T454
Test name
Test status
Simulation time 1193030829 ps
CPU time 11.31 seconds
Started Jun 11 12:35:54 PM PDT 24
Finished Jun 11 12:36:07 PM PDT 24
Peak memory 218968 kb
Host smart-88503b18-a499-45d1-aac7-d3772a0c0502
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540075380 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.540075380
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2856693544
Short name T428
Test name
Test status
Simulation time 332691502 ps
CPU time 4.02 seconds
Started Jun 11 12:35:53 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 210796 kb
Host smart-2bea1cfc-b8f5-4d56-b09c-ed85261281f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856693544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2856693544
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3329527433
Short name T462
Test name
Test status
Simulation time 19648647199 ps
CPU time 46.92 seconds
Started Jun 11 12:35:54 PM PDT 24
Finished Jun 11 12:36:43 PM PDT 24
Peak memory 211036 kb
Host smart-99810d8d-9922-4019-92b7-9c3be7b43fae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329527433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3329527433
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.814101962
Short name T443
Test name
Test status
Simulation time 88913513 ps
CPU time 4.34 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 211012 kb
Host smart-61360052-bc78-4cf9-a713-f2565302cab4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814101962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.814101962
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.354759482
Short name T383
Test name
Test status
Simulation time 386371358 ps
CPU time 11.72 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:06 PM PDT 24
Peak memory 219020 kb
Host smart-62ec78e8-d6f5-4b9d-ae9f-0941ff6d84d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354759482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.354759482
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.226883223
Short name T391
Test name
Test status
Simulation time 385201728 ps
CPU time 4.58 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 219040 kb
Host smart-32439346-1ce4-40bb-b3b9-7d21df37c3fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226883223 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.226883223
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.716017958
Short name T66
Test name
Test status
Simulation time 2977070579 ps
CPU time 12.85 seconds
Started Jun 11 12:35:54 PM PDT 24
Finished Jun 11 12:36:09 PM PDT 24
Peak memory 218800 kb
Host smart-2e5176f6-2561-4695-b248-3dd5dc875570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716017958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.716017958
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3616101021
Short name T387
Test name
Test status
Simulation time 12432764811 ps
CPU time 60.17 seconds
Started Jun 11 12:35:56 PM PDT 24
Finished Jun 11 12:36:58 PM PDT 24
Peak memory 211004 kb
Host smart-438d4563-77c5-4dac-939e-be0af899fe4e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616101021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3616101021
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.496933173
Short name T419
Test name
Test status
Simulation time 3204065312 ps
CPU time 9.09 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:04 PM PDT 24
Peak memory 219140 kb
Host smart-3f617c6e-d8eb-42aa-8de2-99d672b5d2a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496933173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.496933173
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.958811580
Short name T445
Test name
Test status
Simulation time 629571513 ps
CPU time 10.66 seconds
Started Jun 11 12:35:54 PM PDT 24
Finished Jun 11 12:36:06 PM PDT 24
Peak memory 218888 kb
Host smart-14d7363f-ca24-4511-bdf7-878f36f979c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958811580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.958811580
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4078360281
Short name T381
Test name
Test status
Simulation time 10198260151 ps
CPU time 11.84 seconds
Started Jun 11 12:35:58 PM PDT 24
Finished Jun 11 12:36:11 PM PDT 24
Peak memory 219268 kb
Host smart-23fb7cc4-6814-474d-818e-11de9ca10503
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078360281 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4078360281
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3642263464
Short name T442
Test name
Test status
Simulation time 5060007647 ps
CPU time 11.42 seconds
Started Jun 11 12:36:00 PM PDT 24
Finished Jun 11 12:36:12 PM PDT 24
Peak memory 211056 kb
Host smart-de5a7a97-79d1-40a1-b303-a199015697e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642263464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3642263464
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.454722903
Short name T85
Test name
Test status
Simulation time 2225855677 ps
CPU time 28.22 seconds
Started Jun 11 12:35:53 PM PDT 24
Finished Jun 11 12:36:23 PM PDT 24
Peak memory 211312 kb
Host smart-e752ae0d-a4df-4123-bb2c-4f63b5cd88af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454722903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.454722903
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2749816363
Short name T99
Test name
Test status
Simulation time 2713724198 ps
CPU time 13.88 seconds
Started Jun 11 12:35:54 PM PDT 24
Finished Jun 11 12:36:09 PM PDT 24
Peak memory 211288 kb
Host smart-e33b85f3-c594-43d1-96e7-ecdd9367fdce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749816363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2749816363
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1975431826
Short name T410
Test name
Test status
Simulation time 333851027 ps
CPU time 6.67 seconds
Started Jun 11 12:36:00 PM PDT 24
Finished Jun 11 12:36:07 PM PDT 24
Peak memory 219052 kb
Host smart-6f53cc89-85c1-4579-81a9-32044bb41864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975431826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1975431826
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3182990877
Short name T109
Test name
Test status
Simulation time 1875106619 ps
CPU time 76.79 seconds
Started Jun 11 12:35:56 PM PDT 24
Finished Jun 11 12:37:14 PM PDT 24
Peak memory 212568 kb
Host smart-b5f703d6-ebb9-4733-aab5-f2047fd97d14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182990877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3182990877
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1395317345
Short name T386
Test name
Test status
Simulation time 1331525802 ps
CPU time 12.34 seconds
Started Jun 11 12:36:06 PM PDT 24
Finished Jun 11 12:36:20 PM PDT 24
Peak memory 219184 kb
Host smart-a105ea3c-454b-4cf1-8751-5e01d6faefa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395317345 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1395317345
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1260891889
Short name T438
Test name
Test status
Simulation time 1440240057 ps
CPU time 12.72 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:19 PM PDT 24
Peak memory 210812 kb
Host smart-c8118f73-a085-450b-842a-dcda93db3d13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260891889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1260891889
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2647626518
Short name T69
Test name
Test status
Simulation time 46116893498 ps
CPU time 90.14 seconds
Started Jun 11 12:36:03 PM PDT 24
Finished Jun 11 12:37:34 PM PDT 24
Peak memory 211276 kb
Host smart-3c0ff1eb-b7f8-4f6f-a946-86f3360884a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647626518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2647626518
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4293315268
Short name T63
Test name
Test status
Simulation time 334221503 ps
CPU time 4.25 seconds
Started Jun 11 12:36:03 PM PDT 24
Finished Jun 11 12:36:08 PM PDT 24
Peak memory 210940 kb
Host smart-5ae846ae-2094-44a5-969b-8f52cc973872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293315268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.4293315268
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.428979903
Short name T408
Test name
Test status
Simulation time 172159823 ps
CPU time 8.95 seconds
Started Jun 11 12:36:03 PM PDT 24
Finished Jun 11 12:36:13 PM PDT 24
Peak memory 219048 kb
Host smart-411b14d3-012d-4f32-95d1-466e712440f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428979903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.428979903
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2141962448
Short name T436
Test name
Test status
Simulation time 2698285511 ps
CPU time 37.73 seconds
Started Jun 11 12:36:06 PM PDT 24
Finished Jun 11 12:36:45 PM PDT 24
Peak memory 212328 kb
Host smart-0a7ac79e-970a-42ce-a2d2-89fb2440d96a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141962448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2141962448
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3765387591
Short name T421
Test name
Test status
Simulation time 187294902 ps
CPU time 6.3 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:12 PM PDT 24
Peak memory 219136 kb
Host smart-f64048b2-86ec-4930-a05e-72acdd010f77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765387591 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3765387591
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.484275037
Short name T400
Test name
Test status
Simulation time 5117707816 ps
CPU time 12.29 seconds
Started Jun 11 12:36:02 PM PDT 24
Finished Jun 11 12:36:15 PM PDT 24
Peak memory 210996 kb
Host smart-ce5b7210-1dd6-4a5c-9da5-fd03ddb57012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484275037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.484275037
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2206307626
Short name T78
Test name
Test status
Simulation time 35996956029 ps
CPU time 79.14 seconds
Started Jun 11 12:36:04 PM PDT 24
Finished Jun 11 12:37:25 PM PDT 24
Peak memory 210968 kb
Host smart-7d58e127-60e1-4e74-a835-82dd1d57c7d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206307626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2206307626
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4037651663
Short name T433
Test name
Test status
Simulation time 3134587692 ps
CPU time 12.57 seconds
Started Jun 11 12:36:04 PM PDT 24
Finished Jun 11 12:36:18 PM PDT 24
Peak memory 219008 kb
Host smart-40acc770-1f87-4559-a800-6f33c4b83395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037651663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4037651663
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2673332997
Short name T451
Test name
Test status
Simulation time 2913673339 ps
CPU time 11.95 seconds
Started Jun 11 12:36:08 PM PDT 24
Finished Jun 11 12:36:21 PM PDT 24
Peak memory 219084 kb
Host smart-99561d86-2dae-4a87-8695-398c839c7142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673332997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2673332997
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.772735075
Short name T113
Test name
Test status
Simulation time 798034393 ps
CPU time 38.76 seconds
Started Jun 11 12:36:09 PM PDT 24
Finished Jun 11 12:36:49 PM PDT 24
Peak memory 212404 kb
Host smart-789927e9-a793-4a52-8bbe-a93fe64f2342
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772735075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.772735075
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3802071664
Short name T460
Test name
Test status
Simulation time 1608686901 ps
CPU time 13.83 seconds
Started Jun 11 12:35:42 PM PDT 24
Finished Jun 11 12:35:57 PM PDT 24
Peak memory 210916 kb
Host smart-8cb05ebc-ad64-4587-b981-45df45819074
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802071664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3802071664
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2760179408
Short name T440
Test name
Test status
Simulation time 1330159486 ps
CPU time 10.26 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:07 PM PDT 24
Peak memory 210952 kb
Host smart-752bf02e-0213-4bc3-a0ee-37f09f58213b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760179408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2760179408
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1281358923
Short name T424
Test name
Test status
Simulation time 1269347359 ps
CPU time 15.06 seconds
Started Jun 11 12:35:42 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 218704 kb
Host smart-a39f077b-8006-4193-85c0-3caf8bcdf76b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281358923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1281358923
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3105905516
Short name T397
Test name
Test status
Simulation time 511652257 ps
CPU time 4.99 seconds
Started Jun 11 12:35:50 PM PDT 24
Finished Jun 11 12:35:57 PM PDT 24
Peak memory 219140 kb
Host smart-520e930f-f366-4987-a9a3-800916c17025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105905516 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3105905516
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.801080020
Short name T425
Test name
Test status
Simulation time 2047396811 ps
CPU time 16.73 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:36:02 PM PDT 24
Peak memory 210972 kb
Host smart-0a2ef3d6-42f3-4b40-b51d-72998629dfbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801080020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.801080020
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.654838355
Short name T426
Test name
Test status
Simulation time 3211388530 ps
CPU time 7.7 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:35:53 PM PDT 24
Peak memory 210772 kb
Host smart-98ad9b98-0f35-462d-ba94-ac03312d2646
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654838355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.654838355
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2648269614
Short name T403
Test name
Test status
Simulation time 15797882209 ps
CPU time 10.14 seconds
Started Jun 11 12:35:41 PM PDT 24
Finished Jun 11 12:35:53 PM PDT 24
Peak memory 210724 kb
Host smart-7f966b0e-b1cb-4bab-82a7-65a4c4da5082
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648269614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2648269614
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4179913397
Short name T79
Test name
Test status
Simulation time 1108848571 ps
CPU time 28.05 seconds
Started Jun 11 12:35:45 PM PDT 24
Finished Jun 11 12:36:14 PM PDT 24
Peak memory 210980 kb
Host smart-19c25108-5cff-4840-992d-b9028fa55fe5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179913397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4179913397
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1353006037
Short name T423
Test name
Test status
Simulation time 256222926 ps
CPU time 7.52 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:02 PM PDT 24
Peak memory 211032 kb
Host smart-01c0f910-d60b-4d6a-885c-c738b4bd2e22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353006037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1353006037
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.859041281
Short name T388
Test name
Test status
Simulation time 91061191 ps
CPU time 6.31 seconds
Started Jun 11 12:35:41 PM PDT 24
Finished Jun 11 12:35:50 PM PDT 24
Peak memory 218980 kb
Host smart-93aae84f-508b-43de-b42f-dfce15d28b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859041281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.859041281
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3421524162
Short name T417
Test name
Test status
Simulation time 3799295768 ps
CPU time 40.19 seconds
Started Jun 11 12:35:41 PM PDT 24
Finished Jun 11 12:36:23 PM PDT 24
Peak memory 219204 kb
Host smart-6e4d1c1c-0332-4c95-b4f4-2115a69a5888
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421524162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3421524162
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.30870704
Short name T406
Test name
Test status
Simulation time 334305244 ps
CPU time 4.25 seconds
Started Jun 11 12:35:43 PM PDT 24
Finished Jun 11 12:35:49 PM PDT 24
Peak memory 210956 kb
Host smart-9b4b3182-9c0f-453a-a641-af10f7bfb363
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30870704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasi
ng.30870704
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1716249205
Short name T449
Test name
Test status
Simulation time 8246439571 ps
CPU time 15.99 seconds
Started Jun 11 12:35:42 PM PDT 24
Finished Jun 11 12:36:00 PM PDT 24
Peak memory 211076 kb
Host smart-52ae0907-09c6-47e0-86d2-c83d4d239808
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716249205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1716249205
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1285543816
Short name T86
Test name
Test status
Simulation time 587175106 ps
CPU time 7.94 seconds
Started Jun 11 12:35:40 PM PDT 24
Finished Jun 11 12:35:49 PM PDT 24
Peak memory 210912 kb
Host smart-07a3480a-cf16-4391-a0db-ffbc126e9b04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285543816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1285543816
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1191368520
Short name T382
Test name
Test status
Simulation time 6519928195 ps
CPU time 14.98 seconds
Started Jun 11 12:35:39 PM PDT 24
Finished Jun 11 12:35:56 PM PDT 24
Peak memory 219188 kb
Host smart-628e33f7-c15a-40fa-a5a9-a2c063cb8655
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191368520 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1191368520
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2896700117
Short name T83
Test name
Test status
Simulation time 9248465690 ps
CPU time 15.97 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:36:01 PM PDT 24
Peak memory 210984 kb
Host smart-9b10e1dc-baea-4af0-ae3b-03f781733367
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896700117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2896700117
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4182785926
Short name T412
Test name
Test status
Simulation time 16503251936 ps
CPU time 9.9 seconds
Started Jun 11 12:35:41 PM PDT 24
Finished Jun 11 12:35:53 PM PDT 24
Peak memory 210668 kb
Host smart-65eb4032-617d-4fd7-88f9-648d114f5b4e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182785926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4182785926
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.306828149
Short name T368
Test name
Test status
Simulation time 3123438630 ps
CPU time 12.36 seconds
Started Jun 11 12:35:40 PM PDT 24
Finished Jun 11 12:35:54 PM PDT 24
Peak memory 210708 kb
Host smart-e2e55a1f-f513-4c3b-993c-a3161acae495
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306828149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
306828149
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3713719397
Short name T393
Test name
Test status
Simulation time 27531812989 ps
CPU time 50.6 seconds
Started Jun 11 12:35:46 PM PDT 24
Finished Jun 11 12:36:38 PM PDT 24
Peak memory 211020 kb
Host smart-082b98df-d0bc-4261-9424-ec13be27cd8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713719397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3713719397
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2175193259
Short name T102
Test name
Test status
Simulation time 14379595994 ps
CPU time 15.49 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:36:01 PM PDT 24
Peak memory 211284 kb
Host smart-430a2640-612d-4754-9f03-8ec8620f7312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175193259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2175193259
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3362990624
Short name T437
Test name
Test status
Simulation time 8666923076 ps
CPU time 19.06 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:36:05 PM PDT 24
Peak memory 219016 kb
Host smart-23c75b7d-8988-4863-9418-cd4b0ea6304d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362990624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3362990624
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.578735803
Short name T53
Test name
Test status
Simulation time 1391398576 ps
CPU time 38.72 seconds
Started Jun 11 12:35:41 PM PDT 24
Finished Jun 11 12:36:22 PM PDT 24
Peak memory 219128 kb
Host smart-d051f140-996f-4228-b8b3-d0cc04d5239d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578735803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.578735803
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2991028213
Short name T80
Test name
Test status
Simulation time 1814167312 ps
CPU time 14.47 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:11 PM PDT 24
Peak memory 218828 kb
Host smart-6934503e-2c44-4606-85c2-34c558a80a92
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991028213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2991028213
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.150236759
Short name T405
Test name
Test status
Simulation time 261228985 ps
CPU time 4.27 seconds
Started Jun 11 12:35:43 PM PDT 24
Finished Jun 11 12:35:49 PM PDT 24
Peak memory 210960 kb
Host smart-d5b316cc-4aab-4e0d-b288-7dff1848b4e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150236759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.150236759
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3323567022
Short name T422
Test name
Test status
Simulation time 1411709733 ps
CPU time 5.69 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:00 PM PDT 24
Peak memory 218972 kb
Host smart-8537116d-1481-4f79-bbd8-7fb2047f8cd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323567022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3323567022
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2601503843
Short name T374
Test name
Test status
Simulation time 6150965365 ps
CPU time 12.07 seconds
Started Jun 11 12:35:41 PM PDT 24
Finished Jun 11 12:35:55 PM PDT 24
Peak memory 219204 kb
Host smart-ee1020c9-e5c7-418f-98f8-b4b70f2628cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601503843 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2601503843
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4263949029
Short name T404
Test name
Test status
Simulation time 2185972715 ps
CPU time 16.18 seconds
Started Jun 11 12:35:39 PM PDT 24
Finished Jun 11 12:35:57 PM PDT 24
Peak memory 211016 kb
Host smart-0f857018-b19a-41dc-abf7-b8e1d004d450
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263949029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4263949029
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2369049845
Short name T407
Test name
Test status
Simulation time 7190939798 ps
CPU time 12.71 seconds
Started Jun 11 12:35:45 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 210748 kb
Host smart-1afd77ed-1f1c-44c8-ac51-00ffdfc08cf8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369049845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2369049845
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3425416686
Short name T367
Test name
Test status
Simulation time 6114599124 ps
CPU time 11.98 seconds
Started Jun 11 12:35:39 PM PDT 24
Finished Jun 11 12:35:53 PM PDT 24
Peak memory 210752 kb
Host smart-5907b1c1-29b4-4aad-bf6d-da831cfe4ab9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425416686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3425416686
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2237797443
Short name T104
Test name
Test status
Simulation time 23056598307 ps
CPU time 89.39 seconds
Started Jun 11 12:35:42 PM PDT 24
Finished Jun 11 12:37:13 PM PDT 24
Peak memory 211968 kb
Host smart-f19a31bf-efde-4b0f-a132-aa0ebcfb102d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237797443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2237797443
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4267801252
Short name T98
Test name
Test status
Simulation time 521712623 ps
CPU time 7.79 seconds
Started Jun 11 12:35:40 PM PDT 24
Finished Jun 11 12:35:49 PM PDT 24
Peak memory 210980 kb
Host smart-60ff1e6e-6a31-41ec-9a12-54b06598dff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267801252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4267801252
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3932163555
Short name T378
Test name
Test status
Simulation time 1380237451 ps
CPU time 16.57 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:11 PM PDT 24
Peak memory 219028 kb
Host smart-8210ab36-2c22-4ac4-978f-7e156ecbcd5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932163555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3932163555
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2956173761
Short name T54
Test name
Test status
Simulation time 339635487 ps
CPU time 71.87 seconds
Started Jun 11 12:35:42 PM PDT 24
Finished Jun 11 12:36:56 PM PDT 24
Peak memory 219148 kb
Host smart-63cdd976-1613-452b-805e-72f6974058ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956173761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2956173761
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1040525233
Short name T380
Test name
Test status
Simulation time 2224863095 ps
CPU time 16.21 seconds
Started Jun 11 12:35:41 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 219232 kb
Host smart-6e87b649-707a-48cb-b50a-46f57e3c1733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040525233 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1040525233
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2252603400
Short name T458
Test name
Test status
Simulation time 4512267370 ps
CPU time 7.28 seconds
Started Jun 11 12:35:50 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 210972 kb
Host smart-9331c9c3-501e-436d-ae33-dda194c8b25f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252603400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2252603400
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1427077532
Short name T456
Test name
Test status
Simulation time 3343459321 ps
CPU time 36.93 seconds
Started Jun 11 12:35:43 PM PDT 24
Finished Jun 11 12:36:21 PM PDT 24
Peak memory 210972 kb
Host smart-4b004d1c-12d1-43c6-9829-730b4088125a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427077532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1427077532
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1614358638
Short name T430
Test name
Test status
Simulation time 1950235737 ps
CPU time 15.43 seconds
Started Jun 11 12:35:43 PM PDT 24
Finished Jun 11 12:36:00 PM PDT 24
Peak memory 218976 kb
Host smart-590191c0-c16f-41bc-8580-d79f269aa06e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614358638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1614358638
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2928082993
Short name T379
Test name
Test status
Simulation time 5727373642 ps
CPU time 18.56 seconds
Started Jun 11 12:35:42 PM PDT 24
Finished Jun 11 12:36:02 PM PDT 24
Peak memory 219108 kb
Host smart-99dca550-a398-466a-ba54-3ca7c5385ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928082993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2928082993
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.246150441
Short name T398
Test name
Test status
Simulation time 2072687545 ps
CPU time 6.92 seconds
Started Jun 11 12:35:43 PM PDT 24
Finished Jun 11 12:35:52 PM PDT 24
Peak memory 212384 kb
Host smart-6298ce7a-02dd-4765-b8af-62404351177d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246150441 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.246150441
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2560353590
Short name T84
Test name
Test status
Simulation time 378738241 ps
CPU time 4.22 seconds
Started Jun 11 12:35:45 PM PDT 24
Finished Jun 11 12:35:51 PM PDT 24
Peak memory 218072 kb
Host smart-95dd4c39-1238-4a2c-8bdd-b70adeb2479e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560353590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2560353590
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2781552521
Short name T103
Test name
Test status
Simulation time 616226876 ps
CPU time 7.9 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:02 PM PDT 24
Peak memory 210984 kb
Host smart-64728ada-5f7a-4b4e-9c1e-a55dde61fe78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781552521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2781552521
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4201201518
Short name T389
Test name
Test status
Simulation time 1533513312 ps
CPU time 10.24 seconds
Started Jun 11 12:35:45 PM PDT 24
Finished Jun 11 12:35:57 PM PDT 24
Peak memory 219028 kb
Host smart-3e5d58cb-79d9-487a-999e-d2e432f2670f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201201518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4201201518
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3036152811
Short name T111
Test name
Test status
Simulation time 4587045549 ps
CPU time 41.57 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:36 PM PDT 24
Peak memory 212736 kb
Host smart-09c7c38b-d33f-47d7-bfe6-73e532d3f76f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036152811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3036152811
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.424147496
Short name T375
Test name
Test status
Simulation time 1328788418 ps
CPU time 7.76 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:04 PM PDT 24
Peak memory 219096 kb
Host smart-0b53c60f-32d3-431a-a9cc-bcec8a318815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424147496 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.424147496
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3936185622
Short name T416
Test name
Test status
Simulation time 7038609918 ps
CPU time 14.32 seconds
Started Jun 11 12:35:48 PM PDT 24
Finished Jun 11 12:36:04 PM PDT 24
Peak memory 219172 kb
Host smart-d1b9fe3f-c8c7-4829-829c-f65ca1067432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936185622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3936185622
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3854459608
Short name T432
Test name
Test status
Simulation time 826297957 ps
CPU time 32.37 seconds
Started Jun 11 12:35:43 PM PDT 24
Finished Jun 11 12:36:17 PM PDT 24
Peak memory 210900 kb
Host smart-aeb08f0d-816d-431c-95da-f856176a6324
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854459608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3854459608
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2962233379
Short name T56
Test name
Test status
Simulation time 977431981 ps
CPU time 9.98 seconds
Started Jun 11 12:35:51 PM PDT 24
Finished Jun 11 12:36:02 PM PDT 24
Peak memory 210988 kb
Host smart-52e6f46a-3b0a-4b6f-a165-465e01d4b07f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962233379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2962233379
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2570918432
Short name T394
Test name
Test status
Simulation time 2126989012 ps
CPU time 13.56 seconds
Started Jun 11 12:35:50 PM PDT 24
Finished Jun 11 12:36:05 PM PDT 24
Peak memory 219032 kb
Host smart-3e33be86-3116-4627-a868-d4fb0a42cd00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570918432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2570918432
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1811047977
Short name T116
Test name
Test status
Simulation time 1737687944 ps
CPU time 45.09 seconds
Started Jun 11 12:35:41 PM PDT 24
Finished Jun 11 12:36:28 PM PDT 24
Peak memory 213416 kb
Host smart-bca8cdc0-790d-4448-b40b-786b8b9aca08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811047977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1811047977
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1492362725
Short name T414
Test name
Test status
Simulation time 1505335585 ps
CPU time 12.25 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:06 PM PDT 24
Peak memory 219060 kb
Host smart-9d56dfbc-6708-412d-86a5-f9421f819f20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492362725 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1492362725
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1558343273
Short name T409
Test name
Test status
Simulation time 85480931 ps
CPU time 4.19 seconds
Started Jun 11 12:35:43 PM PDT 24
Finished Jun 11 12:35:49 PM PDT 24
Peak memory 210928 kb
Host smart-477ebc59-eb07-4011-a708-2bdd82fa95a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558343273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1558343273
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1839411424
Short name T413
Test name
Test status
Simulation time 10453672760 ps
CPU time 86.8 seconds
Started Jun 11 12:35:48 PM PDT 24
Finished Jun 11 12:37:16 PM PDT 24
Peak memory 211048 kb
Host smart-8a40ad34-4ecc-4fc3-becc-56011bae3be0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839411424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1839411424
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1047674759
Short name T402
Test name
Test status
Simulation time 3858970352 ps
CPU time 16.49 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:13 PM PDT 24
Peak memory 211000 kb
Host smart-06402241-0a8b-44b8-ac7f-745ca6503023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047674759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1047674759
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3834896248
Short name T444
Test name
Test status
Simulation time 7521394214 ps
CPU time 19.14 seconds
Started Jun 11 12:35:52 PM PDT 24
Finished Jun 11 12:36:13 PM PDT 24
Peak memory 218972 kb
Host smart-de8dda0c-eabc-43e2-ab52-da58b4aadcbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834896248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3834896248
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2576346470
Short name T105
Test name
Test status
Simulation time 5261112008 ps
CPU time 73.25 seconds
Started Jun 11 12:35:43 PM PDT 24
Finished Jun 11 12:36:58 PM PDT 24
Peak memory 211712 kb
Host smart-c20acb0e-d8df-429f-9440-552407cd72ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576346470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2576346470
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1408569940
Short name T441
Test name
Test status
Simulation time 2866599966 ps
CPU time 13.73 seconds
Started Jun 11 12:35:45 PM PDT 24
Finished Jun 11 12:36:00 PM PDT 24
Peak memory 219188 kb
Host smart-22f5343e-6dc3-40f1-91e7-2a5ba068695c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408569940 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1408569940
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1200126442
Short name T55
Test name
Test status
Simulation time 3777027740 ps
CPU time 10.33 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:36:07 PM PDT 24
Peak memory 219128 kb
Host smart-c0482a39-8bf5-48f3-a8ba-4d45dd349ada
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200126442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1200126442
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1142024932
Short name T87
Test name
Test status
Simulation time 15841961987 ps
CPU time 75.05 seconds
Started Jun 11 12:35:51 PM PDT 24
Finished Jun 11 12:37:07 PM PDT 24
Peak memory 211008 kb
Host smart-53b3cbcb-85b0-4e79-bd4c-8bd918bf8a09
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142024932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1142024932
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.8050788
Short name T455
Test name
Test status
Simulation time 6015858569 ps
CPU time 13 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:35:59 PM PDT 24
Peak memory 219176 kb
Host smart-1105785a-6b7d-40bd-9426-397c6c6bd807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8050788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl
_same_csr_outstanding.8050788
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3414933290
Short name T418
Test name
Test status
Simulation time 1866692885 ps
CPU time 18.08 seconds
Started Jun 11 12:35:44 PM PDT 24
Finished Jun 11 12:36:04 PM PDT 24
Peak memory 218936 kb
Host smart-88c303b6-bb6d-49dc-a9fe-4d3303c8a2d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414933290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3414933290
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3825987163
Short name T112
Test name
Test status
Simulation time 1303028084 ps
CPU time 72.24 seconds
Started Jun 11 12:35:55 PM PDT 24
Finished Jun 11 12:37:09 PM PDT 24
Peak memory 219092 kb
Host smart-8a6cd92a-3989-4dc3-aefa-73b9021faeb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825987163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3825987163
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.487849080
Short name T138
Test name
Test status
Simulation time 6043125548 ps
CPU time 11.72 seconds
Started Jun 11 12:36:04 PM PDT 24
Finished Jun 11 12:36:17 PM PDT 24
Peak memory 210920 kb
Host smart-cf49c757-d0ce-43fc-a460-fb4d27508cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487849080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.487849080
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3260547509
Short name T206
Test name
Test status
Simulation time 1098602358 ps
CPU time 55.72 seconds
Started Jun 11 12:36:02 PM PDT 24
Finished Jun 11 12:36:58 PM PDT 24
Peak memory 226548 kb
Host smart-e838b1f4-4ff4-4359-8fd5-9fb326013a9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260547509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3260547509
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2215937432
Short name T257
Test name
Test status
Simulation time 11212458843 ps
CPU time 26.44 seconds
Started Jun 11 12:36:03 PM PDT 24
Finished Jun 11 12:36:31 PM PDT 24
Peak memory 211780 kb
Host smart-bf48e469-d052-4c27-a39a-ef5c4796e0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215937432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2215937432
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1504349437
Short name T17
Test name
Test status
Simulation time 947414490 ps
CPU time 50.59 seconds
Started Jun 11 12:36:08 PM PDT 24
Finished Jun 11 12:36:59 PM PDT 24
Peak memory 235116 kb
Host smart-f7c62627-b120-453a-9924-3e2b216a42ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504349437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1504349437
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3725244969
Short name T75
Test name
Test status
Simulation time 10310239574 ps
CPU time 27.65 seconds
Started Jun 11 12:36:04 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 213472 kb
Host smart-658abb3e-fd38-4786-bd5b-228e69fe22d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725244969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3725244969
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1309161837
Short name T240
Test name
Test status
Simulation time 502481959 ps
CPU time 7.19 seconds
Started Jun 11 12:36:07 PM PDT 24
Finished Jun 11 12:36:16 PM PDT 24
Peak memory 210884 kb
Host smart-4bdf0bdc-544c-4395-9e0c-237828649541
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309161837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1309161837
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3372944218
Short name T222
Test name
Test status
Simulation time 250646776 ps
CPU time 5.71 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:12 PM PDT 24
Peak memory 210728 kb
Host smart-c094767f-8252-4009-a7ca-11f6d5672c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372944218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3372944218
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1415912130
Short name T166
Test name
Test status
Simulation time 38256382257 ps
CPU time 366.83 seconds
Started Jun 11 12:36:03 PM PDT 24
Finished Jun 11 12:42:10 PM PDT 24
Peak memory 233808 kb
Host smart-eee6ce20-ebc4-44d9-8c51-4b0e0115522d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415912130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1415912130
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3851647510
Short name T249
Test name
Test status
Simulation time 7973072053 ps
CPU time 25.29 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:31 PM PDT 24
Peak memory 212756 kb
Host smart-76ed4d3f-191a-4980-bb48-2364904c780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851647510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3851647510
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4023882283
Short name T196
Test name
Test status
Simulation time 97636138 ps
CPU time 5.47 seconds
Started Jun 11 12:36:09 PM PDT 24
Finished Jun 11 12:36:15 PM PDT 24
Peak memory 210960 kb
Host smart-d51d5bbc-6b16-458a-ab94-1355dbee34d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023882283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4023882283
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1621103647
Short name T15
Test name
Test status
Simulation time 1616147310 ps
CPU time 99.18 seconds
Started Jun 11 12:36:08 PM PDT 24
Finished Jun 11 12:37:48 PM PDT 24
Peak memory 236312 kb
Host smart-00fb8be2-8f79-48ac-8d0e-5b7be87caadb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621103647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1621103647
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2338893698
Short name T158
Test name
Test status
Simulation time 5263641725 ps
CPU time 25.99 seconds
Started Jun 11 12:36:06 PM PDT 24
Finished Jun 11 12:36:34 PM PDT 24
Peak memory 213620 kb
Host smart-45e844eb-1b78-44d4-afc0-d4a61f502543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338893698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2338893698
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1785052349
Short name T7
Test name
Test status
Simulation time 10176340585 ps
CPU time 45.04 seconds
Started Jun 11 12:36:07 PM PDT 24
Finished Jun 11 12:36:53 PM PDT 24
Peak memory 216608 kb
Host smart-16815941-7526-458e-b5a1-68ff7ea185f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785052349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1785052349
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.408912173
Short name T262
Test name
Test status
Simulation time 6868022890 ps
CPU time 14.36 seconds
Started Jun 11 12:36:16 PM PDT 24
Finished Jun 11 12:36:31 PM PDT 24
Peak memory 210924 kb
Host smart-ff936730-b9ae-4662-8538-8996787525bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408912173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.408912173
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1510767851
Short name T169
Test name
Test status
Simulation time 14104307366 ps
CPU time 164.44 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:39:04 PM PDT 24
Peak memory 238916 kb
Host smart-55ae622f-bc83-43d2-b0fe-1f20f1e97a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510767851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1510767851
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.399902791
Short name T175
Test name
Test status
Simulation time 40402654972 ps
CPU time 31.77 seconds
Started Jun 11 12:36:17 PM PDT 24
Finished Jun 11 12:36:50 PM PDT 24
Peak memory 210968 kb
Host smart-7aaf6a5b-e0a7-4b5d-8c6c-80377f3304b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399902791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.399902791
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2802033694
Short name T155
Test name
Test status
Simulation time 183007457 ps
CPU time 5.36 seconds
Started Jun 11 12:36:16 PM PDT 24
Finished Jun 11 12:36:22 PM PDT 24
Peak memory 210844 kb
Host smart-7afec9f4-2fd8-410a-b07e-21c35a8ceee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802033694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2802033694
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3643297460
Short name T157
Test name
Test status
Simulation time 183524344 ps
CPU time 10.36 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:32 PM PDT 24
Peak memory 212736 kb
Host smart-c04c3356-80f5-4426-b912-843acbb3e9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643297460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3643297460
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3273327444
Short name T211
Test name
Test status
Simulation time 15034245637 ps
CPU time 40.88 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:37:01 PM PDT 24
Peak memory 216604 kb
Host smart-2e6ebfd5-bf61-4782-b610-4c4c80c9010d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273327444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3273327444
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1188907491
Short name T314
Test name
Test status
Simulation time 1912551025 ps
CPU time 15.41 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:36:39 PM PDT 24
Peak memory 210740 kb
Host smart-51efe64d-181d-4f2b-90a1-06d196d3a55f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188907491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1188907491
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4208943761
Short name T119
Test name
Test status
Simulation time 41476964843 ps
CPU time 346.73 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 212192 kb
Host smart-0fb26fbf-07a4-4271-aab6-8fa55d7be713
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208943761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4208943761
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2861765754
Short name T215
Test name
Test status
Simulation time 9775594755 ps
CPU time 29.13 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:50 PM PDT 24
Peak memory 211740 kb
Host smart-8ab69654-8355-45b0-9d56-0608c49b6395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861765754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2861765754
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.74725518
Short name T177
Test name
Test status
Simulation time 507345864 ps
CPU time 8.7 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:30 PM PDT 24
Peak memory 210944 kb
Host smart-27c3cfe4-44b5-490e-a313-1440ce12171b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74725518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.74725518
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.809636626
Short name T90
Test name
Test status
Simulation time 1633337835 ps
CPU time 10.07 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:31 PM PDT 24
Peak memory 212996 kb
Host smart-14f6d019-7385-45ed-a3c8-2ba8b20d334a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809636626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.809636626
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.77694355
Short name T309
Test name
Test status
Simulation time 207552957 ps
CPU time 6.79 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:28 PM PDT 24
Peak memory 210876 kb
Host smart-a327cd8a-9110-4a58-a631-593dfd2c3792
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77694355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.rom_ctrl_stress_all.77694355
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1122322265
Short name T142
Test name
Test status
Simulation time 1235870187 ps
CPU time 8.32 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:30 PM PDT 24
Peak memory 210728 kb
Host smart-3efbc1c9-a2c1-448d-855a-2504c74bf620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122322265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1122322265
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3642580358
Short name T185
Test name
Test status
Simulation time 972626078 ps
CPU time 69.61 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:37:33 PM PDT 24
Peak memory 227516 kb
Host smart-dcd3ff02-123a-4a1d-b62c-c8bbf244de43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642580358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3642580358
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2223698755
Short name T4
Test name
Test status
Simulation time 840433727 ps
CPU time 14.96 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:36:38 PM PDT 24
Peak memory 210812 kb
Host smart-4f394a07-30ef-4b99-99d2-780c7e65dc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223698755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2223698755
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3063010335
Short name T234
Test name
Test status
Simulation time 2588361933 ps
CPU time 13.29 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:32 PM PDT 24
Peak memory 210996 kb
Host smart-89333ff6-7d5f-45a8-9d5c-a770650cf83e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063010335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3063010335
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1296185970
Short name T360
Test name
Test status
Simulation time 12002447878 ps
CPU time 30.31 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:50 PM PDT 24
Peak memory 214188 kb
Host smart-6187b3b3-a9d7-4191-9524-d218b98be2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296185970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1296185970
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2696167422
Short name T271
Test name
Test status
Simulation time 4397791638 ps
CPU time 28.64 seconds
Started Jun 11 12:36:16 PM PDT 24
Finished Jun 11 12:36:45 PM PDT 24
Peak memory 213864 kb
Host smart-655c6bdc-5a10-41c3-b762-37039e30715b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696167422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2696167422
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2407792161
Short name T269
Test name
Test status
Simulation time 1206084931 ps
CPU time 6.61 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:26 PM PDT 24
Peak memory 210768 kb
Host smart-0e1b223f-c1a1-4f8a-a789-765954ae5a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407792161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2407792161
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2892719587
Short name T319
Test name
Test status
Simulation time 81646641820 ps
CPU time 384.65 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:42:46 PM PDT 24
Peak memory 234464 kb
Host smart-84f1d2d3-f005-4e3b-82f8-023611eca348
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892719587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2892719587
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3827555734
Short name T330
Test name
Test status
Simulation time 880113369 ps
CPU time 8.28 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:29 PM PDT 24
Peak memory 210964 kb
Host smart-4ee2fb04-7137-454b-9361-8df04cb7002d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827555734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3827555734
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.331019844
Short name T361
Test name
Test status
Simulation time 1186303647 ps
CPU time 11.55 seconds
Started Jun 11 12:36:17 PM PDT 24
Finished Jun 11 12:36:29 PM PDT 24
Peak memory 213080 kb
Host smart-219ad3fe-be94-4e2f-ba0a-a64a89728096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331019844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.331019844
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2623745752
Short name T335
Test name
Test status
Simulation time 4046710702 ps
CPU time 11.18 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 212044 kb
Host smart-9c398f7f-c397-430f-9bfe-672a31945508
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623745752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2623745752
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.446690042
Short name T58
Test name
Test status
Simulation time 2341087569 ps
CPU time 11.71 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:36:35 PM PDT 24
Peak memory 210792 kb
Host smart-1d7f2797-8fbb-4630-bcca-e7926681bde3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446690042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.446690042
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2946439007
Short name T266
Test name
Test status
Simulation time 178361418570 ps
CPU time 272.09 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:40:54 PM PDT 24
Peak memory 228224 kb
Host smart-c80cb9a6-06c4-4c12-856f-d58828885628
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946439007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2946439007
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3683811084
Short name T230
Test name
Test status
Simulation time 3878076732 ps
CPU time 13.75 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:32 PM PDT 24
Peak memory 211856 kb
Host smart-a4a2154d-44df-4317-8d2b-be205af97a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683811084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3683811084
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1171278775
Short name T219
Test name
Test status
Simulation time 2616813078 ps
CPU time 13.19 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:34 PM PDT 24
Peak memory 210992 kb
Host smart-5afa9442-4cc9-453e-abb9-3188c63e6ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171278775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1171278775
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.605012899
Short name T161
Test name
Test status
Simulation time 686794345 ps
CPU time 14.38 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:34 PM PDT 24
Peak memory 213416 kb
Host smart-0c479d73-a06b-4e2b-b6b3-33e8e1820f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605012899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.605012899
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2750622844
Short name T135
Test name
Test status
Simulation time 405459482 ps
CPU time 10 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:31 PM PDT 24
Peak memory 210736 kb
Host smart-4d028b37-ca62-4f99-a9d9-f4f7cd642c08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750622844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2750622844
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.909248971
Short name T244
Test name
Test status
Simulation time 4277489278 ps
CPU time 10.51 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 210776 kb
Host smart-a9cbe257-041b-495e-9183-667e2b15e3ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909248971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.909248971
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1491820
Short name T126
Test name
Test status
Simulation time 2918808301 ps
CPU time 88.11 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:37:48 PM PDT 24
Peak memory 232392 kb
Host smart-dac59cdd-cb80-42b7-acad-b34d5173e1a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_cor
rupt_sig_fatal_chk.1491820
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.11298627
Short name T125
Test name
Test status
Simulation time 8392524235 ps
CPU time 32.87 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:54 PM PDT 24
Peak memory 212116 kb
Host smart-79ebf710-9bce-4e44-a3c8-4b28b8bb5828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11298627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.11298627
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.118810755
Short name T341
Test name
Test status
Simulation time 2029089244 ps
CPU time 16.18 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:38 PM PDT 24
Peak memory 210872 kb
Host smart-50b3ec6c-d7b3-4f98-a897-b3a8c29ea13e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118810755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.118810755
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1061836484
Short name T159
Test name
Test status
Simulation time 22134384705 ps
CPU time 39.78 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:37:01 PM PDT 24
Peak memory 213680 kb
Host smart-ebdf190e-3c2e-4d19-aeba-38b064da3761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061836484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1061836484
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2609467521
Short name T94
Test name
Test status
Simulation time 11613367988 ps
CPU time 53.2 seconds
Started Jun 11 12:36:22 PM PDT 24
Finished Jun 11 12:37:18 PM PDT 24
Peak memory 214760 kb
Host smart-8bb8fbc3-14f9-4fb2-ab43-4cc7124cf311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609467521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2609467521
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2503372710
Short name T316
Test name
Test status
Simulation time 88335912 ps
CPU time 4.37 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:26 PM PDT 24
Peak memory 210764 kb
Host smart-7701f4ac-9f8c-41be-bfd9-f076853d0317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503372710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2503372710
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2248081230
Short name T227
Test name
Test status
Simulation time 100292342485 ps
CPU time 381.55 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:42:45 PM PDT 24
Peak memory 214256 kb
Host smart-1d072f65-7589-462b-957c-1f9e8989fe4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248081230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2248081230
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2148240025
Short name T153
Test name
Test status
Simulation time 16402471538 ps
CPU time 33.62 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:36:57 PM PDT 24
Peak memory 214304 kb
Host smart-a47a8d56-631e-4292-b712-3011c5783ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148240025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2148240025
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3102288384
Short name T49
Test name
Test status
Simulation time 2120200889 ps
CPU time 17.5 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:39 PM PDT 24
Peak memory 210932 kb
Host smart-ea91a72c-e4c8-455f-a599-fdce0dd447b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102288384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3102288384
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.369319379
Short name T366
Test name
Test status
Simulation time 783142812 ps
CPU time 10.1 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 213364 kb
Host smart-2ed04a9b-50a4-4b09-ba11-e337dd224473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369319379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.369319379
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3644025350
Short name T129
Test name
Test status
Simulation time 7722130634 ps
CPU time 65.99 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:37:29 PM PDT 24
Peak memory 216120 kb
Host smart-789a7dd9-bcd5-4d5e-9c78-c0500ad48f1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644025350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3644025350
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1534351691
Short name T22
Test name
Test status
Simulation time 192488920425 ps
CPU time 1794.84 seconds
Started Jun 11 12:36:23 PM PDT 24
Finished Jun 11 01:06:20 PM PDT 24
Peak memory 236396 kb
Host smart-13cab319-aa66-4169-a272-fd905dbacfba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534351691 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1534351691
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3546222188
Short name T91
Test name
Test status
Simulation time 2054041697 ps
CPU time 16.25 seconds
Started Jun 11 12:36:22 PM PDT 24
Finished Jun 11 12:36:41 PM PDT 24
Peak memory 210796 kb
Host smart-b30a52fe-e2f0-44ec-8fe9-cf3ce6a233cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546222188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3546222188
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3292298825
Short name T210
Test name
Test status
Simulation time 5061507948 ps
CPU time 140.24 seconds
Started Jun 11 12:36:23 PM PDT 24
Finished Jun 11 12:38:45 PM PDT 24
Peak memory 237540 kb
Host smart-fe59bc38-7149-4953-ba29-a2ac0b995e38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292298825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3292298825
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1322771438
Short name T264
Test name
Test status
Simulation time 4111168639 ps
CPU time 16.09 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:37 PM PDT 24
Peak memory 212116 kb
Host smart-f0cf4b51-e8dd-4981-9936-8c1040860d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322771438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1322771438
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3042191354
Short name T97
Test name
Test status
Simulation time 1668719471 ps
CPU time 8.11 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:36:31 PM PDT 24
Peak memory 210880 kb
Host smart-860ce2e4-d268-48b3-947c-ed6edac048b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042191354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3042191354
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3431634867
Short name T72
Test name
Test status
Simulation time 3617433883 ps
CPU time 22.55 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:42 PM PDT 24
Peak memory 213112 kb
Host smart-fe065edd-af8d-4c9f-a513-42877b347469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431634867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3431634867
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4243935327
Short name T200
Test name
Test status
Simulation time 2903020403 ps
CPU time 37.8 seconds
Started Jun 11 12:36:23 PM PDT 24
Finished Jun 11 12:37:03 PM PDT 24
Peak memory 219056 kb
Host smart-eac59b9d-302e-4b9d-b9d4-8b3fb3149a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243935327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4243935327
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.332310832
Short name T212
Test name
Test status
Simulation time 561590355 ps
CPU time 5.98 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:36:40 PM PDT 24
Peak memory 210796 kb
Host smart-60f192b8-3c5d-48b9-988d-2bac8e86b3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332310832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.332310832
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1203134796
Short name T231
Test name
Test status
Simulation time 94371995372 ps
CPU time 299.8 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:41:20 PM PDT 24
Peak memory 237144 kb
Host smart-12ef09c6-bd36-4079-8c56-7881121e15bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203134796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1203134796
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1459971143
Short name T327
Test name
Test status
Simulation time 404107651 ps
CPU time 5.58 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:36:29 PM PDT 24
Peak memory 210936 kb
Host smart-ad1ea4d6-1921-44ad-a67d-702fed170527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459971143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1459971143
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4115155644
Short name T179
Test name
Test status
Simulation time 363184405 ps
CPU time 10.02 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:32 PM PDT 24
Peak memory 213220 kb
Host smart-d5634006-019f-43d0-a655-e42079678da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115155644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4115155644
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3189383660
Short name T243
Test name
Test status
Simulation time 2363204038 ps
CPU time 20.18 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:36:44 PM PDT 24
Peak memory 214228 kb
Host smart-fcb43a66-e6e6-4168-95a7-dfd643faf6d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189383660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3189383660
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2348151397
Short name T203
Test name
Test status
Simulation time 779759765 ps
CPU time 7.22 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:36:40 PM PDT 24
Peak memory 210796 kb
Host smart-70d92de4-288e-4050-bb54-6dad2999203b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348151397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2348151397
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3687715207
Short name T197
Test name
Test status
Simulation time 88746327824 ps
CPU time 464.47 seconds
Started Jun 11 12:36:28 PM PDT 24
Finished Jun 11 12:44:13 PM PDT 24
Peak memory 225356 kb
Host smart-30a78e61-3baa-437f-bba5-3f97c5b5c583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687715207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3687715207
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3650177566
Short name T363
Test name
Test status
Simulation time 39271974903 ps
CPU time 34.15 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:37:14 PM PDT 24
Peak memory 211736 kb
Host smart-b225e1b2-6844-48ad-8b04-2ef6f299ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650177566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3650177566
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3197922637
Short name T346
Test name
Test status
Simulation time 718456415 ps
CPU time 9.63 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:36:44 PM PDT 24
Peak memory 210960 kb
Host smart-9a726f76-384d-4757-9b3f-992506b0f6b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197922637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3197922637
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2531987255
Short name T322
Test name
Test status
Simulation time 11530274714 ps
CPU time 29.65 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:37:00 PM PDT 24
Peak memory 213948 kb
Host smart-9337de20-d7a9-4ad4-a899-0e128da408bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531987255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2531987255
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3412931957
Short name T305
Test name
Test status
Simulation time 33735048004 ps
CPU time 68.32 seconds
Started Jun 11 12:36:28 PM PDT 24
Finished Jun 11 12:37:37 PM PDT 24
Peak memory 216956 kb
Host smart-6579469f-6b3d-4ab5-bf0f-2eb845c82785
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412931957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3412931957
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.587422168
Short name T147
Test name
Test status
Simulation time 88296104 ps
CPU time 4.35 seconds
Started Jun 11 12:36:02 PM PDT 24
Finished Jun 11 12:36:07 PM PDT 24
Peak memory 210776 kb
Host smart-90c9ffda-9b65-4ac1-9fa2-2eed7c397047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587422168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.587422168
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1882276005
Short name T184
Test name
Test status
Simulation time 80324459846 ps
CPU time 393.56 seconds
Started Jun 11 12:36:01 PM PDT 24
Finished Jun 11 12:42:35 PM PDT 24
Peak memory 238448 kb
Host smart-20e1c3c9-2e99-4012-ad35-7b89823f4366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882276005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1882276005
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.150258640
Short name T254
Test name
Test status
Simulation time 5876280387 ps
CPU time 32.33 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:38 PM PDT 24
Peak memory 212000 kb
Host smart-32944950-5d79-4a2c-a9f1-5699e99712c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150258640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.150258640
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2341563947
Short name T208
Test name
Test status
Simulation time 6019266784 ps
CPU time 8.8 seconds
Started Jun 11 12:36:04 PM PDT 24
Finished Jun 11 12:36:15 PM PDT 24
Peak memory 211040 kb
Host smart-0fd4db11-6b0a-4bfa-a96e-dad64f435b47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341563947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2341563947
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3665188209
Short name T26
Test name
Test status
Simulation time 1188096896 ps
CPU time 99.3 seconds
Started Jun 11 12:36:06 PM PDT 24
Finished Jun 11 12:37:47 PM PDT 24
Peak memory 236304 kb
Host smart-e421957d-236a-4609-9bce-fdc5eccbb2c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665188209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3665188209
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2108934266
Short name T204
Test name
Test status
Simulation time 4007883991 ps
CPU time 37.82 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:45 PM PDT 24
Peak memory 212864 kb
Host smart-fdcd42c6-4336-4f7b-a1e0-19cba84cccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108934266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2108934266
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1873658407
Short name T324
Test name
Test status
Simulation time 87578734092 ps
CPU time 69.83 seconds
Started Jun 11 12:36:03 PM PDT 24
Finished Jun 11 12:37:14 PM PDT 24
Peak memory 216040 kb
Host smart-3cb21651-0f00-4307-ae46-328659ed829c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873658407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1873658407
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1657193564
Short name T191
Test name
Test status
Simulation time 1035746699 ps
CPU time 4.2 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:36:45 PM PDT 24
Peak memory 210712 kb
Host smart-0e442bb3-8092-4d5b-bff1-7748d1f995c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657193564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1657193564
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2432034872
Short name T132
Test name
Test status
Simulation time 35400629893 ps
CPU time 345.32 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:42:18 PM PDT 24
Peak memory 212248 kb
Host smart-045f9187-c27f-4fe3-b293-017a534d022c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432034872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2432034872
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.712845627
Short name T24
Test name
Test status
Simulation time 15018797840 ps
CPU time 33.1 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 12:37:05 PM PDT 24
Peak memory 212260 kb
Host smart-82446548-d51c-4744-89e1-f7fb42b69c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712845627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.712845627
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.967033342
Short name T50
Test name
Test status
Simulation time 2729701691 ps
CPU time 9.7 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 12:36:41 PM PDT 24
Peak memory 211280 kb
Host smart-03718446-eecb-437f-80bf-da7b30d08307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967033342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.967033342
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1999305157
Short name T209
Test name
Test status
Simulation time 2720953655 ps
CPU time 26.49 seconds
Started Jun 11 12:36:28 PM PDT 24
Finished Jun 11 12:36:55 PM PDT 24
Peak memory 212688 kb
Host smart-a2a5e8d0-9111-4f6b-8229-959a09a5f897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999305157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1999305157
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3572242833
Short name T133
Test name
Test status
Simulation time 1235221496 ps
CPU time 11.21 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:36:44 PM PDT 24
Peak memory 210796 kb
Host smart-d98e3d3e-4414-4456-8c5b-37b4f7aabb33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572242833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3572242833
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4238426041
Short name T276
Test name
Test status
Simulation time 4139237253 ps
CPU time 31.4 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:37:05 PM PDT 24
Peak memory 212620 kb
Host smart-823872ff-1e4f-43df-9df2-d13b8092b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238426041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4238426041
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3536103821
Short name T258
Test name
Test status
Simulation time 1361764722 ps
CPU time 7.57 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:36:37 PM PDT 24
Peak memory 211192 kb
Host smart-ea441936-e7a3-412b-b4e4-12e447e95b1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536103821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3536103821
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.922894545
Short name T195
Test name
Test status
Simulation time 2072460799 ps
CPU time 24.92 seconds
Started Jun 11 12:36:27 PM PDT 24
Finished Jun 11 12:36:52 PM PDT 24
Peak memory 213124 kb
Host smart-59709925-f4c3-49a5-b20c-118659cd7a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922894545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.922894545
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2891541931
Short name T128
Test name
Test status
Simulation time 4286066041 ps
CPU time 9.09 seconds
Started Jun 11 12:36:33 PM PDT 24
Finished Jun 11 12:36:43 PM PDT 24
Peak memory 211180 kb
Host smart-db475e21-2b46-4c64-9146-2fe018061ba8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891541931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2891541931
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1765931173
Short name T41
Test name
Test status
Simulation time 45632533817 ps
CPU time 1786.62 seconds
Started Jun 11 12:36:38 PM PDT 24
Finished Jun 11 01:06:26 PM PDT 24
Peak memory 235424 kb
Host smart-5ecad92c-3cf5-4ee7-9fab-ec6077598869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765931173 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1765931173
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1675339317
Short name T359
Test name
Test status
Simulation time 1108012610 ps
CPU time 10.45 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:36:43 PM PDT 24
Peak memory 210772 kb
Host smart-1281b660-177b-4341-a481-2634229683e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675339317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1675339317
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1218062578
Short name T365
Test name
Test status
Simulation time 1742974024 ps
CPU time 88.54 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:38:02 PM PDT 24
Peak memory 212124 kb
Host smart-285fda4f-766b-4542-8369-4244b9f050b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218062578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1218062578
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3678476396
Short name T328
Test name
Test status
Simulation time 23822961420 ps
CPU time 27.42 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:37:01 PM PDT 24
Peak memory 211900 kb
Host smart-8f19f56c-570e-405c-ab27-e70b933a74ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678476396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3678476396
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2102562918
Short name T30
Test name
Test status
Simulation time 3042402367 ps
CPU time 13.11 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:36:46 PM PDT 24
Peak memory 211064 kb
Host smart-61bb8ed8-4365-44c3-9ed1-cdcefd50089b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102562918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2102562918
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2540916962
Short name T77
Test name
Test status
Simulation time 376931467 ps
CPU time 9.97 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:36:51 PM PDT 24
Peak memory 212880 kb
Host smart-5e88b480-7041-4cad-bea3-71013a9d200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540916962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2540916962
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3510360665
Short name T356
Test name
Test status
Simulation time 4441677237 ps
CPU time 47.23 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:37:21 PM PDT 24
Peak memory 218916 kb
Host smart-318bfd8f-562b-4461-a1e5-340bdc3416d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510360665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3510360665
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2041983769
Short name T173
Test name
Test status
Simulation time 500618155 ps
CPU time 7.55 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 12:36:39 PM PDT 24
Peak memory 210796 kb
Host smart-112779d7-04d9-4b51-ad75-ba6c278bb573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041983769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2041983769
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3042697133
Short name T289
Test name
Test status
Simulation time 8594716871 ps
CPU time 141.04 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 12:38:53 PM PDT 24
Peak memory 238428 kb
Host smart-cfc0687b-1ed5-423c-af06-6d6f4ae274ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042697133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3042697133
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.407194255
Short name T148
Test name
Test status
Simulation time 9906919668 ps
CPU time 23.93 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:36:57 PM PDT 24
Peak memory 211880 kb
Host smart-b5b21bcf-26c0-4f15-be1d-2517ab3e568c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407194255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.407194255
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3509014027
Short name T348
Test name
Test status
Simulation time 600502118 ps
CPU time 5.28 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:36:39 PM PDT 24
Peak memory 210912 kb
Host smart-a5d7e569-10f6-4d7d-a7c2-1cb4f618a09d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509014027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3509014027
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2750541055
Short name T275
Test name
Test status
Simulation time 11353186511 ps
CPU time 25.88 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:36:56 PM PDT 24
Peak memory 213340 kb
Host smart-f756395d-7899-40aa-bbdb-60bdc8723eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750541055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2750541055
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2192257590
Short name T272
Test name
Test status
Simulation time 1454785703 ps
CPU time 32.47 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:37:06 PM PDT 24
Peak memory 215960 kb
Host smart-64aa7c42-8d9e-42ff-9ea6-0c66179a28b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192257590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2192257590
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3700967790
Short name T267
Test name
Test status
Simulation time 479563553 ps
CPU time 4.99 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:36:39 PM PDT 24
Peak memory 210796 kb
Host smart-174860b7-7500-4554-a972-621257a2dfd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700967790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3700967790
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.857828261
Short name T248
Test name
Test status
Simulation time 15004012881 ps
CPU time 93.92 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:38:14 PM PDT 24
Peak memory 232344 kb
Host smart-74caee84-c299-417e-a12c-29e7a1e71b4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857828261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.857828261
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.600597970
Short name T353
Test name
Test status
Simulation time 397523209 ps
CPU time 9.5 seconds
Started Jun 11 12:36:28 PM PDT 24
Finished Jun 11 12:36:38 PM PDT 24
Peak memory 211644 kb
Host smart-c20a7e66-8281-4d87-b3ba-9dac0fe816ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600597970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.600597970
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2385445462
Short name T306
Test name
Test status
Simulation time 196360079 ps
CPU time 5.72 seconds
Started Jun 11 12:36:27 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 210852 kb
Host smart-e9d022bb-84b3-4824-bac6-4547ce66031c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385445462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2385445462
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1363289398
Short name T214
Test name
Test status
Simulation time 2031175807 ps
CPU time 16.45 seconds
Started Jun 11 12:36:38 PM PDT 24
Finished Jun 11 12:36:56 PM PDT 24
Peak memory 212992 kb
Host smart-642a27bb-d26e-4520-a477-dfbc79ff6389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363289398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1363289398
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2413519123
Short name T205
Test name
Test status
Simulation time 1475752539 ps
CPU time 24.53 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:36:57 PM PDT 24
Peak memory 214148 kb
Host smart-fb1e886b-2526-441a-8146-6d724ff3c37e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413519123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2413519123
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3836892236
Short name T143
Test name
Test status
Simulation time 3731172532 ps
CPU time 9.35 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:36:43 PM PDT 24
Peak memory 210860 kb
Host smart-ae3df9e8-d7ac-43d3-9646-80ef6ec04a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836892236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3836892236
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2690439793
Short name T342
Test name
Test status
Simulation time 13015671995 ps
CPU time 95.33 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:38:16 PM PDT 24
Peak memory 237436 kb
Host smart-bf02c80b-f04d-42e4-8d3a-f75ba590b0ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690439793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2690439793
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4183235632
Short name T229
Test name
Test status
Simulation time 650832844 ps
CPU time 9.34 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:36:50 PM PDT 24
Peak memory 210860 kb
Host smart-0bdce3aa-dc85-4d04-8a16-bfa616c4ae01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183235632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4183235632
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.236598547
Short name T11
Test name
Test status
Simulation time 19501333184 ps
CPU time 22.87 seconds
Started Jun 11 12:36:38 PM PDT 24
Finished Jun 11 12:37:03 PM PDT 24
Peak memory 214048 kb
Host smart-c8fe6421-0ce8-49d1-8369-9905dc238caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236598547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.236598547
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.835902651
Short name T216
Test name
Test status
Simulation time 3143476441 ps
CPU time 31.18 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:37:05 PM PDT 24
Peak memory 212560 kb
Host smart-05593210-5f77-461e-935d-8d9624f2122a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835902651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.835902651
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2870002272
Short name T331
Test name
Test status
Simulation time 88820820 ps
CPU time 4.19 seconds
Started Jun 11 12:36:40 PM PDT 24
Finished Jun 11 12:36:45 PM PDT 24
Peak memory 210620 kb
Host smart-d17573ef-03f9-4d71-8841-f8cfce140699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870002272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2870002272
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4199582142
Short name T14
Test name
Test status
Simulation time 6908031976 ps
CPU time 138.69 seconds
Started Jun 11 12:36:27 PM PDT 24
Finished Jun 11 12:38:47 PM PDT 24
Peak memory 240504 kb
Host smart-3ee9e41a-2d7b-483f-9482-2954ce359385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199582142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4199582142
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3339037155
Short name T176
Test name
Test status
Simulation time 25167880726 ps
CPU time 27.91 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:37:08 PM PDT 24
Peak memory 211732 kb
Host smart-a23f6360-2992-45e8-a185-354a97241e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339037155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3339037155
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.636178178
Short name T3
Test name
Test status
Simulation time 382291427 ps
CPU time 5.64 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 12:36:38 PM PDT 24
Peak memory 210912 kb
Host smart-71f5f7b8-da65-407d-91ed-bc613d36b1e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636178178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.636178178
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.376318441
Short name T246
Test name
Test status
Simulation time 43641177363 ps
CPU time 32.93 seconds
Started Jun 11 12:36:40 PM PDT 24
Finished Jun 11 12:37:14 PM PDT 24
Peak memory 213800 kb
Host smart-90cd4584-87bb-43e0-b615-0e0dfc3e9f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376318441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.376318441
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2142019039
Short name T354
Test name
Test status
Simulation time 4194080440 ps
CPU time 36.62 seconds
Started Jun 11 12:36:28 PM PDT 24
Finished Jun 11 12:37:06 PM PDT 24
Peak memory 214140 kb
Host smart-a984f999-7a7c-4759-8ffd-42aa44174074
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142019039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2142019039
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2535945727
Short name T287
Test name
Test status
Simulation time 1989221905 ps
CPU time 7.45 seconds
Started Jun 11 12:36:27 PM PDT 24
Finished Jun 11 12:36:36 PM PDT 24
Peak memory 210684 kb
Host smart-adb672f4-8d37-43e8-bb0f-9751ed88cef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535945727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2535945727
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2991864596
Short name T124
Test name
Test status
Simulation time 403897203261 ps
CPU time 270.46 seconds
Started Jun 11 12:36:26 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 224536 kb
Host smart-caed7f69-a1d5-4636-91b0-d0333e4ccbbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991864596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2991864596
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2655076615
Short name T198
Test name
Test status
Simulation time 6412299167 ps
CPU time 19.07 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:36:49 PM PDT 24
Peak memory 212052 kb
Host smart-895a5455-b906-485d-83dd-47a355fd01d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655076615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2655076615
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.581874606
Short name T274
Test name
Test status
Simulation time 394775493 ps
CPU time 7.86 seconds
Started Jun 11 12:36:40 PM PDT 24
Finished Jun 11 12:36:49 PM PDT 24
Peak memory 210804 kb
Host smart-30c1616c-319b-4187-8ed9-b1dba7c5403e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581874606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.581874606
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2212455813
Short name T340
Test name
Test status
Simulation time 535988061 ps
CPU time 11.76 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:36:42 PM PDT 24
Peak memory 212148 kb
Host smart-8793934c-68aa-47ad-996b-0b518dc4a7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212455813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2212455813
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1551735641
Short name T2
Test name
Test status
Simulation time 798422930 ps
CPU time 19.49 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:36:50 PM PDT 24
Peak memory 213724 kb
Host smart-82f78046-ed67-43f7-8660-f60732f2339b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551735641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1551735641
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1686234376
Short name T136
Test name
Test status
Simulation time 207987149 ps
CPU time 5.67 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:36:36 PM PDT 24
Peak memory 210724 kb
Host smart-c92c78c1-487a-451f-a5fd-0a856a0c5a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686234376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1686234376
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2960466062
Short name T134
Test name
Test status
Simulation time 110510942707 ps
CPU time 485.92 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:44:36 PM PDT 24
Peak memory 224732 kb
Host smart-e01b0d6c-6ff1-4955-9935-97dd5dd9a116
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960466062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2960466062
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2545946287
Short name T201
Test name
Test status
Simulation time 32773556767 ps
CPU time 30.04 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:37:10 PM PDT 24
Peak memory 211740 kb
Host smart-98c147b7-0a2f-4feb-8c60-f28c72bffb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545946287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2545946287
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.363706662
Short name T165
Test name
Test status
Simulation time 1166504036 ps
CPU time 12.52 seconds
Started Jun 11 12:36:40 PM PDT 24
Finished Jun 11 12:36:54 PM PDT 24
Peak memory 210820 kb
Host smart-8879d0d8-546d-41e5-9577-273b0f8eb60d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363706662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.363706662
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3647873016
Short name T170
Test name
Test status
Simulation time 6097132626 ps
CPU time 19.94 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 12:36:52 PM PDT 24
Peak memory 213160 kb
Host smart-2d4784bc-5575-4372-af2d-763069c8934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647873016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3647873016
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4192463035
Short name T279
Test name
Test status
Simulation time 14529507304 ps
CPU time 15.34 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:36:45 PM PDT 24
Peak memory 210872 kb
Host smart-35914fd6-3db1-467d-9c77-6010effdb7cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192463035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4192463035
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.409128195
Short name T347
Test name
Test status
Simulation time 60858800754 ps
CPU time 627.4 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:47:04 PM PDT 24
Peak memory 235212 kb
Host smart-4fed4a09-944f-4d1f-8d3e-a2b689139e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409128195 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.409128195
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2105186495
Short name T349
Test name
Test status
Simulation time 828125290 ps
CPU time 4.2 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:36:45 PM PDT 24
Peak memory 210656 kb
Host smart-6ba3e50e-8108-418d-9a41-338151ec9b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105186495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2105186495
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1035966139
Short name T304
Test name
Test status
Simulation time 39780368370 ps
CPU time 394.08 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 213304 kb
Host smart-e57e0522-e1ae-4f66-8bc4-9cce1791ab69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035966139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1035966139
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3207683629
Short name T297
Test name
Test status
Simulation time 9227552496 ps
CPU time 22.3 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:36:59 PM PDT 24
Peak memory 212136 kb
Host smart-6abd597a-6ac8-4ca8-af6a-a28a69383357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207683629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3207683629
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4274471748
Short name T357
Test name
Test status
Simulation time 192203389 ps
CPU time 5.32 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 12:36:37 PM PDT 24
Peak memory 210964 kb
Host smart-b1b518b0-fc43-4665-8f5a-8a11bc944295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274471748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4274471748
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3601776869
Short name T51
Test name
Test status
Simulation time 550133627 ps
CPU time 11.4 seconds
Started Jun 11 12:36:29 PM PDT 24
Finished Jun 11 12:36:41 PM PDT 24
Peak memory 213248 kb
Host smart-344d00c8-da92-4623-831c-43afd76e297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601776869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3601776869
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2402022172
Short name T9
Test name
Test status
Simulation time 11612573582 ps
CPU time 32.03 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:37:08 PM PDT 24
Peak memory 214380 kb
Host smart-7ccdb69d-a80d-4a12-a919-f29f556d15ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402022172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2402022172
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4085400649
Short name T302
Test name
Test status
Simulation time 10047614104 ps
CPU time 11.32 seconds
Started Jun 11 12:36:06 PM PDT 24
Finished Jun 11 12:36:19 PM PDT 24
Peak memory 210924 kb
Host smart-fb0ace0b-9223-46de-8e60-695d6149ee82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085400649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4085400649
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2686269057
Short name T29
Test name
Test status
Simulation time 1925908658 ps
CPU time 130.54 seconds
Started Jun 11 12:36:09 PM PDT 24
Finished Jun 11 12:38:20 PM PDT 24
Peak memory 236356 kb
Host smart-3cb2a803-7e26-463f-ad8a-d830fdba5b20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686269057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2686269057
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1407876780
Short name T362
Test name
Test status
Simulation time 2706169497 ps
CPU time 25.68 seconds
Started Jun 11 12:36:06 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 211716 kb
Host smart-314021db-8fb2-483b-b47a-8106a95b11ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407876780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1407876780
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.879473165
Short name T13
Test name
Test status
Simulation time 2629119557 ps
CPU time 11.77 seconds
Started Jun 11 12:36:04 PM PDT 24
Finished Jun 11 12:36:17 PM PDT 24
Peak memory 210944 kb
Host smart-5da6b0be-2925-4f96-859b-49097099a42b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879473165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.879473165
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3928045552
Short name T27
Test name
Test status
Simulation time 1924459573 ps
CPU time 61.49 seconds
Started Jun 11 12:36:04 PM PDT 24
Finished Jun 11 12:37:07 PM PDT 24
Peak memory 236228 kb
Host smart-917774a4-13dc-42fc-9173-983ec673795e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928045552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3928045552
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3825939414
Short name T358
Test name
Test status
Simulation time 177935103 ps
CPU time 9.98 seconds
Started Jun 11 12:36:02 PM PDT 24
Finished Jun 11 12:36:13 PM PDT 24
Peak memory 211752 kb
Host smart-ea66f99e-ae94-4b02-ab6e-eb0e6a141834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825939414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3825939414
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1591944571
Short name T351
Test name
Test status
Simulation time 5680033140 ps
CPU time 16.36 seconds
Started Jun 11 12:36:09 PM PDT 24
Finished Jun 11 12:36:26 PM PDT 24
Peak memory 210884 kb
Host smart-aa904ef6-c0b6-473b-bca8-49c69e47d26a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591944571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1591944571
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.42902228
Short name T250
Test name
Test status
Simulation time 1562067129 ps
CPU time 13.74 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:36:46 PM PDT 24
Peak memory 210772 kb
Host smart-96eb42e2-87cf-437f-9d32-bb5a67b38b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42902228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.42902228
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3013047054
Short name T156
Test name
Test status
Simulation time 13033856030 ps
CPU time 191.84 seconds
Started Jun 11 12:36:28 PM PDT 24
Finished Jun 11 12:39:41 PM PDT 24
Peak memory 212252 kb
Host smart-a170d4bf-1482-4ff2-a9e7-9f523c0f90d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013047054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3013047054
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.986159178
Short name T345
Test name
Test status
Simulation time 2189314052 ps
CPU time 22.15 seconds
Started Jun 11 12:36:32 PM PDT 24
Finished Jun 11 12:36:56 PM PDT 24
Peak memory 211856 kb
Host smart-ad3ac510-8ec2-474d-bda3-643f4730b814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986159178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.986159178
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4236241092
Short name T171
Test name
Test status
Simulation time 1551334018 ps
CPU time 14.3 seconds
Started Jun 11 12:36:28 PM PDT 24
Finished Jun 11 12:36:44 PM PDT 24
Peak memory 210908 kb
Host smart-7b30c900-924a-4ac8-a94f-59106f6d7eb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236241092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4236241092
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.624073913
Short name T160
Test name
Test status
Simulation time 23038320849 ps
CPU time 33.97 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:37:11 PM PDT 24
Peak memory 213440 kb
Host smart-0b609293-ad27-4db2-959e-934374872f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624073913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.624073913
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2136193557
Short name T332
Test name
Test status
Simulation time 885981360 ps
CPU time 6.98 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 12:36:38 PM PDT 24
Peak memory 210880 kb
Host smart-6c42032c-465a-49ce-b8f2-0c2c62b0266c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136193557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2136193557
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.585559576
Short name T213
Test name
Test status
Simulation time 1761528526 ps
CPU time 14.27 seconds
Started Jun 11 12:36:31 PM PDT 24
Finished Jun 11 12:36:47 PM PDT 24
Peak memory 210768 kb
Host smart-a550a407-c73f-4e9c-847f-964e2ad464a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585559576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.585559576
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4158520027
Short name T336
Test name
Test status
Simulation time 48378724284 ps
CPU time 183.88 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:39:40 PM PDT 24
Peak memory 227280 kb
Host smart-7655ab2c-627f-4a35-a576-9b498176fa15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158520027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4158520027
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.103568972
Short name T236
Test name
Test status
Simulation time 3029902040 ps
CPU time 18.87 seconds
Started Jun 11 12:36:34 PM PDT 24
Finished Jun 11 12:36:54 PM PDT 24
Peak memory 211724 kb
Host smart-bbc9367d-695a-4dea-a263-8bf2d4bd6f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103568972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.103568972
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4164978217
Short name T337
Test name
Test status
Simulation time 8574895182 ps
CPU time 10.9 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:36:51 PM PDT 24
Peak memory 210924 kb
Host smart-d145513e-fdfd-4cb7-97bb-12a59bb49788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164978217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4164978217
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3503357787
Short name T149
Test name
Test status
Simulation time 8592867070 ps
CPU time 34.19 seconds
Started Jun 11 12:36:30 PM PDT 24
Finished Jun 11 12:37:06 PM PDT 24
Peak memory 213460 kb
Host smart-b0ad935a-0611-4731-a723-7d6e08c50c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503357787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3503357787
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3658897997
Short name T312
Test name
Test status
Simulation time 3464116987 ps
CPU time 20.65 seconds
Started Jun 11 12:36:28 PM PDT 24
Finished Jun 11 12:36:49 PM PDT 24
Peak memory 211792 kb
Host smart-2d38bdfd-c4a2-496e-b1f6-2d564768766a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658897997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3658897997
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1306306103
Short name T186
Test name
Test status
Simulation time 347242999 ps
CPU time 4.43 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:36:41 PM PDT 24
Peak memory 210728 kb
Host smart-58661db3-658d-42bb-a0e0-7b727a5cfd4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306306103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1306306103
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.231184451
Short name T339
Test name
Test status
Simulation time 7565123094 ps
CPU time 114.17 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:38:31 PM PDT 24
Peak memory 234916 kb
Host smart-c7d5f1a8-9c99-4bdd-a36f-c66479160182
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231184451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.231184451
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.500331570
Short name T235
Test name
Test status
Simulation time 3845559799 ps
CPU time 31.19 seconds
Started Jun 11 12:36:38 PM PDT 24
Finished Jun 11 12:37:11 PM PDT 24
Peak memory 211520 kb
Host smart-2c75bfad-5874-4714-8793-0e73ecb36554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500331570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.500331570
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.813210983
Short name T152
Test name
Test status
Simulation time 1079935386 ps
CPU time 12.08 seconds
Started Jun 11 12:36:38 PM PDT 24
Finished Jun 11 12:36:51 PM PDT 24
Peak memory 210884 kb
Host smart-33411a0b-285d-4773-bbac-4d0e5a8e46e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813210983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.813210983
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.754793178
Short name T350
Test name
Test status
Simulation time 3012389367 ps
CPU time 30.63 seconds
Started Jun 11 12:36:37 PM PDT 24
Finished Jun 11 12:37:09 PM PDT 24
Peak memory 212668 kb
Host smart-05f84427-502d-4883-90e1-c6e9429e7f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754793178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.754793178
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.486775601
Short name T303
Test name
Test status
Simulation time 498281586 ps
CPU time 29.74 seconds
Started Jun 11 12:36:37 PM PDT 24
Finished Jun 11 12:37:08 PM PDT 24
Peak memory 215476 kb
Host smart-7691e168-f15d-46e2-8b38-e82f98557d61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486775601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.486775601
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3610339586
Short name T18
Test name
Test status
Simulation time 1630841853 ps
CPU time 7.1 seconds
Started Jun 11 12:36:37 PM PDT 24
Finished Jun 11 12:36:45 PM PDT 24
Peak memory 210736 kb
Host smart-e166f6c2-8382-4993-91a8-39da26f689c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610339586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3610339586
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1186934290
Short name T5
Test name
Test status
Simulation time 17537065629 ps
CPU time 132.01 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:39:02 PM PDT 24
Peak memory 232388 kb
Host smart-22713a20-ea2a-4148-9451-c2d756665d38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186934290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1186934290
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2620744728
Short name T40
Test name
Test status
Simulation time 3998260896 ps
CPU time 21.22 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:36:57 PM PDT 24
Peak memory 211576 kb
Host smart-09457411-8973-4b96-a2d9-63c97c05ab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620744728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2620744728
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2679165118
Short name T253
Test name
Test status
Simulation time 100144524 ps
CPU time 5.84 seconds
Started Jun 11 12:36:43 PM PDT 24
Finished Jun 11 12:36:50 PM PDT 24
Peak memory 210912 kb
Host smart-cdb29ba8-6e40-4cfa-868c-e664898bd098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679165118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2679165118
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3252455522
Short name T73
Test name
Test status
Simulation time 3679487383 ps
CPU time 37.27 seconds
Started Jun 11 12:36:43 PM PDT 24
Finished Jun 11 12:37:21 PM PDT 24
Peak memory 213200 kb
Host smart-0c3bb8ad-1f83-4eb7-88d1-dff34a0887f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252455522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3252455522
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3526639866
Short name T320
Test name
Test status
Simulation time 1188092989 ps
CPU time 17.94 seconds
Started Jun 11 12:36:50 PM PDT 24
Finished Jun 11 12:37:09 PM PDT 24
Peak memory 210876 kb
Host smart-475a0e84-2dc5-4e04-a74c-9de14468ade9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526639866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3526639866
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.494702144
Short name T42
Test name
Test status
Simulation time 21068348795 ps
CPU time 396.16 seconds
Started Jun 11 12:36:37 PM PDT 24
Finished Jun 11 12:43:15 PM PDT 24
Peak memory 231744 kb
Host smart-1299e9cf-9c06-419e-b4be-f19a2299f669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494702144 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.494702144
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1887052137
Short name T308
Test name
Test status
Simulation time 1724698715 ps
CPU time 14.12 seconds
Started Jun 11 12:36:38 PM PDT 24
Finished Jun 11 12:36:53 PM PDT 24
Peak memory 210756 kb
Host smart-fb804cc5-5633-4517-adc6-e28be9e0fdb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887052137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1887052137
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3497717625
Short name T187
Test name
Test status
Simulation time 81247636951 ps
CPU time 196.7 seconds
Started Jun 11 12:36:38 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 236680 kb
Host smart-71d97e42-dcce-47d3-990a-28167ee9296a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497717625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3497717625
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2379708798
Short name T313
Test name
Test status
Simulation time 3230131029 ps
CPU time 28.84 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:37:09 PM PDT 24
Peak memory 211524 kb
Host smart-e37a53b8-d4d7-48ff-944f-e7aef05052d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379708798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2379708798
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2189838269
Short name T310
Test name
Test status
Simulation time 1812274809 ps
CPU time 8.29 seconds
Started Jun 11 12:36:38 PM PDT 24
Finished Jun 11 12:36:47 PM PDT 24
Peak memory 210964 kb
Host smart-1377b77f-7c63-450a-81ed-21fd15f66647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2189838269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2189838269
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2660305664
Short name T233
Test name
Test status
Simulation time 1129303919 ps
CPU time 19.04 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:36:56 PM PDT 24
Peak memory 213152 kb
Host smart-fa380d86-97b3-451e-8ca2-4ba9c2982d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660305664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2660305664
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2914655221
Short name T282
Test name
Test status
Simulation time 4639015036 ps
CPU time 26.9 seconds
Started Jun 11 12:36:43 PM PDT 24
Finished Jun 11 12:37:10 PM PDT 24
Peak memory 213440 kb
Host smart-9db39074-9e0e-4853-b5ce-c8f88c9c8cef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914655221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2914655221
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.220048083
Short name T59
Test name
Test status
Simulation time 2003462052 ps
CPU time 10.46 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:36:47 PM PDT 24
Peak memory 210780 kb
Host smart-20accec4-af60-42c0-a29a-4096030c9e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220048083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.220048083
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1337772635
Short name T37
Test name
Test status
Simulation time 4749336362 ps
CPU time 17.07 seconds
Started Jun 11 12:36:40 PM PDT 24
Finished Jun 11 12:36:59 PM PDT 24
Peak memory 212004 kb
Host smart-aa21d8b9-2281-4e47-9e4c-53642c37e454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337772635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1337772635
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.20696563
Short name T168
Test name
Test status
Simulation time 2627343084 ps
CPU time 17.28 seconds
Started Jun 11 12:36:36 PM PDT 24
Finished Jun 11 12:36:55 PM PDT 24
Peak memory 210996 kb
Host smart-c047a29a-dfee-4da9-b6ed-959b5a74f6cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20696563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.20696563
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3664044698
Short name T343
Test name
Test status
Simulation time 3359760696 ps
CPU time 22.02 seconds
Started Jun 11 12:36:35 PM PDT 24
Finished Jun 11 12:36:59 PM PDT 24
Peak memory 213180 kb
Host smart-a67e878b-3a64-443c-a45b-7f44ef03eabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664044698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3664044698
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3435074907
Short name T74
Test name
Test status
Simulation time 8552224469 ps
CPU time 37.83 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:37:18 PM PDT 24
Peak memory 214752 kb
Host smart-88fd0df3-d2a1-4408-82bc-4e1d6d6d3a8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435074907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3435074907
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1343699556
Short name T220
Test name
Test status
Simulation time 89339776 ps
CPU time 4.29 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:36:54 PM PDT 24
Peak memory 210648 kb
Host smart-0655e0d7-1b06-42a3-b908-cc4f11363663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343699556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1343699556
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2733450229
Short name T301
Test name
Test status
Simulation time 14380329737 ps
CPU time 120.47 seconds
Started Jun 11 12:36:42 PM PDT 24
Finished Jun 11 12:38:43 PM PDT 24
Peak memory 212164 kb
Host smart-a428ddb9-789b-4c7c-aeea-985327d5ed8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733450229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2733450229
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2460543197
Short name T352
Test name
Test status
Simulation time 667228730 ps
CPU time 9.48 seconds
Started Jun 11 12:36:38 PM PDT 24
Finished Jun 11 12:36:49 PM PDT 24
Peak memory 211800 kb
Host smart-5af2d242-bc3d-4934-bca4-de39129d7a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460543197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2460543197
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.946297229
Short name T338
Test name
Test status
Simulation time 2272088233 ps
CPU time 9.17 seconds
Started Jun 11 12:36:37 PM PDT 24
Finished Jun 11 12:36:47 PM PDT 24
Peak memory 210980 kb
Host smart-3d285049-4358-40f8-a0a4-7704b8c8d24d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946297229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.946297229
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3628387375
Short name T20
Test name
Test status
Simulation time 706679256 ps
CPU time 14.78 seconds
Started Jun 11 12:36:43 PM PDT 24
Finished Jun 11 12:36:59 PM PDT 24
Peak memory 213192 kb
Host smart-2cd13d48-e90f-4eeb-8195-66ad8e74f652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628387375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3628387375
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1624280812
Short name T288
Test name
Test status
Simulation time 1139458718 ps
CPU time 20.93 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:37:02 PM PDT 24
Peak memory 214976 kb
Host smart-06aaf82a-932c-4b72-97d2-a4268948bd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624280812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1624280812
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1764766918
Short name T95
Test name
Test status
Simulation time 182522019 ps
CPU time 4.26 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:36:54 PM PDT 24
Peak memory 210660 kb
Host smart-10031304-8be2-45a5-9f4f-d20df66422eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764766918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1764766918
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3614766733
Short name T318
Test name
Test status
Simulation time 45367141490 ps
CPU time 133.67 seconds
Started Jun 11 12:36:39 PM PDT 24
Finished Jun 11 12:38:54 PM PDT 24
Peak memory 234436 kb
Host smart-5900ebdf-a4f0-416f-b870-4003e02dfbf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614766733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3614766733
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.719191405
Short name T172
Test name
Test status
Simulation time 345210744 ps
CPU time 11.73 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:02 PM PDT 24
Peak memory 211476 kb
Host smart-f1cada71-6317-442b-a34e-4fdfb0c522d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719191405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.719191405
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3229874638
Short name T283
Test name
Test status
Simulation time 9475191386 ps
CPU time 11.18 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:37:01 PM PDT 24
Peak memory 211052 kb
Host smart-4f658558-09b9-480d-918d-4a90bce63598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229874638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3229874638
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3373042060
Short name T281
Test name
Test status
Simulation time 6846463822 ps
CPU time 29.02 seconds
Started Jun 11 12:36:36 PM PDT 24
Finished Jun 11 12:37:06 PM PDT 24
Peak memory 213456 kb
Host smart-93923b48-9cc3-41a9-838d-16a83680d72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373042060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3373042060
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.425239402
Short name T183
Test name
Test status
Simulation time 3165449958 ps
CPU time 39.91 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:29 PM PDT 24
Peak memory 216500 kb
Host smart-7d9ee5c7-f422-4cdd-b747-f730940ad1c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425239402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.425239402
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1387394942
Short name T299
Test name
Test status
Simulation time 18764663935 ps
CPU time 10.57 seconds
Started Jun 11 12:36:36 PM PDT 24
Finished Jun 11 12:36:48 PM PDT 24
Peak memory 210888 kb
Host smart-60805998-bf52-4428-9631-643e3f8ef3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387394942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1387394942
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2828591646
Short name T120
Test name
Test status
Simulation time 3845960357 ps
CPU time 114.46 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:38:44 PM PDT 24
Peak memory 237480 kb
Host smart-aa32af11-b577-4e2c-b0cf-f975445d0a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828591646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2828591646
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3002864337
Short name T202
Test name
Test status
Simulation time 3909407486 ps
CPU time 30.61 seconds
Started Jun 11 12:36:40 PM PDT 24
Finished Jun 11 12:37:12 PM PDT 24
Peak memory 211616 kb
Host smart-4e277884-e890-4565-932f-8be9d5b6a077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002864337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3002864337
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1477025069
Short name T39
Test name
Test status
Simulation time 1722401583 ps
CPU time 14.87 seconds
Started Jun 11 12:36:50 PM PDT 24
Finished Jun 11 12:37:06 PM PDT 24
Peak memory 210952 kb
Host smart-7bb58dd1-03c7-48c6-9e77-c100106b8f4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477025069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1477025069
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1270840471
Short name T261
Test name
Test status
Simulation time 8362127218 ps
CPU time 42.87 seconds
Started Jun 11 12:36:50 PM PDT 24
Finished Jun 11 12:37:34 PM PDT 24
Peak memory 214012 kb
Host smart-d4d46e87-63f2-4c5f-9e2b-2f4d537da53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270840471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1270840471
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1687187324
Short name T364
Test name
Test status
Simulation time 5733510022 ps
CPU time 17.77 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:08 PM PDT 24
Peak memory 213524 kb
Host smart-22d8d7d7-3c03-494e-b3b9-9183a56e6dbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687187324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1687187324
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1470516322
Short name T60
Test name
Test status
Simulation time 416605132 ps
CPU time 4.18 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:36:54 PM PDT 24
Peak memory 210760 kb
Host smart-a5a0b96d-a248-4594-b557-2ef6435bb646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470516322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1470516322
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2812505553
Short name T325
Test name
Test status
Simulation time 24588868491 ps
CPU time 189.97 seconds
Started Jun 11 12:36:54 PM PDT 24
Finished Jun 11 12:40:05 PM PDT 24
Peak memory 234520 kb
Host smart-48e38d19-622f-42bf-a349-9ea8e6385157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812505553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2812505553
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3927504510
Short name T141
Test name
Test status
Simulation time 639969842 ps
CPU time 9.38 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:00 PM PDT 24
Peak memory 211532 kb
Host smart-4053c71e-f19b-4e56-9551-16ff70f23e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927504510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3927504510
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1399733949
Short name T178
Test name
Test status
Simulation time 1712784152 ps
CPU time 10.6 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:36:59 PM PDT 24
Peak memory 210928 kb
Host smart-1a4c30ee-6c8e-4ffd-ab5b-737e7e553919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399733949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1399733949
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1075137640
Short name T163
Test name
Test status
Simulation time 2509650548 ps
CPU time 15.21 seconds
Started Jun 11 12:36:54 PM PDT 24
Finished Jun 11 12:37:10 PM PDT 24
Peak memory 212808 kb
Host smart-4d2fd8c0-65bf-47a8-ae0e-4b0481643e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075137640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1075137640
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4028438930
Short name T48
Test name
Test status
Simulation time 6761106985 ps
CPU time 25.99 seconds
Started Jun 11 12:36:53 PM PDT 24
Finished Jun 11 12:37:19 PM PDT 24
Peak memory 212516 kb
Host smart-d9d13a1d-9f42-41bb-9d96-c20d4a8030f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028438930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4028438930
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.768857249
Short name T224
Test name
Test status
Simulation time 1532767367 ps
CPU time 13.43 seconds
Started Jun 11 12:36:08 PM PDT 24
Finished Jun 11 12:36:22 PM PDT 24
Peak memory 210772 kb
Host smart-6ef576fa-397e-46f4-b74a-0a8027bd96e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768857249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.768857249
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1707140814
Short name T193
Test name
Test status
Simulation time 170460380282 ps
CPU time 434.7 seconds
Started Jun 11 12:36:03 PM PDT 24
Finished Jun 11 12:43:19 PM PDT 24
Peak memory 236892 kb
Host smart-09c94d1b-1083-4c09-9071-bf8255459160
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707140814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1707140814
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2065107291
Short name T273
Test name
Test status
Simulation time 3494246040 ps
CPU time 29.48 seconds
Started Jun 11 12:36:03 PM PDT 24
Finished Jun 11 12:36:34 PM PDT 24
Peak memory 211612 kb
Host smart-40ad546a-43aa-4601-8927-67a323854064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065107291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2065107291
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.203301529
Short name T207
Test name
Test status
Simulation time 1819232747 ps
CPU time 16.31 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:23 PM PDT 24
Peak memory 210884 kb
Host smart-2de0f474-b3d7-4672-8cca-430e4cfa07d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=203301529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.203301529
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.601883496
Short name T255
Test name
Test status
Simulation time 856521344 ps
CPU time 13.01 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:20 PM PDT 24
Peak memory 213204 kb
Host smart-ec3d067a-f233-485d-9133-8ae150cab906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601883496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.601883496
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3793668339
Short name T92
Test name
Test status
Simulation time 283112142 ps
CPU time 15.76 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:23 PM PDT 24
Peak memory 213400 kb
Host smart-8ba5ec9d-e64d-4fb0-82b9-da2c815cfaa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793668339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3793668339
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3087204671
Short name T192
Test name
Test status
Simulation time 168202289 ps
CPU time 4.27 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:36:54 PM PDT 24
Peak memory 210740 kb
Host smart-5dbd6ad1-f457-40e0-8b94-2a4f26fe01ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087204671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3087204671
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1046351478
Short name T237
Test name
Test status
Simulation time 68055987848 ps
CPU time 221.1 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:40:30 PM PDT 24
Peak memory 237584 kb
Host smart-bc7a5f8c-acff-4cfa-aa53-a00dc2673659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046351478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1046351478
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2826183665
Short name T199
Test name
Test status
Simulation time 3339880412 ps
CPU time 28.7 seconds
Started Jun 11 12:36:46 PM PDT 24
Finished Jun 11 12:37:16 PM PDT 24
Peak memory 211580 kb
Host smart-2218001e-ff81-428c-8999-6d11b3a8369c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826183665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2826183665
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2674986333
Short name T270
Test name
Test status
Simulation time 1814977544 ps
CPU time 16.48 seconds
Started Jun 11 12:36:46 PM PDT 24
Finished Jun 11 12:37:04 PM PDT 24
Peak memory 210940 kb
Host smart-3a27ccdb-16dd-4cfa-a061-f5f2429b9b2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674986333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2674986333
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1833425561
Short name T315
Test name
Test status
Simulation time 3147119837 ps
CPU time 18.69 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:08 PM PDT 24
Peak memory 213480 kb
Host smart-31aba941-538e-4730-a3e3-ef5bf3425f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833425561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1833425561
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3414466426
Short name T307
Test name
Test status
Simulation time 39432270829 ps
CPU time 31.94 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:22 PM PDT 24
Peak memory 213972 kb
Host smart-b08bb593-c60d-4112-956a-dd90133571d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414466426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3414466426
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2165736327
Short name T252
Test name
Test status
Simulation time 1164115318 ps
CPU time 11.47 seconds
Started Jun 11 12:36:54 PM PDT 24
Finished Jun 11 12:37:06 PM PDT 24
Peak memory 210712 kb
Host smart-adfee43f-3312-4f4e-9bb9-94124529bd89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165736327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2165736327
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4181341370
Short name T93
Test name
Test status
Simulation time 15020727900 ps
CPU time 140.18 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:39:09 PM PDT 24
Peak memory 233116 kb
Host smart-1751d181-24db-4350-aba6-494144e371d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181341370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4181341370
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2857909942
Short name T189
Test name
Test status
Simulation time 340989941 ps
CPU time 9.6 seconds
Started Jun 11 12:36:50 PM PDT 24
Finished Jun 11 12:37:01 PM PDT 24
Peak memory 211416 kb
Host smart-470c9e7f-d39f-4afe-b574-6848ae46c860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857909942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2857909942
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3490719847
Short name T333
Test name
Test status
Simulation time 374243792 ps
CPU time 5.24 seconds
Started Jun 11 12:36:53 PM PDT 24
Finished Jun 11 12:37:00 PM PDT 24
Peak memory 210860 kb
Host smart-9fd8c236-34bb-46e2-843f-a95928638f74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490719847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3490719847
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2731262869
Short name T291
Test name
Test status
Simulation time 4511087330 ps
CPU time 18.52 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:09 PM PDT 24
Peak memory 213884 kb
Host smart-850ed772-e10a-42c5-a36e-30202a5c737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731262869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2731262869
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1471235166
Short name T265
Test name
Test status
Simulation time 16019236582 ps
CPU time 24.04 seconds
Started Jun 11 12:36:51 PM PDT 24
Finished Jun 11 12:37:17 PM PDT 24
Peak memory 215872 kb
Host smart-c4303fa8-fba7-4b69-8c6f-faf66e5c2ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471235166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1471235166
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1744784864
Short name T329
Test name
Test status
Simulation time 10419270535 ps
CPU time 13.68 seconds
Started Jun 11 12:36:54 PM PDT 24
Finished Jun 11 12:37:09 PM PDT 24
Peak memory 210920 kb
Host smart-1b2f4c61-e91c-4218-8bc0-302538c354ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744784864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1744784864
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1979563486
Short name T334
Test name
Test status
Simulation time 94579796007 ps
CPU time 240.53 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:40:50 PM PDT 24
Peak memory 236520 kb
Host smart-9b2c7b46-16bb-4b37-9007-b5cd309f805c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979563486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1979563486
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1994323860
Short name T286
Test name
Test status
Simulation time 2250645616 ps
CPU time 23.69 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:14 PM PDT 24
Peak memory 211584 kb
Host smart-a16ad01d-c59e-4c2f-b3a9-462c53a46677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994323860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1994323860
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1591689920
Short name T300
Test name
Test status
Simulation time 1407555727 ps
CPU time 13.47 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:04 PM PDT 24
Peak memory 210956 kb
Host smart-f869c55f-4906-43e2-8fdd-9c830fd885b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591689920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1591689920
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3795824173
Short name T221
Test name
Test status
Simulation time 3058140986 ps
CPU time 27.29 seconds
Started Jun 11 12:36:49 PM PDT 24
Finished Jun 11 12:37:18 PM PDT 24
Peak memory 213300 kb
Host smart-6847ff61-9114-4683-9786-d1eaa6a5c1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795824173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3795824173
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1441493367
Short name T278
Test name
Test status
Simulation time 586693280 ps
CPU time 16.56 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:07 PM PDT 24
Peak memory 215088 kb
Host smart-96d022ac-3c96-42b8-aa37-f5bc01c5bf02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441493367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1441493367
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2977842986
Short name T6
Test name
Test status
Simulation time 2138835725 ps
CPU time 17.02 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:37:05 PM PDT 24
Peak memory 210764 kb
Host smart-0e261420-e905-433a-ad28-4f6c25fa016c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977842986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2977842986
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1634729279
Short name T285
Test name
Test status
Simulation time 19111099230 ps
CPU time 199.72 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:40:09 PM PDT 24
Peak memory 232604 kb
Host smart-3d630876-b274-409a-994a-267538a4bab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634729279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1634729279
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3251776122
Short name T32
Test name
Test status
Simulation time 342627292 ps
CPU time 9.5 seconds
Started Jun 11 12:36:49 PM PDT 24
Finished Jun 11 12:37:00 PM PDT 24
Peak memory 212300 kb
Host smart-c5b0893c-8c21-4cb7-9456-0a30d225c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251776122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3251776122
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2855740605
Short name T245
Test name
Test status
Simulation time 8259142506 ps
CPU time 16.82 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:37:05 PM PDT 24
Peak memory 211068 kb
Host smart-6c71aaeb-67ee-4bcc-b0ce-91a6d8eb010b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2855740605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2855740605
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2677591955
Short name T228
Test name
Test status
Simulation time 2746022867 ps
CPU time 26.03 seconds
Started Jun 11 12:36:50 PM PDT 24
Finished Jun 11 12:37:18 PM PDT 24
Peak memory 212336 kb
Host smart-df4e3b0d-3d19-4819-9172-891dcee15194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677591955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2677591955
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2339481461
Short name T174
Test name
Test status
Simulation time 1769996148 ps
CPU time 18.2 seconds
Started Jun 11 12:36:53 PM PDT 24
Finished Jun 11 12:37:12 PM PDT 24
Peak memory 213292 kb
Host smart-04e42bd6-f951-4375-b740-566dac76baf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339481461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2339481461
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1046754341
Short name T61
Test name
Test status
Simulation time 2967418419 ps
CPU time 12.11 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:37:00 PM PDT 24
Peak memory 210792 kb
Host smart-5a9fc2c0-f36b-4257-b469-74bf20b851ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046754341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1046754341
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2747937660
Short name T247
Test name
Test status
Simulation time 240309368883 ps
CPU time 577.65 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:46:27 PM PDT 24
Peak memory 236564 kb
Host smart-b7619490-18ce-466e-a88b-a601540c02ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747937660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2747937660
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.359934386
Short name T181
Test name
Test status
Simulation time 2364017143 ps
CPU time 9.27 seconds
Started Jun 11 12:36:51 PM PDT 24
Finished Jun 11 12:37:02 PM PDT 24
Peak memory 211604 kb
Host smart-01811ab9-93c0-4542-a2a6-3cffdf2e78b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359934386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.359934386
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2573919922
Short name T259
Test name
Test status
Simulation time 611943080 ps
CPU time 7.2 seconds
Started Jun 11 12:36:54 PM PDT 24
Finished Jun 11 12:37:02 PM PDT 24
Peak memory 210760 kb
Host smart-5cac0600-4532-4b17-b13a-6ff1a2427ed9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573919922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2573919922
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.598078949
Short name T146
Test name
Test status
Simulation time 2344585659 ps
CPU time 24.11 seconds
Started Jun 11 12:36:46 PM PDT 24
Finished Jun 11 12:37:11 PM PDT 24
Peak memory 213028 kb
Host smart-57ff0297-9c5d-44be-9402-1093c6387931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598078949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.598078949
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2868300779
Short name T317
Test name
Test status
Simulation time 2152343160 ps
CPU time 17.53 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:37:06 PM PDT 24
Peak memory 211660 kb
Host smart-886e381c-4ba0-49c5-b36e-43888c091713
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868300779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2868300779
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2296057696
Short name T144
Test name
Test status
Simulation time 1882634582 ps
CPU time 16.14 seconds
Started Jun 11 12:36:48 PM PDT 24
Finished Jun 11 12:37:06 PM PDT 24
Peak memory 211056 kb
Host smart-4ad6d026-1177-4e8e-9453-fe36e90d6d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296057696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2296057696
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.654527301
Short name T34
Test name
Test status
Simulation time 12384792229 ps
CPU time 198.85 seconds
Started Jun 11 12:36:54 PM PDT 24
Finished Jun 11 12:40:14 PM PDT 24
Peak memory 237528 kb
Host smart-c9d2c823-b3ff-4f28-a71f-e65c328c23c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654527301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.654527301
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4136829035
Short name T123
Test name
Test status
Simulation time 2972956533 ps
CPU time 26.88 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 12:37:16 PM PDT 24
Peak memory 211724 kb
Host smart-46c4c267-699a-422d-95bd-8a8df5497a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136829035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4136829035
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4178108200
Short name T131
Test name
Test status
Simulation time 4463192001 ps
CPU time 17.65 seconds
Started Jun 11 12:36:50 PM PDT 24
Finished Jun 11 12:37:09 PM PDT 24
Peak memory 211036 kb
Host smart-6d985dbf-264f-46bb-b5ee-1887b59ea38e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178108200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4178108200
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4090018824
Short name T145
Test name
Test status
Simulation time 15397437540 ps
CPU time 31.51 seconds
Started Jun 11 12:36:46 PM PDT 24
Finished Jun 11 12:37:19 PM PDT 24
Peak memory 214080 kb
Host smart-f8c375e0-8841-456e-a889-c2d8141ca124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090018824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4090018824
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1328879144
Short name T321
Test name
Test status
Simulation time 8185859272 ps
CPU time 20.2 seconds
Started Jun 11 12:36:50 PM PDT 24
Finished Jun 11 12:37:12 PM PDT 24
Peak memory 211200 kb
Host smart-140c9464-6687-485b-a141-3d1fa70705c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328879144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1328879144
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3620923437
Short name T280
Test name
Test status
Simulation time 2929024107 ps
CPU time 13.28 seconds
Started Jun 11 12:36:53 PM PDT 24
Finished Jun 11 12:37:07 PM PDT 24
Peak memory 210832 kb
Host smart-787b8603-72f7-4be6-8488-256ac4e98403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620923437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3620923437
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.322718858
Short name T33
Test name
Test status
Simulation time 183620625002 ps
CPU time 405.98 seconds
Started Jun 11 12:36:54 PM PDT 24
Finished Jun 11 12:43:41 PM PDT 24
Peak memory 212396 kb
Host smart-523b947c-b92c-4fae-af2b-e625955a6350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322718858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.322718858
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1441454638
Short name T292
Test name
Test status
Simulation time 7401742086 ps
CPU time 23.58 seconds
Started Jun 11 12:36:53 PM PDT 24
Finished Jun 11 12:37:18 PM PDT 24
Peak memory 212112 kb
Host smart-b3a9aa36-ef7e-4235-95bf-5054ead8f10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441454638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1441454638
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2859048562
Short name T241
Test name
Test status
Simulation time 37865663006 ps
CPU time 17.06 seconds
Started Jun 11 12:36:54 PM PDT 24
Finished Jun 11 12:37:12 PM PDT 24
Peak memory 211088 kb
Host smart-65745e28-dc5d-49b9-aa76-641111eebdc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859048562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2859048562
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1506385119
Short name T180
Test name
Test status
Simulation time 2672950104 ps
CPU time 31.38 seconds
Started Jun 11 12:36:46 PM PDT 24
Finished Jun 11 12:37:18 PM PDT 24
Peak memory 213072 kb
Host smart-3035b2e3-59b3-4a05-be33-35de3bf087ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506385119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1506385119
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3265014911
Short name T251
Test name
Test status
Simulation time 1857383706 ps
CPU time 28.07 seconds
Started Jun 11 12:36:53 PM PDT 24
Finished Jun 11 12:37:22 PM PDT 24
Peak memory 215368 kb
Host smart-c644a4ac-814f-4fc4-94de-7be237d1910c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265014911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3265014911
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.52617377
Short name T263
Test name
Test status
Simulation time 2449719746 ps
CPU time 12.08 seconds
Started Jun 11 12:37:06 PM PDT 24
Finished Jun 11 12:37:19 PM PDT 24
Peak memory 210848 kb
Host smart-5a7ee788-660b-4ef2-9377-38eeb65e0ee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52617377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.52617377
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1955673265
Short name T256
Test name
Test status
Simulation time 1903959095 ps
CPU time 123.28 seconds
Started Jun 11 12:36:49 PM PDT 24
Finished Jun 11 12:38:54 PM PDT 24
Peak memory 232436 kb
Host smart-eaf32222-b692-4265-b438-5d921ac1ef58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955673265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1955673265
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1543167552
Short name T182
Test name
Test status
Simulation time 175996596 ps
CPU time 9.31 seconds
Started Jun 11 12:36:53 PM PDT 24
Finished Jun 11 12:37:04 PM PDT 24
Peak memory 211592 kb
Host smart-a7d8ae0c-e569-4514-9833-36bc4680cb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543167552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1543167552
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3275695913
Short name T8
Test name
Test status
Simulation time 4624491720 ps
CPU time 12.25 seconds
Started Jun 11 12:36:46 PM PDT 24
Finished Jun 11 12:36:59 PM PDT 24
Peak memory 211088 kb
Host smart-5d66db99-1003-4974-a587-e5e1b144b496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275695913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3275695913
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2038422846
Short name T154
Test name
Test status
Simulation time 3934490416 ps
CPU time 15.92 seconds
Started Jun 11 12:36:46 PM PDT 24
Finished Jun 11 12:37:03 PM PDT 24
Peak memory 212804 kb
Host smart-f53d909a-b092-4290-8280-8675b48ef388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038422846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2038422846
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4155412253
Short name T96
Test name
Test status
Simulation time 47177339039 ps
CPU time 115.28 seconds
Started Jun 11 12:36:50 PM PDT 24
Finished Jun 11 12:38:47 PM PDT 24
Peak memory 219036 kb
Host smart-3b6d0a05-0f9d-4f47-9b1c-ed94e254faf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155412253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4155412253
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1775676858
Short name T47
Test name
Test status
Simulation time 554516151652 ps
CPU time 2101.75 seconds
Started Jun 11 12:36:47 PM PDT 24
Finished Jun 11 01:11:51 PM PDT 24
Peak memory 237892 kb
Host smart-4d8342ea-0b35-4c18-aba5-a3d0b0e4e12a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775676858 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1775676858
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.426038327
Short name T223
Test name
Test status
Simulation time 168551896 ps
CPU time 4.19 seconds
Started Jun 11 12:37:00 PM PDT 24
Finished Jun 11 12:37:05 PM PDT 24
Peak memory 210760 kb
Host smart-36fec906-ada0-4b16-b4ed-335decce6fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426038327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.426038327
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3653305644
Short name T293
Test name
Test status
Simulation time 16816903290 ps
CPU time 219.75 seconds
Started Jun 11 12:37:00 PM PDT 24
Finished Jun 11 12:40:42 PM PDT 24
Peak memory 228084 kb
Host smart-56a90b67-6ba0-476c-8eff-d9d5a9a3aef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653305644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3653305644
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.301683675
Short name T232
Test name
Test status
Simulation time 3765653557 ps
CPU time 32.15 seconds
Started Jun 11 12:37:01 PM PDT 24
Finished Jun 11 12:37:35 PM PDT 24
Peak memory 211368 kb
Host smart-5190f087-d85f-4340-b11b-eaf2a094ca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301683675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.301683675
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1640251439
Short name T130
Test name
Test status
Simulation time 1778105322 ps
CPU time 15.95 seconds
Started Jun 11 12:37:05 PM PDT 24
Finished Jun 11 12:37:22 PM PDT 24
Peak memory 210976 kb
Host smart-dbd80ea6-ea92-4fd3-8f65-43b0050e1440
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640251439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1640251439
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2976648148
Short name T326
Test name
Test status
Simulation time 3959184660 ps
CPU time 24.26 seconds
Started Jun 11 12:37:01 PM PDT 24
Finished Jun 11 12:37:27 PM PDT 24
Peak memory 213380 kb
Host smart-01834632-5cf2-4ac4-bbf2-88d1e92ba783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976648148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2976648148
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4081647146
Short name T28
Test name
Test status
Simulation time 770394091 ps
CPU time 21.51 seconds
Started Jun 11 12:37:03 PM PDT 24
Finished Jun 11 12:37:26 PM PDT 24
Peak memory 215652 kb
Host smart-5cb1fabb-9675-47b7-9892-ebe5c1dfb49a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081647146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4081647146
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3560989501
Short name T294
Test name
Test status
Simulation time 11406100141 ps
CPU time 712.96 seconds
Started Jun 11 12:37:04 PM PDT 24
Finished Jun 11 12:48:58 PM PDT 24
Peak memory 231676 kb
Host smart-4be33679-5a12-42b8-af10-43e986d8452f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560989501 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3560989501
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2287408161
Short name T188
Test name
Test status
Simulation time 113464181265 ps
CPU time 294.8 seconds
Started Jun 11 12:36:59 PM PDT 24
Finished Jun 11 12:41:55 PM PDT 24
Peak memory 213300 kb
Host smart-89613164-c604-4470-9f55-64a7247d4ab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287408161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2287408161
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.825479861
Short name T226
Test name
Test status
Simulation time 4383824204 ps
CPU time 35.47 seconds
Started Jun 11 12:37:04 PM PDT 24
Finished Jun 11 12:37:41 PM PDT 24
Peak memory 212104 kb
Host smart-6d8f55d4-84d3-42b0-99ee-6ab97eb9b548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825479861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.825479861
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.408375710
Short name T323
Test name
Test status
Simulation time 594799216 ps
CPU time 9.06 seconds
Started Jun 11 12:36:59 PM PDT 24
Finished Jun 11 12:37:09 PM PDT 24
Peak memory 210964 kb
Host smart-85257384-f3cc-4c3a-b11d-f576b9942b3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408375710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.408375710
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2723350711
Short name T268
Test name
Test status
Simulation time 22760715744 ps
CPU time 29.86 seconds
Started Jun 11 12:37:02 PM PDT 24
Finished Jun 11 12:37:33 PM PDT 24
Peak memory 214408 kb
Host smart-b8f1bb14-0b0e-4fd0-a039-a3f2ee337f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723350711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2723350711
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1413271269
Short name T298
Test name
Test status
Simulation time 6824230470 ps
CPU time 45.85 seconds
Started Jun 11 12:37:03 PM PDT 24
Finished Jun 11 12:37:50 PM PDT 24
Peak memory 219000 kb
Host smart-3f5abd5b-040d-4b29-a632-5f805172afcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413271269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1413271269
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3789250522
Short name T44
Test name
Test status
Simulation time 18766703058 ps
CPU time 4245.25 seconds
Started Jun 11 12:37:00 PM PDT 24
Finished Jun 11 01:47:47 PM PDT 24
Peak memory 232372 kb
Host smart-19e6cb89-17cf-4b0c-b554-d4d3392cf3b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789250522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3789250522
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1671936838
Short name T217
Test name
Test status
Simulation time 2132670156 ps
CPU time 11.26 seconds
Started Jun 11 12:36:17 PM PDT 24
Finished Jun 11 12:36:30 PM PDT 24
Peak memory 210768 kb
Host smart-d39d8afe-181b-4c68-8cdd-7ad09c81db95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671936838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1671936838
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2839699230
Short name T290
Test name
Test status
Simulation time 21034914426 ps
CPU time 237.26 seconds
Started Jun 11 12:36:10 PM PDT 24
Finished Jun 11 12:40:09 PM PDT 24
Peak memory 237464 kb
Host smart-3ec551ee-b4dd-4d93-bc02-f9de660ff491
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839699230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2839699230
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1177451814
Short name T311
Test name
Test status
Simulation time 3067741227 ps
CPU time 18.79 seconds
Started Jun 11 12:36:07 PM PDT 24
Finished Jun 11 12:36:27 PM PDT 24
Peak memory 211720 kb
Host smart-62b154dc-0a08-4a6b-8726-143e20d6b6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177451814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1177451814
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2484028315
Short name T344
Test name
Test status
Simulation time 1547757472 ps
CPU time 13.96 seconds
Started Jun 11 12:36:05 PM PDT 24
Finished Jun 11 12:36:20 PM PDT 24
Peak memory 210940 kb
Host smart-c25b7ec0-28a3-4266-aca1-997b743c5326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484028315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2484028315
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3761575557
Short name T162
Test name
Test status
Simulation time 7502662258 ps
CPU time 15.05 seconds
Started Jun 11 12:36:11 PM PDT 24
Finished Jun 11 12:36:27 PM PDT 24
Peak memory 214020 kb
Host smart-884fb48d-bd69-4c57-818e-584c6ae53094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761575557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3761575557
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4057109607
Short name T127
Test name
Test status
Simulation time 713351561 ps
CPU time 9.14 seconds
Started Jun 11 12:36:10 PM PDT 24
Finished Jun 11 12:36:21 PM PDT 24
Peak memory 210740 kb
Host smart-c8d18451-d46e-4746-a6fc-3b28b86e0da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057109607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4057109607
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3436432147
Short name T150
Test name
Test status
Simulation time 1220501694 ps
CPU time 11.85 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:34 PM PDT 24
Peak memory 210744 kb
Host smart-5ff78fe8-5229-4d65-8126-f9b749c60972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436432147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3436432147
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1455085462
Short name T242
Test name
Test status
Simulation time 7080715768 ps
CPU time 119.27 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:38:19 PM PDT 24
Peak memory 233992 kb
Host smart-bd079ef9-a54e-45e9-816e-0c48bc7e9744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455085462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1455085462
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4160027054
Short name T296
Test name
Test status
Simulation time 4783778141 ps
CPU time 23.32 seconds
Started Jun 11 12:36:17 PM PDT 24
Finished Jun 11 12:36:42 PM PDT 24
Peak memory 211976 kb
Host smart-83b8a250-7078-46ee-a71d-e0f52854459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160027054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4160027054
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2661688290
Short name T277
Test name
Test status
Simulation time 4550692046 ps
CPU time 11.18 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:32 PM PDT 24
Peak memory 211008 kb
Host smart-76bd66b5-dcaf-4fb9-9a83-7179861bcdc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661688290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2661688290
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3031371074
Short name T12
Test name
Test status
Simulation time 6103653713 ps
CPU time 31.11 seconds
Started Jun 11 12:36:14 PM PDT 24
Finished Jun 11 12:36:46 PM PDT 24
Peak memory 214060 kb
Host smart-07d8aba7-d3ab-43d3-89e6-91c3d2215ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031371074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3031371074
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.676503378
Short name T218
Test name
Test status
Simulation time 1973728490 ps
CPU time 15.7 seconds
Started Jun 11 12:36:17 PM PDT 24
Finished Jun 11 12:36:34 PM PDT 24
Peak memory 210760 kb
Host smart-8edaf00f-651b-4cda-bb11-5d5c14739d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676503378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.676503378
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1905969578
Short name T238
Test name
Test status
Simulation time 87701989474 ps
CPU time 217.98 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:39:59 PM PDT 24
Peak memory 237460 kb
Host smart-85b360b0-663b-4480-acd0-5b8cd566a54d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905969578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1905969578
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1356516505
Short name T225
Test name
Test status
Simulation time 2866319031 ps
CPU time 26.86 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:46 PM PDT 24
Peak memory 211560 kb
Host smart-dfd2a2e1-730b-4ca4-beb8-a75daab156bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356516505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1356516505
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1570057088
Short name T260
Test name
Test status
Simulation time 3858691918 ps
CPU time 16.67 seconds
Started Jun 11 12:36:16 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 210992 kb
Host smart-28bcd94d-e5bb-4d53-95d4-6c05718ae1be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570057088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1570057088
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4163478877
Short name T284
Test name
Test status
Simulation time 4982960756 ps
CPU time 18.49 seconds
Started Jun 11 12:36:14 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 213360 kb
Host smart-8c49595f-7743-4437-a663-752c715628be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163478877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4163478877
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2300891788
Short name T137
Test name
Test status
Simulation time 12881123143 ps
CPU time 34.53 seconds
Started Jun 11 12:36:16 PM PDT 24
Finished Jun 11 12:36:52 PM PDT 24
Peak memory 212916 kb
Host smart-050cda2a-53e7-4ce7-b5ef-6a633163b845
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300891788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2300891788
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.620355836
Short name T45
Test name
Test status
Simulation time 21906958687 ps
CPU time 878.06 seconds
Started Jun 11 12:36:14 PM PDT 24
Finished Jun 11 12:50:53 PM PDT 24
Peak memory 235480 kb
Host smart-0f88fdf7-2b96-440e-aa89-328ce298cd38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620355836 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.620355836
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1246893692
Short name T164
Test name
Test status
Simulation time 333786083 ps
CPU time 4.17 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:23 PM PDT 24
Peak memory 210796 kb
Host smart-2af69943-39d1-4a6c-bf28-5a855c36e6c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246893692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1246893692
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1415401152
Short name T140
Test name
Test status
Simulation time 20346019096 ps
CPU time 219.4 seconds
Started Jun 11 12:36:22 PM PDT 24
Finished Jun 11 12:40:04 PM PDT 24
Peak memory 237800 kb
Host smart-afb05c98-4a1c-4625-b1d7-6f29105fffdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415401152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1415401152
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2409142974
Short name T139
Test name
Test status
Simulation time 7638707241 ps
CPU time 32.39 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:54 PM PDT 24
Peak memory 212124 kb
Host smart-df2b0eb2-3916-4234-9cf2-30de7d87478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409142974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2409142974
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2404381249
Short name T151
Test name
Test status
Simulation time 7318761217 ps
CPU time 16.27 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:38 PM PDT 24
Peak memory 211052 kb
Host smart-462c677b-689c-46c4-bc2d-d9b35152a8e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404381249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2404381249
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1127679306
Short name T190
Test name
Test status
Simulation time 15752716350 ps
CPU time 37.67 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:36:57 PM PDT 24
Peak memory 214084 kb
Host smart-a5c9bb9b-2335-470a-9a53-67b68918c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127679306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1127679306
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3196481545
Short name T194
Test name
Test status
Simulation time 5678499127 ps
CPU time 60.05 seconds
Started Jun 11 12:36:17 PM PDT 24
Finished Jun 11 12:37:18 PM PDT 24
Peak memory 216468 kb
Host smart-b052e57a-88a9-4a5c-ab26-04d9128fbec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196481545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3196481545
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2861377719
Short name T23
Test name
Test status
Simulation time 44800517805 ps
CPU time 1398.98 seconds
Started Jun 11 12:36:22 PM PDT 24
Finished Jun 11 12:59:44 PM PDT 24
Peak memory 232624 kb
Host smart-3d8d6af0-61dd-488c-b1a6-2f05e5f83fa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861377719 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2861377719
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.186181802
Short name T295
Test name
Test status
Simulation time 8372041675 ps
CPU time 16.48 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:39 PM PDT 24
Peak memory 210892 kb
Host smart-fd9e1956-57dc-45d1-a4b9-5712182d3b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186181802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.186181802
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3023339189
Short name T355
Test name
Test status
Simulation time 50493055710 ps
CPU time 236.37 seconds
Started Jun 11 12:36:21 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 239856 kb
Host smart-f3ca9edc-c117-4b80-b37a-584a1f9404e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023339189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3023339189
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.24926492
Short name T122
Test name
Test status
Simulation time 9954837416 ps
CPU time 23.91 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:45 PM PDT 24
Peak memory 212016 kb
Host smart-b3327c70-daeb-4918-bb62-3977a0eb4d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24926492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.24926492
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.493182067
Short name T121
Test name
Test status
Simulation time 4952096257 ps
CPU time 13.18 seconds
Started Jun 11 12:36:14 PM PDT 24
Finished Jun 11 12:36:28 PM PDT 24
Peak memory 211048 kb
Host smart-14448031-304a-45d9-af4b-771561c940e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=493182067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.493182067
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2207705135
Short name T239
Test name
Test status
Simulation time 33054877760 ps
CPU time 25.38 seconds
Started Jun 11 12:36:19 PM PDT 24
Finished Jun 11 12:36:46 PM PDT 24
Peak memory 213756 kb
Host smart-e4bc6399-b8bb-4438-85ce-4606acce8609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207705135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2207705135
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3872773145
Short name T167
Test name
Test status
Simulation time 373075359 ps
CPU time 11.43 seconds
Started Jun 11 12:36:20 PM PDT 24
Finished Jun 11 12:36:33 PM PDT 24
Peak memory 213656 kb
Host smart-f8ce5cde-0f74-4c1d-83c1-73f89e8a197b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872773145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3872773145
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3268391834
Short name T43
Test name
Test status
Simulation time 29547465985 ps
CPU time 1135.8 seconds
Started Jun 11 12:36:18 PM PDT 24
Finished Jun 11 12:55:15 PM PDT 24
Peak memory 230448 kb
Host smart-4db3c114-6371-4bf2-b3b0-134c86a2ff96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268391834 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3268391834
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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