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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 91.99 97.72 100.00 98.62 97.45 98.37


Total test records in report: 461
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T307 /workspace/coverage/default/6.rom_ctrl_smoke.2521254207 Jun 13 01:19:51 PM PDT 24 Jun 13 01:20:03 PM PDT 24 192358677 ps
T308 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2539363474 Jun 13 01:21:41 PM PDT 24 Jun 13 01:21:56 PM PDT 24 1597566957 ps
T309 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3870428042 Jun 13 01:20:00 PM PDT 24 Jun 13 01:20:13 PM PDT 24 885089601 ps
T310 /workspace/coverage/default/38.rom_ctrl_alert_test.1798167125 Jun 13 01:21:43 PM PDT 24 Jun 13 01:21:48 PM PDT 24 88061395 ps
T27 /workspace/coverage/default/0.rom_ctrl_sec_cm.1329489540 Jun 13 01:19:41 PM PDT 24 Jun 13 01:21:31 PM PDT 24 6846437654 ps
T311 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.799282005 Jun 13 01:19:44 PM PDT 24 Jun 13 01:20:16 PM PDT 24 15562170302 ps
T312 /workspace/coverage/default/6.rom_ctrl_stress_all.433202133 Jun 13 01:19:50 PM PDT 24 Jun 13 01:21:04 PM PDT 24 13094058975 ps
T313 /workspace/coverage/default/31.rom_ctrl_stress_all.1883107836 Jun 13 01:21:17 PM PDT 24 Jun 13 01:22:03 PM PDT 24 4836777221 ps
T314 /workspace/coverage/default/40.rom_ctrl_stress_all.829305625 Jun 13 01:21:52 PM PDT 24 Jun 13 01:22:38 PM PDT 24 16610336195 ps
T315 /workspace/coverage/default/23.rom_ctrl_smoke.1718604071 Jun 13 01:20:58 PM PDT 24 Jun 13 01:21:30 PM PDT 24 2767179092 ps
T316 /workspace/coverage/default/42.rom_ctrl_alert_test.2439740245 Jun 13 01:21:58 PM PDT 24 Jun 13 01:22:13 PM PDT 24 1734616938 ps
T317 /workspace/coverage/default/3.rom_ctrl_alert_test.3446168201 Jun 13 01:19:50 PM PDT 24 Jun 13 01:20:06 PM PDT 24 23277829324 ps
T318 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1058243999 Jun 13 01:20:57 PM PDT 24 Jun 13 01:21:11 PM PDT 24 2214105261 ps
T319 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.565678033 Jun 13 01:21:28 PM PDT 24 Jun 13 01:27:34 PM PDT 24 81058378962 ps
T320 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2862649614 Jun 13 01:21:57 PM PDT 24 Jun 13 01:22:06 PM PDT 24 7005577502 ps
T321 /workspace/coverage/default/33.rom_ctrl_alert_test.539358311 Jun 13 01:21:25 PM PDT 24 Jun 13 01:21:34 PM PDT 24 3443214641 ps
T322 /workspace/coverage/default/45.rom_ctrl_alert_test.2201307351 Jun 13 01:22:06 PM PDT 24 Jun 13 01:22:20 PM PDT 24 3164530967 ps
T323 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1947348104 Jun 13 01:19:44 PM PDT 24 Jun 13 01:19:57 PM PDT 24 8245514670 ps
T324 /workspace/coverage/default/26.rom_ctrl_stress_all.3544707750 Jun 13 01:21:05 PM PDT 24 Jun 13 01:21:53 PM PDT 24 4491591756 ps
T325 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3846523911 Jun 13 01:20:36 PM PDT 24 Jun 13 01:25:42 PM PDT 24 66817045953 ps
T326 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3441353408 Jun 13 01:19:45 PM PDT 24 Jun 13 01:20:01 PM PDT 24 1807339684 ps
T327 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4150193881 Jun 13 01:20:13 PM PDT 24 Jun 13 01:20:25 PM PDT 24 253522550 ps
T328 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2292523923 Jun 13 01:20:20 PM PDT 24 Jun 13 01:23:44 PM PDT 24 23848588205 ps
T329 /workspace/coverage/default/45.rom_ctrl_stress_all.147604261 Jun 13 01:22:06 PM PDT 24 Jun 13 01:22:42 PM PDT 24 15856964259 ps
T330 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1900114978 Jun 13 01:20:49 PM PDT 24 Jun 13 01:21:03 PM PDT 24 7315023033 ps
T331 /workspace/coverage/default/21.rom_ctrl_alert_test.3308427499 Jun 13 01:20:50 PM PDT 24 Jun 13 01:21:06 PM PDT 24 1795641543 ps
T332 /workspace/coverage/default/42.rom_ctrl_smoke.548669113 Jun 13 01:21:57 PM PDT 24 Jun 13 01:22:08 PM PDT 24 1064869070 ps
T333 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3129565539 Jun 13 01:20:50 PM PDT 24 Jun 13 01:21:16 PM PDT 24 2381461851 ps
T334 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3241643549 Jun 13 01:21:09 PM PDT 24 Jun 13 01:21:16 PM PDT 24 564595543 ps
T335 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.441567661 Jun 13 01:21:05 PM PDT 24 Jun 13 01:24:33 PM PDT 24 78418554019 ps
T336 /workspace/coverage/default/19.rom_ctrl_stress_all.310116874 Jun 13 01:20:52 PM PDT 24 Jun 13 01:21:48 PM PDT 24 20596632296 ps
T337 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4173803229 Jun 13 01:20:28 PM PDT 24 Jun 13 01:25:28 PM PDT 24 25947025751 ps
T338 /workspace/coverage/default/24.rom_ctrl_smoke.3338252399 Jun 13 01:20:58 PM PDT 24 Jun 13 01:21:32 PM PDT 24 4005917825 ps
T339 /workspace/coverage/default/44.rom_ctrl_smoke.1751426608 Jun 13 01:21:56 PM PDT 24 Jun 13 01:22:07 PM PDT 24 710654325 ps
T340 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2253523215 Jun 13 01:21:13 PM PDT 24 Jun 13 01:21:23 PM PDT 24 348144577 ps
T341 /workspace/coverage/default/8.rom_ctrl_alert_test.3675269523 Jun 13 01:20:06 PM PDT 24 Jun 13 01:20:17 PM PDT 24 903437436 ps
T342 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4105251163 Jun 13 01:20:12 PM PDT 24 Jun 13 01:20:26 PM PDT 24 1038146085 ps
T343 /workspace/coverage/default/47.rom_ctrl_alert_test.3167701576 Jun 13 01:22:08 PM PDT 24 Jun 13 01:22:26 PM PDT 24 4162668832 ps
T344 /workspace/coverage/default/4.rom_ctrl_alert_test.805263420 Jun 13 01:19:50 PM PDT 24 Jun 13 01:19:59 PM PDT 24 4869517200 ps
T345 /workspace/coverage/default/28.rom_ctrl_alert_test.338580821 Jun 13 01:21:13 PM PDT 24 Jun 13 01:21:20 PM PDT 24 859552361 ps
T346 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1581742962 Jun 13 01:21:05 PM PDT 24 Jun 13 01:21:18 PM PDT 24 8860476747 ps
T28 /workspace/coverage/default/1.rom_ctrl_sec_cm.759194729 Jun 13 01:19:44 PM PDT 24 Jun 13 01:21:35 PM PDT 24 4177753541 ps
T347 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3643528541 Jun 13 01:19:53 PM PDT 24 Jun 13 01:20:21 PM PDT 24 3099368300 ps
T348 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1444274177 Jun 13 01:22:08 PM PDT 24 Jun 13 01:22:23 PM PDT 24 2061331695 ps
T349 /workspace/coverage/default/43.rom_ctrl_alert_test.1367580882 Jun 13 01:21:56 PM PDT 24 Jun 13 01:22:10 PM PDT 24 2931498298 ps
T350 /workspace/coverage/default/13.rom_ctrl_smoke.3722892139 Jun 13 01:20:27 PM PDT 24 Jun 13 01:20:55 PM PDT 24 4860886540 ps
T351 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.6131059 Jun 13 01:21:44 PM PDT 24 Jun 13 01:22:15 PM PDT 24 3621760058 ps
T352 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2703701940 Jun 13 01:22:07 PM PDT 24 Jun 13 01:22:22 PM PDT 24 1685249249 ps
T353 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1040736211 Jun 13 01:20:35 PM PDT 24 Jun 13 01:21:06 PM PDT 24 13408910225 ps
T354 /workspace/coverage/default/20.rom_ctrl_stress_all.70015204 Jun 13 01:20:42 PM PDT 24 Jun 13 01:20:57 PM PDT 24 204759368 ps
T355 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3982032292 Jun 13 01:21:23 PM PDT 24 Jun 13 01:21:29 PM PDT 24 311763839 ps
T356 /workspace/coverage/default/11.rom_ctrl_alert_test.3737844870 Jun 13 01:20:21 PM PDT 24 Jun 13 01:20:31 PM PDT 24 693632040 ps
T357 /workspace/coverage/default/3.rom_ctrl_smoke.3418268610 Jun 13 01:19:45 PM PDT 24 Jun 13 01:20:13 PM PDT 24 11175292575 ps
T358 /workspace/coverage/default/21.rom_ctrl_smoke.1087247306 Jun 13 01:20:51 PM PDT 24 Jun 13 01:21:02 PM PDT 24 193239560 ps
T359 /workspace/coverage/default/33.rom_ctrl_smoke.2565500066 Jun 13 01:21:23 PM PDT 24 Jun 13 01:22:04 PM PDT 24 17006684705 ps
T360 /workspace/coverage/default/43.rom_ctrl_smoke.1243393802 Jun 13 01:21:58 PM PDT 24 Jun 13 01:22:28 PM PDT 24 2761863473 ps
T361 /workspace/coverage/default/3.rom_ctrl_stress_all.1040963892 Jun 13 01:19:45 PM PDT 24 Jun 13 01:20:16 PM PDT 24 2469129510 ps
T362 /workspace/coverage/default/49.rom_ctrl_smoke.3611003476 Jun 13 01:22:09 PM PDT 24 Jun 13 01:22:48 PM PDT 24 4188844889 ps
T363 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2703338918 Jun 13 01:20:56 PM PDT 24 Jun 13 01:22:17 PM PDT 24 1233130998 ps
T364 /workspace/coverage/default/19.rom_ctrl_smoke.1372694600 Jun 13 01:20:44 PM PDT 24 Jun 13 01:21:06 PM PDT 24 1732564063 ps
T365 /workspace/coverage/default/6.rom_ctrl_alert_test.407378245 Jun 13 01:19:58 PM PDT 24 Jun 13 01:20:04 PM PDT 24 88853545 ps
T366 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2415804126 Jun 13 01:21:57 PM PDT 24 Jun 13 01:22:15 PM PDT 24 7728433760 ps
T367 /workspace/coverage/default/35.rom_ctrl_smoke.2134196185 Jun 13 01:21:31 PM PDT 24 Jun 13 01:21:42 PM PDT 24 405127541 ps
T368 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.290046825 Jun 13 01:19:51 PM PDT 24 Jun 13 01:20:05 PM PDT 24 2428448640 ps
T369 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3085603122 Jun 13 01:20:19 PM PDT 24 Jun 13 01:20:53 PM PDT 24 20680269354 ps
T370 /workspace/coverage/default/28.rom_ctrl_smoke.363082233 Jun 13 01:21:05 PM PDT 24 Jun 13 01:21:37 PM PDT 24 18149389973 ps
T57 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1216213950 Jun 13 01:19:14 PM PDT 24 Jun 13 01:19:24 PM PDT 24 652784935 ps
T58 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.206083979 Jun 13 01:18:51 PM PDT 24 Jun 13 01:18:56 PM PDT 24 348203284 ps
T59 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.113775254 Jun 13 01:18:28 PM PDT 24 Jun 13 01:18:39 PM PDT 24 774868468 ps
T101 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.719259676 Jun 13 01:19:20 PM PDT 24 Jun 13 01:19:39 PM PDT 24 733660085 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.207730585 Jun 13 01:18:22 PM PDT 24 Jun 13 01:18:33 PM PDT 24 1188994295 ps
T107 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.303101221 Jun 13 01:18:44 PM PDT 24 Jun 13 01:18:54 PM PDT 24 118637329 ps
T372 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1422362260 Jun 13 01:19:22 PM PDT 24 Jun 13 01:19:31 PM PDT 24 2523244707 ps
T54 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1853240929 Jun 13 01:18:45 PM PDT 24 Jun 13 01:20:03 PM PDT 24 1945739505 ps
T373 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1462791529 Jun 13 01:19:41 PM PDT 24 Jun 13 01:19:55 PM PDT 24 4184952118 ps
T374 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2407731290 Jun 13 01:19:29 PM PDT 24 Jun 13 01:19:47 PM PDT 24 2257111726 ps
T375 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3734276995 Jun 13 01:19:07 PM PDT 24 Jun 13 01:19:24 PM PDT 24 1826056507 ps
T102 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1889578243 Jun 13 01:18:23 PM PDT 24 Jun 13 01:18:28 PM PDT 24 346950382 ps
T103 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1484625229 Jun 13 01:19:40 PM PDT 24 Jun 13 01:19:57 PM PDT 24 8479155356 ps
T376 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3873629578 Jun 13 01:19:12 PM PDT 24 Jun 13 01:19:23 PM PDT 24 4280716035 ps
T377 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.287900127 Jun 13 01:19:30 PM PDT 24 Jun 13 01:19:42 PM PDT 24 4425909204 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.9920057 Jun 13 01:18:46 PM PDT 24 Jun 13 01:18:57 PM PDT 24 421904910 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.795820280 Jun 13 01:18:31 PM PDT 24 Jun 13 01:18:42 PM PDT 24 1822323527 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.457185646 Jun 13 01:18:44 PM PDT 24 Jun 13 01:18:50 PM PDT 24 1027256505 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2689154049 Jun 13 01:18:39 PM PDT 24 Jun 13 01:18:48 PM PDT 24 783396268 ps
T55 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3935250500 Jun 13 01:19:39 PM PDT 24 Jun 13 01:20:21 PM PDT 24 1198415080 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.480936028 Jun 13 01:19:05 PM PDT 24 Jun 13 01:19:10 PM PDT 24 94672033 ps
T383 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.225218470 Jun 13 01:18:51 PM PDT 24 Jun 13 01:18:56 PM PDT 24 85645317 ps
T104 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3940384594 Jun 13 01:19:28 PM PDT 24 Jun 13 01:19:43 PM PDT 24 10399949931 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.909248841 Jun 13 01:18:53 PM PDT 24 Jun 13 01:19:11 PM PDT 24 11049433587 ps
T62 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2231986271 Jun 13 01:18:53 PM PDT 24 Jun 13 01:19:01 PM PDT 24 792354518 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.611314104 Jun 13 01:18:53 PM PDT 24 Jun 13 01:18:59 PM PDT 24 211677253 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1075080442 Jun 13 01:18:32 PM PDT 24 Jun 13 01:18:46 PM PDT 24 7048900954 ps
T63 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2422288986 Jun 13 01:18:31 PM PDT 24 Jun 13 01:18:44 PM PDT 24 6179150675 ps
T105 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1377017331 Jun 13 01:18:30 PM PDT 24 Jun 13 01:19:12 PM PDT 24 34488240592 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.546795378 Jun 13 01:19:24 PM PDT 24 Jun 13 01:19:35 PM PDT 24 873238789 ps
T64 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.525513470 Jun 13 01:19:21 PM PDT 24 Jun 13 01:19:28 PM PDT 24 300337338 ps
T388 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1583820282 Jun 13 01:18:52 PM PDT 24 Jun 13 01:19:10 PM PDT 24 6725054512 ps
T65 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2706894451 Jun 13 01:19:41 PM PDT 24 Jun 13 01:19:48 PM PDT 24 1030045659 ps
T66 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1709508843 Jun 13 01:19:13 PM PDT 24 Jun 13 01:19:23 PM PDT 24 839886065 ps
T67 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.166010040 Jun 13 01:19:13 PM PDT 24 Jun 13 01:19:29 PM PDT 24 7533835523 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3646536750 Jun 13 01:18:52 PM PDT 24 Jun 13 01:19:09 PM PDT 24 4242715873 ps
T95 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3461590074 Jun 13 01:19:42 PM PDT 24 Jun 13 01:20:42 PM PDT 24 14070882086 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.534565101 Jun 13 01:18:48 PM PDT 24 Jun 13 01:18:56 PM PDT 24 613957570 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1708208007 Jun 13 01:18:45 PM PDT 24 Jun 13 01:18:50 PM PDT 24 347590917 ps
T56 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1223634583 Jun 13 01:18:24 PM PDT 24 Jun 13 01:19:08 PM PDT 24 6505434743 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2319939867 Jun 13 01:18:23 PM PDT 24 Jun 13 01:18:28 PM PDT 24 1383922397 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2541187206 Jun 13 01:18:58 PM PDT 24 Jun 13 01:19:20 PM PDT 24 2040233623 ps
T108 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1760392902 Jun 13 01:19:30 PM PDT 24 Jun 13 01:20:49 PM PDT 24 3718410800 ps
T96 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.525240629 Jun 13 01:19:05 PM PDT 24 Jun 13 01:19:16 PM PDT 24 638450888 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.619744708 Jun 13 01:18:47 PM PDT 24 Jun 13 01:19:00 PM PDT 24 5442834899 ps
T97 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2662642342 Jun 13 01:18:32 PM PDT 24 Jun 13 01:18:44 PM PDT 24 4970721333 ps
T98 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3540821776 Jun 13 01:19:21 PM PDT 24 Jun 13 01:19:28 PM PDT 24 1309469734 ps
T99 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1759242387 Jun 13 01:18:28 PM PDT 24 Jun 13 01:18:36 PM PDT 24 2379716679 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.375624523 Jun 13 01:18:40 PM PDT 24 Jun 13 01:18:54 PM PDT 24 1617257420 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.972688735 Jun 13 01:18:24 PM PDT 24 Jun 13 01:18:41 PM PDT 24 24716712654 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3925227850 Jun 13 01:19:06 PM PDT 24 Jun 13 01:19:17 PM PDT 24 850553888 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1256917726 Jun 13 01:18:51 PM PDT 24 Jun 13 01:19:04 PM PDT 24 2482470042 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1331037274 Jun 13 01:18:38 PM PDT 24 Jun 13 01:18:49 PM PDT 24 1152480587 ps
T73 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1254153872 Jun 13 01:19:06 PM PDT 24 Jun 13 01:19:13 PM PDT 24 89310145 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2481362975 Jun 13 01:19:13 PM PDT 24 Jun 13 01:19:56 PM PDT 24 2348722052 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.987065770 Jun 13 01:18:59 PM PDT 24 Jun 13 01:19:48 PM PDT 24 8588161446 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2812423442 Jun 13 01:19:06 PM PDT 24 Jun 13 01:19:18 PM PDT 24 851665284 ps
T399 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2939824934 Jun 13 01:19:40 PM PDT 24 Jun 13 01:19:47 PM PDT 24 174842180 ps
T106 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.371411026 Jun 13 01:19:30 PM PDT 24 Jun 13 01:20:11 PM PDT 24 3828937562 ps
T74 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3810282145 Jun 13 01:19:29 PM PDT 24 Jun 13 01:20:24 PM PDT 24 9295841652 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1674046133 Jun 13 01:19:29 PM PDT 24 Jun 13 01:19:47 PM PDT 24 2114554428 ps
T401 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1917735849 Jun 13 01:19:07 PM PDT 24 Jun 13 01:19:24 PM PDT 24 2870639017 ps
T402 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2690688635 Jun 13 01:19:13 PM PDT 24 Jun 13 01:19:24 PM PDT 24 1115478620 ps
T403 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3429820705 Jun 13 01:19:07 PM PDT 24 Jun 13 01:19:24 PM PDT 24 1802533646 ps
T404 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2223829465 Jun 13 01:19:27 PM PDT 24 Jun 13 01:19:42 PM PDT 24 3373401679 ps
T75 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3709188046 Jun 13 01:19:41 PM PDT 24 Jun 13 01:19:52 PM PDT 24 944633940 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1717387068 Jun 13 01:18:26 PM PDT 24 Jun 13 01:18:43 PM PDT 24 3852152385 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4114820150 Jun 13 01:19:13 PM PDT 24 Jun 13 01:19:58 PM PDT 24 8430730865 ps
T406 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3051478856 Jun 13 01:19:29 PM PDT 24 Jun 13 01:19:38 PM PDT 24 1523647461 ps
T407 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3890988420 Jun 13 01:19:24 PM PDT 24 Jun 13 01:19:36 PM PDT 24 550514276 ps
T408 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3734461502 Jun 13 01:19:23 PM PDT 24 Jun 13 01:19:40 PM PDT 24 8449592556 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3913968818 Jun 13 01:19:27 PM PDT 24 Jun 13 01:19:44 PM PDT 24 2018267613 ps
T118 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3899494798 Jun 13 01:18:24 PM PDT 24 Jun 13 01:19:02 PM PDT 24 1045118395 ps
T410 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3095285518 Jun 13 01:19:22 PM PDT 24 Jun 13 01:19:32 PM PDT 24 652716542 ps
T411 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.898466786 Jun 13 01:19:30 PM PDT 24 Jun 13 01:19:39 PM PDT 24 174164804 ps
T114 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3786043831 Jun 13 01:19:29 PM PDT 24 Jun 13 01:20:06 PM PDT 24 784608546 ps
T412 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4276716589 Jun 13 01:19:12 PM PDT 24 Jun 13 01:19:22 PM PDT 24 912667916 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3036045905 Jun 13 01:18:27 PM PDT 24 Jun 13 01:18:47 PM PDT 24 1980575936 ps
T414 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3198858052 Jun 13 01:19:20 PM PDT 24 Jun 13 01:19:25 PM PDT 24 362053922 ps
T415 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3636765800 Jun 13 01:19:14 PM PDT 24 Jun 13 01:19:34 PM PDT 24 367354510 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3179738605 Jun 13 01:18:39 PM PDT 24 Jun 13 01:18:51 PM PDT 24 3615087751 ps
T417 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4196128986 Jun 13 01:19:21 PM PDT 24 Jun 13 01:20:09 PM PDT 24 8026717813 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3372265988 Jun 13 01:18:47 PM PDT 24 Jun 13 01:18:58 PM PDT 24 984194133 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4030594160 Jun 13 01:18:26 PM PDT 24 Jun 13 01:18:30 PM PDT 24 333071179 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3010871159 Jun 13 01:18:32 PM PDT 24 Jun 13 01:18:43 PM PDT 24 6885541158 ps
T421 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2754972889 Jun 13 01:19:06 PM PDT 24 Jun 13 01:19:21 PM PDT 24 2982565183 ps
T422 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2172310347 Jun 13 01:18:52 PM PDT 24 Jun 13 01:19:02 PM PDT 24 2777165253 ps
T423 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4185347831 Jun 13 01:19:16 PM PDT 24 Jun 13 01:19:35 PM PDT 24 2019796897 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4224563077 Jun 13 01:19:27 PM PDT 24 Jun 13 01:19:39 PM PDT 24 1294264192 ps
T425 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1465869104 Jun 13 01:18:45 PM PDT 24 Jun 13 01:19:02 PM PDT 24 7136172658 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3579263974 Jun 13 01:18:54 PM PDT 24 Jun 13 01:19:09 PM PDT 24 1667301614 ps
T76 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1635342923 Jun 13 01:18:46 PM PDT 24 Jun 13 01:19:54 PM PDT 24 28169836082 ps
T77 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3327054489 Jun 13 01:19:04 PM PDT 24 Jun 13 01:19:45 PM PDT 24 15872751676 ps
T427 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1194644182 Jun 13 01:19:16 PM PDT 24 Jun 13 01:19:26 PM PDT 24 10867148657 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3666869844 Jun 13 01:18:23 PM PDT 24 Jun 13 01:19:04 PM PDT 24 12891983384 ps
T428 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.258185046 Jun 13 01:19:27 PM PDT 24 Jun 13 01:19:34 PM PDT 24 182338605 ps
T429 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4141532253 Jun 13 01:19:41 PM PDT 24 Jun 13 01:19:53 PM PDT 24 3423693896 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2932634914 Jun 13 01:18:40 PM PDT 24 Jun 13 01:18:53 PM PDT 24 2355691796 ps
T431 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.131949330 Jun 13 01:18:53 PM PDT 24 Jun 13 01:19:37 PM PDT 24 5045747763 ps
T432 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2103122789 Jun 13 01:18:57 PM PDT 24 Jun 13 01:19:53 PM PDT 24 11809331217 ps
T433 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1901207740 Jun 13 01:18:51 PM PDT 24 Jun 13 01:19:46 PM PDT 24 6586784064 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3739774226 Jun 13 01:18:24 PM PDT 24 Jun 13 01:18:41 PM PDT 24 8176708616 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3458301516 Jun 13 01:18:45 PM PDT 24 Jun 13 01:19:36 PM PDT 24 11341644496 ps
T436 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2794315002 Jun 13 01:19:27 PM PDT 24 Jun 13 01:19:38 PM PDT 24 2790052421 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3600005038 Jun 13 01:19:08 PM PDT 24 Jun 13 01:20:24 PM PDT 24 5469047806 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1844485395 Jun 13 01:19:05 PM PDT 24 Jun 13 01:19:54 PM PDT 24 4788058755 ps
T438 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1976828737 Jun 13 01:19:28 PM PDT 24 Jun 13 01:19:44 PM PDT 24 1719362930 ps
T119 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.246512297 Jun 13 01:18:45 PM PDT 24 Jun 13 01:19:30 PM PDT 24 5238157930 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3293186784 Jun 13 01:19:41 PM PDT 24 Jun 13 01:19:58 PM PDT 24 2088566374 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.625375140 Jun 13 01:18:28 PM PDT 24 Jun 13 01:18:36 PM PDT 24 1604933475 ps
T116 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.821168878 Jun 13 01:19:24 PM PDT 24 Jun 13 01:20:37 PM PDT 24 3995697384 ps
T80 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1345692392 Jun 13 01:19:29 PM PDT 24 Jun 13 01:19:46 PM PDT 24 4316359158 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2940807165 Jun 13 01:18:24 PM PDT 24 Jun 13 01:18:28 PM PDT 24 379058263 ps
T442 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2876277824 Jun 13 01:19:40 PM PDT 24 Jun 13 01:19:47 PM PDT 24 1683687806 ps
T443 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1856250458 Jun 13 01:19:21 PM PDT 24 Jun 13 01:20:04 PM PDT 24 21081463154 ps
T79 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.634487971 Jun 13 01:18:31 PM PDT 24 Jun 13 01:18:48 PM PDT 24 2051590416 ps
T86 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.725818954 Jun 13 01:19:28 PM PDT 24 Jun 13 01:19:38 PM PDT 24 3702901300 ps
T444 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4028631838 Jun 13 01:19:41 PM PDT 24 Jun 13 01:19:49 PM PDT 24 168504691 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2407686728 Jun 13 01:18:45 PM PDT 24 Jun 13 01:18:59 PM PDT 24 3358443261 ps
T117 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1026285928 Jun 13 01:19:27 PM PDT 24 Jun 13 01:20:38 PM PDT 24 877493892 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.535570533 Jun 13 01:18:45 PM PDT 24 Jun 13 01:19:04 PM PDT 24 26156828585 ps
T82 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.222719921 Jun 13 01:19:14 PM PDT 24 Jun 13 01:19:47 PM PDT 24 9700676790 ps
T446 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4100569334 Jun 13 01:19:07 PM PDT 24 Jun 13 01:19:18 PM PDT 24 3260566577 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1380221464 Jun 13 01:18:23 PM PDT 24 Jun 13 01:19:45 PM PDT 24 39452384382 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.253459725 Jun 13 01:19:28 PM PDT 24 Jun 13 01:19:41 PM PDT 24 1238505354 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1780548830 Jun 13 01:19:28 PM PDT 24 Jun 13 01:20:11 PM PDT 24 15336956779 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3855125446 Jun 13 01:18:45 PM PDT 24 Jun 13 01:18:56 PM PDT 24 4117891554 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1342966269 Jun 13 01:19:41 PM PDT 24 Jun 13 01:19:59 PM PDT 24 6581299259 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2267098888 Jun 13 01:18:25 PM PDT 24 Jun 13 01:18:35 PM PDT 24 507131697 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3078538977 Jun 13 01:19:40 PM PDT 24 Jun 13 01:20:23 PM PDT 24 6975384141 ps
T452 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3922918433 Jun 13 01:19:24 PM PDT 24 Jun 13 01:19:35 PM PDT 24 1101145646 ps
T453 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.829425000 Jun 13 01:19:05 PM PDT 24 Jun 13 01:19:21 PM PDT 24 1173294110 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3899908940 Jun 13 01:19:28 PM PDT 24 Jun 13 01:20:13 PM PDT 24 8760090719 ps
T84 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2596404137 Jun 13 01:19:08 PM PDT 24 Jun 13 01:20:02 PM PDT 24 7289118355 ps
T85 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3182312662 Jun 13 01:19:40 PM PDT 24 Jun 13 01:20:46 PM PDT 24 23848823133 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3644148304 Jun 13 01:18:45 PM PDT 24 Jun 13 01:18:57 PM PDT 24 2135878785 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.50117831 Jun 13 01:18:53 PM PDT 24 Jun 13 01:19:09 PM PDT 24 5136077498 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3171577051 Jun 13 01:18:45 PM PDT 24 Jun 13 01:19:00 PM PDT 24 3171460696 ps
T457 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1413991232 Jun 13 01:19:25 PM PDT 24 Jun 13 01:19:59 PM PDT 24 2379619498 ps
T458 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1878145670 Jun 13 01:19:40 PM PDT 24 Jun 13 01:19:57 PM PDT 24 2148691063 ps
T459 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.190597003 Jun 13 01:19:21 PM PDT 24 Jun 13 01:19:57 PM PDT 24 164466577 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2658977070 Jun 13 01:18:39 PM PDT 24 Jun 13 01:18:47 PM PDT 24 1336929322 ps
T460 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3311824503 Jun 13 01:18:39 PM PDT 24 Jun 13 01:19:17 PM PDT 24 577101053 ps
T112 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1607533239 Jun 13 01:19:04 PM PDT 24 Jun 13 01:19:47 PM PDT 24 1191061619 ps
T461 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.980753749 Jun 13 01:19:06 PM PDT 24 Jun 13 01:19:29 PM PDT 24 4005441397 ps

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.74043139
Short name T10
Test name
Test status
Simulation time 21347268559 ps
CPU time 260.87 seconds
Started Jun 13 01:20:05 PM PDT 24
Finished Jun 13 01:24:27 PM PDT 24
Peak memory 238184 kb
Host smart-19086a8e-69a6-443b-8b5c-6604894c1888
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74043139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_cor
rupt_sig_fatal_chk.74043139
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2807839514
Short name T13
Test name
Test status
Simulation time 59534474764 ps
CPU time 2774.66 seconds
Started Jun 13 01:21:00 PM PDT 24
Finished Jun 13 02:07:15 PM PDT 24
Peak memory 235632 kb
Host smart-af061008-43f3-4a87-a288-7e1028724433
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807839514 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2807839514
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2261939883
Short name T16
Test name
Test status
Simulation time 50780493876 ps
CPU time 69.24 seconds
Started Jun 13 01:20:27 PM PDT 24
Finished Jun 13 01:21:37 PM PDT 24
Peak memory 217128 kb
Host smart-1e2c287e-3691-4ab2-95e2-9dd25878e0f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261939883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2261939883
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4248088108
Short name T124
Test name
Test status
Simulation time 16602327405 ps
CPU time 294.32 seconds
Started Jun 13 01:21:33 PM PDT 24
Finished Jun 13 01:26:28 PM PDT 24
Peak memory 236852 kb
Host smart-c0a16e0f-b51b-4771-bba8-d43a6294d667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248088108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4248088108
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1760392902
Short name T108
Test name
Test status
Simulation time 3718410800 ps
CPU time 78.02 seconds
Started Jun 13 01:19:30 PM PDT 24
Finished Jun 13 01:20:49 PM PDT 24
Peak memory 211576 kb
Host smart-33304566-a252-4866-bace-d0f19cd92fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760392902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1760392902
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2345275324
Short name T283
Test name
Test status
Simulation time 1264955297 ps
CPU time 91.75 seconds
Started Jun 13 01:21:07 PM PDT 24
Finished Jun 13 01:22:39 PM PDT 24
Peak memory 236568 kb
Host smart-55c50260-0626-47f0-9293-3804fb555981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345275324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2345275324
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1875663401
Short name T5
Test name
Test status
Simulation time 1950615507 ps
CPU time 6.89 seconds
Started Jun 13 01:20:46 PM PDT 24
Finished Jun 13 01:20:54 PM PDT 24
Peak memory 211124 kb
Host smart-3d0d195f-8211-4882-8a28-8c445cbbf140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875663401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1875663401
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3032341660
Short name T24
Test name
Test status
Simulation time 707441387 ps
CPU time 109.45 seconds
Started Jun 13 01:19:55 PM PDT 24
Finished Jun 13 01:21:45 PM PDT 24
Peak memory 236468 kb
Host smart-b81fc406-12e7-429c-97d9-eeaa1bcab5e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032341660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3032341660
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.206083979
Short name T58
Test name
Test status
Simulation time 348203284 ps
CPU time 4.2 seconds
Started Jun 13 01:18:51 PM PDT 24
Finished Jun 13 01:18:56 PM PDT 24
Peak memory 211348 kb
Host smart-4b8e2ad3-3c36-453f-be0d-9bb467b1bd5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206083979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.206083979
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1026285928
Short name T117
Test name
Test status
Simulation time 877493892 ps
CPU time 70.71 seconds
Started Jun 13 01:19:27 PM PDT 24
Finished Jun 13 01:20:38 PM PDT 24
Peak memory 219808 kb
Host smart-8ab4a3ea-b0c5-46f2-b1de-54c4ede776c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026285928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1026285928
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1836188534
Short name T35
Test name
Test status
Simulation time 11219528373 ps
CPU time 27.04 seconds
Started Jun 13 01:19:46 PM PDT 24
Finished Jun 13 01:20:13 PM PDT 24
Peak memory 212140 kb
Host smart-effe9c14-28c0-4d36-9b5e-6f546c755b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836188534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1836188534
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2145358572
Short name T9
Test name
Test status
Simulation time 362997710 ps
CPU time 9.85 seconds
Started Jun 13 01:20:21 PM PDT 24
Finished Jun 13 01:20:31 PM PDT 24
Peak memory 211936 kb
Host smart-73246d4f-38eb-4d49-93e1-457949580ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145358572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2145358572
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.621910654
Short name T40
Test name
Test status
Simulation time 4352865278 ps
CPU time 22.55 seconds
Started Jun 13 01:20:44 PM PDT 24
Finished Jun 13 01:21:08 PM PDT 24
Peak memory 212176 kb
Host smart-27c5cd90-d3e6-4668-bb3f-06d26a77fd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621910654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.621910654
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.371411026
Short name T106
Test name
Test status
Simulation time 3828937562 ps
CPU time 39.75 seconds
Started Jun 13 01:19:30 PM PDT 24
Finished Jun 13 01:20:11 PM PDT 24
Peak memory 211548 kb
Host smart-8f47aab7-7731-420f-8784-7784efe89a06
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371411026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.371411026
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1607533239
Short name T112
Test name
Test status
Simulation time 1191061619 ps
CPU time 42.13 seconds
Started Jun 13 01:19:04 PM PDT 24
Finished Jun 13 01:19:47 PM PDT 24
Peak memory 212848 kb
Host smart-47cfdc18-ff57-4545-a771-74e7ef8af496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607533239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1607533239
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.246512297
Short name T119
Test name
Test status
Simulation time 5238157930 ps
CPU time 43.66 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:19:30 PM PDT 24
Peak memory 219644 kb
Host smart-311556b3-6291-46ae-ac75-62a1added5b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246512297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.246512297
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1759242387
Short name T99
Test name
Test status
Simulation time 2379716679 ps
CPU time 7.6 seconds
Started Jun 13 01:18:28 PM PDT 24
Finished Jun 13 01:18:36 PM PDT 24
Peak memory 219680 kb
Host smart-948b14c2-a19d-401f-a7d5-720a1bfbd4d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759242387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1759242387
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.634487971
Short name T79
Test name
Test status
Simulation time 2051590416 ps
CPU time 16.06 seconds
Started Jun 13 01:18:31 PM PDT 24
Finished Jun 13 01:18:48 PM PDT 24
Peak memory 219220 kb
Host smart-779c0f30-308e-4608-8209-eccb49e637dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634487971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.634487971
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2733819840
Short name T71
Test name
Test status
Simulation time 212726594 ps
CPU time 14.53 seconds
Started Jun 13 01:21:25 PM PDT 24
Finished Jun 13 01:21:40 PM PDT 24
Peak memory 213592 kb
Host smart-51412b85-b375-41c9-a85e-ed00f6d3c197
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733819840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2733819840
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2319939867
Short name T391
Test name
Test status
Simulation time 1383922397 ps
CPU time 4.29 seconds
Started Jun 13 01:18:23 PM PDT 24
Finished Jun 13 01:18:28 PM PDT 24
Peak memory 218116 kb
Host smart-de9cf721-5bd1-4e57-91f9-bd56cffc4659
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319939867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2319939867
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3739774226
Short name T434
Test name
Test status
Simulation time 8176708616 ps
CPU time 16.8 seconds
Started Jun 13 01:18:24 PM PDT 24
Finished Jun 13 01:18:41 PM PDT 24
Peak memory 219608 kb
Host smart-4903fe97-afb1-48c3-8c2e-538b3a8a4ef7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739774226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3739774226
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1717387068
Short name T405
Test name
Test status
Simulation time 3852152385 ps
CPU time 17.08 seconds
Started Jun 13 01:18:26 PM PDT 24
Finished Jun 13 01:18:43 PM PDT 24
Peak memory 219400 kb
Host smart-fd5404d6-ff65-47a8-a673-c08fe7fe6e10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717387068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1717387068
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.625375140
Short name T440
Test name
Test status
Simulation time 1604933475 ps
CPU time 7.16 seconds
Started Jun 13 01:18:28 PM PDT 24
Finished Jun 13 01:18:36 PM PDT 24
Peak memory 219648 kb
Host smart-37670131-259b-43fb-a892-4c6f7c37c3a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625375140 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.625375140
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1889578243
Short name T102
Test name
Test status
Simulation time 346950382 ps
CPU time 4.27 seconds
Started Jun 13 01:18:23 PM PDT 24
Finished Jun 13 01:18:28 PM PDT 24
Peak memory 211408 kb
Host smart-6636adf8-c458-4486-bbab-39766b9156d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889578243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1889578243
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.207730585
Short name T371
Test name
Test status
Simulation time 1188994295 ps
CPU time 10.9 seconds
Started Jun 13 01:18:22 PM PDT 24
Finished Jun 13 01:18:33 PM PDT 24
Peak memory 211252 kb
Host smart-d3f1bdfd-605f-4ece-848a-c1358faebcdd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207730585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.207730585
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2940807165
Short name T441
Test name
Test status
Simulation time 379058263 ps
CPU time 4.31 seconds
Started Jun 13 01:18:24 PM PDT 24
Finished Jun 13 01:18:28 PM PDT 24
Peak memory 211280 kb
Host smart-0797e8de-caf5-471a-bef4-bec27a349cc8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940807165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2940807165
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1380221464
Short name T83
Test name
Test status
Simulation time 39452384382 ps
CPU time 82.32 seconds
Started Jun 13 01:18:23 PM PDT 24
Finished Jun 13 01:19:45 PM PDT 24
Peak memory 211580 kb
Host smart-df310f38-c668-4c06-955b-c331c93d7166
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380221464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1380221464
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3036045905
Short name T413
Test name
Test status
Simulation time 1980575936 ps
CPU time 19.52 seconds
Started Jun 13 01:18:27 PM PDT 24
Finished Jun 13 01:18:47 PM PDT 24
Peak memory 219560 kb
Host smart-392b0648-3732-46d6-8c4e-dafae5e9a021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036045905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3036045905
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3899494798
Short name T118
Test name
Test status
Simulation time 1045118395 ps
CPU time 37.33 seconds
Started Jun 13 01:18:24 PM PDT 24
Finished Jun 13 01:19:02 PM PDT 24
Peak memory 212796 kb
Host smart-c1078585-2424-4e49-89ca-f9c98c9b3136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899494798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3899494798
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1075080442
Short name T386
Test name
Test status
Simulation time 7048900954 ps
CPU time 13.13 seconds
Started Jun 13 01:18:32 PM PDT 24
Finished Jun 13 01:18:46 PM PDT 24
Peak memory 211580 kb
Host smart-4ac57f32-b0e5-4cea-bd0e-957198be9f23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075080442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1075080442
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.113775254
Short name T59
Test name
Test status
Simulation time 774868468 ps
CPU time 10.74 seconds
Started Jun 13 01:18:28 PM PDT 24
Finished Jun 13 01:18:39 PM PDT 24
Peak memory 219568 kb
Host smart-3c00ed44-e584-422a-acef-18a2c9818bc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113775254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.113775254
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3010871159
Short name T420
Test name
Test status
Simulation time 6885541158 ps
CPU time 10.91 seconds
Started Jun 13 01:18:32 PM PDT 24
Finished Jun 13 01:18:43 PM PDT 24
Peak memory 219712 kb
Host smart-0c77b2e2-eb6f-4cd5-97e0-486fbaa01505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010871159 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3010871159
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2422288986
Short name T63
Test name
Test status
Simulation time 6179150675 ps
CPU time 12.41 seconds
Started Jun 13 01:18:31 PM PDT 24
Finished Jun 13 01:18:44 PM PDT 24
Peak memory 211512 kb
Host smart-285b3efd-5cb3-4315-8cf0-3b247c41f2a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422288986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2422288986
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4030594160
Short name T419
Test name
Test status
Simulation time 333071179 ps
CPU time 4.11 seconds
Started Jun 13 01:18:26 PM PDT 24
Finished Jun 13 01:18:30 PM PDT 24
Peak memory 211292 kb
Host smart-aab7e667-d872-4a87-a91b-335224a31723
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030594160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4030594160
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.972688735
Short name T395
Test name
Test status
Simulation time 24716712654 ps
CPU time 16.7 seconds
Started Jun 13 01:18:24 PM PDT 24
Finished Jun 13 01:18:41 PM PDT 24
Peak memory 211416 kb
Host smart-53944bbf-623e-421f-96f9-af6dfd865714
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972688735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
972688735
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3666869844
Short name T78
Test name
Test status
Simulation time 12891983384 ps
CPU time 40.61 seconds
Started Jun 13 01:18:23 PM PDT 24
Finished Jun 13 01:19:04 PM PDT 24
Peak memory 211560 kb
Host smart-5b43dd7a-8f39-48b2-b019-82f5e3af8d4e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666869844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3666869844
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2662642342
Short name T97
Test name
Test status
Simulation time 4970721333 ps
CPU time 11.64 seconds
Started Jun 13 01:18:32 PM PDT 24
Finished Jun 13 01:18:44 PM PDT 24
Peak memory 211592 kb
Host smart-1b36ec48-9d63-47b3-9f6c-9396d6089879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662642342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2662642342
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2267098888
Short name T451
Test name
Test status
Simulation time 507131697 ps
CPU time 8.67 seconds
Started Jun 13 01:18:25 PM PDT 24
Finished Jun 13 01:18:35 PM PDT 24
Peak memory 219584 kb
Host smart-bb9fe025-7eb4-4492-a54a-7d52d8188bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267098888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2267098888
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1223634583
Short name T56
Test name
Test status
Simulation time 6505434743 ps
CPU time 43.43 seconds
Started Jun 13 01:18:24 PM PDT 24
Finished Jun 13 01:19:08 PM PDT 24
Peak memory 212844 kb
Host smart-282db66c-83de-4c8a-a202-8b1dec5e5f17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223634583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1223634583
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3873629578
Short name T376
Test name
Test status
Simulation time 4280716035 ps
CPU time 10.38 seconds
Started Jun 13 01:19:12 PM PDT 24
Finished Jun 13 01:19:23 PM PDT 24
Peak memory 219656 kb
Host smart-e6fb0c22-32a8-4721-aa45-a176e10989be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873629578 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3873629578
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4276716589
Short name T412
Test name
Test status
Simulation time 912667916 ps
CPU time 9.03 seconds
Started Jun 13 01:19:12 PM PDT 24
Finished Jun 13 01:19:22 PM PDT 24
Peak memory 211420 kb
Host smart-4166c81d-c839-476e-86eb-cf38a84b0c1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276716589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4276716589
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3636765800
Short name T415
Test name
Test status
Simulation time 367354510 ps
CPU time 19.53 seconds
Started Jun 13 01:19:14 PM PDT 24
Finished Jun 13 01:19:34 PM PDT 24
Peak memory 211432 kb
Host smart-23b310e1-9b3c-475f-8b02-39dd4e466701
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636765800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3636765800
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1216213950
Short name T57
Test name
Test status
Simulation time 652784935 ps
CPU time 10.25 seconds
Started Jun 13 01:19:14 PM PDT 24
Finished Jun 13 01:19:24 PM PDT 24
Peak memory 219568 kb
Host smart-d1e6edc5-5db2-41ab-b1e3-9c4421e4779a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216213950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1216213950
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2690688635
Short name T402
Test name
Test status
Simulation time 1115478620 ps
CPU time 10.59 seconds
Started Jun 13 01:19:13 PM PDT 24
Finished Jun 13 01:19:24 PM PDT 24
Peak memory 219524 kb
Host smart-8eecda4d-f310-40a1-a3a4-edf9c76d17cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690688635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2690688635
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4114820150
Short name T110
Test name
Test status
Simulation time 8430730865 ps
CPU time 45.02 seconds
Started Jun 13 01:19:13 PM PDT 24
Finished Jun 13 01:19:58 PM PDT 24
Peak memory 212892 kb
Host smart-6346439b-07b9-4b79-8595-8d8134b96766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114820150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4114820150
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1422362260
Short name T372
Test name
Test status
Simulation time 2523244707 ps
CPU time 8.34 seconds
Started Jun 13 01:19:22 PM PDT 24
Finished Jun 13 01:19:31 PM PDT 24
Peak memory 212956 kb
Host smart-a48281a7-18b9-4aa3-8dd2-cc80610d0a8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422362260 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1422362260
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2223829465
Short name T404
Test name
Test status
Simulation time 3373401679 ps
CPU time 13.99 seconds
Started Jun 13 01:19:27 PM PDT 24
Finished Jun 13 01:19:42 PM PDT 24
Peak memory 219552 kb
Host smart-54421f90-ecc9-4ceb-b9db-7f7fa0f3a04a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223829465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2223829465
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.222719921
Short name T82
Test name
Test status
Simulation time 9700676790 ps
CPU time 32.62 seconds
Started Jun 13 01:19:14 PM PDT 24
Finished Jun 13 01:19:47 PM PDT 24
Peak memory 211544 kb
Host smart-06b69b29-c1ee-4fe4-82af-4118336c7133
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222719921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.222719921
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.525513470
Short name T64
Test name
Test status
Simulation time 300337338 ps
CPU time 6.38 seconds
Started Jun 13 01:19:21 PM PDT 24
Finished Jun 13 01:19:28 PM PDT 24
Peak memory 218900 kb
Host smart-21d63677-4ac5-4a52-86b5-af969eb009e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525513470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.525513470
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4185347831
Short name T423
Test name
Test status
Simulation time 2019796897 ps
CPU time 19.63 seconds
Started Jun 13 01:19:16 PM PDT 24
Finished Jun 13 01:19:35 PM PDT 24
Peak memory 219544 kb
Host smart-67b41ef7-b71c-46cf-ad2a-fec0c5062b41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185347831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4185347831
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4196128986
Short name T417
Test name
Test status
Simulation time 8026717813 ps
CPU time 47.12 seconds
Started Jun 13 01:19:21 PM PDT 24
Finished Jun 13 01:20:09 PM PDT 24
Peak memory 213264 kb
Host smart-82e2bff6-0b61-4852-9424-32853dea015a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196128986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4196128986
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.258185046
Short name T428
Test name
Test status
Simulation time 182338605 ps
CPU time 6.36 seconds
Started Jun 13 01:19:27 PM PDT 24
Finished Jun 13 01:19:34 PM PDT 24
Peak memory 219816 kb
Host smart-39b0a221-ae7d-45d1-acc2-311fe3b56502
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258185046 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.258185046
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3198858052
Short name T414
Test name
Test status
Simulation time 362053922 ps
CPU time 4.29 seconds
Started Jun 13 01:19:20 PM PDT 24
Finished Jun 13 01:19:25 PM PDT 24
Peak memory 211440 kb
Host smart-482a1abe-1456-49ae-a773-23ab131efee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198858052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3198858052
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1856250458
Short name T443
Test name
Test status
Simulation time 21081463154 ps
CPU time 41.74 seconds
Started Jun 13 01:19:21 PM PDT 24
Finished Jun 13 01:20:04 PM PDT 24
Peak memory 211564 kb
Host smart-9595bb24-6f79-4030-a860-a257bbe1400e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856250458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1856250458
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3540821776
Short name T98
Test name
Test status
Simulation time 1309469734 ps
CPU time 6.35 seconds
Started Jun 13 01:19:21 PM PDT 24
Finished Jun 13 01:19:28 PM PDT 24
Peak memory 219068 kb
Host smart-d58f5735-e881-42ac-a91b-661748acc6ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540821776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3540821776
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3734461502
Short name T408
Test name
Test status
Simulation time 8449592556 ps
CPU time 16.14 seconds
Started Jun 13 01:19:23 PM PDT 24
Finished Jun 13 01:19:40 PM PDT 24
Peak memory 219640 kb
Host smart-d542f047-efef-4fad-a88c-99342f4a4e73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734461502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3734461502
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4224563077
Short name T424
Test name
Test status
Simulation time 1294264192 ps
CPU time 12.1 seconds
Started Jun 13 01:19:27 PM PDT 24
Finished Jun 13 01:19:39 PM PDT 24
Peak memory 219832 kb
Host smart-2f95110b-3a73-4f09-9966-63daad94f5fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224563077 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4224563077
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3922918433
Short name T452
Test name
Test status
Simulation time 1101145646 ps
CPU time 10.49 seconds
Started Jun 13 01:19:24 PM PDT 24
Finished Jun 13 01:19:35 PM PDT 24
Peak memory 211368 kb
Host smart-f762c816-bd35-4558-80b5-4538623b1331
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922918433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3922918433
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.719259676
Short name T101
Test name
Test status
Simulation time 733660085 ps
CPU time 18.55 seconds
Started Jun 13 01:19:20 PM PDT 24
Finished Jun 13 01:19:39 PM PDT 24
Peak memory 211308 kb
Host smart-eed36d9d-3bc5-4eb5-bfa1-a9107554e2de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719259676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.719259676
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3095285518
Short name T410
Test name
Test status
Simulation time 652716542 ps
CPU time 9.06 seconds
Started Jun 13 01:19:22 PM PDT 24
Finished Jun 13 01:19:32 PM PDT 24
Peak memory 211452 kb
Host smart-ae53c293-110a-4e4c-b24d-8d2479a05187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095285518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3095285518
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.546795378
Short name T387
Test name
Test status
Simulation time 873238789 ps
CPU time 11.16 seconds
Started Jun 13 01:19:24 PM PDT 24
Finished Jun 13 01:19:35 PM PDT 24
Peak memory 219312 kb
Host smart-2f32c008-3672-41af-aca8-7886e205a167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546795378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.546795378
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.821168878
Short name T116
Test name
Test status
Simulation time 3995697384 ps
CPU time 72.74 seconds
Started Jun 13 01:19:24 PM PDT 24
Finished Jun 13 01:20:37 PM PDT 24
Peak memory 219720 kb
Host smart-c2f550c6-8f15-4a4a-bd55-25e49bc24ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821168878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.821168878
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1976828737
Short name T438
Test name
Test status
Simulation time 1719362930 ps
CPU time 14.59 seconds
Started Jun 13 01:19:28 PM PDT 24
Finished Jun 13 01:19:44 PM PDT 24
Peak memory 219636 kb
Host smart-0dc2e617-50bf-48ec-97f2-5dc66e4f00e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976828737 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1976828737
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3940384594
Short name T104
Test name
Test status
Simulation time 10399949931 ps
CPU time 13.69 seconds
Started Jun 13 01:19:28 PM PDT 24
Finished Jun 13 01:19:43 PM PDT 24
Peak memory 211508 kb
Host smart-6d6e974e-e289-4689-b0df-f1d978673e62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940384594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3940384594
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1413991232
Short name T457
Test name
Test status
Simulation time 2379619498 ps
CPU time 33.65 seconds
Started Jun 13 01:19:25 PM PDT 24
Finished Jun 13 01:19:59 PM PDT 24
Peak memory 218612 kb
Host smart-9cf58287-b865-4a65-8adf-76778ac79253
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413991232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1413991232
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3913968818
Short name T409
Test name
Test status
Simulation time 2018267613 ps
CPU time 15.84 seconds
Started Jun 13 01:19:27 PM PDT 24
Finished Jun 13 01:19:44 PM PDT 24
Peak memory 211472 kb
Host smart-49f2ad6e-0b97-4894-a410-1f60cbc8cf28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913968818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3913968818
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3890988420
Short name T407
Test name
Test status
Simulation time 550514276 ps
CPU time 12.01 seconds
Started Jun 13 01:19:24 PM PDT 24
Finished Jun 13 01:19:36 PM PDT 24
Peak memory 219232 kb
Host smart-d3054866-0553-4b27-ab0f-710e60276634
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890988420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3890988420
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.190597003
Short name T459
Test name
Test status
Simulation time 164466577 ps
CPU time 35.85 seconds
Started Jun 13 01:19:21 PM PDT 24
Finished Jun 13 01:19:57 PM PDT 24
Peak memory 219580 kb
Host smart-92cbdd6b-e116-4057-9a72-938c7a67d021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190597003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.190597003
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.253459725
Short name T447
Test name
Test status
Simulation time 1238505354 ps
CPU time 11.91 seconds
Started Jun 13 01:19:28 PM PDT 24
Finished Jun 13 01:19:41 PM PDT 24
Peak memory 219680 kb
Host smart-0c15e80e-a7f5-435f-a0fa-125772859823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253459725 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.253459725
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.725818954
Short name T86
Test name
Test status
Simulation time 3702901300 ps
CPU time 8.76 seconds
Started Jun 13 01:19:28 PM PDT 24
Finished Jun 13 01:19:38 PM PDT 24
Peak memory 219700 kb
Host smart-6f2b6aa6-c14a-4886-8479-e7f35e991adc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725818954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.725818954
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3810282145
Short name T74
Test name
Test status
Simulation time 9295841652 ps
CPU time 54.13 seconds
Started Jun 13 01:19:29 PM PDT 24
Finished Jun 13 01:20:24 PM PDT 24
Peak memory 211552 kb
Host smart-7762e09b-4ff2-4567-bf88-6158da2fffb1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810282145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3810282145
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3051478856
Short name T406
Test name
Test status
Simulation time 1523647461 ps
CPU time 8.69 seconds
Started Jun 13 01:19:29 PM PDT 24
Finished Jun 13 01:19:38 PM PDT 24
Peak memory 218644 kb
Host smart-de50e16a-0b86-44a3-874f-68a44fdd3032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051478856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3051478856
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.287900127
Short name T377
Test name
Test status
Simulation time 4425909204 ps
CPU time 11.13 seconds
Started Jun 13 01:19:30 PM PDT 24
Finished Jun 13 01:19:42 PM PDT 24
Peak memory 219688 kb
Host smart-4c2ed41c-3fd0-4877-9ca7-e27536eefece
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287900127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.287900127
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1780548830
Short name T448
Test name
Test status
Simulation time 15336956779 ps
CPU time 42.12 seconds
Started Jun 13 01:19:28 PM PDT 24
Finished Jun 13 01:20:11 PM PDT 24
Peak memory 213252 kb
Host smart-774b21d9-ad38-4d83-b006-47eaaef2f86b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780548830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1780548830
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1674046133
Short name T400
Test name
Test status
Simulation time 2114554428 ps
CPU time 16.83 seconds
Started Jun 13 01:19:29 PM PDT 24
Finished Jun 13 01:19:47 PM PDT 24
Peak memory 219576 kb
Host smart-d32f1f4d-bffa-443a-87e1-3550cd8a20e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674046133 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1674046133
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1345692392
Short name T80
Test name
Test status
Simulation time 4316359158 ps
CPU time 16.24 seconds
Started Jun 13 01:19:29 PM PDT 24
Finished Jun 13 01:19:46 PM PDT 24
Peak memory 211564 kb
Host smart-fa6df71a-fc7c-4116-9ab4-11945ae215e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345692392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1345692392
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3899908940
Short name T87
Test name
Test status
Simulation time 8760090719 ps
CPU time 44.5 seconds
Started Jun 13 01:19:28 PM PDT 24
Finished Jun 13 01:20:13 PM PDT 24
Peak memory 211532 kb
Host smart-70ac03ef-0c3a-4439-a3c8-053566d39b17
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899908940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3899908940
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2794315002
Short name T436
Test name
Test status
Simulation time 2790052421 ps
CPU time 10.21 seconds
Started Jun 13 01:19:27 PM PDT 24
Finished Jun 13 01:19:38 PM PDT 24
Peak memory 219700 kb
Host smart-60c025f6-7c44-4bca-999d-96583ea33442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794315002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2794315002
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2407731290
Short name T374
Test name
Test status
Simulation time 2257111726 ps
CPU time 16.53 seconds
Started Jun 13 01:19:29 PM PDT 24
Finished Jun 13 01:19:47 PM PDT 24
Peak memory 219676 kb
Host smart-aedcc893-b5bb-4bfb-a926-6e793c61d32f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407731290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2407731290
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1462791529
Short name T373
Test name
Test status
Simulation time 4184952118 ps
CPU time 13.54 seconds
Started Jun 13 01:19:41 PM PDT 24
Finished Jun 13 01:19:55 PM PDT 24
Peak memory 219756 kb
Host smart-23890e71-8f2e-49a9-ad30-4de596594679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462791529 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1462791529
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3709188046
Short name T75
Test name
Test status
Simulation time 944633940 ps
CPU time 9.86 seconds
Started Jun 13 01:19:41 PM PDT 24
Finished Jun 13 01:19:52 PM PDT 24
Peak memory 219016 kb
Host smart-e6d88b78-4ab0-46d7-b932-7f31f6dbd2b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709188046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3709188046
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2876277824
Short name T442
Test name
Test status
Simulation time 1683687806 ps
CPU time 6.53 seconds
Started Jun 13 01:19:40 PM PDT 24
Finished Jun 13 01:19:47 PM PDT 24
Peak memory 219084 kb
Host smart-c8f1bedf-f73a-4db3-a0d6-13785704f7a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876277824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2876277824
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.898466786
Short name T411
Test name
Test status
Simulation time 174164804 ps
CPU time 8.49 seconds
Started Jun 13 01:19:30 PM PDT 24
Finished Jun 13 01:19:39 PM PDT 24
Peak memory 219568 kb
Host smart-9acd4cdd-5b49-445a-af72-a835344e3514
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898466786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.898466786
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3786043831
Short name T114
Test name
Test status
Simulation time 784608546 ps
CPU time 36.3 seconds
Started Jun 13 01:19:29 PM PDT 24
Finished Jun 13 01:20:06 PM PDT 24
Peak memory 219488 kb
Host smart-b3f9db8b-22fc-4fee-80aa-bf619a20fe06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786043831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3786043831
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1342966269
Short name T450
Test name
Test status
Simulation time 6581299259 ps
CPU time 16.73 seconds
Started Jun 13 01:19:41 PM PDT 24
Finished Jun 13 01:19:59 PM PDT 24
Peak memory 219712 kb
Host smart-9bb8e30a-bed4-4470-8255-54e3a7a9aa0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342966269 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1342966269
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4141532253
Short name T429
Test name
Test status
Simulation time 3423693896 ps
CPU time 11.48 seconds
Started Jun 13 01:19:41 PM PDT 24
Finished Jun 13 01:19:53 PM PDT 24
Peak memory 211520 kb
Host smart-ae6099e5-8541-4238-910e-bbfdb5d18e76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141532253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4141532253
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3461590074
Short name T95
Test name
Test status
Simulation time 14070882086 ps
CPU time 59.31 seconds
Started Jun 13 01:19:42 PM PDT 24
Finished Jun 13 01:20:42 PM PDT 24
Peak memory 211768 kb
Host smart-8c92eb1a-f8c3-4042-a3e2-88b66a490c37
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461590074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3461590074
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2706894451
Short name T65
Test name
Test status
Simulation time 1030045659 ps
CPU time 6.18 seconds
Started Jun 13 01:19:41 PM PDT 24
Finished Jun 13 01:19:48 PM PDT 24
Peak memory 211432 kb
Host smart-d9ce66e4-9dee-458c-ab9c-b66687527a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706894451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2706894451
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4028631838
Short name T444
Test name
Test status
Simulation time 168504691 ps
CPU time 6.62 seconds
Started Jun 13 01:19:41 PM PDT 24
Finished Jun 13 01:19:49 PM PDT 24
Peak memory 219548 kb
Host smart-f7fab68b-dcb1-4bec-a710-b08ac0c657e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028631838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4028631838
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3078538977
Short name T115
Test name
Test status
Simulation time 6975384141 ps
CPU time 42.82 seconds
Started Jun 13 01:19:40 PM PDT 24
Finished Jun 13 01:20:23 PM PDT 24
Peak memory 211720 kb
Host smart-12d5558a-d645-4195-af9c-d2c7eb6aaa5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078538977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3078538977
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1878145670
Short name T458
Test name
Test status
Simulation time 2148691063 ps
CPU time 16.17 seconds
Started Jun 13 01:19:40 PM PDT 24
Finished Jun 13 01:19:57 PM PDT 24
Peak memory 219688 kb
Host smart-a2f1d02b-eace-4ff8-9751-e566a6336bea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878145670 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1878145670
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1484625229
Short name T103
Test name
Test status
Simulation time 8479155356 ps
CPU time 16.18 seconds
Started Jun 13 01:19:40 PM PDT 24
Finished Jun 13 01:19:57 PM PDT 24
Peak memory 219548 kb
Host smart-228f9d05-d4f8-4a4e-9a29-2f0177a62fbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484625229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1484625229
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3182312662
Short name T85
Test name
Test status
Simulation time 23848823133 ps
CPU time 65.03 seconds
Started Jun 13 01:19:40 PM PDT 24
Finished Jun 13 01:20:46 PM PDT 24
Peak memory 211532 kb
Host smart-f1e87434-901c-425e-a448-234679e97c9b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182312662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3182312662
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3293186784
Short name T439
Test name
Test status
Simulation time 2088566374 ps
CPU time 16.17 seconds
Started Jun 13 01:19:41 PM PDT 24
Finished Jun 13 01:19:58 PM PDT 24
Peak memory 211444 kb
Host smart-e2c663f3-2eb3-4908-9dfd-d3dbdf848d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293186784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3293186784
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2939824934
Short name T399
Test name
Test status
Simulation time 174842180 ps
CPU time 6.43 seconds
Started Jun 13 01:19:40 PM PDT 24
Finished Jun 13 01:19:47 PM PDT 24
Peak memory 219544 kb
Host smart-69dc2ee6-7c8c-48c6-b219-45630104dc61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939824934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2939824934
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3935250500
Short name T55
Test name
Test status
Simulation time 1198415080 ps
CPU time 41.47 seconds
Started Jun 13 01:19:39 PM PDT 24
Finished Jun 13 01:20:21 PM PDT 24
Peak memory 211408 kb
Host smart-98e82493-e56c-41fa-83e5-c7434ac9aa2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935250500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3935250500
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1331037274
Short name T72
Test name
Test status
Simulation time 1152480587 ps
CPU time 10.87 seconds
Started Jun 13 01:18:38 PM PDT 24
Finished Jun 13 01:18:49 PM PDT 24
Peak memory 211348 kb
Host smart-3bf7b1e1-9893-4c31-80bc-037dc57c4904
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331037274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1331037274
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3179738605
Short name T416
Test name
Test status
Simulation time 3615087751 ps
CPU time 10.29 seconds
Started Jun 13 01:18:39 PM PDT 24
Finished Jun 13 01:18:51 PM PDT 24
Peak memory 218452 kb
Host smart-beccd048-962a-4a17-9bd1-55e5978d5f21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179738605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3179738605
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2932634914
Short name T430
Test name
Test status
Simulation time 2355691796 ps
CPU time 12.19 seconds
Started Jun 13 01:18:40 PM PDT 24
Finished Jun 13 01:18:53 PM PDT 24
Peak memory 211480 kb
Host smart-c2c2f2b5-5968-41f0-8172-7e7ca95193b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932634914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2932634914
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.535570533
Short name T445
Test name
Test status
Simulation time 26156828585 ps
CPU time 17.44 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:19:04 PM PDT 24
Peak memory 219780 kb
Host smart-a5959558-d800-49cb-a246-7cbd1a827028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535570533 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.535570533
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2658977070
Short name T88
Test name
Test status
Simulation time 1336929322 ps
CPU time 7.87 seconds
Started Jun 13 01:18:39 PM PDT 24
Finished Jun 13 01:18:47 PM PDT 24
Peak memory 211392 kb
Host smart-a9d73037-4e54-4d71-95da-a8d11350e2df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658977070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2658977070
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2689154049
Short name T381
Test name
Test status
Simulation time 783396268 ps
CPU time 8.91 seconds
Started Jun 13 01:18:39 PM PDT 24
Finished Jun 13 01:18:48 PM PDT 24
Peak memory 211276 kb
Host smart-0be541b4-cf0f-4237-9906-64f15fe06ceb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689154049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2689154049
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.375624523
Short name T394
Test name
Test status
Simulation time 1617257420 ps
CPU time 13.48 seconds
Started Jun 13 01:18:40 PM PDT 24
Finished Jun 13 01:18:54 PM PDT 24
Peak memory 211264 kb
Host smart-b93a0a6c-70ad-42b3-bc4f-63663a4f496e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375624523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
375624523
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1377017331
Short name T105
Test name
Test status
Simulation time 34488240592 ps
CPU time 40.6 seconds
Started Jun 13 01:18:30 PM PDT 24
Finished Jun 13 01:19:12 PM PDT 24
Peak memory 211600 kb
Host smart-6b16e285-acb9-4b98-a52a-fb129247d2ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377017331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1377017331
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3372265988
Short name T418
Test name
Test status
Simulation time 984194133 ps
CPU time 9.88 seconds
Started Jun 13 01:18:47 PM PDT 24
Finished Jun 13 01:18:58 PM PDT 24
Peak memory 219568 kb
Host smart-4fd8256e-c647-48ef-a34a-3ec15020491d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372265988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3372265988
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.795820280
Short name T379
Test name
Test status
Simulation time 1822323527 ps
CPU time 10.27 seconds
Started Jun 13 01:18:31 PM PDT 24
Finished Jun 13 01:18:42 PM PDT 24
Peak memory 219568 kb
Host smart-95abdc24-4498-49b1-90b6-5da51e1d55c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795820280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.795820280
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3311824503
Short name T460
Test name
Test status
Simulation time 577101053 ps
CPU time 36.74 seconds
Started Jun 13 01:18:39 PM PDT 24
Finished Jun 13 01:19:17 PM PDT 24
Peak memory 211852 kb
Host smart-44e72ab6-c626-4036-ad1c-8be50545e674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311824503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3311824503
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2407686728
Short name T81
Test name
Test status
Simulation time 3358443261 ps
CPU time 13.67 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:18:59 PM PDT 24
Peak memory 211496 kb
Host smart-459383f0-0d51-4e82-8790-d36d0aa32a40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407686728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2407686728
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3644148304
Short name T454
Test name
Test status
Simulation time 2135878785 ps
CPU time 10.87 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:18:57 PM PDT 24
Peak memory 219072 kb
Host smart-4c497a65-3d9c-4ba5-95d2-a89de64d95de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644148304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3644148304
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.534565101
Short name T68
Test name
Test status
Simulation time 613957570 ps
CPU time 7.83 seconds
Started Jun 13 01:18:48 PM PDT 24
Finished Jun 13 01:18:56 PM PDT 24
Peak memory 211352 kb
Host smart-48c496b6-d319-4619-a1ea-69828ccb192d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534565101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.534565101
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.457185646
Short name T380
Test name
Test status
Simulation time 1027256505 ps
CPU time 5.52 seconds
Started Jun 13 01:18:44 PM PDT 24
Finished Jun 13 01:18:50 PM PDT 24
Peak memory 219564 kb
Host smart-8b2a40d8-cbc4-4eb9-99bb-b72f4cf97e4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457185646 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.457185646
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1465869104
Short name T425
Test name
Test status
Simulation time 7136172658 ps
CPU time 15.61 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:19:02 PM PDT 24
Peak memory 219684 kb
Host smart-ad820a2b-cb8e-4f2a-80d2-e3360b61d184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465869104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1465869104
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1708208007
Short name T390
Test name
Test status
Simulation time 347590917 ps
CPU time 4.21 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:18:50 PM PDT 24
Peak memory 211264 kb
Host smart-5e6259c0-195a-4bf0-bcb4-0d9cdb5e59f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708208007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1708208007
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.619744708
Short name T393
Test name
Test status
Simulation time 5442834899 ps
CPU time 12.02 seconds
Started Jun 13 01:18:47 PM PDT 24
Finished Jun 13 01:19:00 PM PDT 24
Peak memory 211408 kb
Host smart-fc7827f8-0fd3-48e1-82eb-5bab331ce0da
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619744708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
619744708
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3458301516
Short name T435
Test name
Test status
Simulation time 11341644496 ps
CPU time 49.44 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:19:36 PM PDT 24
Peak memory 218596 kb
Host smart-37e2da49-850a-40d6-875f-3b9032779fb6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458301516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3458301516
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3171577051
Short name T456
Test name
Test status
Simulation time 3171460696 ps
CPU time 13.48 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:19:00 PM PDT 24
Peak memory 211464 kb
Host smart-07d8a691-b0ed-4847-b3f6-a1dab9fe3869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171577051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3171577051
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.303101221
Short name T107
Test name
Test status
Simulation time 118637329 ps
CPU time 9.15 seconds
Started Jun 13 01:18:44 PM PDT 24
Finished Jun 13 01:18:54 PM PDT 24
Peak memory 219504 kb
Host smart-b69337f5-5ea1-4e12-97de-759add50f0ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303101221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.303101221
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3646536750
Short name T389
Test name
Test status
Simulation time 4242715873 ps
CPU time 16.54 seconds
Started Jun 13 01:18:52 PM PDT 24
Finished Jun 13 01:19:09 PM PDT 24
Peak memory 211572 kb
Host smart-49c2f6e8-d5b2-4d3c-ab40-3ba7a3872ade
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646536750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3646536750
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.50117831
Short name T455
Test name
Test status
Simulation time 5136077498 ps
CPU time 15.17 seconds
Started Jun 13 01:18:53 PM PDT 24
Finished Jun 13 01:19:09 PM PDT 24
Peak memory 211532 kb
Host smart-9f204ddc-4f9f-4ca4-9a7a-4312e9fb1a31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50117831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_res
et.50117831
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.909248841
Short name T384
Test name
Test status
Simulation time 11049433587 ps
CPU time 16.56 seconds
Started Jun 13 01:18:53 PM PDT 24
Finished Jun 13 01:19:11 PM PDT 24
Peak memory 219680 kb
Host smart-0211b57d-3b9c-47b9-acf5-e3ef305193f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909248841 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.909248841
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2231986271
Short name T62
Test name
Test status
Simulation time 792354518 ps
CPU time 7.61 seconds
Started Jun 13 01:18:53 PM PDT 24
Finished Jun 13 01:19:01 PM PDT 24
Peak memory 211440 kb
Host smart-b2b0356f-b9ce-4b1f-b6d0-1568a6b990ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231986271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2231986271
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.611314104
Short name T385
Test name
Test status
Simulation time 211677253 ps
CPU time 5.67 seconds
Started Jun 13 01:18:53 PM PDT 24
Finished Jun 13 01:18:59 PM PDT 24
Peak memory 211284 kb
Host smart-e1910bf9-7f13-471c-8c8f-cdc96d0ae989
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611314104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.611314104
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3855125446
Short name T449
Test name
Test status
Simulation time 4117891554 ps
CPU time 9.92 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:18:56 PM PDT 24
Peak memory 211428 kb
Host smart-2b8dcb67-ed18-4ab6-8875-2deeef98ea29
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855125446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3855125446
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1635342923
Short name T76
Test name
Test status
Simulation time 28169836082 ps
CPU time 67.48 seconds
Started Jun 13 01:18:46 PM PDT 24
Finished Jun 13 01:19:54 PM PDT 24
Peak memory 211572 kb
Host smart-956e6f9b-61c9-4a75-b5e6-b84673ebc66c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635342923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1635342923
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3579263974
Short name T426
Test name
Test status
Simulation time 1667301614 ps
CPU time 14.38 seconds
Started Jun 13 01:18:54 PM PDT 24
Finished Jun 13 01:19:09 PM PDT 24
Peak memory 211612 kb
Host smart-a603e400-33f3-40fd-b72c-5b6f3ab29ef3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579263974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3579263974
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.9920057
Short name T378
Test name
Test status
Simulation time 421904910 ps
CPU time 10.49 seconds
Started Jun 13 01:18:46 PM PDT 24
Finished Jun 13 01:18:57 PM PDT 24
Peak memory 219536 kb
Host smart-91280fc4-90c4-4ff9-8f20-1adf3afff698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9920057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.9920057
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1853240929
Short name T54
Test name
Test status
Simulation time 1945739505 ps
CPU time 77.3 seconds
Started Jun 13 01:18:45 PM PDT 24
Finished Jun 13 01:20:03 PM PDT 24
Peak memory 212912 kb
Host smart-f5bfc2e9-b986-4543-9fe4-7429ce4a4d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853240929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1853240929
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1256917726
Short name T397
Test name
Test status
Simulation time 2482470042 ps
CPU time 12.51 seconds
Started Jun 13 01:18:51 PM PDT 24
Finished Jun 13 01:19:04 PM PDT 24
Peak memory 219772 kb
Host smart-8d132f39-a8bf-4c2e-a085-a6ea297c7a9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256917726 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1256917726
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.225218470
Short name T383
Test name
Test status
Simulation time 85645317 ps
CPU time 4.27 seconds
Started Jun 13 01:18:51 PM PDT 24
Finished Jun 13 01:18:56 PM PDT 24
Peak memory 211292 kb
Host smart-49464621-946e-4d1e-9260-9a4cd0b3859a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225218470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.225218470
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1901207740
Short name T433
Test name
Test status
Simulation time 6586784064 ps
CPU time 54.65 seconds
Started Jun 13 01:18:51 PM PDT 24
Finished Jun 13 01:19:46 PM PDT 24
Peak memory 211480 kb
Host smart-19fd725e-2893-4984-905b-58fa42d2dff4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901207740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1901207740
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2172310347
Short name T422
Test name
Test status
Simulation time 2777165253 ps
CPU time 9.44 seconds
Started Jun 13 01:18:52 PM PDT 24
Finished Jun 13 01:19:02 PM PDT 24
Peak memory 219612 kb
Host smart-c26c1d58-268e-46a2-8dc0-00d92f034e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172310347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2172310347
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1583820282
Short name T388
Test name
Test status
Simulation time 6725054512 ps
CPU time 17.6 seconds
Started Jun 13 01:18:52 PM PDT 24
Finished Jun 13 01:19:10 PM PDT 24
Peak memory 219692 kb
Host smart-a44f3e92-7b37-48f2-86e2-324ee32e27db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583820282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1583820282
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.131949330
Short name T431
Test name
Test status
Simulation time 5045747763 ps
CPU time 43.42 seconds
Started Jun 13 01:18:53 PM PDT 24
Finished Jun 13 01:19:37 PM PDT 24
Peak memory 219668 kb
Host smart-80d7ab92-eacf-4382-884d-5c19f9682804
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131949330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.131949330
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3734276995
Short name T375
Test name
Test status
Simulation time 1826056507 ps
CPU time 14.99 seconds
Started Jun 13 01:19:07 PM PDT 24
Finished Jun 13 01:19:24 PM PDT 24
Peak memory 219556 kb
Host smart-596aeadd-d4fd-480a-8df0-99f94869141b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734276995 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3734276995
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3925227850
Short name T396
Test name
Test status
Simulation time 850553888 ps
CPU time 9.15 seconds
Started Jun 13 01:19:06 PM PDT 24
Finished Jun 13 01:19:17 PM PDT 24
Peak memory 219020 kb
Host smart-baa2a30b-3c29-440e-8489-a5d69256fa96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925227850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3925227850
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2103122789
Short name T432
Test name
Test status
Simulation time 11809331217 ps
CPU time 54.83 seconds
Started Jun 13 01:18:57 PM PDT 24
Finished Jun 13 01:19:53 PM PDT 24
Peak memory 211560 kb
Host smart-b1976de6-2a75-43ba-9db9-7357074d8cd3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103122789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2103122789
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3429820705
Short name T403
Test name
Test status
Simulation time 1802533646 ps
CPU time 15.15 seconds
Started Jun 13 01:19:07 PM PDT 24
Finished Jun 13 01:19:24 PM PDT 24
Peak memory 211460 kb
Host smart-6dd93a91-9d31-40c8-8904-9d68a8542145
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429820705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3429820705
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2541187206
Short name T392
Test name
Test status
Simulation time 2040233623 ps
CPU time 20.42 seconds
Started Jun 13 01:18:58 PM PDT 24
Finished Jun 13 01:19:20 PM PDT 24
Peak memory 219556 kb
Host smart-04e2274a-3e69-4b21-a20a-272b2c171a80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541187206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2541187206
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.987065770
Short name T109
Test name
Test status
Simulation time 8588161446 ps
CPU time 47.47 seconds
Started Jun 13 01:18:59 PM PDT 24
Finished Jun 13 01:19:48 PM PDT 24
Peak memory 219696 kb
Host smart-3ce4d6c3-ffc0-4891-b80a-1175188fb040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987065770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.987065770
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.480936028
Short name T382
Test name
Test status
Simulation time 94672033 ps
CPU time 4.52 seconds
Started Jun 13 01:19:05 PM PDT 24
Finished Jun 13 01:19:10 PM PDT 24
Peak memory 219568 kb
Host smart-28cdd124-563c-4134-a33d-f9bd640adcb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480936028 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.480936028
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2812423442
Short name T398
Test name
Test status
Simulation time 851665284 ps
CPU time 9.7 seconds
Started Jun 13 01:19:06 PM PDT 24
Finished Jun 13 01:19:18 PM PDT 24
Peak memory 211384 kb
Host smart-03921ae9-554f-43ac-a089-c8ae08cd2278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812423442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2812423442
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2596404137
Short name T84
Test name
Test status
Simulation time 7289118355 ps
CPU time 52.57 seconds
Started Jun 13 01:19:08 PM PDT 24
Finished Jun 13 01:20:02 PM PDT 24
Peak memory 211576 kb
Host smart-edda129c-cfb2-4703-a774-21becedf1f07
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596404137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2596404137
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4100569334
Short name T446
Test name
Test status
Simulation time 3260566577 ps
CPU time 8.88 seconds
Started Jun 13 01:19:07 PM PDT 24
Finished Jun 13 01:19:18 PM PDT 24
Peak memory 211568 kb
Host smart-8d019bef-e503-4f97-b7e5-2d1d0abb70bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100569334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.4100569334
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1917735849
Short name T401
Test name
Test status
Simulation time 2870639017 ps
CPU time 15.14 seconds
Started Jun 13 01:19:07 PM PDT 24
Finished Jun 13 01:19:24 PM PDT 24
Peak memory 219660 kb
Host smart-93cf2483-891d-4fc2-8341-611439acf142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917735849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1917735849
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2754972889
Short name T421
Test name
Test status
Simulation time 2982565183 ps
CPU time 12.33 seconds
Started Jun 13 01:19:06 PM PDT 24
Finished Jun 13 01:19:21 PM PDT 24
Peak memory 219732 kb
Host smart-6bd49bca-3ad8-4498-8936-d7891f5fc828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754972889 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2754972889
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1254153872
Short name T73
Test name
Test status
Simulation time 89310145 ps
CPU time 4.18 seconds
Started Jun 13 01:19:06 PM PDT 24
Finished Jun 13 01:19:13 PM PDT 24
Peak memory 211356 kb
Host smart-35d22740-46fb-4284-9a0a-9f39d34f1300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254153872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1254153872
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1844485395
Short name T437
Test name
Test status
Simulation time 4788058755 ps
CPU time 46.36 seconds
Started Jun 13 01:19:05 PM PDT 24
Finished Jun 13 01:19:54 PM PDT 24
Peak memory 211496 kb
Host smart-bedded01-0914-4fd4-90f1-b5d3b7edb610
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844485395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1844485395
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.525240629
Short name T96
Test name
Test status
Simulation time 638450888 ps
CPU time 8.26 seconds
Started Jun 13 01:19:05 PM PDT 24
Finished Jun 13 01:19:16 PM PDT 24
Peak memory 211420 kb
Host smart-9382e8a8-73ed-4b59-baef-72107470ecfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525240629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.525240629
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.829425000
Short name T453
Test name
Test status
Simulation time 1173294110 ps
CPU time 14.84 seconds
Started Jun 13 01:19:05 PM PDT 24
Finished Jun 13 01:19:21 PM PDT 24
Peak memory 219540 kb
Host smart-40dcfba3-53f9-4653-8e84-dff82920947f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829425000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.829425000
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3600005038
Short name T111
Test name
Test status
Simulation time 5469047806 ps
CPU time 74.23 seconds
Started Jun 13 01:19:08 PM PDT 24
Finished Jun 13 01:20:24 PM PDT 24
Peak memory 213040 kb
Host smart-85e1103c-d0bc-48d9-bdab-e9c53f08648a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600005038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3600005038
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1194644182
Short name T427
Test name
Test status
Simulation time 10867148657 ps
CPU time 9.57 seconds
Started Jun 13 01:19:16 PM PDT 24
Finished Jun 13 01:19:26 PM PDT 24
Peak memory 219756 kb
Host smart-f6924261-df5e-4da9-8874-eace1de3d0df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194644182 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1194644182
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.166010040
Short name T67
Test name
Test status
Simulation time 7533835523 ps
CPU time 15.34 seconds
Started Jun 13 01:19:13 PM PDT 24
Finished Jun 13 01:19:29 PM PDT 24
Peak memory 219636 kb
Host smart-5cd02740-e7bd-4d87-b6bb-6d260ae45a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166010040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.166010040
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3327054489
Short name T77
Test name
Test status
Simulation time 15872751676 ps
CPU time 39.6 seconds
Started Jun 13 01:19:04 PM PDT 24
Finished Jun 13 01:19:45 PM PDT 24
Peak memory 211532 kb
Host smart-de620202-a1b5-4b32-9718-65ade663b26e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327054489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3327054489
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1709508843
Short name T66
Test name
Test status
Simulation time 839886065 ps
CPU time 9.41 seconds
Started Jun 13 01:19:13 PM PDT 24
Finished Jun 13 01:19:23 PM PDT 24
Peak memory 211488 kb
Host smart-c687e3c5-2523-4c6e-9eb1-30a3cf1bfced
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709508843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1709508843
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.980753749
Short name T461
Test name
Test status
Simulation time 4005441397 ps
CPU time 21.2 seconds
Started Jun 13 01:19:06 PM PDT 24
Finished Jun 13 01:19:29 PM PDT 24
Peak memory 217528 kb
Host smart-15781172-8aca-4fe0-9d33-605a23e1c4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980753749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.980753749
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2481362975
Short name T113
Test name
Test status
Simulation time 2348722052 ps
CPU time 42.49 seconds
Started Jun 13 01:19:13 PM PDT 24
Finished Jun 13 01:19:56 PM PDT 24
Peak memory 219656 kb
Host smart-4e51044c-fdaa-401b-81ae-88782c93e35c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481362975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2481362975
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1982079724
Short name T205
Test name
Test status
Simulation time 3435519719 ps
CPU time 9.37 seconds
Started Jun 13 01:19:41 PM PDT 24
Finished Jun 13 01:19:52 PM PDT 24
Peak memory 211164 kb
Host smart-9ed7da2b-97ad-446f-93d8-8bf9864e0385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982079724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1982079724
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1527850122
Short name T169
Test name
Test status
Simulation time 28268589865 ps
CPU time 261.01 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:24:07 PM PDT 24
Peak memory 228436 kb
Host smart-bfdb0c33-6639-4d60-9e47-c50c07b536cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527850122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1527850122
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3441353408
Short name T326
Test name
Test status
Simulation time 1807339684 ps
CPU time 15.66 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:20:01 PM PDT 24
Peak memory 211276 kb
Host smart-52282f0d-6a7c-45a3-81cf-b466aca4d740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441353408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3441353408
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1329489540
Short name T27
Test name
Test status
Simulation time 6846437654 ps
CPU time 109.14 seconds
Started Jun 13 01:19:41 PM PDT 24
Finished Jun 13 01:21:31 PM PDT 24
Peak memory 235712 kb
Host smart-e3e0507f-8bf4-4c8e-93da-d5927c730938
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329489540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1329489540
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1021164017
Short name T248
Test name
Test status
Simulation time 6262606360 ps
CPU time 32.17 seconds
Started Jun 13 01:19:43 PM PDT 24
Finished Jun 13 01:20:15 PM PDT 24
Peak memory 214512 kb
Host smart-bf886015-bcd6-441b-afaf-67d68182a67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021164017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1021164017
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.446226726
Short name T12
Test name
Test status
Simulation time 5930289668 ps
CPU time 70.36 seconds
Started Jun 13 01:19:40 PM PDT 24
Finished Jun 13 01:20:51 PM PDT 24
Peak memory 214308 kb
Host smart-f7ec0833-bafb-407d-aa85-5619258bc605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446226726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.446226726
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1912632111
Short name T14
Test name
Test status
Simulation time 248302108489 ps
CPU time 2212.11 seconds
Started Jun 13 01:19:39 PM PDT 24
Finished Jun 13 01:56:32 PM PDT 24
Peak memory 248836 kb
Host smart-fff6d11e-1171-4350-98e8-5975e19e5695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912632111 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1912632111
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3020979030
Short name T91
Test name
Test status
Simulation time 1373656830 ps
CPU time 12.29 seconds
Started Jun 13 01:19:48 PM PDT 24
Finished Jun 13 01:20:01 PM PDT 24
Peak memory 211116 kb
Host smart-cf5767a1-55e3-4b9c-9f30-b4242a668b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020979030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3020979030
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.57126527
Short name T291
Test name
Test status
Simulation time 24257566034 ps
CPU time 121.72 seconds
Started Jun 13 01:19:46 PM PDT 24
Finished Jun 13 01:21:48 PM PDT 24
Peak memory 225456 kb
Host smart-a85d4cab-0938-479c-b580-c07a12a4cf3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57126527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.57126527
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2672541234
Short name T296
Test name
Test status
Simulation time 2995224348 ps
CPU time 26.66 seconds
Started Jun 13 01:19:44 PM PDT 24
Finished Jun 13 01:20:12 PM PDT 24
Peak memory 212208 kb
Host smart-22c83621-e597-4551-8a97-a2d648f1e9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672541234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2672541234
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.727285070
Short name T128
Test name
Test status
Simulation time 8242347496 ps
CPU time 18.19 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:20:04 PM PDT 24
Peak memory 211344 kb
Host smart-1eb066ce-d0a7-40f7-9a12-3a458f3c76ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727285070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.727285070
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.759194729
Short name T28
Test name
Test status
Simulation time 4177753541 ps
CPU time 109.88 seconds
Started Jun 13 01:19:44 PM PDT 24
Finished Jun 13 01:21:35 PM PDT 24
Peak memory 236520 kb
Host smart-4fae6f36-2862-4c4e-9fe3-89a4f21f05e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759194729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.759194729
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2824323606
Short name T260
Test name
Test status
Simulation time 4171989162 ps
CPU time 40.33 seconds
Started Jun 13 01:19:48 PM PDT 24
Finished Jun 13 01:20:29 PM PDT 24
Peak memory 213732 kb
Host smart-5aac7895-0b14-4725-801c-6ce5fd0a1722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824323606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2824323606
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3840519625
Short name T187
Test name
Test status
Simulation time 674805047 ps
CPU time 13.7 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:20:00 PM PDT 24
Peak memory 213372 kb
Host smart-4da39a08-78d9-4df5-92dc-223fe6425b16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840519625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3840519625
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.29844212
Short name T301
Test name
Test status
Simulation time 85441785 ps
CPU time 4.42 seconds
Started Jun 13 01:20:20 PM PDT 24
Finished Jun 13 01:20:25 PM PDT 24
Peak memory 211116 kb
Host smart-adad14e0-ac26-4051-b06b-68db10ba6b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29844212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.29844212
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3188470704
Short name T264
Test name
Test status
Simulation time 34475223952 ps
CPU time 305.89 seconds
Started Jun 13 01:20:12 PM PDT 24
Finished Jun 13 01:25:19 PM PDT 24
Peak memory 237920 kb
Host smart-71bf93f0-a8bd-4a3d-883d-d1117d83fc0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188470704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3188470704
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3560107298
Short name T44
Test name
Test status
Simulation time 1176532928 ps
CPU time 17.74 seconds
Started Jun 13 01:20:21 PM PDT 24
Finished Jun 13 01:20:39 PM PDT 24
Peak memory 211628 kb
Host smart-ddf2b2e9-029b-4dc4-ad70-4b211334877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560107298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3560107298
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4105251163
Short name T342
Test name
Test status
Simulation time 1038146085 ps
CPU time 12.12 seconds
Started Jun 13 01:20:12 PM PDT 24
Finished Jun 13 01:20:26 PM PDT 24
Peak memory 211292 kb
Host smart-4736d321-c4b1-4cf3-a2c0-d42f9912d41d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105251163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4105251163
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4029256187
Short name T149
Test name
Test status
Simulation time 17709604473 ps
CPU time 25.05 seconds
Started Jun 13 01:20:12 PM PDT 24
Finished Jun 13 01:20:38 PM PDT 24
Peak memory 213896 kb
Host smart-39c5ed9a-aa47-48c3-8ed7-052c9b947ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029256187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4029256187
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.492424343
Short name T239
Test name
Test status
Simulation time 3570588726 ps
CPU time 12.15 seconds
Started Jun 13 01:20:12 PM PDT 24
Finished Jun 13 01:20:25 PM PDT 24
Peak memory 212012 kb
Host smart-7e47dd4d-6fd8-4276-a62c-9b5436181d56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492424343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.492424343
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3737844870
Short name T356
Test name
Test status
Simulation time 693632040 ps
CPU time 8.68 seconds
Started Jun 13 01:20:21 PM PDT 24
Finished Jun 13 01:20:31 PM PDT 24
Peak memory 211144 kb
Host smart-0e0f5b9f-c76c-48f9-956e-3c32802d706a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737844870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3737844870
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2292523923
Short name T328
Test name
Test status
Simulation time 23848588205 ps
CPU time 204.32 seconds
Started Jun 13 01:20:20 PM PDT 24
Finished Jun 13 01:23:44 PM PDT 24
Peak memory 237648 kb
Host smart-7a5110ef-1d2f-4e77-b195-dffad65cfaf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292523923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2292523923
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.658024248
Short name T181
Test name
Test status
Simulation time 1279990288 ps
CPU time 13.17 seconds
Started Jun 13 01:20:20 PM PDT 24
Finished Jun 13 01:20:33 PM PDT 24
Peak memory 211476 kb
Host smart-629f99d3-70d3-4d79-a1d6-67a984e25ace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658024248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.658024248
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2626941647
Short name T279
Test name
Test status
Simulation time 725906359 ps
CPU time 10.28 seconds
Started Jun 13 01:20:19 PM PDT 24
Finished Jun 13 01:20:30 PM PDT 24
Peak memory 213220 kb
Host smart-15bcc209-985a-4708-9493-c920bed279aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626941647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2626941647
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2926534932
Short name T221
Test name
Test status
Simulation time 3631124664 ps
CPU time 23.57 seconds
Started Jun 13 01:20:21 PM PDT 24
Finished Jun 13 01:20:45 PM PDT 24
Peak memory 213840 kb
Host smart-4e79b815-dadd-4c11-a71d-5650a2ed7cc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926534932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2926534932
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2920657591
Short name T302
Test name
Test status
Simulation time 748195116 ps
CPU time 9.13 seconds
Started Jun 13 01:20:28 PM PDT 24
Finished Jun 13 01:20:38 PM PDT 24
Peak memory 211132 kb
Host smart-6208cd40-a5c8-4bb3-b5ac-3f844faf2311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920657591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2920657591
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.765464857
Short name T36
Test name
Test status
Simulation time 2064731005 ps
CPU time 128.9 seconds
Started Jun 13 01:20:20 PM PDT 24
Finished Jun 13 01:22:30 PM PDT 24
Peak memory 233628 kb
Host smart-749dbf87-b6f0-49b3-ad9e-b81d6f97a967
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765464857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.765464857
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3085603122
Short name T369
Test name
Test status
Simulation time 20680269354 ps
CPU time 33.17 seconds
Started Jun 13 01:20:19 PM PDT 24
Finished Jun 13 01:20:53 PM PDT 24
Peak memory 212256 kb
Host smart-b12b2318-aded-4961-bdab-481ee42a9b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085603122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3085603122
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2838326676
Short name T257
Test name
Test status
Simulation time 534820071 ps
CPU time 7.47 seconds
Started Jun 13 01:20:21 PM PDT 24
Finished Jun 13 01:20:29 PM PDT 24
Peak memory 211292 kb
Host smart-fde0cc03-98d7-4e51-899c-2d573d1c1380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838326676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2838326676
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.915986250
Short name T246
Test name
Test status
Simulation time 13604659007 ps
CPU time 29.41 seconds
Started Jun 13 01:20:21 PM PDT 24
Finished Jun 13 01:20:51 PM PDT 24
Peak memory 214476 kb
Host smart-a402719e-8e10-44e6-ab35-9f810950bf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915986250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.915986250
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2671022956
Short name T245
Test name
Test status
Simulation time 57021317468 ps
CPU time 65.13 seconds
Started Jun 13 01:20:19 PM PDT 24
Finished Jun 13 01:21:25 PM PDT 24
Peak memory 219328 kb
Host smart-b5b11803-bb73-44ad-b55f-34a104a6be68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671022956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2671022956
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1709152602
Short name T131
Test name
Test status
Simulation time 179060608 ps
CPU time 4.36 seconds
Started Jun 13 01:20:30 PM PDT 24
Finished Jun 13 01:20:35 PM PDT 24
Peak memory 211124 kb
Host smart-e0a90339-aeb0-4fcb-9c84-fe1e555a4e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709152602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1709152602
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1230853750
Short name T261
Test name
Test status
Simulation time 5224929452 ps
CPU time 75.32 seconds
Started Jun 13 01:20:29 PM PDT 24
Finished Jun 13 01:21:45 PM PDT 24
Peak memory 228348 kb
Host smart-bd74b4ec-85a7-4a91-ac41-014ff8be7110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230853750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1230853750
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1157009541
Short name T220
Test name
Test status
Simulation time 5907052525 ps
CPU time 18.67 seconds
Started Jun 13 01:20:28 PM PDT 24
Finished Jun 13 01:20:47 PM PDT 24
Peak memory 211512 kb
Host smart-5e36c560-d2ca-4baa-926e-d2a5b1a53928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157009541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1157009541
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.458542175
Short name T20
Test name
Test status
Simulation time 11656275878 ps
CPU time 12.88 seconds
Started Jun 13 01:20:28 PM PDT 24
Finished Jun 13 01:20:42 PM PDT 24
Peak memory 211344 kb
Host smart-f04502c6-d2c9-4f14-9e80-dbade89ddb47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458542175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.458542175
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3722892139
Short name T350
Test name
Test status
Simulation time 4860886540 ps
CPU time 27.76 seconds
Started Jun 13 01:20:27 PM PDT 24
Finished Jun 13 01:20:55 PM PDT 24
Peak memory 214120 kb
Host smart-fc54dfa6-a021-4fdd-b31b-070a53cb2abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722892139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3722892139
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.61035374
Short name T241
Test name
Test status
Simulation time 11980677100 ps
CPU time 33.91 seconds
Started Jun 13 01:20:29 PM PDT 24
Finished Jun 13 01:21:04 PM PDT 24
Peak memory 213588 kb
Host smart-8ee73e2a-649c-4686-932d-862543216778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61035374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.rom_ctrl_stress_all.61035374
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.202588238
Short name T151
Test name
Test status
Simulation time 533720532 ps
CPU time 8.17 seconds
Started Jun 13 01:20:27 PM PDT 24
Finished Jun 13 01:20:36 PM PDT 24
Peak memory 211124 kb
Host smart-34274343-f020-4348-9f51-98ea84d27d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202588238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.202588238
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4173803229
Short name T337
Test name
Test status
Simulation time 25947025751 ps
CPU time 298.93 seconds
Started Jun 13 01:20:28 PM PDT 24
Finished Jun 13 01:25:28 PM PDT 24
Peak memory 225000 kb
Host smart-4e67d05a-6de0-4e81-844e-1913c4fb3bf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173803229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4173803229
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2451427674
Short name T292
Test name
Test status
Simulation time 2233832833 ps
CPU time 23.91 seconds
Started Jun 13 01:20:28 PM PDT 24
Finished Jun 13 01:20:53 PM PDT 24
Peak memory 211872 kb
Host smart-0ba3ed13-0779-4205-8655-de78e3893265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451427674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2451427674
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.139047721
Short name T163
Test name
Test status
Simulation time 666280822 ps
CPU time 8.22 seconds
Started Jun 13 01:20:25 PM PDT 24
Finished Jun 13 01:20:33 PM PDT 24
Peak memory 211284 kb
Host smart-4bc578d8-587c-4177-824b-89070333765c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139047721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.139047721
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4063529059
Short name T155
Test name
Test status
Simulation time 3727660667 ps
CPU time 37.41 seconds
Started Jun 13 01:20:27 PM PDT 24
Finished Jun 13 01:21:05 PM PDT 24
Peak memory 213748 kb
Host smart-b53da50c-7d2f-4cae-8a94-7e69cdbcac74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063529059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4063529059
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1299976863
Short name T53
Test name
Test status
Simulation time 1240005075 ps
CPU time 11.87 seconds
Started Jun 13 01:20:35 PM PDT 24
Finished Jun 13 01:20:47 PM PDT 24
Peak memory 210972 kb
Host smart-4fe3cbab-fdea-4c06-938b-6edc1d8dfd77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299976863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1299976863
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1586631209
Short name T23
Test name
Test status
Simulation time 6348023032 ps
CPU time 85.75 seconds
Started Jun 13 01:20:37 PM PDT 24
Finished Jun 13 01:22:04 PM PDT 24
Peak memory 224840 kb
Host smart-9e81ae6f-8903-4e64-972c-8f92654c6e36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586631209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1586631209
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3605912863
Short name T274
Test name
Test status
Simulation time 2507771021 ps
CPU time 25.19 seconds
Started Jun 13 01:20:35 PM PDT 24
Finished Jun 13 01:21:00 PM PDT 24
Peak memory 211792 kb
Host smart-2d63feb7-b58a-48fc-9a0b-8247836fc42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605912863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3605912863
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2536010859
Short name T179
Test name
Test status
Simulation time 6473043226 ps
CPU time 15.89 seconds
Started Jun 13 01:20:35 PM PDT 24
Finished Jun 13 01:20:51 PM PDT 24
Peak memory 211308 kb
Host smart-bdf227bf-dc90-48d6-abcb-2b7ad1e8a002
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536010859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2536010859
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2012300947
Short name T289
Test name
Test status
Simulation time 188458899 ps
CPU time 10.04 seconds
Started Jun 13 01:20:26 PM PDT 24
Finished Jun 13 01:20:36 PM PDT 24
Peak memory 213920 kb
Host smart-c8cb2e6f-4e4e-4404-a36c-53d440d5de21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012300947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2012300947
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.347825076
Short name T294
Test name
Test status
Simulation time 234270151 ps
CPU time 10.06 seconds
Started Jun 13 01:20:38 PM PDT 24
Finished Jun 13 01:20:48 PM PDT 24
Peak memory 211048 kb
Host smart-3886742e-0e8b-4e8c-83c8-8640f6fbd7d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347825076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.347825076
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1673769291
Short name T273
Test name
Test status
Simulation time 833913217 ps
CPU time 9.49 seconds
Started Jun 13 01:20:35 PM PDT 24
Finished Jun 13 01:20:46 PM PDT 24
Peak memory 211132 kb
Host smart-60d24173-ca21-40d5-9bc9-8ae410b0851c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673769291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1673769291
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3846523911
Short name T325
Test name
Test status
Simulation time 66817045953 ps
CPU time 305.38 seconds
Started Jun 13 01:20:36 PM PDT 24
Finished Jun 13 01:25:42 PM PDT 24
Peak memory 233608 kb
Host smart-553d4c5b-e035-4bdc-ba47-acd7148a0b32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846523911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3846523911
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1040736211
Short name T353
Test name
Test status
Simulation time 13408910225 ps
CPU time 29.42 seconds
Started Jun 13 01:20:35 PM PDT 24
Finished Jun 13 01:21:06 PM PDT 24
Peak memory 212312 kb
Host smart-6b4e986a-6fbd-423d-aa2f-e2cd368ab631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040736211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1040736211
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3848433299
Short name T278
Test name
Test status
Simulation time 4950972672 ps
CPU time 12.66 seconds
Started Jun 13 01:20:39 PM PDT 24
Finished Jun 13 01:20:52 PM PDT 24
Peak memory 211348 kb
Host smart-14ebc50a-a47e-4ec9-a47e-00aa07266c8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3848433299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3848433299
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2797000341
Short name T254
Test name
Test status
Simulation time 2757453450 ps
CPU time 17.86 seconds
Started Jun 13 01:20:37 PM PDT 24
Finished Jun 13 01:20:56 PM PDT 24
Peak memory 213668 kb
Host smart-98783050-3a8f-40f9-9afd-e80704ae30eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797000341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2797000341
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1189803243
Short name T256
Test name
Test status
Simulation time 295282680 ps
CPU time 17.52 seconds
Started Jun 13 01:20:37 PM PDT 24
Finished Jun 13 01:20:55 PM PDT 24
Peak memory 213568 kb
Host smart-fe388690-e89b-4c08-8f40-301f239b96bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189803243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1189803243
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1307453744
Short name T152
Test name
Test status
Simulation time 6699550358 ps
CPU time 14.59 seconds
Started Jun 13 01:20:44 PM PDT 24
Finished Jun 13 01:21:00 PM PDT 24
Peak memory 211188 kb
Host smart-c1be7fbf-a046-4acb-beee-3c877f32477d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307453744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1307453744
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2881782441
Short name T306
Test name
Test status
Simulation time 20877402568 ps
CPU time 162.95 seconds
Started Jun 13 01:20:42 PM PDT 24
Finished Jun 13 01:23:27 PM PDT 24
Peak memory 237660 kb
Host smart-dece2302-b2ed-4553-8f42-a90dc4f8ff17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881782441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2881782441
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2129190952
Short name T287
Test name
Test status
Simulation time 4585870095 ps
CPU time 17.3 seconds
Started Jun 13 01:20:43 PM PDT 24
Finished Jun 13 01:21:02 PM PDT 24
Peak memory 212232 kb
Host smart-5f00ac6e-763a-4010-a94d-5981e0852073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129190952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2129190952
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.154543048
Short name T213
Test name
Test status
Simulation time 1393056019 ps
CPU time 13.06 seconds
Started Jun 13 01:20:34 PM PDT 24
Finished Jun 13 01:20:47 PM PDT 24
Peak memory 211228 kb
Host smart-9a97d8aa-e15c-491e-a9b6-76115dca34d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154543048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.154543048
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2012143155
Short name T230
Test name
Test status
Simulation time 1416449375 ps
CPU time 11.92 seconds
Started Jun 13 01:20:38 PM PDT 24
Finished Jun 13 01:20:50 PM PDT 24
Peak memory 213984 kb
Host smart-9e1ea066-5c37-4d67-9f9e-e3dc170ebbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012143155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2012143155
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.649221719
Short name T259
Test name
Test status
Simulation time 573684555 ps
CPU time 7.14 seconds
Started Jun 13 01:20:39 PM PDT 24
Finished Jun 13 01:20:46 PM PDT 24
Peak memory 211100 kb
Host smart-0df5a23a-4467-4fb5-b255-f712ecf14bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649221719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.649221719
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.4210751498
Short name T227
Test name
Test status
Simulation time 8897601998 ps
CPU time 336.81 seconds
Started Jun 13 01:20:43 PM PDT 24
Finished Jun 13 01:26:21 PM PDT 24
Peak memory 227608 kb
Host smart-033f4a6a-003d-402f-82b9-50dcbc42bfd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210751498 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.4210751498
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4293884466
Short name T238
Test name
Test status
Simulation time 3367093233 ps
CPU time 49.08 seconds
Started Jun 13 01:20:45 PM PDT 24
Finished Jun 13 01:21:35 PM PDT 24
Peak memory 211648 kb
Host smart-2cca3da1-19b7-4781-937f-62b969baef36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293884466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4293884466
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3919409709
Short name T218
Test name
Test status
Simulation time 693763332 ps
CPU time 9.82 seconds
Started Jun 13 01:20:42 PM PDT 24
Finished Jun 13 01:20:53 PM PDT 24
Peak memory 211880 kb
Host smart-3000eb67-4891-4a66-9cb8-d40e667a9fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919409709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3919409709
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2205461664
Short name T19
Test name
Test status
Simulation time 1814357102 ps
CPU time 16.07 seconds
Started Jun 13 01:20:43 PM PDT 24
Finished Jun 13 01:21:00 PM PDT 24
Peak memory 211328 kb
Host smart-2a1e8c2c-6540-4726-9637-46212ef28561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205461664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2205461664
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3877098134
Short name T250
Test name
Test status
Simulation time 2440106097 ps
CPU time 23.64 seconds
Started Jun 13 01:20:42 PM PDT 24
Finished Jun 13 01:21:07 PM PDT 24
Peak memory 213492 kb
Host smart-7a5b0ddf-4cd1-4431-b0e0-afaefcda3bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877098134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3877098134
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1434173356
Short name T1
Test name
Test status
Simulation time 23338780316 ps
CPU time 63.07 seconds
Started Jun 13 01:20:46 PM PDT 24
Finished Jun 13 01:21:50 PM PDT 24
Peak memory 219328 kb
Host smart-30c7206b-c664-45ec-99cd-25b6e2486bf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434173356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1434173356
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4145787789
Short name T276
Test name
Test status
Simulation time 4092683123 ps
CPU time 10.12 seconds
Started Jun 13 01:20:46 PM PDT 24
Finished Jun 13 01:20:57 PM PDT 24
Peak memory 211196 kb
Host smart-c687b8ff-97b8-43ae-b777-73d843149f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145787789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4145787789
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2309338233
Short name T202
Test name
Test status
Simulation time 26805646793 ps
CPU time 144.37 seconds
Started Jun 13 01:20:46 PM PDT 24
Finished Jun 13 01:23:11 PM PDT 24
Peak memory 237628 kb
Host smart-c8dc1366-affa-4ef7-911d-62edf2073e6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309338233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2309338233
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3093774664
Short name T126
Test name
Test status
Simulation time 348110555 ps
CPU time 9.89 seconds
Started Jun 13 01:20:45 PM PDT 24
Finished Jun 13 01:20:57 PM PDT 24
Peak memory 211784 kb
Host smart-3aabfba0-655c-4aba-9d1d-4973b9bdb79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093774664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3093774664
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1106016446
Short name T192
Test name
Test status
Simulation time 637170232 ps
CPU time 5.37 seconds
Started Jun 13 01:20:44 PM PDT 24
Finished Jun 13 01:20:50 PM PDT 24
Peak memory 211284 kb
Host smart-a0104a2a-afa4-4093-9d17-8174fbf21244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106016446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1106016446
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1372694600
Short name T364
Test name
Test status
Simulation time 1732564063 ps
CPU time 20.74 seconds
Started Jun 13 01:20:44 PM PDT 24
Finished Jun 13 01:21:06 PM PDT 24
Peak memory 213544 kb
Host smart-f1f09541-9487-4fb3-93bf-d73a59546e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372694600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1372694600
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.310116874
Short name T336
Test name
Test status
Simulation time 20596632296 ps
CPU time 54.85 seconds
Started Jun 13 01:20:52 PM PDT 24
Finished Jun 13 01:21:48 PM PDT 24
Peak memory 214592 kb
Host smart-4c6677d0-2a97-42fc-aafa-0cf89c71132a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310116874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.310116874
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1254636312
Short name T50
Test name
Test status
Simulation time 205111828791 ps
CPU time 1941.3 seconds
Started Jun 13 01:20:46 PM PDT 24
Finished Jun 13 01:53:09 PM PDT 24
Peak memory 236320 kb
Host smart-93c3f1fd-4a67-4e18-9956-920bd6417507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254636312 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1254636312
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.921663566
Short name T168
Test name
Test status
Simulation time 1073763427 ps
CPU time 7.86 seconds
Started Jun 13 01:19:43 PM PDT 24
Finished Jun 13 01:19:52 PM PDT 24
Peak memory 211132 kb
Host smart-9f35e55a-3adb-4536-87ad-3b15c3bfdd7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921663566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.921663566
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.777885877
Short name T45
Test name
Test status
Simulation time 46181347009 ps
CPU time 334.06 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:25:20 PM PDT 24
Peak memory 237016 kb
Host smart-4e346ec6-d41d-4e27-94ec-372e6da078ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777885877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.777885877
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1947348104
Short name T323
Test name
Test status
Simulation time 8245514670 ps
CPU time 12.52 seconds
Started Jun 13 01:19:44 PM PDT 24
Finished Jun 13 01:19:57 PM PDT 24
Peak memory 212580 kb
Host smart-416b2cdf-dd78-434e-8318-94ca40b1bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947348104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1947348104
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.397065085
Short name T190
Test name
Test status
Simulation time 8792653081 ps
CPU time 13.2 seconds
Started Jun 13 01:19:43 PM PDT 24
Finished Jun 13 01:19:58 PM PDT 24
Peak memory 211380 kb
Host smart-c903e76c-a069-4c6e-8a3b-d6bfd56d6b43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397065085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.397065085
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3045344138
Short name T25
Test name
Test status
Simulation time 319984098 ps
CPU time 51.25 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:20:37 PM PDT 24
Peak memory 235164 kb
Host smart-c0050c36-7bbd-4f15-b392-9006a179a8e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045344138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3045344138
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2126727637
Short name T164
Test name
Test status
Simulation time 3145567666 ps
CPU time 25.44 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:20:12 PM PDT 24
Peak memory 213576 kb
Host smart-9a8b5548-9cb4-44d1-9031-5e6052130fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126727637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2126727637
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3573725156
Short name T240
Test name
Test status
Simulation time 19698666197 ps
CPU time 92.28 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:21:18 PM PDT 24
Peak memory 217468 kb
Host smart-5b69df35-ef2b-44d8-868d-a3ff87d0d9c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573725156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3573725156
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3381787682
Short name T243
Test name
Test status
Simulation time 543947376 ps
CPU time 7.66 seconds
Started Jun 13 01:20:49 PM PDT 24
Finished Jun 13 01:20:59 PM PDT 24
Peak memory 211092 kb
Host smart-8534d8ec-00fa-449e-9526-2e08f449ba7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381787682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3381787682
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3343735098
Short name T22
Test name
Test status
Simulation time 131970472932 ps
CPU time 315.29 seconds
Started Jun 13 01:20:46 PM PDT 24
Finished Jun 13 01:26:02 PM PDT 24
Peak memory 212748 kb
Host smart-0bf8a34b-6113-40aa-a9d1-67ce2c2270bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343735098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3343735098
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1900114978
Short name T330
Test name
Test status
Simulation time 7315023033 ps
CPU time 12.36 seconds
Started Jun 13 01:20:49 PM PDT 24
Finished Jun 13 01:21:03 PM PDT 24
Peak memory 211356 kb
Host smart-c48ba472-86b7-4ce9-a2b9-5bcae16a3192
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900114978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1900114978
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1240790287
Short name T234
Test name
Test status
Simulation time 13054619657 ps
CPU time 32.28 seconds
Started Jun 13 01:20:42 PM PDT 24
Finished Jun 13 01:21:16 PM PDT 24
Peak memory 214104 kb
Host smart-91ddaf81-f81c-46b3-b33f-bca2903619b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240790287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1240790287
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.70015204
Short name T354
Test name
Test status
Simulation time 204759368 ps
CPU time 13.96 seconds
Started Jun 13 01:20:42 PM PDT 24
Finished Jun 13 01:20:57 PM PDT 24
Peak memory 213932 kb
Host smart-9f01b543-e40d-4ba3-a9c3-0da3f7f15116
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70015204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 20.rom_ctrl_stress_all.70015204
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3308427499
Short name T331
Test name
Test status
Simulation time 1795641543 ps
CPU time 15.32 seconds
Started Jun 13 01:20:50 PM PDT 24
Finished Jun 13 01:21:06 PM PDT 24
Peak memory 211092 kb
Host smart-5eccd0fe-6c73-4248-838c-825854cd76b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308427499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3308427499
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3396146858
Short name T134
Test name
Test status
Simulation time 27928867274 ps
CPU time 270.9 seconds
Started Jun 13 01:20:49 PM PDT 24
Finished Jun 13 01:25:21 PM PDT 24
Peak memory 227868 kb
Host smart-4087c132-7a0c-42e8-a739-435a0834dbd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396146858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3396146858
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3129565539
Short name T333
Test name
Test status
Simulation time 2381461851 ps
CPU time 24.79 seconds
Started Jun 13 01:20:50 PM PDT 24
Finished Jun 13 01:21:16 PM PDT 24
Peak memory 211264 kb
Host smart-3d737842-d0be-44ee-a593-63eac7e5b6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129565539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3129565539
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.512690753
Short name T32
Test name
Test status
Simulation time 706812324 ps
CPU time 9.67 seconds
Started Jun 13 01:20:51 PM PDT 24
Finished Jun 13 01:21:02 PM PDT 24
Peak memory 211276 kb
Host smart-5fab4641-fcbf-4b71-86b4-03c014b3dc83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512690753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.512690753
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1087247306
Short name T358
Test name
Test status
Simulation time 193239560 ps
CPU time 10.16 seconds
Started Jun 13 01:20:51 PM PDT 24
Finished Jun 13 01:21:02 PM PDT 24
Peak memory 213636 kb
Host smart-6c5fdf34-9c07-4e9d-bf9f-8c81b1d7b6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087247306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1087247306
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3176071704
Short name T219
Test name
Test status
Simulation time 54055636087 ps
CPU time 66.35 seconds
Started Jun 13 01:20:58 PM PDT 24
Finished Jun 13 01:22:05 PM PDT 24
Peak memory 219132 kb
Host smart-d66a41cf-6f04-4512-9d35-dca86d142c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176071704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3176071704
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1432012295
Short name T61
Test name
Test status
Simulation time 89218877 ps
CPU time 4.33 seconds
Started Jun 13 01:20:53 PM PDT 24
Finished Jun 13 01:20:57 PM PDT 24
Peak memory 211124 kb
Host smart-1e2d0136-9f56-4648-b4e4-0ed89f94a0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432012295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1432012295
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.838556871
Short name T180
Test name
Test status
Simulation time 4237242383 ps
CPU time 123.28 seconds
Started Jun 13 01:20:52 PM PDT 24
Finished Jun 13 01:22:56 PM PDT 24
Peak memory 212540 kb
Host smart-ee20e857-d86a-42e8-a15f-163c9db06ead
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838556871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.838556871
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.610392225
Short name T125
Test name
Test status
Simulation time 7290210445 ps
CPU time 21.63 seconds
Started Jun 13 01:20:51 PM PDT 24
Finished Jun 13 01:21:13 PM PDT 24
Peak memory 212456 kb
Host smart-3c858235-dbf8-4086-a9b6-3f5c3368285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610392225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.610392225
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2094251689
Short name T135
Test name
Test status
Simulation time 6967358765 ps
CPU time 15.59 seconds
Started Jun 13 01:20:58 PM PDT 24
Finished Jun 13 01:21:15 PM PDT 24
Peak memory 211148 kb
Host smart-b6fbd3c9-72f7-4291-858e-999ba08ffefa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2094251689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2094251689
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1767546813
Short name T268
Test name
Test status
Simulation time 186120499 ps
CPU time 10.5 seconds
Started Jun 13 01:20:49 PM PDT 24
Finished Jun 13 01:21:01 PM PDT 24
Peak memory 213912 kb
Host smart-91473ea5-e694-40f4-a461-d7dbd6a12e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767546813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1767546813
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2477522410
Short name T228
Test name
Test status
Simulation time 2547720703 ps
CPU time 9.64 seconds
Started Jun 13 01:20:51 PM PDT 24
Finished Jun 13 01:21:02 PM PDT 24
Peak memory 211296 kb
Host smart-60c634bd-da9a-44c5-872c-a6442c356d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477522410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2477522410
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3940119774
Short name T2
Test name
Test status
Simulation time 2392917822 ps
CPU time 12.98 seconds
Started Jun 13 01:20:51 PM PDT 24
Finished Jun 13 01:21:05 PM PDT 24
Peak memory 211148 kb
Host smart-e6f7baa7-d908-44a5-8108-90b98dce9441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940119774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3940119774
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4225248506
Short name T191
Test name
Test status
Simulation time 311529592469 ps
CPU time 281.15 seconds
Started Jun 13 01:20:51 PM PDT 24
Finished Jun 13 01:25:33 PM PDT 24
Peak memory 234928 kb
Host smart-6954b847-c6a5-455a-9125-8182000c2988
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225248506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4225248506
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2469190266
Short name T217
Test name
Test status
Simulation time 7223575861 ps
CPU time 30.64 seconds
Started Jun 13 01:20:50 PM PDT 24
Finished Jun 13 01:21:22 PM PDT 24
Peak memory 212516 kb
Host smart-502036ee-50cf-46e0-8e0d-b0bb91c4d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469190266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2469190266
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.303502099
Short name T11
Test name
Test status
Simulation time 145413790 ps
CPU time 5.77 seconds
Started Jun 13 01:20:51 PM PDT 24
Finished Jun 13 01:20:58 PM PDT 24
Peak memory 211284 kb
Host smart-b2e65220-e8d1-4f92-9948-c5f28326ade9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303502099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.303502099
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1718604071
Short name T315
Test name
Test status
Simulation time 2767179092 ps
CPU time 30.77 seconds
Started Jun 13 01:20:58 PM PDT 24
Finished Jun 13 01:21:30 PM PDT 24
Peak memory 213248 kb
Host smart-b4fba3f7-11ba-40b7-b429-71585c7b3028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718604071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1718604071
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3860758622
Short name T139
Test name
Test status
Simulation time 1806929697 ps
CPU time 15.86 seconds
Started Jun 13 01:20:57 PM PDT 24
Finished Jun 13 01:21:13 PM PDT 24
Peak memory 211132 kb
Host smart-c5a91494-4b35-4c2b-9674-4696591627fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860758622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3860758622
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2703338918
Short name T363
Test name
Test status
Simulation time 1233130998 ps
CPU time 79.57 seconds
Started Jun 13 01:20:56 PM PDT 24
Finished Jun 13 01:22:17 PM PDT 24
Peak memory 236488 kb
Host smart-d3184aac-d93f-4334-91ea-8f7f9156214c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703338918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2703338918
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3241815196
Short name T141
Test name
Test status
Simulation time 1459755026 ps
CPU time 18.84 seconds
Started Jun 13 01:20:56 PM PDT 24
Finished Jun 13 01:21:15 PM PDT 24
Peak memory 211840 kb
Host smart-55447f2e-24d2-4406-a94f-388ed596d21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241815196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3241815196
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3097296233
Short name T133
Test name
Test status
Simulation time 133856348 ps
CPU time 5.8 seconds
Started Jun 13 01:20:57 PM PDT 24
Finished Jun 13 01:21:04 PM PDT 24
Peak memory 211292 kb
Host smart-95874b92-47ff-491c-b187-bb369b48588b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097296233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3097296233
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3338252399
Short name T338
Test name
Test status
Simulation time 4005917825 ps
CPU time 33 seconds
Started Jun 13 01:20:58 PM PDT 24
Finished Jun 13 01:21:32 PM PDT 24
Peak memory 213172 kb
Host smart-da9c9f4c-35f4-4069-af99-33c76cc596b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338252399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3338252399
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2270566944
Short name T216
Test name
Test status
Simulation time 1483901607 ps
CPU time 17.33 seconds
Started Jun 13 01:20:59 PM PDT 24
Finished Jun 13 01:21:17 PM PDT 24
Peak memory 216528 kb
Host smart-1adce543-ffa3-46aa-beb5-53f0267c1c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270566944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2270566944
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1426246852
Short name T160
Test name
Test status
Simulation time 3286436855 ps
CPU time 14.2 seconds
Started Jun 13 01:20:57 PM PDT 24
Finished Jun 13 01:21:12 PM PDT 24
Peak memory 211212 kb
Host smart-956bd8fa-372c-42af-9221-47de15f69fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426246852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1426246852
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3759300735
Short name T207
Test name
Test status
Simulation time 52306427457 ps
CPU time 316.27 seconds
Started Jun 13 01:20:57 PM PDT 24
Finished Jun 13 01:26:14 PM PDT 24
Peak memory 240624 kb
Host smart-fb066399-15fd-4c11-9581-53dc3c482387
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759300735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3759300735
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1058243999
Short name T318
Test name
Test status
Simulation time 2214105261 ps
CPU time 13.29 seconds
Started Jun 13 01:20:57 PM PDT 24
Finished Jun 13 01:21:11 PM PDT 24
Peak memory 212192 kb
Host smart-f51b222b-f2eb-481e-8b55-2974aeb5d992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058243999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1058243999
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2955890762
Short name T305
Test name
Test status
Simulation time 716770228 ps
CPU time 6.78 seconds
Started Jun 13 01:20:58 PM PDT 24
Finished Jun 13 01:21:06 PM PDT 24
Peak memory 211292 kb
Host smart-fe9dbd7b-b50c-41f4-8d3f-a953576d2656
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955890762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2955890762
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3854984566
Short name T162
Test name
Test status
Simulation time 2580327614 ps
CPU time 24.86 seconds
Started Jun 13 01:20:56 PM PDT 24
Finished Jun 13 01:21:22 PM PDT 24
Peak memory 213276 kb
Host smart-7687dc4f-1124-48f7-8905-18bb725d7948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854984566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3854984566
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.596641594
Short name T157
Test name
Test status
Simulation time 3548398930 ps
CPU time 15.29 seconds
Started Jun 13 01:20:57 PM PDT 24
Finished Jun 13 01:21:14 PM PDT 24
Peak memory 212452 kb
Host smart-3830b2df-4159-499b-b9b0-b2cc0bccc457
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596641594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.596641594
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.154826045
Short name T255
Test name
Test status
Simulation time 5268362081 ps
CPU time 11.89 seconds
Started Jun 13 01:21:03 PM PDT 24
Finished Jun 13 01:21:16 PM PDT 24
Peak memory 211060 kb
Host smart-8731150a-7f91-441a-9a40-0103e4500e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154826045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.154826045
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.441567661
Short name T335
Test name
Test status
Simulation time 78418554019 ps
CPU time 206.72 seconds
Started Jun 13 01:21:05 PM PDT 24
Finished Jun 13 01:24:33 PM PDT 24
Peak memory 237660 kb
Host smart-72697b96-c09e-48ce-8007-6c8763b06877
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441567661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.441567661
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4280647188
Short name T177
Test name
Test status
Simulation time 754806290 ps
CPU time 9.17 seconds
Started Jun 13 01:21:13 PM PDT 24
Finished Jun 13 01:21:23 PM PDT 24
Peak memory 211584 kb
Host smart-1fe453a4-5165-40ee-9f2b-9804083c2ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280647188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4280647188
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1581742962
Short name T346
Test name
Test status
Simulation time 8860476747 ps
CPU time 12.44 seconds
Started Jun 13 01:21:05 PM PDT 24
Finished Jun 13 01:21:18 PM PDT 24
Peak memory 211368 kb
Host smart-b91dcdf5-7f52-4fef-8d4d-0fe8dcfd5117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581742962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1581742962
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2207969440
Short name T70
Test name
Test status
Simulation time 3578774742 ps
CPU time 14.69 seconds
Started Jun 13 01:20:56 PM PDT 24
Finished Jun 13 01:21:12 PM PDT 24
Peak memory 212936 kb
Host smart-b1239a22-0e02-4817-bd1f-b934e09b3784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207969440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2207969440
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3544707750
Short name T324
Test name
Test status
Simulation time 4491591756 ps
CPU time 47.29 seconds
Started Jun 13 01:21:05 PM PDT 24
Finished Jun 13 01:21:53 PM PDT 24
Peak memory 213044 kb
Host smart-21bef123-17d1-41bc-aefe-a62fd508096c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544707750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3544707750
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2860874754
Short name T15
Test name
Test status
Simulation time 69453843499 ps
CPU time 2917.78 seconds
Started Jun 13 01:21:04 PM PDT 24
Finished Jun 13 02:09:44 PM PDT 24
Peak memory 235824 kb
Host smart-46afebc4-eba8-41c3-90ae-0c79f7483b0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860874754 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2860874754
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1337761677
Short name T225
Test name
Test status
Simulation time 4569658055 ps
CPU time 11.5 seconds
Started Jun 13 01:21:05 PM PDT 24
Finished Jun 13 01:21:17 PM PDT 24
Peak memory 211196 kb
Host smart-383f89bf-8e5f-4f1e-8e88-56102b22463b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337761677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1337761677
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2253523215
Short name T340
Test name
Test status
Simulation time 348144577 ps
CPU time 9.19 seconds
Started Jun 13 01:21:13 PM PDT 24
Finished Jun 13 01:21:23 PM PDT 24
Peak memory 211756 kb
Host smart-3cb2a260-884f-43aa-8be7-96fd13d28588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253523215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2253523215
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3241643549
Short name T334
Test name
Test status
Simulation time 564595543 ps
CPU time 6.54 seconds
Started Jun 13 01:21:09 PM PDT 24
Finished Jun 13 01:21:16 PM PDT 24
Peak memory 211292 kb
Host smart-a3ef7b63-31db-4b6e-8451-3e40abb77e0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241643549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3241643549
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2625453142
Short name T17
Test name
Test status
Simulation time 8941023013 ps
CPU time 25.46 seconds
Started Jun 13 01:21:03 PM PDT 24
Finished Jun 13 01:21:29 PM PDT 24
Peak memory 214092 kb
Host smart-5f955bbe-dab6-4efd-8272-feaa7f1d3192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625453142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2625453142
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4180793548
Short name T21
Test name
Test status
Simulation time 127454262 ps
CPU time 6.25 seconds
Started Jun 13 01:21:12 PM PDT 24
Finished Jun 13 01:21:19 PM PDT 24
Peak memory 211040 kb
Host smart-43b809ba-77cd-45c7-83e8-45affa6650a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180793548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4180793548
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.208070531
Short name T47
Test name
Test status
Simulation time 92423676436 ps
CPU time 3468.19 seconds
Started Jun 13 01:21:04 PM PDT 24
Finished Jun 13 02:18:53 PM PDT 24
Peak memory 244076 kb
Host smart-e136f881-da61-4328-b499-74abb9690c99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208070531 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.208070531
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.338580821
Short name T345
Test name
Test status
Simulation time 859552361 ps
CPU time 5.76 seconds
Started Jun 13 01:21:13 PM PDT 24
Finished Jun 13 01:21:20 PM PDT 24
Peak memory 211084 kb
Host smart-2a8e0e39-5265-4c5c-8581-264a20be195d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338580821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.338580821
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3584223494
Short name T193
Test name
Test status
Simulation time 17735120916 ps
CPU time 193.99 seconds
Started Jun 13 01:21:04 PM PDT 24
Finished Jun 13 01:24:19 PM PDT 24
Peak memory 213612 kb
Host smart-ec2c9cf9-be49-4ac0-8ab2-05faf02af28d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584223494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3584223494
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.853438400
Short name T229
Test name
Test status
Simulation time 767829494 ps
CPU time 15.24 seconds
Started Jun 13 01:21:05 PM PDT 24
Finished Jun 13 01:21:22 PM PDT 24
Peak memory 211764 kb
Host smart-bd15a055-9821-4a28-a53a-77ca73480d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853438400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.853438400
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4264742710
Short name T94
Test name
Test status
Simulation time 1251323797 ps
CPU time 7.45 seconds
Started Jun 13 01:21:05 PM PDT 24
Finished Jun 13 01:21:14 PM PDT 24
Peak memory 211284 kb
Host smart-298858fc-ef6e-40d7-8604-ba8b9526d603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264742710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4264742710
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.363082233
Short name T370
Test name
Test status
Simulation time 18149389973 ps
CPU time 31.23 seconds
Started Jun 13 01:21:05 PM PDT 24
Finished Jun 13 01:21:37 PM PDT 24
Peak memory 214344 kb
Host smart-e0058b6d-63b4-4183-a391-4d096e5a1a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363082233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.363082233
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3647617646
Short name T223
Test name
Test status
Simulation time 841669140 ps
CPU time 15.35 seconds
Started Jun 13 01:21:02 PM PDT 24
Finished Jun 13 01:21:18 PM PDT 24
Peak memory 213536 kb
Host smart-e0e7a139-250b-4ea2-b8f4-ec989e58a968
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647617646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3647617646
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3294711953
Short name T171
Test name
Test status
Simulation time 1123875207 ps
CPU time 5.26 seconds
Started Jun 13 01:21:16 PM PDT 24
Finished Jun 13 01:21:22 PM PDT 24
Peak memory 211116 kb
Host smart-08cd9a6f-c4e3-416e-b439-c48ff152e0a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294711953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3294711953
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3991283040
Short name T34
Test name
Test status
Simulation time 28121859763 ps
CPU time 204.07 seconds
Started Jun 13 01:21:11 PM PDT 24
Finished Jun 13 01:24:35 PM PDT 24
Peak memory 236544 kb
Host smart-e9cc5a26-4ac5-4ff5-ba48-c18f556fd5ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991283040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3991283040
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3717292888
Short name T280
Test name
Test status
Simulation time 5508112445 ps
CPU time 34.36 seconds
Started Jun 13 01:21:16 PM PDT 24
Finished Jun 13 01:21:52 PM PDT 24
Peak memory 212088 kb
Host smart-40c62280-43e5-4736-ae48-2db292afca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717292888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3717292888
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4015028836
Short name T226
Test name
Test status
Simulation time 3711956718 ps
CPU time 15.46 seconds
Started Jun 13 01:21:12 PM PDT 24
Finished Jun 13 01:21:29 PM PDT 24
Peak memory 211148 kb
Host smart-dbe5409f-8f87-4380-a269-c751520a49b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015028836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4015028836
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1473919183
Short name T267
Test name
Test status
Simulation time 5242324856 ps
CPU time 17.82 seconds
Started Jun 13 01:21:10 PM PDT 24
Finished Jun 13 01:21:28 PM PDT 24
Peak memory 214164 kb
Host smart-24d95fbe-2149-4139-8897-7eeeb4965e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473919183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1473919183
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.54606826
Short name T174
Test name
Test status
Simulation time 9709029137 ps
CPU time 45.46 seconds
Started Jun 13 01:21:12 PM PDT 24
Finished Jun 13 01:21:58 PM PDT 24
Peak memory 215588 kb
Host smart-01b2a2d5-f12d-4a37-945b-7be1e1d2bac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54606826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.rom_ctrl_stress_all.54606826
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3446168201
Short name T317
Test name
Test status
Simulation time 23277829324 ps
CPU time 16.2 seconds
Started Jun 13 01:19:50 PM PDT 24
Finished Jun 13 01:20:06 PM PDT 24
Peak memory 211136 kb
Host smart-07d30609-fac4-4a07-9bc5-a24101d40f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446168201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3446168201
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3263921580
Short name T251
Test name
Test status
Simulation time 109390257454 ps
CPU time 524.92 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:28:31 PM PDT 24
Peak memory 237556 kb
Host smart-356c65db-c459-4fad-bc67-75ca1eec25e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263921580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3263921580
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.799282005
Short name T311
Test name
Test status
Simulation time 15562170302 ps
CPU time 31.78 seconds
Started Jun 13 01:19:44 PM PDT 24
Finished Jun 13 01:20:16 PM PDT 24
Peak memory 212184 kb
Host smart-64966d69-0af9-4429-a0ea-3809f85cb18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799282005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.799282005
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3821452189
Short name T173
Test name
Test status
Simulation time 1988590245 ps
CPU time 16.72 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:20:02 PM PDT 24
Peak memory 211244 kb
Host smart-49b9d3e8-32c7-40d1-8cd6-5a5cb02aecd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821452189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3821452189
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1932965919
Short name T26
Test name
Test status
Simulation time 1206635758 ps
CPU time 101.68 seconds
Started Jun 13 01:19:50 PM PDT 24
Finished Jun 13 01:21:32 PM PDT 24
Peak memory 233700 kb
Host smart-d8bf7fa3-03e9-4249-844a-ca48980e967b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932965919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1932965919
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3418268610
Short name T357
Test name
Test status
Simulation time 11175292575 ps
CPU time 27.16 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:20:13 PM PDT 24
Peak memory 213812 kb
Host smart-f53d6718-9fb7-41bb-973c-fc690c521c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418268610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3418268610
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1040963892
Short name T361
Test name
Test status
Simulation time 2469129510 ps
CPU time 30.68 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:20:16 PM PDT 24
Peak memory 215012 kb
Host smart-6398a4e9-49b9-44e0-9da7-7059fc378393
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040963892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1040963892
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.4095769650
Short name T206
Test name
Test status
Simulation time 10222558221 ps
CPU time 14.88 seconds
Started Jun 13 01:21:28 PM PDT 24
Finished Jun 13 01:21:44 PM PDT 24
Peak memory 211180 kb
Host smart-8d68edbe-68aa-47bd-a2ad-1af4279deada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095769650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.4095769650
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.565678033
Short name T319
Test name
Test status
Simulation time 81058378962 ps
CPU time 365.52 seconds
Started Jun 13 01:21:28 PM PDT 24
Finished Jun 13 01:27:34 PM PDT 24
Peak memory 236292 kb
Host smart-7befcb0f-c884-4fc7-9d2f-8ac8dae457a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565678033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.565678033
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1216046189
Short name T159
Test name
Test status
Simulation time 666217996 ps
CPU time 9.68 seconds
Started Jun 13 01:21:15 PM PDT 24
Finished Jun 13 01:21:26 PM PDT 24
Peak memory 211912 kb
Host smart-85e7f7f9-eb21-421f-891e-c069c6bf47bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216046189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1216046189
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3588483289
Short name T263
Test name
Test status
Simulation time 3404682955 ps
CPU time 15.4 seconds
Started Jun 13 01:21:28 PM PDT 24
Finished Jun 13 01:21:44 PM PDT 24
Peak memory 211340 kb
Host smart-8538f608-575c-44d1-a6fe-38f423bbb192
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588483289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3588483289
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.522650925
Short name T129
Test name
Test status
Simulation time 270010340 ps
CPU time 12.04 seconds
Started Jun 13 01:21:23 PM PDT 24
Finished Jun 13 01:21:36 PM PDT 24
Peak memory 213556 kb
Host smart-c356d4d1-4db1-400a-b0d6-10d48ad2322c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522650925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.522650925
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1439004615
Short name T266
Test name
Test status
Simulation time 14285122533 ps
CPU time 38.66 seconds
Started Jun 13 01:21:16 PM PDT 24
Finished Jun 13 01:21:55 PM PDT 24
Peak memory 213984 kb
Host smart-2169155d-82ad-495b-90bc-5bcf3d1bb224
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439004615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1439004615
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2537673870
Short name T146
Test name
Test status
Simulation time 346832509 ps
CPU time 4.29 seconds
Started Jun 13 01:21:27 PM PDT 24
Finished Jun 13 01:21:32 PM PDT 24
Peak memory 211120 kb
Host smart-4f6353eb-395b-401f-9160-0672d40265fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537673870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2537673870
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2328660372
Short name T182
Test name
Test status
Simulation time 5948906639 ps
CPU time 147.17 seconds
Started Jun 13 01:21:14 PM PDT 24
Finished Jun 13 01:23:43 PM PDT 24
Peak memory 225516 kb
Host smart-1b306b9a-c7a4-45ed-a354-7878191ac4e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328660372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2328660372
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1843624181
Short name T175
Test name
Test status
Simulation time 173550746 ps
CPU time 9.45 seconds
Started Jun 13 01:21:17 PM PDT 24
Finished Jun 13 01:21:28 PM PDT 24
Peak memory 211804 kb
Host smart-8f66b622-a4dd-40d3-9117-1ab080d14239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843624181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1843624181
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1433046597
Short name T4
Test name
Test status
Simulation time 27744136125 ps
CPU time 16.49 seconds
Started Jun 13 01:21:20 PM PDT 24
Finished Jun 13 01:21:37 PM PDT 24
Peak memory 211356 kb
Host smart-ae86d43f-7469-4bbc-813c-1a01d8fc3970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433046597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1433046597
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1599387213
Short name T269
Test name
Test status
Simulation time 3141724089 ps
CPU time 28.69 seconds
Started Jun 13 01:21:17 PM PDT 24
Finished Jun 13 01:21:46 PM PDT 24
Peak memory 213656 kb
Host smart-d1519a81-97b6-4553-b38f-40b2c2f5a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599387213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1599387213
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1883107836
Short name T313
Test name
Test status
Simulation time 4836777221 ps
CPU time 45.29 seconds
Started Jun 13 01:21:17 PM PDT 24
Finished Jun 13 01:22:03 PM PDT 24
Peak memory 214084 kb
Host smart-2533d436-1df3-48cc-8632-0dd337d874e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883107836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1883107836
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.392283122
Short name T224
Test name
Test status
Simulation time 347619437 ps
CPU time 4.41 seconds
Started Jun 13 01:21:24 PM PDT 24
Finished Jun 13 01:21:29 PM PDT 24
Peak memory 211132 kb
Host smart-698b0cb0-0417-425d-b807-17ac3a742c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392283122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.392283122
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2782759381
Short name T158
Test name
Test status
Simulation time 25253229598 ps
CPU time 267.07 seconds
Started Jun 13 01:21:23 PM PDT 24
Finished Jun 13 01:25:51 PM PDT 24
Peak memory 237684 kb
Host smart-fd521d4c-7c43-4d54-b660-88f169e47c87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782759381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2782759381
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1567389115
Short name T178
Test name
Test status
Simulation time 982041062 ps
CPU time 16.62 seconds
Started Jun 13 01:21:28 PM PDT 24
Finished Jun 13 01:21:46 PM PDT 24
Peak memory 211828 kb
Host smart-0886b36a-42a3-41f5-8645-f2eb359e628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567389115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1567389115
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1648897631
Short name T262
Test name
Test status
Simulation time 375733718 ps
CPU time 5.63 seconds
Started Jun 13 01:21:24 PM PDT 24
Finished Jun 13 01:21:30 PM PDT 24
Peak memory 211284 kb
Host smart-b76f1d94-7b6a-41b4-8b54-ff2af1f76256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648897631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1648897631
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2413319552
Short name T90
Test name
Test status
Simulation time 9558332892 ps
CPU time 25.12 seconds
Started Jun 13 01:21:28 PM PDT 24
Finished Jun 13 01:21:54 PM PDT 24
Peak memory 214048 kb
Host smart-bfcf61f4-331a-4390-9945-8f5fd2ac1e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413319552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2413319552
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4055091670
Short name T209
Test name
Test status
Simulation time 18861423192 ps
CPU time 50.69 seconds
Started Jun 13 01:21:24 PM PDT 24
Finished Jun 13 01:22:15 PM PDT 24
Peak memory 215724 kb
Host smart-3e25e32e-a295-417b-81ea-5b4a09e0a39b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055091670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4055091670
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.539358311
Short name T321
Test name
Test status
Simulation time 3443214641 ps
CPU time 8.62 seconds
Started Jun 13 01:21:25 PM PDT 24
Finished Jun 13 01:21:34 PM PDT 24
Peak memory 211196 kb
Host smart-030a71e8-1b6b-4106-a0a0-b7b07ccf8276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539358311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.539358311
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2061663069
Short name T304
Test name
Test status
Simulation time 1796124011 ps
CPU time 112.94 seconds
Started Jun 13 01:21:28 PM PDT 24
Finished Jun 13 01:23:22 PM PDT 24
Peak memory 228332 kb
Host smart-6dbd2331-47f5-40b6-9836-bedf3bf04a02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061663069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2061663069
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4036509037
Short name T198
Test name
Test status
Simulation time 2344211023 ps
CPU time 24.65 seconds
Started Jun 13 01:21:26 PM PDT 24
Finished Jun 13 01:21:51 PM PDT 24
Peak memory 211832 kb
Host smart-aae73667-ca56-4c31-94d9-fe674457a8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036509037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4036509037
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3982032292
Short name T355
Test name
Test status
Simulation time 311763839 ps
CPU time 5.45 seconds
Started Jun 13 01:21:23 PM PDT 24
Finished Jun 13 01:21:29 PM PDT 24
Peak memory 211248 kb
Host smart-d3b07362-1117-4171-8022-2b8ea8572fef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982032292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3982032292
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2565500066
Short name T359
Test name
Test status
Simulation time 17006684705 ps
CPU time 39.75 seconds
Started Jun 13 01:21:23 PM PDT 24
Finished Jun 13 01:22:04 PM PDT 24
Peak memory 213828 kb
Host smart-fbf6cf8b-c72b-4d9f-ba34-2b4a4f0fdae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565500066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2565500066
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2854169851
Short name T271
Test name
Test status
Simulation time 1378133829 ps
CPU time 4.47 seconds
Started Jun 13 01:21:32 PM PDT 24
Finished Jun 13 01:21:37 PM PDT 24
Peak memory 210972 kb
Host smart-b167f88d-2af1-42e4-8706-17e3d6259aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854169851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2854169851
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.518962475
Short name T127
Test name
Test status
Simulation time 35644024422 ps
CPU time 374.68 seconds
Started Jun 13 01:21:32 PM PDT 24
Finished Jun 13 01:27:47 PM PDT 24
Peak memory 234740 kb
Host smart-b65691d4-38b1-4bcb-adc1-ddcccfcc8eb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518962475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.518962475
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1315540397
Short name T272
Test name
Test status
Simulation time 5088545021 ps
CPU time 25.08 seconds
Started Jun 13 01:21:30 PM PDT 24
Finished Jun 13 01:21:55 PM PDT 24
Peak memory 212144 kb
Host smart-dcaee9c0-17e2-4be5-a97e-0c632ab2b02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315540397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1315540397
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1113539322
Short name T100
Test name
Test status
Simulation time 4239126992 ps
CPU time 17.42 seconds
Started Jun 13 01:21:33 PM PDT 24
Finished Jun 13 01:21:52 PM PDT 24
Peak memory 211364 kb
Host smart-9534594d-29d4-4269-907a-3811d7c0207f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113539322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1113539322
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3131640685
Short name T295
Test name
Test status
Simulation time 9428309208 ps
CPU time 27.41 seconds
Started Jun 13 01:21:30 PM PDT 24
Finished Jun 13 01:21:58 PM PDT 24
Peak memory 212552 kb
Host smart-add0c50d-7e7f-4895-af0c-76e05d6f2107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131640685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3131640685
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1774052015
Short name T176
Test name
Test status
Simulation time 997723728 ps
CPU time 13.79 seconds
Started Jun 13 01:21:30 PM PDT 24
Finished Jun 13 01:21:45 PM PDT 24
Peak memory 212876 kb
Host smart-bc9fbc13-956b-4757-adb3-3ac29ba873d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774052015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1774052015
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3308192003
Short name T43
Test name
Test status
Simulation time 1643160969 ps
CPU time 14.04 seconds
Started Jun 13 01:21:32 PM PDT 24
Finished Jun 13 01:21:47 PM PDT 24
Peak memory 211124 kb
Host smart-bece5cd2-b596-40b2-94e9-15ce0a0d8463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308192003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3308192003
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2181583427
Short name T265
Test name
Test status
Simulation time 2964565963 ps
CPU time 14.73 seconds
Started Jun 13 01:21:31 PM PDT 24
Finished Jun 13 01:21:46 PM PDT 24
Peak memory 212276 kb
Host smart-7becac7e-7683-48ba-b8c4-2c46f68b33b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181583427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2181583427
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.595700382
Short name T148
Test name
Test status
Simulation time 96051642 ps
CPU time 5.41 seconds
Started Jun 13 01:21:30 PM PDT 24
Finished Jun 13 01:21:36 PM PDT 24
Peak memory 211244 kb
Host smart-e4b48cf2-21b5-4779-a2de-2c3691a013ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595700382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.595700382
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2134196185
Short name T367
Test name
Test status
Simulation time 405127541 ps
CPU time 10.37 seconds
Started Jun 13 01:21:31 PM PDT 24
Finished Jun 13 01:21:42 PM PDT 24
Peak memory 213440 kb
Host smart-ab26ce1f-2568-4e62-85ca-3262a67a0b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134196185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2134196185
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.96391255
Short name T170
Test name
Test status
Simulation time 7080762535 ps
CPU time 32.22 seconds
Started Jun 13 01:21:37 PM PDT 24
Finished Jun 13 01:22:10 PM PDT 24
Peak memory 214164 kb
Host smart-3e114dfc-aa66-4559-a58b-7e1ff0a59cd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96391255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 35.rom_ctrl_stress_all.96391255
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4077483499
Short name T285
Test name
Test status
Simulation time 3308939015 ps
CPU time 9.37 seconds
Started Jun 13 01:21:39 PM PDT 24
Finished Jun 13 01:21:49 PM PDT 24
Peak memory 211176 kb
Host smart-ff8aa3ac-a907-4012-b253-88b445f8f863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077483499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4077483499
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2347599458
Short name T200
Test name
Test status
Simulation time 7489167015 ps
CPU time 108.52 seconds
Started Jun 13 01:21:38 PM PDT 24
Finished Jun 13 01:23:27 PM PDT 24
Peak memory 234708 kb
Host smart-063675c2-da41-4ea0-9e80-405f1f17ef32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347599458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2347599458
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3344772669
Short name T165
Test name
Test status
Simulation time 8778320524 ps
CPU time 19.11 seconds
Started Jun 13 01:21:41 PM PDT 24
Finished Jun 13 01:22:00 PM PDT 24
Peak memory 211272 kb
Host smart-037d00d3-15b8-4f1f-ac4c-daa3039604ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344772669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3344772669
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1353244034
Short name T232
Test name
Test status
Simulation time 1693921970 ps
CPU time 15.01 seconds
Started Jun 13 01:21:39 PM PDT 24
Finished Jun 13 01:21:55 PM PDT 24
Peak memory 211284 kb
Host smart-28d8d38b-165f-4096-9611-d1babda6c9db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353244034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1353244034
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1706650807
Short name T154
Test name
Test status
Simulation time 4636149113 ps
CPU time 24.39 seconds
Started Jun 13 01:21:36 PM PDT 24
Finished Jun 13 01:22:01 PM PDT 24
Peak memory 213592 kb
Host smart-e6e72518-8fd3-4ca2-8b16-7e6a091f666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706650807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1706650807
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2898925386
Short name T130
Test name
Test status
Simulation time 13617262171 ps
CPU time 66.35 seconds
Started Jun 13 01:21:36 PM PDT 24
Finished Jun 13 01:22:43 PM PDT 24
Peak memory 214420 kb
Host smart-f7aff7e5-2546-4f54-91d4-e128e786c342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898925386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2898925386
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3201648307
Short name T60
Test name
Test status
Simulation time 85474989 ps
CPU time 4.37 seconds
Started Jun 13 01:21:45 PM PDT 24
Finished Jun 13 01:21:51 PM PDT 24
Peak memory 211144 kb
Host smart-5c70ec76-7c5d-4074-9c77-5d0491e97c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201648307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3201648307
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1541427210
Short name T39
Test name
Test status
Simulation time 51256495962 ps
CPU time 232.01 seconds
Started Jun 13 01:21:43 PM PDT 24
Finished Jun 13 01:25:36 PM PDT 24
Peak memory 224972 kb
Host smart-791dd0ff-a7a1-45cd-883f-d5d5b9612e1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541427210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1541427210
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.223772613
Short name T41
Test name
Test status
Simulation time 2748291041 ps
CPU time 26.29 seconds
Started Jun 13 01:21:45 PM PDT 24
Finished Jun 13 01:22:13 PM PDT 24
Peak memory 211988 kb
Host smart-3a9288b4-011c-4bfc-a8c0-7f14667991cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223772613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.223772613
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2539363474
Short name T308
Test name
Test status
Simulation time 1597566957 ps
CPU time 14.24 seconds
Started Jun 13 01:21:41 PM PDT 24
Finished Jun 13 01:21:56 PM PDT 24
Peak memory 211284 kb
Host smart-161ca175-193d-4c54-938b-fc5fc1c2a32d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539363474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2539363474
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1566245657
Short name T298
Test name
Test status
Simulation time 8258446185 ps
CPU time 43.06 seconds
Started Jun 13 01:21:36 PM PDT 24
Finished Jun 13 01:22:20 PM PDT 24
Peak memory 213756 kb
Host smart-d327f880-89bf-4b28-8d63-4cc27694f0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566245657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1566245657
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2329438326
Short name T183
Test name
Test status
Simulation time 125414927 ps
CPU time 6.36 seconds
Started Jun 13 01:21:38 PM PDT 24
Finished Jun 13 01:21:45 PM PDT 24
Peak memory 211240 kb
Host smart-3429993d-ea91-4ba2-a2c2-a5db149cb665
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329438326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2329438326
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2002130177
Short name T48
Test name
Test status
Simulation time 53087977349 ps
CPU time 6963.22 seconds
Started Jun 13 01:21:44 PM PDT 24
Finished Jun 13 03:17:49 PM PDT 24
Peak memory 235832 kb
Host smart-79ceb881-212a-45e5-b2bb-89b62e11ebda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002130177 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2002130177
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1798167125
Short name T310
Test name
Test status
Simulation time 88061395 ps
CPU time 4.22 seconds
Started Jun 13 01:21:43 PM PDT 24
Finished Jun 13 01:21:48 PM PDT 24
Peak memory 211124 kb
Host smart-f7059856-ceb3-42dc-bcd4-04e3b172f47a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798167125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1798167125
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1522920976
Short name T33
Test name
Test status
Simulation time 186950417337 ps
CPU time 324.01 seconds
Started Jun 13 01:21:43 PM PDT 24
Finished Jun 13 01:27:08 PM PDT 24
Peak memory 213616 kb
Host smart-3f46cd9f-f4f8-49e3-8ee7-6bf649daa7f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522920976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1522920976
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3441523587
Short name T297
Test name
Test status
Simulation time 3613932897 ps
CPU time 18.97 seconds
Started Jun 13 01:21:47 PM PDT 24
Finished Jun 13 01:22:07 PM PDT 24
Peak memory 211832 kb
Host smart-31eebf53-dd20-4add-8fbe-921cddf74ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441523587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3441523587
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2557579819
Short name T270
Test name
Test status
Simulation time 789014938 ps
CPU time 10.6 seconds
Started Jun 13 01:21:45 PM PDT 24
Finished Jun 13 01:21:57 PM PDT 24
Peak memory 211316 kb
Host smart-1d672951-dad9-4e80-93c2-4b57618638b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557579819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2557579819
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3038110439
Short name T300
Test name
Test status
Simulation time 13832270226 ps
CPU time 29.2 seconds
Started Jun 13 01:21:47 PM PDT 24
Finished Jun 13 01:22:17 PM PDT 24
Peak memory 213588 kb
Host smart-3707d917-a1c8-4045-b9e2-a74db0464dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038110439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3038110439
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1851200706
Short name T303
Test name
Test status
Simulation time 4811143859 ps
CPU time 31.97 seconds
Started Jun 13 01:21:43 PM PDT 24
Finished Jun 13 01:22:16 PM PDT 24
Peak memory 215320 kb
Host smart-6bcd3c42-818d-425a-8a22-f97caab43586
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851200706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1851200706
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4047840436
Short name T286
Test name
Test status
Simulation time 43555905491 ps
CPU time 1652.8 seconds
Started Jun 13 01:21:44 PM PDT 24
Finished Jun 13 01:49:19 PM PDT 24
Peak memory 231364 kb
Host smart-5cdd99f7-55b0-4dbf-a667-da8d6707ed5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047840436 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4047840436
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3495697300
Short name T222
Test name
Test status
Simulation time 135093626 ps
CPU time 5.12 seconds
Started Jun 13 01:21:44 PM PDT 24
Finished Jun 13 01:21:50 PM PDT 24
Peak memory 211124 kb
Host smart-bb067b30-4f2d-45d7-bb1a-b002596ab5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495697300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3495697300
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.427711836
Short name T31
Test name
Test status
Simulation time 8571083569 ps
CPU time 124.78 seconds
Started Jun 13 01:21:44 PM PDT 24
Finished Jun 13 01:23:50 PM PDT 24
Peak memory 212560 kb
Host smart-570bf6ea-9640-41c0-9dbb-3ff23bd6a87e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427711836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.427711836
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.6131059
Short name T351
Test name
Test status
Simulation time 3621760058 ps
CPU time 30.54 seconds
Started Jun 13 01:21:44 PM PDT 24
Finished Jun 13 01:22:15 PM PDT 24
Peak memory 211868 kb
Host smart-eb1719e2-dcb6-46c0-9468-64c252cdf8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6131059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.6131059
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4004538911
Short name T122
Test name
Test status
Simulation time 97879589 ps
CPU time 5.78 seconds
Started Jun 13 01:21:47 PM PDT 24
Finished Jun 13 01:21:53 PM PDT 24
Peak memory 211292 kb
Host smart-59a16a70-13af-4827-bec3-53c47b240cf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004538911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4004538911
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.28718796
Short name T8
Test name
Test status
Simulation time 5189119265 ps
CPU time 28.33 seconds
Started Jun 13 01:21:45 PM PDT 24
Finished Jun 13 01:22:15 PM PDT 24
Peak memory 213800 kb
Host smart-85cc201c-f02c-437d-9d14-bb79efed1607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28718796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.28718796
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3607953028
Short name T233
Test name
Test status
Simulation time 766708024 ps
CPU time 22.41 seconds
Started Jun 13 01:21:44 PM PDT 24
Finished Jun 13 01:22:08 PM PDT 24
Peak memory 214044 kb
Host smart-154024d9-5386-495f-aba4-563bbf65e54c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607953028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3607953028
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.343189918
Short name T52
Test name
Test status
Simulation time 110129044149 ps
CPU time 964.23 seconds
Started Jun 13 01:21:45 PM PDT 24
Finished Jun 13 01:37:51 PM PDT 24
Peak memory 235836 kb
Host smart-a57ecb59-0a81-4edc-80d9-b4807bf8d5cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343189918 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.343189918
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.805263420
Short name T344
Test name
Test status
Simulation time 4869517200 ps
CPU time 7.83 seconds
Started Jun 13 01:19:50 PM PDT 24
Finished Jun 13 01:19:59 PM PDT 24
Peak memory 211196 kb
Host smart-8e229e08-e449-46cf-8749-bf6c2c920a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805263420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.805263420
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.562648257
Short name T142
Test name
Test status
Simulation time 67031099354 ps
CPU time 344.42 seconds
Started Jun 13 01:19:52 PM PDT 24
Finished Jun 13 01:25:37 PM PDT 24
Peak memory 234760 kb
Host smart-6a7250e6-3672-4802-8ac6-a989985ed026
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562648257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.562648257
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3643528541
Short name T347
Test name
Test status
Simulation time 3099368300 ps
CPU time 27.58 seconds
Started Jun 13 01:19:53 PM PDT 24
Finished Jun 13 01:20:21 PM PDT 24
Peak memory 211772 kb
Host smart-40fcec53-f3e5-4d62-9c56-7f95f30d4cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643528541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3643528541
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1170594043
Short name T184
Test name
Test status
Simulation time 2183907373 ps
CPU time 7.14 seconds
Started Jun 13 01:19:51 PM PDT 24
Finished Jun 13 01:19:59 PM PDT 24
Peak memory 211384 kb
Host smart-348af447-4c1d-4dbd-b4b2-5140427ec7f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170594043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1170594043
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.740571596
Short name T293
Test name
Test status
Simulation time 669666545 ps
CPU time 10.28 seconds
Started Jun 13 01:19:51 PM PDT 24
Finished Jun 13 01:20:02 PM PDT 24
Peak memory 213344 kb
Host smart-28b7176b-9111-4acd-830a-78c2d256683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740571596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.740571596
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4169096826
Short name T42
Test name
Test status
Simulation time 5555059349 ps
CPU time 24.77 seconds
Started Jun 13 01:19:52 PM PDT 24
Finished Jun 13 01:20:18 PM PDT 24
Peak memory 214136 kb
Host smart-1d519fef-26f7-4ba5-94d7-3d7dee7bf969
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169096826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4169096826
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3905559737
Short name T235
Test name
Test status
Simulation time 905362531 ps
CPU time 7.37 seconds
Started Jun 13 01:21:52 PM PDT 24
Finished Jun 13 01:22:00 PM PDT 24
Peak memory 211156 kb
Host smart-30d18224-c1c9-4939-87ed-27c5879a5912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905559737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3905559737
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2368378068
Short name T199
Test name
Test status
Simulation time 37809073136 ps
CPU time 443.69 seconds
Started Jun 13 01:21:52 PM PDT 24
Finished Jun 13 01:29:16 PM PDT 24
Peak memory 237604 kb
Host smart-007c8317-2e95-451c-8600-7a1e34e5c17d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368378068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2368378068
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3429319221
Short name T196
Test name
Test status
Simulation time 2480738601 ps
CPU time 22.93 seconds
Started Jun 13 01:21:52 PM PDT 24
Finished Jun 13 01:22:15 PM PDT 24
Peak memory 211912 kb
Host smart-4454a947-4b15-4290-8a2b-e9f7b50d7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429319221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3429319221
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2454508839
Short name T120
Test name
Test status
Simulation time 4321459941 ps
CPU time 11.42 seconds
Started Jun 13 01:21:53 PM PDT 24
Finished Jun 13 01:22:04 PM PDT 24
Peak memory 211340 kb
Host smart-7c2175a0-0554-4be4-b744-8ad900c18652
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454508839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2454508839
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2640155882
Short name T156
Test name
Test status
Simulation time 1800876603 ps
CPU time 10.45 seconds
Started Jun 13 01:21:52 PM PDT 24
Finished Jun 13 01:22:03 PM PDT 24
Peak memory 213964 kb
Host smart-772d6adc-3a7d-491f-a4e6-79405e8b617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640155882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2640155882
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.829305625
Short name T314
Test name
Test status
Simulation time 16610336195 ps
CPU time 45.78 seconds
Started Jun 13 01:21:52 PM PDT 24
Finished Jun 13 01:22:38 PM PDT 24
Peak memory 217864 kb
Host smart-c74aa50c-50e6-474a-a44c-148ad96bd005
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829305625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.829305625
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3897451840
Short name T49
Test name
Test status
Simulation time 61133516332 ps
CPU time 1354.3 seconds
Started Jun 13 01:21:50 PM PDT 24
Finished Jun 13 01:44:25 PM PDT 24
Peak memory 235832 kb
Host smart-13032cae-a942-487a-9977-0cab6dbd562d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897451840 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3897451840
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1209234597
Short name T231
Test name
Test status
Simulation time 1038176820 ps
CPU time 4.31 seconds
Started Jun 13 01:21:55 PM PDT 24
Finished Jun 13 01:22:00 PM PDT 24
Peak memory 211112 kb
Host smart-4dcd01fc-0f64-4ab9-a8bc-80b5b0883090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209234597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1209234597
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.13512660
Short name T284
Test name
Test status
Simulation time 22938620986 ps
CPU time 275.77 seconds
Started Jun 13 01:21:57 PM PDT 24
Finished Jun 13 01:26:33 PM PDT 24
Peak memory 234724 kb
Host smart-59519429-e94b-47c7-aa18-89cf8886cb1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13512660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_co
rrupt_sig_fatal_chk.13512660
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.685599784
Short name T92
Test name
Test status
Simulation time 4856667444 ps
CPU time 25.29 seconds
Started Jun 13 01:21:56 PM PDT 24
Finished Jun 13 01:22:22 PM PDT 24
Peak memory 212176 kb
Host smart-7b5ede52-8cb7-403b-8c5f-c0e68e5f2dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685599784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.685599784
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.950884586
Short name T137
Test name
Test status
Simulation time 832968808 ps
CPU time 8.04 seconds
Started Jun 13 01:21:52 PM PDT 24
Finished Jun 13 01:22:00 PM PDT 24
Peak memory 211292 kb
Host smart-b75ed36a-6349-4a31-ac5b-41d6628a936e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950884586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.950884586
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.119115391
Short name T247
Test name
Test status
Simulation time 189210498 ps
CPU time 10.38 seconds
Started Jun 13 01:21:52 PM PDT 24
Finished Jun 13 01:22:03 PM PDT 24
Peak memory 213828 kb
Host smart-b4387b45-fc06-42a4-83c4-a8e702c22aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119115391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.119115391
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3311894659
Short name T166
Test name
Test status
Simulation time 13264779867 ps
CPU time 35.91 seconds
Started Jun 13 01:21:49 PM PDT 24
Finished Jun 13 01:22:26 PM PDT 24
Peak memory 216104 kb
Host smart-ec3a0ff8-b18a-4917-bc4d-316627c603ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311894659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3311894659
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2439740245
Short name T316
Test name
Test status
Simulation time 1734616938 ps
CPU time 14.37 seconds
Started Jun 13 01:21:58 PM PDT 24
Finished Jun 13 01:22:13 PM PDT 24
Peak memory 211116 kb
Host smart-f39ec75a-60f1-4488-8791-16e29537f10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439740245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2439740245
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.528316220
Short name T194
Test name
Test status
Simulation time 31812476655 ps
CPU time 340.72 seconds
Started Jun 13 01:21:58 PM PDT 24
Finished Jun 13 01:27:39 PM PDT 24
Peak memory 212576 kb
Host smart-37e819e7-ebc4-4b45-95f7-c03ee26650e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528316220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.528316220
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1192517072
Short name T144
Test name
Test status
Simulation time 2307594135 ps
CPU time 18.06 seconds
Started Jun 13 01:21:58 PM PDT 24
Finished Jun 13 01:22:17 PM PDT 24
Peak memory 211844 kb
Host smart-64d1ea78-d0f5-4a03-9675-d0bed62ce62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192517072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1192517072
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2348529829
Short name T143
Test name
Test status
Simulation time 1033966082 ps
CPU time 11.56 seconds
Started Jun 13 01:21:57 PM PDT 24
Finished Jun 13 01:22:09 PM PDT 24
Peak memory 211284 kb
Host smart-1bf474d3-bd42-48f5-b707-a2e8b7173d66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348529829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2348529829
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.548669113
Short name T332
Test name
Test status
Simulation time 1064869070 ps
CPU time 9.97 seconds
Started Jun 13 01:21:57 PM PDT 24
Finished Jun 13 01:22:08 PM PDT 24
Peak memory 213896 kb
Host smart-c4a8caec-0815-4707-8db7-e90620c54530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548669113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.548669113
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2368070215
Short name T204
Test name
Test status
Simulation time 21064668858 ps
CPU time 94.39 seconds
Started Jun 13 01:21:56 PM PDT 24
Finished Jun 13 01:23:30 PM PDT 24
Peak memory 216504 kb
Host smart-68416ae5-3597-4a7d-a20b-61deddb2960d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368070215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2368070215
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1367580882
Short name T349
Test name
Test status
Simulation time 2931498298 ps
CPU time 14.18 seconds
Started Jun 13 01:21:56 PM PDT 24
Finished Jun 13 01:22:10 PM PDT 24
Peak memory 211188 kb
Host smart-dea8eaed-07f4-4023-8d7f-3bd73f306539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367580882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1367580882
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1316979467
Short name T275
Test name
Test status
Simulation time 89267788397 ps
CPU time 227.26 seconds
Started Jun 13 01:21:57 PM PDT 24
Finished Jun 13 01:25:45 PM PDT 24
Peak memory 212872 kb
Host smart-6741a990-469d-4272-be7b-13ce69b7636a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316979467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1316979467
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2093845824
Short name T7
Test name
Test status
Simulation time 756163620 ps
CPU time 9.33 seconds
Started Jun 13 01:21:57 PM PDT 24
Finished Jun 13 01:22:07 PM PDT 24
Peak memory 211792 kb
Host smart-9ee407c6-3efe-4a54-9b05-cbea7150f7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093845824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2093845824
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2415804126
Short name T366
Test name
Test status
Simulation time 7728433760 ps
CPU time 16.68 seconds
Started Jun 13 01:21:57 PM PDT 24
Finished Jun 13 01:22:15 PM PDT 24
Peak memory 211348 kb
Host smart-976697da-b7da-4059-80df-c97e51faf94b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2415804126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2415804126
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1243393802
Short name T360
Test name
Test status
Simulation time 2761863473 ps
CPU time 29.51 seconds
Started Jun 13 01:21:58 PM PDT 24
Finished Jun 13 01:22:28 PM PDT 24
Peak memory 213076 kb
Host smart-85441573-b00f-4e50-ba62-4b13513e9147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243393802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1243393802
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3447575205
Short name T214
Test name
Test status
Simulation time 18630562233 ps
CPU time 47.96 seconds
Started Jun 13 01:21:56 PM PDT 24
Finished Jun 13 01:22:45 PM PDT 24
Peak memory 219288 kb
Host smart-99e341f6-3194-4a63-bd21-a689c4db7655
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447575205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3447575205
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1933907704
Short name T212
Test name
Test status
Simulation time 7794734960 ps
CPU time 14.87 seconds
Started Jun 13 01:22:07 PM PDT 24
Finished Jun 13 01:22:22 PM PDT 24
Peak memory 211220 kb
Host smart-63bd63f1-315d-49f1-9021-c11bf4f86a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933907704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1933907704
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3250566856
Short name T37
Test name
Test status
Simulation time 27173334276 ps
CPU time 265.82 seconds
Started Jun 13 01:21:58 PM PDT 24
Finished Jun 13 01:26:24 PM PDT 24
Peak memory 238752 kb
Host smart-6d790161-16f7-4186-96c3-3cbc8e98461e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250566856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3250566856
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3395070475
Short name T6
Test name
Test status
Simulation time 16229857100 ps
CPU time 26.58 seconds
Started Jun 13 01:21:57 PM PDT 24
Finished Jun 13 01:22:24 PM PDT 24
Peak memory 211280 kb
Host smart-973ae052-d998-40b7-b481-28c72b35d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395070475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3395070475
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2862649614
Short name T320
Test name
Test status
Simulation time 7005577502 ps
CPU time 8.46 seconds
Started Jun 13 01:21:57 PM PDT 24
Finished Jun 13 01:22:06 PM PDT 24
Peak memory 211340 kb
Host smart-8150075d-5f81-4bcf-9db8-f7e9b5c83cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862649614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2862649614
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1751426608
Short name T339
Test name
Test status
Simulation time 710654325 ps
CPU time 9.89 seconds
Started Jun 13 01:21:56 PM PDT 24
Finished Jun 13 01:22:07 PM PDT 24
Peak memory 213136 kb
Host smart-31ea0212-89e3-423e-9883-eebda4575ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751426608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1751426608
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1945201789
Short name T236
Test name
Test status
Simulation time 465499092 ps
CPU time 6.47 seconds
Started Jun 13 01:21:58 PM PDT 24
Finished Jun 13 01:22:05 PM PDT 24
Peak memory 211232 kb
Host smart-d6283e54-dc5b-48d8-a06b-7690e447f366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945201789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1945201789
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2201307351
Short name T322
Test name
Test status
Simulation time 3164530967 ps
CPU time 13.44 seconds
Started Jun 13 01:22:06 PM PDT 24
Finished Jun 13 01:22:20 PM PDT 24
Peak memory 211180 kb
Host smart-0f0a1fd1-066b-4bfa-8ee1-967f76a0ea98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201307351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2201307351
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2510260880
Short name T167
Test name
Test status
Simulation time 125397762532 ps
CPU time 306.07 seconds
Started Jun 13 01:22:04 PM PDT 24
Finished Jun 13 01:27:11 PM PDT 24
Peak memory 237612 kb
Host smart-6453f472-90d8-4e7a-a7c7-c7bd48d02bdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510260880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2510260880
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2256981815
Short name T208
Test name
Test status
Simulation time 6724460796 ps
CPU time 29.53 seconds
Started Jun 13 01:22:07 PM PDT 24
Finished Jun 13 01:22:37 PM PDT 24
Peak memory 212432 kb
Host smart-2748135a-c5dd-4914-8723-824f49da87f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256981815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2256981815
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2703701940
Short name T352
Test name
Test status
Simulation time 1685249249 ps
CPU time 14.35 seconds
Started Jun 13 01:22:07 PM PDT 24
Finished Jun 13 01:22:22 PM PDT 24
Peak memory 211276 kb
Host smart-8d3e9a3e-e63f-4136-a415-8212fc903562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703701940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2703701940
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.695825415
Short name T197
Test name
Test status
Simulation time 355701536 ps
CPU time 12.65 seconds
Started Jun 13 01:22:05 PM PDT 24
Finished Jun 13 01:22:18 PM PDT 24
Peak memory 212856 kb
Host smart-971eae82-cc8d-4b98-b8ac-c4b7a5d71985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695825415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.695825415
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.147604261
Short name T329
Test name
Test status
Simulation time 15856964259 ps
CPU time 35.82 seconds
Started Jun 13 01:22:06 PM PDT 24
Finished Jun 13 01:22:42 PM PDT 24
Peak memory 214820 kb
Host smart-e7e01f64-181d-414a-b7ec-220f11a35b56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147604261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.147604261
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1088600439
Short name T258
Test name
Test status
Simulation time 20025979983 ps
CPU time 16.02 seconds
Started Jun 13 01:22:09 PM PDT 24
Finished Jun 13 01:22:26 PM PDT 24
Peak memory 211156 kb
Host smart-b35634db-6cb0-4fe7-b600-c84abab9ba60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088600439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1088600439
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.484400256
Short name T147
Test name
Test status
Simulation time 12183857360 ps
CPU time 64.11 seconds
Started Jun 13 01:22:16 PM PDT 24
Finished Jun 13 01:23:21 PM PDT 24
Peak memory 236564 kb
Host smart-79731584-b7b4-42da-8559-9b5c9f3fcf01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484400256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.484400256
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.619525823
Short name T189
Test name
Test status
Simulation time 676436461 ps
CPU time 11.8 seconds
Started Jun 13 01:22:09 PM PDT 24
Finished Jun 13 01:22:22 PM PDT 24
Peak memory 211912 kb
Host smart-142ce955-ec98-41ac-a798-2423b8acc5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619525823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.619525823
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2224166683
Short name T161
Test name
Test status
Simulation time 5698120947 ps
CPU time 15.23 seconds
Started Jun 13 01:22:09 PM PDT 24
Finished Jun 13 01:22:25 PM PDT 24
Peak memory 211348 kb
Host smart-bfaf3956-c8e7-45dd-84e9-c97c0079b728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224166683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2224166683
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2792437207
Short name T244
Test name
Test status
Simulation time 3553057307 ps
CPU time 30.83 seconds
Started Jun 13 01:22:05 PM PDT 24
Finished Jun 13 01:22:36 PM PDT 24
Peak memory 213660 kb
Host smart-a96c08a9-b32b-40e8-96f2-ac31504658a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792437207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2792437207
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.885863191
Short name T186
Test name
Test status
Simulation time 14769696807 ps
CPU time 39.67 seconds
Started Jun 13 01:22:10 PM PDT 24
Finished Jun 13 01:22:50 PM PDT 24
Peak memory 214644 kb
Host smart-1341fce1-d246-47f0-923d-1833d5696ca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885863191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.885863191
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3167701576
Short name T343
Test name
Test status
Simulation time 4162668832 ps
CPU time 16.94 seconds
Started Jun 13 01:22:08 PM PDT 24
Finished Jun 13 01:22:26 PM PDT 24
Peak memory 211188 kb
Host smart-ae0ea06b-2e6c-4137-9d8f-6d80a90d0a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167701576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3167701576
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1810690673
Short name T150
Test name
Test status
Simulation time 9683766476 ps
CPU time 107.64 seconds
Started Jun 13 01:22:08 PM PDT 24
Finished Jun 13 01:23:57 PM PDT 24
Peak memory 234716 kb
Host smart-5a05dd51-a3fc-4ddb-ab9b-9b9b07f2051e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810690673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1810690673
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1444274177
Short name T348
Test name
Test status
Simulation time 2061331695 ps
CPU time 13.37 seconds
Started Jun 13 01:22:08 PM PDT 24
Finished Jun 13 01:22:23 PM PDT 24
Peak memory 211872 kb
Host smart-c6248278-f76b-4ea2-bad7-df290bb5874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444274177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1444274177
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2540342324
Short name T136
Test name
Test status
Simulation time 482100450 ps
CPU time 8.27 seconds
Started Jun 13 01:22:13 PM PDT 24
Finished Jun 13 01:22:21 PM PDT 24
Peak memory 211316 kb
Host smart-5347fa09-ba33-4063-9cd9-e271967fce6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540342324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2540342324
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3139288672
Short name T195
Test name
Test status
Simulation time 2316846739 ps
CPU time 25.52 seconds
Started Jun 13 01:22:07 PM PDT 24
Finished Jun 13 01:22:33 PM PDT 24
Peak memory 213176 kb
Host smart-b9e48d99-edd7-480d-b2b5-263d5a34efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139288672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3139288672
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3874060466
Short name T188
Test name
Test status
Simulation time 2449625621 ps
CPU time 31.53 seconds
Started Jun 13 01:22:13 PM PDT 24
Finished Jun 13 01:22:45 PM PDT 24
Peak memory 216760 kb
Host smart-df51b53a-9093-4bbc-a69d-5aba0551812f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874060466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3874060466
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1329521966
Short name T281
Test name
Test status
Simulation time 2643686541 ps
CPU time 6.97 seconds
Started Jun 13 01:22:16 PM PDT 24
Finished Jun 13 01:22:24 PM PDT 24
Peak memory 211088 kb
Host smart-91c3ce0a-6b22-40b9-b060-a88f77f35227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329521966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1329521966
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2672013954
Short name T201
Test name
Test status
Simulation time 22348144848 ps
CPU time 80.44 seconds
Started Jun 13 01:22:16 PM PDT 24
Finished Jun 13 01:23:38 PM PDT 24
Peak memory 236580 kb
Host smart-570649c7-b2d3-4d65-8ece-ec068dc180fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672013954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2672013954
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1416799991
Short name T93
Test name
Test status
Simulation time 15156848337 ps
CPU time 32.87 seconds
Started Jun 13 01:22:08 PM PDT 24
Finished Jun 13 01:22:42 PM PDT 24
Peak memory 212124 kb
Host smart-43c5199b-a273-47b3-8698-b9e0ff4267ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416799991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1416799991
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4068004298
Short name T30
Test name
Test status
Simulation time 95631667 ps
CPU time 5.5 seconds
Started Jun 13 01:22:18 PM PDT 24
Finished Jun 13 01:22:24 PM PDT 24
Peak memory 211224 kb
Host smart-9ac88d09-367b-416f-bac6-f434a0fe356a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068004298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4068004298
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2900280113
Short name T121
Test name
Test status
Simulation time 2332807821 ps
CPU time 23.27 seconds
Started Jun 13 01:22:10 PM PDT 24
Finished Jun 13 01:22:34 PM PDT 24
Peak memory 213312 kb
Host smart-8ee54c5e-d22f-49f2-b3fb-8e14dc8cabfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900280113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2900280113
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.277839464
Short name T132
Test name
Test status
Simulation time 17093736595 ps
CPU time 34.03 seconds
Started Jun 13 01:22:08 PM PDT 24
Finished Jun 13 01:22:43 PM PDT 24
Peak memory 213892 kb
Host smart-c021b63f-9a9e-4894-bbf9-58b2fe2280c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277839464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.277839464
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3496402575
Short name T172
Test name
Test status
Simulation time 11822206213 ps
CPU time 17.91 seconds
Started Jun 13 01:22:16 PM PDT 24
Finished Jun 13 01:22:34 PM PDT 24
Peak memory 211196 kb
Host smart-ec00ae3e-39eb-4f4c-bb7a-cbdcea6cab75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496402575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3496402575
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3063876855
Short name T282
Test name
Test status
Simulation time 205053596735 ps
CPU time 334.05 seconds
Started Jun 13 01:22:16 PM PDT 24
Finished Jun 13 01:27:51 PM PDT 24
Peak memory 213620 kb
Host smart-fbef206e-5e6b-4dc0-9791-2be8b3aab287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063876855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3063876855
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.204175206
Short name T140
Test name
Test status
Simulation time 11552875179 ps
CPU time 13.97 seconds
Started Jun 13 01:22:15 PM PDT 24
Finished Jun 13 01:22:29 PM PDT 24
Peak memory 212160 kb
Host smart-549311cc-2f8c-4b8b-ae12-d6e66ebe5f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204175206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.204175206
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2393820626
Short name T123
Test name
Test status
Simulation time 780728830 ps
CPU time 9.89 seconds
Started Jun 13 01:22:15 PM PDT 24
Finished Jun 13 01:22:25 PM PDT 24
Peak memory 211256 kb
Host smart-148b4d61-b2e0-450b-9db0-17c4cbe4762a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393820626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2393820626
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3611003476
Short name T362
Test name
Test status
Simulation time 4188844889 ps
CPU time 38.02 seconds
Started Jun 13 01:22:09 PM PDT 24
Finished Jun 13 01:22:48 PM PDT 24
Peak memory 213704 kb
Host smart-dc5123eb-0c56-4f6d-860f-e58f3063e2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611003476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3611003476
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1971540082
Short name T253
Test name
Test status
Simulation time 20342512971 ps
CPU time 53.92 seconds
Started Jun 13 01:22:16 PM PDT 24
Finished Jun 13 01:23:10 PM PDT 24
Peak memory 216100 kb
Host smart-8bb6f16d-e919-4589-ab1a-910032512a43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971540082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1971540082
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.641959227
Short name T3
Test name
Test status
Simulation time 104890125 ps
CPU time 4.23 seconds
Started Jun 13 01:19:54 PM PDT 24
Finished Jun 13 01:19:59 PM PDT 24
Peak memory 211132 kb
Host smart-8e815d66-1d2f-4f51-9e6a-c9212685cfc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641959227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.641959227
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2275731917
Short name T277
Test name
Test status
Simulation time 1604249936 ps
CPU time 76.64 seconds
Started Jun 13 01:19:51 PM PDT 24
Finished Jun 13 01:21:09 PM PDT 24
Peak memory 212520 kb
Host smart-5ae2e6e7-e94d-4f47-8b48-56fbc18b5fd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275731917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2275731917
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3750288935
Short name T185
Test name
Test status
Simulation time 2480368065 ps
CPU time 24.82 seconds
Started Jun 13 01:19:49 PM PDT 24
Finished Jun 13 01:20:14 PM PDT 24
Peak memory 211852 kb
Host smart-3c3b3d9b-bdbb-4112-be77-f44d9c81b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750288935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3750288935
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4266824867
Short name T252
Test name
Test status
Simulation time 1124641889 ps
CPU time 12.18 seconds
Started Jun 13 01:19:53 PM PDT 24
Finished Jun 13 01:20:06 PM PDT 24
Peak memory 211320 kb
Host smart-ff601f93-3f16-48bf-a3e1-f3ef29d48828
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266824867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4266824867
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3419520687
Short name T69
Test name
Test status
Simulation time 21089520327 ps
CPU time 29.64 seconds
Started Jun 13 01:19:54 PM PDT 24
Finished Jun 13 01:20:25 PM PDT 24
Peak memory 214360 kb
Host smart-9a1869b9-ff4a-4c55-bca2-d802f2334eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419520687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3419520687
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1008892909
Short name T29
Test name
Test status
Simulation time 28706712859 ps
CPU time 58 seconds
Started Jun 13 01:19:55 PM PDT 24
Finished Jun 13 01:20:54 PM PDT 24
Peak memory 219340 kb
Host smart-a50952ba-ff29-4012-9a2a-486ddc0c1ee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008892909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1008892909
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.407378245
Short name T365
Test name
Test status
Simulation time 88853545 ps
CPU time 4.4 seconds
Started Jun 13 01:19:58 PM PDT 24
Finished Jun 13 01:20:04 PM PDT 24
Peak memory 211088 kb
Host smart-f562148b-8fc3-4ea7-bf10-27df706003cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407378245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.407378245
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1426314095
Short name T38
Test name
Test status
Simulation time 56647872105 ps
CPU time 270.89 seconds
Started Jun 13 01:19:57 PM PDT 24
Finished Jun 13 01:24:29 PM PDT 24
Peak memory 236488 kb
Host smart-886cde1b-cf6f-4501-9666-de822609c106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426314095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1426314095
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3870428042
Short name T309
Test name
Test status
Simulation time 885089601 ps
CPU time 12.1 seconds
Started Jun 13 01:20:00 PM PDT 24
Finished Jun 13 01:20:13 PM PDT 24
Peak memory 212244 kb
Host smart-36761021-30c6-4fc0-bff8-1aa7d16a2063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870428042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3870428042
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.290046825
Short name T368
Test name
Test status
Simulation time 2428448640 ps
CPU time 13.29 seconds
Started Jun 13 01:19:51 PM PDT 24
Finished Jun 13 01:20:05 PM PDT 24
Peak memory 211344 kb
Host smart-7e6b2bb5-6d43-4299-a674-b951c81f67d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290046825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.290046825
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2521254207
Short name T307
Test name
Test status
Simulation time 192358677 ps
CPU time 10.23 seconds
Started Jun 13 01:19:51 PM PDT 24
Finished Jun 13 01:20:03 PM PDT 24
Peak memory 213240 kb
Host smart-984ccc6e-4a20-4741-b001-201d5fa03fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521254207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2521254207
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.433202133
Short name T312
Test name
Test status
Simulation time 13094058975 ps
CPU time 73.55 seconds
Started Jun 13 01:19:50 PM PDT 24
Finished Jun 13 01:21:04 PM PDT 24
Peak memory 217284 kb
Host smart-6599affc-b294-4125-a580-30d8163ee1de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433202133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.433202133
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1147187900
Short name T153
Test name
Test status
Simulation time 1909832291 ps
CPU time 11.51 seconds
Started Jun 13 01:20:06 PM PDT 24
Finished Jun 13 01:20:18 PM PDT 24
Peak memory 210976 kb
Host smart-e8d013ec-4ca6-45dd-b4dc-6477b140b792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147187900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1147187900
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3680325287
Short name T242
Test name
Test status
Simulation time 33563932654 ps
CPU time 107.87 seconds
Started Jun 13 01:20:11 PM PDT 24
Finished Jun 13 01:22:00 PM PDT 24
Peak memory 228328 kb
Host smart-345b4726-a4e6-40c3-9a7d-10d427afdb96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680325287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3680325287
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2753710473
Short name T290
Test name
Test status
Simulation time 781917614 ps
CPU time 14.37 seconds
Started Jun 13 01:20:08 PM PDT 24
Finished Jun 13 01:20:22 PM PDT 24
Peak memory 212624 kb
Host smart-5897500a-6e4f-4704-8f9d-36a18590ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753710473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2753710473
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.216794446
Short name T89
Test name
Test status
Simulation time 1493766409 ps
CPU time 5.33 seconds
Started Jun 13 01:20:05 PM PDT 24
Finished Jun 13 01:20:11 PM PDT 24
Peak memory 211280 kb
Host smart-6335ec40-a02e-4772-a15e-126b064d71ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216794446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.216794446
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2114555401
Short name T215
Test name
Test status
Simulation time 750497574 ps
CPU time 10.23 seconds
Started Jun 13 01:19:58 PM PDT 24
Finished Jun 13 01:20:09 PM PDT 24
Peak memory 213216 kb
Host smart-e8b51be1-8f79-4245-ad17-e65a9436105a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114555401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2114555401
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2831814627
Short name T211
Test name
Test status
Simulation time 2938936311 ps
CPU time 12.65 seconds
Started Jun 13 01:20:08 PM PDT 24
Finished Jun 13 01:20:21 PM PDT 24
Peak memory 213772 kb
Host smart-df24a8c4-2146-4d2c-9a54-c8867b1f24ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831814627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2831814627
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.762149226
Short name T46
Test name
Test status
Simulation time 35456790509 ps
CPU time 5567.19 seconds
Started Jun 13 01:20:11 PM PDT 24
Finished Jun 13 02:53:00 PM PDT 24
Peak memory 235804 kb
Host smart-4c4f78d2-4191-443b-8eec-3c16b9d806be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762149226 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.762149226
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3675269523
Short name T341
Test name
Test status
Simulation time 903437436 ps
CPU time 9.77 seconds
Started Jun 13 01:20:06 PM PDT 24
Finished Jun 13 01:20:17 PM PDT 24
Peak memory 211120 kb
Host smart-7d32b7c6-35e9-4faf-8735-20c6264913c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675269523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3675269523
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2858827336
Short name T138
Test name
Test status
Simulation time 6801608476 ps
CPU time 19.92 seconds
Started Jun 13 01:20:07 PM PDT 24
Finished Jun 13 01:20:27 PM PDT 24
Peak memory 212416 kb
Host smart-d231ee1b-cd5d-4561-b3e1-bf7f24e1992e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858827336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2858827336
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.813658109
Short name T203
Test name
Test status
Simulation time 395190209 ps
CPU time 8.18 seconds
Started Jun 13 01:20:04 PM PDT 24
Finished Jun 13 01:20:13 PM PDT 24
Peak memory 211280 kb
Host smart-98b0d5f8-e8cd-49fa-95b5-9e7af481ce85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813658109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.813658109
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1392807081
Short name T18
Test name
Test status
Simulation time 375954712 ps
CPU time 9.81 seconds
Started Jun 13 01:20:11 PM PDT 24
Finished Jun 13 01:20:22 PM PDT 24
Peak memory 213556 kb
Host smart-464adc6e-e5a3-4605-a214-d6bdf0dff534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392807081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1392807081
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1500409247
Short name T51
Test name
Test status
Simulation time 24449167332 ps
CPU time 1016.81 seconds
Started Jun 13 01:20:04 PM PDT 24
Finished Jun 13 01:37:01 PM PDT 24
Peak memory 235840 kb
Host smart-fef20099-2e13-4e13-8fc3-81b364513dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500409247 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1500409247
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2968338802
Short name T145
Test name
Test status
Simulation time 3684237265 ps
CPU time 15.87 seconds
Started Jun 13 01:20:11 PM PDT 24
Finished Jun 13 01:20:27 PM PDT 24
Peak memory 211152 kb
Host smart-cb27e05c-f6c2-4951-8f3a-afe51da0b9a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968338802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2968338802
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2448009969
Short name T288
Test name
Test status
Simulation time 8439298182 ps
CPU time 198.86 seconds
Started Jun 13 01:20:14 PM PDT 24
Finished Jun 13 01:23:33 PM PDT 24
Peak memory 237656 kb
Host smart-ef1bc603-b2bf-4d00-b9c1-749f1f9f0466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448009969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2448009969
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4150193881
Short name T327
Test name
Test status
Simulation time 253522550 ps
CPU time 11.14 seconds
Started Jun 13 01:20:13 PM PDT 24
Finished Jun 13 01:20:25 PM PDT 24
Peak memory 211944 kb
Host smart-e7d31002-caec-499b-96f6-1761af3bdd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150193881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4150193881
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1471889722
Short name T299
Test name
Test status
Simulation time 94585163 ps
CPU time 5.64 seconds
Started Jun 13 01:20:14 PM PDT 24
Finished Jun 13 01:20:20 PM PDT 24
Peak memory 211292 kb
Host smart-8267701b-8a87-472e-8058-eafb4a353850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1471889722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1471889722
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4102176515
Short name T237
Test name
Test status
Simulation time 25401247013 ps
CPU time 31.21 seconds
Started Jun 13 01:20:12 PM PDT 24
Finished Jun 13 01:20:45 PM PDT 24
Peak memory 214576 kb
Host smart-19ebdbd4-90e8-421e-966a-c73ef016b32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102176515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4102176515
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.285272847
Short name T210
Test name
Test status
Simulation time 8250175158 ps
CPU time 75.95 seconds
Started Jun 13 01:20:12 PM PDT 24
Finished Jun 13 01:21:29 PM PDT 24
Peak memory 216708 kb
Host smart-7b1282e3-de1a-4c1a-9157-6a52e6421fc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285272847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.285272847
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3533458435
Short name T249
Test name
Test status
Simulation time 42633336773 ps
CPU time 1630.18 seconds
Started Jun 13 01:20:14 PM PDT 24
Finished Jun 13 01:47:25 PM PDT 24
Peak memory 235832 kb
Host smart-6f429425-a973-4237-ac77-ea5fc59ca7c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533458435 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3533458435
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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