Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 96.89 92.56 97.67 100.00 98.97 97.45 98.37


Total test records in report: 460
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T301 /workspace/coverage/default/26.rom_ctrl_smoke.111949018 Jun 21 05:19:06 PM PDT 24 Jun 21 05:19:19 PM PDT 24 2874167185 ps
T58 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1487424854 Jun 21 05:17:59 PM PDT 24 Jun 21 06:22:42 PM PDT 24 439186199907 ps
T302 /workspace/coverage/default/25.rom_ctrl_alert_test.3152809602 Jun 21 05:19:05 PM PDT 24 Jun 21 05:19:10 PM PDT 24 178819959 ps
T303 /workspace/coverage/default/30.rom_ctrl_alert_test.3270530133 Jun 21 05:19:28 PM PDT 24 Jun 21 05:19:44 PM PDT 24 6415044836 ps
T304 /workspace/coverage/default/3.rom_ctrl_smoke.3804491679 Jun 21 05:17:49 PM PDT 24 Jun 21 05:18:11 PM PDT 24 6624100134 ps
T305 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.65505443 Jun 21 05:18:28 PM PDT 24 Jun 21 05:21:48 PM PDT 24 25995253662 ps
T306 /workspace/coverage/default/2.rom_ctrl_stress_all.2248306936 Jun 21 05:17:49 PM PDT 24 Jun 21 05:18:05 PM PDT 24 3100391742 ps
T307 /workspace/coverage/default/1.rom_ctrl_stress_all.1600135094 Jun 21 05:17:43 PM PDT 24 Jun 21 05:18:53 PM PDT 24 7487259077 ps
T308 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.377409312 Jun 21 05:17:39 PM PDT 24 Jun 21 05:18:12 PM PDT 24 9389069553 ps
T309 /workspace/coverage/default/42.rom_ctrl_smoke.777140376 Jun 21 05:19:53 PM PDT 24 Jun 21 05:20:11 PM PDT 24 923923851 ps
T310 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2751860722 Jun 21 05:18:38 PM PDT 24 Jun 21 05:18:51 PM PDT 24 4730832797 ps
T311 /workspace/coverage/default/19.rom_ctrl_stress_all.1301496563 Jun 21 05:18:52 PM PDT 24 Jun 21 05:19:15 PM PDT 24 1074008541 ps
T312 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3159546358 Jun 21 05:18:43 PM PDT 24 Jun 21 05:18:50 PM PDT 24 100948923 ps
T313 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2690593216 Jun 21 05:19:51 PM PDT 24 Jun 21 05:25:09 PM PDT 24 129459294127 ps
T314 /workspace/coverage/default/4.rom_ctrl_stress_all.3752072986 Jun 21 05:17:59 PM PDT 24 Jun 21 05:18:18 PM PDT 24 1230211165 ps
T315 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3134557337 Jun 21 05:18:35 PM PDT 24 Jun 21 05:18:56 PM PDT 24 6842785320 ps
T25 /workspace/coverage/default/1.rom_ctrl_sec_cm.2930043196 Jun 21 05:17:49 PM PDT 24 Jun 21 05:19:34 PM PDT 24 2023581144 ps
T316 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1914989468 Jun 21 05:19:44 PM PDT 24 Jun 21 05:20:14 PM PDT 24 17657314211 ps
T317 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3336401348 Jun 21 05:18:14 PM PDT 24 Jun 21 05:18:30 PM PDT 24 761923510 ps
T318 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.699153562 Jun 21 05:20:23 PM PDT 24 Jun 21 05:22:40 PM PDT 24 12733047863 ps
T59 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.820034168 Jun 21 05:18:43 PM PDT 24 Jun 21 05:24:14 PM PDT 24 6478863040 ps
T26 /workspace/coverage/default/3.rom_ctrl_sec_cm.3205470782 Jun 21 05:17:57 PM PDT 24 Jun 21 05:19:41 PM PDT 24 2028891962 ps
T319 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2763578213 Jun 21 05:19:44 PM PDT 24 Jun 21 05:20:03 PM PDT 24 8542215496 ps
T320 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4180086643 Jun 21 05:18:42 PM PDT 24 Jun 21 05:19:10 PM PDT 24 5405562978 ps
T321 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2000911814 Jun 21 05:19:59 PM PDT 24 Jun 21 05:20:18 PM PDT 24 5450491558 ps
T322 /workspace/coverage/default/18.rom_ctrl_smoke.2569375350 Jun 21 05:18:42 PM PDT 24 Jun 21 05:18:58 PM PDT 24 2038636673 ps
T323 /workspace/coverage/default/45.rom_ctrl_stress_all.600859586 Jun 21 05:20:06 PM PDT 24 Jun 21 05:20:53 PM PDT 24 3306908924 ps
T324 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2684711185 Jun 21 05:18:05 PM PDT 24 Jun 21 05:18:39 PM PDT 24 3954947432 ps
T325 /workspace/coverage/default/38.rom_ctrl_smoke.4120693262 Jun 21 05:19:55 PM PDT 24 Jun 21 05:20:23 PM PDT 24 57731758164 ps
T326 /workspace/coverage/default/36.rom_ctrl_alert_test.3765045823 Jun 21 05:19:56 PM PDT 24 Jun 21 05:20:06 PM PDT 24 3037089460 ps
T327 /workspace/coverage/default/15.rom_ctrl_alert_test.120522388 Jun 21 05:18:35 PM PDT 24 Jun 21 05:18:50 PM PDT 24 12524496793 ps
T328 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2660961679 Jun 21 05:18:05 PM PDT 24 Jun 21 05:19:52 PM PDT 24 7321543660 ps
T329 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3194121545 Jun 21 05:20:17 PM PDT 24 Jun 21 05:20:33 PM PDT 24 11277083870 ps
T330 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2534310578 Jun 21 05:19:21 PM PDT 24 Jun 21 05:19:38 PM PDT 24 2007497053 ps
T331 /workspace/coverage/default/18.rom_ctrl_alert_test.1946143690 Jun 21 05:18:53 PM PDT 24 Jun 21 05:18:59 PM PDT 24 89313498 ps
T332 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2366943818 Jun 21 05:19:07 PM PDT 24 Jun 21 05:22:51 PM PDT 24 22363110777 ps
T333 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1245097219 Jun 21 05:20:15 PM PDT 24 Jun 21 05:20:27 PM PDT 24 321463069 ps
T334 /workspace/coverage/default/37.rom_ctrl_alert_test.4277699046 Jun 21 05:19:48 PM PDT 24 Jun 21 05:19:53 PM PDT 24 346520106 ps
T335 /workspace/coverage/default/35.rom_ctrl_smoke.2794944318 Jun 21 05:19:40 PM PDT 24 Jun 21 05:20:14 PM PDT 24 19208521541 ps
T336 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.815351116 Jun 21 05:19:19 PM PDT 24 Jun 21 05:22:36 PM PDT 24 30991559009 ps
T337 /workspace/coverage/default/7.rom_ctrl_stress_all.867471964 Jun 21 05:18:06 PM PDT 24 Jun 21 05:18:36 PM PDT 24 1863690353 ps
T338 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2124806772 Jun 21 05:19:37 PM PDT 24 Jun 21 05:19:59 PM PDT 24 3777116685 ps
T339 /workspace/coverage/default/0.rom_ctrl_smoke.2688203153 Jun 21 05:17:40 PM PDT 24 Jun 21 05:17:52 PM PDT 24 476472480 ps
T340 /workspace/coverage/default/9.rom_ctrl_alert_test.2729163218 Jun 21 05:18:16 PM PDT 24 Jun 21 05:18:33 PM PDT 24 4135558379 ps
T341 /workspace/coverage/default/30.rom_ctrl_stress_all.1873660638 Jun 21 05:19:28 PM PDT 24 Jun 21 05:20:06 PM PDT 24 7273616887 ps
T342 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1591325505 Jun 21 05:19:37 PM PDT 24 Jun 21 05:20:02 PM PDT 24 2368397513 ps
T343 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2353182273 Jun 21 05:18:43 PM PDT 24 Jun 21 05:21:45 PM PDT 24 10678192621 ps
T344 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3177112158 Jun 21 05:17:50 PM PDT 24 Jun 21 05:20:59 PM PDT 24 5650364687 ps
T345 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3899887119 Jun 21 05:19:38 PM PDT 24 Jun 21 05:19:58 PM PDT 24 1458554602 ps
T346 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2590291080 Jun 21 05:19:29 PM PDT 24 Jun 21 05:22:21 PM PDT 24 11382827898 ps
T347 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.221361436 Jun 21 05:18:20 PM PDT 24 Jun 21 05:18:46 PM PDT 24 10555429404 ps
T60 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1399672274 Jun 21 05:18:53 PM PDT 24 Jun 21 06:08:13 PM PDT 24 77686223657 ps
T348 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.370546937 Jun 21 05:17:56 PM PDT 24 Jun 21 05:18:09 PM PDT 24 4751635629 ps
T61 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2594413102 Jun 21 05:18:20 PM PDT 24 Jun 21 07:38:14 PM PDT 24 96260515354 ps
T349 /workspace/coverage/default/13.rom_ctrl_stress_all.99924671 Jun 21 05:18:30 PM PDT 24 Jun 21 05:19:26 PM PDT 24 11007817964 ps
T350 /workspace/coverage/default/33.rom_ctrl_smoke.1507074815 Jun 21 05:19:38 PM PDT 24 Jun 21 05:20:09 PM PDT 24 6333732548 ps
T351 /workspace/coverage/default/31.rom_ctrl_smoke.1195912109 Jun 21 05:19:29 PM PDT 24 Jun 21 05:20:01 PM PDT 24 11375453607 ps
T352 /workspace/coverage/default/22.rom_ctrl_alert_test.2162502158 Jun 21 05:18:57 PM PDT 24 Jun 21 05:19:03 PM PDT 24 257164354 ps
T353 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1884970166 Jun 21 05:20:10 PM PDT 24 Jun 21 05:25:36 PM PDT 24 28641813149 ps
T354 /workspace/coverage/default/31.rom_ctrl_stress_all.1795199447 Jun 21 05:19:29 PM PDT 24 Jun 21 05:19:51 PM PDT 24 1339954539 ps
T355 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1885489141 Jun 21 05:20:16 PM PDT 24 Jun 21 05:20:33 PM PDT 24 4462539576 ps
T356 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2888343254 Jun 21 05:20:07 PM PDT 24 Jun 21 05:20:22 PM PDT 24 16092388228 ps
T357 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1581083531 Jun 21 05:19:53 PM PDT 24 Jun 21 05:22:58 PM PDT 24 16403958560 ps
T358 /workspace/coverage/default/22.rom_ctrl_smoke.3660405515 Jun 21 05:18:58 PM PDT 24 Jun 21 05:19:32 PM PDT 24 7512425481 ps
T359 /workspace/coverage/default/1.rom_ctrl_alert_test.2362268603 Jun 21 05:17:49 PM PDT 24 Jun 21 05:18:07 PM PDT 24 2002962791 ps
T360 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3780421925 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:45 PM PDT 24 4468137295 ps
T65 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1315779294 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:40 PM PDT 24 1009204064 ps
T66 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1650965622 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:21 PM PDT 24 10378277871 ps
T67 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2336502458 Jun 21 04:49:30 PM PDT 24 Jun 21 04:49:47 PM PDT 24 96606912 ps
T62 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2949047370 Jun 21 04:49:23 PM PDT 24 Jun 21 04:50:41 PM PDT 24 3053409597 ps
T361 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1765315223 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:20 PM PDT 24 433670782 ps
T362 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3152433753 Jun 21 04:49:07 PM PDT 24 Jun 21 04:49:23 PM PDT 24 7609188046 ps
T73 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3597292685 Jun 21 04:49:30 PM PDT 24 Jun 21 04:49:46 PM PDT 24 86633605 ps
T363 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1091208941 Jun 21 04:49:36 PM PDT 24 Jun 21 04:50:01 PM PDT 24 1787279383 ps
T364 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2859869171 Jun 21 04:49:21 PM PDT 24 Jun 21 04:49:41 PM PDT 24 29965657742 ps
T74 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3645117621 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:18 PM PDT 24 215246610 ps
T115 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3773033560 Jun 21 04:49:07 PM PDT 24 Jun 21 04:49:36 PM PDT 24 6766099220 ps
T75 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.566720621 Jun 21 04:49:29 PM PDT 24 Jun 21 04:49:49 PM PDT 24 838771287 ps
T365 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1509741274 Jun 21 04:49:30 PM PDT 24 Jun 21 04:49:50 PM PDT 24 3536623326 ps
T63 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3624459957 Jun 21 04:49:23 PM PDT 24 Jun 21 04:50:36 PM PDT 24 1526640015 ps
T76 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2705254742 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:48 PM PDT 24 724366581 ps
T116 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1239718329 Jun 21 04:49:11 PM PDT 24 Jun 21 04:49:25 PM PDT 24 1403090428 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1940159444 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:22 PM PDT 24 16429750796 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3757145955 Jun 21 04:49:20 PM PDT 24 Jun 21 04:49:28 PM PDT 24 195409416 ps
T77 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3499089769 Jun 21 04:49:27 PM PDT 24 Jun 21 04:49:51 PM PDT 24 1809634211 ps
T78 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.382062447 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:59 PM PDT 24 1835055243 ps
T64 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3694821368 Jun 21 04:49:21 PM PDT 24 Jun 21 04:50:32 PM PDT 24 303774507 ps
T79 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1705740862 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:42 PM PDT 24 12264609467 ps
T368 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3874846204 Jun 21 04:49:21 PM PDT 24 Jun 21 04:49:36 PM PDT 24 814067897 ps
T109 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1115730638 Jun 21 04:49:10 PM PDT 24 Jun 21 04:49:22 PM PDT 24 3527689528 ps
T80 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.523465615 Jun 21 04:49:27 PM PDT 24 Jun 21 04:50:44 PM PDT 24 13986455095 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1358447582 Jun 21 04:49:07 PM PDT 24 Jun 21 04:49:19 PM PDT 24 4971414801 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1121580577 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:25 PM PDT 24 8104312397 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2486087672 Jun 21 04:49:07 PM PDT 24 Jun 21 04:49:15 PM PDT 24 122946920 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1824409517 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:21 PM PDT 24 3753972180 ps
T372 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4081836881 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:32 PM PDT 24 190579020 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3394409927 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:27 PM PDT 24 4015301405 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3052110483 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:17 PM PDT 24 174739727 ps
T121 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2338621408 Jun 21 04:49:30 PM PDT 24 Jun 21 04:50:56 PM PDT 24 6565468410 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.254813479 Jun 21 04:49:21 PM PDT 24 Jun 21 04:49:32 PM PDT 24 1114958330 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1311621030 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:24 PM PDT 24 1378083195 ps
T375 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2960410767 Jun 21 04:49:32 PM PDT 24 Jun 21 04:50:27 PM PDT 24 2267190752 ps
T376 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4116815786 Jun 21 04:49:28 PM PDT 24 Jun 21 04:49:44 PM PDT 24 86511462 ps
T377 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.635308912 Jun 21 04:49:22 PM PDT 24 Jun 21 04:49:41 PM PDT 24 7320738940 ps
T378 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1792802033 Jun 21 04:49:20 PM PDT 24 Jun 21 04:49:34 PM PDT 24 14653742494 ps
T379 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2341971248 Jun 21 04:49:18 PM PDT 24 Jun 21 04:49:29 PM PDT 24 628074498 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.188414099 Jun 21 04:49:26 PM PDT 24 Jun 21 04:49:48 PM PDT 24 8030078661 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.908495597 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:22 PM PDT 24 3802977743 ps
T382 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3250737034 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:38 PM PDT 24 5794814185 ps
T111 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1899945531 Jun 21 04:49:36 PM PDT 24 Jun 21 04:50:02 PM PDT 24 1988029996 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3647845881 Jun 21 04:49:11 PM PDT 24 Jun 21 04:49:22 PM PDT 24 476412673 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1936099637 Jun 21 04:49:30 PM PDT 24 Jun 21 04:50:32 PM PDT 24 11129423945 ps
T91 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4062904548 Jun 21 04:49:26 PM PDT 24 Jun 21 04:50:12 PM PDT 24 1537055042 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.216292405 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:16 PM PDT 24 833450186 ps
T385 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.950603111 Jun 21 04:49:27 PM PDT 24 Jun 21 04:49:42 PM PDT 24 351294550 ps
T386 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3709349064 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:38 PM PDT 24 498194107 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.524725288 Jun 21 04:49:18 PM PDT 24 Jun 21 04:49:30 PM PDT 24 3230913805 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.239200576 Jun 21 04:49:05 PM PDT 24 Jun 21 04:49:21 PM PDT 24 7874002357 ps
T118 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2916252169 Jun 21 04:49:08 PM PDT 24 Jun 21 04:50:21 PM PDT 24 5996069809 ps
T389 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1499439022 Jun 21 04:49:32 PM PDT 24 Jun 21 04:49:59 PM PDT 24 5078222327 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4043803667 Jun 21 04:49:21 PM PDT 24 Jun 21 04:49:35 PM PDT 24 4642641127 ps
T113 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1921121660 Jun 21 04:49:30 PM PDT 24 Jun 21 04:49:49 PM PDT 24 2722276804 ps
T92 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1120573505 Jun 21 04:49:30 PM PDT 24 Jun 21 04:50:21 PM PDT 24 19059437110 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.962841380 Jun 21 04:49:20 PM PDT 24 Jun 21 04:49:38 PM PDT 24 7308376732 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2627360540 Jun 21 04:49:20 PM PDT 24 Jun 21 04:49:28 PM PDT 24 889444880 ps
T119 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1176990192 Jun 21 04:49:22 PM PDT 24 Jun 21 04:50:36 PM PDT 24 791071802 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1418248431 Jun 21 04:49:11 PM PDT 24 Jun 21 04:49:29 PM PDT 24 1960371090 ps
T393 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.208746660 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:48 PM PDT 24 378931876 ps
T394 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1715488964 Jun 21 04:49:34 PM PDT 24 Jun 21 04:49:53 PM PDT 24 2685835767 ps
T120 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.599020279 Jun 21 04:49:30 PM PDT 24 Jun 21 04:50:52 PM PDT 24 651897603 ps
T395 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2120647738 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:34 PM PDT 24 333573339 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1784905414 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:20 PM PDT 24 1108954851 ps
T128 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3999960281 Jun 21 04:49:21 PM PDT 24 Jun 21 04:50:06 PM PDT 24 2419051865 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1241256987 Jun 21 04:49:21 PM PDT 24 Jun 21 04:49:36 PM PDT 24 4812989543 ps
T125 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.47646947 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:48 PM PDT 24 161560378 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2495314097 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:33 PM PDT 24 97802918 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1187036863 Jun 21 04:49:30 PM PDT 24 Jun 21 04:49:56 PM PDT 24 1024404232 ps
T400 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3980672108 Jun 21 04:49:27 PM PDT 24 Jun 21 04:49:52 PM PDT 24 1726370875 ps
T126 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1399495491 Jun 21 04:49:10 PM PDT 24 Jun 21 04:49:49 PM PDT 24 305007246 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3238374999 Jun 21 04:49:27 PM PDT 24 Jun 21 04:49:45 PM PDT 24 2191679472 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3669783495 Jun 21 04:49:22 PM PDT 24 Jun 21 04:49:30 PM PDT 24 145545316 ps
T122 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1455020352 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:47 PM PDT 24 204418623 ps
T117 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.258355128 Jun 21 04:49:30 PM PDT 24 Jun 21 04:50:00 PM PDT 24 1475875405 ps
T403 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2554313014 Jun 21 04:49:22 PM PDT 24 Jun 21 04:49:38 PM PDT 24 1498270359 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.568718713 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:41 PM PDT 24 1665771894 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2840710079 Jun 21 04:49:06 PM PDT 24 Jun 21 04:49:21 PM PDT 24 1895501576 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.823100511 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:42 PM PDT 24 5740380552 ps
T407 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3639584224 Jun 21 04:49:28 PM PDT 24 Jun 21 04:50:36 PM PDT 24 56196085045 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3982868043 Jun 21 04:49:07 PM PDT 24 Jun 21 04:49:22 PM PDT 24 1847470390 ps
T409 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.219407597 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:13 PM PDT 24 85484858 ps
T410 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2399610320 Jun 21 04:49:27 PM PDT 24 Jun 21 04:50:14 PM PDT 24 645036528 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1148125694 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:18 PM PDT 24 2062423935 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3191724980 Jun 21 04:49:31 PM PDT 24 Jun 21 04:50:28 PM PDT 24 3255233558 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3294462831 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:33 PM PDT 24 89129394 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1978994807 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:22 PM PDT 24 4459293881 ps
T415 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3835644923 Jun 21 04:49:26 PM PDT 24 Jun 21 04:49:49 PM PDT 24 2210539990 ps
T416 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3276768446 Jun 21 04:49:25 PM PDT 24 Jun 21 04:49:43 PM PDT 24 5224945108 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4204291045 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:15 PM PDT 24 334141145 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.579390936 Jun 21 04:49:18 PM PDT 24 Jun 21 04:49:25 PM PDT 24 91084064 ps
T419 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3074794529 Jun 21 04:49:27 PM PDT 24 Jun 21 04:49:40 PM PDT 24 691654393 ps
T99 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.156419436 Jun 21 04:49:19 PM PDT 24 Jun 21 04:49:42 PM PDT 24 543265005 ps
T420 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.605381928 Jun 21 04:49:27 PM PDT 24 Jun 21 04:49:48 PM PDT 24 4167636027 ps
T123 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2635616113 Jun 21 04:49:24 PM PDT 24 Jun 21 04:50:38 PM PDT 24 425358088 ps
T421 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.475725395 Jun 21 04:49:21 PM PDT 24 Jun 21 04:49:30 PM PDT 24 346791556 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.455910666 Jun 21 04:49:20 PM PDT 24 Jun 21 04:49:27 PM PDT 24 86519703 ps
T423 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2973324418 Jun 21 04:49:26 PM PDT 24 Jun 21 04:49:46 PM PDT 24 1226019445 ps
T424 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3958404365 Jun 21 04:49:06 PM PDT 24 Jun 21 04:49:12 PM PDT 24 661555739 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3339227739 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:16 PM PDT 24 411040569 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3517279263 Jun 21 04:49:25 PM PDT 24 Jun 21 04:50:17 PM PDT 24 8793467272 ps
T427 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2629181526 Jun 21 04:49:21 PM PDT 24 Jun 21 04:49:35 PM PDT 24 1096393485 ps
T124 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3931829521 Jun 21 04:49:24 PM PDT 24 Jun 21 04:50:42 PM PDT 24 1369050258 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1581768876 Jun 21 04:49:26 PM PDT 24 Jun 21 04:49:40 PM PDT 24 253015494 ps
T429 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3830894104 Jun 21 04:49:28 PM PDT 24 Jun 21 04:49:45 PM PDT 24 5120607386 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2195239277 Jun 21 04:49:25 PM PDT 24 Jun 21 04:49:38 PM PDT 24 1802898741 ps
T431 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1097340562 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:44 PM PDT 24 9177255127 ps
T94 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3162628333 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:55 PM PDT 24 11407337803 ps
T432 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.333972058 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:34 PM PDT 24 108866411 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.669742978 Jun 21 04:49:30 PM PDT 24 Jun 21 04:49:57 PM PDT 24 2029922609 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2057644245 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:28 PM PDT 24 2176480958 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.205171856 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:25 PM PDT 24 1899961377 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1575080391 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:38 PM PDT 24 2272329815 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.283144956 Jun 21 04:49:30 PM PDT 24 Jun 21 04:50:53 PM PDT 24 2329743126 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4111238924 Jun 21 04:49:20 PM PDT 24 Jun 21 04:49:32 PM PDT 24 766571807 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2109515715 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:38 PM PDT 24 558033987 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1061180223 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:27 PM PDT 24 1860050239 ps
T440 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.429688996 Jun 21 04:49:23 PM PDT 24 Jun 21 04:50:46 PM PDT 24 115863196515 ps
T441 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1335283952 Jun 21 04:49:30 PM PDT 24 Jun 21 04:49:57 PM PDT 24 7532398063 ps
T442 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.760353736 Jun 21 04:49:27 PM PDT 24 Jun 21 04:50:49 PM PDT 24 4889241930 ps
T443 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.388760521 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:41 PM PDT 24 1487646996 ps
T444 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2986154727 Jun 21 04:49:11 PM PDT 24 Jun 21 04:49:19 PM PDT 24 333956320 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2286376082 Jun 21 04:49:10 PM PDT 24 Jun 21 04:49:18 PM PDT 24 388620583 ps
T96 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1622411666 Jun 21 04:49:22 PM PDT 24 Jun 21 04:50:02 PM PDT 24 3132469537 ps
T446 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3863834773 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:37 PM PDT 24 1077989366 ps
T127 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4139220365 Jun 21 04:49:29 PM PDT 24 Jun 21 04:50:50 PM PDT 24 1745857716 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1253322995 Jun 21 04:49:24 PM PDT 24 Jun 21 04:50:25 PM PDT 24 5222642406 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1095983316 Jun 21 04:49:08 PM PDT 24 Jun 21 04:49:18 PM PDT 24 836626449 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2822891835 Jun 21 04:49:07 PM PDT 24 Jun 21 04:49:22 PM PDT 24 9856302239 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2072113066 Jun 21 04:49:17 PM PDT 24 Jun 21 04:49:30 PM PDT 24 1235758095 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2243291595 Jun 21 04:49:07 PM PDT 24 Jun 21 04:49:26 PM PDT 24 9466861188 ps
T450 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2034996140 Jun 21 04:49:23 PM PDT 24 Jun 21 04:49:30 PM PDT 24 519427880 ps
T451 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2452524695 Jun 21 04:49:31 PM PDT 24 Jun 21 04:50:02 PM PDT 24 735733862 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2552471162 Jun 21 04:49:28 PM PDT 24 Jun 21 04:49:56 PM PDT 24 1761215903 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.300683639 Jun 21 04:49:09 PM PDT 24 Jun 21 04:49:18 PM PDT 24 743329870 ps
T454 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2108984043 Jun 21 04:49:30 PM PDT 24 Jun 21 04:49:46 PM PDT 24 182890837 ps
T455 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2148405792 Jun 21 04:49:28 PM PDT 24 Jun 21 04:49:47 PM PDT 24 2587884010 ps
T456 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3794660379 Jun 21 04:49:36 PM PDT 24 Jun 21 04:50:00 PM PDT 24 3546155500 ps
T457 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2478706641 Jun 21 04:49:26 PM PDT 24 Jun 21 04:50:51 PM PDT 24 2089451554 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3481321247 Jun 21 04:49:11 PM PDT 24 Jun 21 04:49:26 PM PDT 24 4121440351 ps
T459 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3409272194 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:35 PM PDT 24 89961319 ps
T460 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.83477718 Jun 21 04:49:24 PM PDT 24 Jun 21 04:49:43 PM PDT 24 1548469472 ps

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2789568851
Short name T4
Test name
Test status
Simulation time 41777645825 ps
CPU time 2790.54 seconds
Started Jun 21 05:18:13 PM PDT 24
Finished Jun 21 06:04:45 PM PDT 24
Peak memory 236688 kb
Host smart-64c1a877-a2e6-49c6-80e1-08f7598cedbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789568851 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2789568851
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2663180807
Short name T16
Test name
Test status
Simulation time 150356152254 ps
CPU time 396.57 seconds
Started Jun 21 05:19:11 PM PDT 24
Finished Jun 21 05:25:49 PM PDT 24
Peak memory 212520 kb
Host smart-c3001f30-56fa-41c9-b381-279c382dbcde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663180807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2663180807
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1135592593
Short name T188
Test name
Test status
Simulation time 17206469933 ps
CPU time 136.47 seconds
Started Jun 21 05:19:38 PM PDT 24
Finished Jun 21 05:21:55 PM PDT 24
Peak memory 234532 kb
Host smart-e3daef44-6bed-4f1f-a8dc-76f1e4fa8e05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135592593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1135592593
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2916252169
Short name T118
Test name
Test status
Simulation time 5996069809 ps
CPU time 71.38 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:50:21 PM PDT 24
Peak memory 213016 kb
Host smart-631e4803-e970-4c81-9955-fa3da00222f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916252169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2916252169
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2266181814
Short name T11
Test name
Test status
Simulation time 760664068 ps
CPU time 40.44 seconds
Started Jun 21 05:18:43 PM PDT 24
Finished Jun 21 05:19:24 PM PDT 24
Peak memory 216868 kb
Host smart-1943a4be-d09f-4602-9b12-c419aac2bb34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266181814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2266181814
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2753519150
Short name T19
Test name
Test status
Simulation time 2143959265 ps
CPU time 109.67 seconds
Started Jun 21 05:17:41 PM PDT 24
Finished Jun 21 05:19:32 PM PDT 24
Peak memory 235784 kb
Host smart-e59d5473-f4d0-47b3-b19e-610232847cdb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753519150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2753519150
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1705740862
Short name T79
Test name
Test status
Simulation time 12264609467 ps
CPU time 11.98 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:42 PM PDT 24
Peak memory 211472 kb
Host smart-085f82b9-67ed-4284-8891-56a2ab8febd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705740862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1705740862
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3624459957
Short name T63
Test name
Test status
Simulation time 1526640015 ps
CPU time 68.73 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:50:36 PM PDT 24
Peak memory 219504 kb
Host smart-4b5a057f-9333-4900-81d6-282ddebebe9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624459957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3624459957
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.594253092
Short name T22
Test name
Test status
Simulation time 98727847312 ps
CPU time 907.19 seconds
Started Jun 21 05:20:23 PM PDT 24
Finished Jun 21 05:35:32 PM PDT 24
Peak memory 235756 kb
Host smart-19597d41-67f1-4ab3-82b3-ea984b71a208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594253092 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.594253092
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4134025377
Short name T6
Test name
Test status
Simulation time 2802336477 ps
CPU time 8.34 seconds
Started Jun 21 05:18:50 PM PDT 24
Finished Jun 21 05:19:00 PM PDT 24
Peak memory 211096 kb
Host smart-609cf44c-65bc-48e1-92fe-313e6cc3225e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134025377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4134025377
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1487144701
Short name T51
Test name
Test status
Simulation time 183252376 ps
CPU time 9.53 seconds
Started Jun 21 05:17:51 PM PDT 24
Finished Jun 21 05:18:02 PM PDT 24
Peak memory 211716 kb
Host smart-102f249e-ed4c-4191-9452-50e7df082372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487144701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1487144701
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3579518758
Short name T55
Test name
Test status
Simulation time 3454150004 ps
CPU time 29.76 seconds
Started Jun 21 05:18:21 PM PDT 24
Finished Jun 21 05:18:51 PM PDT 24
Peak memory 211892 kb
Host smart-e4303d08-6259-4180-8f2d-12b2129560da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579518758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3579518758
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2191928664
Short name T54
Test name
Test status
Simulation time 1876285886 ps
CPU time 21.43 seconds
Started Jun 21 05:19:39 PM PDT 24
Finished Jun 21 05:20:01 PM PDT 24
Peak memory 211732 kb
Host smart-17c90bbb-9159-4997-98ca-987c95773252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191928664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2191928664
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.48772851
Short name T44
Test name
Test status
Simulation time 2862719994 ps
CPU time 16.05 seconds
Started Jun 21 05:17:57 PM PDT 24
Finished Jun 21 05:18:13 PM PDT 24
Peak memory 215132 kb
Host smart-35d1456e-133d-429c-870a-150f1c7316fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48772851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.rom_ctrl_stress_all.48772851
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.599020279
Short name T120
Test name
Test status
Simulation time 651897603 ps
CPU time 70.95 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:50:52 PM PDT 24
Peak memory 219520 kb
Host smart-540b5596-cd77-454b-92ea-9b2eff5925d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599020279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.599020279
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3773033560
Short name T115
Test name
Test status
Simulation time 6766099220 ps
CPU time 27.9 seconds
Started Jun 21 04:49:07 PM PDT 24
Finished Jun 21 04:49:36 PM PDT 24
Peak memory 211500 kb
Host smart-36189f82-bc62-433f-9286-745825c52e24
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773033560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3773033560
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.618574224
Short name T42
Test name
Test status
Simulation time 6719318086 ps
CPU time 103.69 seconds
Started Jun 21 05:18:20 PM PDT 24
Finished Jun 21 05:20:05 PM PDT 24
Peak memory 227780 kb
Host smart-dd5d6c08-28b4-4c80-baee-6de05617ae18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618574224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.618574224
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.283144956
Short name T436
Test name
Test status
Simulation time 2329743126 ps
CPU time 71.06 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:50:53 PM PDT 24
Peak memory 219664 kb
Host smart-d5392598-e642-462b-a84b-5c5648218d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283144956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.283144956
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1311621030
Short name T110
Test name
Test status
Simulation time 1378083195 ps
CPU time 12.42 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:24 PM PDT 24
Peak memory 211336 kb
Host smart-35e9a82a-53fe-4758-83d2-fb50f66eb71a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311621030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1311621030
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4135875608
Short name T100
Test name
Test status
Simulation time 393810117 ps
CPU time 5.88 seconds
Started Jun 21 05:17:58 PM PDT 24
Finished Jun 21 05:18:04 PM PDT 24
Peak memory 211220 kb
Host smart-257ba83d-9346-485b-8323-e1de33edb78f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135875608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4135875608
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3481321247
Short name T458
Test name
Test status
Simulation time 4121440351 ps
CPU time 13.39 seconds
Started Jun 21 04:49:11 PM PDT 24
Finished Jun 21 04:49:26 PM PDT 24
Peak memory 211464 kb
Host smart-5866727a-4bcc-47c1-88a4-c30006d537c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481321247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3481321247
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3052110483
Short name T373
Test name
Test status
Simulation time 174739727 ps
CPU time 5.65 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:17 PM PDT 24
Peak memory 211228 kb
Host smart-ed21d982-bced-428b-a6eb-0c44d8fdee62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052110483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3052110483
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2822891835
Short name T97
Test name
Test status
Simulation time 9856302239 ps
CPU time 14.05 seconds
Started Jun 21 04:49:07 PM PDT 24
Finished Jun 21 04:49:22 PM PDT 24
Peak memory 219500 kb
Host smart-ebe4ad42-c16a-4e9c-b9e3-25e8ed6df27a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822891835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2822891835
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1765315223
Short name T361
Test name
Test status
Simulation time 433670782 ps
CPU time 8.55 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:20 PM PDT 24
Peak memory 219476 kb
Host smart-56be4bc4-499c-4e2c-84bb-1d7b84f98054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765315223 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1765315223
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1978994807
Short name T414
Test name
Test status
Simulation time 4459293881 ps
CPU time 12.73 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:22 PM PDT 24
Peak memory 211132 kb
Host smart-6f40dae9-cb98-40c2-9bf9-83a31c197857
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978994807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1978994807
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.219407597
Short name T409
Test name
Test status
Simulation time 85484858 ps
CPU time 4.3 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:13 PM PDT 24
Peak memory 211204 kb
Host smart-bbec3a30-c8b7-47c0-b97a-c7ca9718adc6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219407597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
219407597
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3162628333
Short name T94
Test name
Test status
Simulation time 11407337803 ps
CPU time 43.97 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:55 PM PDT 24
Peak memory 219632 kb
Host smart-67359f90-c88e-45d0-adf3-586539aa0e22
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162628333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3162628333
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2840710079
Short name T405
Test name
Test status
Simulation time 1895501576 ps
CPU time 14.76 seconds
Started Jun 21 04:49:06 PM PDT 24
Finished Jun 21 04:49:21 PM PDT 24
Peak memory 219480 kb
Host smart-3ced2d5c-c2fa-461f-80db-abddcf5410e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840710079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2840710079
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2057644245
Short name T434
Test name
Test status
Simulation time 2176480958 ps
CPU time 18.45 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:28 PM PDT 24
Peak memory 219500 kb
Host smart-eeeecfdd-c5f2-4ac9-ab2f-99d853cce4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057644245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2057644245
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.205171856
Short name T435
Test name
Test status
Simulation time 1899961377 ps
CPU time 15.01 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:25 PM PDT 24
Peak memory 219276 kb
Host smart-02b03bfa-3133-4c6e-a16b-0582455177a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205171856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.205171856
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1061180223
Short name T439
Test name
Test status
Simulation time 1860050239 ps
CPU time 15.02 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:27 PM PDT 24
Peak memory 211404 kb
Host smart-ca618703-4526-4b07-9734-998b9146f07d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061180223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1061180223
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.300683639
Short name T453
Test name
Test status
Simulation time 743329870 ps
CPU time 7.11 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:18 PM PDT 24
Peak memory 219548 kb
Host smart-8112f7a1-d8d1-4628-8a61-ee0fd27f859d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300683639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.300683639
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2286376082
Short name T445
Test name
Test status
Simulation time 388620583 ps
CPU time 5.37 seconds
Started Jun 21 04:49:10 PM PDT 24
Finished Jun 21 04:49:18 PM PDT 24
Peak memory 219644 kb
Host smart-98befb19-28e9-413e-a4f5-42f3ac568462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286376082 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2286376082
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1239718329
Short name T116
Test name
Test status
Simulation time 1403090428 ps
CPU time 11.91 seconds
Started Jun 21 04:49:11 PM PDT 24
Finished Jun 21 04:49:25 PM PDT 24
Peak memory 211304 kb
Host smart-c0aeeb53-1fd7-4e04-b759-4c81d246a217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239718329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1239718329
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1824409517
Short name T371
Test name
Test status
Simulation time 3753972180 ps
CPU time 9.63 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:21 PM PDT 24
Peak memory 211316 kb
Host smart-d991e86b-1d30-4eed-afd5-ecc855048f85
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824409517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1824409517
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3152433753
Short name T362
Test name
Test status
Simulation time 7609188046 ps
CPU time 14.69 seconds
Started Jun 21 04:49:07 PM PDT 24
Finished Jun 21 04:49:23 PM PDT 24
Peak memory 211292 kb
Host smart-3ec8ab93-b232-43c4-bb1f-8ee705106f84
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152433753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3152433753
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3394409927
Short name T82
Test name
Test status
Simulation time 4015301405 ps
CPU time 18.6 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:27 PM PDT 24
Peak memory 211440 kb
Host smart-3077f8f2-527c-4626-96e7-8cef0579219e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394409927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3394409927
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1148125694
Short name T411
Test name
Test status
Simulation time 2062423935 ps
CPU time 7.54 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:18 PM PDT 24
Peak memory 218360 kb
Host smart-70d98bfb-1848-4b70-a7b8-d9c9366c8e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148125694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1148125694
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2486087672
Short name T370
Test name
Test status
Simulation time 122946920 ps
CPU time 6.8 seconds
Started Jun 21 04:49:07 PM PDT 24
Finished Jun 21 04:49:15 PM PDT 24
Peak memory 219444 kb
Host smart-5982b874-d608-400d-bbef-7f6e2a1903c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486087672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2486087672
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1455020352
Short name T122
Test name
Test status
Simulation time 204418623 ps
CPU time 37.96 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:47 PM PDT 24
Peak memory 211464 kb
Host smart-8b0a94dd-fd02-4432-b72e-44c975b910a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455020352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1455020352
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.605381928
Short name T420
Test name
Test status
Simulation time 4167636027 ps
CPU time 11.22 seconds
Started Jun 21 04:49:27 PM PDT 24
Finished Jun 21 04:49:48 PM PDT 24
Peak memory 219716 kb
Host smart-18ac93d6-59de-4e8e-9515-bebeeb6c380b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605381928 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.605381928
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.823100511
Short name T406
Test name
Test status
Simulation time 5740380552 ps
CPU time 12.94 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:42 PM PDT 24
Peak memory 211416 kb
Host smart-12218c32-5f5c-44ed-a659-fada487f7152
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823100511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.823100511
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1622411666
Short name T96
Test name
Test status
Simulation time 3132469537 ps
CPU time 35.7 seconds
Started Jun 21 04:49:22 PM PDT 24
Finished Jun 21 04:50:02 PM PDT 24
Peak memory 211484 kb
Host smart-cc9e7984-2975-4070-9f58-068b1b40f5bb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622411666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1622411666
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3863834773
Short name T446
Test name
Test status
Simulation time 1077989366 ps
CPU time 9.42 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:37 PM PDT 24
Peak memory 219468 kb
Host smart-dfe84134-174a-4f54-b8ed-bc79b986f6a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863834773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3863834773
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3874846204
Short name T368
Test name
Test status
Simulation time 814067897 ps
CPU time 11.07 seconds
Started Jun 21 04:49:21 PM PDT 24
Finished Jun 21 04:49:36 PM PDT 24
Peak memory 219528 kb
Host smart-320250e2-5995-4fd8-b03d-c7211b1f97d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874846204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3874846204
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3931829521
Short name T124
Test name
Test status
Simulation time 1369050258 ps
CPU time 73.23 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:50:42 PM PDT 24
Peak memory 219544 kb
Host smart-277b4f7d-f1ea-4543-87e6-2550e2057774
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931829521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3931829521
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.635308912
Short name T377
Test name
Test status
Simulation time 7320738940 ps
CPU time 14.71 seconds
Started Jun 21 04:49:22 PM PDT 24
Finished Jun 21 04:49:41 PM PDT 24
Peak memory 219716 kb
Host smart-dbd5745f-01b2-4ca9-ad8b-d6b74dafc09a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635308912 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.635308912
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1120573505
Short name T92
Test name
Test status
Simulation time 19059437110 ps
CPU time 39.65 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:50:21 PM PDT 24
Peak memory 211460 kb
Host smart-097dd687-c66f-4541-acce-eb9f612a0165
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120573505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1120573505
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1097340562
Short name T431
Test name
Test status
Simulation time 9177255127 ps
CPU time 14.82 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:44 PM PDT 24
Peak memory 219580 kb
Host smart-59c31c8c-8a04-43fc-b2e2-b8f114051e6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097340562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1097340562
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2859869171
Short name T364
Test name
Test status
Simulation time 29965657742 ps
CPU time 17.44 seconds
Started Jun 21 04:49:21 PM PDT 24
Finished Jun 21 04:49:41 PM PDT 24
Peak memory 219576 kb
Host smart-c3503810-9eef-46a2-bed7-559c1098272f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859869171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2859869171
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.950603111
Short name T385
Test name
Test status
Simulation time 351294550 ps
CPU time 4.43 seconds
Started Jun 21 04:49:27 PM PDT 24
Finished Jun 21 04:49:42 PM PDT 24
Peak memory 219524 kb
Host smart-e882f8f9-b949-4f25-8eff-3c155f7b68a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950603111 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.950603111
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.669742978
Short name T433
Test name
Test status
Simulation time 2029922609 ps
CPU time 15.73 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:49:57 PM PDT 24
Peak memory 211280 kb
Host smart-389f318d-b699-4d05-a77c-2b40bc512a54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669742978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.669742978
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4062904548
Short name T91
Test name
Test status
Simulation time 1537055042 ps
CPU time 37.25 seconds
Started Jun 21 04:49:26 PM PDT 24
Finished Jun 21 04:50:12 PM PDT 24
Peak memory 211400 kb
Host smart-4efe109f-8762-4c85-816e-c03b4a844c5b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062904548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4062904548
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3074794529
Short name T419
Test name
Test status
Simulation time 691654393 ps
CPU time 4.37 seconds
Started Jun 21 04:49:27 PM PDT 24
Finished Jun 21 04:49:40 PM PDT 24
Peak memory 219512 kb
Host smart-5850ae0f-5a77-4b48-86c3-70ccc9b976b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074794529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3074794529
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3780421925
Short name T360
Test name
Test status
Simulation time 4468137295 ps
CPU time 15.47 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:45 PM PDT 24
Peak memory 219572 kb
Host smart-a5734049-ccf6-4c0e-8ddf-9808ab6085a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780421925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3780421925
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2478706641
Short name T457
Test name
Test status
Simulation time 2089451554 ps
CPU time 76.62 seconds
Started Jun 21 04:49:26 PM PDT 24
Finished Jun 21 04:50:51 PM PDT 24
Peak memory 219520 kb
Host smart-3aa0a332-4a5a-49f8-bd1e-80c869069f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478706641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2478706641
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3276768446
Short name T416
Test name
Test status
Simulation time 5224945108 ps
CPU time 11.93 seconds
Started Jun 21 04:49:25 PM PDT 24
Finished Jun 21 04:49:43 PM PDT 24
Peak memory 219664 kb
Host smart-85db87aa-935e-4184-a8e8-03ae3c803887
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276768446 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3276768446
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.188414099
Short name T380
Test name
Test status
Simulation time 8030078661 ps
CPU time 15.43 seconds
Started Jun 21 04:49:26 PM PDT 24
Finished Jun 21 04:49:48 PM PDT 24
Peak memory 219620 kb
Host smart-f8a342d9-e39d-49ea-bd6e-83e7938d419c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188414099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.188414099
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3639584224
Short name T407
Test name
Test status
Simulation time 56196085045 ps
CPU time 57.54 seconds
Started Jun 21 04:49:28 PM PDT 24
Finished Jun 21 04:50:36 PM PDT 24
Peak memory 211552 kb
Host smart-25fad4c8-2b0c-4343-9b99-9db9c6476d83
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639584224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3639584224
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3597292685
Short name T73
Test name
Test status
Simulation time 86633605 ps
CPU time 4.32 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:49:46 PM PDT 24
Peak memory 211344 kb
Host smart-4fab027d-c2e9-470a-a87a-a1c4ee029920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597292685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3597292685
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2973324418
Short name T423
Test name
Test status
Simulation time 1226019445 ps
CPU time 12.55 seconds
Started Jun 21 04:49:26 PM PDT 24
Finished Jun 21 04:49:46 PM PDT 24
Peak memory 219488 kb
Host smart-fa5b6319-a116-48a6-942c-3c1ecb82496d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973324418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2973324418
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3980672108
Short name T400
Test name
Test status
Simulation time 1726370875 ps
CPU time 15.78 seconds
Started Jun 21 04:49:27 PM PDT 24
Finished Jun 21 04:49:52 PM PDT 24
Peak memory 219560 kb
Host smart-e035a42b-c46e-4c86-8ba0-d146c88041bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980672108 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3980672108
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1581768876
Short name T428
Test name
Test status
Simulation time 253015494 ps
CPU time 5.92 seconds
Started Jun 21 04:49:26 PM PDT 24
Finished Jun 21 04:49:40 PM PDT 24
Peak memory 211344 kb
Host smart-f007423d-e038-426a-9dd7-f30724c829e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581768876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1581768876
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2452524695
Short name T451
Test name
Test status
Simulation time 735733862 ps
CPU time 19.37 seconds
Started Jun 21 04:49:31 PM PDT 24
Finished Jun 21 04:50:02 PM PDT 24
Peak memory 211432 kb
Host smart-c3e9c11c-1574-49eb-ab05-a4a7fbb67518
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452524695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2452524695
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3835644923
Short name T415
Test name
Test status
Simulation time 2210539990 ps
CPU time 16.31 seconds
Started Jun 21 04:49:26 PM PDT 24
Finished Jun 21 04:49:49 PM PDT 24
Peak memory 211524 kb
Host smart-18b2376f-9608-4f8f-ab0a-d27e4fe0858d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835644923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3835644923
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3709349064
Short name T386
Test name
Test status
Simulation time 498194107 ps
CPU time 7.34 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:38 PM PDT 24
Peak memory 219528 kb
Host smart-54c75c71-03d6-4a21-9cf9-f62ee4b598fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709349064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3709349064
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3517279263
Short name T426
Test name
Test status
Simulation time 8793467272 ps
CPU time 46.77 seconds
Started Jun 21 04:49:25 PM PDT 24
Finished Jun 21 04:50:17 PM PDT 24
Peak memory 213056 kb
Host smart-ae9d41ca-e8a2-4e17-b0b7-a69ec20eef3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517279263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3517279263
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2336502458
Short name T67
Test name
Test status
Simulation time 96606912 ps
CPU time 5.55 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:49:47 PM PDT 24
Peak memory 219528 kb
Host smart-ac7ab5bb-daf0-461b-9af9-c9141ce521de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336502458 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2336502458
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.566720621
Short name T75
Test name
Test status
Simulation time 838771287 ps
CPU time 9.29 seconds
Started Jun 21 04:49:29 PM PDT 24
Finished Jun 21 04:49:49 PM PDT 24
Peak memory 211400 kb
Host smart-292a84c5-d599-48eb-a365-29ed8dbcdab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566720621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.566720621
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.523465615
Short name T80
Test name
Test status
Simulation time 13986455095 ps
CPU time 66.5 seconds
Started Jun 21 04:49:27 PM PDT 24
Finished Jun 21 04:50:44 PM PDT 24
Peak memory 211456 kb
Host smart-6e0f3ef1-1dcf-430d-9c21-37b0c7e16c3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523465615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.523465615
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1335283952
Short name T441
Test name
Test status
Simulation time 7532398063 ps
CPU time 15.6 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:49:57 PM PDT 24
Peak memory 219588 kb
Host smart-a39b4fa9-9e7c-487a-82c0-6c80ae921e50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335283952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1335283952
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1509741274
Short name T365
Test name
Test status
Simulation time 3536623326 ps
CPU time 10 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:49:50 PM PDT 24
Peak memory 219576 kb
Host smart-7fb782d2-9916-4e1d-850d-9edea1da92f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509741274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1509741274
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.760353736
Short name T442
Test name
Test status
Simulation time 4889241930 ps
CPU time 71.96 seconds
Started Jun 21 04:49:27 PM PDT 24
Finished Jun 21 04:50:49 PM PDT 24
Peak memory 219628 kb
Host smart-24f5a130-ab00-4702-8511-368112312156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760353736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.760353736
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1091208941
Short name T363
Test name
Test status
Simulation time 1787279383 ps
CPU time 14.34 seconds
Started Jun 21 04:49:36 PM PDT 24
Finished Jun 21 04:50:01 PM PDT 24
Peak memory 219544 kb
Host smart-0c5f0e4a-49c5-4386-8146-6fe45f0b7e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091208941 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1091208941
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2148405792
Short name T455
Test name
Test status
Simulation time 2587884010 ps
CPU time 8.54 seconds
Started Jun 21 04:49:28 PM PDT 24
Finished Jun 21 04:49:47 PM PDT 24
Peak memory 219608 kb
Host smart-d73ce6f0-b31f-47d8-9f30-f077c3e8bdd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148405792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2148405792
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1936099637
Short name T383
Test name
Test status
Simulation time 11129423945 ps
CPU time 50.7 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:50:32 PM PDT 24
Peak memory 218600 kb
Host smart-513a70ac-6c07-4ed3-b2aa-1b099d5e5a02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936099637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1936099637
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2108984043
Short name T454
Test name
Test status
Simulation time 182890837 ps
CPU time 4.31 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:49:46 PM PDT 24
Peak memory 211404 kb
Host smart-3aa5e128-e9f1-4821-b8a8-9a8dfa59d5f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108984043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2108984043
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4116815786
Short name T376
Test name
Test status
Simulation time 86511462 ps
CPU time 6.23 seconds
Started Jun 21 04:49:28 PM PDT 24
Finished Jun 21 04:49:44 PM PDT 24
Peak memory 219452 kb
Host smart-fa6db3da-882c-4671-9ac5-9ae0150983bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116815786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4116815786
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3191724980
Short name T412
Test name
Test status
Simulation time 3255233558 ps
CPU time 45.03 seconds
Started Jun 21 04:49:31 PM PDT 24
Finished Jun 21 04:50:28 PM PDT 24
Peak memory 219616 kb
Host smart-463f2e7b-04c3-49a5-8056-9d9a6f8b4315
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191724980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3191724980
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1715488964
Short name T394
Test name
Test status
Simulation time 2685835767 ps
CPU time 8.28 seconds
Started Jun 21 04:49:34 PM PDT 24
Finished Jun 21 04:49:53 PM PDT 24
Peak memory 219684 kb
Host smart-ab5fe06c-0ff6-489b-aa85-de9d1e6a78b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715488964 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1715488964
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3794660379
Short name T456
Test name
Test status
Simulation time 3546155500 ps
CPU time 13.55 seconds
Started Jun 21 04:49:36 PM PDT 24
Finished Jun 21 04:50:00 PM PDT 24
Peak memory 219560 kb
Host smart-1506bcfe-ddf9-4eeb-a6b2-0274d12993af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794660379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3794660379
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.258355128
Short name T117
Test name
Test status
Simulation time 1475875405 ps
CPU time 18.27 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:50:00 PM PDT 24
Peak memory 211400 kb
Host smart-b31d47cc-3c13-4431-9e2c-296cc08f9b8a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258355128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.258355128
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1899945531
Short name T111
Test name
Test status
Simulation time 1988029996 ps
CPU time 15.78 seconds
Started Jun 21 04:49:36 PM PDT 24
Finished Jun 21 04:50:02 PM PDT 24
Peak memory 211304 kb
Host smart-5538516b-c7ff-4cc6-a9a6-77b315091267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899945531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1899945531
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1499439022
Short name T389
Test name
Test status
Simulation time 5078222327 ps
CPU time 14.79 seconds
Started Jun 21 04:49:32 PM PDT 24
Finished Jun 21 04:49:59 PM PDT 24
Peak memory 219648 kb
Host smart-8114c38e-8760-4035-b276-925173ccce58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499439022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1499439022
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2338621408
Short name T121
Test name
Test status
Simulation time 6565468410 ps
CPU time 74.16 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:50:56 PM PDT 24
Peak memory 219696 kb
Host smart-2bdf1d3f-453d-4b76-83b0-5304d7da5566
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338621408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2338621408
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3250737034
Short name T382
Test name
Test status
Simulation time 5794814185 ps
CPU time 10.19 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:38 PM PDT 24
Peak memory 219724 kb
Host smart-6ededf3f-e072-4a24-bb5e-b2d8dca9461d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250737034 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3250737034
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3409272194
Short name T459
Test name
Test status
Simulation time 89961319 ps
CPU time 4.36 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:35 PM PDT 24
Peak memory 211336 kb
Host smart-5da4ec8c-0d4a-405b-a39a-5ab0f4b58d2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409272194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3409272194
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2960410767
Short name T375
Test name
Test status
Simulation time 2267190752 ps
CPU time 43.4 seconds
Started Jun 21 04:49:32 PM PDT 24
Finished Jun 21 04:50:27 PM PDT 24
Peak memory 211452 kb
Host smart-80084806-6af3-41b7-a555-7a3cecad7a36
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960410767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2960410767
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.83477718
Short name T460
Test name
Test status
Simulation time 1548469472 ps
CPU time 13.45 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:43 PM PDT 24
Peak memory 219460 kb
Host smart-92d3f9cb-e566-4b5a-a17d-117955bd9f4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83477718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ct
rl_same_csr_outstanding.83477718
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2552471162
Short name T452
Test name
Test status
Simulation time 1761215903 ps
CPU time 17.75 seconds
Started Jun 21 04:49:28 PM PDT 24
Finished Jun 21 04:49:56 PM PDT 24
Peak memory 219400 kb
Host smart-1f668a8d-eaeb-4f53-8180-79652662d877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552471162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2552471162
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2399610320
Short name T410
Test name
Test status
Simulation time 645036528 ps
CPU time 39.22 seconds
Started Jun 21 04:49:27 PM PDT 24
Finished Jun 21 04:50:14 PM PDT 24
Peak memory 211408 kb
Host smart-270e6caf-8d88-4e7f-b206-077a2c02e260
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399610320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2399610320
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3238374999
Short name T401
Test name
Test status
Simulation time 2191679472 ps
CPU time 7.99 seconds
Started Jun 21 04:49:27 PM PDT 24
Finished Jun 21 04:49:45 PM PDT 24
Peak memory 219740 kb
Host smart-5f2a6370-090b-4a3b-9a44-48a84de19ae3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238374999 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3238374999
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.388760521
Short name T443
Test name
Test status
Simulation time 1487646996 ps
CPU time 12.57 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:41 PM PDT 24
Peak memory 219484 kb
Host smart-cae28eb4-5c63-4b4c-82c9-b7e887e8cbde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388760521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.388760521
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.429688996
Short name T440
Test name
Test status
Simulation time 115863196515 ps
CPU time 77.29 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:50:46 PM PDT 24
Peak memory 211436 kb
Host smart-c9e03297-c85f-438c-804b-ceecf23a5c40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429688996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.429688996
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3294462831
Short name T413
Test name
Test status
Simulation time 89129394 ps
CPU time 4.39 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:33 PM PDT 24
Peak memory 218728 kb
Host smart-bf9c36bc-0902-4f3a-82d5-12db83fe9e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294462831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3294462831
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.333972058
Short name T432
Test name
Test status
Simulation time 108866411 ps
CPU time 5.9 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:34 PM PDT 24
Peak memory 215892 kb
Host smart-3d0009b3-dac8-4f73-a491-72e17155376c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333972058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.333972058
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4139220365
Short name T127
Test name
Test status
Simulation time 1745857716 ps
CPU time 70.16 seconds
Started Jun 21 04:49:29 PM PDT 24
Finished Jun 21 04:50:50 PM PDT 24
Peak memory 219544 kb
Host smart-4a56f031-27e3-4eeb-8fee-8570b41b0db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139220365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4139220365
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.239200576
Short name T388
Test name
Test status
Simulation time 7874002357 ps
CPU time 15.41 seconds
Started Jun 21 04:49:05 PM PDT 24
Finished Jun 21 04:49:21 PM PDT 24
Peak memory 219256 kb
Host smart-cd13b2ec-7d3c-4f61-9460-d5f7ff196847
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239200576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.239200576
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.216292405
Short name T384
Test name
Test status
Simulation time 833450186 ps
CPU time 5.59 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:16 PM PDT 24
Peak memory 211352 kb
Host smart-52979eff-842e-430d-be0d-3b097f3689fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216292405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.216292405
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3645117621
Short name T74
Test name
Test status
Simulation time 215246610 ps
CPU time 7.22 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:18 PM PDT 24
Peak memory 219456 kb
Host smart-5d23bede-bc78-4337-be02-23680328ab3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645117621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3645117621
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1650965622
Short name T66
Test name
Test status
Simulation time 10378277871 ps
CPU time 11.51 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:21 PM PDT 24
Peak memory 219524 kb
Host smart-fc477be5-9f93-4a3f-9ed7-87bb4f2505fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650965622 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1650965622
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1095983316
Short name T448
Test name
Test status
Simulation time 836626449 ps
CPU time 9.41 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:18 PM PDT 24
Peak memory 219436 kb
Host smart-ce5a9e73-3d82-4b13-83ad-a8976ea1b5c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095983316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1095983316
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4204291045
Short name T417
Test name
Test status
Simulation time 334141145 ps
CPU time 4.05 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:15 PM PDT 24
Peak memory 211120 kb
Host smart-3574013a-d1e7-4f57-bc3e-72a98750f852
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204291045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4204291045
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1940159444
Short name T366
Test name
Test status
Simulation time 16429750796 ps
CPU time 10.81 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:22 PM PDT 24
Peak memory 211324 kb
Host smart-338967cf-7ff6-4b2d-b22e-00c7fb00f804
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940159444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1940159444
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2109515715
Short name T438
Test name
Test status
Simulation time 558033987 ps
CPU time 27.3 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:38 PM PDT 24
Peak memory 211368 kb
Host smart-1c7cb9f4-b54e-4f2e-a0dc-8cee3c286510
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109515715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2109515715
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1115730638
Short name T109
Test name
Test status
Simulation time 3527689528 ps
CPU time 10.37 seconds
Started Jun 21 04:49:10 PM PDT 24
Finished Jun 21 04:49:22 PM PDT 24
Peak memory 219516 kb
Host smart-670542d7-01e9-413f-b26e-aa08cf259b19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115730638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1115730638
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.908495597
Short name T381
Test name
Test status
Simulation time 3802977743 ps
CPU time 12.43 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:22 PM PDT 24
Peak memory 219632 kb
Host smart-2694fd53-48f6-4d25-bd4c-91e50fa9ad71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908495597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.908495597
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.47646947
Short name T125
Test name
Test status
Simulation time 161560378 ps
CPU time 36.4 seconds
Started Jun 21 04:49:09 PM PDT 24
Finished Jun 21 04:49:48 PM PDT 24
Peak memory 212656 kb
Host smart-0eaff0bc-f668-4ffd-b3a6-dae968c2dee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47646947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg
_err.47646947
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1418248431
Short name T392
Test name
Test status
Simulation time 1960371090 ps
CPU time 16.22 seconds
Started Jun 21 04:49:11 PM PDT 24
Finished Jun 21 04:49:29 PM PDT 24
Peak memory 219396 kb
Host smart-cd41d5bd-a40d-488e-abfb-bb8546cc5388
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418248431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1418248431
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1784905414
Short name T396
Test name
Test status
Simulation time 1108954851 ps
CPU time 10.48 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:20 PM PDT 24
Peak memory 211392 kb
Host smart-eb811f7a-8edb-477f-97a4-2d49457b2ba4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784905414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1784905414
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2243291595
Short name T98
Test name
Test status
Simulation time 9466861188 ps
CPU time 18.72 seconds
Started Jun 21 04:49:07 PM PDT 24
Finished Jun 21 04:49:26 PM PDT 24
Peak memory 219640 kb
Host smart-50e7aa7e-ce0e-4b0a-b317-dcabee2b56da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243291595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2243291595
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1121580577
Short name T369
Test name
Test status
Simulation time 8104312397 ps
CPU time 15.84 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:25 PM PDT 24
Peak memory 219664 kb
Host smart-077bb969-50e5-4da0-9b9a-8d3b8cd1bb15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121580577 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1121580577
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1358447582
Short name T81
Test name
Test status
Simulation time 4971414801 ps
CPU time 11.72 seconds
Started Jun 21 04:49:07 PM PDT 24
Finished Jun 21 04:49:19 PM PDT 24
Peak memory 211452 kb
Host smart-bb8ad8d9-6a43-4f99-88a8-a034bb65da46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358447582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1358447582
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3958404365
Short name T424
Test name
Test status
Simulation time 661555739 ps
CPU time 5.31 seconds
Started Jun 21 04:49:06 PM PDT 24
Finished Jun 21 04:49:12 PM PDT 24
Peak memory 211152 kb
Host smart-6da81f45-3cb6-4852-8a11-ec1b48ce1715
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958404365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3958404365
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3982868043
Short name T408
Test name
Test status
Simulation time 1847470390 ps
CPU time 13.91 seconds
Started Jun 21 04:49:07 PM PDT 24
Finished Jun 21 04:49:22 PM PDT 24
Peak memory 211172 kb
Host smart-4ed45f24-6717-4935-b83f-07d42ae2dfcd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982868043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3982868043
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1575080391
Short name T95
Test name
Test status
Simulation time 2272329815 ps
CPU time 27.92 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:38 PM PDT 24
Peak memory 211504 kb
Host smart-804129b7-4716-4989-aeb7-6f5d17cf8169
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575080391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1575080391
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3647845881
Short name T112
Test name
Test status
Simulation time 476412673 ps
CPU time 8.91 seconds
Started Jun 21 04:49:11 PM PDT 24
Finished Jun 21 04:49:22 PM PDT 24
Peak memory 219444 kb
Host smart-307751f6-1ba1-40ff-9fc5-3eb6c3cfadbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647845881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3647845881
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2986154727
Short name T444
Test name
Test status
Simulation time 333956320 ps
CPU time 6.3 seconds
Started Jun 21 04:49:11 PM PDT 24
Finished Jun 21 04:49:19 PM PDT 24
Peak memory 219412 kb
Host smart-7d306295-bdd2-498a-a0d2-a2341cb6eb99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986154727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2986154727
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1399495491
Short name T126
Test name
Test status
Simulation time 305007246 ps
CPU time 36.2 seconds
Started Jun 21 04:49:10 PM PDT 24
Finished Jun 21 04:49:49 PM PDT 24
Peak memory 212888 kb
Host smart-045b3db5-0072-4e88-beb2-f8040624eea0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399495491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1399495491
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.455910666
Short name T422
Test name
Test status
Simulation time 86519703 ps
CPU time 4.31 seconds
Started Jun 21 04:49:20 PM PDT 24
Finished Jun 21 04:49:27 PM PDT 24
Peak memory 211332 kb
Host smart-b1ee3dcd-b100-4b88-8ad5-c552a1b9d9aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455910666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.455910666
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.254813479
Short name T374
Test name
Test status
Simulation time 1114958330 ps
CPU time 7.69 seconds
Started Jun 21 04:49:21 PM PDT 24
Finished Jun 21 04:49:32 PM PDT 24
Peak memory 218272 kb
Host smart-d4b9a9e4-c483-4acb-bbe1-a9acd983caca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254813479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.254813479
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.962841380
Short name T391
Test name
Test status
Simulation time 7308376732 ps
CPU time 16.06 seconds
Started Jun 21 04:49:20 PM PDT 24
Finished Jun 21 04:49:38 PM PDT 24
Peak memory 211464 kb
Host smart-13db6fb0-8fa4-4f8c-8cab-4a418212d855
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962841380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.962841380
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.524725288
Short name T387
Test name
Test status
Simulation time 3230913805 ps
CPU time 9.93 seconds
Started Jun 21 04:49:18 PM PDT 24
Finished Jun 21 04:49:30 PM PDT 24
Peak memory 215644 kb
Host smart-89a6e840-312e-47c0-a509-aa42857ea80e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524725288 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.524725288
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2627360540
Short name T93
Test name
Test status
Simulation time 889444880 ps
CPU time 5.74 seconds
Started Jun 21 04:49:20 PM PDT 24
Finished Jun 21 04:49:28 PM PDT 24
Peak memory 218112 kb
Host smart-d05f2be1-769c-408f-ae46-12549d6b07c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627360540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2627360540
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4043803667
Short name T390
Test name
Test status
Simulation time 4642641127 ps
CPU time 10.49 seconds
Started Jun 21 04:49:21 PM PDT 24
Finished Jun 21 04:49:35 PM PDT 24
Peak memory 211228 kb
Host smart-c6948f85-86ee-4d35-89d3-1a2044664a50
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043803667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4043803667
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2072113066
Short name T449
Test name
Test status
Simulation time 1235758095 ps
CPU time 11.37 seconds
Started Jun 21 04:49:17 PM PDT 24
Finished Jun 21 04:49:30 PM PDT 24
Peak memory 211176 kb
Host smart-03b3eb94-876e-489b-a2cb-91dc726da5c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072113066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2072113066
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.579390936
Short name T418
Test name
Test status
Simulation time 91084064 ps
CPU time 4.37 seconds
Started Jun 21 04:49:18 PM PDT 24
Finished Jun 21 04:49:25 PM PDT 24
Peak memory 218892 kb
Host smart-1242a1ff-d9f7-4c05-b5c3-65eff774e820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579390936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.579390936
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3339227739
Short name T425
Test name
Test status
Simulation time 411040569 ps
CPU time 7.58 seconds
Started Jun 21 04:49:08 PM PDT 24
Finished Jun 21 04:49:16 PM PDT 24
Peak memory 219492 kb
Host smart-d7135d3e-0173-4663-9255-2ff128392305
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339227739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3339227739
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2341971248
Short name T379
Test name
Test status
Simulation time 628074498 ps
CPU time 8.75 seconds
Started Jun 21 04:49:18 PM PDT 24
Finished Jun 21 04:49:29 PM PDT 24
Peak memory 216916 kb
Host smart-d056569a-2226-4fb8-a901-15b05c03acaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341971248 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2341971248
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1792802033
Short name T378
Test name
Test status
Simulation time 14653742494 ps
CPU time 11.25 seconds
Started Jun 21 04:49:20 PM PDT 24
Finished Jun 21 04:49:34 PM PDT 24
Peak memory 219560 kb
Host smart-e509df79-22e2-453e-983b-14c55b584031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792802033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1792802033
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2705254742
Short name T76
Test name
Test status
Simulation time 724366581 ps
CPU time 19.27 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:48 PM PDT 24
Peak memory 211428 kb
Host smart-f7265e22-8f07-495a-ac34-b88663dc1c40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705254742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2705254742
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3830894104
Short name T429
Test name
Test status
Simulation time 5120607386 ps
CPU time 6.97 seconds
Started Jun 21 04:49:28 PM PDT 24
Finished Jun 21 04:49:45 PM PDT 24
Peak memory 211352 kb
Host smart-df29eb0c-a55c-471a-81fb-20eb64bc72b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830894104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3830894104
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4081836881
Short name T372
Test name
Test status
Simulation time 190579020 ps
CPU time 5.76 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:32 PM PDT 24
Peak memory 219432 kb
Host smart-d4197fea-a4b5-4413-b246-7599861dd2ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081836881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4081836881
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2635616113
Short name T123
Test name
Test status
Simulation time 425358088 ps
CPU time 69.51 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:50:38 PM PDT 24
Peak memory 212904 kb
Host smart-e9d082b2-0b90-4b0e-8ecb-af0554096fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635616113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2635616113
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1315779294
Short name T65
Test name
Test status
Simulation time 1009204064 ps
CPU time 10.87 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:40 PM PDT 24
Peak memory 219488 kb
Host smart-c5f81576-9181-4239-94c9-0e6d18233c47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315779294 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1315779294
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3669783495
Short name T402
Test name
Test status
Simulation time 145545316 ps
CPU time 4.07 seconds
Started Jun 21 04:49:22 PM PDT 24
Finished Jun 21 04:49:30 PM PDT 24
Peak memory 211304 kb
Host smart-c39faec7-36b4-413b-b7ea-ec216d724784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669783495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3669783495
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.156419436
Short name T99
Test name
Test status
Simulation time 543265005 ps
CPU time 21.1 seconds
Started Jun 21 04:49:19 PM PDT 24
Finished Jun 21 04:49:42 PM PDT 24
Peak memory 211312 kb
Host smart-30eea833-9a75-4ab9-ab47-360ab75fbe24
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156419436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.156419436
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2554313014
Short name T403
Test name
Test status
Simulation time 1498270359 ps
CPU time 12.6 seconds
Started Jun 21 04:49:22 PM PDT 24
Finished Jun 21 04:49:38 PM PDT 24
Peak memory 219520 kb
Host smart-708d133c-2114-4890-ad68-36384628c99f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554313014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2554313014
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1187036863
Short name T399
Test name
Test status
Simulation time 1024404232 ps
CPU time 14.63 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:49:56 PM PDT 24
Peak memory 216156 kb
Host smart-5526c31f-f44c-4eea-8b24-d3c999bfc681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187036863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1187036863
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3694821368
Short name T64
Test name
Test status
Simulation time 303774507 ps
CPU time 67.53 seconds
Started Jun 21 04:49:21 PM PDT 24
Finished Jun 21 04:50:32 PM PDT 24
Peak memory 219448 kb
Host smart-921a10ca-4300-44e2-acff-87d5718d88bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694821368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3694821368
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.568718713
Short name T404
Test name
Test status
Simulation time 1665771894 ps
CPU time 13.94 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:41 PM PDT 24
Peak memory 219492 kb
Host smart-21ef90ec-c40b-484c-9c85-2ba466f547bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568718713 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.568718713
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3499089769
Short name T77
Test name
Test status
Simulation time 1809634211 ps
CPU time 14.46 seconds
Started Jun 21 04:49:27 PM PDT 24
Finished Jun 21 04:49:51 PM PDT 24
Peak memory 218956 kb
Host smart-7597d46f-94e8-4e8c-bb9a-30f0d3b27551
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499089769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3499089769
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.208746660
Short name T393
Test name
Test status
Simulation time 378931876 ps
CPU time 18.9 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:48 PM PDT 24
Peak memory 211340 kb
Host smart-c2c0175a-f9f9-4870-a97c-afa82b04d74a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208746660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.208746660
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1921121660
Short name T113
Test name
Test status
Simulation time 2722276804 ps
CPU time 7.55 seconds
Started Jun 21 04:49:30 PM PDT 24
Finished Jun 21 04:49:49 PM PDT 24
Peak memory 219040 kb
Host smart-b0b30a5f-0ee6-40a6-a949-96689ce4ee1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921121660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1921121660
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.475725395
Short name T421
Test name
Test status
Simulation time 346791556 ps
CPU time 6.49 seconds
Started Jun 21 04:49:21 PM PDT 24
Finished Jun 21 04:49:30 PM PDT 24
Peak memory 219520 kb
Host smart-88c2a196-297f-459d-872f-1250827affbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475725395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.475725395
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2949047370
Short name T62
Test name
Test status
Simulation time 3053409597 ps
CPU time 74.39 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:50:41 PM PDT 24
Peak memory 219552 kb
Host smart-c2173d60-5278-46a4-9b76-4cdfc4bf52fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949047370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2949047370
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4111238924
Short name T437
Test name
Test status
Simulation time 766571807 ps
CPU time 9.26 seconds
Started Jun 21 04:49:20 PM PDT 24
Finished Jun 21 04:49:32 PM PDT 24
Peak memory 219560 kb
Host smart-00a76bbf-b3db-4cdd-83d5-7cef41da9463
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111238924 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4111238924
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2629181526
Short name T427
Test name
Test status
Simulation time 1096393485 ps
CPU time 10.67 seconds
Started Jun 21 04:49:21 PM PDT 24
Finished Jun 21 04:49:35 PM PDT 24
Peak memory 211292 kb
Host smart-4f41a6ae-a5bc-4dd9-bdc1-4e0cbf251655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629181526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2629181526
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1253322995
Short name T447
Test name
Test status
Simulation time 5222642406 ps
CPU time 56.23 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:50:25 PM PDT 24
Peak memory 211384 kb
Host smart-1b313729-85a9-4c21-8947-032ba60d5b80
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253322995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1253322995
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2495314097
Short name T398
Test name
Test status
Simulation time 97802918 ps
CPU time 6.22 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:33 PM PDT 24
Peak memory 211420 kb
Host smart-47b5544b-7eef-4e4d-9aa3-7f2a4a796b98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495314097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2495314097
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2120647738
Short name T395
Test name
Test status
Simulation time 333573339 ps
CPU time 6.88 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:34 PM PDT 24
Peak memory 219388 kb
Host smart-efb4dc17-2309-4db1-9f08-a7a23d6484b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120647738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2120647738
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1176990192
Short name T119
Test name
Test status
Simulation time 791071802 ps
CPU time 70.51 seconds
Started Jun 21 04:49:22 PM PDT 24
Finished Jun 21 04:50:36 PM PDT 24
Peak memory 219500 kb
Host smart-8f49aa2f-ef3f-4709-b9b9-6401424b58fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176990192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1176990192
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1241256987
Short name T397
Test name
Test status
Simulation time 4812989543 ps
CPU time 11.43 seconds
Started Jun 21 04:49:21 PM PDT 24
Finished Jun 21 04:49:36 PM PDT 24
Peak memory 219656 kb
Host smart-5e84e6cf-b92b-478a-b8fc-0af5bbd230e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241256987 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1241256987
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2034996140
Short name T450
Test name
Test status
Simulation time 519427880 ps
CPU time 4.13 seconds
Started Jun 21 04:49:23 PM PDT 24
Finished Jun 21 04:49:30 PM PDT 24
Peak memory 211108 kb
Host smart-8357a6c3-270e-4837-964f-5cf9e55d8cf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034996140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2034996140
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.382062447
Short name T78
Test name
Test status
Simulation time 1835055243 ps
CPU time 30.53 seconds
Started Jun 21 04:49:24 PM PDT 24
Finished Jun 21 04:49:59 PM PDT 24
Peak memory 211408 kb
Host smart-424de38f-fea1-4467-9162-eb584efe622f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382062447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.382062447
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2195239277
Short name T430
Test name
Test status
Simulation time 1802898741 ps
CPU time 7.02 seconds
Started Jun 21 04:49:25 PM PDT 24
Finished Jun 21 04:49:38 PM PDT 24
Peak memory 211288 kb
Host smart-18ac2dce-b821-4f0a-b253-9a552223938b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195239277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2195239277
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3757145955
Short name T367
Test name
Test status
Simulation time 195409416 ps
CPU time 6.02 seconds
Started Jun 21 04:49:20 PM PDT 24
Finished Jun 21 04:49:28 PM PDT 24
Peak memory 219404 kb
Host smart-72f68c6f-5395-47fd-a2e1-3226fa1b3778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757145955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3757145955
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3999960281
Short name T128
Test name
Test status
Simulation time 2419051865 ps
CPU time 41.89 seconds
Started Jun 21 04:49:21 PM PDT 24
Finished Jun 21 04:50:06 PM PDT 24
Peak memory 211456 kb
Host smart-2d2b2533-b909-4162-ac97-f6a56919dd3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999960281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3999960281
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2296152075
Short name T236
Test name
Test status
Simulation time 993928319 ps
CPU time 9.75 seconds
Started Jun 21 05:17:43 PM PDT 24
Finished Jun 21 05:17:53 PM PDT 24
Peak memory 211056 kb
Host smart-fb054104-b900-4b04-99c5-0a5fd5063561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296152075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2296152075
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1968236641
Short name T53
Test name
Test status
Simulation time 65432495861 ps
CPU time 201.79 seconds
Started Jun 21 05:17:44 PM PDT 24
Finished Jun 21 05:21:06 PM PDT 24
Peak memory 233452 kb
Host smart-bb8b2fd3-56be-4783-9c64-775a6cc6c080
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968236641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1968236641
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.377409312
Short name T308
Test name
Test status
Simulation time 9389069553 ps
CPU time 32.2 seconds
Started Jun 21 05:17:39 PM PDT 24
Finished Jun 21 05:18:12 PM PDT 24
Peak memory 212040 kb
Host smart-497423b4-718d-4c0e-9a50-64ba9677bf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377409312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.377409312
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3881415167
Short name T144
Test name
Test status
Simulation time 3244652200 ps
CPU time 14.25 seconds
Started Jun 21 05:17:43 PM PDT 24
Finished Jun 21 05:17:58 PM PDT 24
Peak memory 211184 kb
Host smart-5d5cb2b3-3ad3-44ed-9807-a108a2d5b6c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881415167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3881415167
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2688203153
Short name T339
Test name
Test status
Simulation time 476472480 ps
CPU time 10.37 seconds
Started Jun 21 05:17:40 PM PDT 24
Finished Jun 21 05:17:52 PM PDT 24
Peak memory 213496 kb
Host smart-b1b5598c-0b20-46cd-8f32-d5101ea6d3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688203153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2688203153
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.938201041
Short name T33
Test name
Test status
Simulation time 6495368471 ps
CPU time 68.35 seconds
Started Jun 21 05:17:41 PM PDT 24
Finished Jun 21 05:18:51 PM PDT 24
Peak memory 216884 kb
Host smart-be9a5248-7157-43e7-88e0-a1ac849059fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938201041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.938201041
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2362268603
Short name T359
Test name
Test status
Simulation time 2002962791 ps
CPU time 17.13 seconds
Started Jun 21 05:17:49 PM PDT 24
Finished Jun 21 05:18:07 PM PDT 24
Peak memory 211056 kb
Host smart-897b3dcf-a274-47fd-939e-b3b21c3784dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362268603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2362268603
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3177112158
Short name T344
Test name
Test status
Simulation time 5650364687 ps
CPU time 188.53 seconds
Started Jun 21 05:17:50 PM PDT 24
Finished Jun 21 05:20:59 PM PDT 24
Peak memory 237848 kb
Host smart-48269709-cd0b-4156-842f-754fce838091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177112158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3177112158
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1187407535
Short name T180
Test name
Test status
Simulation time 2547114158 ps
CPU time 13.61 seconds
Started Jun 21 05:17:41 PM PDT 24
Finished Jun 21 05:17:55 PM PDT 24
Peak memory 211284 kb
Host smart-b5388586-9a1e-4dda-982f-ea9df2327c5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1187407535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1187407535
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2930043196
Short name T25
Test name
Test status
Simulation time 2023581144 ps
CPU time 104.56 seconds
Started Jun 21 05:17:49 PM PDT 24
Finished Jun 21 05:19:34 PM PDT 24
Peak memory 233620 kb
Host smart-6df1f701-00c5-4d0a-97ec-80bc71d78215
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930043196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2930043196
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4109146041
Short name T266
Test name
Test status
Simulation time 16687594608 ps
CPU time 38.71 seconds
Started Jun 21 05:17:42 PM PDT 24
Finished Jun 21 05:18:22 PM PDT 24
Peak memory 214004 kb
Host smart-367ace4c-f107-4170-8d1d-17f3c530267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109146041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4109146041
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1600135094
Short name T307
Test name
Test status
Simulation time 7487259077 ps
CPU time 69.93 seconds
Started Jun 21 05:17:43 PM PDT 24
Finished Jun 21 05:18:53 PM PDT 24
Peak memory 216896 kb
Host smart-63ddc2c2-0873-4841-b165-1c371cb71087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600135094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1600135094
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2413473001
Short name T27
Test name
Test status
Simulation time 2184203132 ps
CPU time 17.44 seconds
Started Jun 21 05:18:16 PM PDT 24
Finished Jun 21 05:18:34 PM PDT 24
Peak memory 211120 kb
Host smart-1316e1e7-0408-4e41-84e9-af3ea8449c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413473001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2413473001
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4045230295
Short name T106
Test name
Test status
Simulation time 111256246990 ps
CPU time 222.44 seconds
Started Jun 21 05:18:20 PM PDT 24
Finished Jun 21 05:22:04 PM PDT 24
Peak memory 212524 kb
Host smart-3528aa0b-0998-4d0c-81fb-7ad657f6acb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045230295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4045230295
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.221361436
Short name T347
Test name
Test status
Simulation time 10555429404 ps
CPU time 25.51 seconds
Started Jun 21 05:18:20 PM PDT 24
Finished Jun 21 05:18:46 PM PDT 24
Peak memory 212192 kb
Host smart-5b956d7d-1350-4005-a957-46027a2174de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221361436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.221361436
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2603669379
Short name T214
Test name
Test status
Simulation time 577087683 ps
CPU time 9.48 seconds
Started Jun 21 05:18:14 PM PDT 24
Finished Jun 21 05:18:25 PM PDT 24
Peak memory 211212 kb
Host smart-c10606f0-118b-46ff-9b54-0050ab7e8408
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2603669379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2603669379
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2492595661
Short name T132
Test name
Test status
Simulation time 3200367291 ps
CPU time 28.45 seconds
Started Jun 21 05:18:14 PM PDT 24
Finished Jun 21 05:18:44 PM PDT 24
Peak memory 213544 kb
Host smart-43da9875-8a1c-494a-a0bd-43ac1450c410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492595661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2492595661
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2446960288
Short name T137
Test name
Test status
Simulation time 2139398445 ps
CPU time 25.92 seconds
Started Jun 21 05:18:15 PM PDT 24
Finished Jun 21 05:18:42 PM PDT 24
Peak memory 215232 kb
Host smart-28efbb18-c267-44f0-9ffa-cdcfdcdc8300
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446960288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2446960288
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3403304421
Short name T274
Test name
Test status
Simulation time 1376766729 ps
CPU time 6.54 seconds
Started Jun 21 05:18:21 PM PDT 24
Finished Jun 21 05:18:28 PM PDT 24
Peak memory 211056 kb
Host smart-2708da9b-983c-434d-ba59-83a018ab895e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403304421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3403304421
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1741842146
Short name T244
Test name
Test status
Simulation time 1224996532 ps
CPU time 13.06 seconds
Started Jun 21 05:18:23 PM PDT 24
Finished Jun 21 05:18:37 PM PDT 24
Peak memory 211160 kb
Host smart-a1c2f282-5035-4cdf-b326-b5362ebe4d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741842146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1741842146
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.851804289
Short name T217
Test name
Test status
Simulation time 2164570899 ps
CPU time 25.88 seconds
Started Jun 21 05:18:14 PM PDT 24
Finished Jun 21 05:18:41 PM PDT 24
Peak memory 213844 kb
Host smart-694bf7d3-611d-4d12-a7e3-c2a6e0299cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851804289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.851804289
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.105313406
Short name T160
Test name
Test status
Simulation time 23796638581 ps
CPU time 17.62 seconds
Started Jun 21 05:18:21 PM PDT 24
Finished Jun 21 05:18:40 PM PDT 24
Peak memory 212268 kb
Host smart-0648f221-12eb-40df-b2e7-2d1fb3014a14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105313406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.105313406
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2594413102
Short name T61
Test name
Test status
Simulation time 96260515354 ps
CPU time 8391.45 seconds
Started Jun 21 05:18:20 PM PDT 24
Finished Jun 21 07:38:14 PM PDT 24
Peak memory 235768 kb
Host smart-e227c420-4397-4bad-a383-1fdf8ef763d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594413102 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2594413102
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3003106241
Short name T146
Test name
Test status
Simulation time 15284481152 ps
CPU time 16.51 seconds
Started Jun 21 05:18:21 PM PDT 24
Finished Jun 21 05:18:39 PM PDT 24
Peak memory 211120 kb
Host smart-09024d6c-18f3-41bd-903e-96df94ab709c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003106241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3003106241
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2876452687
Short name T195
Test name
Test status
Simulation time 30742948972 ps
CPU time 145.77 seconds
Started Jun 21 05:18:22 PM PDT 24
Finished Jun 21 05:20:48 PM PDT 24
Peak memory 212528 kb
Host smart-f4cd1123-66f0-433c-b702-a24eac03a05c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876452687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2876452687
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.168296369
Short name T166
Test name
Test status
Simulation time 1039330808 ps
CPU time 14.86 seconds
Started Jun 21 05:18:22 PM PDT 24
Finished Jun 21 05:18:37 PM PDT 24
Peak memory 211680 kb
Host smart-237129ee-16e5-45a2-aa30-6ac286fbe6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168296369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.168296369
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.747693091
Short name T155
Test name
Test status
Simulation time 1538063590 ps
CPU time 14.16 seconds
Started Jun 21 05:18:20 PM PDT 24
Finished Jun 21 05:18:35 PM PDT 24
Peak memory 211156 kb
Host smart-49a699c1-79d0-4cca-a750-d15c6856c867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747693091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.747693091
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.289675932
Short name T252
Test name
Test status
Simulation time 31232220058 ps
CPU time 31.42 seconds
Started Jun 21 05:18:25 PM PDT 24
Finished Jun 21 05:18:57 PM PDT 24
Peak memory 213752 kb
Host smart-54bae269-1624-4302-b0c9-c0a476b000e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289675932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.289675932
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3357782792
Short name T270
Test name
Test status
Simulation time 5836502633 ps
CPU time 62.77 seconds
Started Jun 21 05:18:25 PM PDT 24
Finished Jun 21 05:19:28 PM PDT 24
Peak memory 216468 kb
Host smart-ece53eb8-e5b4-4351-a54c-f313126d34d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357782792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3357782792
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2826808663
Short name T57
Test name
Test status
Simulation time 96251665830 ps
CPU time 2462.26 seconds
Started Jun 21 05:18:23 PM PDT 24
Finished Jun 21 05:59:27 PM PDT 24
Peak memory 239996 kb
Host smart-162a42e3-3113-4b97-ac75-55a9c46866cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826808663 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2826808663
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1134796531
Short name T8
Test name
Test status
Simulation time 2063588935 ps
CPU time 10.72 seconds
Started Jun 21 05:18:27 PM PDT 24
Finished Jun 21 05:18:38 PM PDT 24
Peak memory 211064 kb
Host smart-b2a9863a-91e2-4ad5-a5e6-36c505d3280a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134796531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1134796531
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.65505443
Short name T305
Test name
Test status
Simulation time 25995253662 ps
CPU time 198.6 seconds
Started Jun 21 05:18:28 PM PDT 24
Finished Jun 21 05:21:48 PM PDT 24
Peak memory 237580 kb
Host smart-cdcc8b78-5287-4dcb-9d30-b9e6b292e6b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65505443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_co
rrupt_sig_fatal_chk.65505443
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.791200522
Short name T228
Test name
Test status
Simulation time 13695891634 ps
CPU time 32.12 seconds
Started Jun 21 05:18:28 PM PDT 24
Finished Jun 21 05:19:01 PM PDT 24
Peak memory 212148 kb
Host smart-1c3db765-a1c0-4c51-9eb1-093791cc77e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791200522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.791200522
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2190062983
Short name T2
Test name
Test status
Simulation time 2108363682 ps
CPU time 17.78 seconds
Started Jun 21 05:18:28 PM PDT 24
Finished Jun 21 05:18:47 PM PDT 24
Peak memory 211212 kb
Host smart-1f7fd633-91a2-444e-9fc9-62addfcfa840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190062983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2190062983
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2770642769
Short name T284
Test name
Test status
Simulation time 188573783 ps
CPU time 10.4 seconds
Started Jun 21 05:18:20 PM PDT 24
Finished Jun 21 05:18:31 PM PDT 24
Peak memory 213008 kb
Host smart-0f1410bd-0d54-4703-b4e2-3c5ae2df0558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770642769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2770642769
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.99924671
Short name T349
Test name
Test status
Simulation time 11007817964 ps
CPU time 55.67 seconds
Started Jun 21 05:18:30 PM PDT 24
Finished Jun 21 05:19:26 PM PDT 24
Peak memory 217732 kb
Host smart-ee6860ac-bead-426a-9826-e5477ba411e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99924671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.rom_ctrl_stress_all.99924671
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2339201502
Short name T177
Test name
Test status
Simulation time 86364479 ps
CPU time 4.27 seconds
Started Jun 21 05:18:38 PM PDT 24
Finished Jun 21 05:18:43 PM PDT 24
Peak memory 211076 kb
Host smart-b6ddb22a-7534-4cc3-9ac9-a2aae5af3e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339201502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2339201502
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.651654931
Short name T260
Test name
Test status
Simulation time 12785393786 ps
CPU time 140.87 seconds
Started Jun 21 05:18:38 PM PDT 24
Finished Jun 21 05:20:59 PM PDT 24
Peak memory 236712 kb
Host smart-2c1f7075-03ef-40cc-9cb8-ce5cce541280
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651654931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.651654931
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3720291747
Short name T185
Test name
Test status
Simulation time 25230222116 ps
CPU time 32.11 seconds
Started Jun 21 05:18:35 PM PDT 24
Finished Jun 21 05:19:08 PM PDT 24
Peak memory 212184 kb
Host smart-8ee1cd6f-90e5-49fe-90b5-530a7d9c569f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720291747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3720291747
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2751860722
Short name T310
Test name
Test status
Simulation time 4730832797 ps
CPU time 12.66 seconds
Started Jun 21 05:18:38 PM PDT 24
Finished Jun 21 05:18:51 PM PDT 24
Peak memory 211276 kb
Host smart-6be34ccc-5d46-49b3-804c-0dd779b82dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751860722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2751860722
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2642587988
Short name T221
Test name
Test status
Simulation time 11253356943 ps
CPU time 29.23 seconds
Started Jun 21 05:18:29 PM PDT 24
Finished Jun 21 05:18:59 PM PDT 24
Peak memory 213852 kb
Host smart-9ed84bd8-b640-4730-96dd-10b05dd33f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642587988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2642587988
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.438552378
Short name T152
Test name
Test status
Simulation time 3145510767 ps
CPU time 22.26 seconds
Started Jun 21 05:18:28 PM PDT 24
Finished Jun 21 05:18:51 PM PDT 24
Peak memory 214192 kb
Host smart-c2d04093-6184-4f36-9f0c-a544fe804ea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438552378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.438552378
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.120522388
Short name T327
Test name
Test status
Simulation time 12524496793 ps
CPU time 14.37 seconds
Started Jun 21 05:18:35 PM PDT 24
Finished Jun 21 05:18:50 PM PDT 24
Peak memory 211120 kb
Host smart-b3287488-7086-4f26-97b1-a8ecd7f3fd85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120522388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.120522388
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.277452251
Short name T298
Test name
Test status
Simulation time 1590987199 ps
CPU time 119.98 seconds
Started Jun 21 05:18:40 PM PDT 24
Finished Jun 21 05:20:40 PM PDT 24
Peak memory 236412 kb
Host smart-abde286a-ffdc-4553-81b4-7c7d4cf9105e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277452251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.277452251
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3134557337
Short name T315
Test name
Test status
Simulation time 6842785320 ps
CPU time 20.13 seconds
Started Jun 21 05:18:35 PM PDT 24
Finished Jun 21 05:18:56 PM PDT 24
Peak memory 212332 kb
Host smart-c5b8ba56-eee6-48ef-9427-a747de09bdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134557337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3134557337
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3117762385
Short name T47
Test name
Test status
Simulation time 879932351 ps
CPU time 8.08 seconds
Started Jun 21 05:18:36 PM PDT 24
Finished Jun 21 05:18:46 PM PDT 24
Peak memory 211208 kb
Host smart-275a40bd-07f2-4264-b8f3-016c65d08fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117762385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3117762385
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3377343313
Short name T216
Test name
Test status
Simulation time 198225950 ps
CPU time 10.49 seconds
Started Jun 21 05:18:35 PM PDT 24
Finished Jun 21 05:18:46 PM PDT 24
Peak memory 213032 kb
Host smart-bd8781d8-7f75-482a-a990-d465a381b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377343313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3377343313
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1884332419
Short name T230
Test name
Test status
Simulation time 2196268461 ps
CPU time 17.44 seconds
Started Jun 21 05:18:36 PM PDT 24
Finished Jun 21 05:18:54 PM PDT 24
Peak memory 213708 kb
Host smart-b171d837-4879-48bd-92ef-12eee45ff41c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884332419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1884332419
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2350010020
Short name T107
Test name
Test status
Simulation time 3875797040 ps
CPU time 16.39 seconds
Started Jun 21 05:18:43 PM PDT 24
Finished Jun 21 05:19:01 PM PDT 24
Peak memory 211136 kb
Host smart-0fe51515-5b08-4b71-b294-8cd6681a4620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350010020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2350010020
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2126969606
Short name T52
Test name
Test status
Simulation time 123836069948 ps
CPU time 380.31 seconds
Started Jun 21 05:18:43 PM PDT 24
Finished Jun 21 05:25:05 PM PDT 24
Peak memory 212520 kb
Host smart-2562a805-b827-4ae5-bffd-1880603ebc3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126969606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2126969606
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.550104302
Short name T209
Test name
Test status
Simulation time 2072297467 ps
CPU time 9.69 seconds
Started Jun 21 05:18:44 PM PDT 24
Finished Jun 21 05:18:55 PM PDT 24
Peak memory 211716 kb
Host smart-2a9fadf5-02df-43e7-9256-2d4dedea14b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550104302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.550104302
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3159546358
Short name T312
Test name
Test status
Simulation time 100948923 ps
CPU time 5.38 seconds
Started Jun 21 05:18:43 PM PDT 24
Finished Jun 21 05:18:50 PM PDT 24
Peak memory 211264 kb
Host smart-beee82ef-80b6-4181-86ad-bcef1fd3ddb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159546358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3159546358
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2151868199
Short name T227
Test name
Test status
Simulation time 1043811365 ps
CPU time 15.55 seconds
Started Jun 21 05:18:43 PM PDT 24
Finished Jun 21 05:19:01 PM PDT 24
Peak memory 213576 kb
Host smart-2689e5ab-983a-4e12-afe6-757d6666e327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151868199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2151868199
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3509567178
Short name T288
Test name
Test status
Simulation time 3375309988 ps
CPU time 26.72 seconds
Started Jun 21 05:18:41 PM PDT 24
Finished Jun 21 05:19:09 PM PDT 24
Peak memory 213460 kb
Host smart-89b07c39-78b6-408b-90af-565d2ad43219
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509567178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3509567178
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.600904718
Short name T233
Test name
Test status
Simulation time 2561660812 ps
CPU time 13.66 seconds
Started Jun 21 05:18:41 PM PDT 24
Finished Jun 21 05:18:56 PM PDT 24
Peak memory 211128 kb
Host smart-6b95bc65-d04a-4f69-a0a3-c92195564a61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600904718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.600904718
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3336191977
Short name T186
Test name
Test status
Simulation time 9147170372 ps
CPU time 169.25 seconds
Started Jun 21 05:18:44 PM PDT 24
Finished Jun 21 05:21:35 PM PDT 24
Peak memory 237584 kb
Host smart-6566b751-5688-4378-a83b-4f4a57103b4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336191977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3336191977
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4180086643
Short name T320
Test name
Test status
Simulation time 5405562978 ps
CPU time 26.39 seconds
Started Jun 21 05:18:42 PM PDT 24
Finished Jun 21 05:19:10 PM PDT 24
Peak memory 212100 kb
Host smart-ca3184d6-4215-46bd-a22f-08feff6deab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180086643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4180086643
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.671704406
Short name T267
Test name
Test status
Simulation time 98374255 ps
CPU time 5.54 seconds
Started Jun 21 05:18:42 PM PDT 24
Finished Jun 21 05:18:49 PM PDT 24
Peak memory 211208 kb
Host smart-74d7eba6-66e6-43c9-a22d-3dcbcb513fea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671704406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.671704406
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2947066969
Short name T84
Test name
Test status
Simulation time 6744302494 ps
CPU time 19.05 seconds
Started Jun 21 05:18:46 PM PDT 24
Finished Jun 21 05:19:06 PM PDT 24
Peak memory 213488 kb
Host smart-547f50c2-a99f-4844-9972-d7c10e75ef14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947066969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2947066969
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3588674775
Short name T30
Test name
Test status
Simulation time 561969674 ps
CPU time 14.12 seconds
Started Jun 21 05:18:43 PM PDT 24
Finished Jun 21 05:18:59 PM PDT 24
Peak memory 213900 kb
Host smart-7b293c10-d665-4335-8e0b-d25111177cbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588674775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3588674775
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.820034168
Short name T59
Test name
Test status
Simulation time 6478863040 ps
CPU time 329.48 seconds
Started Jun 21 05:18:43 PM PDT 24
Finished Jun 21 05:24:14 PM PDT 24
Peak memory 227948 kb
Host smart-306106d0-08a1-4c13-a79f-c98da1498704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820034168 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.820034168
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1946143690
Short name T331
Test name
Test status
Simulation time 89313498 ps
CPU time 4.48 seconds
Started Jun 21 05:18:53 PM PDT 24
Finished Jun 21 05:18:59 PM PDT 24
Peak memory 211056 kb
Host smart-363b5de9-bf22-43d7-a8ad-2d6e5abc206b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946143690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1946143690
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2353182273
Short name T343
Test name
Test status
Simulation time 10678192621 ps
CPU time 181.18 seconds
Started Jun 21 05:18:43 PM PDT 24
Finished Jun 21 05:21:45 PM PDT 24
Peak memory 237580 kb
Host smart-64883e55-265f-4e13-9c8d-a57d9ac0e217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353182273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2353182273
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4285223799
Short name T162
Test name
Test status
Simulation time 1104991863 ps
CPU time 16.75 seconds
Started Jun 21 05:18:51 PM PDT 24
Finished Jun 21 05:19:09 PM PDT 24
Peak memory 211788 kb
Host smart-ef0da02b-c622-4593-8390-79cf05bb0315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285223799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4285223799
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1250974257
Short name T287
Test name
Test status
Simulation time 1384989959 ps
CPU time 13.11 seconds
Started Jun 21 05:18:42 PM PDT 24
Finished Jun 21 05:18:56 PM PDT 24
Peak memory 211212 kb
Host smart-6116fcf6-6ac4-493e-8c1b-8e72eff4035e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250974257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1250974257
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2569375350
Short name T322
Test name
Test status
Simulation time 2038636673 ps
CPU time 14.24 seconds
Started Jun 21 05:18:42 PM PDT 24
Finished Jun 21 05:18:58 PM PDT 24
Peak memory 213240 kb
Host smart-b2feeb2c-c66e-49ca-a472-2059df5e4101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569375350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2569375350
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3453169677
Short name T38
Test name
Test status
Simulation time 41547785035 ps
CPU time 396.08 seconds
Started Jun 21 05:18:58 PM PDT 24
Finished Jun 21 05:25:35 PM PDT 24
Peak memory 238552 kb
Host smart-7ddc6854-9a8d-4bd3-9614-310d2d26f5fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453169677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3453169677
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2469579270
Short name T289
Test name
Test status
Simulation time 2374320071 ps
CPU time 23.59 seconds
Started Jun 21 05:18:52 PM PDT 24
Finished Jun 21 05:19:17 PM PDT 24
Peak memory 211812 kb
Host smart-5965253b-b335-442d-b2b0-fc6d9c58b956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469579270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2469579270
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4234159439
Short name T280
Test name
Test status
Simulation time 1316546773 ps
CPU time 13.06 seconds
Started Jun 21 05:18:58 PM PDT 24
Finished Jun 21 05:19:12 PM PDT 24
Peak memory 211128 kb
Host smart-cb8d1a53-1041-4932-be16-84f3414b7b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234159439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4234159439
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.839284435
Short name T134
Test name
Test status
Simulation time 3135852384 ps
CPU time 29.15 seconds
Started Jun 21 05:18:52 PM PDT 24
Finished Jun 21 05:19:22 PM PDT 24
Peak memory 213184 kb
Host smart-88118a7b-1515-433c-aa16-a1d3e84b3e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839284435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.839284435
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1301496563
Short name T311
Test name
Test status
Simulation time 1074008541 ps
CPU time 21.72 seconds
Started Jun 21 05:18:52 PM PDT 24
Finished Jun 21 05:19:15 PM PDT 24
Peak memory 213416 kb
Host smart-1e13ff95-c710-417c-953d-080562447081
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301496563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1301496563
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1183058548
Short name T292
Test name
Test status
Simulation time 12322361604 ps
CPU time 14.14 seconds
Started Jun 21 05:17:49 PM PDT 24
Finished Jun 21 05:18:04 PM PDT 24
Peak memory 211076 kb
Host smart-f4060a17-c294-429e-95ec-c90d1e6376c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183058548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1183058548
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.581628913
Short name T264
Test name
Test status
Simulation time 54801078619 ps
CPU time 212.33 seconds
Started Jun 21 05:17:49 PM PDT 24
Finished Jun 21 05:21:22 PM PDT 24
Peak memory 233548 kb
Host smart-28d40e6d-47a2-4302-befb-7b62efa2e084
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581628913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.581628913
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.749104677
Short name T263
Test name
Test status
Simulation time 11631660364 ps
CPU time 23.27 seconds
Started Jun 21 05:17:49 PM PDT 24
Finished Jun 21 05:18:13 PM PDT 24
Peak memory 212340 kb
Host smart-49c271e2-7e08-4c94-91a3-ce5b4791655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749104677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.749104677
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2626013696
Short name T249
Test name
Test status
Simulation time 3302474356 ps
CPU time 10.46 seconds
Started Jun 21 05:17:49 PM PDT 24
Finished Jun 21 05:18:00 PM PDT 24
Peak memory 211296 kb
Host smart-a77385ee-d13e-42d1-9ecd-80d72013b10f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626013696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2626013696
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2700129568
Short name T18
Test name
Test status
Simulation time 2056461447 ps
CPU time 64.46 seconds
Started Jun 21 05:17:50 PM PDT 24
Finished Jun 21 05:18:55 PM PDT 24
Peak memory 236108 kb
Host smart-6bcfe89a-9e4c-40b1-9ff5-74491c9701be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700129568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2700129568
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1018964928
Short name T238
Test name
Test status
Simulation time 188577707 ps
CPU time 10.51 seconds
Started Jun 21 05:17:50 PM PDT 24
Finished Jun 21 05:18:01 PM PDT 24
Peak memory 212952 kb
Host smart-1f32510f-e76c-431e-8db0-f6316d9e9043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018964928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1018964928
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2248306936
Short name T306
Test name
Test status
Simulation time 3100391742 ps
CPU time 14.67 seconds
Started Jun 21 05:17:49 PM PDT 24
Finished Jun 21 05:18:05 PM PDT 24
Peak memory 212324 kb
Host smart-6056f37a-3fe2-4306-9c9f-d260f62e230b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248306936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2248306936
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3068277842
Short name T20
Test name
Test status
Simulation time 3879519515 ps
CPU time 13.76 seconds
Started Jun 21 05:18:50 PM PDT 24
Finished Jun 21 05:19:05 PM PDT 24
Peak memory 211128 kb
Host smart-b21a0fd5-1b90-43cd-8883-6d745f7a1007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068277842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3068277842
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2501224596
Short name T226
Test name
Test status
Simulation time 5342463108 ps
CPU time 150.69 seconds
Started Jun 21 05:18:51 PM PDT 24
Finished Jun 21 05:21:23 PM PDT 24
Peak memory 214568 kb
Host smart-cdd8baad-afb8-4a61-89af-a9fab01bf21c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501224596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2501224596
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2187106369
Short name T293
Test name
Test status
Simulation time 175427609 ps
CPU time 9.63 seconds
Started Jun 21 05:18:58 PM PDT 24
Finished Jun 21 05:19:09 PM PDT 24
Peak memory 211700 kb
Host smart-9b70344c-d68d-44b3-8a2a-6a71a13f727b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187106369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2187106369
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.596748660
Short name T219
Test name
Test status
Simulation time 543214876 ps
CPU time 6.52 seconds
Started Jun 21 05:18:50 PM PDT 24
Finished Jun 21 05:18:58 PM PDT 24
Peak memory 211212 kb
Host smart-a1bb5b92-6deb-45df-b35f-1a84c0aa3613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596748660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.596748660
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.160609714
Short name T239
Test name
Test status
Simulation time 8615411179 ps
CPU time 25.77 seconds
Started Jun 21 05:18:49 PM PDT 24
Finished Jun 21 05:19:16 PM PDT 24
Peak memory 212736 kb
Host smart-31193864-5a06-4566-ab30-f13d4bf61f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160609714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.160609714
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3422571345
Short name T259
Test name
Test status
Simulation time 4029438888 ps
CPU time 44.07 seconds
Started Jun 21 05:18:53 PM PDT 24
Finished Jun 21 05:19:38 PM PDT 24
Peak memory 216572 kb
Host smart-ae2343c1-caf9-412c-987b-334bd7c5ee7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422571345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3422571345
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2839760391
Short name T72
Test name
Test status
Simulation time 89029198 ps
CPU time 4.33 seconds
Started Jun 21 05:18:57 PM PDT 24
Finished Jun 21 05:19:02 PM PDT 24
Peak memory 211100 kb
Host smart-97352165-604a-4e74-9618-d8a40356e2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839760391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2839760391
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.302264921
Short name T41
Test name
Test status
Simulation time 62174765753 ps
CPU time 290.64 seconds
Started Jun 21 05:18:54 PM PDT 24
Finished Jun 21 05:23:46 PM PDT 24
Peak memory 237516 kb
Host smart-e682b905-d080-4e7a-b65f-f9ab584c2b46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302264921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.302264921
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4022028876
Short name T213
Test name
Test status
Simulation time 793212888 ps
CPU time 9.74 seconds
Started Jun 21 05:18:55 PM PDT 24
Finished Jun 21 05:19:06 PM PDT 24
Peak memory 211760 kb
Host smart-b5f915a7-2493-44b2-b750-4e263e1661e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022028876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4022028876
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2158190605
Short name T197
Test name
Test status
Simulation time 4657480717 ps
CPU time 11.98 seconds
Started Jun 21 05:18:55 PM PDT 24
Finished Jun 21 05:19:08 PM PDT 24
Peak memory 211152 kb
Host smart-b1a3d6d6-5374-4214-9f98-f22feeb452cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158190605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2158190605
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.103777858
Short name T35
Test name
Test status
Simulation time 2751926835 ps
CPU time 24.98 seconds
Started Jun 21 05:18:51 PM PDT 24
Finished Jun 21 05:19:17 PM PDT 24
Peak memory 213524 kb
Host smart-5f16dde5-6bb1-44a1-80c8-9f4ae2cc44bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103777858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.103777858
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.704081709
Short name T89
Test name
Test status
Simulation time 579146257 ps
CPU time 16.83 seconds
Started Jun 21 05:18:52 PM PDT 24
Finished Jun 21 05:19:10 PM PDT 24
Peak memory 215372 kb
Host smart-a12e9244-a299-47e4-a15d-d38b0959a596
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704081709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.704081709
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1399672274
Short name T60
Test name
Test status
Simulation time 77686223657 ps
CPU time 2958.84 seconds
Started Jun 21 05:18:53 PM PDT 24
Finished Jun 21 06:08:13 PM PDT 24
Peak memory 239940 kb
Host smart-dc22dd88-929d-4f39-ac3a-076d50c89312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399672274 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1399672274
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2162502158
Short name T352
Test name
Test status
Simulation time 257164354 ps
CPU time 5.1 seconds
Started Jun 21 05:18:57 PM PDT 24
Finished Jun 21 05:19:03 PM PDT 24
Peak memory 211076 kb
Host smart-1a9e37e5-6b85-4509-9ca7-526efec0930e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162502158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2162502158
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1314482547
Short name T36
Test name
Test status
Simulation time 137999694476 ps
CPU time 234.09 seconds
Started Jun 21 05:19:01 PM PDT 24
Finished Jun 21 05:22:56 PM PDT 24
Peak memory 236636 kb
Host smart-46911d91-f42e-426c-b784-ce3a1633b495
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314482547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1314482547
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1706229989
Short name T10
Test name
Test status
Simulation time 6090670221 ps
CPU time 28.47 seconds
Started Jun 21 05:18:58 PM PDT 24
Finished Jun 21 05:19:27 PM PDT 24
Peak memory 212412 kb
Host smart-4ce43aca-1ffa-4e45-99fa-25d5bb6eaf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706229989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1706229989
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.187681304
Short name T261
Test name
Test status
Simulation time 10888827615 ps
CPU time 15.49 seconds
Started Jun 21 05:18:57 PM PDT 24
Finished Jun 21 05:19:13 PM PDT 24
Peak memory 211276 kb
Host smart-41018eaa-1bdc-464a-90a3-47879565dedf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187681304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.187681304
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3660405515
Short name T358
Test name
Test status
Simulation time 7512425481 ps
CPU time 32.99 seconds
Started Jun 21 05:18:58 PM PDT 24
Finished Jun 21 05:19:32 PM PDT 24
Peak memory 213704 kb
Host smart-f3550014-c1e9-4116-b3cb-f0e226aa7a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660405515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3660405515
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3797944792
Short name T34
Test name
Test status
Simulation time 298849717 ps
CPU time 16.53 seconds
Started Jun 21 05:19:01 PM PDT 24
Finished Jun 21 05:19:18 PM PDT 24
Peak memory 214844 kb
Host smart-0949a502-d860-4ced-a832-bb2ab72d8fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797944792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3797944792
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1684659741
Short name T71
Test name
Test status
Simulation time 900550977 ps
CPU time 9.58 seconds
Started Jun 21 05:18:59 PM PDT 24
Finished Jun 21 05:19:09 PM PDT 24
Peak memory 211056 kb
Host smart-40197b46-7ae8-4763-9c6d-d7eda5f2297d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684659741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1684659741
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.877285600
Short name T279
Test name
Test status
Simulation time 125528765394 ps
CPU time 325.16 seconds
Started Jun 21 05:18:56 PM PDT 24
Finished Jun 21 05:24:22 PM PDT 24
Peak memory 236592 kb
Host smart-cfcd2e10-e3ee-4255-b6c2-6ace5e421a5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877285600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.877285600
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1750180269
Short name T142
Test name
Test status
Simulation time 2178523758 ps
CPU time 22.24 seconds
Started Jun 21 05:19:02 PM PDT 24
Finished Jun 21 05:19:25 PM PDT 24
Peak memory 212048 kb
Host smart-fa70a1e4-421a-401c-9b8d-a9c68e5a3026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750180269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1750180269
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2656537924
Short name T131
Test name
Test status
Simulation time 2644779885 ps
CPU time 12.92 seconds
Started Jun 21 05:19:01 PM PDT 24
Finished Jun 21 05:19:15 PM PDT 24
Peak memory 211284 kb
Host smart-8840fba7-dd1d-4b4c-85b2-5e306329271c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656537924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2656537924
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3952333871
Short name T254
Test name
Test status
Simulation time 716952901 ps
CPU time 10.01 seconds
Started Jun 21 05:19:01 PM PDT 24
Finished Jun 21 05:19:12 PM PDT 24
Peak memory 213976 kb
Host smart-2d6306ab-78ea-45f2-8fc1-b8a98dbc9e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952333871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3952333871
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2856865909
Short name T276
Test name
Test status
Simulation time 415266123 ps
CPU time 10.94 seconds
Started Jun 21 05:18:57 PM PDT 24
Finished Jun 21 05:19:08 PM PDT 24
Peak memory 213948 kb
Host smart-e3941a64-848c-4f38-b8c1-92e58f4d5b54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856865909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2856865909
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.779075666
Short name T272
Test name
Test status
Simulation time 431991586 ps
CPU time 6.04 seconds
Started Jun 21 05:19:05 PM PDT 24
Finished Jun 21 05:19:12 PM PDT 24
Peak memory 211012 kb
Host smart-8dfbb444-328e-45a6-8eaa-26ad8d1527e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779075666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.779075666
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.23856678
Short name T108
Test name
Test status
Simulation time 6295194077 ps
CPU time 136.82 seconds
Started Jun 21 05:19:04 PM PDT 24
Finished Jun 21 05:21:22 PM PDT 24
Peak memory 237584 kb
Host smart-7d3a083e-6e8b-492a-a1e1-73d07d4378e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23856678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_co
rrupt_sig_fatal_chk.23856678
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2581584460
Short name T242
Test name
Test status
Simulation time 831049706 ps
CPU time 9.9 seconds
Started Jun 21 05:19:05 PM PDT 24
Finished Jun 21 05:19:15 PM PDT 24
Peak memory 211792 kb
Host smart-8af18ea7-3019-41e1-b422-7fccad001dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581584460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2581584460
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2626132883
Short name T247
Test name
Test status
Simulation time 7867452052 ps
CPU time 16.05 seconds
Started Jun 21 05:19:03 PM PDT 24
Finished Jun 21 05:19:20 PM PDT 24
Peak memory 211284 kb
Host smart-675c7a9e-dd9c-4aa1-9eca-2346cdef0843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626132883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2626132883
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.697951446
Short name T31
Test name
Test status
Simulation time 4884761075 ps
CPU time 29.29 seconds
Started Jun 21 05:18:58 PM PDT 24
Finished Jun 21 05:19:29 PM PDT 24
Peak memory 213984 kb
Host smart-bb366623-c5af-465c-9b7d-7e4451a4ea29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697951446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.697951446
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2180498664
Short name T285
Test name
Test status
Simulation time 2791887427 ps
CPU time 14.1 seconds
Started Jun 21 05:19:06 PM PDT 24
Finished Jun 21 05:19:21 PM PDT 24
Peak memory 211104 kb
Host smart-b1b009f0-be6d-4cb4-8aed-16e24b2618d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180498664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2180498664
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2819009763
Short name T56
Test name
Test status
Simulation time 450750577744 ps
CPU time 4267.58 seconds
Started Jun 21 05:19:07 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 252276 kb
Host smart-d1e5accd-2d35-463a-928c-5e4957c228b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819009763 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2819009763
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3152809602
Short name T302
Test name
Test status
Simulation time 178819959 ps
CPU time 4.17 seconds
Started Jun 21 05:19:05 PM PDT 24
Finished Jun 21 05:19:10 PM PDT 24
Peak memory 211076 kb
Host smart-afeceb99-9a3a-40c6-a115-4987bd43f2eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152809602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3152809602
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2366943818
Short name T332
Test name
Test status
Simulation time 22363110777 ps
CPU time 222.75 seconds
Started Jun 21 05:19:07 PM PDT 24
Finished Jun 21 05:22:51 PM PDT 24
Peak memory 238556 kb
Host smart-9f31e776-5f85-4c1d-8f60-3b38eeac45be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366943818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2366943818
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.287853692
Short name T50
Test name
Test status
Simulation time 665764346 ps
CPU time 9.69 seconds
Started Jun 21 05:19:05 PM PDT 24
Finished Jun 21 05:19:16 PM PDT 24
Peak memory 211880 kb
Host smart-16ae32c9-35ae-4d66-8398-1e9630bd9c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287853692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.287853692
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2460860104
Short name T143
Test name
Test status
Simulation time 98124355 ps
CPU time 5.42 seconds
Started Jun 21 05:19:04 PM PDT 24
Finished Jun 21 05:19:10 PM PDT 24
Peak memory 211340 kb
Host smart-34f9feab-4d91-4675-96ab-eb3024e0bd71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460860104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2460860104
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.671392149
Short name T218
Test name
Test status
Simulation time 3533449586 ps
CPU time 31.21 seconds
Started Jun 21 05:19:05 PM PDT 24
Finished Jun 21 05:19:38 PM PDT 24
Peak memory 213884 kb
Host smart-136f270e-c798-427d-88f2-d0c12747d6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671392149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.671392149
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3990482394
Short name T101
Test name
Test status
Simulation time 26648242324 ps
CPU time 25.12 seconds
Started Jun 21 05:19:05 PM PDT 24
Finished Jun 21 05:19:31 PM PDT 24
Peak memory 215460 kb
Host smart-536c4421-352d-4bcf-8cbd-d7871a46e6bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990482394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3990482394
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1316979984
Short name T291
Test name
Test status
Simulation time 4202634250 ps
CPU time 17.5 seconds
Started Jun 21 05:19:14 PM PDT 24
Finished Jun 21 05:19:32 PM PDT 24
Peak memory 211128 kb
Host smart-e4506725-4f4f-4f2b-ba9e-c284394e4a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316979984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1316979984
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1906079332
Short name T256
Test name
Test status
Simulation time 35400081980 ps
CPU time 469.66 seconds
Started Jun 21 05:19:06 PM PDT 24
Finished Jun 21 05:26:57 PM PDT 24
Peak memory 233532 kb
Host smart-9750772c-effd-44c6-a453-c16332345000
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906079332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1906079332
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.625654523
Short name T141
Test name
Test status
Simulation time 30408939493 ps
CPU time 30.22 seconds
Started Jun 21 05:19:16 PM PDT 24
Finished Jun 21 05:19:47 PM PDT 24
Peak memory 212020 kb
Host smart-9d816c3a-2a87-4a93-8476-7dd0cd8a140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625654523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.625654523
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2125055654
Short name T229
Test name
Test status
Simulation time 2501776885 ps
CPU time 9.56 seconds
Started Jun 21 05:19:07 PM PDT 24
Finished Jun 21 05:19:18 PM PDT 24
Peak memory 211272 kb
Host smart-ebef42da-a265-4da9-ace1-b70d6bf35216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125055654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2125055654
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.111949018
Short name T301
Test name
Test status
Simulation time 2874167185 ps
CPU time 12.64 seconds
Started Jun 21 05:19:06 PM PDT 24
Finished Jun 21 05:19:19 PM PDT 24
Peak memory 213500 kb
Host smart-28cbb44d-1104-488e-ab3b-072251485810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111949018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.111949018
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.593987024
Short name T275
Test name
Test status
Simulation time 13172274331 ps
CPU time 51.64 seconds
Started Jun 21 05:19:06 PM PDT 24
Finished Jun 21 05:19:59 PM PDT 24
Peak memory 215140 kb
Host smart-2bc3f3e0-2326-421e-ac36-b5ec6273305a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593987024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.593987024
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1969062230
Short name T138
Test name
Test status
Simulation time 1059526517 ps
CPU time 11.1 seconds
Started Jun 21 05:19:14 PM PDT 24
Finished Jun 21 05:19:26 PM PDT 24
Peak memory 211012 kb
Host smart-5d22d201-a6e8-4951-ba08-2d24145771ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969062230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1969062230
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1535447688
Short name T149
Test name
Test status
Simulation time 14887849453 ps
CPU time 34.29 seconds
Started Jun 21 05:19:13 PM PDT 24
Finished Jun 21 05:19:48 PM PDT 24
Peak memory 212164 kb
Host smart-be4fc4b0-2001-4f99-9bb0-d0162755b422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535447688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1535447688
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1057238698
Short name T286
Test name
Test status
Simulation time 98531877 ps
CPU time 5.83 seconds
Started Jun 21 05:19:12 PM PDT 24
Finished Jun 21 05:19:19 PM PDT 24
Peak memory 211212 kb
Host smart-84c218bf-284b-406a-8821-9b6ed408a003
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057238698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1057238698
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3081977818
Short name T45
Test name
Test status
Simulation time 3323643722 ps
CPU time 22.06 seconds
Started Jun 21 05:19:14 PM PDT 24
Finished Jun 21 05:19:36 PM PDT 24
Peak memory 213224 kb
Host smart-2c5c7fb8-6673-475b-8202-beff4cc75122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081977818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3081977818
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.966454509
Short name T271
Test name
Test status
Simulation time 17973805020 ps
CPU time 77.84 seconds
Started Jun 21 05:19:15 PM PDT 24
Finished Jun 21 05:20:34 PM PDT 24
Peak memory 219216 kb
Host smart-66ac3098-0481-4824-9286-adb61862354f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966454509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.966454509
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1015007837
Short name T295
Test name
Test status
Simulation time 2099523996 ps
CPU time 17.51 seconds
Started Jun 21 05:19:21 PM PDT 24
Finished Jun 21 05:19:39 PM PDT 24
Peak memory 211064 kb
Host smart-c8f1e4cc-1a0f-46ac-8887-4a286916643a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015007837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1015007837
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.815351116
Short name T336
Test name
Test status
Simulation time 30991559009 ps
CPU time 195.41 seconds
Started Jun 21 05:19:19 PM PDT 24
Finished Jun 21 05:22:36 PM PDT 24
Peak memory 212472 kb
Host smart-f1bfc865-7069-4f1a-9a34-24dc160061c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815351116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.815351116
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.218465556
Short name T232
Test name
Test status
Simulation time 5572437576 ps
CPU time 18.83 seconds
Started Jun 21 05:19:19 PM PDT 24
Finished Jun 21 05:19:39 PM PDT 24
Peak memory 212024 kb
Host smart-3506d776-9592-4685-a956-58e8b46d9eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218465556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.218465556
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.543852120
Short name T159
Test name
Test status
Simulation time 5439132758 ps
CPU time 12.51 seconds
Started Jun 21 05:19:20 PM PDT 24
Finished Jun 21 05:19:34 PM PDT 24
Peak memory 211276 kb
Host smart-935ee9e0-8a65-4826-9b35-7a379037fcd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543852120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.543852120
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2769604128
Short name T90
Test name
Test status
Simulation time 4840033778 ps
CPU time 35.53 seconds
Started Jun 21 05:19:16 PM PDT 24
Finished Jun 21 05:19:52 PM PDT 24
Peak memory 212808 kb
Host smart-0120341e-8c3f-4366-988f-d7d33181583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769604128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2769604128
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2092114213
Short name T83
Test name
Test status
Simulation time 4140489221 ps
CPU time 37.58 seconds
Started Jun 21 05:19:21 PM PDT 24
Finished Jun 21 05:19:59 PM PDT 24
Peak memory 213432 kb
Host smart-5de61da0-3ddf-43f8-96c3-2fb1709a38e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092114213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2092114213
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3810699693
Short name T171
Test name
Test status
Simulation time 4736508013 ps
CPU time 16.12 seconds
Started Jun 21 05:19:21 PM PDT 24
Finished Jun 21 05:19:38 PM PDT 24
Peak memory 211120 kb
Host smart-3ae748ee-f0af-410a-95af-4e3c1077875f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810699693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3810699693
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.695558824
Short name T37
Test name
Test status
Simulation time 83041647857 ps
CPU time 414.43 seconds
Started Jun 21 05:19:19 PM PDT 24
Finished Jun 21 05:26:14 PM PDT 24
Peak memory 239376 kb
Host smart-a209e108-66ea-485c-8428-76fa6ef53b88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695558824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.695558824
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.43216849
Short name T231
Test name
Test status
Simulation time 14258546142 ps
CPU time 30.28 seconds
Started Jun 21 05:19:22 PM PDT 24
Finished Jun 21 05:19:53 PM PDT 24
Peak memory 212056 kb
Host smart-8d88c407-a02c-4967-ae45-c7b3a74c16bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43216849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.43216849
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2534310578
Short name T330
Test name
Test status
Simulation time 2007497053 ps
CPU time 16.71 seconds
Started Jun 21 05:19:21 PM PDT 24
Finished Jun 21 05:19:38 PM PDT 24
Peak memory 211156 kb
Host smart-f612a94e-be8e-4b3e-99af-6553336488d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534310578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2534310578
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3361509650
Short name T248
Test name
Test status
Simulation time 2916087506 ps
CPU time 26.71 seconds
Started Jun 21 05:19:21 PM PDT 24
Finished Jun 21 05:19:48 PM PDT 24
Peak memory 213280 kb
Host smart-9938420c-7edd-44c6-b432-9fea80800fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361509650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3361509650
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2069400430
Short name T29
Test name
Test status
Simulation time 6195729804 ps
CPU time 58.6 seconds
Started Jun 21 05:19:20 PM PDT 24
Finished Jun 21 05:20:19 PM PDT 24
Peak memory 217584 kb
Host smart-332ef675-bb8f-4dc9-a8e9-0a73a0b07e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069400430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2069400430
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2069258457
Short name T225
Test name
Test status
Simulation time 2072695073 ps
CPU time 16.05 seconds
Started Jun 21 05:17:57 PM PDT 24
Finished Jun 21 05:18:13 PM PDT 24
Peak memory 211032 kb
Host smart-6273b30c-2eaa-422e-adb3-09133e04c360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069258457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2069258457
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4254076500
Short name T200
Test name
Test status
Simulation time 61636036411 ps
CPU time 267 seconds
Started Jun 21 05:17:59 PM PDT 24
Finished Jun 21 05:22:27 PM PDT 24
Peak memory 233656 kb
Host smart-f16a5eab-6a60-465f-97a6-c6b438e9012f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254076500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4254076500
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.370546937
Short name T348
Test name
Test status
Simulation time 4751635629 ps
CPU time 12.34 seconds
Started Jun 21 05:17:56 PM PDT 24
Finished Jun 21 05:18:09 PM PDT 24
Peak memory 212088 kb
Host smart-b02e64af-520f-458a-9031-3c5f394ebe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370546937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.370546937
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.875255868
Short name T193
Test name
Test status
Simulation time 6133956955 ps
CPU time 11.52 seconds
Started Jun 21 05:17:51 PM PDT 24
Finished Jun 21 05:18:03 PM PDT 24
Peak memory 211276 kb
Host smart-56420731-6cdd-4015-957d-3c7131a1f218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875255868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.875255868
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3205470782
Short name T26
Test name
Test status
Simulation time 2028891962 ps
CPU time 104.06 seconds
Started Jun 21 05:17:57 PM PDT 24
Finished Jun 21 05:19:41 PM PDT 24
Peak memory 235636 kb
Host smart-e4841dd9-2c6a-49ef-a766-fc47e84eee18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205470782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3205470782
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3804491679
Short name T304
Test name
Test status
Simulation time 6624100134 ps
CPU time 21.57 seconds
Started Jun 21 05:17:49 PM PDT 24
Finished Jun 21 05:18:11 PM PDT 24
Peak memory 214800 kb
Host smart-b40478dc-842c-4a01-a158-ca4a31e6f4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804491679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3804491679
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1445467120
Short name T87
Test name
Test status
Simulation time 393970080 ps
CPU time 22.98 seconds
Started Jun 21 05:17:48 PM PDT 24
Finished Jun 21 05:18:12 PM PDT 24
Peak memory 216656 kb
Host smart-4c676cc4-8df0-4c97-89e4-45ee338a8561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445467120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1445467120
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1487424854
Short name T58
Test name
Test status
Simulation time 439186199907 ps
CPU time 3881.34 seconds
Started Jun 21 05:17:59 PM PDT 24
Finished Jun 21 06:22:42 PM PDT 24
Peak memory 231920 kb
Host smart-940a27b6-1b38-45f8-a694-2b7aa5a68f14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487424854 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1487424854
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3270530133
Short name T303
Test name
Test status
Simulation time 6415044836 ps
CPU time 14.41 seconds
Started Jun 21 05:19:28 PM PDT 24
Finished Jun 21 05:19:44 PM PDT 24
Peak memory 211028 kb
Host smart-f14b273d-1e3b-4d2e-8a41-7a032decf986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270530133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3270530133
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2590291080
Short name T346
Test name
Test status
Simulation time 11382827898 ps
CPU time 170.63 seconds
Started Jun 21 05:19:29 PM PDT 24
Finished Jun 21 05:22:21 PM PDT 24
Peak memory 212532 kb
Host smart-8b212769-1ff5-406c-b9d4-b64cd7c776c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590291080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2590291080
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3262129866
Short name T176
Test name
Test status
Simulation time 2821558474 ps
CPU time 25.21 seconds
Started Jun 21 05:19:29 PM PDT 24
Finished Jun 21 05:19:56 PM PDT 24
Peak memory 211256 kb
Host smart-46921acd-dbf3-4503-bb03-adfe3fbfacd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262129866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3262129866
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1159202994
Short name T183
Test name
Test status
Simulation time 1695218287 ps
CPU time 15.03 seconds
Started Jun 21 05:19:28 PM PDT 24
Finished Jun 21 05:19:45 PM PDT 24
Peak memory 211240 kb
Host smart-8a3a1428-8a9e-44ba-9e5b-7e9f325c40c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159202994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1159202994
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.4294777034
Short name T220
Test name
Test status
Simulation time 4672037259 ps
CPU time 32.12 seconds
Started Jun 21 05:19:19 PM PDT 24
Finished Jun 21 05:19:53 PM PDT 24
Peak memory 213732 kb
Host smart-3eb476f2-2ecd-4018-8523-ad57c2dbfc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294777034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.4294777034
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1873660638
Short name T341
Test name
Test status
Simulation time 7273616887 ps
CPU time 37.21 seconds
Started Jun 21 05:19:28 PM PDT 24
Finished Jun 21 05:20:06 PM PDT 24
Peak memory 217404 kb
Host smart-e2e8dfd7-d700-4fb5-99fe-3662c05e6cb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873660638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1873660638
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2111717750
Short name T297
Test name
Test status
Simulation time 12259982360 ps
CPU time 16.04 seconds
Started Jun 21 05:19:30 PM PDT 24
Finished Jun 21 05:19:47 PM PDT 24
Peak memory 211076 kb
Host smart-23367d33-20f0-4127-9094-076e3d360380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111717750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2111717750
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1354554780
Short name T43
Test name
Test status
Simulation time 9907192671 ps
CPU time 98.21 seconds
Started Jun 21 05:19:29 PM PDT 24
Finished Jun 21 05:21:09 PM PDT 24
Peak memory 224344 kb
Host smart-0583bcb0-6f71-42ea-af7a-555519c6fa2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354554780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1354554780
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.246059929
Short name T210
Test name
Test status
Simulation time 4338941733 ps
CPU time 19.14 seconds
Started Jun 21 05:19:32 PM PDT 24
Finished Jun 21 05:19:52 PM PDT 24
Peak memory 212152 kb
Host smart-b1525147-9846-4626-af3c-3a4fb1d39a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246059929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.246059929
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1033687947
Short name T205
Test name
Test status
Simulation time 376436501 ps
CPU time 6.09 seconds
Started Jun 21 05:19:30 PM PDT 24
Finished Jun 21 05:19:38 PM PDT 24
Peak memory 211212 kb
Host smart-7a4613b2-2618-4f0d-b928-f8f1834005f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1033687947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1033687947
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1195912109
Short name T351
Test name
Test status
Simulation time 11375453607 ps
CPU time 30.54 seconds
Started Jun 21 05:19:29 PM PDT 24
Finished Jun 21 05:20:01 PM PDT 24
Peak memory 213876 kb
Host smart-e3201bb4-abb6-4ac8-a4f5-ce33613d49e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195912109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1195912109
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1795199447
Short name T354
Test name
Test status
Simulation time 1339954539 ps
CPU time 21.16 seconds
Started Jun 21 05:19:29 PM PDT 24
Finished Jun 21 05:19:51 PM PDT 24
Peak memory 216440 kb
Host smart-b09205ea-8e14-4926-9462-195374367c3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795199447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1795199447
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3341312037
Short name T139
Test name
Test status
Simulation time 1643715613 ps
CPU time 15.05 seconds
Started Jun 21 05:19:29 PM PDT 24
Finished Jun 21 05:19:45 PM PDT 24
Peak memory 211072 kb
Host smart-83225301-ce65-4837-a65b-273c29ed41ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341312037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3341312037
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.18072451
Short name T15
Test name
Test status
Simulation time 7879810798 ps
CPU time 136.52 seconds
Started Jun 21 05:19:31 PM PDT 24
Finished Jun 21 05:21:48 PM PDT 24
Peak memory 238056 kb
Host smart-82c0dfb7-d2b7-44d0-a1eb-f1e7fcacf757
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18072451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_co
rrupt_sig_fatal_chk.18072451
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.364896664
Short name T191
Test name
Test status
Simulation time 3933256144 ps
CPU time 22.33 seconds
Started Jun 21 05:19:31 PM PDT 24
Finished Jun 21 05:19:55 PM PDT 24
Peak memory 211720 kb
Host smart-2b7e8684-02b9-4b67-b1a0-6d295c7b9532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364896664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.364896664
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2824663310
Short name T154
Test name
Test status
Simulation time 2169473823 ps
CPU time 11.86 seconds
Started Jun 21 05:19:28 PM PDT 24
Finished Jun 21 05:19:41 PM PDT 24
Peak memory 211276 kb
Host smart-60a5fbcd-de89-46b4-a724-7d1d1441a762
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824663310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2824663310
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2657638332
Short name T196
Test name
Test status
Simulation time 5800561017 ps
CPU time 16.66 seconds
Started Jun 21 05:19:32 PM PDT 24
Finished Jun 21 05:19:50 PM PDT 24
Peak memory 214072 kb
Host smart-9d96954d-9104-4307-a940-b7fdef6422b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657638332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2657638332
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4197143899
Short name T181
Test name
Test status
Simulation time 816515093 ps
CPU time 12.14 seconds
Started Jun 21 05:19:30 PM PDT 24
Finished Jun 21 05:19:44 PM PDT 24
Peak memory 213840 kb
Host smart-a3caa3fb-1967-4b6f-b3e3-ec931c3975c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197143899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4197143899
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1115607366
Short name T294
Test name
Test status
Simulation time 3663546137 ps
CPU time 14.86 seconds
Started Jun 21 05:19:37 PM PDT 24
Finished Jun 21 05:19:53 PM PDT 24
Peak memory 211120 kb
Host smart-be762664-0717-41f2-af23-6a9b5203c257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115607366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1115607366
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1591325505
Short name T342
Test name
Test status
Simulation time 2368397513 ps
CPU time 24.41 seconds
Started Jun 21 05:19:37 PM PDT 24
Finished Jun 21 05:20:02 PM PDT 24
Peak memory 211820 kb
Host smart-6c5e6524-ba58-4a6a-bf55-4923d8b9d5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591325505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1591325505
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3824493080
Short name T46
Test name
Test status
Simulation time 1321313686 ps
CPU time 12.71 seconds
Started Jun 21 05:19:39 PM PDT 24
Finished Jun 21 05:19:53 PM PDT 24
Peak memory 211128 kb
Host smart-aa810d34-e51d-49d9-801e-bd199e1a7ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824493080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3824493080
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1507074815
Short name T350
Test name
Test status
Simulation time 6333732548 ps
CPU time 29.27 seconds
Started Jun 21 05:19:38 PM PDT 24
Finished Jun 21 05:20:09 PM PDT 24
Peak memory 214544 kb
Host smart-bd6b5a17-1c5c-44e8-a2fb-1912b696a5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507074815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1507074815
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2532512957
Short name T277
Test name
Test status
Simulation time 330318000 ps
CPU time 19.27 seconds
Started Jun 21 05:19:41 PM PDT 24
Finished Jun 21 05:20:01 PM PDT 24
Peak memory 214192 kb
Host smart-a5ba94c9-1278-44f3-a465-495b3183047a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532512957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2532512957
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.598042153
Short name T175
Test name
Test status
Simulation time 174054880 ps
CPU time 5.55 seconds
Started Jun 21 05:19:39 PM PDT 24
Finished Jun 21 05:19:46 PM PDT 24
Peak memory 210912 kb
Host smart-5c7323cc-9486-4965-aca7-79bbb6e53fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598042153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.598042153
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2563280822
Short name T28
Test name
Test status
Simulation time 148231670468 ps
CPU time 206.18 seconds
Started Jun 21 05:19:39 PM PDT 24
Finished Jun 21 05:23:06 PM PDT 24
Peak memory 237548 kb
Host smart-79a03737-2743-4041-a6c6-ee7b4be3373f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563280822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2563280822
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2494551978
Short name T245
Test name
Test status
Simulation time 13470801684 ps
CPU time 15.28 seconds
Started Jun 21 05:19:38 PM PDT 24
Finished Jun 21 05:19:54 PM PDT 24
Peak memory 211276 kb
Host smart-2a6dd400-3797-4d9b-8ca5-3873fa64030a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2494551978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2494551978
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2538980201
Short name T281
Test name
Test status
Simulation time 2986350995 ps
CPU time 13.61 seconds
Started Jun 21 05:19:38 PM PDT 24
Finished Jun 21 05:19:52 PM PDT 24
Peak memory 213288 kb
Host smart-8e5c1142-4cc3-435b-a7be-6d33cef14a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538980201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2538980201
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4170444615
Short name T129
Test name
Test status
Simulation time 22731322160 ps
CPU time 64.01 seconds
Started Jun 21 05:19:40 PM PDT 24
Finished Jun 21 05:20:45 PM PDT 24
Peak memory 219424 kb
Host smart-21a9d126-71b8-4b4e-b9eb-76bc8aa0214f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170444615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4170444615
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1653220412
Short name T21
Test name
Test status
Simulation time 792185485 ps
CPU time 9.11 seconds
Started Jun 21 05:19:41 PM PDT 24
Finished Jun 21 05:19:51 PM PDT 24
Peak memory 211060 kb
Host smart-dbf18e3d-d7ec-4895-bf35-789f957893a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653220412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1653220412
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1524394100
Short name T39
Test name
Test status
Simulation time 50119246594 ps
CPU time 258.74 seconds
Started Jun 21 05:19:38 PM PDT 24
Finished Jun 21 05:23:58 PM PDT 24
Peak memory 213620 kb
Host smart-d08b7f4b-d6f5-404d-b2d1-084a9ea69440
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524394100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1524394100
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3899887119
Short name T345
Test name
Test status
Simulation time 1458554602 ps
CPU time 19.15 seconds
Started Jun 21 05:19:38 PM PDT 24
Finished Jun 21 05:19:58 PM PDT 24
Peak memory 211140 kb
Host smart-29e5fe8c-6964-4188-bf85-09cc91de92a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899887119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3899887119
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1733240445
Short name T262
Test name
Test status
Simulation time 4426099079 ps
CPU time 9.56 seconds
Started Jun 21 05:19:39 PM PDT 24
Finished Jun 21 05:19:50 PM PDT 24
Peak memory 211216 kb
Host smart-14c1f910-a732-46aa-95e2-a7480cb64a82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733240445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1733240445
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2794944318
Short name T335
Test name
Test status
Simulation time 19208521541 ps
CPU time 33.59 seconds
Started Jun 21 05:19:40 PM PDT 24
Finished Jun 21 05:20:14 PM PDT 24
Peak memory 213952 kb
Host smart-8dec7557-c944-4c6a-8cdd-b5dab6695efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794944318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2794944318
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2659444519
Short name T273
Test name
Test status
Simulation time 873966701 ps
CPU time 23.96 seconds
Started Jun 21 05:19:38 PM PDT 24
Finished Jun 21 05:20:03 PM PDT 24
Peak memory 213892 kb
Host smart-865eab26-f33b-42a1-a51a-63852744ca64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659444519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2659444519
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3114564601
Short name T23
Test name
Test status
Simulation time 47984243040 ps
CPU time 1003.44 seconds
Started Jun 21 05:19:37 PM PDT 24
Finished Jun 21 05:36:22 PM PDT 24
Peak memory 232172 kb
Host smart-35b760e7-6eb5-4b69-a3f6-cca275236416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114564601 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3114564601
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3765045823
Short name T326
Test name
Test status
Simulation time 3037089460 ps
CPU time 8.89 seconds
Started Jun 21 05:19:56 PM PDT 24
Finished Jun 21 05:20:06 PM PDT 24
Peak memory 211132 kb
Host smart-25fbcb0a-c8ce-4d4e-88d2-08a662aec1f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765045823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3765045823
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3752935076
Short name T13
Test name
Test status
Simulation time 14479786428 ps
CPU time 132.72 seconds
Started Jun 21 05:19:39 PM PDT 24
Finished Jun 21 05:21:53 PM PDT 24
Peak memory 236276 kb
Host smart-7eebf3a8-1f50-41dd-9ce3-872d8a87efa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752935076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3752935076
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2124806772
Short name T338
Test name
Test status
Simulation time 3777116685 ps
CPU time 21.96 seconds
Started Jun 21 05:19:37 PM PDT 24
Finished Jun 21 05:19:59 PM PDT 24
Peak memory 211868 kb
Host smart-34465c76-d19d-4f8f-8f89-adc2bd38c8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124806772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2124806772
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.307447424
Short name T174
Test name
Test status
Simulation time 2695808641 ps
CPU time 12.91 seconds
Started Jun 21 05:19:38 PM PDT 24
Finished Jun 21 05:19:52 PM PDT 24
Peak memory 211292 kb
Host smart-df6a1795-f26a-411f-9aa0-43e842df17e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307447424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.307447424
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3478454545
Short name T187
Test name
Test status
Simulation time 7728660172 ps
CPU time 43.36 seconds
Started Jun 21 05:19:37 PM PDT 24
Finished Jun 21 05:20:21 PM PDT 24
Peak memory 214216 kb
Host smart-05487cd2-20b3-43e0-9345-ffe4711f838a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478454545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3478454545
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3623676140
Short name T136
Test name
Test status
Simulation time 3087844436 ps
CPU time 10.89 seconds
Started Jun 21 05:19:40 PM PDT 24
Finished Jun 21 05:19:52 PM PDT 24
Peak memory 211232 kb
Host smart-94c29015-5eb5-4a12-8448-a2db8561f8fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623676140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3623676140
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4277699046
Short name T334
Test name
Test status
Simulation time 346520106 ps
CPU time 4.36 seconds
Started Jun 21 05:19:48 PM PDT 24
Finished Jun 21 05:19:53 PM PDT 24
Peak memory 211004 kb
Host smart-43a0a643-a8c9-4f33-a772-4068373f563e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277699046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4277699046
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1686900923
Short name T246
Test name
Test status
Simulation time 1814136522 ps
CPU time 111.26 seconds
Started Jun 21 05:19:46 PM PDT 24
Finished Jun 21 05:21:38 PM PDT 24
Peak memory 237468 kb
Host smart-3c2034bd-0878-495c-8f4e-73f93ae40cfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686900923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1686900923
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1476031903
Short name T222
Test name
Test status
Simulation time 2509662296 ps
CPU time 24 seconds
Started Jun 21 05:19:45 PM PDT 24
Finished Jun 21 05:20:10 PM PDT 24
Peak memory 211904 kb
Host smart-b7743325-9afe-4b8c-9843-a6164a6d71d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476031903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1476031903
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.120523134
Short name T199
Test name
Test status
Simulation time 5327278686 ps
CPU time 12.57 seconds
Started Jun 21 05:19:55 PM PDT 24
Finished Jun 21 05:20:09 PM PDT 24
Peak memory 211288 kb
Host smart-6f51fe0b-4e86-4580-84fd-9ded0f737a67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=120523134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.120523134
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2957250100
Short name T167
Test name
Test status
Simulation time 13499180002 ps
CPU time 37.12 seconds
Started Jun 21 05:19:56 PM PDT 24
Finished Jun 21 05:20:34 PM PDT 24
Peak memory 214540 kb
Host smart-7641b4d2-2ad7-48bb-abc1-451d9ada2e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957250100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2957250100
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2546320959
Short name T172
Test name
Test status
Simulation time 378162572 ps
CPU time 17.15 seconds
Started Jun 21 05:19:45 PM PDT 24
Finished Jun 21 05:20:03 PM PDT 24
Peak memory 212064 kb
Host smart-20fd557f-da3e-4d54-a68e-c295963b18a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546320959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2546320959
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2355961468
Short name T250
Test name
Test status
Simulation time 2653409855 ps
CPU time 11.79 seconds
Started Jun 21 05:19:45 PM PDT 24
Finished Jun 21 05:19:57 PM PDT 24
Peak memory 211028 kb
Host smart-755ca4ee-d86e-4396-bbcc-c9530352cb4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355961468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2355961468
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1201167671
Short name T215
Test name
Test status
Simulation time 17919256705 ps
CPU time 197.98 seconds
Started Jun 21 05:19:47 PM PDT 24
Finished Jun 21 05:23:06 PM PDT 24
Peak memory 233532 kb
Host smart-570711d7-e205-4257-8c88-eac15d4d8e18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201167671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1201167671
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1914989468
Short name T316
Test name
Test status
Simulation time 17657314211 ps
CPU time 29.49 seconds
Started Jun 21 05:19:44 PM PDT 24
Finished Jun 21 05:20:14 PM PDT 24
Peak memory 212248 kb
Host smart-facefeb7-1f5d-4331-aebb-60099e4c342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914989468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1914989468
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.663569879
Short name T201
Test name
Test status
Simulation time 908446050 ps
CPU time 7.5 seconds
Started Jun 21 05:19:45 PM PDT 24
Finished Jun 21 05:19:53 PM PDT 24
Peak memory 211208 kb
Host smart-a55a0c85-8545-4a2a-9d60-7f8d1b9484d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663569879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.663569879
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4120693262
Short name T325
Test name
Test status
Simulation time 57731758164 ps
CPU time 27.23 seconds
Started Jun 21 05:19:55 PM PDT 24
Finished Jun 21 05:20:23 PM PDT 24
Peak memory 213912 kb
Host smart-340deb48-9170-4599-82cd-48cbff444e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120693262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4120693262
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4188646140
Short name T224
Test name
Test status
Simulation time 2982111358 ps
CPU time 18.56 seconds
Started Jun 21 05:19:55 PM PDT 24
Finished Jun 21 05:20:15 PM PDT 24
Peak memory 211108 kb
Host smart-177c76ec-0171-4aba-ae71-b14388266afd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188646140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4188646140
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4171514264
Short name T69
Test name
Test status
Simulation time 4264951460 ps
CPU time 11.06 seconds
Started Jun 21 05:19:48 PM PDT 24
Finished Jun 21 05:19:59 PM PDT 24
Peak memory 211068 kb
Host smart-398d319f-ac1b-4d76-a17b-4bb7bdf396da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171514264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4171514264
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3088362390
Short name T173
Test name
Test status
Simulation time 118246143389 ps
CPU time 338.88 seconds
Started Jun 21 05:19:55 PM PDT 24
Finished Jun 21 05:25:35 PM PDT 24
Peak memory 237616 kb
Host smart-53c7e435-c1d2-48b2-9dbf-f2baeda71847
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088362390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3088362390
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1202728765
Short name T192
Test name
Test status
Simulation time 15009498707 ps
CPU time 35.87 seconds
Started Jun 21 05:19:45 PM PDT 24
Finished Jun 21 05:20:22 PM PDT 24
Peak memory 212040 kb
Host smart-d74454fc-96ed-483b-8d82-ff23f7cb7d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202728765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1202728765
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2763578213
Short name T319
Test name
Test status
Simulation time 8542215496 ps
CPU time 17.8 seconds
Started Jun 21 05:19:44 PM PDT 24
Finished Jun 21 05:20:03 PM PDT 24
Peak memory 211288 kb
Host smart-432bc36b-f4a2-43ef-a66f-c349094f97f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763578213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2763578213
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3522041200
Short name T190
Test name
Test status
Simulation time 14361067164 ps
CPU time 30.97 seconds
Started Jun 21 05:19:45 PM PDT 24
Finished Jun 21 05:20:17 PM PDT 24
Peak memory 214332 kb
Host smart-f4db7919-be05-4901-85dc-78e3aa989c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522041200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3522041200
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1065211002
Short name T203
Test name
Test status
Simulation time 757800209 ps
CPU time 36.97 seconds
Started Jun 21 05:19:47 PM PDT 24
Finished Jun 21 05:20:24 PM PDT 24
Peak memory 215392 kb
Host smart-20543b9a-7679-4c64-8fb6-972afc6d5565
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065211002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1065211002
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2220486517
Short name T68
Test name
Test status
Simulation time 4281482985 ps
CPU time 10.79 seconds
Started Jun 21 05:17:57 PM PDT 24
Finished Jun 21 05:18:09 PM PDT 24
Peak memory 211128 kb
Host smart-c1b901b3-04ab-482e-bea9-1f414da4b435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220486517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2220486517
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3752084661
Short name T235
Test name
Test status
Simulation time 1376527926 ps
CPU time 83.49 seconds
Started Jun 21 05:17:57 PM PDT 24
Finished Jun 21 05:19:21 PM PDT 24
Peak memory 233460 kb
Host smart-2418ed79-20a2-41b6-86dd-acf183d17b0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752084661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3752084661
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3657681641
Short name T3
Test name
Test status
Simulation time 665248139 ps
CPU time 9.7 seconds
Started Jun 21 05:18:02 PM PDT 24
Finished Jun 21 05:18:12 PM PDT 24
Peak memory 211888 kb
Host smart-1cdf2ff6-6e54-41ab-a27e-8d3f72723912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657681641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3657681641
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2378079667
Short name T17
Test name
Test status
Simulation time 553251173 ps
CPU time 100.65 seconds
Started Jun 21 05:17:59 PM PDT 24
Finished Jun 21 05:19:41 PM PDT 24
Peak memory 236388 kb
Host smart-ef1c8c36-33ed-40ee-8f21-19b70696264e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378079667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2378079667
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.297398586
Short name T161
Test name
Test status
Simulation time 6994315814 ps
CPU time 22.3 seconds
Started Jun 21 05:17:57 PM PDT 24
Finished Jun 21 05:18:20 PM PDT 24
Peak memory 214348 kb
Host smart-4546b0af-0721-4162-ba33-2eb3cedc9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297398586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.297398586
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3752072986
Short name T314
Test name
Test status
Simulation time 1230211165 ps
CPU time 17.33 seconds
Started Jun 21 05:17:59 PM PDT 24
Finished Jun 21 05:18:18 PM PDT 24
Peak memory 211828 kb
Host smart-53e34e2b-03b3-43e9-9c5c-bf1731e8f98a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752072986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3752072986
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.50146440
Short name T290
Test name
Test status
Simulation time 7954842552 ps
CPU time 13.14 seconds
Started Jun 21 05:19:52 PM PDT 24
Finished Jun 21 05:20:06 PM PDT 24
Peak memory 211116 kb
Host smart-527dd655-d674-43d4-aa55-f35f92d5ac66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50146440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.50146440
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2510111880
Short name T240
Test name
Test status
Simulation time 25812422641 ps
CPU time 263.03 seconds
Started Jun 21 05:19:53 PM PDT 24
Finished Jun 21 05:24:17 PM PDT 24
Peak memory 237620 kb
Host smart-f7ecae1a-adda-40d7-a325-c6f35c5c9bb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510111880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2510111880
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1332603608
Short name T148
Test name
Test status
Simulation time 44661955053 ps
CPU time 27.93 seconds
Started Jun 21 05:19:53 PM PDT 24
Finished Jun 21 05:20:22 PM PDT 24
Peak memory 212364 kb
Host smart-810cb994-43dc-405a-a3e0-b85bf58a08de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332603608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1332603608
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.631546511
Short name T9
Test name
Test status
Simulation time 1618756722 ps
CPU time 10.43 seconds
Started Jun 21 05:19:54 PM PDT 24
Finished Jun 21 05:20:05 PM PDT 24
Peak memory 211212 kb
Host smart-24f023e3-67bb-451b-85d4-b65d90c5d9bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631546511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.631546511
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1188483703
Short name T147
Test name
Test status
Simulation time 190314908 ps
CPU time 10.57 seconds
Started Jun 21 05:19:52 PM PDT 24
Finished Jun 21 05:20:03 PM PDT 24
Peak memory 213536 kb
Host smart-536be108-abae-4a87-9a56-c3d35075052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188483703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1188483703
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2918237668
Short name T299
Test name
Test status
Simulation time 4304130109 ps
CPU time 19.55 seconds
Started Jun 21 05:19:52 PM PDT 24
Finished Jun 21 05:20:13 PM PDT 24
Peak memory 211096 kb
Host smart-9612ce32-4d47-460b-9fa3-6abd1603cf6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918237668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2918237668
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.405861718
Short name T178
Test name
Test status
Simulation time 5160177340 ps
CPU time 12.21 seconds
Started Jun 21 05:19:52 PM PDT 24
Finished Jun 21 05:20:06 PM PDT 24
Peak memory 211104 kb
Host smart-9fe033ce-cc1d-4106-8fee-ff360b6cec70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405861718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.405861718
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1581083531
Short name T357
Test name
Test status
Simulation time 16403958560 ps
CPU time 184.08 seconds
Started Jun 21 05:19:53 PM PDT 24
Finished Jun 21 05:22:58 PM PDT 24
Peak memory 212532 kb
Host smart-509de887-89a7-46a8-a1ac-99cfe2bf8f6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581083531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1581083531
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4118935809
Short name T140
Test name
Test status
Simulation time 12040569514 ps
CPU time 20.74 seconds
Started Jun 21 05:19:53 PM PDT 24
Finished Jun 21 05:20:15 PM PDT 24
Peak memory 211204 kb
Host smart-0a60ee84-9f8d-485a-82b8-a48d5508c147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118935809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4118935809
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2545845568
Short name T198
Test name
Test status
Simulation time 430504692 ps
CPU time 8.03 seconds
Started Jun 21 05:20:05 PM PDT 24
Finished Jun 21 05:20:14 PM PDT 24
Peak memory 211208 kb
Host smart-6007f1c1-0aa3-4641-941a-c9571ec4c73e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545845568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2545845568
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1931041218
Short name T300
Test name
Test status
Simulation time 2943872255 ps
CPU time 28.26 seconds
Started Jun 21 05:19:52 PM PDT 24
Finished Jun 21 05:20:22 PM PDT 24
Peak memory 212856 kb
Host smart-abcfbd0b-a5dd-44d2-bbac-89ddddaaa621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931041218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1931041218
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2285697036
Short name T179
Test name
Test status
Simulation time 1277527648 ps
CPU time 14.12 seconds
Started Jun 21 05:19:52 PM PDT 24
Finished Jun 21 05:20:07 PM PDT 24
Peak memory 211996 kb
Host smart-d9e9a3b7-1b64-4dff-8a41-372c3bac63ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285697036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2285697036
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.256156514
Short name T234
Test name
Test status
Simulation time 541366507 ps
CPU time 6.1 seconds
Started Jun 21 05:20:00 PM PDT 24
Finished Jun 21 05:20:08 PM PDT 24
Peak memory 211052 kb
Host smart-3b8614ca-78d7-4773-98df-48ca90f13b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256156514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.256156514
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2690593216
Short name T313
Test name
Test status
Simulation time 129459294127 ps
CPU time 316.57 seconds
Started Jun 21 05:19:51 PM PDT 24
Finished Jun 21 05:25:09 PM PDT 24
Peak memory 237508 kb
Host smart-271364f9-be16-4c80-9d4c-ec62e120f390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690593216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2690593216
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1471687730
Short name T145
Test name
Test status
Simulation time 2870636897 ps
CPU time 26.64 seconds
Started Jun 21 05:19:52 PM PDT 24
Finished Jun 21 05:20:19 PM PDT 24
Peak memory 211804 kb
Host smart-608fa360-9850-4a3c-8de6-26393f7038e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471687730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1471687730
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.780311483
Short name T243
Test name
Test status
Simulation time 189524607 ps
CPU time 5.55 seconds
Started Jun 21 05:19:52 PM PDT 24
Finished Jun 21 05:19:59 PM PDT 24
Peak memory 211212 kb
Host smart-66c04cb1-0d61-4f03-8b62-0f5e66b00ccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=780311483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.780311483
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.777140376
Short name T309
Test name
Test status
Simulation time 923923851 ps
CPU time 16.53 seconds
Started Jun 21 05:19:53 PM PDT 24
Finished Jun 21 05:20:11 PM PDT 24
Peak memory 213200 kb
Host smart-9e9fb799-e7eb-4967-89dd-84b4944ad286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777140376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.777140376
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.551759024
Short name T86
Test name
Test status
Simulation time 1246553480 ps
CPU time 30.99 seconds
Started Jun 21 05:19:52 PM PDT 24
Finished Jun 21 05:20:24 PM PDT 24
Peak memory 216348 kb
Host smart-7394969c-6aae-443b-8346-5bd227f29b73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551759024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.551759024
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.320519559
Short name T163
Test name
Test status
Simulation time 1782394011 ps
CPU time 14.61 seconds
Started Jun 21 05:20:00 PM PDT 24
Finished Jun 21 05:20:16 PM PDT 24
Peak memory 211064 kb
Host smart-13f58cda-c431-4229-919c-bec02be73dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320519559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.320519559
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1592426021
Short name T211
Test name
Test status
Simulation time 2440241169 ps
CPU time 88.95 seconds
Started Jun 21 05:20:00 PM PDT 24
Finished Jun 21 05:21:30 PM PDT 24
Peak memory 228344 kb
Host smart-b680b7a9-9aa6-41f7-bda4-e81cdafb70b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592426021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1592426021
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2000911814
Short name T321
Test name
Test status
Simulation time 5450491558 ps
CPU time 18.24 seconds
Started Jun 21 05:19:59 PM PDT 24
Finished Jun 21 05:20:18 PM PDT 24
Peak memory 212044 kb
Host smart-b2c00e96-4ba6-49ab-bf8d-b86d914dca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000911814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2000911814
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1627585302
Short name T182
Test name
Test status
Simulation time 7275883053 ps
CPU time 9.72 seconds
Started Jun 21 05:20:01 PM PDT 24
Finished Jun 21 05:20:12 PM PDT 24
Peak memory 211276 kb
Host smart-6623c2ab-3d0e-40c8-b6ad-5dc2410b482c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627585302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1627585302
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2590636920
Short name T12
Test name
Test status
Simulation time 8053523473 ps
CPU time 34.42 seconds
Started Jun 21 05:20:01 PM PDT 24
Finished Jun 21 05:20:37 PM PDT 24
Peak memory 214668 kb
Host smart-8929915e-5afc-42f8-9633-9a85de5e2ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590636920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2590636920
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1791348430
Short name T88
Test name
Test status
Simulation time 21459866946 ps
CPU time 55.57 seconds
Started Jun 21 05:20:01 PM PDT 24
Finished Jun 21 05:20:58 PM PDT 24
Peak memory 217032 kb
Host smart-9deb6317-493d-4415-9576-234e25415599
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791348430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1791348430
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2767100697
Short name T151
Test name
Test status
Simulation time 4096969533 ps
CPU time 11.15 seconds
Started Jun 21 05:20:07 PM PDT 24
Finished Jun 21 05:20:19 PM PDT 24
Peak memory 211116 kb
Host smart-e9afaf7e-5c86-44fd-b4b7-fa58a5c56d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767100697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2767100697
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1884970166
Short name T353
Test name
Test status
Simulation time 28641813149 ps
CPU time 325.42 seconds
Started Jun 21 05:20:10 PM PDT 24
Finished Jun 21 05:25:36 PM PDT 24
Peak memory 234176 kb
Host smart-93c1c4a5-3fe7-4718-a77a-f52cc0c6841d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884970166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1884970166
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2300464708
Short name T202
Test name
Test status
Simulation time 1711021171 ps
CPU time 20.62 seconds
Started Jun 21 05:20:08 PM PDT 24
Finished Jun 21 05:20:29 PM PDT 24
Peak memory 211736 kb
Host smart-b234b9e0-e846-499c-a34c-fe5c9eb22597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300464708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2300464708
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1207396424
Short name T14
Test name
Test status
Simulation time 624014861 ps
CPU time 7.75 seconds
Started Jun 21 05:20:08 PM PDT 24
Finished Jun 21 05:20:17 PM PDT 24
Peak memory 211212 kb
Host smart-d182ab17-dd26-4457-a108-0ae6b184033c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207396424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1207396424
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2852746572
Short name T282
Test name
Test status
Simulation time 3881395640 ps
CPU time 13.48 seconds
Started Jun 21 05:20:00 PM PDT 24
Finished Jun 21 05:20:16 PM PDT 24
Peak memory 212776 kb
Host smart-c44775c1-0a2c-4be6-9e09-f3ef98c80265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852746572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2852746572
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.569864363
Short name T133
Test name
Test status
Simulation time 5569551131 ps
CPU time 68.2 seconds
Started Jun 21 05:19:59 PM PDT 24
Finished Jun 21 05:21:08 PM PDT 24
Peak memory 217896 kb
Host smart-6beccefd-65b6-4912-a5ed-cc77157a78e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569864363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.569864363
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2359075377
Short name T194
Test name
Test status
Simulation time 3787416444 ps
CPU time 10.4 seconds
Started Jun 21 05:20:08 PM PDT 24
Finished Jun 21 05:20:19 PM PDT 24
Peak memory 211236 kb
Host smart-b1bbcd54-6e32-4da1-97af-83bc1bdf8b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359075377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2359075377
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1705667559
Short name T255
Test name
Test status
Simulation time 87262054122 ps
CPU time 286.51 seconds
Started Jun 21 05:20:08 PM PDT 24
Finished Jun 21 05:24:55 PM PDT 24
Peak memory 235216 kb
Host smart-0593c50e-1c99-44c4-a582-1da5cb14d506
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705667559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1705667559
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3781863598
Short name T170
Test name
Test status
Simulation time 370935942 ps
CPU time 9.46 seconds
Started Jun 21 05:20:08 PM PDT 24
Finished Jun 21 05:20:18 PM PDT 24
Peak memory 211736 kb
Host smart-2d14cfb8-b132-4074-a4b9-e8a67c36ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781863598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3781863598
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2888343254
Short name T356
Test name
Test status
Simulation time 16092388228 ps
CPU time 14.32 seconds
Started Jun 21 05:20:07 PM PDT 24
Finished Jun 21 05:20:22 PM PDT 24
Peak memory 211216 kb
Host smart-b8b72877-0f2e-49f0-8fa6-7f53c45ec4bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888343254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2888343254
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.414289380
Short name T258
Test name
Test status
Simulation time 814733883 ps
CPU time 10.52 seconds
Started Jun 21 05:20:08 PM PDT 24
Finished Jun 21 05:20:19 PM PDT 24
Peak memory 213692 kb
Host smart-57ce18e9-227e-455d-86da-792b42c58235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414289380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.414289380
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.600859586
Short name T323
Test name
Test status
Simulation time 3306908924 ps
CPU time 45.56 seconds
Started Jun 21 05:20:06 PM PDT 24
Finished Jun 21 05:20:53 PM PDT 24
Peak memory 216012 kb
Host smart-f20b7cbc-4ece-4a3f-b1a4-5ea0c0d35683
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600859586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.600859586
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1622627375
Short name T104
Test name
Test status
Simulation time 489785960 ps
CPU time 4.33 seconds
Started Jun 21 05:20:15 PM PDT 24
Finished Jun 21 05:20:21 PM PDT 24
Peak memory 211056 kb
Host smart-50996401-0eb5-4025-8654-4957deee295c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622627375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1622627375
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1047042503
Short name T241
Test name
Test status
Simulation time 1537248747 ps
CPU time 95.9 seconds
Started Jun 21 05:20:14 PM PDT 24
Finished Jun 21 05:21:51 PM PDT 24
Peak memory 212576 kb
Host smart-cbc5aeee-ca3b-40d5-80cb-b358bf5d353d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047042503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1047042503
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1245097219
Short name T333
Test name
Test status
Simulation time 321463069 ps
CPU time 11.22 seconds
Started Jun 21 05:20:15 PM PDT 24
Finished Jun 21 05:20:27 PM PDT 24
Peak memory 211796 kb
Host smart-68f0c731-8888-4c2a-b892-88b0fb4f22b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245097219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1245097219
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3031933725
Short name T268
Test name
Test status
Simulation time 3578122503 ps
CPU time 11.52 seconds
Started Jun 21 05:20:14 PM PDT 24
Finished Jun 21 05:20:26 PM PDT 24
Peak memory 211276 kb
Host smart-d4dd5e1c-fd39-4a5b-ae84-e907acfe52c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031933725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3031933725
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3798006689
Short name T7
Test name
Test status
Simulation time 34267031777 ps
CPU time 31.34 seconds
Started Jun 21 05:20:10 PM PDT 24
Finished Jun 21 05:20:41 PM PDT 24
Peak memory 214096 kb
Host smart-5c6b30f9-bd9e-4bc0-97b6-371c03ce0e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798006689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3798006689
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1353257203
Short name T102
Test name
Test status
Simulation time 5002040798 ps
CPU time 15.29 seconds
Started Jun 21 05:20:07 PM PDT 24
Finished Jun 21 05:20:23 PM PDT 24
Peak memory 211100 kb
Host smart-97828325-4060-4c5f-8c18-f6ebb034aa52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353257203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1353257203
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.644706004
Short name T169
Test name
Test status
Simulation time 6081347513 ps
CPU time 13.04 seconds
Started Jun 21 05:20:15 PM PDT 24
Finished Jun 21 05:20:29 PM PDT 24
Peak memory 211120 kb
Host smart-a9d04fcc-183d-4796-b111-aac1999f3997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644706004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.644706004
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3884203196
Short name T32
Test name
Test status
Simulation time 69706950463 ps
CPU time 195.86 seconds
Started Jun 21 05:20:14 PM PDT 24
Finished Jun 21 05:23:31 PM PDT 24
Peak memory 212520 kb
Host smart-757a8ed3-9e7c-45d5-8151-e97bedd7c95a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884203196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3884203196
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2256393047
Short name T164
Test name
Test status
Simulation time 3352888908 ps
CPU time 28.73 seconds
Started Jun 21 05:20:16 PM PDT 24
Finished Jun 21 05:20:46 PM PDT 24
Peak memory 211876 kb
Host smart-dd5ba0c0-405f-4674-b872-268d40713469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256393047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2256393047
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3194121545
Short name T329
Test name
Test status
Simulation time 11277083870 ps
CPU time 14.88 seconds
Started Jun 21 05:20:17 PM PDT 24
Finished Jun 21 05:20:33 PM PDT 24
Peak memory 211284 kb
Host smart-fb3da5e1-ff31-41d6-a3c1-78fcda51bf31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194121545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3194121545
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3601043348
Short name T150
Test name
Test status
Simulation time 14407048024 ps
CPU time 34.4 seconds
Started Jun 21 05:20:16 PM PDT 24
Finished Jun 21 05:20:51 PM PDT 24
Peak memory 213636 kb
Host smart-34fb4c5f-4947-4715-9701-3c626db329f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601043348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3601043348
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3860917086
Short name T189
Test name
Test status
Simulation time 9877825422 ps
CPU time 79.93 seconds
Started Jun 21 05:20:16 PM PDT 24
Finished Jun 21 05:21:37 PM PDT 24
Peak memory 217204 kb
Host smart-d1788c4b-1675-4606-bd68-04ca454977d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860917086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3860917086
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1744400551
Short name T251
Test name
Test status
Simulation time 4135621318 ps
CPU time 6.23 seconds
Started Jun 21 05:20:23 PM PDT 24
Finished Jun 21 05:20:31 PM PDT 24
Peak memory 211128 kb
Host smart-1cfe9550-7d3b-4cb2-9b63-76dc1ed54d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744400551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1744400551
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4048501250
Short name T40
Test name
Test status
Simulation time 32259890106 ps
CPU time 172.17 seconds
Started Jun 21 05:20:16 PM PDT 24
Finished Jun 21 05:23:09 PM PDT 24
Peak memory 212440 kb
Host smart-ed3abcd4-3de5-4abe-93d7-da8b41552108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048501250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.4048501250
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1885489141
Short name T355
Test name
Test status
Simulation time 4462539576 ps
CPU time 16.48 seconds
Started Jun 21 05:20:16 PM PDT 24
Finished Jun 21 05:20:33 PM PDT 24
Peak memory 212288 kb
Host smart-02216bef-167c-446d-a12d-99002add7973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885489141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1885489141
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1765777845
Short name T153
Test name
Test status
Simulation time 1536619149 ps
CPU time 8.84 seconds
Started Jun 21 05:20:16 PM PDT 24
Finished Jun 21 05:20:25 PM PDT 24
Peak memory 211212 kb
Host smart-c2629fbe-d0cf-4c74-aa5a-2e0811e8e797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1765777845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1765777845
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1374116236
Short name T184
Test name
Test status
Simulation time 21092453658 ps
CPU time 33.61 seconds
Started Jun 21 05:20:15 PM PDT 24
Finished Jun 21 05:20:49 PM PDT 24
Peak memory 213804 kb
Host smart-8f5b4bf8-266f-42b9-b07a-0f6e13351e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374116236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1374116236
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3688583150
Short name T257
Test name
Test status
Simulation time 3153862612 ps
CPU time 58.6 seconds
Started Jun 21 05:20:17 PM PDT 24
Finished Jun 21 05:21:16 PM PDT 24
Peak memory 219272 kb
Host smart-0f7c5e26-d0de-4284-a160-3fdd517c6705
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688583150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3688583150
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1845166453
Short name T206
Test name
Test status
Simulation time 3150664218 ps
CPU time 13.62 seconds
Started Jun 21 05:20:24 PM PDT 24
Finished Jun 21 05:20:39 PM PDT 24
Peak memory 211140 kb
Host smart-f84a9b24-fcbe-4d9e-b377-62ea6408a10d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845166453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1845166453
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.699153562
Short name T318
Test name
Test status
Simulation time 12733047863 ps
CPU time 135.05 seconds
Started Jun 21 05:20:23 PM PDT 24
Finished Jun 21 05:22:40 PM PDT 24
Peak memory 211380 kb
Host smart-162df0ee-ae3b-4a85-8fa2-0975ac3f4604
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699153562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.699153562
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.208299794
Short name T24
Test name
Test status
Simulation time 2623238414 ps
CPU time 24.31 seconds
Started Jun 21 05:20:24 PM PDT 24
Finished Jun 21 05:20:50 PM PDT 24
Peak memory 211636 kb
Host smart-2677bf93-8603-4c2b-aa51-13703e96c3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208299794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.208299794
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3094805114
Short name T156
Test name
Test status
Simulation time 878451206 ps
CPU time 10.44 seconds
Started Jun 21 05:20:24 PM PDT 24
Finished Jun 21 05:20:36 PM PDT 24
Peak memory 211120 kb
Host smart-06169131-7769-483f-ac53-f93cadbaca8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094805114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3094805114
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.422057619
Short name T1
Test name
Test status
Simulation time 5846454285 ps
CPU time 27.86 seconds
Started Jun 21 05:20:23 PM PDT 24
Finished Jun 21 05:20:53 PM PDT 24
Peak memory 213780 kb
Host smart-f0dd7369-0fce-4784-afe1-b2d99975b0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422057619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.422057619
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.162261447
Short name T135
Test name
Test status
Simulation time 8719824509 ps
CPU time 34.33 seconds
Started Jun 21 05:20:24 PM PDT 24
Finished Jun 21 05:21:00 PM PDT 24
Peak memory 217220 kb
Host smart-7f6690ef-bb30-4346-86e2-94b50496f5d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162261447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.162261447
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1903737058
Short name T165
Test name
Test status
Simulation time 3282073120 ps
CPU time 6.71 seconds
Started Jun 21 05:17:56 PM PDT 24
Finished Jun 21 05:18:04 PM PDT 24
Peak memory 211128 kb
Host smart-ee843513-8dc5-4d24-be46-63ab264da580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903737058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1903737058
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.844288325
Short name T283
Test name
Test status
Simulation time 34916795622 ps
CPU time 316.41 seconds
Started Jun 21 05:17:59 PM PDT 24
Finished Jun 21 05:23:17 PM PDT 24
Peak memory 212520 kb
Host smart-3fc1d744-7962-4347-8e5f-edb5650c77a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844288325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.844288325
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1627152629
Short name T278
Test name
Test status
Simulation time 10794282482 ps
CPU time 25.62 seconds
Started Jun 21 05:17:58 PM PDT 24
Finished Jun 21 05:18:24 PM PDT 24
Peak memory 211944 kb
Host smart-6ca42a7e-4ffc-4314-be55-50870e7ccfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627152629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1627152629
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1295256901
Short name T269
Test name
Test status
Simulation time 11513294813 ps
CPU time 9.67 seconds
Started Jun 21 05:17:59 PM PDT 24
Finished Jun 21 05:18:09 PM PDT 24
Peak memory 211404 kb
Host smart-c6ddee5d-9b46-4afa-8f88-5e8506ed4b28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295256901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1295256901
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.169141940
Short name T253
Test name
Test status
Simulation time 1212826025 ps
CPU time 18.55 seconds
Started Jun 21 05:18:00 PM PDT 24
Finished Jun 21 05:18:19 PM PDT 24
Peak memory 211700 kb
Host smart-b795de0a-8d40-4fe0-9392-12a4f1419601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169141940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.169141940
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1905318397
Short name T265
Test name
Test status
Simulation time 33921664966 ps
CPU time 76.83 seconds
Started Jun 21 05:18:00 PM PDT 24
Finished Jun 21 05:19:17 PM PDT 24
Peak memory 219264 kb
Host smart-bae19e9b-d20d-4d65-860e-406b316e55aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905318397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1905318397
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3950590639
Short name T70
Test name
Test status
Simulation time 497929438 ps
CPU time 5.03 seconds
Started Jun 21 05:18:05 PM PDT 24
Finished Jun 21 05:18:11 PM PDT 24
Peak memory 210972 kb
Host smart-c01eb5e6-aa3d-417b-810b-6b5837767968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950590639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3950590639
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2660961679
Short name T328
Test name
Test status
Simulation time 7321543660 ps
CPU time 106.57 seconds
Started Jun 21 05:18:05 PM PDT 24
Finished Jun 21 05:19:52 PM PDT 24
Peak memory 236560 kb
Host smart-a55e3c63-9a8a-4505-ac0e-dfa422141555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660961679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2660961679
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3424797094
Short name T157
Test name
Test status
Simulation time 2312840943 ps
CPU time 23.73 seconds
Started Jun 21 05:18:05 PM PDT 24
Finished Jun 21 05:18:30 PM PDT 24
Peak memory 211764 kb
Host smart-79bf2ad6-6576-4832-b74b-b9692ef0c129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424797094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3424797094
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.4174672819
Short name T130
Test name
Test status
Simulation time 1014558424 ps
CPU time 11.31 seconds
Started Jun 21 05:18:04 PM PDT 24
Finished Jun 21 05:18:16 PM PDT 24
Peak memory 211168 kb
Host smart-1bb5ca71-ded5-4472-8a62-1092f9076834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174672819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.4174672819
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.28912140
Short name T223
Test name
Test status
Simulation time 4293336285 ps
CPU time 35.46 seconds
Started Jun 21 05:18:00 PM PDT 24
Finished Jun 21 05:18:36 PM PDT 24
Peak memory 213736 kb
Host smart-a63b238c-d8e6-45d5-a4e1-ea8eb27f400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28912140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.28912140
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2856334072
Short name T105
Test name
Test status
Simulation time 1649408575 ps
CPU time 13.35 seconds
Started Jun 21 05:18:06 PM PDT 24
Finished Jun 21 05:18:20 PM PDT 24
Peak memory 211048 kb
Host smart-ace88c5a-1406-4c55-993b-5a807a378e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856334072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2856334072
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2779792661
Short name T103
Test name
Test status
Simulation time 36392583774 ps
CPU time 227.61 seconds
Started Jun 21 05:18:04 PM PDT 24
Finished Jun 21 05:21:53 PM PDT 24
Peak memory 233312 kb
Host smart-92f2e7c3-3e68-4f10-89fc-4c011118d703
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779792661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2779792661
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2684711185
Short name T324
Test name
Test status
Simulation time 3954947432 ps
CPU time 33.56 seconds
Started Jun 21 05:18:05 PM PDT 24
Finished Jun 21 05:18:39 PM PDT 24
Peak memory 211836 kb
Host smart-0201abb3-61f2-46a1-9d21-3d47900f6ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684711185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2684711185
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.958370259
Short name T168
Test name
Test status
Simulation time 256303226 ps
CPU time 7.32 seconds
Started Jun 21 05:18:06 PM PDT 24
Finished Jun 21 05:18:14 PM PDT 24
Peak memory 211212 kb
Host smart-841891f8-5bf0-42b5-af33-86aa54bf7884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=958370259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.958370259
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.89407365
Short name T237
Test name
Test status
Simulation time 3513422113 ps
CPU time 29.8 seconds
Started Jun 21 05:18:05 PM PDT 24
Finished Jun 21 05:18:36 PM PDT 24
Peak memory 213340 kb
Host smart-d17a56d5-4c00-477c-960b-f77fd35beee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89407365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.89407365
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.867471964
Short name T337
Test name
Test status
Simulation time 1863690353 ps
CPU time 29.41 seconds
Started Jun 21 05:18:06 PM PDT 24
Finished Jun 21 05:18:36 PM PDT 24
Peak memory 216496 kb
Host smart-91805b5c-f907-4461-8c1f-c8cc8e2e4384
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867471964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.867471964
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3304265666
Short name T208
Test name
Test status
Simulation time 85429447 ps
CPU time 4.29 seconds
Started Jun 21 05:18:16 PM PDT 24
Finished Jun 21 05:18:21 PM PDT 24
Peak memory 211056 kb
Host smart-d808d174-9538-4569-8785-545603abff61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304265666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3304265666
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.455230242
Short name T48
Test name
Test status
Simulation time 25138324176 ps
CPU time 217.03 seconds
Started Jun 21 05:18:12 PM PDT 24
Finished Jun 21 05:21:50 PM PDT 24
Peak memory 237012 kb
Host smart-c41d0b2f-03ed-4d6f-bfb1-cbba39cf0ae5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455230242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.455230242
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3336401348
Short name T317
Test name
Test status
Simulation time 761923510 ps
CPU time 14.54 seconds
Started Jun 21 05:18:14 PM PDT 24
Finished Jun 21 05:18:30 PM PDT 24
Peak memory 211796 kb
Host smart-ae7c17df-485a-4c95-a777-ad97aa97a306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336401348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3336401348
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.103991206
Short name T114
Test name
Test status
Simulation time 4145047848 ps
CPU time 8.87 seconds
Started Jun 21 05:18:13 PM PDT 24
Finished Jun 21 05:18:23 PM PDT 24
Peak memory 211296 kb
Host smart-89b03b91-6843-4754-a11e-7071444a3644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103991206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.103991206
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3098129558
Short name T212
Test name
Test status
Simulation time 5319278268 ps
CPU time 20.79 seconds
Started Jun 21 05:18:07 PM PDT 24
Finished Jun 21 05:18:28 PM PDT 24
Peak memory 213672 kb
Host smart-c38408d9-fee0-4e48-a80d-6293aebaeb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098129558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3098129558
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1372459093
Short name T5
Test name
Test status
Simulation time 30049738852 ps
CPU time 60.07 seconds
Started Jun 21 05:18:14 PM PDT 24
Finished Jun 21 05:19:15 PM PDT 24
Peak memory 216972 kb
Host smart-ee212216-f9a2-411c-98fe-149a751d09db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372459093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1372459093
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2729163218
Short name T340
Test name
Test status
Simulation time 4135558379 ps
CPU time 16.5 seconds
Started Jun 21 05:18:16 PM PDT 24
Finished Jun 21 05:18:33 PM PDT 24
Peak memory 211120 kb
Host smart-e5167a1c-fbf4-478f-a705-f946ce9925cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729163218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2729163218
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.895654619
Short name T296
Test name
Test status
Simulation time 61898559337 ps
CPU time 199.74 seconds
Started Jun 21 05:18:18 PM PDT 24
Finished Jun 21 05:21:38 PM PDT 24
Peak memory 224968 kb
Host smart-5fe6c764-0d44-4f93-8a2c-3c7636126cd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895654619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.895654619
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.368181226
Short name T158
Test name
Test status
Simulation time 11821303460 ps
CPU time 31.15 seconds
Started Jun 21 05:18:14 PM PDT 24
Finished Jun 21 05:18:46 PM PDT 24
Peak memory 212196 kb
Host smart-cc8f28d7-c1c4-45fd-a00f-2467d708ad76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368181226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.368181226
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2452327249
Short name T204
Test name
Test status
Simulation time 1805598183 ps
CPU time 10.12 seconds
Started Jun 21 05:18:14 PM PDT 24
Finished Jun 21 05:18:25 PM PDT 24
Peak memory 211220 kb
Host smart-56996ac3-3295-4e0b-9137-61175c25098e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452327249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2452327249
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.492513831
Short name T85
Test name
Test status
Simulation time 4992452079 ps
CPU time 28.62 seconds
Started Jun 21 05:18:13 PM PDT 24
Finished Jun 21 05:18:42 PM PDT 24
Peak memory 213376 kb
Host smart-ccfbac48-94c1-4dda-b75b-509f6e110e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492513831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.492513831
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2264975795
Short name T207
Test name
Test status
Simulation time 15421586479 ps
CPU time 44.71 seconds
Started Jun 21 05:18:18 PM PDT 24
Finished Jun 21 05:19:03 PM PDT 24
Peak memory 214320 kb
Host smart-eb95abc9-5b2b-4783-a0e9-e5c9a8b6223f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264975795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2264975795
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1622497245
Short name T49
Test name
Test status
Simulation time 56938417476 ps
CPU time 2133.7 seconds
Started Jun 21 05:18:14 PM PDT 24
Finished Jun 21 05:53:49 PM PDT 24
Peak memory 236364 kb
Host smart-0b97efe6-a586-4019-8aa0-42d1ad370f02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622497245 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1622497245
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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