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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.38 96.89 92.42 97.67 100.00 98.62 97.45 98.60


Total test records in report: 464
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T302 /workspace/coverage/default/48.rom_ctrl_stress_all.2410103463 Jun 23 04:45:54 PM PDT 24 Jun 23 04:47:07 PM PDT 24 57944192384 ps
T303 /workspace/coverage/default/9.rom_ctrl_smoke.2537253138 Jun 23 04:45:10 PM PDT 24 Jun 23 04:45:26 PM PDT 24 673985575 ps
T304 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3083482158 Jun 23 04:45:29 PM PDT 24 Jun 23 04:45:45 PM PDT 24 7873073320 ps
T305 /workspace/coverage/default/8.rom_ctrl_smoke.4007160150 Jun 23 04:45:16 PM PDT 24 Jun 23 04:45:46 PM PDT 24 22321422354 ps
T306 /workspace/coverage/default/6.rom_ctrl_smoke.2087467121 Jun 23 04:45:03 PM PDT 24 Jun 23 04:45:26 PM PDT 24 2129088371 ps
T307 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.365399121 Jun 23 04:45:01 PM PDT 24 Jun 23 04:46:54 PM PDT 24 39820385717 ps
T308 /workspace/coverage/default/32.rom_ctrl_alert_test.1525308282 Jun 23 04:45:37 PM PDT 24 Jun 23 04:45:51 PM PDT 24 3002459316 ps
T309 /workspace/coverage/default/16.rom_ctrl_smoke.1266642219 Jun 23 04:45:18 PM PDT 24 Jun 23 04:45:49 PM PDT 24 6549769184 ps
T310 /workspace/coverage/default/7.rom_ctrl_alert_test.2283518226 Jun 23 04:45:14 PM PDT 24 Jun 23 04:45:32 PM PDT 24 2189995248 ps
T311 /workspace/coverage/default/7.rom_ctrl_stress_all.2864253806 Jun 23 04:45:13 PM PDT 24 Jun 23 04:46:04 PM PDT 24 23732637780 ps
T312 /workspace/coverage/default/27.rom_ctrl_alert_test.54773363 Jun 23 04:45:24 PM PDT 24 Jun 23 04:45:35 PM PDT 24 926481798 ps
T313 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3075003550 Jun 23 04:45:40 PM PDT 24 Jun 23 04:46:12 PM PDT 24 45436988463 ps
T314 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2592358202 Jun 23 04:45:28 PM PDT 24 Jun 23 04:45:33 PM PDT 24 196542026 ps
T315 /workspace/coverage/default/14.rom_ctrl_smoke.2914612277 Jun 23 04:45:18 PM PDT 24 Jun 23 04:45:29 PM PDT 24 186732844 ps
T316 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.470511673 Jun 23 04:45:29 PM PDT 24 Jun 23 04:48:43 PM PDT 24 17891919684 ps
T317 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1883093632 Jun 23 04:45:20 PM PDT 24 Jun 23 04:49:24 PM PDT 24 21439244303 ps
T318 /workspace/coverage/default/49.rom_ctrl_stress_all.3554324370 Jun 23 04:45:42 PM PDT 24 Jun 23 04:45:53 PM PDT 24 137014713 ps
T319 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.978435951 Jun 23 04:45:28 PM PDT 24 Jun 23 04:45:41 PM PDT 24 2787972365 ps
T320 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1424805478 Jun 23 04:45:08 PM PDT 24 Jun 23 04:47:18 PM PDT 24 4122891832 ps
T321 /workspace/coverage/default/45.rom_ctrl_alert_test.1999381571 Jun 23 04:45:35 PM PDT 24 Jun 23 04:45:49 PM PDT 24 3190322789 ps
T322 /workspace/coverage/default/49.rom_ctrl_smoke.2196848086 Jun 23 04:45:49 PM PDT 24 Jun 23 04:46:06 PM PDT 24 4003698640 ps
T323 /workspace/coverage/default/10.rom_ctrl_smoke.3902152276 Jun 23 04:45:08 PM PDT 24 Jun 23 04:45:40 PM PDT 24 3087459787 ps
T324 /workspace/coverage/default/17.rom_ctrl_alert_test.2685316258 Jun 23 04:45:23 PM PDT 24 Jun 23 04:45:39 PM PDT 24 11734681502 ps
T325 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2411808479 Jun 23 04:45:15 PM PDT 24 Jun 23 04:45:36 PM PDT 24 3446522926 ps
T326 /workspace/coverage/default/32.rom_ctrl_smoke.1786658091 Jun 23 04:45:25 PM PDT 24 Jun 23 04:45:38 PM PDT 24 1103754171 ps
T327 /workspace/coverage/default/27.rom_ctrl_smoke.2216135399 Jun 23 04:45:33 PM PDT 24 Jun 23 04:45:44 PM PDT 24 188820415 ps
T328 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1317196374 Jun 23 04:45:26 PM PDT 24 Jun 23 04:47:51 PM PDT 24 28337131014 ps
T329 /workspace/coverage/default/23.rom_ctrl_alert_test.849226656 Jun 23 04:45:22 PM PDT 24 Jun 23 04:45:35 PM PDT 24 1012807155 ps
T330 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.885691815 Jun 23 04:45:31 PM PDT 24 Jun 23 04:45:58 PM PDT 24 10482370180 ps
T331 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.73378153 Jun 23 04:45:23 PM PDT 24 Jun 23 04:45:57 PM PDT 24 23526257332 ps
T332 /workspace/coverage/default/15.rom_ctrl_stress_all.2311546060 Jun 23 04:45:11 PM PDT 24 Jun 23 04:47:38 PM PDT 24 15646669555 ps
T113 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1396230596 Jun 23 04:45:23 PM PDT 24 Jun 23 05:05:43 PM PDT 24 66001133302 ps
T333 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3120737979 Jun 23 04:45:20 PM PDT 24 Jun 23 04:47:36 PM PDT 24 7564255478 ps
T334 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1755767284 Jun 23 04:45:19 PM PDT 24 Jun 23 04:45:28 PM PDT 24 595325133 ps
T335 /workspace/coverage/default/44.rom_ctrl_stress_all.4124941292 Jun 23 04:45:35 PM PDT 24 Jun 23 04:46:25 PM PDT 24 2947588539 ps
T336 /workspace/coverage/default/44.rom_ctrl_smoke.589286485 Jun 23 04:45:55 PM PDT 24 Jun 23 04:46:27 PM PDT 24 3798368828 ps
T337 /workspace/coverage/default/29.rom_ctrl_smoke.568126494 Jun 23 04:45:24 PM PDT 24 Jun 23 04:45:40 PM PDT 24 3642245230 ps
T338 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3123830073 Jun 23 04:45:34 PM PDT 24 Jun 23 04:45:45 PM PDT 24 348246405 ps
T339 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.450473523 Jun 23 04:45:35 PM PDT 24 Jun 23 04:49:39 PM PDT 24 24126065315 ps
T340 /workspace/coverage/default/34.rom_ctrl_alert_test.640770256 Jun 23 04:45:25 PM PDT 24 Jun 23 04:45:38 PM PDT 24 5274860351 ps
T341 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3253344467 Jun 23 04:45:24 PM PDT 24 Jun 23 04:51:37 PM PDT 24 79149264780 ps
T342 /workspace/coverage/default/0.rom_ctrl_smoke.2648957393 Jun 23 04:45:02 PM PDT 24 Jun 23 04:45:38 PM PDT 24 7037190631 ps
T343 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.733223117 Jun 23 04:45:22 PM PDT 24 Jun 23 04:45:51 PM PDT 24 12645507966 ps
T344 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1120191675 Jun 23 04:45:05 PM PDT 24 Jun 23 04:48:58 PM PDT 24 93241372838 ps
T345 /workspace/coverage/default/10.rom_ctrl_alert_test.1532318660 Jun 23 04:45:11 PM PDT 24 Jun 23 04:45:16 PM PDT 24 437534775 ps
T346 /workspace/coverage/default/19.rom_ctrl_stress_all.322070682 Jun 23 04:45:22 PM PDT 24 Jun 23 04:45:44 PM PDT 24 12047724185 ps
T347 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2598704078 Jun 23 04:45:38 PM PDT 24 Jun 23 04:49:23 PM PDT 24 110181631311 ps
T348 /workspace/coverage/default/23.rom_ctrl_smoke.1177560527 Jun 23 04:45:20 PM PDT 24 Jun 23 04:45:43 PM PDT 24 7880440143 ps
T349 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3688660637 Jun 23 04:45:27 PM PDT 24 Jun 23 04:45:47 PM PDT 24 5886324797 ps
T350 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1871101275 Jun 23 04:45:35 PM PDT 24 Jun 23 04:45:50 PM PDT 24 2693670461 ps
T351 /workspace/coverage/default/39.rom_ctrl_alert_test.945713324 Jun 23 04:45:35 PM PDT 24 Jun 23 04:45:46 PM PDT 24 3110764942 ps
T352 /workspace/coverage/default/44.rom_ctrl_alert_test.1726664104 Jun 23 04:45:36 PM PDT 24 Jun 23 04:45:53 PM PDT 24 3998253275 ps
T353 /workspace/coverage/default/37.rom_ctrl_smoke.3847567307 Jun 23 04:45:34 PM PDT 24 Jun 23 04:45:46 PM PDT 24 220720994 ps
T354 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3099540499 Jun 23 04:45:04 PM PDT 24 Jun 23 04:45:14 PM PDT 24 2753554502 ps
T355 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2469929860 Jun 23 04:45:14 PM PDT 24 Jun 23 04:45:24 PM PDT 24 334102934 ps
T356 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4233680308 Jun 23 04:45:21 PM PDT 24 Jun 23 04:45:38 PM PDT 24 925424843 ps
T357 /workspace/coverage/default/12.rom_ctrl_alert_test.3528491328 Jun 23 04:45:10 PM PDT 24 Jun 23 04:45:21 PM PDT 24 3569169491 ps
T45 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.330110519 Jun 23 04:45:11 PM PDT 24 Jun 23 04:57:12 PM PDT 24 76579739772 ps
T358 /workspace/coverage/default/6.rom_ctrl_alert_test.1115873486 Jun 23 04:45:09 PM PDT 24 Jun 23 04:45:19 PM PDT 24 2956411416 ps
T127 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2958967553 Jun 23 04:45:16 PM PDT 24 Jun 23 05:50:22 PM PDT 24 154006478994 ps
T359 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1809976841 Jun 23 04:45:33 PM PDT 24 Jun 23 04:47:52 PM PDT 24 20909773285 ps
T360 /workspace/coverage/default/28.rom_ctrl_smoke.4276483339 Jun 23 04:45:34 PM PDT 24 Jun 23 04:45:45 PM PDT 24 416638510 ps
T361 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2789653136 Jun 23 04:45:24 PM PDT 24 Jun 23 04:45:31 PM PDT 24 102693604 ps
T362 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2847400239 Jun 23 04:45:52 PM PDT 24 Jun 23 04:46:48 PM PDT 24 1015567051 ps
T363 /workspace/coverage/default/18.rom_ctrl_smoke.2784582804 Jun 23 04:45:25 PM PDT 24 Jun 23 04:45:52 PM PDT 24 5538939362 ps
T364 /workspace/coverage/default/21.rom_ctrl_stress_all.3241908204 Jun 23 04:45:34 PM PDT 24 Jun 23 04:46:33 PM PDT 24 53043671212 ps
T365 /workspace/coverage/default/47.rom_ctrl_smoke.3025482065 Jun 23 04:45:57 PM PDT 24 Jun 23 04:46:23 PM PDT 24 2395076515 ps
T366 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.901612887 Jun 23 04:45:24 PM PDT 24 Jun 23 04:45:52 PM PDT 24 2979098826 ps
T367 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2161519594 Jun 23 04:45:08 PM PDT 24 Jun 23 04:45:14 PM PDT 24 100621396 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.618194205 Jun 23 04:44:44 PM PDT 24 Jun 23 04:44:49 PM PDT 24 93682927 ps
T68 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.618743189 Jun 23 04:45:01 PM PDT 24 Jun 23 04:45:17 PM PDT 24 8059539958 ps
T69 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3372722006 Jun 23 04:44:47 PM PDT 24 Jun 23 04:44:58 PM PDT 24 851079791 ps
T74 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2592706809 Jun 23 04:45:02 PM PDT 24 Jun 23 04:46:08 PM PDT 24 80908230390 ps
T368 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3916088432 Jun 23 04:44:56 PM PDT 24 Jun 23 04:45:03 PM PDT 24 595119137 ps
T75 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.270017137 Jun 23 04:44:48 PM PDT 24 Jun 23 04:45:01 PM PDT 24 991746970 ps
T106 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4101320708 Jun 23 04:44:56 PM PDT 24 Jun 23 04:45:04 PM PDT 24 1318734500 ps
T64 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1431379446 Jun 23 04:44:43 PM PDT 24 Jun 23 04:45:21 PM PDT 24 640454353 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.450741692 Jun 23 04:44:51 PM PDT 24 Jun 23 04:46:07 PM PDT 24 9354042227 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.802123192 Jun 23 04:44:42 PM PDT 24 Jun 23 04:45:06 PM PDT 24 1030050603 ps
T369 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1320951145 Jun 23 04:45:01 PM PDT 24 Jun 23 04:45:14 PM PDT 24 5522689144 ps
T76 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2434798109 Jun 23 04:45:05 PM PDT 24 Jun 23 04:45:34 PM PDT 24 565365920 ps
T108 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3762750790 Jun 23 04:44:47 PM PDT 24 Jun 23 04:44:57 PM PDT 24 5706375884 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3939716077 Jun 23 04:45:06 PM PDT 24 Jun 23 04:45:19 PM PDT 24 7100295994 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2024301303 Jun 23 04:44:38 PM PDT 24 Jun 23 04:45:21 PM PDT 24 6043484585 ps
T114 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.359642179 Jun 23 04:45:02 PM PDT 24 Jun 23 04:46:19 PM PDT 24 7977569988 ps
T109 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4070782320 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:10 PM PDT 24 19217808048 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.724748074 Jun 23 04:45:05 PM PDT 24 Jun 23 04:46:01 PM PDT 24 131437058117 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1236366846 Jun 23 04:45:01 PM PDT 24 Jun 23 04:45:12 PM PDT 24 2313053618 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.686814674 Jun 23 04:45:10 PM PDT 24 Jun 23 04:45:23 PM PDT 24 948174852 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2142539540 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:12 PM PDT 24 11642273516 ps
T79 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1274736001 Jun 23 04:44:56 PM PDT 24 Jun 23 04:45:06 PM PDT 24 297128292 ps
T102 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3628907537 Jun 23 04:44:54 PM PDT 24 Jun 23 04:44:59 PM PDT 24 85796377 ps
T80 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2070591659 Jun 23 04:45:06 PM PDT 24 Jun 23 04:46:00 PM PDT 24 18663293065 ps
T81 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.273751298 Jun 23 04:45:06 PM PDT 24 Jun 23 04:45:20 PM PDT 24 6105992419 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2170439423 Jun 23 04:44:48 PM PDT 24 Jun 23 04:45:02 PM PDT 24 1706722835 ps
T373 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2050003564 Jun 23 04:45:02 PM PDT 24 Jun 23 04:45:18 PM PDT 24 7253643887 ps
T103 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2804853515 Jun 23 04:45:10 PM PDT 24 Jun 23 04:45:16 PM PDT 24 223232986 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3537256232 Jun 23 04:44:41 PM PDT 24 Jun 23 04:44:54 PM PDT 24 3720041281 ps
T121 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.428656721 Jun 23 04:44:56 PM PDT 24 Jun 23 04:45:34 PM PDT 24 677642836 ps
T115 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1892386946 Jun 23 04:45:02 PM PDT 24 Jun 23 04:46:16 PM PDT 24 4149247576 ps
T82 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2345237745 Jun 23 04:45:09 PM PDT 24 Jun 23 04:45:22 PM PDT 24 1491668513 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3374154488 Jun 23 04:45:00 PM PDT 24 Jun 23 04:45:09 PM PDT 24 4932695393 ps
T120 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.513294428 Jun 23 04:45:09 PM PDT 24 Jun 23 04:46:18 PM PDT 24 591104707 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1865165449 Jun 23 04:44:43 PM PDT 24 Jun 23 04:45:53 PM PDT 24 7403096607 ps
T88 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2840119037 Jun 23 04:45:05 PM PDT 24 Jun 23 04:45:21 PM PDT 24 7141539316 ps
T376 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1303041504 Jun 23 04:44:55 PM PDT 24 Jun 23 04:45:10 PM PDT 24 1906494769 ps
T122 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.638184573 Jun 23 04:45:01 PM PDT 24 Jun 23 04:46:15 PM PDT 24 4032822244 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3579558023 Jun 23 04:45:01 PM PDT 24 Jun 23 04:45:07 PM PDT 24 85400841 ps
T378 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1581165548 Jun 23 04:45:15 PM PDT 24 Jun 23 04:45:31 PM PDT 24 8300197564 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2658511785 Jun 23 04:44:50 PM PDT 24 Jun 23 04:45:07 PM PDT 24 2620538129 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1233109689 Jun 23 04:45:01 PM PDT 24 Jun 23 04:45:15 PM PDT 24 3028404100 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.231214067 Jun 23 04:44:50 PM PDT 24 Jun 23 04:44:58 PM PDT 24 906445050 ps
T104 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1649287481 Jun 23 04:44:45 PM PDT 24 Jun 23 04:44:59 PM PDT 24 6766625669 ps
T116 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1751183946 Jun 23 04:45:03 PM PDT 24 Jun 23 04:45:49 PM PDT 24 3650870271 ps
T382 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1376799527 Jun 23 04:45:07 PM PDT 24 Jun 23 04:45:22 PM PDT 24 6268003326 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3764264828 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:10 PM PDT 24 2369424343 ps
T105 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1490295511 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:06 PM PDT 24 919731687 ps
T384 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2131819298 Jun 23 04:44:39 PM PDT 24 Jun 23 04:44:57 PM PDT 24 1497862946 ps
T385 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2523842555 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:33 PM PDT 24 210000843 ps
T386 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1090498931 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:09 PM PDT 24 5935685370 ps
T89 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3180857552 Jun 23 04:45:00 PM PDT 24 Jun 23 04:45:12 PM PDT 24 1299807317 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.340402483 Jun 23 04:45:06 PM PDT 24 Jun 23 04:45:25 PM PDT 24 34320692161 ps
T388 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.795223852 Jun 23 04:45:08 PM PDT 24 Jun 23 04:45:19 PM PDT 24 2591994905 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2617503313 Jun 23 04:44:54 PM PDT 24 Jun 23 04:46:09 PM PDT 24 30319642042 ps
T389 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.93481829 Jun 23 04:45:07 PM PDT 24 Jun 23 04:45:15 PM PDT 24 464156614 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.153468360 Jun 23 04:45:14 PM PDT 24 Jun 23 04:45:23 PM PDT 24 2556735783 ps
T391 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1773428922 Jun 23 04:44:49 PM PDT 24 Jun 23 04:45:27 PM PDT 24 12847088899 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3925933239 Jun 23 04:44:52 PM PDT 24 Jun 23 04:45:25 PM PDT 24 1609767610 ps
T92 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2352350948 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:12 PM PDT 24 3178713296 ps
T392 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.849312168 Jun 23 04:45:06 PM PDT 24 Jun 23 04:45:56 PM PDT 24 66235806695 ps
T393 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4184896200 Jun 23 04:45:02 PM PDT 24 Jun 23 04:45:18 PM PDT 24 1829059921 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4075366955 Jun 23 04:45:04 PM PDT 24 Jun 23 04:45:21 PM PDT 24 14954324664 ps
T395 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.965724489 Jun 23 04:45:16 PM PDT 24 Jun 23 04:45:31 PM PDT 24 1534264350 ps
T123 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3524457008 Jun 23 04:45:05 PM PDT 24 Jun 23 04:46:23 PM PDT 24 3535872147 ps
T396 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3371180277 Jun 23 04:44:47 PM PDT 24 Jun 23 04:44:52 PM PDT 24 347422569 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.687202459 Jun 23 04:44:47 PM PDT 24 Jun 23 04:45:34 PM PDT 24 7089808788 ps
T398 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.467963595 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:13 PM PDT 24 3925695788 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1749691636 Jun 23 04:44:40 PM PDT 24 Jun 23 04:44:50 PM PDT 24 2957293720 ps
T400 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2701808420 Jun 23 04:45:13 PM PDT 24 Jun 23 04:45:22 PM PDT 24 266225136 ps
T401 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2165439113 Jun 23 04:44:50 PM PDT 24 Jun 23 04:45:04 PM PDT 24 1435996576 ps
T118 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.156322980 Jun 23 04:45:02 PM PDT 24 Jun 23 04:46:19 PM PDT 24 2590084611 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1937516004 Jun 23 04:44:44 PM PDT 24 Jun 23 04:44:56 PM PDT 24 1225892164 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1228111013 Jun 23 04:45:01 PM PDT 24 Jun 23 04:45:06 PM PDT 24 89007414 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2296866463 Jun 23 04:45:05 PM PDT 24 Jun 23 04:45:13 PM PDT 24 599752696 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2676577159 Jun 23 04:44:47 PM PDT 24 Jun 23 04:45:03 PM PDT 24 2564486385 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.176087549 Jun 23 04:44:49 PM PDT 24 Jun 23 04:44:59 PM PDT 24 711337321 ps
T406 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.803188030 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:31 PM PDT 24 280884508 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1056016969 Jun 23 04:45:04 PM PDT 24 Jun 23 04:45:14 PM PDT 24 876568692 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1412164357 Jun 23 04:44:44 PM PDT 24 Jun 23 04:44:53 PM PDT 24 3259032173 ps
T409 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.324726326 Jun 23 04:44:42 PM PDT 24 Jun 23 04:44:53 PM PDT 24 651363412 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1687271393 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:57 PM PDT 24 33593999394 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1190044758 Jun 23 04:44:51 PM PDT 24 Jun 23 04:45:03 PM PDT 24 5183803078 ps
T412 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4004472971 Jun 23 04:45:10 PM PDT 24 Jun 23 04:45:49 PM PDT 24 6377418118 ps
T413 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3447576678 Jun 23 04:44:48 PM PDT 24 Jun 23 04:45:08 PM PDT 24 3908168939 ps
T414 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1778839779 Jun 23 04:44:47 PM PDT 24 Jun 23 04:45:03 PM PDT 24 1843916481 ps
T415 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.488892770 Jun 23 04:45:05 PM PDT 24 Jun 23 04:45:49 PM PDT 24 19145249562 ps
T94 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3763750245 Jun 23 04:44:52 PM PDT 24 Jun 23 04:45:20 PM PDT 24 6767438671 ps
T416 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.6075952 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:04 PM PDT 24 104325407 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.289250083 Jun 23 04:45:59 PM PDT 24 Jun 23 04:46:05 PM PDT 24 86357241 ps
T418 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.535315387 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:05 PM PDT 24 3375176609 ps
T419 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3714837545 Jun 23 04:44:50 PM PDT 24 Jun 23 04:44:56 PM PDT 24 918968988 ps
T124 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2248498529 Jun 23 04:45:08 PM PDT 24 Jun 23 04:45:47 PM PDT 24 1567012724 ps
T117 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1397286423 Jun 23 04:45:10 PM PDT 24 Jun 23 04:46:22 PM PDT 24 1040020834 ps
T95 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2059162238 Jun 23 04:45:07 PM PDT 24 Jun 23 04:45:16 PM PDT 24 504315848 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2634212608 Jun 23 04:44:59 PM PDT 24 Jun 23 04:45:14 PM PDT 24 1874534028 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1076376794 Jun 23 04:44:41 PM PDT 24 Jun 23 04:44:45 PM PDT 24 168172734 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2131126303 Jun 23 04:44:49 PM PDT 24 Jun 23 04:45:06 PM PDT 24 4226737031 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1387387180 Jun 23 04:45:01 PM PDT 24 Jun 23 04:45:18 PM PDT 24 8363592458 ps
T424 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3459353158 Jun 23 04:45:13 PM PDT 24 Jun 23 04:45:22 PM PDT 24 1817381557 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.692672924 Jun 23 04:44:56 PM PDT 24 Jun 23 04:45:10 PM PDT 24 3183831059 ps
T426 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3911374241 Jun 23 04:44:50 PM PDT 24 Jun 23 04:45:02 PM PDT 24 7933052587 ps
T427 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1637466450 Jun 23 04:45:59 PM PDT 24 Jun 23 04:46:16 PM PDT 24 5932373669 ps
T97 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2354439888 Jun 23 04:45:07 PM PDT 24 Jun 23 04:45:47 PM PDT 24 12261450217 ps
T428 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1661486696 Jun 23 04:45:00 PM PDT 24 Jun 23 04:45:12 PM PDT 24 3747854931 ps
T429 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.968753528 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:05 PM PDT 24 5957449921 ps
T430 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1677395455 Jun 23 04:44:59 PM PDT 24 Jun 23 04:45:04 PM PDT 24 86515588 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2802970145 Jun 23 04:44:42 PM PDT 24 Jun 23 04:44:53 PM PDT 24 15804084283 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.444469416 Jun 23 04:45:15 PM PDT 24 Jun 23 04:45:50 PM PDT 24 4125181160 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.877989484 Jun 23 04:45:05 PM PDT 24 Jun 23 04:45:23 PM PDT 24 1904195211 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3708277298 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:14 PM PDT 24 7987713529 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2191242158 Jun 23 04:44:56 PM PDT 24 Jun 23 04:45:00 PM PDT 24 594209153 ps
T436 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.979282685 Jun 23 04:45:11 PM PDT 24 Jun 23 04:45:23 PM PDT 24 1109769275 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2265610004 Jun 23 04:44:37 PM PDT 24 Jun 23 04:44:48 PM PDT 24 1046870391 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1358160170 Jun 23 04:44:47 PM PDT 24 Jun 23 04:45:27 PM PDT 24 1020609966 ps
T438 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1263788949 Jun 23 04:44:52 PM PDT 24 Jun 23 04:45:53 PM PDT 24 7225889066 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1190184216 Jun 23 04:44:53 PM PDT 24 Jun 23 04:45:17 PM PDT 24 3265010147 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.288357198 Jun 23 04:44:49 PM PDT 24 Jun 23 04:44:57 PM PDT 24 653734518 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1228486916 Jun 23 04:44:50 PM PDT 24 Jun 23 04:44:56 PM PDT 24 515586313 ps
T441 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2190192499 Jun 23 04:45:36 PM PDT 24 Jun 23 04:45:49 PM PDT 24 1973447401 ps
T442 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2247924045 Jun 23 04:44:49 PM PDT 24 Jun 23 04:44:55 PM PDT 24 315667785 ps
T443 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3065737811 Jun 23 04:44:57 PM PDT 24 Jun 23 04:45:14 PM PDT 24 1819264982 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.537999855 Jun 23 04:44:33 PM PDT 24 Jun 23 04:44:50 PM PDT 24 5918270075 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.756544319 Jun 23 04:45:10 PM PDT 24 Jun 23 04:45:20 PM PDT 24 730221844 ps
T446 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1938029927 Jun 23 04:45:07 PM PDT 24 Jun 23 04:45:24 PM PDT 24 1063289062 ps
T447 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1714985851 Jun 23 04:45:03 PM PDT 24 Jun 23 04:45:22 PM PDT 24 743801230 ps
T448 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3027014036 Jun 23 04:44:57 PM PDT 24 Jun 23 04:46:41 PM PDT 24 18075759935 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1425269912 Jun 23 04:45:10 PM PDT 24 Jun 23 04:45:15 PM PDT 24 160741483 ps
T119 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1329708454 Jun 23 04:44:52 PM PDT 24 Jun 23 04:46:10 PM PDT 24 1997853851 ps
T450 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3586951985 Jun 23 04:44:50 PM PDT 24 Jun 23 04:44:55 PM PDT 24 827797526 ps
T125 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3141557505 Jun 23 04:45:05 PM PDT 24 Jun 23 04:45:44 PM PDT 24 1763318065 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4096489433 Jun 23 04:45:36 PM PDT 24 Jun 23 04:45:46 PM PDT 24 2294589318 ps
T452 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.913352074 Jun 23 04:44:52 PM PDT 24 Jun 23 04:45:01 PM PDT 24 609039482 ps
T453 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1246307392 Jun 23 04:44:53 PM PDT 24 Jun 23 04:44:57 PM PDT 24 332614711 ps
T454 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.292278815 Jun 23 04:44:50 PM PDT 24 Jun 23 04:46:13 PM PDT 24 40103006382 ps
T455 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3213300481 Jun 23 04:45:01 PM PDT 24 Jun 23 04:45:08 PM PDT 24 85866458 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.716313596 Jun 23 04:45:05 PM PDT 24 Jun 23 04:45:11 PM PDT 24 176404513 ps
T457 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2625290280 Jun 23 04:45:13 PM PDT 24 Jun 23 04:45:28 PM PDT 24 1876536919 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.424851864 Jun 23 04:44:51 PM PDT 24 Jun 23 04:45:01 PM PDT 24 382841613 ps
T459 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1061511803 Jun 23 04:45:02 PM PDT 24 Jun 23 04:45:16 PM PDT 24 3178571181 ps
T460 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4023130653 Jun 23 04:44:50 PM PDT 24 Jun 23 04:45:09 PM PDT 24 7653670184 ps
T461 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3488691239 Jun 23 04:45:02 PM PDT 24 Jun 23 04:45:14 PM PDT 24 169294523 ps
T462 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.911480916 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:08 PM PDT 24 1133272277 ps
T463 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.161897020 Jun 23 04:45:09 PM PDT 24 Jun 23 04:45:25 PM PDT 24 1437516139 ps
T464 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4139863575 Jun 23 04:44:36 PM PDT 24 Jun 23 04:44:49 PM PDT 24 6537511352 ps

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1869152855
Short name T8
Test name
Test status
Simulation time 126879484014 ps
CPU time 311.62 seconds
Started Jun 23 04:45:39 PM PDT 24
Finished Jun 23 04:50:51 PM PDT 24
Peak memory 224700 kb
Host smart-110ba498-c452-4834-ba68-663883042240
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869152855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1869152855
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1670042981
Short name T20
Test name
Test status
Simulation time 144824478875 ps
CPU time 1329.07 seconds
Started Jun 23 04:45:47 PM PDT 24
Finished Jun 23 05:07:57 PM PDT 24
Peak memory 232104 kb
Host smart-da461d0f-8f6b-40f1-8a38-5f646200385c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670042981 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1670042981
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3759065586
Short name T11
Test name
Test status
Simulation time 1513554874 ps
CPU time 17.33 seconds
Started Jun 23 04:45:27 PM PDT 24
Finished Jun 23 04:45:45 PM PDT 24
Peak memory 211584 kb
Host smart-d0ee4c53-a19f-4efb-ad8f-e14b5d94121b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759065586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3759065586
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.697654705
Short name T6
Test name
Test status
Simulation time 39374127131 ps
CPU time 185.39 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:48:14 PM PDT 24
Peak memory 237152 kb
Host smart-e092068b-4b5f-4a0f-8045-c822415bbfac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697654705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.697654705
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.359642179
Short name T114
Test name
Test status
Simulation time 7977569988 ps
CPU time 76.61 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:46:19 PM PDT 24
Peak memory 212916 kb
Host smart-60554426-b169-4744-b0b0-7c3e6ab254c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359642179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.359642179
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2180859834
Short name T21
Test name
Test status
Simulation time 52465032960 ps
CPU time 2053.67 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 05:19:22 PM PDT 24
Peak memory 236112 kb
Host smart-cfd8260c-edc1-4d7a-83c6-64ed0be5c00a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180859834 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2180859834
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3295290201
Short name T19
Test name
Test status
Simulation time 888055651 ps
CPU time 56.44 seconds
Started Jun 23 04:45:11 PM PDT 24
Finished Jun 23 04:46:09 PM PDT 24
Peak memory 234944 kb
Host smart-620a117e-0c9c-452a-93db-bc102420a342
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295290201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3295290201
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2592706809
Short name T74
Test name
Test status
Simulation time 80908230390 ps
CPU time 65.17 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:46:08 PM PDT 24
Peak memory 211552 kb
Host smart-71e5ef61-8372-4cc3-b2c3-0a8471bb9528
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592706809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2592706809
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1643111602
Short name T41
Test name
Test status
Simulation time 1031227207 ps
CPU time 10.24 seconds
Started Jun 23 04:44:59 PM PDT 24
Finished Jun 23 04:45:09 PM PDT 24
Peak memory 210884 kb
Host smart-4a4c3307-1539-4aea-88d9-3634c45cac63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643111602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1643111602
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.330110519
Short name T45
Test name
Test status
Simulation time 76579739772 ps
CPU time 719.58 seconds
Started Jun 23 04:45:11 PM PDT 24
Finished Jun 23 04:57:12 PM PDT 24
Peak memory 230116 kb
Host smart-3305fa34-3ad7-4714-b9b3-bd597bf52963
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330110519 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.330110519
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.25341794
Short name T49
Test name
Test status
Simulation time 4439876379 ps
CPU time 35.23 seconds
Started Jun 23 04:45:31 PM PDT 24
Finished Jun 23 04:46:07 PM PDT 24
Peak memory 212056 kb
Host smart-d06efa8c-4cb7-4f83-8996-596a90a1633e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25341794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.25341794
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2958967553
Short name T127
Test name
Test status
Simulation time 154006478994 ps
CPU time 3905.51 seconds
Started Jun 23 04:45:16 PM PDT 24
Finished Jun 23 05:50:22 PM PDT 24
Peak memory 246160 kb
Host smart-54b33252-e8b9-4c94-93a7-a2fc65f2df5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958967553 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2958967553
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3731217342
Short name T24
Test name
Test status
Simulation time 170380499 ps
CPU time 9.65 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:45:34 PM PDT 24
Peak memory 213800 kb
Host smart-f22ea6e7-fa09-44cf-8ccb-c062c7308aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731217342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3731217342
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1397286423
Short name T117
Test name
Test status
Simulation time 1040020834 ps
CPU time 71.21 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:46:22 PM PDT 24
Peak memory 212488 kb
Host smart-47d7e946-4a97-4df7-9163-049438069a07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397286423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1397286423
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2024301303
Short name T66
Test name
Test status
Simulation time 6043484585 ps
CPU time 43.04 seconds
Started Jun 23 04:44:38 PM PDT 24
Finished Jun 23 04:45:21 PM PDT 24
Peak memory 219588 kb
Host smart-d7225b17-bacf-4b14-b806-31db0df91ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024301303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2024301303
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1964703246
Short name T58
Test name
Test status
Simulation time 6496376712 ps
CPU time 16.91 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:26 PM PDT 24
Peak memory 211172 kb
Host smart-deb143df-0794-4c8b-afa5-4fe116e16f75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964703246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1964703246
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.156322980
Short name T118
Test name
Test status
Simulation time 2590084611 ps
CPU time 75.53 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:46:19 PM PDT 24
Peak memory 219692 kb
Host smart-26b10b5b-b9be-4410-99a0-b01cbf5e9ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156322980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.156322980
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1329708454
Short name T119
Test name
Test status
Simulation time 1997853851 ps
CPU time 77.16 seconds
Started Jun 23 04:44:52 PM PDT 24
Finished Jun 23 04:46:10 PM PDT 24
Peak memory 212736 kb
Host smart-e9f2e751-b608-4c58-80d7-c84bed2e96ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329708454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1329708454
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3492447610
Short name T4
Test name
Test status
Simulation time 2555805380 ps
CPU time 14.6 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 214772 kb
Host smart-2ad0af04-b6ed-49c8-9290-38d265ecab5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492447610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3492447610
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2345237745
Short name T82
Test name
Test status
Simulation time 1491668513 ps
CPU time 12.09 seconds
Started Jun 23 04:45:09 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 211420 kb
Host smart-86956177-a75f-4620-bd1e-06d89d4a47d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345237745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2345237745
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4139863575
Short name T464
Test name
Test status
Simulation time 6537511352 ps
CPU time 13.21 seconds
Started Jun 23 04:44:36 PM PDT 24
Finished Jun 23 04:44:49 PM PDT 24
Peak memory 211448 kb
Host smart-e4ca0c9f-64de-4970-98d0-602e2f2dab10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139863575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4139863575
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2802970145
Short name T431
Test name
Test status
Simulation time 15804084283 ps
CPU time 10.17 seconds
Started Jun 23 04:44:42 PM PDT 24
Finished Jun 23 04:44:53 PM PDT 24
Peak memory 211448 kb
Host smart-14083abf-624a-4070-a97c-e933b1796ae3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802970145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2802970145
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.537999855
Short name T444
Test name
Test status
Simulation time 5918270075 ps
CPU time 16.56 seconds
Started Jun 23 04:44:33 PM PDT 24
Finished Jun 23 04:44:50 PM PDT 24
Peak memory 218436 kb
Host smart-56e1de4e-d77e-4917-b803-e8af68600cc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537999855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.537999855
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1661486696
Short name T428
Test name
Test status
Simulation time 3747854931 ps
CPU time 12.28 seconds
Started Jun 23 04:45:00 PM PDT 24
Finished Jun 23 04:45:12 PM PDT 24
Peak memory 219584 kb
Host smart-55fe90ac-9ff3-4db7-852a-7bf697697030
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661486696 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1661486696
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2191242158
Short name T435
Test name
Test status
Simulation time 594209153 ps
CPU time 4.31 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:00 PM PDT 24
Peak memory 218028 kb
Host smart-95a25a1e-fda7-4162-8c4a-58a33cb34155
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191242158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2191242158
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3708277298
Short name T434
Test name
Test status
Simulation time 7987713529 ps
CPU time 14.99 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 211220 kb
Host smart-42048ecb-5a72-4a98-8230-97682a620435
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708277298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3708277298
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1303041504
Short name T376
Test name
Test status
Simulation time 1906494769 ps
CPU time 14.44 seconds
Started Jun 23 04:44:55 PM PDT 24
Finished Jun 23 04:45:10 PM PDT 24
Peak memory 211128 kb
Host smart-07a4d240-03e0-4069-9613-66979d46c696
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303041504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1303041504
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3925933239
Short name T91
Test name
Test status
Simulation time 1609767610 ps
CPU time 32.19 seconds
Started Jun 23 04:44:52 PM PDT 24
Finished Jun 23 04:45:25 PM PDT 24
Peak memory 217492 kb
Host smart-5ca58ddf-43cc-423c-b4f6-fe4c53455ff3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925933239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3925933239
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1677395455
Short name T430
Test name
Test status
Simulation time 86515588 ps
CPU time 4.25 seconds
Started Jun 23 04:44:59 PM PDT 24
Finished Jun 23 04:45:04 PM PDT 24
Peak memory 218636 kb
Host smart-09214670-c945-4e5e-8dac-546ed1ae6653
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677395455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1677395455
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.424851864
Short name T458
Test name
Test status
Simulation time 382841613 ps
CPU time 9.11 seconds
Started Jun 23 04:44:51 PM PDT 24
Finished Jun 23 04:45:01 PM PDT 24
Peak memory 219404 kb
Host smart-463659a5-6f06-4cee-bf7d-7e37c697e113
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424851864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.424851864
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2248498529
Short name T124
Test name
Test status
Simulation time 1567012724 ps
CPU time 37.72 seconds
Started Jun 23 04:45:08 PM PDT 24
Finished Jun 23 04:45:47 PM PDT 24
Peak memory 211596 kb
Host smart-74ec063f-96c1-4369-8833-acc72ad257f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248498529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2248498529
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1076376794
Short name T421
Test name
Test status
Simulation time 168172734 ps
CPU time 4.06 seconds
Started Jun 23 04:44:41 PM PDT 24
Finished Jun 23 04:44:45 PM PDT 24
Peak memory 211328 kb
Host smart-e91f2617-05bd-4ee3-acb4-1e2e5735155b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076376794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1076376794
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2142539540
Short name T78
Test name
Test status
Simulation time 11642273516 ps
CPU time 12.88 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:12 PM PDT 24
Peak memory 211448 kb
Host smart-5bdaba59-37e7-44a9-819b-31fd6cf2405e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142539540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2142539540
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2676577159
Short name T404
Test name
Test status
Simulation time 2564486385 ps
CPU time 14.65 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:45:03 PM PDT 24
Peak memory 219212 kb
Host smart-1a26387a-31a1-4e0f-87b5-8c15960e17ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676577159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2676577159
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3939716077
Short name T370
Test name
Test status
Simulation time 7100295994 ps
CPU time 12.46 seconds
Started Jun 23 04:45:06 PM PDT 24
Finished Jun 23 04:45:19 PM PDT 24
Peak memory 219976 kb
Host smart-ccf9d090-6511-4afa-907e-2c27f0b2b884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939716077 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3939716077
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3537256232
Short name T374
Test name
Test status
Simulation time 3720041281 ps
CPU time 11.87 seconds
Started Jun 23 04:44:41 PM PDT 24
Finished Jun 23 04:44:54 PM PDT 24
Peak memory 211428 kb
Host smart-5f367c70-750f-4865-a78e-bafab9acd9ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537256232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3537256232
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1190044758
Short name T411
Test name
Test status
Simulation time 5183803078 ps
CPU time 12.05 seconds
Started Jun 23 04:44:51 PM PDT 24
Finished Jun 23 04:45:03 PM PDT 24
Peak memory 211252 kb
Host smart-96a4e0ff-1adf-4c42-8b32-14dfb3a8d145
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190044758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1190044758
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3579558023
Short name T377
Test name
Test status
Simulation time 85400841 ps
CPU time 4.21 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:07 PM PDT 24
Peak memory 211032 kb
Host smart-9ca899dc-839d-4f45-b389-eb2e77021880
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579558023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3579558023
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1865165449
Short name T83
Test name
Test status
Simulation time 7403096607 ps
CPU time 69.5 seconds
Started Jun 23 04:44:43 PM PDT 24
Finished Jun 23 04:45:53 PM PDT 24
Peak memory 211480 kb
Host smart-a0d45ac2-4a41-44ec-990d-4928074bf982
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865165449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1865165449
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1937516004
Short name T402
Test name
Test status
Simulation time 1225892164 ps
CPU time 11.66 seconds
Started Jun 23 04:44:44 PM PDT 24
Finished Jun 23 04:44:56 PM PDT 24
Peak memory 219464 kb
Host smart-99399942-5a0d-46da-92b2-7468fbf0d696
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937516004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1937516004
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.324726326
Short name T409
Test name
Test status
Simulation time 651363412 ps
CPU time 10.5 seconds
Started Jun 23 04:44:42 PM PDT 24
Finished Jun 23 04:44:53 PM PDT 24
Peak memory 219440 kb
Host smart-9ae5b3c6-2c77-46d9-9969-9be25efde3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324726326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.324726326
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1358160170
Short name T437
Test name
Test status
Simulation time 1020609966 ps
CPU time 39.85 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:45:27 PM PDT 24
Peak memory 218744 kb
Host smart-83771115-1ae0-4e48-aad7-d86aeaa14660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358160170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1358160170
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.535315387
Short name T418
Test name
Test status
Simulation time 3375176609 ps
CPU time 9.99 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:05 PM PDT 24
Peak memory 219640 kb
Host smart-d83fc34f-9253-409e-a542-7a571cb47625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535315387 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.535315387
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2352350948
Short name T92
Test name
Test status
Simulation time 3178713296 ps
CPU time 13.51 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:12 PM PDT 24
Peak memory 211384 kb
Host smart-cc236d8b-73ec-408a-8a91-8b86bc4e27da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352350948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2352350948
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.802123192
Short name T107
Test name
Test status
Simulation time 1030050603 ps
CPU time 24.18 seconds
Started Jun 23 04:44:42 PM PDT 24
Finished Jun 23 04:45:06 PM PDT 24
Peak memory 211320 kb
Host smart-e0c3811e-7e1b-4d6a-8fef-148987e231bb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802123192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.802123192
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.289250083
Short name T417
Test name
Test status
Simulation time 86357241 ps
CPU time 4.27 seconds
Started Jun 23 04:45:59 PM PDT 24
Finished Jun 23 04:46:05 PM PDT 24
Peak memory 211280 kb
Host smart-85cd7740-8f0c-4adb-a41b-f4ab8c1530f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289250083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.289250083
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2131819298
Short name T384
Test name
Test status
Simulation time 1497862946 ps
CPU time 16.91 seconds
Started Jun 23 04:44:39 PM PDT 24
Finished Jun 23 04:44:57 PM PDT 24
Peak memory 219444 kb
Host smart-35aa0b58-a388-4830-a974-4ed3dc2575c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131819298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2131819298
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.638184573
Short name T122
Test name
Test status
Simulation time 4032822244 ps
CPU time 74.12 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:46:15 PM PDT 24
Peak memory 212760 kb
Host smart-6d4c707a-69fc-4ab1-9a23-b64583d36a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638184573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.638184573
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1320951145
Short name T369
Test name
Test status
Simulation time 5522689144 ps
CPU time 13.04 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 219676 kb
Host smart-88b04324-0c4d-491d-bea2-2ef7a0bc86a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320951145 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1320951145
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1246307392
Short name T453
Test name
Test status
Simulation time 332614711 ps
CPU time 4.15 seconds
Started Jun 23 04:44:53 PM PDT 24
Finished Jun 23 04:44:57 PM PDT 24
Peak memory 211264 kb
Host smart-f8270140-8f9d-4cf6-a0c7-a67475b9111b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246307392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1246307392
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3763750245
Short name T94
Test name
Test status
Simulation time 6767438671 ps
CPU time 27.95 seconds
Started Jun 23 04:44:52 PM PDT 24
Finished Jun 23 04:45:20 PM PDT 24
Peak memory 211444 kb
Host smart-f47269ad-c180-4c23-bfef-557d7a47d07d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763750245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3763750245
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2165439113
Short name T401
Test name
Test status
Simulation time 1435996576 ps
CPU time 12.59 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:45:04 PM PDT 24
Peak memory 219444 kb
Host smart-0171eb7f-370d-4a7b-988a-842dc95f6d39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165439113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2165439113
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.686814674
Short name T371
Test name
Test status
Simulation time 948174852 ps
CPU time 12.48 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 219448 kb
Host smart-b6489b5c-94b5-43c4-8e6d-d8bc186436ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686814674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.686814674
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.6075952
Short name T416
Test name
Test status
Simulation time 104325407 ps
CPU time 4.74 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:04 PM PDT 24
Peak memory 219476 kb
Host smart-d2deb702-e554-4a4c-9470-e7286699861c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6075952 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.6075952
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1228111013
Short name T93
Test name
Test status
Simulation time 89007414 ps
CPU time 4.13 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:06 PM PDT 24
Peak memory 218444 kb
Host smart-498468fd-2efd-4390-96a5-0df332f15451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228111013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1228111013
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.488892770
Short name T415
Test name
Test status
Simulation time 19145249562 ps
CPU time 43.04 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 212492 kb
Host smart-a746f6e8-4a4b-4eed-afcd-0cf2ffe8ce94
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488892770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.488892770
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.467963595
Short name T398
Test name
Test status
Simulation time 3925695788 ps
CPU time 14.68 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:13 PM PDT 24
Peak memory 219552 kb
Host smart-dfc41d86-a9e9-4f48-bd2a-29e70f09d353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467963595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.467963595
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4004472971
Short name T412
Test name
Test status
Simulation time 6377418118 ps
CPU time 38.26 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 211760 kb
Host smart-bfc6256c-7a88-45a2-8698-d84913733687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004472971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4004472971
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1581165548
Short name T378
Test name
Test status
Simulation time 8300197564 ps
CPU time 15.46 seconds
Started Jun 23 04:45:15 PM PDT 24
Finished Jun 23 04:45:31 PM PDT 24
Peak memory 219680 kb
Host smart-2e4e00c7-7b36-4914-9de5-d1c0434ad04b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581165548 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1581165548
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1061511803
Short name T459
Test name
Test status
Simulation time 3178571181 ps
CPU time 13.03 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:16 PM PDT 24
Peak memory 211384 kb
Host smart-8f67adad-c5e1-47c3-8f72-ec792d35d332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061511803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1061511803
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.849312168
Short name T392
Test name
Test status
Simulation time 66235806695 ps
CPU time 49.57 seconds
Started Jun 23 04:45:06 PM PDT 24
Finished Jun 23 04:45:56 PM PDT 24
Peak memory 211448 kb
Host smart-12b411a2-8a63-45a7-8f9e-ebcc6f046f0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849312168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.849312168
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1090498931
Short name T386
Test name
Test status
Simulation time 5935685370 ps
CPU time 14.71 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:09 PM PDT 24
Peak memory 211188 kb
Host smart-b0dfcdcc-ea42-4b58-8a79-e1b2138b0019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090498931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1090498931
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.911480916
Short name T462
Test name
Test status
Simulation time 1133272277 ps
CPU time 9.11 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:08 PM PDT 24
Peak memory 219412 kb
Host smart-cf8df440-240a-49c3-9abb-3ad3e85f9800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911480916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.911480916
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2523842555
Short name T385
Test name
Test status
Simulation time 210000843 ps
CPU time 37.89 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:33 PM PDT 24
Peak memory 212724 kb
Host smart-2cffee2d-ed60-4b42-bfab-88ac9421de02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523842555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2523842555
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1233109689
Short name T380
Test name
Test status
Simulation time 3028404100 ps
CPU time 13.39 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:15 PM PDT 24
Peak memory 219676 kb
Host smart-286dba1c-9488-4968-899e-bb62b275905c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233109689 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1233109689
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3371180277
Short name T396
Test name
Test status
Simulation time 347422569 ps
CPU time 4.13 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:44:52 PM PDT 24
Peak memory 211328 kb
Host smart-dfbb41a5-6a19-4540-9b8a-1a6c419964ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371180277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3371180277
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.270017137
Short name T75
Test name
Test status
Simulation time 991746970 ps
CPU time 11.86 seconds
Started Jun 23 04:44:48 PM PDT 24
Finished Jun 23 04:45:01 PM PDT 24
Peak memory 219772 kb
Host smart-9f9fac4f-8443-4604-b801-8d238df8aa07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270017137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.270017137
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3488691239
Short name T461
Test name
Test status
Simulation time 169294523 ps
CPU time 10.55 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 219508 kb
Host smart-ce32d003-ddc2-4b8c-8ef9-73c8f05a423b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488691239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3488691239
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1431379446
Short name T64
Test name
Test status
Simulation time 640454353 ps
CPU time 37.77 seconds
Started Jun 23 04:44:43 PM PDT 24
Finished Jun 23 04:45:21 PM PDT 24
Peak memory 212672 kb
Host smart-d25c8149-3f48-4cd6-9d5b-925ffa062123
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431379446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1431379446
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1425269912
Short name T449
Test name
Test status
Simulation time 160741483 ps
CPU time 4.73 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:45:15 PM PDT 24
Peak memory 219436 kb
Host smart-c45b1d20-8ebc-4c4a-bf6c-60c44d88be15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425269912 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1425269912
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2840119037
Short name T88
Test name
Test status
Simulation time 7141539316 ps
CPU time 15.59 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:45:21 PM PDT 24
Peak memory 211424 kb
Host smart-f1c62f15-507d-41c0-bac5-c2345b79d569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840119037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2840119037
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1773428922
Short name T391
Test name
Test status
Simulation time 12847088899 ps
CPU time 36.97 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:45:27 PM PDT 24
Peak memory 211468 kb
Host smart-6c8f61b5-6290-4607-a3a9-216beb0ec30a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773428922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1773428922
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1490295511
Short name T105
Test name
Test status
Simulation time 919731687 ps
CPU time 11.55 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:06 PM PDT 24
Peak memory 219436 kb
Host smart-2e79f61f-4802-4ad1-a8b0-125efe4aba5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490295511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1490295511
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1938029927
Short name T446
Test name
Test status
Simulation time 1063289062 ps
CPU time 15.05 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:24 PM PDT 24
Peak memory 219412 kb
Host smart-8bf7b80c-21f3-48a0-a9b7-063f54745a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938029927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1938029927
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3141557505
Short name T125
Test name
Test status
Simulation time 1763318065 ps
CPU time 37.98 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:45:44 PM PDT 24
Peak memory 219428 kb
Host smart-5bcd79d7-23c4-4b4c-82cc-041ecce334a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141557505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3141557505
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3916088432
Short name T368
Test name
Test status
Simulation time 595119137 ps
CPU time 6.98 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:03 PM PDT 24
Peak memory 219524 kb
Host smart-29e5e0d4-7aeb-435f-b245-8f2f6b31b586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916088432 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3916088432
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3459353158
Short name T424
Test name
Test status
Simulation time 1817381557 ps
CPU time 7.61 seconds
Started Jun 23 04:45:13 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 218668 kb
Host smart-13376452-2ed5-430c-a8b8-d952ee04bb21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459353158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3459353158
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2354439888
Short name T97
Test name
Test status
Simulation time 12261450217 ps
CPU time 38.57 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:47 PM PDT 24
Peak memory 211468 kb
Host smart-6cba9881-6dd6-49f7-b4d0-4c63da9dbb09
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354439888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2354439888
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.273751298
Short name T81
Test name
Test status
Simulation time 6105992419 ps
CPU time 12.6 seconds
Started Jun 23 04:45:06 PM PDT 24
Finished Jun 23 04:45:20 PM PDT 24
Peak memory 211776 kb
Host smart-e43a8249-9a39-40e4-beb1-59a2584a5bd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273751298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.273751298
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.93481829
Short name T389
Test name
Test status
Simulation time 464156614 ps
CPU time 7.24 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:15 PM PDT 24
Peak memory 219152 kb
Host smart-07b8289b-0800-4503-b7b9-2c647cfee936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93481829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.93481829
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.795223852
Short name T388
Test name
Test status
Simulation time 2591994905 ps
CPU time 9.44 seconds
Started Jun 23 04:45:08 PM PDT 24
Finished Jun 23 04:45:19 PM PDT 24
Peak memory 219628 kb
Host smart-ccaef32c-5f3c-4016-bc4b-fc2b5de84143
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795223852 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.795223852
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3714837545
Short name T419
Test name
Test status
Simulation time 918968988 ps
CPU time 4.3 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:44:56 PM PDT 24
Peak memory 211328 kb
Host smart-d01e1181-537d-4165-af82-368cdcb1fcea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714837545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3714837545
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1714985851
Short name T447
Test name
Test status
Simulation time 743801230 ps
CPU time 18.61 seconds
Started Jun 23 04:45:03 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 211352 kb
Host smart-ea257300-fa9e-4e5b-8695-3df6dfd74694
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714985851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1714985851
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.968753528
Short name T429
Test name
Test status
Simulation time 5957449921 ps
CPU time 11.18 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:05 PM PDT 24
Peak memory 211484 kb
Host smart-c47cb215-bf20-4d67-bea3-6f677ebf7ab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968753528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.968753528
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4184896200
Short name T393
Test name
Test status
Simulation time 1829059921 ps
CPU time 15.72 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:18 PM PDT 24
Peak memory 219448 kb
Host smart-e34352f8-42f8-4dc2-8231-37e3156fc784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184896200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4184896200
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.513294428
Short name T120
Test name
Test status
Simulation time 591104707 ps
CPU time 67.77 seconds
Started Jun 23 04:45:09 PM PDT 24
Finished Jun 23 04:46:18 PM PDT 24
Peak memory 219540 kb
Host smart-f60d0eda-c6b3-42bb-b6d3-47f3a64ef492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513294428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.513294428
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.618743189
Short name T68
Test name
Test status
Simulation time 8059539958 ps
CPU time 15.74 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:17 PM PDT 24
Peak memory 219608 kb
Host smart-2a7451ae-8d0b-44ba-9876-6bc5785a0890
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618743189 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.618743189
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2625290280
Short name T457
Test name
Test status
Simulation time 1876536919 ps
CPU time 14.4 seconds
Started Jun 23 04:45:13 PM PDT 24
Finished Jun 23 04:45:28 PM PDT 24
Peak memory 211424 kb
Host smart-9e1f4162-3d5c-4381-b183-1e172854df5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625290280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2625290280
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.444469416
Short name T432
Test name
Test status
Simulation time 4125181160 ps
CPU time 34.71 seconds
Started Jun 23 04:45:15 PM PDT 24
Finished Jun 23 04:45:50 PM PDT 24
Peak memory 211456 kb
Host smart-6c2fbe86-7ac4-4c6f-b9e2-70570c2b7829
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444469416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.444469416
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1649287481
Short name T104
Test name
Test status
Simulation time 6766625669 ps
CPU time 13.6 seconds
Started Jun 23 04:44:45 PM PDT 24
Finished Jun 23 04:44:59 PM PDT 24
Peak memory 211444 kb
Host smart-09547b09-4379-4155-b4a4-70d71d1e1eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649287481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1649287481
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2701808420
Short name T400
Test name
Test status
Simulation time 266225136 ps
CPU time 7.55 seconds
Started Jun 23 04:45:13 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 219444 kb
Host smart-03155657-862a-42bf-9192-b3309d35cfd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701808420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2701808420
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1751183946
Short name T116
Test name
Test status
Simulation time 3650870271 ps
CPU time 45.8 seconds
Started Jun 23 04:45:03 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 219612 kb
Host smart-2f4b340e-275b-455c-92a5-1e8cfc43bebf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751183946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1751183946
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4096489433
Short name T451
Test name
Test status
Simulation time 2294589318 ps
CPU time 9.2 seconds
Started Jun 23 04:45:36 PM PDT 24
Finished Jun 23 04:45:46 PM PDT 24
Peak memory 218468 kb
Host smart-980a8521-696c-4c8f-be1e-2b6f8c58af68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096489433 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4096489433
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4023130653
Short name T460
Test name
Test status
Simulation time 7653670184 ps
CPU time 13.27 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:45:09 PM PDT 24
Peak memory 219572 kb
Host smart-f53c94e6-3e3d-46ba-9769-e0c90e74dac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023130653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4023130653
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2070591659
Short name T80
Test name
Test status
Simulation time 18663293065 ps
CPU time 52.99 seconds
Started Jun 23 04:45:06 PM PDT 24
Finished Jun 23 04:46:00 PM PDT 24
Peak memory 211408 kb
Host smart-94643670-5bf3-4187-8ac3-872e76f6516d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070591659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2070591659
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1637466450
Short name T427
Test name
Test status
Simulation time 5932373669 ps
CPU time 15.56 seconds
Started Jun 23 04:45:59 PM PDT 24
Finished Jun 23 04:46:16 PM PDT 24
Peak memory 219480 kb
Host smart-dde9008b-bc32-476d-a83d-2bec43b1f183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637466450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1637466450
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2190192499
Short name T441
Test name
Test status
Simulation time 1973447401 ps
CPU time 11.68 seconds
Started Jun 23 04:45:36 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 218296 kb
Host smart-16ace0d8-7bf0-4efe-bd94-8f756ab0eaad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190192499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2190192499
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2059162238
Short name T95
Test name
Test status
Simulation time 504315848 ps
CPU time 7.48 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:16 PM PDT 24
Peak memory 219000 kb
Host smart-8c1849e3-aea8-4b10-b57c-41fb06c0d7f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059162238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2059162238
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.231214067
Short name T381
Test name
Test status
Simulation time 906445050 ps
CPU time 7.24 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:44:58 PM PDT 24
Peak memory 211304 kb
Host smart-08c57e5a-aa4c-4ce6-9d71-23d3af5263b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231214067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.231214067
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1274736001
Short name T79
Test name
Test status
Simulation time 297128292 ps
CPU time 9.19 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:06 PM PDT 24
Peak memory 218220 kb
Host smart-58617547-b122-4c10-9009-02ebdd67d8e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274736001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1274736001
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1228486916
Short name T440
Test name
Test status
Simulation time 515586313 ps
CPU time 5.3 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:44:56 PM PDT 24
Peak memory 219552 kb
Host smart-b1f9d1e6-7aea-49ad-be00-2a99d32ec131
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228486916 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1228486916
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2265610004
Short name T96
Test name
Test status
Simulation time 1046870391 ps
CPU time 10.16 seconds
Started Jun 23 04:44:37 PM PDT 24
Finished Jun 23 04:44:48 PM PDT 24
Peak memory 211256 kb
Host smart-8ebd6002-9040-4102-a209-de6c9a5adba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265610004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2265610004
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.692672924
Short name T425
Test name
Test status
Simulation time 3183831059 ps
CPU time 13.01 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:10 PM PDT 24
Peak memory 211420 kb
Host smart-9cfa6ef7-2810-432f-97f3-d062f9b9fab8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692672924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.692672924
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.153468360
Short name T390
Test name
Test status
Simulation time 2556735783 ps
CPU time 8.14 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 211388 kb
Host smart-cbfb70c9-79bb-4275-b001-f31b077379fd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153468360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
153468360
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1190184216
Short name T98
Test name
Test status
Simulation time 3265010147 ps
CPU time 24.07 seconds
Started Jun 23 04:44:53 PM PDT 24
Finished Jun 23 04:45:17 PM PDT 24
Peak memory 211408 kb
Host smart-d8bcdf12-accb-4d1d-bb22-ee2796403e72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190184216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1190184216
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2296866463
Short name T403
Test name
Test status
Simulation time 599752696 ps
CPU time 7.89 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:45:13 PM PDT 24
Peak memory 211268 kb
Host smart-6b76d758-e54c-4137-9c43-9269291e0434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296866463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2296866463
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2658511785
Short name T379
Test name
Test status
Simulation time 2620538129 ps
CPU time 15.78 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:45:07 PM PDT 24
Peak memory 219552 kb
Host smart-faee480c-9bf2-4a37-8634-bf9ff15c9eab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658511785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2658511785
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.450741692
Short name T65
Test name
Test status
Simulation time 9354042227 ps
CPU time 75.58 seconds
Started Jun 23 04:44:51 PM PDT 24
Finished Jun 23 04:46:07 PM PDT 24
Peak memory 212988 kb
Host smart-ea738aa0-2adc-40f3-89d8-aa67b52ec1b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450741692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.450741692
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.618194205
Short name T67
Test name
Test status
Simulation time 93682927 ps
CPU time 4.27 seconds
Started Jun 23 04:44:44 PM PDT 24
Finished Jun 23 04:44:49 PM PDT 24
Peak memory 211276 kb
Host smart-a91c4398-a21b-468d-b129-cbf62c442690
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618194205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.618194205
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.4101320708
Short name T106
Test name
Test status
Simulation time 1318734500 ps
CPU time 8.42 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:04 PM PDT 24
Peak memory 211324 kb
Host smart-4db5b2e8-cd93-4bd3-ab44-b713fe9e3884
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101320708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.4101320708
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.340402483
Short name T387
Test name
Test status
Simulation time 34320692161 ps
CPU time 18.3 seconds
Started Jun 23 04:45:06 PM PDT 24
Finished Jun 23 04:45:25 PM PDT 24
Peak memory 211364 kb
Host smart-7f841773-9b1b-47ee-a962-0e4ea9df9592
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340402483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.340402483
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2131126303
Short name T422
Test name
Test status
Simulation time 4226737031 ps
CPU time 15.55 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:45:06 PM PDT 24
Peak memory 219608 kb
Host smart-16f3182a-7854-4b66-a9ac-2fb687b2cb1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131126303 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2131126303
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.176087549
Short name T405
Test name
Test status
Simulation time 711337321 ps
CPU time 8.49 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:44:59 PM PDT 24
Peak memory 219216 kb
Host smart-f60c101d-0f30-417e-91c2-d1156afa258d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176087549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.176087549
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3374154488
Short name T375
Test name
Test status
Simulation time 4932695393 ps
CPU time 8.55 seconds
Started Jun 23 04:45:00 PM PDT 24
Finished Jun 23 04:45:09 PM PDT 24
Peak memory 211272 kb
Host smart-17ff5d51-c66d-4af2-b9af-344a67e2b7d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374154488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3374154488
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2634212608
Short name T420
Test name
Test status
Simulation time 1874534028 ps
CPU time 14.14 seconds
Started Jun 23 04:44:59 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 211096 kb
Host smart-8393bf52-a8fe-4c06-80de-df21a975b612
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634212608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2634212608
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.724748074
Short name T77
Test name
Test status
Simulation time 131437058117 ps
CPU time 56.17 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:46:01 PM PDT 24
Peak memory 211320 kb
Host smart-5958ca08-0f1c-4224-a895-c6c93cfd7ad3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724748074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.724748074
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.288357198
Short name T439
Test name
Test status
Simulation time 653734518 ps
CPU time 8 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:44:57 PM PDT 24
Peak memory 210944 kb
Host smart-60d67abd-fb6b-4a99-8068-9a527066ecf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288357198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.288357198
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3764264828
Short name T383
Test name
Test status
Simulation time 2369424343 ps
CPU time 11.85 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:10 PM PDT 24
Peak memory 219552 kb
Host smart-5d6fa06e-bb9f-49b8-b5cd-3f5e2e20f77a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764264828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3764264828
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1387387180
Short name T423
Test name
Test status
Simulation time 8363592458 ps
CPU time 15.34 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:18 PM PDT 24
Peak memory 219564 kb
Host smart-da9a6567-1e8f-405d-9db8-8520d0e2e36d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387387180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1387387180
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.756544319
Short name T445
Test name
Test status
Simulation time 730221844 ps
CPU time 9.09 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:45:20 PM PDT 24
Peak memory 211292 kb
Host smart-2f97c173-50c2-44ef-96d4-a1a9a8309a1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756544319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.756544319
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3372722006
Short name T69
Test name
Test status
Simulation time 851079791 ps
CPU time 10.79 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:44:58 PM PDT 24
Peak memory 211264 kb
Host smart-14a06602-9bd1-4ee6-bf8b-74ac40323053
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372722006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3372722006
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4075366955
Short name T394
Test name
Test status
Simulation time 14954324664 ps
CPU time 16.45 seconds
Started Jun 23 04:45:04 PM PDT 24
Finished Jun 23 04:45:21 PM PDT 24
Peak memory 219596 kb
Host smart-32ccf14b-29f1-42a0-99db-c812f1d2fb7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075366955 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4075366955
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.716313596
Short name T456
Test name
Test status
Simulation time 176404513 ps
CPU time 5.31 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 211328 kb
Host smart-e32a7281-7195-444d-a2ce-49f9791a5370
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716313596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.716313596
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2170439423
Short name T372
Test name
Test status
Simulation time 1706722835 ps
CPU time 13.44 seconds
Started Jun 23 04:44:48 PM PDT 24
Finished Jun 23 04:45:02 PM PDT 24
Peak memory 210848 kb
Host smart-b9f87776-3d7d-4a7b-9685-1fa7d33aa260
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170439423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2170439423
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1412164357
Short name T408
Test name
Test status
Simulation time 3259032173 ps
CPU time 9.04 seconds
Started Jun 23 04:44:44 PM PDT 24
Finished Jun 23 04:44:53 PM PDT 24
Peak memory 211204 kb
Host smart-5ed60fb3-ff91-4d7f-9fe6-ca7417692e37
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412164357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1412164357
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2617503313
Short name T90
Test name
Test status
Simulation time 30319642042 ps
CPU time 73.95 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:46:09 PM PDT 24
Peak memory 211544 kb
Host smart-d281c6f8-103d-49e0-884a-7794c50a0aa9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617503313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2617503313
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1236366846
Short name T101
Test name
Test status
Simulation time 2313053618 ps
CPU time 9.86 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:12 PM PDT 24
Peak memory 219888 kb
Host smart-bd035752-5526-4ff5-83d8-aea0cccf7756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236366846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1236366846
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.877989484
Short name T433
Test name
Test status
Simulation time 1904195211 ps
CPU time 17.15 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 219488 kb
Host smart-09da203f-5b0c-4385-af85-4043216df233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877989484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.877989484
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3524457008
Short name T123
Test name
Test status
Simulation time 3535872147 ps
CPU time 77.3 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:46:23 PM PDT 24
Peak memory 219560 kb
Host smart-7be58a8b-0fe4-4caf-b754-3f4183981fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524457008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3524457008
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2247924045
Short name T442
Test name
Test status
Simulation time 315667785 ps
CPU time 5.26 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:44:55 PM PDT 24
Peak memory 219548 kb
Host smart-b7612329-8a38-452d-b9f7-d515e97894a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247924045 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2247924045
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3586951985
Short name T450
Test name
Test status
Simulation time 827797526 ps
CPU time 4.1 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:44:55 PM PDT 24
Peak memory 211036 kb
Host smart-3c3ab473-d067-44f5-9f0a-f628d65cd85f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586951985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3586951985
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3027014036
Short name T448
Test name
Test status
Simulation time 18075759935 ps
CPU time 103.52 seconds
Started Jun 23 04:44:57 PM PDT 24
Finished Jun 23 04:46:41 PM PDT 24
Peak memory 211472 kb
Host smart-afaff0f8-fb67-4533-94bc-3e30119de431
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027014036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3027014036
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2804853515
Short name T103
Test name
Test status
Simulation time 223232986 ps
CPU time 6.01 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:45:16 PM PDT 24
Peak memory 219288 kb
Host smart-3066a52b-6ed4-4d5e-885a-c7bbcfd23546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804853515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2804853515
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3065737811
Short name T443
Test name
Test status
Simulation time 1819264982 ps
CPU time 16.85 seconds
Started Jun 23 04:44:57 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 219300 kb
Host smart-f6302d1d-abe9-49e3-bfb7-223dcf4e948f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065737811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3065737811
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.913352074
Short name T452
Test name
Test status
Simulation time 609039482 ps
CPU time 8.52 seconds
Started Jun 23 04:44:52 PM PDT 24
Finished Jun 23 04:45:01 PM PDT 24
Peak memory 219500 kb
Host smart-91fc4b33-a17f-486a-9fc2-f92dffa34b97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913352074 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.913352074
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1376799527
Short name T382
Test name
Test status
Simulation time 6268003326 ps
CPU time 13.52 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 219552 kb
Host smart-fe4b1824-7f8e-47fb-b164-b41b48795428
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376799527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1376799527
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1263788949
Short name T438
Test name
Test status
Simulation time 7225889066 ps
CPU time 60.17 seconds
Started Jun 23 04:44:52 PM PDT 24
Finished Jun 23 04:45:53 PM PDT 24
Peak memory 210608 kb
Host smart-7c43dfe4-da90-4d43-a9b1-3a34c6062948
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263788949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1263788949
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1749691636
Short name T399
Test name
Test status
Simulation time 2957293720 ps
CPU time 9.41 seconds
Started Jun 23 04:44:40 PM PDT 24
Finished Jun 23 04:44:50 PM PDT 24
Peak memory 211444 kb
Host smart-4a828c95-ae1b-423f-85b3-3cb2af2d1626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749691636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1749691636
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.161897020
Short name T463
Test name
Test status
Simulation time 1437516139 ps
CPU time 15.28 seconds
Started Jun 23 04:45:09 PM PDT 24
Finished Jun 23 04:45:25 PM PDT 24
Peak memory 219512 kb
Host smart-0ca604a2-9d08-4948-ac15-fe76dc61f60a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161897020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.161897020
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.803188030
Short name T406
Test name
Test status
Simulation time 280884508 ps
CPU time 36.18 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:31 PM PDT 24
Peak memory 219496 kb
Host smart-19baf181-b8cc-47d4-a293-26cf308caf26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803188030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.803188030
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2050003564
Short name T373
Test name
Test status
Simulation time 7253643887 ps
CPU time 14.83 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:18 PM PDT 24
Peak memory 219912 kb
Host smart-9970d681-b0f6-4e95-94b6-a4b5b3f08c4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050003564 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2050003564
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3762750790
Short name T108
Test name
Test status
Simulation time 5706375884 ps
CPU time 9.12 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:44:57 PM PDT 24
Peak memory 219576 kb
Host smart-4b577125-c2ad-4623-99cb-52c41d42c1e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762750790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3762750790
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1687271393
Short name T410
Test name
Test status
Simulation time 33593999394 ps
CPU time 63.34 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:57 PM PDT 24
Peak memory 211472 kb
Host smart-954999ec-0f26-4717-9643-6d0e9a3813e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687271393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1687271393
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3628907537
Short name T102
Test name
Test status
Simulation time 85796377 ps
CPU time 4.49 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:44:59 PM PDT 24
Peak memory 211288 kb
Host smart-06a5471a-580f-44f5-bcc7-b950c6eea590
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628907537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3628907537
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1778839779
Short name T414
Test name
Test status
Simulation time 1843916481 ps
CPU time 16.53 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:45:03 PM PDT 24
Peak memory 219436 kb
Host smart-309afa4a-a6b1-4da2-ac6a-066dbb1f8f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778839779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1778839779
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1892386946
Short name T115
Test name
Test status
Simulation time 4149247576 ps
CPU time 72.83 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:46:16 PM PDT 24
Peak memory 211692 kb
Host smart-b91cbd13-cc9d-4091-8781-80828808458c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892386946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1892386946
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1056016969
Short name T407
Test name
Test status
Simulation time 876568692 ps
CPU time 9.78 seconds
Started Jun 23 04:45:04 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 219484 kb
Host smart-e431c590-0bdc-4595-843c-07b01c0cacfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056016969 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1056016969
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4070782320
Short name T109
Test name
Test status
Simulation time 19217808048 ps
CPU time 15.49 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:10 PM PDT 24
Peak memory 211444 kb
Host smart-7f41fe87-69e9-4afc-89de-d4c530e35f72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070782320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4070782320
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2434798109
Short name T76
Test name
Test status
Simulation time 565365920 ps
CPU time 27.94 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:45:34 PM PDT 24
Peak memory 211320 kb
Host smart-78264d93-8d54-47e3-9f04-c2736eae025d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434798109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2434798109
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.965724489
Short name T395
Test name
Test status
Simulation time 1534264350 ps
CPU time 14.58 seconds
Started Jun 23 04:45:16 PM PDT 24
Finished Jun 23 04:45:31 PM PDT 24
Peak memory 211420 kb
Host smart-b423800c-7f3e-4f69-aef0-9852de1b313c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965724489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.965724489
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3447576678
Short name T413
Test name
Test status
Simulation time 3908168939 ps
CPU time 19.84 seconds
Started Jun 23 04:44:48 PM PDT 24
Finished Jun 23 04:45:08 PM PDT 24
Peak memory 219564 kb
Host smart-461bb2a6-c99b-4770-b51d-1f70715ff322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447576678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3447576678
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.687202459
Short name T397
Test name
Test status
Simulation time 7089808788 ps
CPU time 46.48 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:45:34 PM PDT 24
Peak memory 219620 kb
Host smart-74bf8328-57a6-41ea-b676-2390ccc5d645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687202459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.687202459
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3911374241
Short name T426
Test name
Test status
Simulation time 7933052587 ps
CPU time 10.55 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:45:02 PM PDT 24
Peak memory 219636 kb
Host smart-9c45f8e1-46a4-4ea7-8283-8b30afa78f77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911374241 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3911374241
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3180857552
Short name T89
Test name
Test status
Simulation time 1299807317 ps
CPU time 11.64 seconds
Started Jun 23 04:45:00 PM PDT 24
Finished Jun 23 04:45:12 PM PDT 24
Peak memory 211420 kb
Host smart-b07edb55-0662-40b2-a27b-a60ec8560e1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180857552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3180857552
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.292278815
Short name T454
Test name
Test status
Simulation time 40103006382 ps
CPU time 81.66 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:46:13 PM PDT 24
Peak memory 211452 kb
Host smart-5c435dd0-75a9-4660-a47f-a25173e52585
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292278815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.292278815
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.979282685
Short name T436
Test name
Test status
Simulation time 1109769275 ps
CPU time 10.97 seconds
Started Jun 23 04:45:11 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 218636 kb
Host smart-874942ab-8bbb-4cad-a9d8-51e673605cee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979282685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.979282685
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3213300481
Short name T455
Test name
Test status
Simulation time 85866458 ps
CPU time 6.33 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:08 PM PDT 24
Peak memory 219460 kb
Host smart-056c821a-96d4-473b-9210-72257db0970d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213300481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3213300481
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.428656721
Short name T121
Test name
Test status
Simulation time 677642836 ps
CPU time 36.97 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:34 PM PDT 24
Peak memory 211784 kb
Host smart-f727914a-d99a-4498-abdf-0a9cd67bdb77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428656721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.428656721
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3137450350
Short name T248
Test name
Test status
Simulation time 2294250364 ps
CPU time 16.48 seconds
Started Jun 23 04:45:11 PM PDT 24
Finished Jun 23 04:45:28 PM PDT 24
Peak memory 211020 kb
Host smart-ee8e0d76-413c-45c8-9e86-4658ccd15ba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137450350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3137450350
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1156172713
Short name T227
Test name
Test status
Simulation time 3778525320 ps
CPU time 53.83 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:46:05 PM PDT 24
Peak memory 234952 kb
Host smart-fea74cb0-3dab-4c82-86d2-b5886f58fbc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156172713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1156172713
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.943934978
Short name T231
Test name
Test status
Simulation time 3333285099 ps
CPU time 28.1 seconds
Started Jun 23 04:45:25 PM PDT 24
Finished Jun 23 04:45:54 PM PDT 24
Peak memory 211936 kb
Host smart-3f912ddc-bc6a-4d2c-8da3-e5e37cd56dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943934978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.943934978
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1755767284
Short name T334
Test name
Test status
Simulation time 595325133 ps
CPU time 8.97 seconds
Started Jun 23 04:45:19 PM PDT 24
Finished Jun 23 04:45:28 PM PDT 24
Peak memory 211480 kb
Host smart-06a23d0b-362c-4876-b8dc-ef0d8de44e60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755767284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1755767284
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2648957393
Short name T342
Test name
Test status
Simulation time 7037190631 ps
CPU time 34.53 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:38 PM PDT 24
Peak memory 213968 kb
Host smart-90f00b34-e940-4c10-a14c-a3d10b1bd09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648957393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2648957393
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3008781557
Short name T56
Test name
Test status
Simulation time 430786599095 ps
CPU time 4508.9 seconds
Started Jun 23 04:45:21 PM PDT 24
Finished Jun 23 06:00:32 PM PDT 24
Peak memory 246988 kb
Host smart-27da4dcd-f9fd-4063-9b80-7b5abb352b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008781557 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3008781557
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1326863485
Short name T162
Test name
Test status
Simulation time 920342531 ps
CPU time 6.84 seconds
Started Jun 23 04:45:04 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 210964 kb
Host smart-2fd30a13-c5db-4f5e-9ea8-b0941fbe275b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326863485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1326863485
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.295682896
Short name T184
Test name
Test status
Simulation time 66832433372 ps
CPU time 192.47 seconds
Started Jun 23 04:45:18 PM PDT 24
Finished Jun 23 04:48:31 PM PDT 24
Peak memory 212372 kb
Host smart-8b07e811-8768-435a-a3a0-35b60b57b4d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295682896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.295682896
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2320997619
Short name T130
Test name
Test status
Simulation time 25471194250 ps
CPU time 34.14 seconds
Started Jun 23 04:45:09 PM PDT 24
Finished Jun 23 04:45:44 PM PDT 24
Peak memory 211116 kb
Host smart-63a2486e-1ed4-47de-8a3f-9ed7150f5689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320997619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2320997619
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1390239890
Short name T275
Test name
Test status
Simulation time 691412854 ps
CPU time 5.37 seconds
Started Jun 23 04:45:15 PM PDT 24
Finished Jun 23 04:45:21 PM PDT 24
Peak memory 211120 kb
Host smart-7a4872e6-34aa-4e7e-9457-f885fe4de8a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390239890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1390239890
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2553163638
Short name T17
Test name
Test status
Simulation time 405212435 ps
CPU time 100.45 seconds
Started Jun 23 04:45:06 PM PDT 24
Finished Jun 23 04:46:48 PM PDT 24
Peak memory 235556 kb
Host smart-ae0d28dd-74d4-4445-822f-3b823e243bdf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553163638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2553163638
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.578951039
Short name T86
Test name
Test status
Simulation time 36549929512 ps
CPU time 37.29 seconds
Started Jun 23 04:45:04 PM PDT 24
Finished Jun 23 04:45:42 PM PDT 24
Peak memory 214188 kb
Host smart-d62f8302-aaae-4d31-850b-eead364a73cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578951039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.578951039
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4169146826
Short name T144
Test name
Test status
Simulation time 298859476 ps
CPU time 18.54 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:20 PM PDT 24
Peak memory 213368 kb
Host smart-118407cd-5bba-41e9-a94b-f4a386aee33d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169146826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4169146826
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1532318660
Short name T345
Test name
Test status
Simulation time 437534775 ps
CPU time 4.23 seconds
Started Jun 23 04:45:11 PM PDT 24
Finished Jun 23 04:45:16 PM PDT 24
Peak memory 211024 kb
Host smart-1353f03c-1cbc-4d6c-95b5-f685cece8d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532318660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1532318660
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2309533003
Short name T14
Test name
Test status
Simulation time 27530926433 ps
CPU time 267.66 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:49:42 PM PDT 24
Peak memory 236664 kb
Host smart-84e1fd4b-5d30-4141-bbd4-9003afb363c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309533003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2309533003
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4112667594
Short name T143
Test name
Test status
Simulation time 337098288 ps
CPU time 11.9 seconds
Started Jun 23 04:45:08 PM PDT 24
Finished Jun 23 04:45:21 PM PDT 24
Peak memory 211680 kb
Host smart-6191bc46-f77e-411b-9ea1-63e5b10e504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112667594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4112667594
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3902152276
Short name T323
Test name
Test status
Simulation time 3087459787 ps
CPU time 30.35 seconds
Started Jun 23 04:45:08 PM PDT 24
Finished Jun 23 04:45:40 PM PDT 24
Peak memory 213592 kb
Host smart-4529bee7-67b8-45f6-ac53-060940e0d141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902152276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3902152276
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1882076659
Short name T230
Test name
Test status
Simulation time 654076136 ps
CPU time 14.72 seconds
Started Jun 23 04:44:57 PM PDT 24
Finished Jun 23 04:45:12 PM PDT 24
Peak memory 213504 kb
Host smart-ab90e9e0-231f-4e77-8c97-d3b40b263e0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882076659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1882076659
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3595272443
Short name T158
Test name
Test status
Simulation time 1151544793 ps
CPU time 11.38 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 211204 kb
Host smart-26d6213e-35c4-44e6-aed4-08363f3f07f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595272443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3595272443
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3716805933
Short name T218
Test name
Test status
Simulation time 52535550859 ps
CPU time 79.78 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:46:41 PM PDT 24
Peak memory 236188 kb
Host smart-879c282d-13ef-42b1-a0f2-afd97e32f0bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716805933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3716805933
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.678421124
Short name T235
Test name
Test status
Simulation time 81685862473 ps
CPU time 34.11 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:58 PM PDT 24
Peak memory 211992 kb
Host smart-1d181dab-11bf-4325-8db5-1ea31871fd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678421124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.678421124
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1366471748
Short name T166
Test name
Test status
Simulation time 8906553154 ps
CPU time 17.6 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 211184 kb
Host smart-f20be544-e816-4001-a051-f06490ad1f04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1366471748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1366471748
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.764185051
Short name T13
Test name
Test status
Simulation time 727015374 ps
CPU time 10.39 seconds
Started Jun 23 04:45:12 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 213320 kb
Host smart-5e11e0ac-fc3f-4e26-a8bf-2891108b7185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764185051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.764185051
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3482226544
Short name T200
Test name
Test status
Simulation time 5816406159 ps
CPU time 51.48 seconds
Started Jun 23 04:45:21 PM PDT 24
Finished Jun 23 04:46:15 PM PDT 24
Peak memory 216180 kb
Host smart-d28c8cf5-2994-46c6-bfd9-9f92e64027fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482226544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3482226544
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3528491328
Short name T357
Test name
Test status
Simulation time 3569169491 ps
CPU time 10.04 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:45:21 PM PDT 24
Peak memory 211028 kb
Host smart-c75ca888-8758-4277-94b2-26e66a27bd87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528491328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3528491328
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.645891788
Short name T180
Test name
Test status
Simulation time 26243229475 ps
CPU time 259.09 seconds
Started Jun 23 04:45:12 PM PDT 24
Finished Jun 23 04:49:32 PM PDT 24
Peak memory 212476 kb
Host smart-49187321-eb26-40e4-88a0-6c1836a4a35a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645891788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.645891788
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3455335347
Short name T159
Test name
Test status
Simulation time 1314425331 ps
CPU time 14.06 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 211724 kb
Host smart-a4cc9b59-4e53-400a-89e4-eb1ba36e08ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455335347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3455335347
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.598783361
Short name T286
Test name
Test status
Simulation time 3378505266 ps
CPU time 14.16 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 04:45:43 PM PDT 24
Peak memory 211144 kb
Host smart-ef1271c1-75e8-48a6-a2c9-59192c44f84e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=598783361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.598783361
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3221604719
Short name T183
Test name
Test status
Simulation time 11372786141 ps
CPU time 26.14 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:50 PM PDT 24
Peak memory 213812 kb
Host smart-7560a871-089b-4272-8368-f1b63398fc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221604719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3221604719
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1788065951
Short name T152
Test name
Test status
Simulation time 27319825791 ps
CPU time 42.99 seconds
Started Jun 23 04:45:15 PM PDT 24
Finished Jun 23 04:45:59 PM PDT 24
Peak memory 214392 kb
Host smart-49803af9-7818-4583-a278-ddd5b602d9a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788065951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1788065951
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2535580721
Short name T145
Test name
Test status
Simulation time 1656068570 ps
CPU time 13.98 seconds
Started Jun 23 04:45:21 PM PDT 24
Finished Jun 23 04:45:37 PM PDT 24
Peak memory 210964 kb
Host smart-bbd066be-75c8-458f-83f8-94be9861ef31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535580721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2535580721
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3550617419
Short name T234
Test name
Test status
Simulation time 58489465342 ps
CPU time 175.5 seconds
Started Jun 23 04:45:17 PM PDT 24
Finished Jun 23 04:48:13 PM PDT 24
Peak memory 224884 kb
Host smart-bcc7ef9c-a7c1-4c43-b871-ff368db78d68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550617419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3550617419
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.420203874
Short name T163
Test name
Test status
Simulation time 6860964574 ps
CPU time 17.8 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:41 PM PDT 24
Peak memory 212376 kb
Host smart-f0122bb2-5a4d-4c3e-8aae-d11607bc0359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420203874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.420203874
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2383789549
Short name T110
Test name
Test status
Simulation time 1561709245 ps
CPU time 10.33 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:34 PM PDT 24
Peak memory 211232 kb
Host smart-703d902b-ba10-4707-9d95-34d5da9d987b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383789549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2383789549
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2074075330
Short name T157
Test name
Test status
Simulation time 14970502679 ps
CPU time 39.17 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:46:02 PM PDT 24
Peak memory 213604 kb
Host smart-49d35c7b-a1eb-4710-a2f7-da7ced9f0ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074075330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2074075330
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2066067045
Short name T228
Test name
Test status
Simulation time 10876994585 ps
CPU time 43.89 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 04:46:13 PM PDT 24
Peak memory 218256 kb
Host smart-afeca732-879b-482b-a90e-d61023658559
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066067045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2066067045
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1680252219
Short name T71
Test name
Test status
Simulation time 87942540 ps
CPU time 4.15 seconds
Started Jun 23 04:45:08 PM PDT 24
Finished Jun 23 04:45:13 PM PDT 24
Peak memory 210964 kb
Host smart-cc524e99-e0d9-4244-9258-a809a292bab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680252219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1680252219
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1512872197
Short name T239
Test name
Test status
Simulation time 1883149018 ps
CPU time 114.28 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:47:18 PM PDT 24
Peak memory 227752 kb
Host smart-dad5b3e6-195b-4aa4-897a-b12a2286724c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512872197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1512872197
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.959977104
Short name T222
Test name
Test status
Simulation time 6029487198 ps
CPU time 31.88 seconds
Started Jun 23 04:45:09 PM PDT 24
Finished Jun 23 04:45:42 PM PDT 24
Peak memory 212308 kb
Host smart-7e65e57a-19dc-438b-8043-6132a9c05470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959977104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.959977104
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3099540499
Short name T354
Test name
Test status
Simulation time 2753554502 ps
CPU time 9.69 seconds
Started Jun 23 04:45:04 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 211164 kb
Host smart-0cc29ecd-1e7c-4c90-89bd-9a383aa77abe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099540499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3099540499
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2914612277
Short name T315
Test name
Test status
Simulation time 186732844 ps
CPU time 10.08 seconds
Started Jun 23 04:45:18 PM PDT 24
Finished Jun 23 04:45:29 PM PDT 24
Peak memory 213304 kb
Host smart-d090b401-5ba7-4db6-aecc-ae6be5b26a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914612277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2914612277
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.261313636
Short name T100
Test name
Test status
Simulation time 3133512490 ps
CPU time 23.78 seconds
Started Jun 23 04:45:12 PM PDT 24
Finished Jun 23 04:45:37 PM PDT 24
Peak memory 214240 kb
Host smart-0c895f6a-316a-4e20-8fea-e7342d5c9902
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261313636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.261313636
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1711603247
Short name T280
Test name
Test status
Simulation time 7070444061 ps
CPU time 14.86 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 210444 kb
Host smart-62814955-0608-4557-aafc-1cf2167ea00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711603247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1711603247
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3514099456
Short name T39
Test name
Test status
Simulation time 25428236607 ps
CPU time 253.75 seconds
Started Jun 23 04:45:21 PM PDT 24
Finished Jun 23 04:49:35 PM PDT 24
Peak memory 228240 kb
Host smart-3b1c40f2-f6e9-461f-a96b-d0dca8d824f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514099456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3514099456
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.172091506
Short name T277
Test name
Test status
Simulation time 12304445226 ps
CPU time 27.37 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 211920 kb
Host smart-7cad6488-f9a4-4beb-8932-7c891f3dbcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172091506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.172091506
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.972566609
Short name T185
Test name
Test status
Simulation time 1308031895 ps
CPU time 9.51 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:34 PM PDT 24
Peak memory 211112 kb
Host smart-691db4b4-35bb-4842-9ab6-d7599756be15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972566609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.972566609
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1930886806
Short name T7
Test name
Test status
Simulation time 4892228890 ps
CPU time 16.82 seconds
Started Jun 23 04:45:21 PM PDT 24
Finished Jun 23 04:45:40 PM PDT 24
Peak memory 213964 kb
Host smart-c8652df9-0264-4ea0-9742-054a70a3b37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930886806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1930886806
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2311546060
Short name T332
Test name
Test status
Simulation time 15646669555 ps
CPU time 145.68 seconds
Started Jun 23 04:45:11 PM PDT 24
Finished Jun 23 04:47:38 PM PDT 24
Peak memory 218924 kb
Host smart-92f54b17-6acb-47f7-b35b-dc5787f22639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311546060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2311546060
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.828815842
Short name T274
Test name
Test status
Simulation time 5280509776 ps
CPU time 11.93 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:45:27 PM PDT 24
Peak memory 211136 kb
Host smart-fa8429bb-e0f0-47ba-9aa6-02b5407e86a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828815842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.828815842
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.88360200
Short name T38
Test name
Test status
Simulation time 54775749951 ps
CPU time 217.15 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:49:02 PM PDT 24
Peak memory 212416 kb
Host smart-e05c8513-2db3-45c4-b96a-2ed35e4e16f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88360200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_co
rrupt_sig_fatal_chk.88360200
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3455392197
Short name T207
Test name
Test status
Simulation time 4021100812 ps
CPU time 22.09 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:48 PM PDT 24
Peak memory 211712 kb
Host smart-f0032848-ca00-4cdc-8c9e-87d8d1339426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455392197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3455392197
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1871101275
Short name T350
Test name
Test status
Simulation time 2693670461 ps
CPU time 13.59 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:45:50 PM PDT 24
Peak memory 211184 kb
Host smart-8794ac4a-735b-44c5-abe2-520b6123e151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1871101275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1871101275
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1266642219
Short name T309
Test name
Test status
Simulation time 6549769184 ps
CPU time 30.38 seconds
Started Jun 23 04:45:18 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 214196 kb
Host smart-945cb216-95b2-4d3b-ab2e-c0e1f988f86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266642219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1266642219
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4124532122
Short name T258
Test name
Test status
Simulation time 10800201448 ps
CPU time 67.13 seconds
Started Jun 23 04:45:16 PM PDT 24
Finished Jun 23 04:46:24 PM PDT 24
Peak memory 215468 kb
Host smart-c85290e4-a9a2-4ff7-931f-dbbc26862640
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124532122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4124532122
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.780498296
Short name T51
Test name
Test status
Simulation time 107483557476 ps
CPU time 2090.22 seconds
Started Jun 23 04:45:19 PM PDT 24
Finished Jun 23 05:20:11 PM PDT 24
Peak memory 236040 kb
Host smart-77dd748b-3ade-4425-b564-9cd8c7012bde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780498296 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.780498296
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2685316258
Short name T324
Test name
Test status
Simulation time 11734681502 ps
CPU time 14.31 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:45:39 PM PDT 24
Peak memory 211028 kb
Host smart-24c0cd25-5c73-4812-b9e9-2f3749c496a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685316258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2685316258
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3508106991
Short name T147
Test name
Test status
Simulation time 10287129575 ps
CPU time 22.24 seconds
Started Jun 23 04:45:13 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 212432 kb
Host smart-6ed27c21-a12a-4197-af68-8404d66b5358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508106991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3508106991
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4195832010
Short name T238
Test name
Test status
Simulation time 5097747189 ps
CPU time 16.21 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:45:27 PM PDT 24
Peak memory 211044 kb
Host smart-4408e549-18be-49ae-95ce-216ea66bbfd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195832010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4195832010
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1169131674
Short name T244
Test name
Test status
Simulation time 513965137 ps
CPU time 11.81 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:45:32 PM PDT 24
Peak memory 213608 kb
Host smart-fb4dfb5f-977d-4386-8357-e86ae15e173a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169131674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1169131674
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1400057129
Short name T250
Test name
Test status
Simulation time 339300556 ps
CPU time 7.1 seconds
Started Jun 23 04:45:16 PM PDT 24
Finished Jun 23 04:45:24 PM PDT 24
Peak memory 211180 kb
Host smart-7a1fe0d6-ccc0-46b3-b821-692352a97a22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400057129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1400057129
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1396230596
Short name T113
Test name
Test status
Simulation time 66001133302 ps
CPU time 1217.97 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 05:05:43 PM PDT 24
Peak memory 232480 kb
Host smart-57010b0e-c7fc-45f8-aff2-7585b88dcb1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396230596 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1396230596
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4251456005
Short name T154
Test name
Test status
Simulation time 8482550746 ps
CPU time 16.51 seconds
Started Jun 23 04:45:13 PM PDT 24
Finished Jun 23 04:45:30 PM PDT 24
Peak memory 211028 kb
Host smart-8e13951c-6bd6-4000-98cd-3710e5807817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251456005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4251456005
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1334290718
Short name T197
Test name
Test status
Simulation time 57988639962 ps
CPU time 252.59 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:49:36 PM PDT 24
Peak memory 212452 kb
Host smart-f4249abd-74d3-42e8-92c7-8a656dccb67c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334290718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1334290718
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.812925376
Short name T249
Test name
Test status
Simulation time 32074410586 ps
CPU time 33.33 seconds
Started Jun 23 04:45:08 PM PDT 24
Finished Jun 23 04:45:43 PM PDT 24
Peak memory 211992 kb
Host smart-c5b09fcc-51fb-4019-b314-508ce64a61f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812925376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.812925376
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2161519594
Short name T367
Test name
Test status
Simulation time 100621396 ps
CPU time 5.43 seconds
Started Jun 23 04:45:08 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 211140 kb
Host smart-e53ca28a-dacc-470f-b5d4-53b6467cffbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161519594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2161519594
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2784582804
Short name T363
Test name
Test status
Simulation time 5538939362 ps
CPU time 26.03 seconds
Started Jun 23 04:45:25 PM PDT 24
Finished Jun 23 04:45:52 PM PDT 24
Peak memory 213328 kb
Host smart-ddcc837c-0afb-44f1-a006-3f9cd7fdf4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784582804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2784582804
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2859019349
Short name T199
Test name
Test status
Simulation time 3874999438 ps
CPU time 59 seconds
Started Jun 23 04:45:17 PM PDT 24
Finished Jun 23 04:46:16 PM PDT 24
Peak memory 219172 kb
Host smart-7cdd089e-f329-4012-9155-c26ee3d86346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859019349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2859019349
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2690187978
Short name T142
Test name
Test status
Simulation time 836420544 ps
CPU time 8.43 seconds
Started Jun 23 04:45:15 PM PDT 24
Finished Jun 23 04:45:24 PM PDT 24
Peak memory 210964 kb
Host smart-a0eb1ac5-15bd-4e11-aba1-6af99c90d227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690187978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2690187978
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1555790885
Short name T31
Test name
Test status
Simulation time 115207394738 ps
CPU time 293.94 seconds
Started Jun 23 04:45:19 PM PDT 24
Finished Jun 23 04:50:14 PM PDT 24
Peak memory 227848 kb
Host smart-ab238830-184c-4f04-9552-9b13a9dc42f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555790885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1555790885
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1222355709
Short name T99
Test name
Test status
Simulation time 1971890570 ps
CPU time 12.86 seconds
Started Jun 23 04:45:25 PM PDT 24
Finished Jun 23 04:45:39 PM PDT 24
Peak memory 211604 kb
Host smart-c1b3f071-3be6-4706-ac90-05ed78bfe7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222355709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1222355709
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2469936077
Short name T136
Test name
Test status
Simulation time 4756441187 ps
CPU time 16.97 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:45:50 PM PDT 24
Peak memory 211184 kb
Host smart-777caaeb-1bfd-42b1-9699-43adc1b1b75d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2469936077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2469936077
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.76067172
Short name T273
Test name
Test status
Simulation time 1132999468 ps
CPU time 11.87 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 213848 kb
Host smart-723a399b-e425-4149-bd69-67639c719e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76067172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.76067172
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.322070682
Short name T346
Test name
Test status
Simulation time 12047724185 ps
CPU time 19.79 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:44 PM PDT 24
Peak memory 212532 kb
Host smart-a4a76edd-8e22-4d3c-9387-0888ac9e7387
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322070682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.322070682
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2237946883
Short name T196
Test name
Test status
Simulation time 620223066 ps
CPU time 8.62 seconds
Started Jun 23 04:45:12 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 210960 kb
Host smart-8529904a-12c2-48ba-92f5-b427e04dce6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237946883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2237946883
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.989092232
Short name T37
Test name
Test status
Simulation time 45450127145 ps
CPU time 191.68 seconds
Started Jun 23 04:45:11 PM PDT 24
Finished Jun 23 04:48:24 PM PDT 24
Peak memory 237192 kb
Host smart-c9fece36-72a0-4d29-8a42-c320b3fb4849
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989092232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.989092232
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2421579468
Short name T164
Test name
Test status
Simulation time 15827061457 ps
CPU time 34.28 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:45:40 PM PDT 24
Peak memory 212020 kb
Host smart-f23cbb18-4858-4774-b419-0329e0f7f7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421579468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2421579468
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.659800836
Short name T111
Test name
Test status
Simulation time 3859603679 ps
CPU time 15.69 seconds
Started Jun 23 04:44:59 PM PDT 24
Finished Jun 23 04:45:15 PM PDT 24
Peak memory 211184 kb
Host smart-7d501dfe-ef99-4ae1-a25b-df178b58a28b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659800836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.659800836
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1475200179
Short name T26
Test name
Test status
Simulation time 1380084510 ps
CPU time 112.46 seconds
Started Jun 23 04:45:16 PM PDT 24
Finished Jun 23 04:47:09 PM PDT 24
Peak memory 236748 kb
Host smart-14758817-0ab7-4983-8519-3bbcce466689
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475200179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1475200179
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3593513642
Short name T276
Test name
Test status
Simulation time 187339537 ps
CPU time 9.5 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 213512 kb
Host smart-b2039123-feed-4838-954e-411de4a35530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593513642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3593513642
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.212578347
Short name T295
Test name
Test status
Simulation time 9449816237 ps
CPU time 49.85 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:58 PM PDT 24
Peak memory 219168 kb
Host smart-e4457367-e3d1-41df-8aaf-eb8de0a31115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212578347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.212578347
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4271876917
Short name T288
Test name
Test status
Simulation time 3984438866 ps
CPU time 16.27 seconds
Started Jun 23 04:45:12 PM PDT 24
Finished Jun 23 04:45:29 PM PDT 24
Peak memory 211024 kb
Host smart-810d6de4-795f-479a-852f-2ac61ff4cf9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271876917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4271876917
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.401970680
Short name T15
Test name
Test status
Simulation time 49454785691 ps
CPU time 97.72 seconds
Started Jun 23 04:45:03 PM PDT 24
Finished Jun 23 04:46:41 PM PDT 24
Peak memory 237116 kb
Host smart-a7204a19-4e22-4a43-a274-73f500dbd85c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401970680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.401970680
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1042740728
Short name T5
Test name
Test status
Simulation time 20124206101 ps
CPU time 25.15 seconds
Started Jun 23 04:45:13 PM PDT 24
Finished Jun 23 04:45:39 PM PDT 24
Peak memory 212064 kb
Host smart-282c42a4-8b87-44bb-8b34-ac2d0ff07bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042740728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1042740728
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3101875121
Short name T112
Test name
Test status
Simulation time 8254197506 ps
CPU time 17.18 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:45:32 PM PDT 24
Peak memory 211184 kb
Host smart-c00f1af7-c03f-4ce7-a541-52c9557f9555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101875121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3101875121
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3951350569
Short name T171
Test name
Test status
Simulation time 5478887287 ps
CPU time 24.92 seconds
Started Jun 23 04:45:26 PM PDT 24
Finished Jun 23 04:45:52 PM PDT 24
Peak memory 213980 kb
Host smart-0a6bc5f9-4ae2-4624-a661-7d6e20e5e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951350569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3951350569
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3155601266
Short name T62
Test name
Test status
Simulation time 24748123207 ps
CPU time 60.1 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:46:33 PM PDT 24
Peak memory 215752 kb
Host smart-65ed7a8f-5852-457a-b86d-65cbad97b4ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155601266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3155601266
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1261721077
Short name T72
Test name
Test status
Simulation time 3681000069 ps
CPU time 15.22 seconds
Started Jun 23 04:45:52 PM PDT 24
Finished Jun 23 04:46:09 PM PDT 24
Peak memory 211136 kb
Host smart-fc1fd17d-011f-4178-bb4d-1910636133fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261721077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1261721077
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.4005237714
Short name T201
Test name
Test status
Simulation time 23963402760 ps
CPU time 130.2 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:47:26 PM PDT 24
Peak memory 228264 kb
Host smart-158f3495-e55f-4640-b152-98173075bb4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005237714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.4005237714
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2129564370
Short name T226
Test name
Test status
Simulation time 7630322902 ps
CPU time 32.53 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:58 PM PDT 24
Peak memory 212272 kb
Host smart-1b210400-f336-45df-9bad-92b3c917f965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129564370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2129564370
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1819140424
Short name T43
Test name
Test status
Simulation time 4257948728 ps
CPU time 17.12 seconds
Started Jun 23 04:45:25 PM PDT 24
Finished Jun 23 04:45:45 PM PDT 24
Peak memory 211204 kb
Host smart-376f27f3-efdc-4895-bfad-4eb6eab1fcf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819140424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1819140424
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3915708836
Short name T261
Test name
Test status
Simulation time 31368316752 ps
CPU time 26.43 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 214240 kb
Host smart-3fdff6ab-de86-4874-9dba-746cb32476ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915708836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3915708836
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3241908204
Short name T364
Test name
Test status
Simulation time 53043671212 ps
CPU time 58.68 seconds
Started Jun 23 04:45:34 PM PDT 24
Finished Jun 23 04:46:33 PM PDT 24
Peak memory 216688 kb
Host smart-ad0edec2-510f-4cb6-806d-482910c44fb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241908204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3241908204
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.76612260
Short name T151
Test name
Test status
Simulation time 1242639227 ps
CPU time 11.37 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 210960 kb
Host smart-f4e76d13-62d1-48d5-b2b2-74316a598ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76612260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.76612260
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.393489801
Short name T176
Test name
Test status
Simulation time 13647939680 ps
CPU time 165.85 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:47:51 PM PDT 24
Peak memory 233420 kb
Host smart-ca6cb2e3-ce65-4c06-8c37-1d0dec3ddeb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393489801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.393489801
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2035285833
Short name T263
Test name
Test status
Simulation time 687841831 ps
CPU time 13.91 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:45:29 PM PDT 24
Peak memory 211688 kb
Host smart-cb90e4ce-934e-4ce5-96a4-2ba283e866c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035285833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2035285833
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2756045126
Short name T293
Test name
Test status
Simulation time 97794279 ps
CPU time 5.45 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:31 PM PDT 24
Peak memory 211100 kb
Host smart-e6bdd121-3e76-40d4-8e72-cb0dfca10d8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2756045126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2756045126
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.39790838
Short name T299
Test name
Test status
Simulation time 10624410667 ps
CPU time 28.46 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:54 PM PDT 24
Peak memory 214016 kb
Host smart-208286ad-93e0-496b-8ab7-1479ec4219f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39790838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.39790838
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.409533340
Short name T173
Test name
Test status
Simulation time 8099874421 ps
CPU time 18.16 seconds
Started Jun 23 04:45:16 PM PDT 24
Finished Jun 23 04:45:34 PM PDT 24
Peak memory 212180 kb
Host smart-2cda26a0-8ab7-4bae-824c-62d4eb8e7319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409533340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.409533340
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.849226656
Short name T329
Test name
Test status
Simulation time 1012807155 ps
CPU time 10.71 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:35 PM PDT 24
Peak memory 210964 kb
Host smart-c4daba6d-8d8b-4235-bffc-bbd11324f34a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849226656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.849226656
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3991180360
Short name T240
Test name
Test status
Simulation time 7556128695 ps
CPU time 93.76 seconds
Started Jun 23 04:45:21 PM PDT 24
Finished Jun 23 04:46:56 PM PDT 24
Peak memory 212836 kb
Host smart-d6594ec5-48ac-438d-97ad-d69cfabcb443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991180360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3991180360
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1440628738
Short name T223
Test name
Test status
Simulation time 51643079225 ps
CPU time 32.01 seconds
Started Jun 23 04:45:18 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 212012 kb
Host smart-396c7fda-2405-4316-810a-47d410991806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440628738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1440628738
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3349225768
Short name T245
Test name
Test status
Simulation time 4989297150 ps
CPU time 12.92 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:38 PM PDT 24
Peak memory 211184 kb
Host smart-7614a2a4-95cd-4a4d-b3f8-694294a2d952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349225768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3349225768
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1177560527
Short name T348
Test name
Test status
Simulation time 7880440143 ps
CPU time 21.9 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:45:43 PM PDT 24
Peak memory 213932 kb
Host smart-042ae9e6-ffdb-4791-9650-bc18e91acad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177560527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1177560527
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4113779634
Short name T177
Test name
Test status
Simulation time 14802776851 ps
CPU time 46.24 seconds
Started Jun 23 04:45:19 PM PDT 24
Finished Jun 23 04:46:06 PM PDT 24
Peak memory 216844 kb
Host smart-00907598-6856-4e58-89ba-de6e4631f632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113779634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4113779634
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3912725687
Short name T1
Test name
Test status
Simulation time 2028211665 ps
CPU time 15.82 seconds
Started Jun 23 04:45:19 PM PDT 24
Finished Jun 23 04:45:35 PM PDT 24
Peak memory 210964 kb
Host smart-4aa5cc71-0717-4019-a6d2-d59957232f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912725687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3912725687
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2606099990
Short name T225
Test name
Test status
Simulation time 10124274156 ps
CPU time 160.35 seconds
Started Jun 23 04:45:39 PM PDT 24
Finished Jun 23 04:48:20 PM PDT 24
Peak memory 233404 kb
Host smart-47bc27d8-f885-45b1-90d2-83dc061f3c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606099990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2606099990
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3354137511
Short name T281
Test name
Test status
Simulation time 3404360106 ps
CPU time 28.39 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:52 PM PDT 24
Peak memory 211784 kb
Host smart-fa00a93b-0652-4f42-98f9-b1a751f8dfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354137511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3354137511
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2319685496
Short name T195
Test name
Test status
Simulation time 1207534266 ps
CPU time 12.62 seconds
Started Jun 23 04:45:19 PM PDT 24
Finished Jun 23 04:45:32 PM PDT 24
Peak memory 211120 kb
Host smart-d80baef3-132a-47c2-bc53-7defc3e7d3d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319685496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2319685496
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1520620519
Short name T187
Test name
Test status
Simulation time 1406793194 ps
CPU time 16.5 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:25 PM PDT 24
Peak memory 211800 kb
Host smart-e2d53f94-834d-4f26-a31c-07a782d7a833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520620519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1520620519
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.113957662
Short name T155
Test name
Test status
Simulation time 3977264273 ps
CPU time 15.45 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:45:41 PM PDT 24
Peak memory 211028 kb
Host smart-ee1173ad-847a-4d87-917b-79436393c39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113957662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.113957662
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.785803113
Short name T246
Test name
Test status
Simulation time 342935667353 ps
CPU time 575.87 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:55:01 PM PDT 24
Peak memory 233384 kb
Host smart-9fbce0ef-9a48-4f19-a511-81e6c456ffd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785803113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.785803113
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.513776141
Short name T229
Test name
Test status
Simulation time 2889309510 ps
CPU time 26.72 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:45:47 PM PDT 24
Peak memory 211656 kb
Host smart-af3fda68-2c52-40c6-a9cb-6dc742b8872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513776141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.513776141
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3083482158
Short name T304
Test name
Test status
Simulation time 7873073320 ps
CPU time 15.78 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:45:45 PM PDT 24
Peak memory 211184 kb
Host smart-14f1aa5a-b0e7-4d67-a5dd-f305a98106bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083482158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3083482158
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.386535255
Short name T256
Test name
Test status
Simulation time 14467710558 ps
CPU time 29.94 seconds
Started Jun 23 04:45:18 PM PDT 24
Finished Jun 23 04:45:48 PM PDT 24
Peak memory 213896 kb
Host smart-dc5896d6-8a44-4ef4-b11f-a83863aa70c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386535255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.386535255
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.480609067
Short name T224
Test name
Test status
Simulation time 3817892815 ps
CPU time 20.8 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:45:56 PM PDT 24
Peak memory 212024 kb
Host smart-113670f9-bbfb-4dd7-a3e2-d5d863db5bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480609067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.480609067
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2971109429
Short name T194
Test name
Test status
Simulation time 4903514805 ps
CPU time 12.02 seconds
Started Jun 23 04:45:33 PM PDT 24
Finished Jun 23 04:45:46 PM PDT 24
Peak memory 211028 kb
Host smart-84abc6b0-1bcb-462a-b128-69e2fb4df1b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971109429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2971109429
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1373123946
Short name T178
Test name
Test status
Simulation time 18452729597 ps
CPU time 233.88 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:49:23 PM PDT 24
Peak memory 237564 kb
Host smart-26686491-081f-4ab6-a0e4-b7bd7f8a6f0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373123946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1373123946
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.862042585
Short name T219
Test name
Test status
Simulation time 408556900 ps
CPU time 8.5 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:45:34 PM PDT 24
Peak memory 211120 kb
Host smart-ca5290d4-7a1e-4fd5-bd47-887f37101755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862042585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.862042585
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1564213601
Short name T220
Test name
Test status
Simulation time 1669956685 ps
CPU time 15.15 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 213404 kb
Host smart-ad1ae94b-9471-4c51-828c-43d47bd284e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564213601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1564213601
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2782799836
Short name T236
Test name
Test status
Simulation time 11727920202 ps
CPU time 109.47 seconds
Started Jun 23 04:45:36 PM PDT 24
Finished Jun 23 04:47:26 PM PDT 24
Peak memory 219152 kb
Host smart-088e98e3-1c5d-4f75-b2f2-bf3819bda837
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782799836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2782799836
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.54773363
Short name T312
Test name
Test status
Simulation time 926481798 ps
CPU time 9.44 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:35 PM PDT 24
Peak memory 210944 kb
Host smart-c8ca49da-293e-4575-b433-7c351b884e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54773363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.54773363
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.450473523
Short name T339
Test name
Test status
Simulation time 24126065315 ps
CPU time 242.32 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:49:39 PM PDT 24
Peak memory 232600 kb
Host smart-8019fe1a-471b-437e-aabe-ce218848144c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450473523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.450473523
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2411808479
Short name T325
Test name
Test status
Simulation time 3446522926 ps
CPU time 20.45 seconds
Started Jun 23 04:45:15 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 211648 kb
Host smart-0d6f6513-202a-43bb-9b30-eeb5d6d34788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411808479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2411808479
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.563977035
Short name T168
Test name
Test status
Simulation time 1542006231 ps
CPU time 6.8 seconds
Started Jun 23 04:45:30 PM PDT 24
Finished Jun 23 04:45:38 PM PDT 24
Peak memory 211108 kb
Host smart-0d08b2b3-15c8-4086-9595-26c457d84f7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563977035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.563977035
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2216135399
Short name T327
Test name
Test status
Simulation time 188820415 ps
CPU time 10.3 seconds
Started Jun 23 04:45:33 PM PDT 24
Finished Jun 23 04:45:44 PM PDT 24
Peak memory 213680 kb
Host smart-7c8beb5b-a864-4e28-a27d-37040818ded0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216135399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2216135399
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.199062700
Short name T278
Test name
Test status
Simulation time 2354175818 ps
CPU time 40.12 seconds
Started Jun 23 04:45:19 PM PDT 24
Finished Jun 23 04:45:59 PM PDT 24
Peak memory 215000 kb
Host smart-71739e3a-ba4b-47bc-acc5-3c6fd4430555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199062700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.199062700
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1529614730
Short name T175
Test name
Test status
Simulation time 4929226857 ps
CPU time 12.11 seconds
Started Jun 23 04:45:18 PM PDT 24
Finished Jun 23 04:45:30 PM PDT 24
Peak memory 211028 kb
Host smart-c979b3af-6114-43b1-8b7b-e15fbe2fa914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529614730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1529614730
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3253344467
Short name T341
Test name
Test status
Simulation time 79149264780 ps
CPU time 371.09 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:51:37 PM PDT 24
Peak memory 228116 kb
Host smart-aa879658-15dc-429e-8261-39482db42af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253344467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3253344467
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2206354028
Short name T46
Test name
Test status
Simulation time 341325291 ps
CPU time 9.51 seconds
Started Jun 23 04:45:25 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 212192 kb
Host smart-c8a6c760-0ec2-4f16-b7c9-57c3353dc506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206354028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2206354028
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4049370223
Short name T160
Test name
Test status
Simulation time 96314272 ps
CPU time 5.57 seconds
Started Jun 23 04:45:27 PM PDT 24
Finished Jun 23 04:45:33 PM PDT 24
Peak memory 211120 kb
Host smart-ae62d1b1-50e5-4dbe-8bd4-560fc2823b1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4049370223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4049370223
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.4276483339
Short name T360
Test name
Test status
Simulation time 416638510 ps
CPU time 10.58 seconds
Started Jun 23 04:45:34 PM PDT 24
Finished Jun 23 04:45:45 PM PDT 24
Peak memory 213348 kb
Host smart-f8a3ec9f-22ad-49e6-97d5-577088dd7408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276483339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.4276483339
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.319993482
Short name T131
Test name
Test status
Simulation time 2509667239 ps
CPU time 10.78 seconds
Started Jun 23 04:45:42 PM PDT 24
Finished Jun 23 04:45:54 PM PDT 24
Peak memory 211112 kb
Host smart-f70f7f32-88cf-486f-97af-ba07f0287643
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319993482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.319993482
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.170753083
Short name T50
Test name
Test status
Simulation time 234628168281 ps
CPU time 2336.65 seconds
Started Jun 23 04:45:47 PM PDT 24
Finished Jun 23 05:24:44 PM PDT 24
Peak memory 243868 kb
Host smart-50a29fe7-875d-46c6-8761-f5b0803449e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170753083 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.170753083
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.610807634
Short name T215
Test name
Test status
Simulation time 6186583811 ps
CPU time 13.14 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:45:34 PM PDT 24
Peak memory 211024 kb
Host smart-214986ef-5d2e-40e6-a082-a0e7bfa628cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610807634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.610807634
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3120737979
Short name T333
Test name
Test status
Simulation time 7564255478 ps
CPU time 135.84 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:47:36 PM PDT 24
Peak memory 237476 kb
Host smart-abdb2840-e7c3-4127-b7d2-98651ecd9f1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120737979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3120737979
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4233680308
Short name T356
Test name
Test status
Simulation time 925424843 ps
CPU time 15.69 seconds
Started Jun 23 04:45:21 PM PDT 24
Finished Jun 23 04:45:38 PM PDT 24
Peak memory 211752 kb
Host smart-9640f310-5ee1-4477-983d-4fc40fa89a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233680308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4233680308
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3884525968
Short name T208
Test name
Test status
Simulation time 8189993397 ps
CPU time 11.42 seconds
Started Jun 23 04:45:26 PM PDT 24
Finished Jun 23 04:45:38 PM PDT 24
Peak memory 211184 kb
Host smart-b0c0f7b2-ca33-4d05-b0fd-7c8fec7c3bf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884525968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3884525968
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.568126494
Short name T337
Test name
Test status
Simulation time 3642245230 ps
CPU time 14.31 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:40 PM PDT 24
Peak memory 213980 kb
Host smart-b571e71e-3f1b-42ec-8c4e-fe50c4f09912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568126494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.568126494
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.943254282
Short name T296
Test name
Test status
Simulation time 17833263094 ps
CPU time 41.11 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:46:11 PM PDT 24
Peak memory 216436 kb
Host smart-84ce63f3-8df7-4918-bfde-56cd628f7f67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943254282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.943254282
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3303831268
Short name T291
Test name
Test status
Simulation time 489248496 ps
CPU time 4.3 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:03 PM PDT 24
Peak memory 210964 kb
Host smart-6d5884e1-15b3-4f33-935e-107445ad4a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303831268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3303831268
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.876491728
Short name T36
Test name
Test status
Simulation time 28047751278 ps
CPU time 132.61 seconds
Started Jun 23 04:45:15 PM PDT 24
Finished Jun 23 04:47:29 PM PDT 24
Peak memory 238624 kb
Host smart-64ca1047-39dd-4e88-b537-1a605e5b2aca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876491728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.876491728
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4217728876
Short name T209
Test name
Test status
Simulation time 666200541 ps
CPU time 9.57 seconds
Started Jun 23 04:45:18 PM PDT 24
Finished Jun 23 04:45:28 PM PDT 24
Peak memory 211688 kb
Host smart-d5ed10a4-4177-4160-abe2-07fa43db3b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217728876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4217728876
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2325750311
Short name T282
Test name
Test status
Simulation time 313937786 ps
CPU time 7.54 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 211112 kb
Host smart-7278b453-384b-44e1-9ded-012a1e888259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325750311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2325750311
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1626379804
Short name T18
Test name
Test status
Simulation time 3986631672 ps
CPU time 58.08 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:46:00 PM PDT 24
Peak memory 236120 kb
Host smart-b713601d-4090-4dcc-a017-224c13259e2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626379804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1626379804
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.819313322
Short name T206
Test name
Test status
Simulation time 3433286784 ps
CPU time 20.12 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:17 PM PDT 24
Peak memory 213248 kb
Host smart-e41a0fab-6ae5-4001-8e73-cf08da6c9a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819313322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.819313322
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3838891422
Short name T213
Test name
Test status
Simulation time 10377139820 ps
CPU time 76.87 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:46:26 PM PDT 24
Peak memory 216592 kb
Host smart-3f750c53-8a59-49a1-9fe2-6da795a18625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838891422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3838891422
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1697141903
Short name T10
Test name
Test status
Simulation time 1831821012 ps
CPU time 14.47 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 04:45:43 PM PDT 24
Peak memory 210964 kb
Host smart-48691e08-5edb-45e2-9464-08f2b8af5f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697141903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1697141903
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3274706674
Short name T126
Test name
Test status
Simulation time 210980245710 ps
CPU time 272.73 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:50:06 PM PDT 24
Peak memory 212376 kb
Host smart-90841d96-dfb0-4a47-92a4-aa7b43ae2a63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274706674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3274706674
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.733223117
Short name T343
Test name
Test status
Simulation time 12645507966 ps
CPU time 26.82 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 212052 kb
Host smart-cfb543a6-3a72-418b-93ce-120d5633e3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733223117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.733223117
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.28500577
Short name T139
Test name
Test status
Simulation time 9358564770 ps
CPU time 12.86 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:37 PM PDT 24
Peak memory 211168 kb
Host smart-780b71c5-6651-41d6-bfdb-3d10919a156c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28500577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.28500577
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2652599518
Short name T27
Test name
Test status
Simulation time 716976169 ps
CPU time 9.95 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:45:43 PM PDT 24
Peak memory 213540 kb
Host smart-c5e35f48-038c-4fe1-a00b-2e09a8357767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652599518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2652599518
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.58845548
Short name T260
Test name
Test status
Simulation time 10532580100 ps
CPU time 43.37 seconds
Started Jun 23 04:45:26 PM PDT 24
Finished Jun 23 04:46:15 PM PDT 24
Peak memory 216844 kb
Host smart-f5a3848c-d013-47e6-9e16-f402b97a0cf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58845548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 30.rom_ctrl_stress_all.58845548
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1161185721
Short name T283
Test name
Test status
Simulation time 133155682 ps
CPU time 5.09 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:45:26 PM PDT 24
Peak memory 211044 kb
Host smart-c25faba3-6769-4a40-932b-66f98a6e1746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161185721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1161185721
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2262361016
Short name T284
Test name
Test status
Simulation time 21220068930 ps
CPU time 214.16 seconds
Started Jun 23 04:45:26 PM PDT 24
Finished Jun 23 04:49:01 PM PDT 24
Peak memory 233400 kb
Host smart-5ca435df-ae2d-4c7e-b4eb-7bbb62b33dd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262361016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2262361016
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2377600918
Short name T262
Test name
Test status
Simulation time 6375564513 ps
CPU time 28.43 seconds
Started Jun 23 04:45:27 PM PDT 24
Finished Jun 23 04:45:56 PM PDT 24
Peak memory 212312 kb
Host smart-a350bbce-c6fb-4734-8ad7-8133d7e4350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377600918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2377600918
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2790087953
Short name T279
Test name
Test status
Simulation time 4290545960 ps
CPU time 10.97 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 211184 kb
Host smart-1b7aa232-0145-46f5-aa2a-48e418383ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790087953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2790087953
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3218139735
Short name T265
Test name
Test status
Simulation time 3090295705 ps
CPU time 16.36 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:45:52 PM PDT 24
Peak memory 212884 kb
Host smart-ef393bf5-c48b-4502-b34e-f6ce3e29b9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218139735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3218139735
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1748169025
Short name T254
Test name
Test status
Simulation time 1115238840 ps
CPU time 17.94 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 213140 kb
Host smart-8b96ca00-ec4e-4ee9-8b5f-82d7090a58a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748169025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1748169025
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1525308282
Short name T308
Test name
Test status
Simulation time 3002459316 ps
CPU time 13.29 seconds
Started Jun 23 04:45:37 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 211016 kb
Host smart-34ff5d0f-4dcb-4e3f-b839-61fb2acf5a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525308282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1525308282
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1229146409
Short name T211
Test name
Test status
Simulation time 14693346079 ps
CPU time 200.29 seconds
Started Jun 23 04:45:38 PM PDT 24
Finished Jun 23 04:48:58 PM PDT 24
Peak memory 236968 kb
Host smart-dae10ef3-5418-4be4-a7a3-17eb1d0103f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229146409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1229146409
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1925267480
Short name T170
Test name
Test status
Simulation time 1308896338 ps
CPU time 18.04 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:45:39 PM PDT 24
Peak memory 211768 kb
Host smart-78c08e8e-560f-4bb4-95ff-d04697eb9d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925267480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1925267480
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1144448091
Short name T253
Test name
Test status
Simulation time 1877957472 ps
CPU time 15.22 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 211112 kb
Host smart-2a194ec2-865b-4ffb-b1d7-d8b539d54274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144448091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1144448091
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1786658091
Short name T326
Test name
Test status
Simulation time 1103754171 ps
CPU time 11.93 seconds
Started Jun 23 04:45:25 PM PDT 24
Finished Jun 23 04:45:38 PM PDT 24
Peak memory 212284 kb
Host smart-1c403e0b-8e71-401b-b43a-d5791ab6772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786658091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1786658091
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1771148373
Short name T165
Test name
Test status
Simulation time 8754610023 ps
CPU time 17.15 seconds
Started Jun 23 04:45:21 PM PDT 24
Finished Jun 23 04:45:39 PM PDT 24
Peak memory 211876 kb
Host smart-2aaa5f17-68d2-47ab-89f9-12bc2d0ca6fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771148373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1771148373
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3238661857
Short name T9
Test name
Test status
Simulation time 2146767318 ps
CPU time 16.78 seconds
Started Jun 23 04:45:42 PM PDT 24
Finished Jun 23 04:46:00 PM PDT 24
Peak memory 211072 kb
Host smart-668017e1-4459-4583-bc4a-9fbf6206f468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238661857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3238661857
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1883093632
Short name T317
Test name
Test status
Simulation time 21439244303 ps
CPU time 243.12 seconds
Started Jun 23 04:45:20 PM PDT 24
Finished Jun 23 04:49:24 PM PDT 24
Peak memory 236956 kb
Host smart-336d187c-2290-48e0-b7fd-c812357ba888
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883093632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1883093632
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1323608662
Short name T255
Test name
Test status
Simulation time 12626624955 ps
CPU time 27.76 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 04:45:57 PM PDT 24
Peak memory 211096 kb
Host smart-29c4b2c7-9ab3-4cc4-a979-be8d32dbeb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323608662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1323608662
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.580147593
Short name T174
Test name
Test status
Simulation time 368865332 ps
CPU time 5.45 seconds
Started Jun 23 04:45:30 PM PDT 24
Finished Jun 23 04:45:37 PM PDT 24
Peak memory 211228 kb
Host smart-bb558142-dc04-4d7a-a121-e5ff88119a6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580147593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.580147593
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.71044488
Short name T267
Test name
Test status
Simulation time 2379017163 ps
CPU time 24.49 seconds
Started Jun 23 04:45:30 PM PDT 24
Finished Jun 23 04:45:55 PM PDT 24
Peak memory 211744 kb
Host smart-3cd9c704-2ef6-4d78-90b1-8df5153cc337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71044488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.71044488
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.521931618
Short name T287
Test name
Test status
Simulation time 6265664048 ps
CPU time 64.52 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:46:28 PM PDT 24
Peak memory 216752 kb
Host smart-ec1b93af-8b92-4120-9c74-aaee30765290
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521931618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.521931618
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.640770256
Short name T340
Test name
Test status
Simulation time 5274860351 ps
CPU time 11.94 seconds
Started Jun 23 04:45:25 PM PDT 24
Finished Jun 23 04:45:38 PM PDT 24
Peak memory 211256 kb
Host smart-614de673-7feb-4463-880d-ad3854204eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640770256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.640770256
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2786503751
Short name T186
Test name
Test status
Simulation time 19205935506 ps
CPU time 191.58 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:48:37 PM PDT 24
Peak memory 236404 kb
Host smart-7a03fb38-3d6a-4138-a71d-f480d3562a72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786503751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2786503751
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1788355601
Short name T251
Test name
Test status
Simulation time 667203310 ps
CPU time 9.42 seconds
Started Jun 23 04:45:26 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 211696 kb
Host smart-29c63e9f-f541-4009-938b-e58e560fa43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788355601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1788355601
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1536286811
Short name T34
Test name
Test status
Simulation time 184001288 ps
CPU time 5.49 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:45:39 PM PDT 24
Peak memory 211228 kb
Host smart-97f7efd4-edf8-4067-89ad-ca4c1b5e5e74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536286811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1536286811
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1608363704
Short name T237
Test name
Test status
Simulation time 3441770151 ps
CPU time 22.31 seconds
Started Jun 23 04:45:38 PM PDT 24
Finished Jun 23 04:46:01 PM PDT 24
Peak memory 213400 kb
Host smart-37053a28-dc0a-4869-b6a1-c7011dd170a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608363704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1608363704
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.774472402
Short name T84
Test name
Test status
Simulation time 3566547961 ps
CPU time 21.49 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 04:45:50 PM PDT 24
Peak memory 213476 kb
Host smart-a28e38d5-2501-418e-8609-1c6a64e88e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774472402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.774472402
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1890883921
Short name T54
Test name
Test status
Simulation time 119746052447 ps
CPU time 2088.29 seconds
Started Jun 23 04:45:31 PM PDT 24
Finished Jun 23 05:20:21 PM PDT 24
Peak memory 235624 kb
Host smart-fc0518ea-e264-451c-beb3-f4d0e7f674d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890883921 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1890883921
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2227491560
Short name T138
Test name
Test status
Simulation time 1474203272 ps
CPU time 13.18 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:39 PM PDT 24
Peak memory 211316 kb
Host smart-79fcebd2-c3b2-4c9f-88fe-070833efb4e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227491560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2227491560
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2847400239
Short name T362
Test name
Test status
Simulation time 1015567051 ps
CPU time 55.34 seconds
Started Jun 23 04:45:52 PM PDT 24
Finished Jun 23 04:46:48 PM PDT 24
Peak memory 227664 kb
Host smart-0533a5d0-ca88-492f-9784-9089462f43e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847400239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2847400239
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.73378153
Short name T331
Test name
Test status
Simulation time 23526257332 ps
CPU time 32.05 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:45:57 PM PDT 24
Peak memory 211996 kb
Host smart-fd31e995-e53e-431a-88dd-d2a8c55f3e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73378153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.73378153
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2592358202
Short name T314
Test name
Test status
Simulation time 196542026 ps
CPU time 5.36 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 04:45:33 PM PDT 24
Peak memory 211200 kb
Host smart-e9818589-66b4-4a24-8699-b362ee7d3582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2592358202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2592358202
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2326786773
Short name T181
Test name
Test status
Simulation time 4541612095 ps
CPU time 22.75 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:45:52 PM PDT 24
Peak memory 213064 kb
Host smart-7fdec274-1e96-4fd0-b652-ef535c7fad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326786773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2326786773
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3635463801
Short name T191
Test name
Test status
Simulation time 14354057037 ps
CPU time 64.8 seconds
Started Jun 23 04:45:48 PM PDT 24
Finished Jun 23 04:46:54 PM PDT 24
Peak memory 217204 kb
Host smart-ef7227e5-2a0e-4ec8-b711-b0922ddb5da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635463801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3635463801
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.685180253
Short name T137
Test name
Test status
Simulation time 169656669 ps
CPU time 5.53 seconds
Started Jun 23 04:45:37 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 210964 kb
Host smart-307202ba-df92-4ca9-9a3e-8da6f96f5352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685180253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.685180253
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.407231330
Short name T268
Test name
Test status
Simulation time 65831672636 ps
CPU time 249.1 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:49:34 PM PDT 24
Peak memory 212504 kb
Host smart-ffe35bb5-a281-4c50-91eb-25c979cc0e33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407231330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.407231330
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3336188234
Short name T32
Test name
Test status
Simulation time 14913652634 ps
CPU time 31.27 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:55 PM PDT 24
Peak memory 212028 kb
Host smart-466a2c5e-c061-41af-ab7c-f744fa6729a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336188234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3336188234
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1715583171
Short name T189
Test name
Test status
Simulation time 278844363 ps
CPU time 6.73 seconds
Started Jun 23 04:45:39 PM PDT 24
Finished Jun 23 04:45:47 PM PDT 24
Peak memory 211116 kb
Host smart-ac217955-ffaf-463d-9120-124546a98b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715583171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1715583171
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1545012196
Short name T243
Test name
Test status
Simulation time 8554049505 ps
CPU time 43.78 seconds
Started Jun 23 04:45:30 PM PDT 24
Finished Jun 23 04:46:15 PM PDT 24
Peak memory 213164 kb
Host smart-f40146d6-f2af-4043-a6cc-fed6c3745731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545012196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1545012196
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.157816841
Short name T87
Test name
Test status
Simulation time 5100500445 ps
CPU time 40.02 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:46:06 PM PDT 24
Peak memory 217652 kb
Host smart-007040ef-0439-45b6-8318-b9ab89135e94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157816841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.157816841
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2254085465
Short name T29
Test name
Test status
Simulation time 1338049740 ps
CPU time 8.4 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 04:45:37 PM PDT 24
Peak memory 210964 kb
Host smart-5c5a920e-d327-46a3-984e-dad959bb0a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254085465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2254085465
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1809976841
Short name T359
Test name
Test status
Simulation time 20909773285 ps
CPU time 138.09 seconds
Started Jun 23 04:45:33 PM PDT 24
Finished Jun 23 04:47:52 PM PDT 24
Peak memory 235040 kb
Host smart-73d5afa4-8138-4668-bcc6-802dcd113f63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809976841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1809976841
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3020317016
Short name T150
Test name
Test status
Simulation time 1637984504 ps
CPU time 18.29 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:45:54 PM PDT 24
Peak memory 211876 kb
Host smart-ec43f111-621d-4972-85c6-96dfcf05e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020317016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3020317016
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2100488828
Short name T172
Test name
Test status
Simulation time 11524047681 ps
CPU time 15.63 seconds
Started Jun 23 04:45:52 PM PDT 24
Finished Jun 23 04:46:09 PM PDT 24
Peak memory 211144 kb
Host smart-47e477bd-2142-4e8a-9908-bc6de1bed3e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100488828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2100488828
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3847567307
Short name T353
Test name
Test status
Simulation time 220720994 ps
CPU time 10.52 seconds
Started Jun 23 04:45:34 PM PDT 24
Finished Jun 23 04:45:46 PM PDT 24
Peak memory 213720 kb
Host smart-b6cc1db2-f4fe-4fea-9d7e-468d72da3692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847567307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3847567307
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.478454308
Short name T42
Test name
Test status
Simulation time 16788838649 ps
CPU time 90.95 seconds
Started Jun 23 04:45:47 PM PDT 24
Finished Jun 23 04:47:18 PM PDT 24
Peak memory 217332 kb
Host smart-87347f36-0381-49e1-b9bf-d3e1120df8f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478454308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.478454308
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.36924798
Short name T216
Test name
Test status
Simulation time 171163502 ps
CPU time 5.45 seconds
Started Jun 23 04:45:37 PM PDT 24
Finished Jun 23 04:45:43 PM PDT 24
Peak memory 210956 kb
Host smart-e5b315c2-58af-4e8c-8d69-5e45ce587957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36924798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.36924798
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1416147042
Short name T188
Test name
Test status
Simulation time 28655912415 ps
CPU time 192.2 seconds
Started Jun 23 04:45:26 PM PDT 24
Finished Jun 23 04:48:39 PM PDT 24
Peak memory 225432 kb
Host smart-59bd3c7b-b71e-4a9f-8d7a-799374027bf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416147042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1416147042
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2820929978
Short name T129
Test name
Test status
Simulation time 581115944 ps
CPU time 13.97 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:45:44 PM PDT 24
Peak memory 211684 kb
Host smart-a6b75109-9d48-4fa3-b80e-91756f896b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820929978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2820929978
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2115414274
Short name T133
Test name
Test status
Simulation time 458459872 ps
CPU time 5.49 seconds
Started Jun 23 04:45:31 PM PDT 24
Finished Jun 23 04:45:37 PM PDT 24
Peak memory 211120 kb
Host smart-6ea79423-d13f-4319-98a5-6fed4eb3e38f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115414274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2115414274
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2088038168
Short name T242
Test name
Test status
Simulation time 4941139359 ps
CPU time 19.55 seconds
Started Jun 23 04:45:37 PM PDT 24
Finished Jun 23 04:45:57 PM PDT 24
Peak memory 213836 kb
Host smart-c93076e9-e021-4d3d-8fe2-3fa223787111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088038168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2088038168
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.453123890
Short name T141
Test name
Test status
Simulation time 1028504973 ps
CPU time 19.09 seconds
Started Jun 23 04:45:31 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 213208 kb
Host smart-e29d27e8-eac8-4b79-8fb7-938e10d52808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453123890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.453123890
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.945713324
Short name T351
Test name
Test status
Simulation time 3110764942 ps
CPU time 9.44 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:45:46 PM PDT 24
Peak memory 211128 kb
Host smart-ecfa72ed-ef10-4b96-a7b0-99d086dacb55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945713324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.945713324
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1317196374
Short name T328
Test name
Test status
Simulation time 28337131014 ps
CPU time 144.27 seconds
Started Jun 23 04:45:26 PM PDT 24
Finished Jun 23 04:47:51 PM PDT 24
Peak memory 228352 kb
Host smart-90137d86-9272-4838-afe1-6099ea8c4b9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317196374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1317196374
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.901612887
Short name T366
Test name
Test status
Simulation time 2979098826 ps
CPU time 25.95 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:52 PM PDT 24
Peak memory 211724 kb
Host smart-ea6c3917-3f95-4442-81dd-d428da64ebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901612887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.901612887
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3688660637
Short name T349
Test name
Test status
Simulation time 5886324797 ps
CPU time 13.56 seconds
Started Jun 23 04:45:27 PM PDT 24
Finished Jun 23 04:45:47 PM PDT 24
Peak memory 211184 kb
Host smart-b4517486-8f17-4485-8153-d7beb6064628
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688660637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3688660637
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4035972250
Short name T301
Test name
Test status
Simulation time 580583185 ps
CPU time 10.11 seconds
Started Jun 23 04:45:46 PM PDT 24
Finished Jun 23 04:45:57 PM PDT 24
Peak memory 213448 kb
Host smart-d3039c79-f9da-4641-a53f-d81357219081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035972250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4035972250
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.864410169
Short name T30
Test name
Test status
Simulation time 4656319395 ps
CPU time 17.58 seconds
Started Jun 23 04:45:37 PM PDT 24
Finished Jun 23 04:45:55 PM PDT 24
Peak memory 215052 kb
Host smart-116ae249-533f-4d15-b9bd-97331da7aeeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864410169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.864410169
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1513810731
Short name T55
Test name
Test status
Simulation time 131502512223 ps
CPU time 2163.43 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 235672 kb
Host smart-9f90c3f0-e395-4680-9636-81c40324797d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513810731 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1513810731
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1120191675
Short name T344
Test name
Test status
Simulation time 93241372838 ps
CPU time 232.73 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:48:58 PM PDT 24
Peak memory 236476 kb
Host smart-f1fc6132-e095-4689-80fc-af6dde39170b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120191675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1120191675
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2469929860
Short name T355
Test name
Test status
Simulation time 334102934 ps
CPU time 9.42 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:45:24 PM PDT 24
Peak memory 211696 kb
Host smart-742ed637-08f7-46cc-8eef-dfcc4811e49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469929860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2469929860
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.633545001
Short name T205
Test name
Test status
Simulation time 8493746276 ps
CPU time 16.78 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:20 PM PDT 24
Peak memory 211244 kb
Host smart-792b8941-ac3f-404e-bd9c-1141b95eb0a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633545001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.633545001
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3635990761
Short name T25
Test name
Test status
Simulation time 2788381784 ps
CPU time 107.97 seconds
Started Jun 23 04:44:57 PM PDT 24
Finished Jun 23 04:46:46 PM PDT 24
Peak memory 237400 kb
Host smart-077b095a-1bd9-4cdf-bf64-b9e2e833aa0a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635990761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3635990761
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4058537391
Short name T2
Test name
Test status
Simulation time 4267870708 ps
CPU time 38.24 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:41 PM PDT 24
Peak memory 213184 kb
Host smart-a53f6edc-9142-4194-acbb-62d90014452d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058537391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4058537391
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3456695871
Short name T12
Test name
Test status
Simulation time 2341188816 ps
CPU time 30.02 seconds
Started Jun 23 04:45:06 PM PDT 24
Finished Jun 23 04:45:37 PM PDT 24
Peak memory 213708 kb
Host smart-68b56eab-88e2-4751-bb36-0d3a51b99d08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456695871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3456695871
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.89981861
Short name T70
Test name
Test status
Simulation time 320749800 ps
CPU time 4.4 seconds
Started Jun 23 04:45:30 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 210960 kb
Host smart-cb23a967-f456-4c68-bd0e-5676a4751ab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89981861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.89981861
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.470511673
Short name T316
Test name
Test status
Simulation time 17891919684 ps
CPU time 193.23 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:48:43 PM PDT 24
Peak memory 238196 kb
Host smart-d9cfc3c6-5936-4ead-a5db-8c71a686d51c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470511673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.470511673
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.885691815
Short name T330
Test name
Test status
Simulation time 10482370180 ps
CPU time 26.21 seconds
Started Jun 23 04:45:31 PM PDT 24
Finished Jun 23 04:45:58 PM PDT 24
Peak memory 212092 kb
Host smart-eb5cecad-5457-464a-b7e6-d883f2303d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885691815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.885691815
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2541604871
Short name T128
Test name
Test status
Simulation time 10115077346 ps
CPU time 15.87 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 04:45:45 PM PDT 24
Peak memory 211424 kb
Host smart-848d28d2-607d-4e80-8efa-af3ca80bc16e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2541604871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2541604871
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3525806119
Short name T203
Test name
Test status
Simulation time 7164263087 ps
CPU time 26.24 seconds
Started Jun 23 04:45:30 PM PDT 24
Finished Jun 23 04:45:58 PM PDT 24
Peak memory 214288 kb
Host smart-0dd8218d-af29-4d86-b4ad-135ceb5e53ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525806119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3525806119
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3984509198
Short name T132
Test name
Test status
Simulation time 11597837153 ps
CPU time 15.02 seconds
Started Jun 23 04:45:37 PM PDT 24
Finished Jun 23 04:45:53 PM PDT 24
Peak memory 210992 kb
Host smart-a23e030f-346d-4a61-a33f-3c763bdd0b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984509198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3984509198
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3277412137
Short name T149
Test name
Test status
Simulation time 746232613 ps
CPU time 7.09 seconds
Started Jun 23 04:45:38 PM PDT 24
Finished Jun 23 04:45:46 PM PDT 24
Peak memory 210952 kb
Host smart-443ad054-7fd3-4754-99fc-7452c04fc599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277412137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3277412137
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4222633416
Short name T33
Test name
Test status
Simulation time 80888294824 ps
CPU time 409.21 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:52:19 PM PDT 24
Peak memory 213856 kb
Host smart-a1102eeb-b307-40ee-b9e4-ef170be011e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222633416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4222633416
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.172099748
Short name T257
Test name
Test status
Simulation time 827535550 ps
CPU time 12.56 seconds
Started Jun 23 04:45:22 PM PDT 24
Finished Jun 23 04:45:37 PM PDT 24
Peak memory 212248 kb
Host smart-ac3cb897-d193-4249-84b2-3ed6d2e21dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172099748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.172099748
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3778725894
Short name T182
Test name
Test status
Simulation time 4658486227 ps
CPU time 12.02 seconds
Started Jun 23 04:45:33 PM PDT 24
Finished Jun 23 04:45:46 PM PDT 24
Peak memory 211296 kb
Host smart-4f851185-c4d1-4e2c-8488-171383cb4cb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778725894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3778725894
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1029645067
Short name T297
Test name
Test status
Simulation time 3298910570 ps
CPU time 31.63 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:46:02 PM PDT 24
Peak memory 213260 kb
Host smart-985bdfb8-ffdd-40af-9026-ec5f1629167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029645067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1029645067
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.850533003
Short name T298
Test name
Test status
Simulation time 820172673 ps
CPU time 21.25 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:45:54 PM PDT 24
Peak memory 214892 kb
Host smart-81e08d2b-f0bd-4f2c-8d43-63d286aa3cf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850533003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.850533003
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2965571888
Short name T44
Test name
Test status
Simulation time 190514415930 ps
CPU time 2044.88 seconds
Started Jun 23 04:45:45 PM PDT 24
Finished Jun 23 05:19:51 PM PDT 24
Peak memory 236064 kb
Host smart-4895d423-bcf7-4020-9920-1f80ff336c25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965571888 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2965571888
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.408324357
Short name T73
Test name
Test status
Simulation time 175657498 ps
CPU time 4.34 seconds
Started Jun 23 04:45:49 PM PDT 24
Finished Jun 23 04:45:54 PM PDT 24
Peak memory 211072 kb
Host smart-8d8003b6-5238-4024-b301-0a5a06af09c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408324357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.408324357
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2130639389
Short name T272
Test name
Test status
Simulation time 3404427744 ps
CPU time 10.59 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:45:48 PM PDT 24
Peak memory 211184 kb
Host smart-90df504a-030e-4cf6-92a4-e6d6f8ac45bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2130639389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2130639389
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.819863707
Short name T85
Test name
Test status
Simulation time 8966678920 ps
CPU time 25.28 seconds
Started Jun 23 04:45:30 PM PDT 24
Finished Jun 23 04:45:57 PM PDT 24
Peak memory 213940 kb
Host smart-cfe1e0b3-bec7-47cc-8ddf-5e293853044c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819863707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.819863707
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4238613245
Short name T221
Test name
Test status
Simulation time 629558830 ps
CPU time 16.06 seconds
Started Jun 23 04:45:31 PM PDT 24
Finished Jun 23 04:45:48 PM PDT 24
Peak memory 214848 kb
Host smart-846fc0a1-bc7f-4ce4-aa70-167f11eb50de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238613245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4238613245
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.272809832
Short name T53
Test name
Test status
Simulation time 17254868458 ps
CPU time 3049.12 seconds
Started Jun 23 04:45:30 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 227848 kb
Host smart-f739bd63-2de2-4e87-b92e-9a745c1edcef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272809832 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.272809832
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3764138935
Short name T269
Test name
Test status
Simulation time 8912981497 ps
CPU time 16.7 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:45:46 PM PDT 24
Peak memory 211028 kb
Host smart-c0a602e0-9a74-4e26-9258-1d78e4f6a32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764138935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3764138935
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1428035036
Short name T198
Test name
Test status
Simulation time 5039656360 ps
CPU time 82.36 seconds
Started Jun 23 04:45:40 PM PDT 24
Finished Jun 23 04:47:03 PM PDT 24
Peak memory 228264 kb
Host smart-3e323f0b-756e-4938-8bb4-0ef2dbe6cf39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428035036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1428035036
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.246378235
Short name T300
Test name
Test status
Simulation time 15776035346 ps
CPU time 32.49 seconds
Started Jun 23 04:45:46 PM PDT 24
Finished Jun 23 04:46:19 PM PDT 24
Peak memory 212044 kb
Host smart-1e6d3750-6f11-4a4e-b347-1503baba4204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246378235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.246378235
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.978435951
Short name T319
Test name
Test status
Simulation time 2787972365 ps
CPU time 12.27 seconds
Started Jun 23 04:45:28 PM PDT 24
Finished Jun 23 04:45:41 PM PDT 24
Peak memory 211156 kb
Host smart-cf3ab5ee-8399-4fb2-9a35-ce4828e9d2bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978435951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.978435951
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4110668132
Short name T57
Test name
Test status
Simulation time 6478629105 ps
CPU time 15.73 seconds
Started Jun 23 04:45:40 PM PDT 24
Finished Jun 23 04:45:56 PM PDT 24
Peak memory 212796 kb
Host smart-778ab534-3a7d-4cdb-8408-7571426d3072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110668132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4110668132
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.38148435
Short name T190
Test name
Test status
Simulation time 6143429856 ps
CPU time 54.19 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:46:30 PM PDT 24
Peak memory 215700 kb
Host smart-fc8e520c-6d8c-40a7-976e-95e3d5b418f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38148435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 43.rom_ctrl_stress_all.38148435
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1726664104
Short name T352
Test name
Test status
Simulation time 3998253275 ps
CPU time 16.03 seconds
Started Jun 23 04:45:36 PM PDT 24
Finished Jun 23 04:45:53 PM PDT 24
Peak memory 211380 kb
Host smart-6ed0ccd2-0cfa-4696-971d-eecd75b1bdc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726664104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1726664104
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2159126138
Short name T40
Test name
Test status
Simulation time 603744795668 ps
CPU time 292.06 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 04:50:25 PM PDT 24
Peak memory 237596 kb
Host smart-4ff6c0f8-094c-4769-90f7-d1b258a339a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159126138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2159126138
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3695095968
Short name T47
Test name
Test status
Simulation time 171881569 ps
CPU time 9.74 seconds
Started Jun 23 04:45:31 PM PDT 24
Finished Jun 23 04:45:41 PM PDT 24
Peak memory 212044 kb
Host smart-10a73434-6c0f-47ee-b8aa-61bfc784da07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695095968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3695095968
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1458181103
Short name T156
Test name
Test status
Simulation time 5280956251 ps
CPU time 13.45 seconds
Started Jun 23 04:45:29 PM PDT 24
Finished Jun 23 04:45:43 PM PDT 24
Peak memory 211172 kb
Host smart-43f26b87-480f-4425-a11d-9cdf15304b2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458181103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1458181103
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.589286485
Short name T336
Test name
Test status
Simulation time 3798368828 ps
CPU time 31.3 seconds
Started Jun 23 04:45:55 PM PDT 24
Finished Jun 23 04:46:27 PM PDT 24
Peak memory 213508 kb
Host smart-17d8c9ef-33ee-407e-a6d4-10ddecff7904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589286485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.589286485
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4124941292
Short name T335
Test name
Test status
Simulation time 2947588539 ps
CPU time 49.36 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:46:25 PM PDT 24
Peak memory 216000 kb
Host smart-71510854-1b0a-4709-b76e-c151653dcba8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124941292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4124941292
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1999381571
Short name T321
Test name
Test status
Simulation time 3190322789 ps
CPU time 13.68 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 211004 kb
Host smart-bfb6ac5b-6eae-4b9d-8ea1-9cf1c0a706d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999381571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1999381571
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.91532887
Short name T161
Test name
Test status
Simulation time 18164424860 ps
CPU time 172.28 seconds
Started Jun 23 04:45:36 PM PDT 24
Finished Jun 23 04:48:29 PM PDT 24
Peak memory 235604 kb
Host smart-06257e3b-13b6-4b19-b6e3-1bf522535aec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91532887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_co
rrupt_sig_fatal_chk.91532887
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3261376139
Short name T140
Test name
Test status
Simulation time 3672924557 ps
CPU time 21.8 seconds
Started Jun 23 04:45:30 PM PDT 24
Finished Jun 23 04:45:53 PM PDT 24
Peak memory 211816 kb
Host smart-2c5880c7-94f0-490e-aff0-c607953f96cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261376139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3261376139
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.386774870
Short name T294
Test name
Test status
Simulation time 399582458 ps
CPU time 5.53 seconds
Started Jun 23 04:45:43 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 211220 kb
Host smart-a68062ef-c768-4efa-9810-656e5f1dca17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386774870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.386774870
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4051630466
Short name T241
Test name
Test status
Simulation time 368534151 ps
CPU time 10.49 seconds
Started Jun 23 04:45:38 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 213448 kb
Host smart-faa43dd9-d921-4354-8621-da1b9337cc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051630466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4051630466
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2805341696
Short name T210
Test name
Test status
Simulation time 295382542 ps
CPU time 15.26 seconds
Started Jun 23 04:45:33 PM PDT 24
Finished Jun 23 04:45:49 PM PDT 24
Peak memory 214904 kb
Host smart-78c94976-f0ba-4997-b6a6-c5e1e7304967
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805341696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2805341696
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3973949752
Short name T252
Test name
Test status
Simulation time 8792605878 ps
CPU time 16.06 seconds
Started Jun 23 04:45:38 PM PDT 24
Finished Jun 23 04:45:55 PM PDT 24
Peak memory 211028 kb
Host smart-94cb3c3a-2894-421b-bd22-4d8bb9fe4482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973949752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3973949752
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1914155368
Short name T193
Test name
Test status
Simulation time 65293060261 ps
CPU time 328.24 seconds
Started Jun 23 04:45:55 PM PDT 24
Finished Jun 23 04:51:25 PM PDT 24
Peak memory 236996 kb
Host smart-532e493f-d63f-45f6-8baf-a18fcc679b20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914155368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1914155368
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.167913446
Short name T204
Test name
Test status
Simulation time 7646205213 ps
CPU time 23.26 seconds
Started Jun 23 04:45:40 PM PDT 24
Finished Jun 23 04:46:04 PM PDT 24
Peak memory 212240 kb
Host smart-d075d450-4cdb-4c9f-b4a7-643317415e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167913446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.167913446
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2789653136
Short name T361
Test name
Test status
Simulation time 102693604 ps
CPU time 5.29 seconds
Started Jun 23 04:45:24 PM PDT 24
Finished Jun 23 04:45:31 PM PDT 24
Peak memory 211124 kb
Host smart-92ff7451-b343-41f0-81e1-f06092a78390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789653136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2789653136
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.989684314
Short name T212
Test name
Test status
Simulation time 8877833628 ps
CPU time 25.64 seconds
Started Jun 23 04:45:36 PM PDT 24
Finished Jun 23 04:46:03 PM PDT 24
Peak memory 213808 kb
Host smart-f5d97254-1524-4212-8d72-67614aa4a035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989684314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.989684314
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3834130931
Short name T3
Test name
Test status
Simulation time 906797129 ps
CPU time 26.96 seconds
Started Jun 23 04:45:41 PM PDT 24
Finished Jun 23 04:46:08 PM PDT 24
Peak memory 216524 kb
Host smart-9eefbc4d-7d2a-4bc1-800d-360271fe9d68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834130931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3834130931
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.682993508
Short name T146
Test name
Test status
Simulation time 108672435 ps
CPU time 4.24 seconds
Started Jun 23 04:45:50 PM PDT 24
Finished Jun 23 04:45:56 PM PDT 24
Peak memory 210964 kb
Host smart-9650e162-3243-4b26-9c1c-f55fd2506e71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682993508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.682993508
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2598704078
Short name T347
Test name
Test status
Simulation time 110181631311 ps
CPU time 224.49 seconds
Started Jun 23 04:45:38 PM PDT 24
Finished Jun 23 04:49:23 PM PDT 24
Peak memory 237428 kb
Host smart-808cd2cd-15f1-4bd3-b846-f84cb332db98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598704078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2598704078
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3075003550
Short name T313
Test name
Test status
Simulation time 45436988463 ps
CPU time 31.38 seconds
Started Jun 23 04:45:40 PM PDT 24
Finished Jun 23 04:46:12 PM PDT 24
Peak memory 211980 kb
Host smart-0d6dca29-0332-4166-8920-140deb76152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075003550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3075003550
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3879252314
Short name T290
Test name
Test status
Simulation time 1700567090 ps
CPU time 14.64 seconds
Started Jun 23 04:45:45 PM PDT 24
Finished Jun 23 04:46:00 PM PDT 24
Peak memory 211120 kb
Host smart-85a37cf7-cd4c-4b74-aebe-99b53ba06402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3879252314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3879252314
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3025482065
Short name T365
Test name
Test status
Simulation time 2395076515 ps
CPU time 24.24 seconds
Started Jun 23 04:45:57 PM PDT 24
Finished Jun 23 04:46:23 PM PDT 24
Peak memory 213032 kb
Host smart-7d309d97-78fb-4a1a-91e6-81a067f7ad86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025482065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3025482065
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3778211853
Short name T148
Test name
Test status
Simulation time 13429729231 ps
CPU time 34.93 seconds
Started Jun 23 04:45:47 PM PDT 24
Finished Jun 23 04:46:22 PM PDT 24
Peak memory 216736 kb
Host smart-0b126010-0c4c-4e9e-b9e1-bb4e01556e8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778211853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3778211853
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2927837985
Short name T63
Test name
Test status
Simulation time 8469875735 ps
CPU time 16.77 seconds
Started Jun 23 04:45:26 PM PDT 24
Finished Jun 23 04:45:44 PM PDT 24
Peak memory 211008 kb
Host smart-72f97892-634a-4329-b760-e9a23808fb51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927837985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2927837985
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3115983634
Short name T153
Test name
Test status
Simulation time 789905588 ps
CPU time 55.03 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:46:20 PM PDT 24
Peak memory 237388 kb
Host smart-feb40691-4ee3-414c-abc0-8b9e872e4a86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115983634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3115983634
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3123830073
Short name T338
Test name
Test status
Simulation time 348246405 ps
CPU time 9.61 seconds
Started Jun 23 04:45:34 PM PDT 24
Finished Jun 23 04:45:45 PM PDT 24
Peak memory 211620 kb
Host smart-dd9108ef-d065-404a-911e-0807f1882d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123830073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3123830073
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3265100806
Short name T16
Test name
Test status
Simulation time 2072212330 ps
CPU time 16.74 seconds
Started Jun 23 04:45:45 PM PDT 24
Finished Jun 23 04:46:03 PM PDT 24
Peak memory 211120 kb
Host smart-32682a02-a117-4954-91a1-317bf7091c52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265100806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3265100806
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1516477594
Short name T271
Test name
Test status
Simulation time 7596186929 ps
CPU time 22.08 seconds
Started Jun 23 04:45:39 PM PDT 24
Finished Jun 23 04:46:02 PM PDT 24
Peak memory 213544 kb
Host smart-ac7d8b28-a8c3-4e17-9d01-f51a46ac6aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516477594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1516477594
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2410103463
Short name T302
Test name
Test status
Simulation time 57944192384 ps
CPU time 71.51 seconds
Started Jun 23 04:45:54 PM PDT 24
Finished Jun 23 04:47:07 PM PDT 24
Peak memory 215968 kb
Host smart-aa7870bb-1118-4ad7-9377-93f7739b155a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410103463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2410103463
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3490394560
Short name T217
Test name
Test status
Simulation time 15596435914 ps
CPU time 13.44 seconds
Started Jun 23 04:45:37 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 211028 kb
Host smart-60e41673-343c-4b29-9abe-a48c00b36f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490394560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3490394560
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.296715866
Short name T264
Test name
Test status
Simulation time 2079618529 ps
CPU time 135.05 seconds
Started Jun 23 04:45:40 PM PDT 24
Finished Jun 23 04:47:56 PM PDT 24
Peak memory 236388 kb
Host smart-a5d25d2f-8cd6-48bb-8a2c-4ae7ddb60907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296715866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.296715866
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1051925530
Short name T23
Test name
Test status
Simulation time 3759413913 ps
CPU time 15.9 seconds
Started Jun 23 04:45:54 PM PDT 24
Finished Jun 23 04:46:11 PM PDT 24
Peak memory 211712 kb
Host smart-a7f68034-4ae1-414e-b0c3-501aa6207d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051925530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1051925530
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1234897516
Short name T28
Test name
Test status
Simulation time 797672098 ps
CPU time 10.57 seconds
Started Jun 23 04:45:48 PM PDT 24
Finished Jun 23 04:45:59 PM PDT 24
Peak memory 211120 kb
Host smart-e8189230-0b06-418e-b292-42690cde246b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234897516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1234897516
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2196848086
Short name T322
Test name
Test status
Simulation time 4003698640 ps
CPU time 16.6 seconds
Started Jun 23 04:45:49 PM PDT 24
Finished Jun 23 04:46:06 PM PDT 24
Peak memory 213224 kb
Host smart-f8babe91-3ca9-4abf-80f6-0b37a375686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196848086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2196848086
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3554324370
Short name T318
Test name
Test status
Simulation time 137014713 ps
CPU time 10.66 seconds
Started Jun 23 04:45:42 PM PDT 24
Finished Jun 23 04:45:53 PM PDT 24
Peak memory 210900 kb
Host smart-b792d683-00c3-42be-91d9-a6f80f13c196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554324370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3554324370
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.419568896
Short name T52
Test name
Test status
Simulation time 31469255650 ps
CPU time 6598.66 seconds
Started Jun 23 04:45:32 PM PDT 24
Finished Jun 23 06:35:32 PM PDT 24
Peak memory 235652 kb
Host smart-772eaf69-17c3-4fe1-acf2-1f667bb1f073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419568896 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.419568896
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1812577135
Short name T266
Test name
Test status
Simulation time 3446182557 ps
CPU time 13.53 seconds
Started Jun 23 04:45:04 PM PDT 24
Finished Jun 23 04:45:18 PM PDT 24
Peak memory 211028 kb
Host smart-4e8d17b5-ac5d-4a7c-9abd-c4f4ec5e0c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812577135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1812577135
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3252028053
Short name T192
Test name
Test status
Simulation time 79115522818 ps
CPU time 375.3 seconds
Started Jun 23 04:45:00 PM PDT 24
Finished Jun 23 04:51:16 PM PDT 24
Peak memory 236868 kb
Host smart-d36916b2-4687-4cd5-bb05-012d35864884
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252028053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3252028053
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.585424388
Short name T232
Test name
Test status
Simulation time 693987888 ps
CPU time 9.73 seconds
Started Jun 23 04:44:53 PM PDT 24
Finished Jun 23 04:45:03 PM PDT 24
Peak memory 211876 kb
Host smart-2a632e41-2be6-4ca0-9cf8-a5aaeab8ee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585424388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.585424388
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3193211690
Short name T179
Test name
Test status
Simulation time 4795079509 ps
CPU time 12.03 seconds
Started Jun 23 04:45:15 PM PDT 24
Finished Jun 23 04:45:27 PM PDT 24
Peak memory 211184 kb
Host smart-02a390aa-3323-45e6-aac2-de0ce7cd8ba3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193211690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3193211690
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2238325345
Short name T247
Test name
Test status
Simulation time 9930904911 ps
CPU time 22.35 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:45:37 PM PDT 24
Peak memory 213892 kb
Host smart-19bc9236-b1e0-4046-a348-25f6576cd24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238325345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2238325345
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1944523352
Short name T135
Test name
Test status
Simulation time 312307941 ps
CPU time 17.27 seconds
Started Jun 23 04:45:04 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 212928 kb
Host smart-ed5ef406-b2bd-4e77-a776-7f4a78b988a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944523352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1944523352
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1115873486
Short name T358
Test name
Test status
Simulation time 2956411416 ps
CPU time 8.93 seconds
Started Jun 23 04:45:09 PM PDT 24
Finished Jun 23 04:45:19 PM PDT 24
Peak memory 211028 kb
Host smart-32373ce6-7c35-4861-bfe4-f9abe3db1e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115873486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1115873486
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.365399121
Short name T307
Test name
Test status
Simulation time 39820385717 ps
CPU time 112.54 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:46:54 PM PDT 24
Peak memory 236556 kb
Host smart-d9c8e8bc-873c-4c55-a870-4bba4ade8316
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365399121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.365399121
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3292726949
Short name T35
Test name
Test status
Simulation time 11606435416 ps
CPU time 26.28 seconds
Started Jun 23 04:45:19 PM PDT 24
Finished Jun 23 04:45:46 PM PDT 24
Peak memory 211112 kb
Host smart-cf88cd65-f969-445d-b45e-f6fe6fa455e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292726949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3292726949
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2244454208
Short name T61
Test name
Test status
Simulation time 102776826 ps
CPU time 5.72 seconds
Started Jun 23 04:45:06 PM PDT 24
Finished Jun 23 04:45:13 PM PDT 24
Peak memory 211116 kb
Host smart-8614bc0e-5163-4628-bbf9-a38e1b991a4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244454208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2244454208
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2087467121
Short name T306
Test name
Test status
Simulation time 2129088371 ps
CPU time 22.03 seconds
Started Jun 23 04:45:03 PM PDT 24
Finished Jun 23 04:45:26 PM PDT 24
Peak memory 213096 kb
Host smart-a2c32abc-5191-45e8-8970-723adf1eaa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087467121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2087467121
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.206972262
Short name T134
Test name
Test status
Simulation time 4957207408 ps
CPU time 55.53 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:46:06 PM PDT 24
Peak memory 216792 kb
Host smart-6f165f02-a5fb-4397-b540-06eac012eb2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206972262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.206972262
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2283518226
Short name T310
Test name
Test status
Simulation time 2189995248 ps
CPU time 17.21 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:45:32 PM PDT 24
Peak memory 211020 kb
Host smart-4251f813-a1f6-45f4-8ad8-a501e02106e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283518226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2283518226
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1424805478
Short name T320
Test name
Test status
Simulation time 4122891832 ps
CPU time 128.1 seconds
Started Jun 23 04:45:08 PM PDT 24
Finished Jun 23 04:47:18 PM PDT 24
Peak memory 237800 kb
Host smart-dc5c025e-9c94-4993-92a2-2e53542b6883
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424805478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1424805478
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.732461757
Short name T285
Test name
Test status
Simulation time 5612648499 ps
CPU time 26.77 seconds
Started Jun 23 04:45:23 PM PDT 24
Finished Jun 23 04:45:51 PM PDT 24
Peak memory 212104 kb
Host smart-dfd29624-d94a-476b-b14a-920975c07da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732461757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.732461757
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2292874158
Short name T292
Test name
Test status
Simulation time 194022511 ps
CPU time 5.65 seconds
Started Jun 23 04:45:16 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 211104 kb
Host smart-484f7534-9bc1-4d3b-85ff-9aeebfeb9648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2292874158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2292874158
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2182327008
Short name T214
Test name
Test status
Simulation time 190437837 ps
CPU time 10.19 seconds
Started Jun 23 04:45:11 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 212976 kb
Host smart-c61219bd-8a1f-4e60-845b-3e2cafeabe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182327008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2182327008
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2864253806
Short name T311
Test name
Test status
Simulation time 23732637780 ps
CPU time 50.64 seconds
Started Jun 23 04:45:13 PM PDT 24
Finished Jun 23 04:46:04 PM PDT 24
Peak memory 219168 kb
Host smart-e30ba8cd-4b10-4605-8a84-7e48c7c5500c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864253806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2864253806
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1164452753
Short name T289
Test name
Test status
Simulation time 85452912 ps
CPU time 4.22 seconds
Started Jun 23 04:45:35 PM PDT 24
Finished Jun 23 04:45:40 PM PDT 24
Peak memory 210964 kb
Host smart-bb897c74-0f15-4092-93d4-1458a5beee99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164452753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1164452753
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1149530323
Short name T48
Test name
Test status
Simulation time 31898525443 ps
CPU time 321.4 seconds
Started Jun 23 04:45:13 PM PDT 24
Finished Jun 23 04:50:35 PM PDT 24
Peak memory 237472 kb
Host smart-10202ec6-33b6-4fec-846c-872631f19dc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149530323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1149530323
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4047061692
Short name T167
Test name
Test status
Simulation time 14443751767 ps
CPU time 30.89 seconds
Started Jun 23 04:44:59 PM PDT 24
Finished Jun 23 04:45:30 PM PDT 24
Peak memory 212100 kb
Host smart-d7635229-18ff-4d45-af7f-e52ab0de46d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047061692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4047061692
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2644427180
Short name T259
Test name
Test status
Simulation time 3130481219 ps
CPU time 14.55 seconds
Started Jun 23 04:45:05 PM PDT 24
Finished Jun 23 04:45:21 PM PDT 24
Peak memory 211184 kb
Host smart-be170fb8-1952-45b5-b04f-85e6f703c396
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644427180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2644427180
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4007160150
Short name T305
Test name
Test status
Simulation time 22321422354 ps
CPU time 29.61 seconds
Started Jun 23 04:45:16 PM PDT 24
Finished Jun 23 04:45:46 PM PDT 24
Peak memory 214060 kb
Host smart-186cd718-d868-4916-9fd1-d0fff4332de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007160150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4007160150
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1049731612
Short name T202
Test name
Test status
Simulation time 11775610018 ps
CPU time 88.2 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:46:30 PM PDT 24
Peak memory 216388 kb
Host smart-98cf8a64-bfbe-47bb-a6ab-705e73268c04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049731612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1049731612
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4069498460
Short name T270
Test name
Test status
Simulation time 12296602378 ps
CPU time 15.15 seconds
Started Jun 23 04:45:14 PM PDT 24
Finished Jun 23 04:45:31 PM PDT 24
Peak memory 211256 kb
Host smart-ec22c9e2-d8ba-476e-9191-0fba7ba2e61e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069498460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4069498460
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1774406557
Short name T233
Test name
Test status
Simulation time 68237255286 ps
CPU time 141.08 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:47:30 PM PDT 24
Peak memory 236460 kb
Host smart-ed9635e2-2a73-42a5-bd1f-a8fb446d9cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774406557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1774406557
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3652080823
Short name T59
Test name
Test status
Simulation time 2074160511 ps
CPU time 22.93 seconds
Started Jun 23 04:45:12 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 211616 kb
Host smart-743a9976-549c-488c-94a3-0cc7db8de58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652080823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3652080823
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3770160465
Short name T169
Test name
Test status
Simulation time 389414196 ps
CPU time 5.64 seconds
Started Jun 23 04:45:09 PM PDT 24
Finished Jun 23 04:45:15 PM PDT 24
Peak memory 211104 kb
Host smart-6f79e0f2-1ace-4cb2-9c1d-8d3bfad51f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770160465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3770160465
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2537253138
Short name T303
Test name
Test status
Simulation time 673985575 ps
CPU time 14.5 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:45:26 PM PDT 24
Peak memory 213712 kb
Host smart-149be563-9cb2-4538-85dd-07c8255aa18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537253138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2537253138
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3848922922
Short name T60
Test name
Test status
Simulation time 1999672807 ps
CPU time 25.07 seconds
Started Jun 23 04:45:26 PM PDT 24
Finished Jun 23 04:45:52 PM PDT 24
Peak memory 215408 kb
Host smart-f091bacf-ad1c-4ff6-a073-9f44c5a1d7b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848922922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3848922922
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3128896868
Short name T22
Test name
Test status
Simulation time 23629512222 ps
CPU time 1614.29 seconds
Started Jun 23 04:45:15 PM PDT 24
Finished Jun 23 05:12:11 PM PDT 24
Peak memory 224916 kb
Host smart-4ca17069-4162-4a33-b186-64e6a963f8d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128896868 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3128896868
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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