Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.67 100.00 98.28 97.45 98.37


Total test records in report: 463
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T316 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4054078937 Jun 24 05:29:30 PM PDT 24 Jun 24 05:29:52 PM PDT 24 1758007825 ps
T317 /workspace/coverage/default/9.rom_ctrl_alert_test.894628059 Jun 24 05:29:06 PM PDT 24 Jun 24 05:29:12 PM PDT 24 347967895 ps
T318 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4282147656 Jun 24 05:29:10 PM PDT 24 Jun 24 05:29:26 PM PDT 24 2891554787 ps
T319 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.371544704 Jun 24 05:28:56 PM PDT 24 Jun 24 05:29:10 PM PDT 24 260221147 ps
T320 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3475530767 Jun 24 05:29:40 PM PDT 24 Jun 24 05:33:09 PM PDT 24 21665745633 ps
T321 /workspace/coverage/default/7.rom_ctrl_alert_test.3047874753 Jun 24 05:28:55 PM PDT 24 Jun 24 05:29:11 PM PDT 24 2978275658 ps
T322 /workspace/coverage/default/40.rom_ctrl_alert_test.875297411 Jun 24 05:29:29 PM PDT 24 Jun 24 05:29:48 PM PDT 24 9184085794 ps
T323 /workspace/coverage/default/13.rom_ctrl_stress_all.2011733599 Jun 24 05:29:07 PM PDT 24 Jun 24 05:30:01 PM PDT 24 25758338898 ps
T324 /workspace/coverage/default/12.rom_ctrl_stress_all.4153096682 Jun 24 05:29:10 PM PDT 24 Jun 24 05:29:32 PM PDT 24 17072478503 ps
T325 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3785858090 Jun 24 05:29:11 PM PDT 24 Jun 24 05:29:30 PM PDT 24 2357668921 ps
T326 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1762637415 Jun 24 05:29:08 PM PDT 24 Jun 24 05:29:15 PM PDT 24 1547176721 ps
T327 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1585974542 Jun 24 05:29:35 PM PDT 24 Jun 24 05:29:45 PM PDT 24 347775592 ps
T328 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1207929304 Jun 24 05:29:38 PM PDT 24 Jun 24 05:29:51 PM PDT 24 4102667881 ps
T329 /workspace/coverage/default/2.rom_ctrl_stress_all.1820634267 Jun 24 05:28:55 PM PDT 24 Jun 24 05:29:14 PM PDT 24 2465821378 ps
T330 /workspace/coverage/default/10.rom_ctrl_smoke.2213805220 Jun 24 05:29:06 PM PDT 24 Jun 24 05:29:45 PM PDT 24 4197147765 ps
T331 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3258858828 Jun 24 05:29:05 PM PDT 24 Jun 24 05:29:16 PM PDT 24 976240317 ps
T332 /workspace/coverage/default/44.rom_ctrl_stress_all.2905347083 Jun 24 05:29:32 PM PDT 24 Jun 24 05:30:16 PM PDT 24 24826697141 ps
T333 /workspace/coverage/default/1.rom_ctrl_smoke.444671426 Jun 24 05:28:54 PM PDT 24 Jun 24 05:29:14 PM PDT 24 1321786068 ps
T334 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1416150831 Jun 24 05:29:09 PM PDT 24 Jun 24 05:29:20 PM PDT 24 2070584169 ps
T335 /workspace/coverage/default/28.rom_ctrl_alert_test.1759093494 Jun 24 05:29:19 PM PDT 24 Jun 24 05:29:33 PM PDT 24 4297382112 ps
T336 /workspace/coverage/default/17.rom_ctrl_smoke.4201706953 Jun 24 05:29:16 PM PDT 24 Jun 24 05:29:52 PM PDT 24 3307457122 ps
T337 /workspace/coverage/default/35.rom_ctrl_smoke.1783579347 Jun 24 05:29:32 PM PDT 24 Jun 24 05:30:08 PM PDT 24 23225324074 ps
T338 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1973352136 Jun 24 05:28:41 PM PDT 24 Jun 24 05:28:57 PM PDT 24 9470925250 ps
T339 /workspace/coverage/default/34.rom_ctrl_stress_all.2176760353 Jun 24 05:29:17 PM PDT 24 Jun 24 05:29:37 PM PDT 24 1586780161 ps
T340 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2993642729 Jun 24 05:29:09 PM PDT 24 Jun 24 05:29:27 PM PDT 24 1677292829 ps
T341 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1789715998 Jun 24 05:29:32 PM PDT 24 Jun 24 06:18:33 PM PDT 24 76906131375 ps
T342 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1864700493 Jun 24 05:29:43 PM PDT 24 Jun 24 05:30:06 PM PDT 24 4271120127 ps
T343 /workspace/coverage/default/40.rom_ctrl_stress_all.3609645219 Jun 24 05:29:27 PM PDT 24 Jun 24 05:30:22 PM PDT 24 4809507095 ps
T344 /workspace/coverage/default/14.rom_ctrl_alert_test.2053006360 Jun 24 05:29:10 PM PDT 24 Jun 24 05:29:18 PM PDT 24 346590307 ps
T345 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2871371421 Jun 24 05:29:06 PM PDT 24 Jun 24 05:29:13 PM PDT 24 197043710 ps
T346 /workspace/coverage/default/3.rom_ctrl_alert_test.1032158132 Jun 24 05:29:00 PM PDT 24 Jun 24 05:29:06 PM PDT 24 347910764 ps
T347 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3614496114 Jun 24 05:29:19 PM PDT 24 Jun 24 05:38:30 PM PDT 24 127426228959 ps
T348 /workspace/coverage/default/12.rom_ctrl_alert_test.2267838409 Jun 24 05:29:07 PM PDT 24 Jun 24 05:29:23 PM PDT 24 6850635354 ps
T349 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3536837796 Jun 24 05:29:40 PM PDT 24 Jun 24 05:30:49 PM PDT 24 4073459034 ps
T350 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1156535967 Jun 24 05:29:05 PM PDT 24 Jun 24 05:29:35 PM PDT 24 15535420981 ps
T25 /workspace/coverage/default/0.rom_ctrl_sec_cm.2659251815 Jun 24 05:28:54 PM PDT 24 Jun 24 05:30:47 PM PDT 24 7061821151 ps
T351 /workspace/coverage/default/21.rom_ctrl_stress_all.4187067249 Jun 24 05:29:07 PM PDT 24 Jun 24 05:29:31 PM PDT 24 9444529096 ps
T26 /workspace/coverage/default/1.rom_ctrl_sec_cm.1184770336 Jun 24 05:28:53 PM PDT 24 Jun 24 05:29:57 PM PDT 24 3845854189 ps
T352 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1115028865 Jun 24 05:29:32 PM PDT 24 Jun 24 05:30:08 PM PDT 24 4158617881 ps
T353 /workspace/coverage/default/17.rom_ctrl_alert_test.1736066920 Jun 24 05:29:11 PM PDT 24 Jun 24 05:29:26 PM PDT 24 2708780168 ps
T354 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.994428154 Jun 24 05:28:54 PM PDT 24 Jun 24 05:29:10 PM PDT 24 6773322942 ps
T355 /workspace/coverage/default/27.rom_ctrl_alert_test.1845713053 Jun 24 05:29:18 PM PDT 24 Jun 24 05:29:37 PM PDT 24 1941134002 ps
T356 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.443748981 Jun 24 05:28:54 PM PDT 24 Jun 24 05:30:14 PM PDT 24 29130471321 ps
T357 /workspace/coverage/default/19.rom_ctrl_stress_all.4104540438 Jun 24 05:29:14 PM PDT 24 Jun 24 05:29:34 PM PDT 24 3241246687 ps
T358 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3933641162 Jun 24 05:29:18 PM PDT 24 Jun 24 05:29:32 PM PDT 24 172605001 ps
T359 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3462508917 Jun 24 05:29:11 PM PDT 24 Jun 24 05:33:32 PM PDT 24 456817888181 ps
T97 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1706692283 Jun 24 05:29:12 PM PDT 24 Jun 24 05:29:23 PM PDT 24 227759739 ps
T98 /workspace/coverage/default/25.rom_ctrl_stress_all.3745696271 Jun 24 05:29:13 PM PDT 24 Jun 24 05:29:25 PM PDT 24 518027355 ps
T99 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2645911515 Jun 24 05:28:54 PM PDT 24 Jun 24 05:39:45 PM PDT 24 39852991236 ps
T100 /workspace/coverage/default/15.rom_ctrl_smoke.273370598 Jun 24 05:29:11 PM PDT 24 Jun 24 05:29:26 PM PDT 24 1546978491 ps
T101 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3241253904 Jun 24 05:29:19 PM PDT 24 Jun 24 05:29:38 PM PDT 24 5771024886 ps
T102 /workspace/coverage/default/9.rom_ctrl_smoke.2822539496 Jun 24 05:28:57 PM PDT 24 Jun 24 05:29:25 PM PDT 24 15939102262 ps
T103 /workspace/coverage/default/16.rom_ctrl_alert_test.3559454668 Jun 24 05:29:11 PM PDT 24 Jun 24 05:29:27 PM PDT 24 1325272063 ps
T104 /workspace/coverage/default/13.rom_ctrl_alert_test.3381627185 Jun 24 05:29:10 PM PDT 24 Jun 24 05:29:18 PM PDT 24 91980143 ps
T105 /workspace/coverage/default/37.rom_ctrl_smoke.468872658 Jun 24 05:29:25 PM PDT 24 Jun 24 05:29:44 PM PDT 24 18154979844 ps
T106 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2077827444 Jun 24 05:29:39 PM PDT 24 Jun 24 05:29:50 PM PDT 24 700395404 ps
T360 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.807921682 Jun 24 05:29:22 PM PDT 24 Jun 24 05:32:45 PM PDT 24 114387973320 ps
T361 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2465212449 Jun 24 05:28:54 PM PDT 24 Jun 24 05:29:11 PM PDT 24 1447949625 ps
T362 /workspace/coverage/default/33.rom_ctrl_stress_all.2995365978 Jun 24 05:29:21 PM PDT 24 Jun 24 05:29:55 PM PDT 24 9809103303 ps
T363 /workspace/coverage/default/28.rom_ctrl_smoke.3789904503 Jun 24 05:29:18 PM PDT 24 Jun 24 05:29:31 PM PDT 24 767062007 ps
T364 /workspace/coverage/default/5.rom_ctrl_stress_all.1223857035 Jun 24 05:28:52 PM PDT 24 Jun 24 05:29:06 PM PDT 24 1022680016 ps
T365 /workspace/coverage/default/5.rom_ctrl_smoke.2742381236 Jun 24 05:28:56 PM PDT 24 Jun 24 05:29:32 PM PDT 24 16864419341 ps
T366 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.489351743 Jun 24 05:29:08 PM PDT 24 Jun 24 05:30:10 PM PDT 24 794015182 ps
T367 /workspace/coverage/default/8.rom_ctrl_alert_test.2379332557 Jun 24 05:28:57 PM PDT 24 Jun 24 05:29:12 PM PDT 24 2714367815 ps
T368 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2161993873 Jun 24 05:29:24 PM PDT 24 Jun 24 05:29:31 PM PDT 24 191176631 ps
T369 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.82047818 Jun 24 05:29:08 PM PDT 24 Jun 24 05:31:25 PM PDT 24 15723126845 ps
T370 /workspace/coverage/default/3.rom_ctrl_stress_all.520117393 Jun 24 05:28:52 PM PDT 24 Jun 24 05:29:55 PM PDT 24 10134292343 ps
T371 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2926763856 Jun 24 05:29:40 PM PDT 24 Jun 24 05:29:47 PM PDT 24 96293962 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1497881306 Jun 24 06:06:54 PM PDT 24 Jun 24 06:07:01 PM PDT 24 172376661 ps
T372 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.909116944 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:19 PM PDT 24 14395929207 ps
T68 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.695191107 Jun 24 06:06:51 PM PDT 24 Jun 24 06:07:09 PM PDT 24 8094515583 ps
T69 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1545971796 Jun 24 06:06:39 PM PDT 24 Jun 24 06:07:08 PM PDT 24 560702587 ps
T373 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2134052943 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:20 PM PDT 24 1772989330 ps
T374 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1755144924 Jun 24 06:06:49 PM PDT 24 Jun 24 06:07:08 PM PDT 24 11659501901 ps
T114 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1596894705 Jun 24 06:06:47 PM PDT 24 Jun 24 06:06:58 PM PDT 24 8381756238 ps
T107 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.706587077 Jun 24 06:06:49 PM PDT 24 Jun 24 06:07:02 PM PDT 24 26836254094 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1610059054 Jun 24 06:06:49 PM PDT 24 Jun 24 06:07:04 PM PDT 24 6722529050 ps
T74 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3118493864 Jun 24 06:06:42 PM PDT 24 Jun 24 06:06:50 PM PDT 24 168143873 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2141413320 Jun 24 06:06:48 PM PDT 24 Jun 24 06:07:04 PM PDT 24 1871673171 ps
T63 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1759558403 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:46 PM PDT 24 2094524459 ps
T75 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3259613718 Jun 24 06:06:54 PM PDT 24 Jun 24 06:07:22 PM PDT 24 2140891494 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.660919746 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:12 PM PDT 24 663347066 ps
T64 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2669992830 Jun 24 06:06:51 PM PDT 24 Jun 24 06:07:37 PM PDT 24 28393566389 ps
T377 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4133396458 Jun 24 06:07:04 PM PDT 24 Jun 24 06:07:24 PM PDT 24 3644875869 ps
T76 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3031608253 Jun 24 06:07:01 PM PDT 24 Jun 24 06:07:11 PM PDT 24 1312224057 ps
T65 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.945317567 Jun 24 06:07:01 PM PDT 24 Jun 24 06:07:50 PM PDT 24 2377085138 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3511292939 Jun 24 06:06:43 PM PDT 24 Jun 24 06:06:49 PM PDT 24 171234260 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3222062158 Jun 24 06:06:47 PM PDT 24 Jun 24 06:07:12 PM PDT 24 1774495841 ps
T115 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2688472367 Jun 24 06:06:44 PM PDT 24 Jun 24 06:06:58 PM PDT 24 2862532443 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1248838147 Jun 24 06:06:41 PM PDT 24 Jun 24 06:06:48 PM PDT 24 383503272 ps
T380 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2761262167 Jun 24 06:06:59 PM PDT 24 Jun 24 06:07:14 PM PDT 24 1859147133 ps
T381 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3811105365 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:13 PM PDT 24 106530543 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4256804948 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:57 PM PDT 24 16887670935 ps
T78 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2900186663 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:54 PM PDT 24 19919279598 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.795780665 Jun 24 06:07:04 PM PDT 24 Jun 24 06:07:23 PM PDT 24 22488344730 ps
T79 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3663564123 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:52 PM PDT 24 2744396189 ps
T133 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1630579811 Jun 24 06:06:58 PM PDT 24 Jun 24 06:07:45 PM PDT 24 1811834855 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2262493796 Jun 24 06:06:54 PM PDT 24 Jun 24 06:07:05 PM PDT 24 2293014777 ps
T385 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.692699732 Jun 24 06:06:53 PM PDT 24 Jun 24 06:07:04 PM PDT 24 422438318 ps
T386 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3426733897 Jun 24 06:06:51 PM PDT 24 Jun 24 06:07:04 PM PDT 24 4834653522 ps
T80 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3292284381 Jun 24 06:06:46 PM PDT 24 Jun 24 06:06:54 PM PDT 24 1384526491 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2254331807 Jun 24 06:06:39 PM PDT 24 Jun 24 06:06:54 PM PDT 24 4955529581 ps
T84 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3556291168 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:11 PM PDT 24 171184259 ps
T135 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2802676949 Jun 24 06:06:51 PM PDT 24 Jun 24 06:07:38 PM PDT 24 1880729346 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3654648715 Jun 24 06:06:54 PM PDT 24 Jun 24 06:06:59 PM PDT 24 346437464 ps
T110 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2142882844 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:20 PM PDT 24 17158376412 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.215847377 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:55 PM PDT 24 2217431406 ps
T130 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2126163192 Jun 24 06:06:50 PM PDT 24 Jun 24 06:07:29 PM PDT 24 505207045 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4217964969 Jun 24 06:06:41 PM PDT 24 Jun 24 06:06:52 PM PDT 24 7777201728 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.485829467 Jun 24 06:06:46 PM PDT 24 Jun 24 06:07:00 PM PDT 24 1288768204 ps
T131 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2781519518 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:52 PM PDT 24 30286526598 ps
T111 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3300201406 Jun 24 06:07:05 PM PDT 24 Jun 24 06:07:23 PM PDT 24 6769811192 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3999496193 Jun 24 06:06:41 PM PDT 24 Jun 24 06:06:50 PM PDT 24 414084731 ps
T392 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.646355163 Jun 24 06:07:04 PM PDT 24 Jun 24 06:07:23 PM PDT 24 4797413769 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1466359953 Jun 24 06:06:49 PM PDT 24 Jun 24 06:07:01 PM PDT 24 415455661 ps
T394 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2195459596 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:21 PM PDT 24 1008556114 ps
T112 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2403783019 Jun 24 06:06:57 PM PDT 24 Jun 24 06:07:10 PM PDT 24 1038475736 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2330963220 Jun 24 06:06:51 PM PDT 24 Jun 24 06:06:57 PM PDT 24 111857850 ps
T127 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2532474 Jun 24 06:06:47 PM PDT 24 Jun 24 06:08:05 PM PDT 24 2262235057 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1019765611 Jun 24 06:06:44 PM PDT 24 Jun 24 06:06:59 PM PDT 24 1826459124 ps
T85 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3450108953 Jun 24 06:06:50 PM PDT 24 Jun 24 06:07:45 PM PDT 24 5841533166 ps
T397 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1207678533 Jun 24 06:06:43 PM PDT 24 Jun 24 06:06:49 PM PDT 24 380222592 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2932253245 Jun 24 06:06:41 PM PDT 24 Jun 24 06:06:54 PM PDT 24 4685799280 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3123899937 Jun 24 06:06:42 PM PDT 24 Jun 24 06:07:05 PM PDT 24 2173447184 ps
T132 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3030052206 Jun 24 06:06:48 PM PDT 24 Jun 24 06:08:02 PM PDT 24 24752612634 ps
T128 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1335955917 Jun 24 06:06:51 PM PDT 24 Jun 24 06:08:08 PM PDT 24 6711106889 ps
T113 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1622848420 Jun 24 06:06:42 PM PDT 24 Jun 24 06:06:55 PM PDT 24 2809119908 ps
T400 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2126678959 Jun 24 06:06:49 PM PDT 24 Jun 24 06:07:04 PM PDT 24 6723216038 ps
T129 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.73887782 Jun 24 06:06:49 PM PDT 24 Jun 24 06:07:58 PM PDT 24 446765922 ps
T123 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.713577880 Jun 24 06:06:40 PM PDT 24 Jun 24 06:07:20 PM PDT 24 5315290160 ps
T401 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.421546485 Jun 24 06:06:51 PM PDT 24 Jun 24 06:07:08 PM PDT 24 8041269699 ps
T86 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.19670589 Jun 24 06:06:51 PM PDT 24 Jun 24 06:06:57 PM PDT 24 111902177 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1518806389 Jun 24 06:07:01 PM PDT 24 Jun 24 06:08:08 PM PDT 24 25629513829 ps
T402 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3678441113 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:20 PM PDT 24 1712484490 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3490447027 Jun 24 06:06:39 PM PDT 24 Jun 24 06:06:52 PM PDT 24 2065610819 ps
T134 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1621042004 Jun 24 06:07:01 PM PDT 24 Jun 24 06:07:47 PM PDT 24 7412987886 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3471248428 Jun 24 06:06:54 PM PDT 24 Jun 24 06:07:00 PM PDT 24 194588283 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3121598276 Jun 24 06:06:52 PM PDT 24 Jun 24 06:07:00 PM PDT 24 367388309 ps
T405 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3239249054 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:14 PM PDT 24 197625120 ps
T406 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2864661580 Jun 24 06:06:57 PM PDT 24 Jun 24 06:07:11 PM PDT 24 2425788157 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1534390812 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:57 PM PDT 24 4910418128 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.21867098 Jun 24 06:06:39 PM PDT 24 Jun 24 06:06:49 PM PDT 24 496842039 ps
T139 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1509799531 Jun 24 06:06:59 PM PDT 24 Jun 24 06:08:18 PM PDT 24 9158982785 ps
T408 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.945644086 Jun 24 06:07:11 PM PDT 24 Jun 24 06:08:15 PM PDT 24 9645004716 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2263455514 Jun 24 06:06:39 PM PDT 24 Jun 24 06:06:50 PM PDT 24 2281346947 ps
T410 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2455143016 Jun 24 06:06:50 PM PDT 24 Jun 24 06:07:01 PM PDT 24 150254717 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.477264610 Jun 24 06:06:43 PM PDT 24 Jun 24 06:06:58 PM PDT 24 1442602153 ps
T124 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2910509308 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:35 PM PDT 24 2016241258 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2087878579 Jun 24 06:06:50 PM PDT 24 Jun 24 06:07:01 PM PDT 24 955589038 ps
T125 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.31606106 Jun 24 06:06:48 PM PDT 24 Jun 24 06:08:08 PM PDT 24 9317424798 ps
T88 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1812957708 Jun 24 06:06:55 PM PDT 24 Jun 24 06:08:33 PM PDT 24 25321725598 ps
T413 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4238603432 Jun 24 06:07:00 PM PDT 24 Jun 24 06:07:09 PM PDT 24 4152168644 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4047366035 Jun 24 06:06:49 PM PDT 24 Jun 24 06:07:48 PM PDT 24 28028902698 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3837304792 Jun 24 06:06:47 PM PDT 24 Jun 24 06:07:07 PM PDT 24 23663520170 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4158002466 Jun 24 06:06:44 PM PDT 24 Jun 24 06:07:05 PM PDT 24 1522445941 ps
T140 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3358323413 Jun 24 06:06:49 PM PDT 24 Jun 24 06:08:05 PM PDT 24 1349933094 ps
T416 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2456002798 Jun 24 06:06:59 PM PDT 24 Jun 24 06:07:12 PM PDT 24 4199274557 ps
T417 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2560609298 Jun 24 06:06:50 PM PDT 24 Jun 24 06:07:03 PM PDT 24 1277131283 ps
T418 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2946813772 Jun 24 06:06:49 PM PDT 24 Jun 24 06:07:04 PM PDT 24 5885663581 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.852861899 Jun 24 06:06:50 PM PDT 24 Jun 24 06:06:57 PM PDT 24 712415550 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.530942083 Jun 24 06:06:50 PM PDT 24 Jun 24 06:07:07 PM PDT 24 3150266940 ps
T89 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1832445279 Jun 24 06:06:39 PM PDT 24 Jun 24 06:07:08 PM PDT 24 3014535438 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3626321123 Jun 24 06:06:48 PM PDT 24 Jun 24 06:07:03 PM PDT 24 1662969883 ps
T422 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3110307674 Jun 24 06:07:01 PM PDT 24 Jun 24 06:07:19 PM PDT 24 4188561135 ps
T423 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2501449009 Jun 24 06:07:01 PM PDT 24 Jun 24 06:07:11 PM PDT 24 597587294 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.237687258 Jun 24 06:06:51 PM PDT 24 Jun 24 06:06:59 PM PDT 24 1474975869 ps
T425 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2357045061 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:16 PM PDT 24 2016164885 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3876039046 Jun 24 06:06:49 PM PDT 24 Jun 24 06:07:02 PM PDT 24 3479879567 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.335502724 Jun 24 06:06:51 PM PDT 24 Jun 24 06:07:09 PM PDT 24 2325994657 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3889999882 Jun 24 06:07:02 PM PDT 24 Jun 24 06:08:02 PM PDT 24 4654342199 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2337142999 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:26 PM PDT 24 17733798572 ps
T137 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3114335317 Jun 24 06:07:01 PM PDT 24 Jun 24 06:08:14 PM PDT 24 986816905 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.724326637 Jun 24 06:06:45 PM PDT 24 Jun 24 06:07:00 PM PDT 24 1658816522 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2358849202 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:50 PM PDT 24 822348454 ps
T136 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3101649604 Jun 24 06:06:51 PM PDT 24 Jun 24 06:07:32 PM PDT 24 3063381247 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4050189083 Jun 24 06:07:06 PM PDT 24 Jun 24 06:07:26 PM PDT 24 21375710220 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2821841121 Jun 24 06:06:54 PM PDT 24 Jun 24 06:07:06 PM PDT 24 1069448475 ps
T434 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1512732615 Jun 24 06:07:00 PM PDT 24 Jun 24 06:07:14 PM PDT 24 2862403935 ps
T138 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3930732409 Jun 24 06:07:01 PM PDT 24 Jun 24 06:08:14 PM PDT 24 1205728915 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3574034565 Jun 24 06:07:02 PM PDT 24 Jun 24 06:08:22 PM PDT 24 33831975992 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4250276268 Jun 24 06:07:00 PM PDT 24 Jun 24 06:07:06 PM PDT 24 343930421 ps
T437 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1102096974 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:21 PM PDT 24 2426153352 ps
T438 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2968675011 Jun 24 06:06:54 PM PDT 24 Jun 24 06:07:48 PM PDT 24 5605072550 ps
T439 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1423122310 Jun 24 06:06:59 PM PDT 24 Jun 24 06:07:18 PM PDT 24 7383361245 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2048185874 Jun 24 06:06:49 PM PDT 24 Jun 24 06:06:55 PM PDT 24 129910611 ps
T441 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3669488211 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:18 PM PDT 24 3685298740 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3404680414 Jun 24 06:06:43 PM PDT 24 Jun 24 06:07:32 PM PDT 24 1894185800 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1534520859 Jun 24 06:06:43 PM PDT 24 Jun 24 06:06:55 PM PDT 24 845845249 ps
T444 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.800764964 Jun 24 06:06:50 PM PDT 24 Jun 24 06:06:56 PM PDT 24 85830347 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.818166037 Jun 24 06:06:45 PM PDT 24 Jun 24 06:07:02 PM PDT 24 2127053153 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.210069000 Jun 24 06:06:50 PM PDT 24 Jun 24 06:07:05 PM PDT 24 6356258335 ps
T447 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2260958431 Jun 24 06:06:49 PM PDT 24 Jun 24 06:08:07 PM PDT 24 2080156183 ps
T87 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3692301370 Jun 24 06:06:52 PM PDT 24 Jun 24 06:07:04 PM PDT 24 21355270698 ps
T448 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3839158418 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:21 PM PDT 24 1310641122 ps
T449 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2980186888 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:16 PM PDT 24 373972398 ps
T450 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.726041253 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:18 PM PDT 24 1022080409 ps
T141 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2485876405 Jun 24 06:07:01 PM PDT 24 Jun 24 06:07:45 PM PDT 24 1115408033 ps
T451 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2932958611 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:53 PM PDT 24 10261546875 ps
T452 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3894806601 Jun 24 06:06:50 PM PDT 24 Jun 24 06:07:06 PM PDT 24 9020226190 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2812968886 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:59 PM PDT 24 1688843786 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.394703859 Jun 24 06:06:58 PM PDT 24 Jun 24 06:07:04 PM PDT 24 85464354 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.6243402 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:12 PM PDT 24 171594195 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1774514322 Jun 24 06:06:53 PM PDT 24 Jun 24 06:07:07 PM PDT 24 6914139454 ps
T457 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2034749518 Jun 24 06:06:59 PM PDT 24 Jun 24 06:07:38 PM PDT 24 4346813244 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4116919710 Jun 24 06:06:48 PM PDT 24 Jun 24 06:06:56 PM PDT 24 1260848186 ps
T458 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3480498874 Jun 24 06:06:51 PM PDT 24 Jun 24 06:06:57 PM PDT 24 102556181 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.911964869 Jun 24 06:06:50 PM PDT 24 Jun 24 06:07:02 PM PDT 24 4106011485 ps
T460 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.214632496 Jun 24 06:07:08 PM PDT 24 Jun 24 06:07:22 PM PDT 24 1320587004 ps
T461 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2617339369 Jun 24 06:07:01 PM PDT 24 Jun 24 06:07:13 PM PDT 24 973222694 ps
T462 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4150106259 Jun 24 06:07:02 PM PDT 24 Jun 24 06:07:17 PM PDT 24 6838714124 ps
T90 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3258034657 Jun 24 06:07:01 PM PDT 24 Jun 24 06:07:10 PM PDT 24 6456636238 ps
T463 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3149078566 Jun 24 06:07:03 PM PDT 24 Jun 24 06:07:22 PM PDT 24 1960215483 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4093016455 Jun 24 06:06:41 PM PDT 24 Jun 24 06:06:57 PM PDT 24 5291963734 ps

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3922411609
Short name T1
Test name
Test status
Simulation time 1550994994 ps
CPU time 101.24 seconds
Started Jun 24 05:29:31 PM PDT 24
Finished Jun 24 05:31:14 PM PDT 24
Peak memory 236524 kb
Host smart-183b4365-a694-4825-bfc5-500089f5d56e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922411609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3922411609
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4110377182
Short name T11
Test name
Test status
Simulation time 50248743262 ps
CPU time 1138.85 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:47:54 PM PDT 24
Peak memory 234792 kb
Host smart-bdaf22f2-417d-4933-9429-38db02b10f62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110377182 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.4110377182
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.354335781
Short name T10
Test name
Test status
Simulation time 12023603899 ps
CPU time 26.79 seconds
Started Jun 24 05:29:34 PM PDT 24
Finished Jun 24 05:30:01 PM PDT 24
Peak memory 214320 kb
Host smart-096bd168-0e47-42e0-8b75-24d9c9662d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354335781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.354335781
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3959180890
Short name T3
Test name
Test status
Simulation time 79402993059 ps
CPU time 696.66 seconds
Started Jun 24 05:29:39 PM PDT 24
Finished Jun 24 05:41:17 PM PDT 24
Peak memory 233980 kb
Host smart-d4678c1d-859f-4867-ac19-dbee20692112
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959180890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3959180890
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.295281677
Short name T47
Test name
Test status
Simulation time 8883651271 ps
CPU time 111.46 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 05:31:09 PM PDT 24
Peak memory 237628 kb
Host smart-d3cad46a-f5c5-449a-b9d5-3c7417a964b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295281677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.295281677
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2802676949
Short name T135
Test name
Test status
Simulation time 1880729346 ps
CPU time 46.03 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 219600 kb
Host smart-3f0c6678-3dea-40ca-a448-f98fdfa40c48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802676949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2802676949
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3596708072
Short name T13
Test name
Test status
Simulation time 22891429892 ps
CPU time 5283.59 seconds
Started Jun 24 05:29:28 PM PDT 24
Finished Jun 24 06:57:33 PM PDT 24
Peak memory 235688 kb
Host smart-ecf652de-3577-4ea3-b674-0cc96a477bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596708072 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3596708072
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1159558802
Short name T19
Test name
Test status
Simulation time 1664278026 ps
CPU time 61.06 seconds
Started Jun 24 05:28:52 PM PDT 24
Finished Jun 24 05:29:53 PM PDT 24
Peak memory 236476 kb
Host smart-31328c1a-7a16-46fc-9a6e-d19240ccf1f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159558802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1159558802
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2126163192
Short name T130
Test name
Test status
Simulation time 505207045 ps
CPU time 38.02 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:07:29 PM PDT 24
Peak memory 212788 kb
Host smart-a0095b83-2834-4c78-b70c-89f1b5462bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126163192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2126163192
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3663564123
Short name T79
Test name
Test status
Simulation time 2744396189 ps
CPU time 44.38 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:52 PM PDT 24
Peak memory 211556 kb
Host smart-d5ec2d7c-c1ed-4487-8486-95fe22b48272
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663564123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3663564123
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3598474342
Short name T23
Test name
Test status
Simulation time 5461389749 ps
CPU time 13.43 seconds
Started Jun 24 05:29:40 PM PDT 24
Finished Jun 24 05:29:54 PM PDT 24
Peak memory 211112 kb
Host smart-5b631a9a-fc52-46c3-bc8f-cc09a4a2a4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598474342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3598474342
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3848717594
Short name T66
Test name
Test status
Simulation time 7102555630 ps
CPU time 13.84 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:10 PM PDT 24
Peak memory 213252 kb
Host smart-05cab49a-c80a-4918-81a1-493b9352efc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848717594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3848717594
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.86774255
Short name T8
Test name
Test status
Simulation time 34298318881 ps
CPU time 31.45 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 05:29:49 PM PDT 24
Peak memory 212128 kb
Host smart-70aeee80-fc85-402c-a860-0bab2c9bb49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86774255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.86774255
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3258858828
Short name T331
Test name
Test status
Simulation time 976240317 ps
CPU time 9.97 seconds
Started Jun 24 05:29:05 PM PDT 24
Finished Jun 24 05:29:16 PM PDT 24
Peak memory 211824 kb
Host smart-0be9640e-304f-43c4-833c-fef4b999b17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258858828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3258858828
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.73887782
Short name T129
Test name
Test status
Simulation time 446765922 ps
CPU time 67.65 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:07:58 PM PDT 24
Peak memory 219568 kb
Host smart-f9467c8a-7c1f-4f1f-b4da-d8a5f2b29871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73887782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg
_err.73887782
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2485876405
Short name T141
Test name
Test status
Simulation time 1115408033 ps
CPU time 41.83 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:07:45 PM PDT 24
Peak memory 212692 kb
Host smart-7e360d23-9284-4fa0-ab2d-e1bed967b05e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485876405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2485876405
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3118493864
Short name T74
Test name
Test status
Simulation time 168143873 ps
CPU time 5.55 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:50 PM PDT 24
Peak memory 211420 kb
Host smart-57cbaab0-cf0a-4e79-bdb8-22e053a8fad3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118493864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3118493864
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3682360004
Short name T51
Test name
Test status
Simulation time 305621329983 ps
CPU time 2879.18 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 06:17:17 PM PDT 24
Peak memory 248000 kb
Host smart-d9519a10-f823-41f8-b731-d450bf65e13d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682360004 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3682360004
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.713577880
Short name T123
Test name
Test status
Simulation time 5315290160 ps
CPU time 36.74 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:07:20 PM PDT 24
Peak memory 211584 kb
Host smart-66cf2ce2-ca89-4be4-a418-9b1ccc0718f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713577880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.713577880
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.945317567
Short name T65
Test name
Test status
Simulation time 2377085138 ps
CPU time 47.29 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:07:50 PM PDT 24
Peak memory 212924 kb
Host smart-baad79de-fbe3-4e54-b38e-888011648067
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945317567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.945317567
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1706692283
Short name T97
Test name
Test status
Simulation time 227759739 ps
CPU time 7.31 seconds
Started Jun 24 05:29:12 PM PDT 24
Finished Jun 24 05:29:23 PM PDT 24
Peak memory 211244 kb
Host smart-7d36fba5-3d72-42bd-a5be-4560740ee49d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706692283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1706692283
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.962037747
Short name T146
Test name
Test status
Simulation time 7767980349 ps
CPU time 75.84 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:30:12 PM PDT 24
Peak memory 216856 kb
Host smart-7cf7f722-21e1-432d-8fc6-4f96b5be4a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962037747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.962037747
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2254331807
Short name T387
Test name
Test status
Simulation time 4955529581 ps
CPU time 11.91 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:54 PM PDT 24
Peak memory 211552 kb
Host smart-70f4c423-9f7e-4795-b39c-003989aa8d6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254331807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2254331807
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1534390812
Short name T93
Test name
Test status
Simulation time 4910418128 ps
CPU time 13.61 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:57 PM PDT 24
Peak memory 219604 kb
Host smart-132ea8b4-4b69-40af-9842-f56af700ec31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534390812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1534390812
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1207678533
Short name T397
Test name
Test status
Simulation time 380222592 ps
CPU time 4.47 seconds
Started Jun 24 06:06:43 PM PDT 24
Finished Jun 24 06:06:49 PM PDT 24
Peak memory 212920 kb
Host smart-5d7d1965-2542-4bff-92bc-37232b4b4263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207678533 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1207678533
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2688472367
Short name T115
Test name
Test status
Simulation time 2862532443 ps
CPU time 12.94 seconds
Started Jun 24 06:06:44 PM PDT 24
Finished Jun 24 06:06:58 PM PDT 24
Peak memory 211488 kb
Host smart-9b0ff0ef-f3ec-4c18-af76-97d2a6389509
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688472367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2688472367
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.21867098
Short name T407
Test name
Test status
Simulation time 496842039 ps
CPU time 7.28 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:49 PM PDT 24
Peak memory 211204 kb
Host smart-cc2d1db7-0732-483d-89db-b1d230d62d90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_
mem_partial_access.21867098
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1019765611
Short name T396
Test name
Test status
Simulation time 1826459124 ps
CPU time 14.04 seconds
Started Jun 24 06:06:44 PM PDT 24
Finished Jun 24 06:06:59 PM PDT 24
Peak memory 211164 kb
Host smart-558d2238-d71d-498b-9631-490b91ef9e87
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019765611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1019765611
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2087878579
Short name T412
Test name
Test status
Simulation time 955589038 ps
CPU time 9.9 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:07:01 PM PDT 24
Peak memory 219564 kb
Host smart-3cb223de-22d0-476b-a4f6-d78ae9128437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087878579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2087878579
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3123899937
Short name T399
Test name
Test status
Simulation time 2173447184 ps
CPU time 20.42 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:07:05 PM PDT 24
Peak memory 219560 kb
Host smart-d245f568-cc3b-4de0-a968-ad5ba93836d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123899937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3123899937
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3292284381
Short name T80
Test name
Test status
Simulation time 1384526491 ps
CPU time 6.77 seconds
Started Jun 24 06:06:46 PM PDT 24
Finished Jun 24 06:06:54 PM PDT 24
Peak memory 211432 kb
Host smart-fd706310-0663-44ad-b56b-ec3ea40c3be6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292284381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3292284381
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.335502724
Short name T427
Test name
Test status
Simulation time 2325994657 ps
CPU time 16.87 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:07:09 PM PDT 24
Peak memory 219608 kb
Host smart-ce2c5940-cacc-417b-94e6-fb310029fa62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335502724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.335502724
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2812968886
Short name T453
Test name
Test status
Simulation time 1688843786 ps
CPU time 16.25 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:59 PM PDT 24
Peak memory 211428 kb
Host smart-156a1576-6d68-4678-a7b1-e8c6891f0706
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812968886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2812968886
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.724326637
Short name T430
Test name
Test status
Simulation time 1658816522 ps
CPU time 13.91 seconds
Started Jun 24 06:06:45 PM PDT 24
Finished Jun 24 06:07:00 PM PDT 24
Peak memory 219860 kb
Host smart-843d9351-772c-49ed-b915-ac52d4e2c171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724326637 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.724326637
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4093016455
Short name T96
Test name
Test status
Simulation time 5291963734 ps
CPU time 13.23 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:57 PM PDT 24
Peak memory 219460 kb
Host smart-68fb6abe-69a0-4d27-ae29-c756bce3730e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093016455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4093016455
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.477264610
Short name T411
Test name
Test status
Simulation time 1442602153 ps
CPU time 12.76 seconds
Started Jun 24 06:06:43 PM PDT 24
Finished Jun 24 06:06:58 PM PDT 24
Peak memory 211232 kb
Host smart-42d43186-2ff2-4a3e-ba25-9d6053eff22a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477264610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.477264610
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3999496193
Short name T391
Test name
Test status
Simulation time 414084731 ps
CPU time 6.79 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:50 PM PDT 24
Peak memory 211240 kb
Host smart-5c1b76c9-f789-4b6b-a77e-93e7673bab59
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999496193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3999496193
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4158002466
Short name T94
Test name
Test status
Simulation time 1522445941 ps
CPU time 19.32 seconds
Started Jun 24 06:06:44 PM PDT 24
Finished Jun 24 06:07:05 PM PDT 24
Peak memory 211432 kb
Host smart-9054d817-a62d-4066-aefe-43ac87b5810d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158002466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4158002466
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3490447027
Short name T403
Test name
Test status
Simulation time 2065610819 ps
CPU time 10.57 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:52 PM PDT 24
Peak memory 219580 kb
Host smart-ab831678-4b3c-456b-8f5e-5236a8a526c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490447027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3490447027
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.215847377
Short name T388
Test name
Test status
Simulation time 2217431406 ps
CPU time 12.27 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:55 PM PDT 24
Peak memory 219672 kb
Host smart-1d0341d9-5e63-455f-8924-1576d17bfb09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215847377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.215847377
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3404680414
Short name T442
Test name
Test status
Simulation time 1894185800 ps
CPU time 47.08 seconds
Started Jun 24 06:06:43 PM PDT 24
Finished Jun 24 06:07:32 PM PDT 24
Peak memory 219572 kb
Host smart-9f17dd0f-841e-463a-a2d0-501143079495
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404680414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3404680414
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2330963220
Short name T395
Test name
Test status
Simulation time 111857850 ps
CPU time 5.19 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:06:57 PM PDT 24
Peak memory 219628 kb
Host smart-6f51012a-cb41-4d55-a116-69a5d21bdfbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330963220 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2330963220
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3556291168
Short name T84
Test name
Test status
Simulation time 171184259 ps
CPU time 4.28 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:11 PM PDT 24
Peak memory 218564 kb
Host smart-67f67cc3-ac7b-427c-9230-50dd8585903b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556291168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3556291168
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1812957708
Short name T88
Test name
Test status
Simulation time 25321725598 ps
CPU time 96.54 seconds
Started Jun 24 06:06:55 PM PDT 24
Finished Jun 24 06:08:33 PM PDT 24
Peak memory 211552 kb
Host smart-483f42a6-9be0-45e0-8a79-103aa21a5134
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812957708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1812957708
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2048185874
Short name T440
Test name
Test status
Simulation time 129910611 ps
CPU time 5.57 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:06:55 PM PDT 24
Peak memory 211396 kb
Host smart-db330cdb-3a2b-42a7-9cce-b1c1b24487da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048185874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2048185874
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.692699732
Short name T385
Test name
Test status
Simulation time 422438318 ps
CPU time 10.57 seconds
Started Jun 24 06:06:53 PM PDT 24
Finished Jun 24 06:07:04 PM PDT 24
Peak memory 219540 kb
Host smart-6cb81991-2c6b-4dd7-9dfb-fec9d5042ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692699732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.692699732
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1759558403
Short name T63
Test name
Test status
Simulation time 2094524459 ps
CPU time 38.91 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:46 PM PDT 24
Peak memory 213444 kb
Host smart-2cc0dc9d-28c1-48d4-a367-ea11a70fa7e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759558403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1759558403
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1755144924
Short name T374
Test name
Test status
Simulation time 11659501901 ps
CPU time 16.96 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:07:08 PM PDT 24
Peak memory 219708 kb
Host smart-db223a39-f93f-4a80-a87a-6543748d53b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755144924 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1755144924
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1497881306
Short name T67
Test name
Test status
Simulation time 172376661 ps
CPU time 5.56 seconds
Started Jun 24 06:06:54 PM PDT 24
Finished Jun 24 06:07:01 PM PDT 24
Peak memory 218456 kb
Host smart-8be4454c-6211-4160-b686-6a506329752d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497881306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1497881306
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2900186663
Short name T78
Test name
Test status
Simulation time 19919279598 ps
CPU time 47.28 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 211572 kb
Host smart-0e968a16-2645-4c25-a7a6-9f9eb833366b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900186663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2900186663
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2141413320
Short name T108
Test name
Test status
Simulation time 1871673171 ps
CPU time 15.32 seconds
Started Jun 24 06:06:48 PM PDT 24
Finished Jun 24 06:07:04 PM PDT 24
Peak memory 211440 kb
Host smart-5a456495-534e-4671-ab19-c84a387d8b7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141413320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2141413320
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2455143016
Short name T410
Test name
Test status
Simulation time 150254717 ps
CPU time 9.76 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:07:01 PM PDT 24
Peak memory 215092 kb
Host smart-eb5f7042-7c65-4654-b1c8-a22e075e6d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455143016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2455143016
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4150106259
Short name T462
Test name
Test status
Simulation time 6838714124 ps
CPU time 10.93 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:17 PM PDT 24
Peak memory 219776 kb
Host smart-0685cb99-6492-4323-aab3-281e0361d6b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150106259 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4150106259
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3031608253
Short name T76
Test name
Test status
Simulation time 1312224057 ps
CPU time 6.57 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:07:11 PM PDT 24
Peak memory 211260 kb
Host smart-f865cb4b-e4d8-4c6b-b722-709921d524dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031608253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3031608253
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3450108953
Short name T85
Test name
Test status
Simulation time 5841533166 ps
CPU time 53.06 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:07:45 PM PDT 24
Peak memory 211576 kb
Host smart-26e67e58-2c42-47aa-ba0b-490585500e3b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450108953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3450108953
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.726041253
Short name T450
Test name
Test status
Simulation time 1022080409 ps
CPU time 10.57 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:18 PM PDT 24
Peak memory 211404 kb
Host smart-55a9fe92-c6a5-438a-8910-cfc18c2d36f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726041253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.726041253
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3839158418
Short name T448
Test name
Test status
Simulation time 1310641122 ps
CPU time 14.43 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:21 PM PDT 24
Peak memory 219528 kb
Host smart-7584aed9-1472-4227-8514-02fe1d12812e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839158418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3839158418
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3930732409
Short name T138
Test name
Test status
Simulation time 1205728915 ps
CPU time 71.07 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:08:14 PM PDT 24
Peak memory 211948 kb
Host smart-b0827048-5cb8-4ad6-8ec5-5cf614910cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930732409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3930732409
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3811105365
Short name T381
Test name
Test status
Simulation time 106530543 ps
CPU time 5.37 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:13 PM PDT 24
Peak memory 219628 kb
Host smart-7b99fc23-7c99-4f2b-963d-1cccfed0fc88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811105365 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3811105365
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2357045061
Short name T425
Test name
Test status
Simulation time 2016164885 ps
CPU time 9.8 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:16 PM PDT 24
Peak memory 211356 kb
Host smart-1db2fddb-c485-4ca2-a4ae-6e53181822ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357045061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2357045061
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2932958611
Short name T451
Test name
Test status
Simulation time 10261546875 ps
CPU time 46.62 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 211552 kb
Host smart-1e5baf9b-623e-4ab5-bb42-61ba9994df9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932958611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2932958611
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.6243402
Short name T455
Test name
Test status
Simulation time 171594195 ps
CPU time 4.45 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:12 PM PDT 24
Peak memory 211372 kb
Host smart-3a7b1180-5b0f-4b41-a226-098a445fed6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6243402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctr
l_same_csr_outstanding.6243402
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2195459596
Short name T394
Test name
Test status
Simulation time 1008556114 ps
CPU time 14.23 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:21 PM PDT 24
Peak memory 216208 kb
Host smart-039c5f89-d206-440a-9633-4844d109dbe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195459596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2195459596
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4238603432
Short name T413
Test name
Test status
Simulation time 4152168644 ps
CPU time 9.15 seconds
Started Jun 24 06:07:00 PM PDT 24
Finished Jun 24 06:07:09 PM PDT 24
Peak memory 219684 kb
Host smart-daead8db-d3a6-4a0a-a140-3025df2ad871
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238603432 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4238603432
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4250276268
Short name T436
Test name
Test status
Simulation time 343930421 ps
CPU time 5.37 seconds
Started Jun 24 06:07:00 PM PDT 24
Finished Jun 24 06:07:06 PM PDT 24
Peak memory 211640 kb
Host smart-6e28712c-4e0d-4180-bf7e-6c4dbdcb61b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250276268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4250276268
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1512732615
Short name T434
Test name
Test status
Simulation time 2862403935 ps
CPU time 12.5 seconds
Started Jun 24 06:07:00 PM PDT 24
Finished Jun 24 06:07:14 PM PDT 24
Peak memory 211548 kb
Host smart-54285296-7579-43ef-b92e-c3e349b6a4ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512732615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1512732615
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2980186888
Short name T449
Test name
Test status
Simulation time 373972398 ps
CPU time 10.25 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:16 PM PDT 24
Peak memory 219548 kb
Host smart-a7f74b6a-c286-4d2d-bca9-fb7571b84e95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980186888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2980186888
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1509799531
Short name T139
Test name
Test status
Simulation time 9158982785 ps
CPU time 78.12 seconds
Started Jun 24 06:06:59 PM PDT 24
Finished Jun 24 06:08:18 PM PDT 24
Peak memory 219728 kb
Host smart-717ab349-38cc-4d84-9484-b1d6c7c5e8d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509799531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1509799531
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3239249054
Short name T405
Test name
Test status
Simulation time 197625120 ps
CPU time 5.76 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:14 PM PDT 24
Peak memory 219656 kb
Host smart-f66f1ce5-b22b-4fc4-b80e-5b0c7398aa88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239249054 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3239249054
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2142882844
Short name T110
Test name
Test status
Simulation time 17158376412 ps
CPU time 14.48 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:20 PM PDT 24
Peak memory 211584 kb
Host smart-57964d21-2ef3-4bd6-abce-879325205f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142882844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2142882844
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2910509308
Short name T124
Test name
Test status
Simulation time 2016241258 ps
CPU time 28.42 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:35 PM PDT 24
Peak memory 211448 kb
Host smart-dc8cba04-3f14-4b12-8a93-f4f195e0fe15
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910509308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2910509308
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2456002798
Short name T416
Test name
Test status
Simulation time 4199274557 ps
CPU time 12.82 seconds
Started Jun 24 06:06:59 PM PDT 24
Finished Jun 24 06:07:12 PM PDT 24
Peak memory 211560 kb
Host smart-d291affa-9245-406c-be66-dca5db419fad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456002798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2456002798
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.795780665
Short name T383
Test name
Test status
Simulation time 22488344730 ps
CPU time 14.86 seconds
Started Jun 24 06:07:04 PM PDT 24
Finished Jun 24 06:07:23 PM PDT 24
Peak memory 219640 kb
Host smart-0198aa0f-b44a-41f1-9218-27334b63471b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795780665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.795780665
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1621042004
Short name T134
Test name
Test status
Simulation time 7412987886 ps
CPU time 44.42 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:07:47 PM PDT 24
Peak memory 213204 kb
Host smart-226213f8-3165-41d7-af05-8873d9b9339d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621042004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1621042004
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4133396458
Short name T377
Test name
Test status
Simulation time 3644875869 ps
CPU time 15.52 seconds
Started Jun 24 06:07:04 PM PDT 24
Finished Jun 24 06:07:24 PM PDT 24
Peak memory 219776 kb
Host smart-53492784-eb59-41e2-97a2-604da9682995
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133396458 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4133396458
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3258034657
Short name T90
Test name
Test status
Simulation time 6456636238 ps
CPU time 7.27 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:07:10 PM PDT 24
Peak memory 211480 kb
Host smart-1fc227bf-1e0c-4fe6-8a85-219a94e7780c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258034657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3258034657
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2034749518
Short name T457
Test name
Test status
Simulation time 4346813244 ps
CPU time 37.88 seconds
Started Jun 24 06:06:59 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 211572 kb
Host smart-5db77293-21e9-461f-96fc-f9153733d17f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034749518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2034749518
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.214632496
Short name T460
Test name
Test status
Simulation time 1320587004 ps
CPU time 12.07 seconds
Started Jun 24 06:07:08 PM PDT 24
Finished Jun 24 06:07:22 PM PDT 24
Peak memory 219568 kb
Host smart-bbaa6ca6-9249-4e4e-b1d9-53437533967d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214632496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.214632496
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.909116944
Short name T372
Test name
Test status
Simulation time 14395929207 ps
CPU time 12.16 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:19 PM PDT 24
Peak memory 219652 kb
Host smart-c34df8d0-c8d5-45aa-90a2-f1c6cb43fd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909116944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.909116944
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3114335317
Short name T137
Test name
Test status
Simulation time 986816905 ps
CPU time 71.08 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:08:14 PM PDT 24
Peak memory 212488 kb
Host smart-4f583f47-818d-4787-9cfb-acd3a9913a34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114335317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3114335317
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2134052943
Short name T373
Test name
Test status
Simulation time 1772989330 ps
CPU time 13.88 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:20 PM PDT 24
Peak memory 219584 kb
Host smart-38e52abd-a408-4e6a-95d0-8c95a96f10aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134052943 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2134052943
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3678441113
Short name T402
Test name
Test status
Simulation time 1712484490 ps
CPU time 14.45 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:20 PM PDT 24
Peak memory 219288 kb
Host smart-d68fec49-d73b-4542-bf54-6b0ef6f17848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678441113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3678441113
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1518806389
Short name T92
Test name
Test status
Simulation time 25629513829 ps
CPU time 63.77 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:08:08 PM PDT 24
Peak memory 211584 kb
Host smart-4f7cfd25-a2bb-44aa-9581-47bd85f46731
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518806389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1518806389
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4050189083
Short name T432
Test name
Test status
Simulation time 21375710220 ps
CPU time 16.32 seconds
Started Jun 24 06:07:06 PM PDT 24
Finished Jun 24 06:07:26 PM PDT 24
Peak memory 219672 kb
Host smart-3b5fb9af-0a04-4a4c-b879-70ea6d75831d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050189083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4050189083
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1423122310
Short name T439
Test name
Test status
Simulation time 7383361245 ps
CPU time 17.94 seconds
Started Jun 24 06:06:59 PM PDT 24
Finished Jun 24 06:07:18 PM PDT 24
Peak memory 219664 kb
Host smart-ae82cac1-ec02-4c15-b1a7-f5f95d2bb899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423122310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1423122310
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2761262167
Short name T380
Test name
Test status
Simulation time 1859147133 ps
CPU time 14.81 seconds
Started Jun 24 06:06:59 PM PDT 24
Finished Jun 24 06:07:14 PM PDT 24
Peak memory 219624 kb
Host smart-806b18a7-560d-4c71-aeaf-3fac356ccea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761262167 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2761262167
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3110307674
Short name T422
Test name
Test status
Simulation time 4188561135 ps
CPU time 15.88 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:07:19 PM PDT 24
Peak memory 211548 kb
Host smart-8a5f59aa-18ac-4179-a795-c3cd37a1714f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110307674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3110307674
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3889999882
Short name T428
Test name
Test status
Simulation time 4654342199 ps
CPU time 55.57 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:08:02 PM PDT 24
Peak memory 211556 kb
Host smart-1146beab-0af1-471a-b5a7-561d33313829
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889999882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3889999882
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3300201406
Short name T111
Test name
Test status
Simulation time 6769811192 ps
CPU time 13.79 seconds
Started Jun 24 06:07:05 PM PDT 24
Finished Jun 24 06:07:23 PM PDT 24
Peak memory 211884 kb
Host smart-7d11e1f9-2e97-4b18-a4d5-3453ccd1e11b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300201406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3300201406
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.646355163
Short name T392
Test name
Test status
Simulation time 4797413769 ps
CPU time 15.08 seconds
Started Jun 24 06:07:04 PM PDT 24
Finished Jun 24 06:07:23 PM PDT 24
Peak memory 219660 kb
Host smart-cd7e155c-95a4-41c7-92bf-fc6a35ed0a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646355163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.646355163
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1630579811
Short name T133
Test name
Test status
Simulation time 1811834855 ps
CPU time 46.06 seconds
Started Jun 24 06:06:58 PM PDT 24
Finished Jun 24 06:07:45 PM PDT 24
Peak memory 219568 kb
Host smart-5c16252f-0d05-498c-9ee9-555453908861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630579811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1630579811
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3669488211
Short name T441
Test name
Test status
Simulation time 3685298740 ps
CPU time 10.22 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:18 PM PDT 24
Peak memory 219764 kb
Host smart-23e22122-7d39-48b2-99e5-354d502869dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669488211 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3669488211
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2501449009
Short name T423
Test name
Test status
Simulation time 597587294 ps
CPU time 7.88 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:07:11 PM PDT 24
Peak memory 211444 kb
Host smart-a12ae49f-9191-4e19-9314-e91f057c112c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501449009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2501449009
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.945644086
Short name T408
Test name
Test status
Simulation time 9645004716 ps
CPU time 62.02 seconds
Started Jun 24 06:07:11 PM PDT 24
Finished Jun 24 06:08:15 PM PDT 24
Peak memory 211576 kb
Host smart-c81a7b1a-9a86-48ba-870a-65c81f34a0aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945644086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.945644086
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2617339369
Short name T461
Test name
Test status
Simulation time 973222694 ps
CPU time 9.97 seconds
Started Jun 24 06:07:01 PM PDT 24
Finished Jun 24 06:07:13 PM PDT 24
Peak memory 219400 kb
Host smart-f8f96f9b-28db-4d14-a1aa-b6c5f95017d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617339369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2617339369
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2337142999
Short name T429
Test name
Test status
Simulation time 17733798572 ps
CPU time 19.69 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:26 PM PDT 24
Peak memory 219644 kb
Host smart-e62d7c9d-1673-4f0f-81cc-f0e6d66c5214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337142999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2337142999
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2781519518
Short name T131
Test name
Test status
Simulation time 30286526598 ps
CPU time 45.22 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:52 PM PDT 24
Peak memory 219716 kb
Host smart-32f30ddc-d022-4b83-b4ec-f3d7fb277766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781519518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2781519518
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2932253245
Short name T398
Test name
Test status
Simulation time 4685799280 ps
CPU time 10.71 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:54 PM PDT 24
Peak memory 211212 kb
Host smart-b1b3d631-5e6a-4155-ab3d-f7930c16dafd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932253245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2932253245
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3511292939
Short name T378
Test name
Test status
Simulation time 171234260 ps
CPU time 4.57 seconds
Started Jun 24 06:06:43 PM PDT 24
Finished Jun 24 06:06:49 PM PDT 24
Peak memory 211364 kb
Host smart-27f52124-a450-4767-a3f8-2eaaa7d89584
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511292939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3511292939
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4256804948
Short name T382
Test name
Test status
Simulation time 16887670935 ps
CPU time 14.69 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:57 PM PDT 24
Peak memory 219516 kb
Host smart-7460f4d7-e012-413d-a1b3-36b9483f460c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256804948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4256804948
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1248838147
Short name T379
Test name
Test status
Simulation time 383503272 ps
CPU time 4.68 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:48 PM PDT 24
Peak memory 219640 kb
Host smart-44cc54aa-91ea-400d-9b19-7b926742c9f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248838147 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1248838147
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.237687258
Short name T424
Test name
Test status
Simulation time 1474975869 ps
CPU time 6.66 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:06:59 PM PDT 24
Peak memory 211428 kb
Host smart-3f9ace2c-5d0d-4da7-80ee-833c6ed8561b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237687258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.237687258
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2263455514
Short name T409
Test name
Test status
Simulation time 2281346947 ps
CPU time 8.09 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:50 PM PDT 24
Peak memory 211352 kb
Host smart-6f26a496-bf1b-4ed9-90a5-2266c941e254
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263455514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2263455514
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.818166037
Short name T445
Test name
Test status
Simulation time 2127053153 ps
CPU time 16.46 seconds
Started Jun 24 06:06:45 PM PDT 24
Finished Jun 24 06:07:02 PM PDT 24
Peak memory 211460 kb
Host smart-e6222707-095c-4a40-b829-2cba1b8214e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818166037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
818166037
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1832445279
Short name T89
Test name
Test status
Simulation time 3014535438 ps
CPU time 27.32 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:07:08 PM PDT 24
Peak memory 211540 kb
Host smart-73497804-0890-4193-9847-5a3a06fbd57a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832445279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1832445279
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2358849202
Short name T431
Test name
Test status
Simulation time 822348454 ps
CPU time 7.38 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:50 PM PDT 24
Peak memory 218640 kb
Host smart-6bac9b97-8e6c-49b6-9bdf-8a66a555f35b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358849202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2358849202
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.485829467
Short name T390
Test name
Test status
Simulation time 1288768204 ps
CPU time 13.25 seconds
Started Jun 24 06:06:46 PM PDT 24
Finished Jun 24 06:07:00 PM PDT 24
Peak memory 219540 kb
Host smart-d7f3942f-cd33-4cf4-a6f9-d4ffcef626d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485829467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.485829467
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2532474
Short name T127
Test name
Test status
Simulation time 2262235057 ps
CPU time 77.94 seconds
Started Jun 24 06:06:47 PM PDT 24
Finished Jun 24 06:08:05 PM PDT 24
Peak memory 211800 kb
Host smart-b1a8165e-920c-4369-9a06-9ffa5548c6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_
err.2532474
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1596894705
Short name T114
Test name
Test status
Simulation time 8381756238 ps
CPU time 10.72 seconds
Started Jun 24 06:06:47 PM PDT 24
Finished Jun 24 06:06:58 PM PDT 24
Peak memory 219028 kb
Host smart-b30138b7-7084-4457-aebe-99e37b2131a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596894705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1596894705
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.800764964
Short name T444
Test name
Test status
Simulation time 85830347 ps
CPU time 4.53 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:06:56 PM PDT 24
Peak memory 211428 kb
Host smart-306b16cf-2cd2-4417-b81c-2a1807b04c1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800764964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.800764964
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4116919710
Short name T95
Test name
Test status
Simulation time 1260848186 ps
CPU time 7.74 seconds
Started Jun 24 06:06:48 PM PDT 24
Finished Jun 24 06:06:56 PM PDT 24
Peak memory 219184 kb
Host smart-10a66f9e-785f-495a-bf41-72a4c50954e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116919710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4116919710
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1534520859
Short name T443
Test name
Test status
Simulation time 845845249 ps
CPU time 10.18 seconds
Started Jun 24 06:06:43 PM PDT 24
Finished Jun 24 06:06:55 PM PDT 24
Peak memory 219652 kb
Host smart-4a58c0d7-e6f5-42e2-90af-551f942a437a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534520859 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1534520859
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.210069000
Short name T446
Test name
Test status
Simulation time 6356258335 ps
CPU time 13.5 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:07:05 PM PDT 24
Peak memory 219624 kb
Host smart-2cda55d9-4f40-4b63-9f6b-43b780d98e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210069000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.210069000
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.530942083
Short name T420
Test name
Test status
Simulation time 3150266940 ps
CPU time 15.41 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:07:07 PM PDT 24
Peak memory 211240 kb
Host smart-7ead60b6-e80d-471b-bc45-e5dba00db9f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530942083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.530942083
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4217964969
Short name T389
Test name
Test status
Simulation time 7777201728 ps
CPU time 9.14 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:52 PM PDT 24
Peak memory 211308 kb
Host smart-3ecbf144-68cf-43e6-883b-cde1f9f55a2f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217964969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4217964969
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3222062158
Short name T77
Test name
Test status
Simulation time 1774495841 ps
CPU time 24.89 seconds
Started Jun 24 06:06:47 PM PDT 24
Finished Jun 24 06:07:12 PM PDT 24
Peak memory 210672 kb
Host smart-8fd2c4f4-6489-4904-98ca-7b76ca61f0bc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222062158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3222062158
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1622848420
Short name T113
Test name
Test status
Simulation time 2809119908 ps
CPU time 10.34 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:55 PM PDT 24
Peak memory 219676 kb
Host smart-28ac0e7a-9785-4607-a15c-6a9f44396ed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622848420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1622848420
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1466359953
Short name T393
Test name
Test status
Simulation time 415455661 ps
CPU time 11.17 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:07:01 PM PDT 24
Peak memory 219488 kb
Host smart-bdf27798-fd37-462e-963e-e954ca724917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466359953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1466359953
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3101649604
Short name T136
Test name
Test status
Simulation time 3063381247 ps
CPU time 39.05 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:07:32 PM PDT 24
Peak memory 219720 kb
Host smart-07eb16cc-0d32-44aa-8593-6e2cdf72cbf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101649604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3101649604
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.695191107
Short name T68
Test name
Test status
Simulation time 8094515583 ps
CPU time 16.42 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:07:09 PM PDT 24
Peak memory 211552 kb
Host smart-8329e52a-7039-4a7b-9766-2fbbf52367d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695191107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.695191107
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.394703859
Short name T454
Test name
Test status
Simulation time 85464354 ps
CPU time 4.74 seconds
Started Jun 24 06:06:58 PM PDT 24
Finished Jun 24 06:07:04 PM PDT 24
Peak memory 211432 kb
Host smart-bfd85184-afcc-4404-b300-b8de6010a822
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394703859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.394703859
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3121598276
Short name T91
Test name
Test status
Simulation time 367388309 ps
CPU time 7.4 seconds
Started Jun 24 06:06:52 PM PDT 24
Finished Jun 24 06:07:00 PM PDT 24
Peak memory 219568 kb
Host smart-a9dc4fcb-4a86-4e6b-965a-602ba87b3b52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121598276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3121598276
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3471248428
Short name T404
Test name
Test status
Simulation time 194588283 ps
CPU time 5.01 seconds
Started Jun 24 06:06:54 PM PDT 24
Finished Jun 24 06:07:00 PM PDT 24
Peak memory 214632 kb
Host smart-aaab581f-1d27-4fb5-8e60-356b7ebab85c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471248428 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3471248428
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.852861899
Short name T419
Test name
Test status
Simulation time 712415550 ps
CPU time 5.75 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:06:57 PM PDT 24
Peak memory 218800 kb
Host smart-d6eb9c96-83fc-446c-8157-58639c21ab87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852861899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.852861899
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1610059054
Short name T375
Test name
Test status
Simulation time 6722529050 ps
CPU time 13.63 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:07:04 PM PDT 24
Peak memory 211348 kb
Host smart-4732687e-3a8f-432e-b9be-f783363c0133
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610059054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1610059054
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1774514322
Short name T456
Test name
Test status
Simulation time 6914139454 ps
CPU time 14.19 seconds
Started Jun 24 06:06:53 PM PDT 24
Finished Jun 24 06:07:07 PM PDT 24
Peak memory 211348 kb
Host smart-e7165537-5787-4a0f-a7b1-3d79486fc201
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774514322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1774514322
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1545971796
Short name T69
Test name
Test status
Simulation time 560702587 ps
CPU time 27.52 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:07:08 PM PDT 24
Peak memory 211452 kb
Host smart-f1b7e4da-2480-4b96-b4dc-96de37f1f62b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545971796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1545971796
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.706587077
Short name T107
Test name
Test status
Simulation time 26836254094 ps
CPU time 12.47 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:07:02 PM PDT 24
Peak memory 211692 kb
Host smart-98bb05ec-38af-408c-b371-adca0f4300d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706587077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.706587077
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.911964869
Short name T459
Test name
Test status
Simulation time 4106011485 ps
CPU time 10.69 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:07:02 PM PDT 24
Peak memory 219664 kb
Host smart-77603084-1ece-4541-b126-e55753a6afbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911964869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.911964869
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.421546485
Short name T401
Test name
Test status
Simulation time 8041269699 ps
CPU time 15.91 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:07:08 PM PDT 24
Peak memory 216164 kb
Host smart-2cfb9cd1-7425-45a9-83ca-41a96dcb8dbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421546485 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.421546485
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2126678959
Short name T400
Test name
Test status
Simulation time 6723216038 ps
CPU time 13.78 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:07:04 PM PDT 24
Peak memory 211560 kb
Host smart-ac3ea5af-2ff4-4be8-af98-77020f8b9a6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126678959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2126678959
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3574034565
Short name T435
Test name
Test status
Simulation time 33831975992 ps
CPU time 75.02 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:08:22 PM PDT 24
Peak memory 211540 kb
Host smart-e0edb5b0-34cb-460d-becc-16237d5314fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574034565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3574034565
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3654648715
Short name T109
Test name
Test status
Simulation time 346437464 ps
CPU time 4.32 seconds
Started Jun 24 06:06:54 PM PDT 24
Finished Jun 24 06:06:59 PM PDT 24
Peak memory 218692 kb
Host smart-2ebf22ea-dfba-45b8-b827-6f3b6aa30ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654648715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3654648715
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3876039046
Short name T426
Test name
Test status
Simulation time 3479879567 ps
CPU time 11.87 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:07:02 PM PDT 24
Peak memory 219672 kb
Host smart-eea7f15f-6090-4f24-a604-9a97c87b45cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876039046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3876039046
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3030052206
Short name T132
Test name
Test status
Simulation time 24752612634 ps
CPU time 73.04 seconds
Started Jun 24 06:06:48 PM PDT 24
Finished Jun 24 06:08:02 PM PDT 24
Peak memory 219696 kb
Host smart-f9cccb9b-bced-4b65-8511-f1305539b347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030052206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3030052206
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3426733897
Short name T386
Test name
Test status
Simulation time 4834653522 ps
CPU time 11.66 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:07:04 PM PDT 24
Peak memory 219740 kb
Host smart-5343adb8-b749-4fe0-978b-5ab40b215381
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426733897 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3426733897
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3149078566
Short name T463
Test name
Test status
Simulation time 1960215483 ps
CPU time 14.82 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:22 PM PDT 24
Peak memory 211408 kb
Host smart-09e55a09-e4ba-4ea2-bcca-a4fd8620c77b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149078566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3149078566
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3259613718
Short name T75
Test name
Test status
Simulation time 2140891494 ps
CPU time 27.02 seconds
Started Jun 24 06:06:54 PM PDT 24
Finished Jun 24 06:07:22 PM PDT 24
Peak memory 211452 kb
Host smart-f3bd139e-687e-49c1-a779-ebab9be0e8b3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259613718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3259613718
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2946813772
Short name T418
Test name
Test status
Simulation time 5885663581 ps
CPU time 13.64 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:07:04 PM PDT 24
Peak memory 211868 kb
Host smart-61148a88-7136-435e-b38f-efa85e0f5d22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946813772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2946813772
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2864661580
Short name T406
Test name
Test status
Simulation time 2425788157 ps
CPU time 13.65 seconds
Started Jun 24 06:06:57 PM PDT 24
Finished Jun 24 06:07:11 PM PDT 24
Peak memory 219632 kb
Host smart-0fe731ff-95fe-4da0-b81e-6eea4e9f039d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864661580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2864661580
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2260958431
Short name T447
Test name
Test status
Simulation time 2080156183 ps
CPU time 77.32 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:08:07 PM PDT 24
Peak memory 212636 kb
Host smart-22170a14-7ba5-4967-a02f-2e38b7bbbcc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260958431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2260958431
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.660919746
Short name T376
Test name
Test status
Simulation time 663347066 ps
CPU time 4.76 seconds
Started Jun 24 06:07:03 PM PDT 24
Finished Jun 24 06:07:12 PM PDT 24
Peak memory 219580 kb
Host smart-184d3c09-5f07-42f3-8202-49375d6224ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660919746 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.660919746
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3692301370
Short name T87
Test name
Test status
Simulation time 21355270698 ps
CPU time 10.93 seconds
Started Jun 24 06:06:52 PM PDT 24
Finished Jun 24 06:07:04 PM PDT 24
Peak memory 219852 kb
Host smart-21f1d2d2-070b-47ea-af01-05697bce42a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692301370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3692301370
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.31606106
Short name T125
Test name
Test status
Simulation time 9317424798 ps
CPU time 79.03 seconds
Started Jun 24 06:06:48 PM PDT 24
Finished Jun 24 06:08:08 PM PDT 24
Peak memory 218604 kb
Host smart-d2ad0814-cc23-4973-a474-52fe99b9e839
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31606106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pass
thru_mem_tl_intg_err.31606106
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2821841121
Short name T433
Test name
Test status
Simulation time 1069448475 ps
CPU time 10.54 seconds
Started Jun 24 06:06:54 PM PDT 24
Finished Jun 24 06:07:06 PM PDT 24
Peak memory 219568 kb
Host smart-c05f475c-97fd-4598-a765-0f74f7648d53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821841121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2821841121
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1102096974
Short name T437
Test name
Test status
Simulation time 2426153352 ps
CPU time 15.71 seconds
Started Jun 24 06:07:02 PM PDT 24
Finished Jun 24 06:07:21 PM PDT 24
Peak memory 219668 kb
Host smart-2dcb533e-18d6-4410-8036-d47291615f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102096974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1102096974
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2669992830
Short name T64
Test name
Test status
Simulation time 28393566389 ps
CPU time 44.83 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:07:37 PM PDT 24
Peak memory 212680 kb
Host smart-51c68edf-cc4b-45bd-b67f-689fc56b7831
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669992830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2669992830
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3480498874
Short name T458
Test name
Test status
Simulation time 102556181 ps
CPU time 4.86 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:06:57 PM PDT 24
Peak memory 219516 kb
Host smart-14dd33c2-e068-4afa-b7fd-dce6dc6f5faf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480498874 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3480498874
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.19670589
Short name T86
Test name
Test status
Simulation time 111902177 ps
CPU time 4.1 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:06:57 PM PDT 24
Peak memory 211372 kb
Host smart-9ecf7ebd-f620-4db2-8e16-564ea1d8306e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19670589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.19670589
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4047366035
Short name T414
Test name
Test status
Simulation time 28028902698 ps
CPU time 58.32 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:07:48 PM PDT 24
Peak memory 211584 kb
Host smart-8ab5c6f5-cdf5-4f92-a725-9773b8f9ee4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047366035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4047366035
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3894806601
Short name T452
Test name
Test status
Simulation time 9020226190 ps
CPU time 14.43 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:07:06 PM PDT 24
Peak memory 219672 kb
Host smart-a42d2e9a-385e-4d5d-a2a9-7d3a62e06697
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894806601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3894806601
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3837304792
Short name T415
Test name
Test status
Simulation time 23663520170 ps
CPU time 19.31 seconds
Started Jun 24 06:06:47 PM PDT 24
Finished Jun 24 06:07:07 PM PDT 24
Peak memory 219664 kb
Host smart-785cf521-d54a-4304-a5c7-48348bf182be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837304792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3837304792
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1335955917
Short name T128
Test name
Test status
Simulation time 6711106889 ps
CPU time 75.32 seconds
Started Jun 24 06:06:51 PM PDT 24
Finished Jun 24 06:08:08 PM PDT 24
Peak memory 219692 kb
Host smart-6e6f3153-112a-41ca-bfb0-8e63bd927600
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335955917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1335955917
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2560609298
Short name T417
Test name
Test status
Simulation time 1277131283 ps
CPU time 11.96 seconds
Started Jun 24 06:06:50 PM PDT 24
Finished Jun 24 06:07:03 PM PDT 24
Peak memory 219820 kb
Host smart-73cd989f-61ff-4c4c-8dce-78c5ac5d7875
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560609298 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2560609298
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3626321123
Short name T421
Test name
Test status
Simulation time 1662969883 ps
CPU time 13.83 seconds
Started Jun 24 06:06:48 PM PDT 24
Finished Jun 24 06:07:03 PM PDT 24
Peak memory 211416 kb
Host smart-fc933736-04cb-4b34-aaa4-393ab20463a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626321123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3626321123
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2968675011
Short name T438
Test name
Test status
Simulation time 5605072550 ps
CPU time 52.63 seconds
Started Jun 24 06:06:54 PM PDT 24
Finished Jun 24 06:07:48 PM PDT 24
Peak memory 211576 kb
Host smart-6d5b810c-a896-4fcf-9ed3-3b4432fb9f2a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968675011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2968675011
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2403783019
Short name T112
Test name
Test status
Simulation time 1038475736 ps
CPU time 12.13 seconds
Started Jun 24 06:06:57 PM PDT 24
Finished Jun 24 06:07:10 PM PDT 24
Peak memory 211516 kb
Host smart-da68910d-9bfc-41fe-b6b6-0b3118b00bdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403783019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2403783019
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2262493796
Short name T384
Test name
Test status
Simulation time 2293014777 ps
CPU time 10.03 seconds
Started Jun 24 06:06:54 PM PDT 24
Finished Jun 24 06:07:05 PM PDT 24
Peak memory 219664 kb
Host smart-12288e6a-6e5d-4c37-98a2-b2efa2ea42a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262493796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2262493796
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3358323413
Short name T140
Test name
Test status
Simulation time 1349933094 ps
CPU time 74.86 seconds
Started Jun 24 06:06:49 PM PDT 24
Finished Jun 24 06:08:05 PM PDT 24
Peak memory 219568 kb
Host smart-eb7123b5-a4f7-432c-8227-fc4ef336ab30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358323413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3358323413
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.771705036
Short name T156
Test name
Test status
Simulation time 1424686499 ps
CPU time 8.54 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:05 PM PDT 24
Peak memory 211084 kb
Host smart-27ba2e53-c01e-4930-aa6d-5459edc67ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771705036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.771705036
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3843948698
Short name T309
Test name
Test status
Simulation time 9137012377 ps
CPU time 172.8 seconds
Started Jun 24 05:28:40 PM PDT 24
Finished Jun 24 05:31:34 PM PDT 24
Peak memory 233996 kb
Host smart-e43404ef-605f-4eb0-a90f-808e2d128d66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843948698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3843948698
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1964843656
Short name T315
Test name
Test status
Simulation time 2355472667 ps
CPU time 23.39 seconds
Started Jun 24 05:28:41 PM PDT 24
Finished Jun 24 05:29:05 PM PDT 24
Peak memory 211752 kb
Host smart-86a40798-1580-4142-97b8-a16e990c2680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964843656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1964843656
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1973352136
Short name T338
Test name
Test status
Simulation time 9470925250 ps
CPU time 15.84 seconds
Started Jun 24 05:28:41 PM PDT 24
Finished Jun 24 05:28:57 PM PDT 24
Peak memory 211248 kb
Host smart-9ca0ac6a-9270-4d05-bca5-a2237a32dfd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973352136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1973352136
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2659251815
Short name T25
Test name
Test status
Simulation time 7061821151 ps
CPU time 111.1 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:30:47 PM PDT 24
Peak memory 233800 kb
Host smart-a81b32ae-bbc1-47ac-993b-ffa0e886dd0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659251815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2659251815
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3395971296
Short name T83
Test name
Test status
Simulation time 10636505167 ps
CPU time 31.02 seconds
Started Jun 24 05:28:40 PM PDT 24
Finished Jun 24 05:29:12 PM PDT 24
Peak memory 214272 kb
Host smart-8bcb800d-684b-4896-a369-fe70c3a4278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395971296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3395971296
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.153283742
Short name T271
Test name
Test status
Simulation time 2800704784 ps
CPU time 39.98 seconds
Started Jun 24 05:28:40 PM PDT 24
Finished Jun 24 05:29:20 PM PDT 24
Peak memory 216200 kb
Host smart-92f9323d-e23f-40eb-9f2a-9f08720ef81f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153283742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.153283742
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2341562460
Short name T265
Test name
Test status
Simulation time 5494786995 ps
CPU time 11.64 seconds
Started Jun 24 05:29:00 PM PDT 24
Finished Jun 24 05:29:13 PM PDT 24
Peak memory 211044 kb
Host smart-6f753978-cdb6-4a2f-be45-8e57f50f132f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341562460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2341562460
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1201252110
Short name T293
Test name
Test status
Simulation time 13482241351 ps
CPU time 255.82 seconds
Started Jun 24 05:28:53 PM PDT 24
Finished Jun 24 05:33:10 PM PDT 24
Peak memory 212640 kb
Host smart-bb1f10d2-eccb-4230-8e73-49e610857f5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201252110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1201252110
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.564635647
Short name T263
Test name
Test status
Simulation time 5042722909 ps
CPU time 25.21 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:20 PM PDT 24
Peak memory 212508 kb
Host smart-c69e331b-22c8-4f27-acb7-6a965d294c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564635647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.564635647
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2240542850
Short name T235
Test name
Test status
Simulation time 8510510916 ps
CPU time 12.78 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:29:12 PM PDT 24
Peak memory 211236 kb
Host smart-39e3e9c1-f9d9-4d61-b9de-a572c1279b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240542850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2240542850
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1184770336
Short name T26
Test name
Test status
Simulation time 3845854189 ps
CPU time 62.63 seconds
Started Jun 24 05:28:53 PM PDT 24
Finished Jun 24 05:29:57 PM PDT 24
Peak memory 236296 kb
Host smart-32cd000a-6109-4e6d-a40d-a7f2d9d0ffd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184770336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1184770336
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.444671426
Short name T333
Test name
Test status
Simulation time 1321786068 ps
CPU time 18.41 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:14 PM PDT 24
Peak memory 211736 kb
Host smart-c8260de4-1101-4eb2-9745-10100669aefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444671426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.444671426
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2645911515
Short name T99
Test name
Test status
Simulation time 39852991236 ps
CPU time 648.1 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:39:45 PM PDT 24
Peak memory 235736 kb
Host smart-a36ee93a-c6f7-4d29-b3f5-41ef776b134b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645911515 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2645911515
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2151185466
Short name T234
Test name
Test status
Simulation time 182833353 ps
CPU time 4.37 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:17 PM PDT 24
Peak memory 211096 kb
Host smart-00596dc0-3f03-4c96-a4ee-906078bbb64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151185466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2151185466
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2191258721
Short name T227
Test name
Test status
Simulation time 199476289350 ps
CPU time 288.65 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:33:56 PM PDT 24
Peak memory 234668 kb
Host smart-0bd91d18-0279-43c0-b088-dae799226209
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191258721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2191258721
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1241481803
Short name T300
Test name
Test status
Simulation time 15772566438 ps
CPU time 35.4 seconds
Started Jun 24 05:29:05 PM PDT 24
Finished Jun 24 05:29:41 PM PDT 24
Peak memory 212136 kb
Host smart-6736214a-d4ba-4c01-b83f-2a13ed258338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241481803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1241481803
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1762637415
Short name T326
Test name
Test status
Simulation time 1547176721 ps
CPU time 5.72 seconds
Started Jun 24 05:29:08 PM PDT 24
Finished Jun 24 05:29:15 PM PDT 24
Peak memory 211216 kb
Host smart-0ff78552-1625-4e82-8fcf-250747b8581a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762637415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1762637415
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2213805220
Short name T330
Test name
Test status
Simulation time 4197147765 ps
CPU time 37.57 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:29:45 PM PDT 24
Peak memory 213968 kb
Host smart-ceedf348-19a4-4f30-b5ae-229b8290b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213805220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2213805220
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2785816221
Short name T82
Test name
Test status
Simulation time 4562232238 ps
CPU time 46.53 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:29:53 PM PDT 24
Peak memory 216380 kb
Host smart-d542a935-82be-4e8a-b602-23cb98cc6a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785816221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2785816221
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3651405224
Short name T73
Test name
Test status
Simulation time 2576387315 ps
CPU time 7.47 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:29:15 PM PDT 24
Peak memory 211148 kb
Host smart-ce0261dd-4d1c-4a05-a7db-21b1c5f7305b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651405224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3651405224
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.82047818
Short name T369
Test name
Test status
Simulation time 15723126845 ps
CPU time 135.9 seconds
Started Jun 24 05:29:08 PM PDT 24
Finished Jun 24 05:31:25 PM PDT 24
Peak memory 237596 kb
Host smart-975d4586-ded0-4ff5-bcf8-b1b618d933c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82047818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_co
rrupt_sig_fatal_chk.82047818
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1156535967
Short name T350
Test name
Test status
Simulation time 15535420981 ps
CPU time 28.53 seconds
Started Jun 24 05:29:05 PM PDT 24
Finished Jun 24 05:29:35 PM PDT 24
Peak memory 211220 kb
Host smart-97c6fb34-8616-4608-a21c-602eff6037cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156535967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1156535967
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1563371269
Short name T275
Test name
Test status
Simulation time 1169624267 ps
CPU time 10.28 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:29:18 PM PDT 24
Peak memory 211252 kb
Host smart-dba24957-b965-4177-8b96-c56fba017ce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563371269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1563371269
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2409493977
Short name T268
Test name
Test status
Simulation time 781902465 ps
CPU time 15.85 seconds
Started Jun 24 05:29:09 PM PDT 24
Finished Jun 24 05:29:27 PM PDT 24
Peak memory 211188 kb
Host smart-daae08e1-df02-4675-8906-5eae245dd321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409493977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2409493977
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1181277346
Short name T289
Test name
Test status
Simulation time 23310167995 ps
CPU time 68.71 seconds
Started Jun 24 05:29:07 PM PDT 24
Finished Jun 24 05:30:17 PM PDT 24
Peak memory 216064 kb
Host smart-94cc48fc-4e3d-4a2d-a7c7-52622908a87c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181277346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1181277346
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2267838409
Short name T348
Test name
Test status
Simulation time 6850635354 ps
CPU time 14.47 seconds
Started Jun 24 05:29:07 PM PDT 24
Finished Jun 24 05:29:23 PM PDT 24
Peak memory 211392 kb
Host smart-3dffff03-caf3-414a-b040-fcd4f391fdf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267838409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2267838409
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2881184149
Short name T212
Test name
Test status
Simulation time 48740286700 ps
CPU time 251.95 seconds
Started Jun 24 05:29:05 PM PDT 24
Finished Jun 24 05:33:19 PM PDT 24
Peak memory 233472 kb
Host smart-0a2b2f1c-acc6-49d2-afdf-fbadaf520572
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881184149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2881184149
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3560756858
Short name T175
Test name
Test status
Simulation time 15127782774 ps
CPU time 32.06 seconds
Started Jun 24 05:29:05 PM PDT 24
Finished Jun 24 05:29:39 PM PDT 24
Peak memory 212212 kb
Host smart-befb6bbd-265e-4432-907d-df56edeb0ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560756858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3560756858
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1416150831
Short name T334
Test name
Test status
Simulation time 2070584169 ps
CPU time 8.43 seconds
Started Jun 24 05:29:09 PM PDT 24
Finished Jun 24 05:29:20 PM PDT 24
Peak memory 211228 kb
Host smart-94541acc-73aa-41f9-bb7f-d6fb43d97209
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416150831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1416150831
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.584421056
Short name T285
Test name
Test status
Simulation time 13750230981 ps
CPU time 30.22 seconds
Started Jun 24 05:29:05 PM PDT 24
Finished Jun 24 05:29:36 PM PDT 24
Peak memory 213708 kb
Host smart-bbe16963-c5ca-415e-a3bc-b06dba10ca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584421056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.584421056
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4153096682
Short name T324
Test name
Test status
Simulation time 17072478503 ps
CPU time 18.87 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:32 PM PDT 24
Peak memory 212412 kb
Host smart-d62bb912-49fa-4cae-a03f-bf7e1d9b47da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153096682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4153096682
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3381627185
Short name T104
Test name
Test status
Simulation time 91980143 ps
CPU time 4.43 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:18 PM PDT 24
Peak memory 211088 kb
Host smart-abe0fe74-d9a1-4598-8f38-0f8b2ab8b8ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381627185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3381627185
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3960968946
Short name T244
Test name
Test status
Simulation time 23750920632 ps
CPU time 226.8 seconds
Started Jun 24 05:29:05 PM PDT 24
Finished Jun 24 05:32:53 PM PDT 24
Peak memory 234956 kb
Host smart-dc0e4cf5-1b2e-4e1d-b433-78c7fcd740e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960968946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3960968946
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2441044335
Short name T176
Test name
Test status
Simulation time 702569285 ps
CPU time 5.68 seconds
Started Jun 24 05:29:08 PM PDT 24
Finished Jun 24 05:29:15 PM PDT 24
Peak memory 211192 kb
Host smart-f9f956c6-fb92-4564-b1b5-651c660cecd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2441044335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2441044335
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.4203368681
Short name T223
Test name
Test status
Simulation time 8601765240 ps
CPU time 38.35 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:52 PM PDT 24
Peak memory 214132 kb
Host smart-3cf9d687-4644-421f-a925-b485f69d3407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203368681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.4203368681
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2011733599
Short name T323
Test name
Test status
Simulation time 25758338898 ps
CPU time 52.76 seconds
Started Jun 24 05:29:07 PM PDT 24
Finished Jun 24 05:30:01 PM PDT 24
Peak memory 215796 kb
Host smart-73f3b3a2-32ad-42f4-8d5b-6fad79a82396
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011733599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2011733599
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2053006360
Short name T344
Test name
Test status
Simulation time 346590307 ps
CPU time 4.3 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:18 PM PDT 24
Peak memory 211088 kb
Host smart-9973a8a2-3c55-4325-a3bc-34a390379729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053006360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2053006360
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3375943957
Short name T242
Test name
Test status
Simulation time 60169527669 ps
CPU time 350.11 seconds
Started Jun 24 05:29:12 PM PDT 24
Finished Jun 24 05:35:06 PM PDT 24
Peak memory 234680 kb
Host smart-b5caa459-2b3e-4d09-b7b9-566155193659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375943957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3375943957
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2244703148
Short name T31
Test name
Test status
Simulation time 13995687081 ps
CPU time 29.3 seconds
Started Jun 24 05:29:08 PM PDT 24
Finished Jun 24 05:29:39 PM PDT 24
Peak memory 212292 kb
Host smart-4a0c51d2-8ccb-4bca-9f5f-b49babf7702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244703148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2244703148
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.195598674
Short name T284
Test name
Test status
Simulation time 1202135790 ps
CPU time 9.74 seconds
Started Jun 24 05:29:09 PM PDT 24
Finished Jun 24 05:29:21 PM PDT 24
Peak memory 211244 kb
Host smart-e01f13eb-037e-45a0-8fb5-046704c4509d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195598674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.195598674
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2068708698
Short name T247
Test name
Test status
Simulation time 1723406986 ps
CPU time 21.99 seconds
Started Jun 24 05:29:12 PM PDT 24
Finished Jun 24 05:29:37 PM PDT 24
Peak memory 212896 kb
Host smart-ec56537e-0d6f-460d-882c-e9f252bbffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068708698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2068708698
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1821962606
Short name T170
Test name
Test status
Simulation time 414626605 ps
CPU time 24.37 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:29:32 PM PDT 24
Peak memory 215256 kb
Host smart-3f7d3426-ecfe-450a-b7b7-afa498ce93b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821962606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1821962606
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2626197478
Short name T169
Test name
Test status
Simulation time 8307328760 ps
CPU time 16.27 seconds
Started Jun 24 05:29:09 PM PDT 24
Finished Jun 24 05:29:27 PM PDT 24
Peak memory 211044 kb
Host smart-34e37bbd-a1de-480e-9069-c05a53091d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626197478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2626197478
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3222036706
Short name T207
Test name
Test status
Simulation time 39155463252 ps
CPU time 280.43 seconds
Started Jun 24 05:29:16 PM PDT 24
Finished Jun 24 05:34:00 PM PDT 24
Peak memory 233868 kb
Host smart-3ed94568-de38-4d56-bcaa-81e003620dbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222036706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3222036706
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.441110776
Short name T160
Test name
Test status
Simulation time 1754993148 ps
CPU time 15.26 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:29:22 PM PDT 24
Peak memory 211192 kb
Host smart-1881a421-7a91-4485-b9ab-71e52547d2e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441110776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.441110776
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.273370598
Short name T100
Test name
Test status
Simulation time 1546978491 ps
CPU time 12.02 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 213804 kb
Host smart-6c4eebaf-271d-4583-834b-6cf0648dedf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273370598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.273370598
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4007774077
Short name T168
Test name
Test status
Simulation time 6747371627 ps
CPU time 40.34 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:29:48 PM PDT 24
Peak memory 215364 kb
Host smart-72072e55-8376-49c3-b715-030d24c0fe57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007774077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4007774077
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3559454668
Short name T103
Test name
Test status
Simulation time 1325272063 ps
CPU time 12.19 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:27 PM PDT 24
Peak memory 211052 kb
Host smart-e4aa2ccf-e7e0-4f81-b7d5-8681edbf09ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559454668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3559454668
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1731164596
Short name T312
Test name
Test status
Simulation time 288108418700 ps
CPU time 305.67 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 05:34:23 PM PDT 24
Peak memory 224632 kb
Host smart-e1cb45e3-ee42-403f-83c6-43a8c7a7684e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731164596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1731164596
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1358853017
Short name T267
Test name
Test status
Simulation time 4132378424 ps
CPU time 34.65 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:48 PM PDT 24
Peak memory 211760 kb
Host smart-bab7aa0f-62a9-4c47-9f77-5925e04700e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358853017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1358853017
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4027196436
Short name T4
Test name
Test status
Simulation time 2168233715 ps
CPU time 17.69 seconds
Started Jun 24 05:29:09 PM PDT 24
Finished Jun 24 05:29:28 PM PDT 24
Peak memory 211200 kb
Host smart-4ecb1389-0da4-4bf6-9e40-5caa3fe1a6e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027196436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4027196436
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.278355371
Short name T153
Test name
Test status
Simulation time 13472995856 ps
CPU time 29.35 seconds
Started Jun 24 05:29:16 PM PDT 24
Finished Jun 24 05:29:49 PM PDT 24
Peak memory 214032 kb
Host smart-1bcd14bb-d317-4c98-af59-8e7e952f038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278355371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.278355371
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2946073751
Short name T258
Test name
Test status
Simulation time 4145658726 ps
CPU time 43.94 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 05:30:02 PM PDT 24
Peak memory 216084 kb
Host smart-d2bfa76a-13a0-4c38-8b06-78005bb15e4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946073751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2946073751
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1736066920
Short name T353
Test name
Test status
Simulation time 2708780168 ps
CPU time 12.18 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 211152 kb
Host smart-520dad29-aab2-4f18-99bf-ef27552d245c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736066920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1736066920
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2648878132
Short name T294
Test name
Test status
Simulation time 36429681277 ps
CPU time 130.55 seconds
Started Jun 24 05:29:13 PM PDT 24
Finished Jun 24 05:31:27 PM PDT 24
Peak memory 212472 kb
Host smart-340fabe7-2678-44ff-aa2c-518ab75acb6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648878132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2648878132
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2717401611
Short name T202
Test name
Test status
Simulation time 173810905 ps
CPU time 9.39 seconds
Started Jun 24 05:29:12 PM PDT 24
Finished Jun 24 05:29:25 PM PDT 24
Peak memory 211800 kb
Host smart-67403422-6860-473c-95aa-4c19ec0458f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717401611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2717401611
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.191777406
Short name T298
Test name
Test status
Simulation time 1645163517 ps
CPU time 14.22 seconds
Started Jun 24 05:29:12 PM PDT 24
Finished Jun 24 05:29:30 PM PDT 24
Peak memory 211208 kb
Host smart-dcfb43a2-6ec5-4c65-8956-0c4d1e9cda20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=191777406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.191777406
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.4201706953
Short name T336
Test name
Test status
Simulation time 3307457122 ps
CPU time 32.33 seconds
Started Jun 24 05:29:16 PM PDT 24
Finished Jun 24 05:29:52 PM PDT 24
Peak memory 213472 kb
Host smart-11e25bd0-5193-483b-b8f1-82f4d58fda05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201706953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.4201706953
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1391163802
Short name T191
Test name
Test status
Simulation time 63543601094 ps
CPU time 48.66 seconds
Started Jun 24 05:29:13 PM PDT 24
Finished Jun 24 05:30:05 PM PDT 24
Peak memory 216680 kb
Host smart-325c0a70-8e72-44da-a3ac-27d26afe60a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391163802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1391163802
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3774399791
Short name T155
Test name
Test status
Simulation time 999931881 ps
CPU time 10.49 seconds
Started Jun 24 05:29:13 PM PDT 24
Finished Jun 24 05:29:27 PM PDT 24
Peak memory 211088 kb
Host smart-b1b61cb7-d342-4edd-87c2-c3d7e9415c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774399791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3774399791
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3462508917
Short name T359
Test name
Test status
Simulation time 456817888181 ps
CPU time 257.32 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:33:32 PM PDT 24
Peak memory 237896 kb
Host smart-aa5bb08e-3d19-45ea-b267-526498cea275
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462508917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3462508917
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.705379145
Short name T302
Test name
Test status
Simulation time 8537282909 ps
CPU time 22.03 seconds
Started Jun 24 05:29:13 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 211904 kb
Host smart-6b80b92b-425e-4a32-8bcd-e627e5418f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705379145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.705379145
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4282147656
Short name T318
Test name
Test status
Simulation time 2891554787 ps
CPU time 13.9 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 211304 kb
Host smart-3e02e2dc-7b92-4f95-81c1-56b3e820dd66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282147656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4282147656
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1494833044
Short name T15
Test name
Test status
Simulation time 192477543 ps
CPU time 9.93 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 05:29:28 PM PDT 24
Peak memory 213004 kb
Host smart-7e94c371-5344-4334-b30f-c309212b9bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494833044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1494833044
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1821586063
Short name T61
Test name
Test status
Simulation time 589478260 ps
CPU time 31.18 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:46 PM PDT 24
Peak memory 216888 kb
Host smart-34dc0e4b-8807-41d6-ae86-04512b642808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821586063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1821586063
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.987799792
Short name T239
Test name
Test status
Simulation time 6304235060 ps
CPU time 12.61 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:28 PM PDT 24
Peak memory 211152 kb
Host smart-245e3b49-64d3-4f90-b01b-d47ef0143f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987799792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.987799792
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.489351743
Short name T366
Test name
Test status
Simulation time 794015182 ps
CPU time 60.95 seconds
Started Jun 24 05:29:08 PM PDT 24
Finished Jun 24 05:30:10 PM PDT 24
Peak memory 236456 kb
Host smart-7d6deb7b-80fa-4360-9770-d2cc42a99a04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489351743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.489351743
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.713480391
Short name T248
Test name
Test status
Simulation time 258451202 ps
CPU time 10.95 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 211176 kb
Host smart-351185e8-a2ad-4d3b-8b55-6c382dac1d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713480391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.713480391
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1127719058
Short name T158
Test name
Test status
Simulation time 482367002 ps
CPU time 8.37 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 211236 kb
Host smart-3a79a839-4c99-4521-8e9f-53565f38baf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127719058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1127719058
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1532460331
Short name T261
Test name
Test status
Simulation time 5839099312 ps
CPU time 20.98 seconds
Started Jun 24 05:29:13 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 214256 kb
Host smart-6d477cab-2a21-4a31-8181-665c8ea34eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532460331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1532460331
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4104540438
Short name T357
Test name
Test status
Simulation time 3241246687 ps
CPU time 16.35 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 05:29:34 PM PDT 24
Peak memory 211988 kb
Host smart-c8b2a0eb-4686-49e9-b3f4-e8ed27aa791a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104540438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4104540438
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.825215852
Short name T183
Test name
Test status
Simulation time 8833236320 ps
CPU time 16.97 seconds
Started Jun 24 05:28:58 PM PDT 24
Finished Jun 24 05:29:17 PM PDT 24
Peak memory 211132 kb
Host smart-78b976bb-b951-47e9-9b80-210fde6d11b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825215852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.825215852
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.443748981
Short name T356
Test name
Test status
Simulation time 29130471321 ps
CPU time 78.9 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:30:14 PM PDT 24
Peak memory 228404 kb
Host smart-5d3bd5a2-4e29-4aa7-b57d-78e12ee4053c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443748981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.443748981
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2465212449
Short name T361
Test name
Test status
Simulation time 1447949625 ps
CPU time 15.4 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:11 PM PDT 24
Peak memory 211772 kb
Host smart-89b34cb2-4593-41ff-93f7-29650dd2ab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465212449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2465212449
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1067852799
Short name T117
Test name
Test status
Simulation time 506096970 ps
CPU time 8.68 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:06 PM PDT 24
Peak memory 211492 kb
Host smart-f4e2e62e-38b5-4698-862f-0460f009606f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067852799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1067852799
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1820634267
Short name T329
Test name
Test status
Simulation time 2465821378 ps
CPU time 16.45 seconds
Started Jun 24 05:28:55 PM PDT 24
Finished Jun 24 05:29:14 PM PDT 24
Peak memory 212876 kb
Host smart-8704c9b3-ed10-4662-9a86-2b700c769439
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820634267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1820634267
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3861792090
Short name T304
Test name
Test status
Simulation time 24145511098 ps
CPU time 923.43 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:44:23 PM PDT 24
Peak memory 235776 kb
Host smart-f24a9110-4e43-4a0a-9481-20d9d71108fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861792090 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3861792090
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3311217130
Short name T189
Test name
Test status
Simulation time 3515698586 ps
CPU time 13.82 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:27 PM PDT 24
Peak memory 211152 kb
Host smart-2c7325dd-c222-4920-a811-b3baa23c0d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311217130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3311217130
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.193259912
Short name T39
Test name
Test status
Simulation time 42949613627 ps
CPU time 406.41 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:36:00 PM PDT 24
Peak memory 228312 kb
Host smart-6fb348ad-2ddb-4efa-a123-4e712e1942a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193259912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.193259912
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.851692160
Short name T58
Test name
Test status
Simulation time 499259200 ps
CPU time 13.28 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:27 PM PDT 24
Peak memory 211896 kb
Host smart-7f11d061-cf4d-4131-a041-e310c4907f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851692160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.851692160
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2560438503
Short name T203
Test name
Test status
Simulation time 2640118411 ps
CPU time 9.94 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:31 PM PDT 24
Peak memory 210280 kb
Host smart-5a3dfd73-ec7c-40e0-9c8c-7674369c0455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2560438503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2560438503
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.835098941
Short name T216
Test name
Test status
Simulation time 17511620988 ps
CPU time 34.74 seconds
Started Jun 24 05:29:17 PM PDT 24
Finished Jun 24 05:29:55 PM PDT 24
Peak memory 214432 kb
Host smart-91a993a4-7de2-478b-841e-63689660a5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835098941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.835098941
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2063296844
Short name T257
Test name
Test status
Simulation time 619577599 ps
CPU time 12.15 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:33 PM PDT 24
Peak memory 210000 kb
Host smart-e5c0eb30-75ed-4bc4-9574-18cd2207701c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063296844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2063296844
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3196733648
Short name T29
Test name
Test status
Simulation time 563993326 ps
CPU time 8.05 seconds
Started Jun 24 05:29:09 PM PDT 24
Finished Jun 24 05:29:18 PM PDT 24
Peak memory 211060 kb
Host smart-fe67b0af-b567-448e-80e1-6465340555f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196733648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3196733648
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.779793751
Short name T310
Test name
Test status
Simulation time 114410113082 ps
CPU time 233.03 seconds
Started Jun 24 05:29:13 PM PDT 24
Finished Jun 24 05:33:10 PM PDT 24
Peak memory 212528 kb
Host smart-d0146b7a-24ac-4ca1-93f3-061ff118c86c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779793751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.779793751
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3470258503
Short name T253
Test name
Test status
Simulation time 333275590 ps
CPU time 12.33 seconds
Started Jun 24 05:29:07 PM PDT 24
Finished Jun 24 05:29:21 PM PDT 24
Peak memory 211628 kb
Host smart-4ceca398-8e7a-4bcf-a574-8ea58b2e4c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470258503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3470258503
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.590694801
Short name T228
Test name
Test status
Simulation time 1795674612 ps
CPU time 5.62 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:19 PM PDT 24
Peak memory 211508 kb
Host smart-5ef2b5fe-396a-4011-8683-0486b3409214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590694801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.590694801
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1488474299
Short name T161
Test name
Test status
Simulation time 865503158 ps
CPU time 15.63 seconds
Started Jun 24 05:29:07 PM PDT 24
Finished Jun 24 05:29:24 PM PDT 24
Peak memory 213804 kb
Host smart-b6372ce5-ecb6-4e5c-a09c-7a8cb92cbc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488474299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1488474299
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4187067249
Short name T351
Test name
Test status
Simulation time 9444529096 ps
CPU time 22.9 seconds
Started Jun 24 05:29:07 PM PDT 24
Finished Jun 24 05:29:31 PM PDT 24
Peak memory 214352 kb
Host smart-0d513431-6fa8-4fad-ae47-ecf0eaf83d1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187067249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4187067249
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3561606650
Short name T311
Test name
Test status
Simulation time 348342367 ps
CPU time 4.24 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:19 PM PDT 24
Peak memory 211088 kb
Host smart-69139627-4b1a-496d-9be5-a49d7ae8e475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561606650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3561606650
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1914650591
Short name T18
Test name
Test status
Simulation time 5286118564 ps
CPU time 71.61 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:30:25 PM PDT 24
Peak memory 225372 kb
Host smart-2a99ff9a-890c-48d7-b515-f861c3ddc0aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914650591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1914650591
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.24423946
Short name T152
Test name
Test status
Simulation time 5090147699 ps
CPU time 17.67 seconds
Started Jun 24 05:29:09 PM PDT 24
Finished Jun 24 05:29:28 PM PDT 24
Peak memory 212016 kb
Host smart-8c966e51-5596-4c05-8e1d-ff6cd57a4524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24423946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.24423946
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2871371421
Short name T345
Test name
Test status
Simulation time 197043710 ps
CPU time 5.72 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:29:13 PM PDT 24
Peak memory 211136 kb
Host smart-49dffe6e-f101-4681-93e2-240a72748056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871371421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2871371421
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1928422188
Short name T209
Test name
Test status
Simulation time 360998698 ps
CPU time 10.65 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:23 PM PDT 24
Peak memory 213504 kb
Host smart-c8f1bfdb-b9c9-4a74-b120-d76ee666de79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928422188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1928422188
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3306322109
Short name T174
Test name
Test status
Simulation time 331299870 ps
CPU time 19.93 seconds
Started Jun 24 05:29:09 PM PDT 24
Finished Jun 24 05:29:30 PM PDT 24
Peak memory 215760 kb
Host smart-ee655d6d-cffa-4ddc-8873-3a0ae9cfc016
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306322109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3306322109
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2313638461
Short name T167
Test name
Test status
Simulation time 6239100423 ps
CPU time 11.77 seconds
Started Jun 24 05:29:16 PM PDT 24
Finished Jun 24 05:29:31 PM PDT 24
Peak memory 211104 kb
Host smart-1879db6b-b05e-4332-9e8b-f46d16332620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313638461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2313638461
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.569704975
Short name T38
Test name
Test status
Simulation time 63122582558 ps
CPU time 217.78 seconds
Started Jun 24 05:29:16 PM PDT 24
Finished Jun 24 05:32:57 PM PDT 24
Peak memory 236076 kb
Host smart-93e7c593-952c-4879-b09b-af826904dd31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569704975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.569704975
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3785858090
Short name T325
Test name
Test status
Simulation time 2357668921 ps
CPU time 16.69 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:30 PM PDT 24
Peak memory 212012 kb
Host smart-ab435202-4026-4644-b0e0-8e816c284d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785858090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3785858090
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.535781021
Short name T28
Test name
Test status
Simulation time 1185846654 ps
CPU time 12.46 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 211148 kb
Host smart-3803ba01-7eae-4038-a420-c3894ca954a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535781021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.535781021
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2720741718
Short name T274
Test name
Test status
Simulation time 16073534017 ps
CPU time 31.19 seconds
Started Jun 24 05:29:16 PM PDT 24
Finished Jun 24 05:29:51 PM PDT 24
Peak memory 213488 kb
Host smart-699c0b32-8c9a-48f0-9303-8ade3800ab67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720741718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2720741718
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1044297654
Short name T6
Test name
Test status
Simulation time 2934330366 ps
CPU time 14.52 seconds
Started Jun 24 05:29:13 PM PDT 24
Finished Jun 24 05:29:31 PM PDT 24
Peak memory 211152 kb
Host smart-c3b6ec35-0771-4449-bd89-61d491f2942c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044297654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1044297654
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.149276078
Short name T214
Test name
Test status
Simulation time 21386370311 ps
CPU time 205.88 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:32:40 PM PDT 24
Peak memory 228404 kb
Host smart-152a2be8-54c7-484e-991a-6f73d963cda6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149276078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.149276078
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2303367353
Short name T147
Test name
Test status
Simulation time 2503786366 ps
CPU time 17.59 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 05:29:35 PM PDT 24
Peak memory 211512 kb
Host smart-1a10ced7-abce-48c3-bba8-e3847fcb508a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303367353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2303367353
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1810313724
Short name T59
Test name
Test status
Simulation time 515222130 ps
CPU time 10.13 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:23 PM PDT 24
Peak memory 213308 kb
Host smart-46ffbc0f-47b1-46ca-a787-11703fd0a6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810313724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1810313724
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2209833276
Short name T307
Test name
Test status
Simulation time 223686023 ps
CPU time 14.09 seconds
Started Jun 24 05:29:11 PM PDT 24
Finished Jun 24 05:29:29 PM PDT 24
Peak memory 213220 kb
Host smart-a3207316-13c6-495d-8335-04b036f80e79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209833276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2209833276
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.88483845
Short name T72
Test name
Test status
Simulation time 333882422 ps
CPU time 4.38 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 211088 kb
Host smart-efcc44db-3819-4a95-97fb-6f6e7d7836f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88483845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.88483845
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1651299085
Short name T262
Test name
Test status
Simulation time 992207490 ps
CPU time 13.06 seconds
Started Jun 24 05:29:14 PM PDT 24
Finished Jun 24 05:29:30 PM PDT 24
Peak memory 211892 kb
Host smart-ca03b14d-e552-49c1-83b7-65d3a8f1f0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651299085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1651299085
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2068881645
Short name T296
Test name
Test status
Simulation time 1704742804 ps
CPU time 8.57 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:30 PM PDT 24
Peak memory 211244 kb
Host smart-19772546-5a6a-4998-a948-59f8353010d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068881645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2068881645
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1214976349
Short name T226
Test name
Test status
Simulation time 718876344 ps
CPU time 10.11 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:29:22 PM PDT 24
Peak memory 213492 kb
Host smart-cdf0312d-fda0-413c-aeaf-b2ea8f1716b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214976349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1214976349
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3745696271
Short name T98
Test name
Test status
Simulation time 518027355 ps
CPU time 8.07 seconds
Started Jun 24 05:29:13 PM PDT 24
Finished Jun 24 05:29:25 PM PDT 24
Peak memory 211060 kb
Host smart-9b4f8cb0-3a7c-4514-8841-23a193e5d8a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745696271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3745696271
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1514568845
Short name T273
Test name
Test status
Simulation time 89209536 ps
CPU time 4.29 seconds
Started Jun 24 05:29:16 PM PDT 24
Finished Jun 24 05:29:24 PM PDT 24
Peak memory 211068 kb
Host smart-a3d24074-b8c9-448a-a6bb-7fad4ad18962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514568845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1514568845
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1974853541
Short name T177
Test name
Test status
Simulation time 2753152087 ps
CPU time 88.17 seconds
Started Jun 24 05:29:17 PM PDT 24
Finished Jun 24 05:30:49 PM PDT 24
Peak memory 237836 kb
Host smart-6260ba95-f5d0-4df1-a82d-f9c80ae03bab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974853541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1974853541
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1743158780
Short name T122
Test name
Test status
Simulation time 3399346057 ps
CPU time 29.71 seconds
Started Jun 24 05:29:15 PM PDT 24
Finished Jun 24 05:29:48 PM PDT 24
Peak memory 211816 kb
Host smart-15039517-42b2-4975-9ca5-1061ce8fd9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743158780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1743158780
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3518758484
Short name T217
Test name
Test status
Simulation time 8041870371 ps
CPU time 16.79 seconds
Started Jun 24 05:29:15 PM PDT 24
Finished Jun 24 05:29:36 PM PDT 24
Peak memory 211308 kb
Host smart-36564236-a1c6-4342-83ce-b1cf185985bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518758484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3518758484
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.4154831366
Short name T171
Test name
Test status
Simulation time 21379837443 ps
CPU time 35.51 seconds
Started Jun 24 05:29:24 PM PDT 24
Finished Jun 24 05:30:01 PM PDT 24
Peak memory 214224 kb
Host smart-7c858a39-98e1-4a4c-821c-e023ceaba792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154831366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.4154831366
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2815141639
Short name T196
Test name
Test status
Simulation time 25235521630 ps
CPU time 49.19 seconds
Started Jun 24 05:29:15 PM PDT 24
Finished Jun 24 05:30:08 PM PDT 24
Peak memory 214356 kb
Host smart-a7220603-0458-4ad5-9ad8-49fc379a1ae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815141639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2815141639
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1845713053
Short name T355
Test name
Test status
Simulation time 1941134002 ps
CPU time 16.06 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:37 PM PDT 24
Peak memory 211088 kb
Host smart-b9671ef7-75c8-4172-ab05-d19dc24cdb1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845713053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1845713053
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3614496114
Short name T347
Test name
Test status
Simulation time 127426228959 ps
CPU time 547.62 seconds
Started Jun 24 05:29:19 PM PDT 24
Finished Jun 24 05:38:30 PM PDT 24
Peak memory 213584 kb
Host smart-0b031ef3-1423-48e5-9889-d7752407a18d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614496114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3614496114
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.131643013
Short name T159
Test name
Test status
Simulation time 1549004859 ps
CPU time 19.12 seconds
Started Jun 24 05:29:21 PM PDT 24
Finished Jun 24 05:29:43 PM PDT 24
Peak memory 211960 kb
Host smart-66ab506f-8fe6-4156-96f0-4e3e6b860074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131643013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.131643013
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4142368580
Short name T264
Test name
Test status
Simulation time 1604799481 ps
CPU time 14.59 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:36 PM PDT 24
Peak memory 211236 kb
Host smart-57ed8415-ede1-4334-8642-0ff8cef6ca9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142368580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4142368580
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3251658267
Short name T184
Test name
Test status
Simulation time 1979918803 ps
CPU time 21.29 seconds
Started Jun 24 05:29:19 PM PDT 24
Finished Jun 24 05:29:44 PM PDT 24
Peak memory 213496 kb
Host smart-15c6aeeb-b10a-4b72-80fd-5ef82965a24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251658267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3251658267
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2215966013
Short name T270
Test name
Test status
Simulation time 1463519523 ps
CPU time 21.09 seconds
Started Jun 24 05:29:20 PM PDT 24
Finished Jun 24 05:29:44 PM PDT 24
Peak memory 213416 kb
Host smart-e7a235b6-3800-45ac-8577-74a0683bbc9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215966013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2215966013
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1759093494
Short name T335
Test name
Test status
Simulation time 4297382112 ps
CPU time 10.77 seconds
Started Jun 24 05:29:19 PM PDT 24
Finished Jun 24 05:29:33 PM PDT 24
Peak memory 211136 kb
Host smart-feba7fde-113a-41b7-8aeb-98a884b10204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759093494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1759093494
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2642611436
Short name T249
Test name
Test status
Simulation time 1938866572 ps
CPU time 123.73 seconds
Started Jun 24 05:29:20 PM PDT 24
Finished Jun 24 05:31:27 PM PDT 24
Peak memory 228216 kb
Host smart-51522389-cd6f-472b-976d-87107c83c462
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642611436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2642611436
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1875483141
Short name T305
Test name
Test status
Simulation time 341097716 ps
CPU time 9.39 seconds
Started Jun 24 05:29:21 PM PDT 24
Finished Jun 24 05:29:33 PM PDT 24
Peak memory 211728 kb
Host smart-5f03a4a7-14c1-4968-8061-9575dc63b339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875483141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1875483141
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3184358781
Short name T283
Test name
Test status
Simulation time 1738583042 ps
CPU time 14.87 seconds
Started Jun 24 05:29:17 PM PDT 24
Finished Jun 24 05:29:36 PM PDT 24
Peak memory 211244 kb
Host smart-a4bf283d-e3cb-4d59-9b93-81b41f4a12b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184358781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3184358781
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3789904503
Short name T363
Test name
Test status
Simulation time 767062007 ps
CPU time 9.92 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:31 PM PDT 24
Peak memory 213216 kb
Host smart-6fcec93d-cf6d-4f7e-ac9b-e598c081efec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789904503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3789904503
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.928023029
Short name T16
Test name
Test status
Simulation time 7046397686 ps
CPU time 46.5 seconds
Started Jun 24 05:29:20 PM PDT 24
Finished Jun 24 05:30:09 PM PDT 24
Peak memory 216664 kb
Host smart-abcf4949-e661-4089-9467-c508f93bd3cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928023029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.928023029
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2110643751
Short name T12
Test name
Test status
Simulation time 123641968468 ps
CPU time 2345.47 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 06:08:27 PM PDT 24
Peak memory 239360 kb
Host smart-1f7c152b-fdd8-49bd-9a77-b456ef93eeb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110643751 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2110643751
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3743771957
Short name T198
Test name
Test status
Simulation time 11531966675 ps
CPU time 12.96 seconds
Started Jun 24 05:29:19 PM PDT 24
Finished Jun 24 05:29:35 PM PDT 24
Peak memory 211144 kb
Host smart-cbe723c1-50d8-4668-bd40-b2c4ffa4e3d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743771957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3743771957
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1639174255
Short name T48
Test name
Test status
Simulation time 90130859540 ps
CPU time 261.21 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:33:43 PM PDT 24
Peak memory 213580 kb
Host smart-812abcbc-851d-45bc-b954-4fa624dbfba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639174255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1639174255
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2364006441
Short name T236
Test name
Test status
Simulation time 2351625725 ps
CPU time 17.32 seconds
Started Jun 24 05:29:15 PM PDT 24
Finished Jun 24 05:29:36 PM PDT 24
Peak memory 211956 kb
Host smart-01ca714e-d441-4188-b1df-2700410e6704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364006441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2364006441
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3832798573
Short name T215
Test name
Test status
Simulation time 8634487139 ps
CPU time 15.21 seconds
Started Jun 24 05:29:24 PM PDT 24
Finished Jun 24 05:29:40 PM PDT 24
Peak memory 211276 kb
Host smart-0e12f059-46c4-4ca8-b903-9c1fee279cc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832798573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3832798573
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.594032070
Short name T81
Test name
Test status
Simulation time 3515684186 ps
CPU time 33.82 seconds
Started Jun 24 05:29:17 PM PDT 24
Finished Jun 24 05:29:55 PM PDT 24
Peak memory 213268 kb
Host smart-ca244497-b9a7-4a5f-ae0b-fbcdf36d1d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594032070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.594032070
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4006066769
Short name T121
Test name
Test status
Simulation time 4241092280 ps
CPU time 32.33 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:54 PM PDT 24
Peak memory 215828 kb
Host smart-39f7e12a-7922-47c7-abb1-7d66b534a347
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006066769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4006066769
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1032158132
Short name T346
Test name
Test status
Simulation time 347910764 ps
CPU time 4.41 seconds
Started Jun 24 05:29:00 PM PDT 24
Finished Jun 24 05:29:06 PM PDT 24
Peak memory 210980 kb
Host smart-aa138a2d-e9d3-4823-b472-b2d0901e953f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032158132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1032158132
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.54638771
Short name T40
Test name
Test status
Simulation time 6331691192 ps
CPU time 103.86 seconds
Started Jun 24 05:28:56 PM PDT 24
Finished Jun 24 05:30:42 PM PDT 24
Peak memory 228120 kb
Host smart-3980a19e-eaed-4da5-86ba-4c7b1b2b7833
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54638771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_cor
rupt_sig_fatal_chk.54638771
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2627137014
Short name T24
Test name
Test status
Simulation time 2314705728 ps
CPU time 23.22 seconds
Started Jun 24 05:28:55 PM PDT 24
Finished Jun 24 05:29:20 PM PDT 24
Peak memory 211868 kb
Host smart-e2de5782-b34d-4fd5-b832-4bed75ef7b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627137014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2627137014
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.994428154
Short name T354
Test name
Test status
Simulation time 6773322942 ps
CPU time 15.25 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:10 PM PDT 24
Peak memory 211292 kb
Host smart-f6d13631-ffa7-410b-9436-80d82c3168a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994428154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.994428154
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1030495518
Short name T20
Test name
Test status
Simulation time 274768593 ps
CPU time 54.76 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:29:54 PM PDT 24
Peak memory 236336 kb
Host smart-b683521f-a202-4c80-bc2c-f4c41769ccc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030495518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1030495518
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4083924678
Short name T142
Test name
Test status
Simulation time 4287879435 ps
CPU time 19.81 seconds
Started Jun 24 05:28:53 PM PDT 24
Finished Jun 24 05:29:14 PM PDT 24
Peak memory 213092 kb
Host smart-3d9ef78f-751a-4acb-a369-7bce7d5882d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083924678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4083924678
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.520117393
Short name T370
Test name
Test status
Simulation time 10134292343 ps
CPU time 62.36 seconds
Started Jun 24 05:28:52 PM PDT 24
Finished Jun 24 05:29:55 PM PDT 24
Peak memory 218524 kb
Host smart-ab627b26-00a3-4019-b5eb-1fd374e1024e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520117393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.520117393
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3627890667
Short name T181
Test name
Test status
Simulation time 505206631 ps
CPU time 7.68 seconds
Started Jun 24 05:29:19 PM PDT 24
Finished Jun 24 05:29:30 PM PDT 24
Peak memory 211084 kb
Host smart-78059404-caec-4a93-b4da-7a0d1f0d02da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627890667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3627890667
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.807921682
Short name T360
Test name
Test status
Simulation time 114387973320 ps
CPU time 201.03 seconds
Started Jun 24 05:29:22 PM PDT 24
Finished Jun 24 05:32:45 PM PDT 24
Peak memory 214108 kb
Host smart-f79d1239-9dff-44de-bd8b-7978f4992287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807921682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.807921682
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2699568921
Short name T241
Test name
Test status
Simulation time 4689987495 ps
CPU time 24 seconds
Started Jun 24 05:29:17 PM PDT 24
Finished Jun 24 05:29:44 PM PDT 24
Peak memory 212220 kb
Host smart-f6a54680-64c7-4264-ad19-d005245088cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699568921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2699568921
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3241253904
Short name T101
Test name
Test status
Simulation time 5771024886 ps
CPU time 15.16 seconds
Started Jun 24 05:29:19 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 211292 kb
Host smart-a0baa703-68b0-47c1-9c48-ce124f6184dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241253904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3241253904
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.4076203578
Short name T266
Test name
Test status
Simulation time 380726069 ps
CPU time 10.04 seconds
Started Jun 24 05:29:24 PM PDT 24
Finished Jun 24 05:29:35 PM PDT 24
Peak memory 213980 kb
Host smart-50c426c4-5b1d-4cf9-afbf-a01fd63cf6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076203578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.4076203578
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3670001322
Short name T148
Test name
Test status
Simulation time 8791193908 ps
CPU time 22.15 seconds
Started Jun 24 05:29:17 PM PDT 24
Finished Jun 24 05:29:43 PM PDT 24
Peak memory 214796 kb
Host smart-c782e135-31da-4787-9f99-ef90832b7230
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670001322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3670001322
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2628408627
Short name T52
Test name
Test status
Simulation time 13249204910 ps
CPU time 5019.21 seconds
Started Jun 24 05:29:25 PM PDT 24
Finished Jun 24 06:53:06 PM PDT 24
Peak memory 227576 kb
Host smart-bbf7806c-acd8-4aac-a6f1-849c35dc6463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628408627 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2628408627
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1008514800
Short name T286
Test name
Test status
Simulation time 182135295 ps
CPU time 4.38 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 211088 kb
Host smart-6f7e9746-b18f-44be-94a9-761e76c81e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008514800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1008514800
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3828387000
Short name T297
Test name
Test status
Simulation time 4927285895 ps
CPU time 95.9 seconds
Started Jun 24 05:29:17 PM PDT 24
Finished Jun 24 05:30:56 PM PDT 24
Peak memory 238012 kb
Host smart-50a8243a-3bbe-413f-91b0-d2eb70494bd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828387000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3828387000
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.899063429
Short name T281
Test name
Test status
Simulation time 17887792423 ps
CPU time 16.81 seconds
Started Jun 24 05:29:23 PM PDT 24
Finished Jun 24 05:29:42 PM PDT 24
Peak memory 212112 kb
Host smart-8a5d668f-8621-4ceb-a8e2-db7d8bfe3cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899063429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.899063429
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2161993873
Short name T368
Test name
Test status
Simulation time 191176631 ps
CPU time 5.37 seconds
Started Jun 24 05:29:24 PM PDT 24
Finished Jun 24 05:29:31 PM PDT 24
Peak memory 211212 kb
Host smart-a4a79347-3451-497c-b57c-e35ccc987495
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161993873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2161993873
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4160241202
Short name T290
Test name
Test status
Simulation time 6736900013 ps
CPU time 30.32 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:51 PM PDT 24
Peak memory 213992 kb
Host smart-0bbec09b-7dbd-41ca-9287-86628c0c86d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160241202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4160241202
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2656316325
Short name T56
Test name
Test status
Simulation time 209016304 ps
CPU time 14.02 seconds
Started Jun 24 05:29:21 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 213360 kb
Host smart-d5c116ff-7ae8-4da5-a601-36a65eb71ea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656316325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2656316325
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.311413420
Short name T50
Test name
Test status
Simulation time 208645348165 ps
CPU time 1737.44 seconds
Started Jun 24 05:29:20 PM PDT 24
Finished Jun 24 05:58:21 PM PDT 24
Peak memory 238544 kb
Host smart-cf374922-20c0-4c39-beb5-1c4bebe51de3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311413420 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.311413420
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1465293754
Short name T70
Test name
Test status
Simulation time 344713339 ps
CPU time 6.41 seconds
Started Jun 24 05:29:25 PM PDT 24
Finished Jun 24 05:29:33 PM PDT 24
Peak memory 211088 kb
Host smart-c4591337-120c-4d5e-bfa4-6bc3c1b29b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465293754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1465293754
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2529549779
Short name T250
Test name
Test status
Simulation time 57193903797 ps
CPU time 269.97 seconds
Started Jun 24 05:29:20 PM PDT 24
Finished Jun 24 05:33:53 PM PDT 24
Peak memory 236712 kb
Host smart-4c4c10ab-bc27-4b48-bebd-58a8c27a2c4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529549779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2529549779
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.119818748
Short name T179
Test name
Test status
Simulation time 10561743583 ps
CPU time 25.34 seconds
Started Jun 24 05:29:21 PM PDT 24
Finished Jun 24 05:29:49 PM PDT 24
Peak memory 212200 kb
Host smart-c3e42d59-fd4a-4b4b-826e-017f44d78861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119818748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.119818748
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2330527204
Short name T211
Test name
Test status
Simulation time 1435532122 ps
CPU time 13.94 seconds
Started Jun 24 05:29:22 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 211224 kb
Host smart-4ba70a0c-0e8f-4b85-8608-2224d598a117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330527204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2330527204
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2152908587
Short name T7
Test name
Test status
Simulation time 1935900423 ps
CPU time 17.36 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:39 PM PDT 24
Peak memory 213376 kb
Host smart-16ff047d-74a2-44f7-a09c-76b0da706158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152908587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2152908587
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4160266872
Short name T193
Test name
Test status
Simulation time 577223427 ps
CPU time 35.53 seconds
Started Jun 24 05:29:24 PM PDT 24
Finished Jun 24 05:30:01 PM PDT 24
Peak memory 215208 kb
Host smart-722b4600-d9c3-48ac-89fb-58923b29cdbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160266872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4160266872
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2123026490
Short name T208
Test name
Test status
Simulation time 1298109807 ps
CPU time 6.54 seconds
Started Jun 24 05:29:24 PM PDT 24
Finished Jun 24 05:29:32 PM PDT 24
Peak memory 211088 kb
Host smart-5879c76f-c5c3-4e1d-8907-e09d425aacb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123026490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2123026490
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1895807179
Short name T42
Test name
Test status
Simulation time 96380171319 ps
CPU time 257.84 seconds
Started Jun 24 05:29:25 PM PDT 24
Finished Jun 24 05:33:44 PM PDT 24
Peak memory 236864 kb
Host smart-7ee7af71-2d5d-449d-8448-b8c5621db9dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895807179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1895807179
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.35145354
Short name T246
Test name
Test status
Simulation time 421192185 ps
CPU time 12.8 seconds
Started Jun 24 05:29:24 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 211868 kb
Host smart-d985148b-4ead-4b3c-aa6d-a5d64feb9e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35145354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.35145354
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1508510421
Short name T165
Test name
Test status
Simulation time 1900369410 ps
CPU time 15.74 seconds
Started Jun 24 05:29:21 PM PDT 24
Finished Jun 24 05:29:39 PM PDT 24
Peak memory 210748 kb
Host smart-54926315-2f44-4915-bba0-f5c37000f997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508510421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1508510421
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2795837577
Short name T229
Test name
Test status
Simulation time 3696483367 ps
CPU time 33.91 seconds
Started Jun 24 05:29:22 PM PDT 24
Finished Jun 24 05:29:58 PM PDT 24
Peak memory 213020 kb
Host smart-d03b553c-197f-4faa-9ed9-15954efb1d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795837577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2795837577
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2995365978
Short name T362
Test name
Test status
Simulation time 9809103303 ps
CPU time 31.09 seconds
Started Jun 24 05:29:21 PM PDT 24
Finished Jun 24 05:29:55 PM PDT 24
Peak memory 214108 kb
Host smart-238f486c-6094-49d5-9af7-51d3ef6ebc5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995365978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2995365978
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1789715998
Short name T341
Test name
Test status
Simulation time 76906131375 ps
CPU time 2938.78 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 06:18:33 PM PDT 24
Peak memory 240012 kb
Host smart-fb359ba8-67e1-46bf-94a4-fef78a780a5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789715998 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1789715998
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3253793539
Short name T186
Test name
Test status
Simulation time 1557026678 ps
CPU time 12.99 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:29:47 PM PDT 24
Peak memory 211076 kb
Host smart-95cd511d-6d9a-48cd-8bcf-d0a4869acd02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253793539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3253793539
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1115028865
Short name T352
Test name
Test status
Simulation time 4158617881 ps
CPU time 34.12 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:30:08 PM PDT 24
Peak memory 211872 kb
Host smart-51f8d595-c35a-41f0-b854-54d0b6ad57fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115028865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1115028865
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.5785946
Short name T172
Test name
Test status
Simulation time 8325541877 ps
CPU time 16.84 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:29:51 PM PDT 24
Peak memory 211312 kb
Host smart-8e1262c5-9c94-4be4-9ec8-1a2173ac0d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5785946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.5785946
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.869209455
Short name T187
Test name
Test status
Simulation time 7419817000 ps
CPU time 39.75 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:30:13 PM PDT 24
Peak memory 214344 kb
Host smart-7bea6e22-2f45-4146-8ca5-e4dadbbda90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869209455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.869209455
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2176760353
Short name T339
Test name
Test status
Simulation time 1586780161 ps
CPU time 16.42 seconds
Started Jun 24 05:29:17 PM PDT 24
Finished Jun 24 05:29:37 PM PDT 24
Peak memory 211720 kb
Host smart-8904a9d4-fe55-46fa-98cf-4f7c53819b16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176760353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2176760353
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1362987554
Short name T55
Test name
Test status
Simulation time 118917246559 ps
CPU time 1108.98 seconds
Started Jun 24 05:29:25 PM PDT 24
Finished Jun 24 05:47:55 PM PDT 24
Peak memory 230644 kb
Host smart-6dcc5474-f7dd-453a-aa69-d98db0d10856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362987554 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1362987554
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2608573084
Short name T232
Test name
Test status
Simulation time 174894735 ps
CPU time 4.75 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:29:36 PM PDT 24
Peak memory 211060 kb
Host smart-fbd20247-8a93-4b39-93c8-fc4c01404a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608573084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2608573084
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3422261100
Short name T251
Test name
Test status
Simulation time 25416489756 ps
CPU time 131.35 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:31:45 PM PDT 24
Peak memory 236600 kb
Host smart-9aa2fd98-3f20-4a46-bf2c-8ecb8cc944dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422261100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3422261100
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3933641162
Short name T358
Test name
Test status
Simulation time 172605001 ps
CPU time 9.7 seconds
Started Jun 24 05:29:18 PM PDT 24
Finished Jun 24 05:29:32 PM PDT 24
Peak memory 212092 kb
Host smart-8bb3a8e2-bbb2-4ce5-a4de-b82c554fefdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933641162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3933641162
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1748682397
Short name T224
Test name
Test status
Simulation time 1275382789 ps
CPU time 11.57 seconds
Started Jun 24 05:29:21 PM PDT 24
Finished Jun 24 05:29:35 PM PDT 24
Peak memory 211136 kb
Host smart-a77957a2-0b1e-4818-9cbd-6b7f73f63dcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748682397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1748682397
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1783579347
Short name T337
Test name
Test status
Simulation time 23225324074 ps
CPU time 33.98 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:30:08 PM PDT 24
Peak memory 214152 kb
Host smart-c4a3578d-de3f-4b00-8b58-e5bbbe79b31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783579347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1783579347
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3408096082
Short name T200
Test name
Test status
Simulation time 4180866763 ps
CPU time 41.54 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:30:15 PM PDT 24
Peak memory 213620 kb
Host smart-d58b858c-4792-40a0-a6bc-72084e7bf87b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408096082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3408096082
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1601812363
Short name T62
Test name
Test status
Simulation time 4585717643 ps
CPU time 7.11 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 211392 kb
Host smart-5813556f-785d-4989-9fc3-ce3efcb5e725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601812363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1601812363
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2913717602
Short name T36
Test name
Test status
Simulation time 11622593989 ps
CPU time 106.69 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:31:18 PM PDT 24
Peak memory 234564 kb
Host smart-083306b9-6211-4cd8-b743-47dbada8dd72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913717602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2913717602
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2233450177
Short name T46
Test name
Test status
Simulation time 347817326 ps
CPU time 9.87 seconds
Started Jun 24 05:29:28 PM PDT 24
Finished Jun 24 05:29:40 PM PDT 24
Peak memory 212008 kb
Host smart-7302e934-c6f0-4166-b19d-a762ebc109cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233450177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2233450177
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3723559732
Short name T256
Test name
Test status
Simulation time 24881553491 ps
CPU time 17.03 seconds
Started Jun 24 05:29:28 PM PDT 24
Finished Jun 24 05:29:46 PM PDT 24
Peak memory 211292 kb
Host smart-4aa373ca-3798-4b87-8596-a2a879576f30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3723559732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3723559732
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.360063999
Short name T195
Test name
Test status
Simulation time 4041505836 ps
CPU time 32.87 seconds
Started Jun 24 05:29:25 PM PDT 24
Finished Jun 24 05:29:59 PM PDT 24
Peak memory 212860 kb
Host smart-47743ea2-6279-46ef-a01a-ffc3c61c341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360063999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.360063999
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3812868048
Short name T254
Test name
Test status
Simulation time 36901497863 ps
CPU time 36.57 seconds
Started Jun 24 05:29:26 PM PDT 24
Finished Jun 24 05:30:04 PM PDT 24
Peak memory 214364 kb
Host smart-8c097b26-ecd2-47e2-8301-78a76f7b9d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812868048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3812868048
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3375009822
Short name T279
Test name
Test status
Simulation time 1196807451 ps
CPU time 11.4 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:29:42 PM PDT 24
Peak memory 211088 kb
Host smart-9ecbca8c-99ce-4e31-a9b4-b541b4aee9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375009822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3375009822
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1859482812
Short name T35
Test name
Test status
Simulation time 140457302615 ps
CPU time 313.73 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:34:46 PM PDT 24
Peak memory 212452 kb
Host smart-01f680d5-4854-419f-a6fc-a7935019c9b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859482812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1859482812
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1732495819
Short name T151
Test name
Test status
Simulation time 4059395915 ps
CPU time 34.53 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:30:06 PM PDT 24
Peak memory 212108 kb
Host smart-578467b8-c67b-46b3-a7a1-319c8cc1dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732495819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1732495819
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2827896151
Short name T119
Test name
Test status
Simulation time 2010733012 ps
CPU time 16.79 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:29:48 PM PDT 24
Peak memory 211232 kb
Host smart-3aa395fb-695d-4f53-9bba-95c715f9eb01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827896151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2827896151
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.468872658
Short name T105
Test name
Test status
Simulation time 18154979844 ps
CPU time 17.32 seconds
Started Jun 24 05:29:25 PM PDT 24
Finished Jun 24 05:29:44 PM PDT 24
Peak memory 214244 kb
Host smart-dc27d2d4-443c-4733-a1ab-661ea94efa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468872658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.468872658
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2420074842
Short name T252
Test name
Test status
Simulation time 1403626767 ps
CPU time 7.76 seconds
Started Jun 24 05:29:28 PM PDT 24
Finished Jun 24 05:29:37 PM PDT 24
Peak memory 210756 kb
Host smart-101b6fce-c6af-49a4-a9b5-42a23c55ce9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420074842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2420074842
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3396728559
Short name T240
Test name
Test status
Simulation time 436117692 ps
CPU time 6.72 seconds
Started Jun 24 05:29:27 PM PDT 24
Finished Jun 24 05:29:35 PM PDT 24
Peak memory 211072 kb
Host smart-82e7c1db-c9c5-4857-8c51-4fd773544e3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396728559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3396728559
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1430536991
Short name T43
Test name
Test status
Simulation time 16612601654 ps
CPU time 185.25 seconds
Started Jun 24 05:29:26 PM PDT 24
Finished Jun 24 05:32:33 PM PDT 24
Peak memory 237580 kb
Host smart-c776d480-5030-4b2b-bf7b-ef6882a5a311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430536991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1430536991
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2813051008
Short name T225
Test name
Test status
Simulation time 4239842237 ps
CPU time 33.2 seconds
Started Jun 24 05:29:26 PM PDT 24
Finished Jun 24 05:30:01 PM PDT 24
Peak memory 212164 kb
Host smart-9b29a7d8-f984-4dae-9fc9-a8fb24acf3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813051008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2813051008
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2327976441
Short name T260
Test name
Test status
Simulation time 1372722038 ps
CPU time 9.5 seconds
Started Jun 24 05:29:27 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 211244 kb
Host smart-ff50ad81-9069-4052-9fa9-3cb05609cf52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327976441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2327976441
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.149260054
Short name T145
Test name
Test status
Simulation time 1806855372 ps
CPU time 10.24 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:29:41 PM PDT 24
Peak memory 212692 kb
Host smart-c99187b5-44e7-4d5a-85b3-b17f352416c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149260054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.149260054
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2809935720
Short name T116
Test name
Test status
Simulation time 875039777 ps
CPU time 31.74 seconds
Started Jun 24 05:29:28 PM PDT 24
Finished Jun 24 05:30:02 PM PDT 24
Peak memory 215720 kb
Host smart-15a3f482-5a02-4be8-8649-98f7a9e0bf75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809935720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2809935720
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2541461917
Short name T276
Test name
Test status
Simulation time 85674953 ps
CPU time 4.23 seconds
Started Jun 24 05:29:27 PM PDT 24
Finished Jun 24 05:29:33 PM PDT 24
Peak memory 211080 kb
Host smart-971572f4-2f62-42e3-872e-7ce3c1ea389a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541461917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2541461917
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3923206283
Short name T288
Test name
Test status
Simulation time 26243463565 ps
CPU time 279.75 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:34:10 PM PDT 24
Peak memory 212608 kb
Host smart-d25db862-f157-4f00-8922-067fe59b2130
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923206283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3923206283
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4054078937
Short name T316
Test name
Test status
Simulation time 1758007825 ps
CPU time 20.67 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:29:52 PM PDT 24
Peak memory 211436 kb
Host smart-128a36d0-752a-4651-bcb7-f82c031fbdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054078937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4054078937
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2294948750
Short name T303
Test name
Test status
Simulation time 1870810655 ps
CPU time 17.11 seconds
Started Jun 24 05:29:26 PM PDT 24
Finished Jun 24 05:29:44 PM PDT 24
Peak memory 211244 kb
Host smart-5c2bfc5b-2fe6-4fcd-8b3b-f1d5a3dc884f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294948750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2294948750
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1949354812
Short name T185
Test name
Test status
Simulation time 2119767995 ps
CPU time 13.92 seconds
Started Jun 24 05:29:28 PM PDT 24
Finished Jun 24 05:29:44 PM PDT 24
Peak memory 213224 kb
Host smart-c337f86a-4077-4c90-903d-2f56fd018dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949354812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1949354812
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2949730984
Short name T166
Test name
Test status
Simulation time 2150821365 ps
CPU time 30.92 seconds
Started Jun 24 05:29:25 PM PDT 24
Finished Jun 24 05:29:58 PM PDT 24
Peak memory 214492 kb
Host smart-a461f3b6-ba93-4ba7-a7d7-805a438d7441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949730984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2949730984
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1109243430
Short name T54
Test name
Test status
Simulation time 189328667342 ps
CPU time 1823.45 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:59:56 PM PDT 24
Peak memory 236364 kb
Host smart-86840865-ede6-48b7-b4f0-14d1ef06d33a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109243430 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1109243430
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1753897562
Short name T313
Test name
Test status
Simulation time 2127949764 ps
CPU time 11.7 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:07 PM PDT 24
Peak memory 211068 kb
Host smart-7a7851fc-1f32-4369-82f9-fea8399ea1a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753897562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1753897562
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.375416319
Short name T301
Test name
Test status
Simulation time 90861889684 ps
CPU time 444.89 seconds
Started Jun 24 05:28:53 PM PDT 24
Finished Jun 24 05:36:19 PM PDT 24
Peak memory 234700 kb
Host smart-5d012459-b33a-4690-9f3f-0013dcb658f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375416319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.375416319
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1801947219
Short name T308
Test name
Test status
Simulation time 2568299957 ps
CPU time 18.33 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:15 PM PDT 24
Peak memory 212132 kb
Host smart-cd0344b7-46c1-481c-a263-2ded28b9c899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801947219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1801947219
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2993642729
Short name T340
Test name
Test status
Simulation time 1677292829 ps
CPU time 15.05 seconds
Started Jun 24 05:29:09 PM PDT 24
Finished Jun 24 05:29:27 PM PDT 24
Peak memory 211228 kb
Host smart-a670575d-694d-4c14-aace-1bb04215e8b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993642729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2993642729
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2936733372
Short name T21
Test name
Test status
Simulation time 207586358 ps
CPU time 99.51 seconds
Started Jun 24 05:28:55 PM PDT 24
Finished Jun 24 05:30:38 PM PDT 24
Peak memory 237868 kb
Host smart-f6ce07a9-6264-44cd-bb84-7e86105b2702
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936733372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2936733372
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.343421980
Short name T60
Test name
Test status
Simulation time 3615065764 ps
CPU time 30.93 seconds
Started Jun 24 05:28:56 PM PDT 24
Finished Jun 24 05:29:30 PM PDT 24
Peak memory 213700 kb
Host smart-cba9b5d6-cfee-4afd-a1e1-3484aab6f971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343421980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.343421980
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.11272192
Short name T218
Test name
Test status
Simulation time 17208937810 ps
CPU time 32.39 seconds
Started Jun 24 05:28:58 PM PDT 24
Finished Jun 24 05:29:32 PM PDT 24
Peak memory 214308 kb
Host smart-5bb8276b-65d4-406d-9982-2fcc4b37b6ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11272192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.rom_ctrl_stress_all.11272192
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.875297411
Short name T322
Test name
Test status
Simulation time 9184085794 ps
CPU time 17.08 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:29:48 PM PDT 24
Peak memory 211124 kb
Host smart-bcc05f76-9447-4426-9fc0-165d6c259adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875297411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.875297411
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2816132600
Short name T306
Test name
Test status
Simulation time 7474066891 ps
CPU time 94.29 seconds
Started Jun 24 05:29:28 PM PDT 24
Finished Jun 24 05:31:03 PM PDT 24
Peak memory 225160 kb
Host smart-68916cb6-b986-4503-af4f-7a26f0fa8f4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816132600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2816132600
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.268047643
Short name T237
Test name
Test status
Simulation time 3233777089 ps
CPU time 29.04 seconds
Started Jun 24 05:29:29 PM PDT 24
Finished Jun 24 05:30:00 PM PDT 24
Peak memory 211804 kb
Host smart-469aa046-d327-47dd-85c5-4ae42ba01f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268047643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.268047643
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.555124553
Short name T178
Test name
Test status
Simulation time 2006376656 ps
CPU time 16.48 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:29:48 PM PDT 24
Peak memory 211240 kb
Host smart-3fe6b7b8-4ad6-4dad-a454-6d9839df24dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555124553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.555124553
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3256343063
Short name T180
Test name
Test status
Simulation time 4364692785 ps
CPU time 39.34 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:30:11 PM PDT 24
Peak memory 213792 kb
Host smart-a009cc03-32bf-44cf-a15d-565204b74b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256343063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3256343063
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3609645219
Short name T343
Test name
Test status
Simulation time 4809507095 ps
CPU time 53.75 seconds
Started Jun 24 05:29:27 PM PDT 24
Finished Jun 24 05:30:22 PM PDT 24
Peak memory 213760 kb
Host smart-758bbcd9-8ef0-40e4-8c67-42e8756542c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609645219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3609645219
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2671765441
Short name T157
Test name
Test status
Simulation time 414852250 ps
CPU time 4.24 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:29:36 PM PDT 24
Peak memory 211092 kb
Host smart-a981a986-2a87-4195-8606-ca76eb3fac78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671765441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2671765441
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3183400170
Short name T292
Test name
Test status
Simulation time 19504297706 ps
CPU time 227.25 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:33:19 PM PDT 24
Peak memory 237492 kb
Host smart-cd2cb136-5f1b-4985-906c-4a1a4c857963
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183400170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3183400170
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1585834219
Short name T44
Test name
Test status
Simulation time 665243352 ps
CPU time 9.34 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:29:42 PM PDT 24
Peak memory 211780 kb
Host smart-851e7771-d681-4dab-bd5c-b550c0d895d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585834219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1585834219
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2270207959
Short name T182
Test name
Test status
Simulation time 7604902461 ps
CPU time 15.91 seconds
Started Jun 24 05:29:33 PM PDT 24
Finished Jun 24 05:29:50 PM PDT 24
Peak memory 211308 kb
Host smart-2a336005-20c7-4226-a03e-8fc696c4409c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270207959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2270207959
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2206615212
Short name T314
Test name
Test status
Simulation time 3630385135 ps
CPU time 23.03 seconds
Started Jun 24 05:29:31 PM PDT 24
Finished Jun 24 05:29:56 PM PDT 24
Peak memory 213452 kb
Host smart-6a0fdcd1-a231-4761-8dfb-515cfd9eefe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206615212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2206615212
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2788539417
Short name T238
Test name
Test status
Simulation time 4505597627 ps
CPU time 54.6 seconds
Started Jun 24 05:29:31 PM PDT 24
Finished Jun 24 05:30:27 PM PDT 24
Peak memory 216644 kb
Host smart-c8a4f8ea-9bdc-48a4-b136-a903ba1c8974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788539417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2788539417
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2285063629
Short name T291
Test name
Test status
Simulation time 1035025429 ps
CPU time 10.21 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:29:43 PM PDT 24
Peak memory 211088 kb
Host smart-1efc1550-6e3e-4aa5-b562-8af8ce877640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285063629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2285063629
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2982868231
Short name T150
Test name
Test status
Simulation time 2315834320 ps
CPU time 16.66 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:29:49 PM PDT 24
Peak memory 211976 kb
Host smart-cfed61ac-7cd7-4c31-a8b9-50c5e29afa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982868231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2982868231
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.457918594
Short name T255
Test name
Test status
Simulation time 464546967 ps
CPU time 5.65 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:29:37 PM PDT 24
Peak memory 211244 kb
Host smart-47d89b87-86a0-406d-8d27-5c6cbe5edbbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457918594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.457918594
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1845967638
Short name T243
Test name
Test status
Simulation time 2905063268 ps
CPU time 25.79 seconds
Started Jun 24 05:29:28 PM PDT 24
Finished Jun 24 05:29:56 PM PDT 24
Peak memory 215140 kb
Host smart-392caa4e-2e2f-41b4-88c1-934f0ae7f145
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845967638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1845967638
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.478910947
Short name T190
Test name
Test status
Simulation time 1823698754 ps
CPU time 14.92 seconds
Started Jun 24 05:29:36 PM PDT 24
Finished Jun 24 05:29:52 PM PDT 24
Peak memory 210996 kb
Host smart-5f23682a-8fd6-4411-9d23-ffdf9801dd31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478910947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.478910947
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.465540719
Short name T41
Test name
Test status
Simulation time 99338920182 ps
CPU time 300.85 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:34:35 PM PDT 24
Peak memory 237644 kb
Host smart-fa51c824-cfa0-4881-95f6-6dc3dd3111f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465540719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.465540719
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3190981193
Short name T5
Test name
Test status
Simulation time 1650753048 ps
CPU time 18.47 seconds
Started Jun 24 05:29:36 PM PDT 24
Finished Jun 24 05:29:56 PM PDT 24
Peak memory 211856 kb
Host smart-1f6d86be-5b09-4be6-af53-6f8531640293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190981193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3190981193
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2113331012
Short name T231
Test name
Test status
Simulation time 7080830220 ps
CPU time 16.07 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:29:49 PM PDT 24
Peak memory 211292 kb
Host smart-f3dfc428-c5dd-4310-8104-d81961fd16ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113331012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2113331012
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2201978375
Short name T2
Test name
Test status
Simulation time 3335391436 ps
CPU time 34.47 seconds
Started Jun 24 05:29:36 PM PDT 24
Finished Jun 24 05:30:11 PM PDT 24
Peak memory 213636 kb
Host smart-b50767a0-d229-43d9-bd13-2c19d3999345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201978375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2201978375
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2149514100
Short name T17
Test name
Test status
Simulation time 20249117157 ps
CPU time 35.06 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:30:09 PM PDT 24
Peak memory 213992 kb
Host smart-d511bed5-f06e-445d-b040-ff3aa6b8bede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149514100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2149514100
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3434652171
Short name T49
Test name
Test status
Simulation time 56807472341 ps
CPU time 2136.49 seconds
Started Jun 24 05:29:36 PM PDT 24
Finished Jun 24 06:05:13 PM PDT 24
Peak memory 243880 kb
Host smart-76a43ccd-45e0-4676-96f7-7e00b714dfd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434652171 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3434652171
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2950151690
Short name T188
Test name
Test status
Simulation time 334419725 ps
CPU time 4.27 seconds
Started Jun 24 05:29:36 PM PDT 24
Finished Jun 24 05:29:41 PM PDT 24
Peak memory 211000 kb
Host smart-72cb0849-1ad6-44af-bb05-42f286abd8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950151690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2950151690
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3475530767
Short name T320
Test name
Test status
Simulation time 21665745633 ps
CPU time 208.76 seconds
Started Jun 24 05:29:40 PM PDT 24
Finished Jun 24 05:33:09 PM PDT 24
Peak memory 228408 kb
Host smart-2c9b0df0-a0d9-4bca-8fa4-042954e56c85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475530767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3475530767
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1585974542
Short name T327
Test name
Test status
Simulation time 347775592 ps
CPU time 9.13 seconds
Started Jun 24 05:29:35 PM PDT 24
Finished Jun 24 05:29:45 PM PDT 24
Peak memory 211752 kb
Host smart-b13c9480-b33b-40b2-833f-ec355897c9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585974542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1585974542
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3842257108
Short name T201
Test name
Test status
Simulation time 1445606445 ps
CPU time 13.19 seconds
Started Jun 24 05:29:37 PM PDT 24
Finished Jun 24 05:29:51 PM PDT 24
Peak memory 211156 kb
Host smart-71c66ff7-fd4a-46cb-a80a-85cf3e894d0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842257108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3842257108
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.637155567
Short name T163
Test name
Test status
Simulation time 3273192305 ps
CPU time 32.03 seconds
Started Jun 24 05:29:30 PM PDT 24
Finished Jun 24 05:30:04 PM PDT 24
Peak memory 213276 kb
Host smart-7fd48353-a2b3-4be7-a128-3b0d48d1623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637155567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.637155567
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2905347083
Short name T332
Test name
Test status
Simulation time 24826697141 ps
CPU time 42.49 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:30:16 PM PDT 24
Peak memory 219232 kb
Host smart-764b819b-08a5-4f93-a186-5f5624cd6b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905347083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2905347083
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3108925684
Short name T126
Test name
Test status
Simulation time 83368739220 ps
CPU time 2767.01 seconds
Started Jun 24 05:29:28 PM PDT 24
Finished Jun 24 06:15:37 PM PDT 24
Peak memory 235796 kb
Host smart-29695fb3-9f5e-4513-901b-e2db0ea52064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108925684 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3108925684
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.265602637
Short name T194
Test name
Test status
Simulation time 378149249 ps
CPU time 4.3 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 211088 kb
Host smart-9f463e82-d28c-4065-86b7-3e2e1208cd22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265602637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.265602637
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.382915866
Short name T204
Test name
Test status
Simulation time 348020613 ps
CPU time 9.6 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:29:43 PM PDT 24
Peak memory 211856 kb
Host smart-00ab35a4-00ed-424a-8c3a-c27a67389203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382915866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.382915866
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2077827444
Short name T106
Test name
Test status
Simulation time 700395404 ps
CPU time 9.9 seconds
Started Jun 24 05:29:39 PM PDT 24
Finished Jun 24 05:29:50 PM PDT 24
Peak memory 211244 kb
Host smart-76f17972-5972-4f95-a41d-3c81896dc938
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2077827444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2077827444
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.678412033
Short name T245
Test name
Test status
Simulation time 5842315417 ps
CPU time 17.43 seconds
Started Jun 24 05:29:33 PM PDT 24
Finished Jun 24 05:29:52 PM PDT 24
Peak memory 213624 kb
Host smart-7d02c02a-4e05-4775-b38c-ab17a507226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678412033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.678412033
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2285089529
Short name T164
Test name
Test status
Simulation time 4323615748 ps
CPU time 14.14 seconds
Started Jun 24 05:29:39 PM PDT 24
Finished Jun 24 05:29:54 PM PDT 24
Peak memory 212144 kb
Host smart-9ffc39b8-0d88-49b2-b56b-896ddbe9fe9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285089529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2285089529
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2146943773
Short name T219
Test name
Test status
Simulation time 88362288 ps
CPU time 4.4 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 211088 kb
Host smart-b596503f-55e1-4328-ad77-f791a0acd1a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146943773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2146943773
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3536837796
Short name T349
Test name
Test status
Simulation time 4073459034 ps
CPU time 67.77 seconds
Started Jun 24 05:29:40 PM PDT 24
Finished Jun 24 05:30:49 PM PDT 24
Peak memory 228408 kb
Host smart-367dabab-eea6-4d88-b9b1-8e3257aad041
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536837796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3536837796
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2815938985
Short name T57
Test name
Test status
Simulation time 8227353000 ps
CPU time 15.75 seconds
Started Jun 24 05:29:27 PM PDT 24
Finished Jun 24 05:29:45 PM PDT 24
Peak memory 211200 kb
Host smart-4665510d-7c50-4b79-b214-194c60c96baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815938985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2815938985
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2926763856
Short name T371
Test name
Test status
Simulation time 96293962 ps
CPU time 5.43 seconds
Started Jun 24 05:29:40 PM PDT 24
Finished Jun 24 05:29:47 PM PDT 24
Peak memory 211240 kb
Host smart-1da5f81f-82aa-4aa9-9370-eebb42626880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926763856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2926763856
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3039897289
Short name T162
Test name
Test status
Simulation time 8854914878 ps
CPU time 28.97 seconds
Started Jun 24 05:29:40 PM PDT 24
Finished Jun 24 05:30:10 PM PDT 24
Peak memory 214096 kb
Host smart-83a24640-d5f4-4c3d-9e3f-2c284d219d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039897289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3039897289
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.411564204
Short name T213
Test name
Test status
Simulation time 40306831002 ps
CPU time 93.38 seconds
Started Jun 24 05:29:40 PM PDT 24
Finished Jun 24 05:31:14 PM PDT 24
Peak memory 217720 kb
Host smart-dc43c8ee-1f5d-4ff1-a8a4-d256fdb6893a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411564204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.411564204
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3929374465
Short name T206
Test name
Test status
Simulation time 4165887659 ps
CPU time 16.21 seconds
Started Jun 24 05:29:45 PM PDT 24
Finished Jun 24 05:30:02 PM PDT 24
Peak memory 211156 kb
Host smart-607ca9bf-e589-47cf-a4a6-f8c98265bc9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929374465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3929374465
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1444975266
Short name T27
Test name
Test status
Simulation time 41282123173 ps
CPU time 210.91 seconds
Started Jun 24 05:29:37 PM PDT 24
Finished Jun 24 05:33:09 PM PDT 24
Peak memory 212560 kb
Host smart-68c42a4f-8756-4413-a1cc-a6004f0caa40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444975266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1444975266
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1864700493
Short name T342
Test name
Test status
Simulation time 4271120127 ps
CPU time 22.35 seconds
Started Jun 24 05:29:43 PM PDT 24
Finished Jun 24 05:30:06 PM PDT 24
Peak memory 212184 kb
Host smart-5eda4545-dea7-479c-a2de-e28ccd300c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864700493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1864700493
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.733088772
Short name T210
Test name
Test status
Simulation time 1598192306 ps
CPU time 10.22 seconds
Started Jun 24 05:29:45 PM PDT 24
Finished Jun 24 05:29:56 PM PDT 24
Peak memory 211248 kb
Host smart-7a8b23d5-d391-44c4-b370-aebcb78689ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733088772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.733088772
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1297282643
Short name T154
Test name
Test status
Simulation time 6295011154 ps
CPU time 20 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:29:54 PM PDT 24
Peak memory 213860 kb
Host smart-36dbeb88-5e16-4535-b449-0578f8ca14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297282643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1297282643
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1959104843
Short name T192
Test name
Test status
Simulation time 5366844098 ps
CPU time 56.49 seconds
Started Jun 24 05:29:32 PM PDT 24
Finished Jun 24 05:30:30 PM PDT 24
Peak memory 218052 kb
Host smart-9a4f96b1-89b1-4b54-ad46-e0dcf3b51f0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959104843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1959104843
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.548627356
Short name T33
Test name
Test status
Simulation time 23605541535 ps
CPU time 301.88 seconds
Started Jun 24 05:29:39 PM PDT 24
Finished Jun 24 05:34:41 PM PDT 24
Peak memory 228316 kb
Host smart-3ea24d87-c380-4da9-b5af-cf0fbeba9478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548627356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.548627356
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.345356257
Short name T287
Test name
Test status
Simulation time 434068404 ps
CPU time 12.51 seconds
Started Jun 24 05:29:44 PM PDT 24
Finished Jun 24 05:29:57 PM PDT 24
Peak memory 212260 kb
Host smart-23fbe275-8f24-4aee-be64-54d8cc13ed3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345356257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.345356257
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1207929304
Short name T328
Test name
Test status
Simulation time 4102667881 ps
CPU time 12.17 seconds
Started Jun 24 05:29:38 PM PDT 24
Finished Jun 24 05:29:51 PM PDT 24
Peak memory 211308 kb
Host smart-c03fd0d0-b49e-4492-90eb-fad2ad5056f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207929304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1207929304
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2578980850
Short name T14
Test name
Test status
Simulation time 182436898 ps
CPU time 10.17 seconds
Started Jun 24 05:29:37 PM PDT 24
Finished Jun 24 05:29:48 PM PDT 24
Peak memory 212976 kb
Host smart-2aaeaa6e-25c9-4f28-b278-31d6850d2bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578980850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2578980850
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2636802714
Short name T143
Test name
Test status
Simulation time 55775958222 ps
CPU time 43.4 seconds
Started Jun 24 05:29:43 PM PDT 24
Finished Jun 24 05:30:27 PM PDT 24
Peak memory 217056 kb
Host smart-6f044204-5534-4b7a-8990-8986f8ebacd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636802714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2636802714
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2945282468
Short name T299
Test name
Test status
Simulation time 43183765842 ps
CPU time 1764.09 seconds
Started Jun 24 05:29:37 PM PDT 24
Finished Jun 24 05:59:02 PM PDT 24
Peak memory 231988 kb
Host smart-5f36f16d-9b66-4ca6-951f-010cc8df4565
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945282468 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2945282468
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2644979483
Short name T205
Test name
Test status
Simulation time 691870635 ps
CPU time 8.66 seconds
Started Jun 24 05:29:48 PM PDT 24
Finished Jun 24 05:29:57 PM PDT 24
Peak memory 211092 kb
Host smart-c3576040-5780-416a-a6e2-276b4299a770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644979483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2644979483
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3298165468
Short name T37
Test name
Test status
Simulation time 24012634304 ps
CPU time 268.91 seconds
Started Jun 24 05:29:42 PM PDT 24
Finished Jun 24 05:34:12 PM PDT 24
Peak memory 213808 kb
Host smart-de0cadac-1198-4491-b25c-f0bb7a85c074
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298165468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3298165468
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2226636910
Short name T45
Test name
Test status
Simulation time 340847479 ps
CPU time 9.68 seconds
Started Jun 24 05:29:39 PM PDT 24
Finished Jun 24 05:29:50 PM PDT 24
Peak memory 212000 kb
Host smart-842524e4-1a91-4049-960a-72c8acd63c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226636910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2226636910
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3920042384
Short name T118
Test name
Test status
Simulation time 1100853425 ps
CPU time 11.89 seconds
Started Jun 24 05:29:37 PM PDT 24
Finished Jun 24 05:29:50 PM PDT 24
Peak memory 211268 kb
Host smart-773d1740-29fb-4c4f-a859-17b1a5edd64a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920042384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3920042384
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2230429153
Short name T295
Test name
Test status
Simulation time 617866929 ps
CPU time 14.37 seconds
Started Jun 24 05:29:36 PM PDT 24
Finished Jun 24 05:29:52 PM PDT 24
Peak memory 213188 kb
Host smart-99f4c6bc-451d-4937-a5e8-c930de6fb4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230429153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2230429153
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2443054506
Short name T259
Test name
Test status
Simulation time 10777218680 ps
CPU time 15.43 seconds
Started Jun 24 05:29:37 PM PDT 24
Finished Jun 24 05:29:54 PM PDT 24
Peak memory 215024 kb
Host smart-df156902-aab6-4c15-9079-ffbff5f6b866
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443054506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2443054506
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3439886702
Short name T71
Test name
Test status
Simulation time 320880764 ps
CPU time 5.53 seconds
Started Jun 24 05:29:04 PM PDT 24
Finished Jun 24 05:29:11 PM PDT 24
Peak memory 211088 kb
Host smart-7babfe2f-cceb-428f-a634-ff44b88acad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439886702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3439886702
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.4005183700
Short name T220
Test name
Test status
Simulation time 44029896196 ps
CPU time 367.91 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:35:07 PM PDT 24
Peak memory 233364 kb
Host smart-e99c584f-3984-4cff-acac-28dcf7173265
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005183700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.4005183700
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1907529742
Short name T272
Test name
Test status
Simulation time 4603703711 ps
CPU time 20.93 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:18 PM PDT 24
Peak memory 212280 kb
Host smart-8a075a09-d1b1-4102-a385-69c83e65e387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907529742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1907529742
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3791208055
Short name T221
Test name
Test status
Simulation time 1496986160 ps
CPU time 13.82 seconds
Started Jun 24 05:28:54 PM PDT 24
Finished Jun 24 05:29:09 PM PDT 24
Peak memory 211228 kb
Host smart-c70c306d-9515-4195-b467-6c6fcbe51288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791208055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3791208055
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2742381236
Short name T365
Test name
Test status
Simulation time 16864419341 ps
CPU time 33.62 seconds
Started Jun 24 05:28:56 PM PDT 24
Finished Jun 24 05:29:32 PM PDT 24
Peak memory 213576 kb
Host smart-f5074c84-d771-4602-a7ee-d101f13e684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742381236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2742381236
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1223857035
Short name T364
Test name
Test status
Simulation time 1022680016 ps
CPU time 12.85 seconds
Started Jun 24 05:28:52 PM PDT 24
Finished Jun 24 05:29:06 PM PDT 24
Peak memory 211068 kb
Host smart-78071f27-63d5-4853-bb91-537b7f5bfcd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223857035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1223857035
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2745786838
Short name T22
Test name
Test status
Simulation time 951157340 ps
CPU time 9.84 seconds
Started Jun 24 05:28:55 PM PDT 24
Finished Jun 24 05:29:08 PM PDT 24
Peak memory 211080 kb
Host smart-33f757f1-a0ef-4089-bb82-2fb0ec537bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745786838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2745786838
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1761630907
Short name T30
Test name
Test status
Simulation time 24101324621 ps
CPU time 313.5 seconds
Started Jun 24 05:28:55 PM PDT 24
Finished Jun 24 05:34:11 PM PDT 24
Peak memory 212676 kb
Host smart-edd8e5f5-cabf-4746-95b2-688822541eda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761630907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1761630907
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.342847566
Short name T277
Test name
Test status
Simulation time 19042983271 ps
CPU time 16.68 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:29:16 PM PDT 24
Peak memory 211828 kb
Host smart-516b58e3-6608-40f6-a257-9d0254921b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342847566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.342847566
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3544928922
Short name T34
Test name
Test status
Simulation time 7065424391 ps
CPU time 15.66 seconds
Started Jun 24 05:28:53 PM PDT 24
Finished Jun 24 05:29:09 PM PDT 24
Peak memory 211308 kb
Host smart-d713b09c-c72f-41b3-ab4f-71bde246c319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3544928922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3544928922
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2711146183
Short name T9
Test name
Test status
Simulation time 750322778 ps
CPU time 10.63 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:29:10 PM PDT 24
Peak memory 213616 kb
Host smart-086847bb-51b4-45da-a3ed-c1ee48a1410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711146183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2711146183
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.735695419
Short name T173
Test name
Test status
Simulation time 1751184748 ps
CPU time 12.76 seconds
Started Jun 24 05:28:55 PM PDT 24
Finished Jun 24 05:29:10 PM PDT 24
Peak memory 211792 kb
Host smart-58312771-f8c7-44cd-b526-4ea1c6bfe765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735695419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.735695419
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3047874753
Short name T321
Test name
Test status
Simulation time 2978275658 ps
CPU time 12.78 seconds
Started Jun 24 05:28:55 PM PDT 24
Finished Jun 24 05:29:11 PM PDT 24
Peak memory 211044 kb
Host smart-c4c7205a-3d8c-4390-ba80-fafa42e8c5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047874753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3047874753
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.339288557
Short name T233
Test name
Test status
Simulation time 47028215281 ps
CPU time 161.28 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:31:41 PM PDT 24
Peak memory 212592 kb
Host smart-979eb209-1ea4-43cc-88bc-8151ca1412bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339288557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.339288557
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.371544704
Short name T319
Test name
Test status
Simulation time 260221147 ps
CPU time 11.41 seconds
Started Jun 24 05:28:56 PM PDT 24
Finished Jun 24 05:29:10 PM PDT 24
Peak memory 211824 kb
Host smart-3197be67-5b94-4214-8a60-4d4544aff08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371544704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.371544704
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3398310675
Short name T199
Test name
Test status
Simulation time 3578908857 ps
CPU time 11.19 seconds
Started Jun 24 05:28:56 PM PDT 24
Finished Jun 24 05:29:10 PM PDT 24
Peak memory 211296 kb
Host smart-16286dd5-982d-40a0-a6ca-2ab1379a2801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398310675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3398310675
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1557422566
Short name T144
Test name
Test status
Simulation time 184695376 ps
CPU time 10.2 seconds
Started Jun 24 05:28:56 PM PDT 24
Finished Jun 24 05:29:09 PM PDT 24
Peak memory 212228 kb
Host smart-793b0051-763a-4d43-bbf8-dd906613cf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557422566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1557422566
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2007052497
Short name T280
Test name
Test status
Simulation time 1845986676 ps
CPU time 29.81 seconds
Started Jun 24 05:28:55 PM PDT 24
Finished Jun 24 05:29:28 PM PDT 24
Peak memory 216012 kb
Host smart-e7a47532-a6c3-430a-a221-068d1e78723c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007052497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2007052497
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2379332557
Short name T367
Test name
Test status
Simulation time 2714367815 ps
CPU time 12.53 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:29:12 PM PDT 24
Peak memory 211048 kb
Host smart-c065c080-9875-4547-aafb-264b456d7a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379332557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2379332557
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.436486291
Short name T282
Test name
Test status
Simulation time 68166558744 ps
CPU time 360.64 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:35:00 PM PDT 24
Peak memory 238204 kb
Host smart-d930c365-1a60-4003-963d-2fa8120d459f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436486291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.436486291
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1924959810
Short name T278
Test name
Test status
Simulation time 2049769570 ps
CPU time 21.4 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:29:20 PM PDT 24
Peak memory 212080 kb
Host smart-8d3248d8-2949-43fc-978e-93e8bbaf8058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924959810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1924959810
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2961329340
Short name T197
Test name
Test status
Simulation time 3687069462 ps
CPU time 11.41 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:29:11 PM PDT 24
Peak memory 211308 kb
Host smart-49592fa7-04eb-4950-8d64-00ac46c8f2b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961329340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2961329340
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.856828042
Short name T230
Test name
Test status
Simulation time 3778474940 ps
CPU time 43.79 seconds
Started Jun 24 05:28:56 PM PDT 24
Finished Jun 24 05:29:42 PM PDT 24
Peak memory 212344 kb
Host smart-b6ae3572-69ec-465e-b628-8e353f9f3f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856828042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.856828042
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1689793556
Short name T222
Test name
Test status
Simulation time 25311472217 ps
CPU time 39.91 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:29:39 PM PDT 24
Peak memory 214232 kb
Host smart-6e9bc6fc-c6ad-49c3-93ba-cceb896df7f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689793556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1689793556
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.894628059
Short name T317
Test name
Test status
Simulation time 347967895 ps
CPU time 4.25 seconds
Started Jun 24 05:29:06 PM PDT 24
Finished Jun 24 05:29:12 PM PDT 24
Peak memory 210980 kb
Host smart-13bd5f67-3f91-4c58-96cf-b4b956941707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894628059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.894628059
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3460987947
Short name T32
Test name
Test status
Simulation time 674051045941 ps
CPU time 333.54 seconds
Started Jun 24 05:29:08 PM PDT 24
Finished Jun 24 05:34:42 PM PDT 24
Peak memory 228400 kb
Host smart-d4ddadc0-9df3-4320-9e4f-777438927e02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460987947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3460987947
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1151098201
Short name T149
Test name
Test status
Simulation time 2796939329 ps
CPU time 18.29 seconds
Started Jun 24 05:29:07 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 211760 kb
Host smart-2f67eed9-7e26-46da-9c3f-a453786e6386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151098201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1151098201
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4257506195
Short name T120
Test name
Test status
Simulation time 35874629753 ps
CPU time 18.31 seconds
Started Jun 24 05:29:05 PM PDT 24
Finished Jun 24 05:29:24 PM PDT 24
Peak memory 211308 kb
Host smart-7f6c585f-7f7a-42eb-9608-07976a4d589e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257506195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4257506195
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2822539496
Short name T102
Test name
Test status
Simulation time 15939102262 ps
CPU time 25.78 seconds
Started Jun 24 05:28:57 PM PDT 24
Finished Jun 24 05:29:25 PM PDT 24
Peak memory 213916 kb
Host smart-ccf900e3-4dac-4386-a593-3d48a8e949c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822539496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2822539496
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3385797928
Short name T269
Test name
Test status
Simulation time 4541503628 ps
CPU time 34.9 seconds
Started Jun 24 05:29:07 PM PDT 24
Finished Jun 24 05:29:43 PM PDT 24
Peak memory 216888 kb
Host smart-7e8414ae-7fa4-4121-bdf6-1511c29aa61f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385797928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3385797928
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2670400912
Short name T53
Test name
Test status
Simulation time 161222910851 ps
CPU time 646.82 seconds
Started Jun 24 05:29:10 PM PDT 24
Finished Jun 24 05:40:00 PM PDT 24
Peak memory 229352 kb
Host smart-e1e42dce-e598-4175-a123-b81eb399143a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670400912 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.2670400912
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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