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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.67 100.00 98.28 97.45 98.37


Total test records in report: 467
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T297 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.423085239 Jun 25 04:53:44 PM PDT 24 Jun 25 04:54:42 PM PDT 24 1744617925 ps
T298 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3138118033 Jun 25 04:53:09 PM PDT 24 Jun 25 04:53:36 PM PDT 24 11388771357 ps
T299 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1581129132 Jun 25 04:54:42 PM PDT 24 Jun 25 04:54:53 PM PDT 24 2367063037 ps
T300 /workspace/coverage/default/7.rom_ctrl_stress_all.2129705210 Jun 25 04:53:36 PM PDT 24 Jun 25 04:53:44 PM PDT 24 388328989 ps
T301 /workspace/coverage/default/1.rom_ctrl_stress_all.1745344599 Jun 25 04:53:16 PM PDT 24 Jun 25 04:53:55 PM PDT 24 15396940841 ps
T302 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2031213219 Jun 25 04:53:52 PM PDT 24 Jun 25 04:53:59 PM PDT 24 418192482 ps
T99 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2476956558 Jun 25 04:54:26 PM PDT 24 Jun 25 04:54:35 PM PDT 24 1138995847 ps
T303 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1335890604 Jun 25 04:53:42 PM PDT 24 Jun 25 04:53:55 PM PDT 24 4783659121 ps
T304 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1402466651 Jun 25 04:54:55 PM PDT 24 Jun 25 04:55:12 PM PDT 24 1996176850 ps
T305 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1415512541 Jun 25 04:53:17 PM PDT 24 Jun 25 04:53:35 PM PDT 24 2204673635 ps
T306 /workspace/coverage/default/15.rom_ctrl_smoke.2703868671 Jun 25 04:53:51 PM PDT 24 Jun 25 04:54:23 PM PDT 24 3220507312 ps
T307 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1519522462 Jun 25 04:54:41 PM PDT 24 Jun 25 04:58:56 PM PDT 24 26253432408 ps
T308 /workspace/coverage/default/21.rom_ctrl_alert_test.1956526235 Jun 25 04:54:04 PM PDT 24 Jun 25 04:54:17 PM PDT 24 1307227824 ps
T309 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.138775131 Jun 25 04:53:19 PM PDT 24 Jun 25 04:53:36 PM PDT 24 2005668273 ps
T310 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.224269132 Jun 25 04:54:34 PM PDT 24 Jun 25 04:55:59 PM PDT 24 4976728186 ps
T311 /workspace/coverage/default/19.rom_ctrl_stress_all.1538697225 Jun 25 04:53:50 PM PDT 24 Jun 25 04:54:03 PM PDT 24 512773074 ps
T312 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2667579312 Jun 25 04:53:55 PM PDT 24 Jun 25 04:54:22 PM PDT 24 2953683864 ps
T313 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.464768915 Jun 25 04:53:51 PM PDT 24 Jun 25 04:54:03 PM PDT 24 168598190 ps
T314 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4043641218 Jun 25 04:54:17 PM PDT 24 Jun 25 04:57:11 PM PDT 24 2497307571 ps
T315 /workspace/coverage/default/41.rom_ctrl_stress_all.2403738378 Jun 25 04:54:41 PM PDT 24 Jun 25 04:54:58 PM PDT 24 303553288 ps
T316 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4077236829 Jun 25 04:53:19 PM PDT 24 Jun 25 04:53:35 PM PDT 24 1585329569 ps
T317 /workspace/coverage/default/5.rom_ctrl_smoke.2301450336 Jun 25 04:53:25 PM PDT 24 Jun 25 04:53:46 PM PDT 24 1481384865 ps
T318 /workspace/coverage/default/6.rom_ctrl_alert_test.4057578879 Jun 25 04:53:35 PM PDT 24 Jun 25 04:53:46 PM PDT 24 1804786391 ps
T319 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1403536297 Jun 25 04:53:54 PM PDT 24 Jun 25 04:59:56 PM PDT 24 42543693174 ps
T320 /workspace/coverage/default/2.rom_ctrl_smoke.921199548 Jun 25 04:53:20 PM PDT 24 Jun 25 04:53:31 PM PDT 24 177640096 ps
T321 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2680681977 Jun 25 04:53:34 PM PDT 24 Jun 25 04:53:44 PM PDT 24 528942367 ps
T322 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3675252767 Jun 25 04:54:24 PM PDT 24 Jun 25 04:54:51 PM PDT 24 2775904432 ps
T323 /workspace/coverage/default/20.rom_ctrl_stress_all.3667240234 Jun 25 04:54:07 PM PDT 24 Jun 25 04:55:12 PM PDT 24 28564723927 ps
T324 /workspace/coverage/default/31.rom_ctrl_alert_test.1133919552 Jun 25 04:54:26 PM PDT 24 Jun 25 04:54:38 PM PDT 24 2175745611 ps
T325 /workspace/coverage/default/44.rom_ctrl_smoke.830362542 Jun 25 04:54:42 PM PDT 24 Jun 25 04:54:54 PM PDT 24 189852107 ps
T326 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3188021312 Jun 25 04:53:36 PM PDT 24 Jun 25 05:05:25 PM PDT 24 80914088886 ps
T327 /workspace/coverage/default/13.rom_ctrl_stress_all.2519587679 Jun 25 04:53:44 PM PDT 24 Jun 25 04:53:54 PM PDT 24 288635222 ps
T328 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4255615104 Jun 25 04:54:24 PM PDT 24 Jun 25 04:59:19 PM PDT 24 51232275070 ps
T329 /workspace/coverage/default/25.rom_ctrl_alert_test.2700899937 Jun 25 04:54:15 PM PDT 24 Jun 25 04:54:32 PM PDT 24 8191715082 ps
T330 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1547643149 Jun 25 04:54:54 PM PDT 24 Jun 25 04:55:24 PM PDT 24 6898734278 ps
T331 /workspace/coverage/default/24.rom_ctrl_smoke.2062051047 Jun 25 04:54:16 PM PDT 24 Jun 25 04:54:45 PM PDT 24 4183447599 ps
T332 /workspace/coverage/default/48.rom_ctrl_alert_test.1974160280 Jun 25 04:55:05 PM PDT 24 Jun 25 04:55:17 PM PDT 24 2037306663 ps
T333 /workspace/coverage/default/40.rom_ctrl_alert_test.3012973738 Jun 25 04:54:44 PM PDT 24 Jun 25 04:54:55 PM PDT 24 979975576 ps
T334 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1394091524 Jun 25 04:53:26 PM PDT 24 Jun 25 04:53:37 PM PDT 24 179444337 ps
T335 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2547592556 Jun 25 04:54:46 PM PDT 24 Jun 25 04:55:04 PM PDT 24 7398547663 ps
T336 /workspace/coverage/default/47.rom_ctrl_smoke.2510789669 Jun 25 04:54:54 PM PDT 24 Jun 25 04:55:17 PM PDT 24 1946763867 ps
T337 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1313040093 Jun 25 04:54:26 PM PDT 24 Jun 25 04:54:33 PM PDT 24 1540466684 ps
T338 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.996170415 Jun 25 04:54:18 PM PDT 24 Jun 25 04:54:46 PM PDT 24 6346237375 ps
T339 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1221712929 Jun 25 04:54:33 PM PDT 24 Jun 25 04:55:04 PM PDT 24 3613082035 ps
T340 /workspace/coverage/default/49.rom_ctrl_stress_all.1318746663 Jun 25 04:55:04 PM PDT 24 Jun 25 04:55:18 PM PDT 24 643047790 ps
T341 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1686781110 Jun 25 04:54:57 PM PDT 24 Jun 25 04:55:15 PM PDT 24 8525937987 ps
T342 /workspace/coverage/default/28.rom_ctrl_smoke.1605840880 Jun 25 04:54:18 PM PDT 24 Jun 25 04:54:52 PM PDT 24 16781232294 ps
T343 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3183860805 Jun 25 04:53:27 PM PDT 24 Jun 25 04:58:26 PM PDT 24 101532203458 ps
T344 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.367029829 Jun 25 04:53:43 PM PDT 24 Jun 25 04:54:06 PM PDT 24 4245336031 ps
T345 /workspace/coverage/default/20.rom_ctrl_alert_test.250596996 Jun 25 04:54:04 PM PDT 24 Jun 25 04:54:17 PM PDT 24 1086619168 ps
T346 /workspace/coverage/default/42.rom_ctrl_smoke.3437900997 Jun 25 04:54:44 PM PDT 24 Jun 25 04:55:10 PM PDT 24 1829015153 ps
T347 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1941693292 Jun 25 04:54:22 PM PDT 24 Jun 25 04:54:29 PM PDT 24 374434262 ps
T348 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.374153941 Jun 25 04:53:36 PM PDT 24 Jun 25 04:53:53 PM PDT 24 7504696551 ps
T349 /workspace/coverage/default/26.rom_ctrl_alert_test.4182126709 Jun 25 04:54:16 PM PDT 24 Jun 25 04:54:27 PM PDT 24 1437668981 ps
T350 /workspace/coverage/default/0.rom_ctrl_alert_test.2557598514 Jun 25 04:53:18 PM PDT 24 Jun 25 04:53:32 PM PDT 24 2923355328 ps
T351 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.4223350519 Jun 25 04:54:24 PM PDT 24 Jun 25 06:08:16 PM PDT 24 70473988306 ps
T352 /workspace/coverage/default/47.rom_ctrl_stress_all.1643891227 Jun 25 04:54:52 PM PDT 24 Jun 25 04:55:07 PM PDT 24 2686772141 ps
T27 /workspace/coverage/default/4.rom_ctrl_sec_cm.2303963859 Jun 25 04:53:25 PM PDT 24 Jun 25 04:55:07 PM PDT 24 236262450 ps
T353 /workspace/coverage/default/27.rom_ctrl_alert_test.2289193911 Jun 25 04:54:18 PM PDT 24 Jun 25 04:54:27 PM PDT 24 740340920 ps
T354 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2500917513 Jun 25 04:54:54 PM PDT 24 Jun 25 04:55:00 PM PDT 24 659985283 ps
T355 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.981738961 Jun 25 04:54:17 PM PDT 24 Jun 25 04:54:27 PM PDT 24 832140177 ps
T356 /workspace/coverage/default/2.rom_ctrl_stress_all.3417671816 Jun 25 04:53:19 PM PDT 24 Jun 25 04:54:21 PM PDT 24 28300418456 ps
T357 /workspace/coverage/default/33.rom_ctrl_smoke.1654290896 Jun 25 04:54:25 PM PDT 24 Jun 25 04:54:42 PM PDT 24 595215675 ps
T358 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3123949292 Jun 25 04:53:11 PM PDT 24 Jun 25 05:00:45 PM PDT 24 49595960400 ps
T359 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1164324520 Jun 25 04:54:43 PM PDT 24 Jun 25 04:54:59 PM PDT 24 3464892192 ps
T360 /workspace/coverage/default/28.rom_ctrl_alert_test.2348620660 Jun 25 04:54:16 PM PDT 24 Jun 25 04:54:23 PM PDT 24 854351508 ps
T361 /workspace/coverage/default/49.rom_ctrl_alert_test.2687351876 Jun 25 04:55:04 PM PDT 24 Jun 25 04:55:21 PM PDT 24 1544009400 ps
T362 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2223643086 Jun 25 04:54:43 PM PDT 24 Jun 25 04:55:05 PM PDT 24 3767888304 ps
T363 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.804698198 Jun 25 04:54:38 PM PDT 24 Jun 25 04:55:01 PM PDT 24 2053451725 ps
T364 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2060230952 Jun 25 04:53:54 PM PDT 24 Jun 25 05:41:17 PM PDT 24 801035590239 ps
T365 /workspace/coverage/default/41.rom_ctrl_smoke.3246109579 Jun 25 04:54:47 PM PDT 24 Jun 25 04:54:58 PM PDT 24 207527741 ps
T366 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.385145344 Jun 25 04:54:04 PM PDT 24 Jun 25 04:54:29 PM PDT 24 24496544956 ps
T54 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.71278892 Jun 25 04:52:41 PM PDT 24 Jun 25 04:54:08 PM PDT 24 44863987554 ps
T367 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3405653157 Jun 25 04:53:10 PM PDT 24 Jun 25 04:53:20 PM PDT 24 600372624 ps
T51 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.777294067 Jun 25 04:53:11 PM PDT 24 Jun 25 04:53:49 PM PDT 24 156530541 ps
T52 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3739261335 Jun 25 04:53:10 PM PDT 24 Jun 25 04:54:23 PM PDT 24 465181596 ps
T368 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1841721495 Jun 25 04:53:10 PM PDT 24 Jun 25 04:53:31 PM PDT 24 8258078619 ps
T369 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.87284856 Jun 25 04:52:50 PM PDT 24 Jun 25 04:52:56 PM PDT 24 85889918 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4224725154 Jun 25 04:52:54 PM PDT 24 Jun 25 04:53:09 PM PDT 24 5630376139 ps
T371 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.7152992 Jun 25 04:53:10 PM PDT 24 Jun 25 04:53:22 PM PDT 24 165183252 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2455515500 Jun 25 04:52:39 PM PDT 24 Jun 25 04:54:05 PM PDT 24 10703855507 ps
T92 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4000598014 Jun 25 04:53:00 PM PDT 24 Jun 25 04:53:17 PM PDT 24 25649687681 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.845128160 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:14 PM PDT 24 1321184984 ps
T372 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.120951032 Jun 25 04:52:50 PM PDT 24 Jun 25 04:53:02 PM PDT 24 821861167 ps
T59 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3197817474 Jun 25 04:52:49 PM PDT 24 Jun 25 04:53:04 PM PDT 24 2512329352 ps
T60 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.350734235 Jun 25 04:53:11 PM PDT 24 Jun 25 04:53:47 PM PDT 24 1094297721 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2866880628 Jun 25 04:52:50 PM PDT 24 Jun 25 04:53:03 PM PDT 24 5126357406 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2974581428 Jun 25 04:52:38 PM PDT 24 Jun 25 04:53:51 PM PDT 24 32651054616 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2300956848 Jun 25 04:52:50 PM PDT 24 Jun 25 04:52:57 PM PDT 24 1016007453 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2157212331 Jun 25 04:52:50 PM PDT 24 Jun 25 04:53:03 PM PDT 24 4875357429 ps
T53 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1318862452 Jun 25 04:53:00 PM PDT 24 Jun 25 04:54:17 PM PDT 24 5765762003 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1779804407 Jun 25 04:52:43 PM PDT 24 Jun 25 04:53:02 PM PDT 24 1683521676 ps
T376 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1314096255 Jun 25 04:52:41 PM PDT 24 Jun 25 04:52:48 PM PDT 24 496258168 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2595833797 Jun 25 04:52:58 PM PDT 24 Jun 25 04:54:01 PM PDT 24 25573229539 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1717431771 Jun 25 04:52:42 PM PDT 24 Jun 25 04:52:48 PM PDT 24 127509102 ps
T62 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.32328139 Jun 25 04:52:55 PM PDT 24 Jun 25 04:53:29 PM PDT 24 7956357356 ps
T63 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.832933828 Jun 25 04:53:00 PM PDT 24 Jun 25 04:53:18 PM PDT 24 3547789406 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2591524528 Jun 25 04:52:43 PM PDT 24 Jun 25 04:52:57 PM PDT 24 2497654912 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3179931996 Jun 25 04:52:54 PM PDT 24 Jun 25 04:53:03 PM PDT 24 692117090 ps
T379 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4120570344 Jun 25 04:52:58 PM PDT 24 Jun 25 04:53:12 PM PDT 24 1155954564 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.894455100 Jun 25 04:52:38 PM PDT 24 Jun 25 04:52:43 PM PDT 24 333378258 ps
T65 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1722473599 Jun 25 04:52:57 PM PDT 24 Jun 25 04:53:11 PM PDT 24 1583071217 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1181969572 Jun 25 04:52:41 PM PDT 24 Jun 25 04:52:54 PM PDT 24 4752329321 ps
T66 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3346153543 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:12 PM PDT 24 3785323800 ps
T67 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2687191392 Jun 25 04:52:43 PM PDT 24 Jun 25 04:52:59 PM PDT 24 1787186180 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1947318756 Jun 25 04:53:10 PM PDT 24 Jun 25 04:53:21 PM PDT 24 3551095476 ps
T94 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.343966470 Jun 25 04:52:53 PM PDT 24 Jun 25 04:52:59 PM PDT 24 126206486 ps
T95 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2728659579 Jun 25 04:53:09 PM PDT 24 Jun 25 04:53:16 PM PDT 24 90311406 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3427120141 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:14 PM PDT 24 5161544128 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2425187438 Jun 25 04:52:39 PM PDT 24 Jun 25 04:52:57 PM PDT 24 1309028593 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.946160650 Jun 25 04:53:00 PM PDT 24 Jun 25 04:53:11 PM PDT 24 609074915 ps
T96 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4110103958 Jun 25 04:52:49 PM PDT 24 Jun 25 04:52:58 PM PDT 24 1399574261 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2836710385 Jun 25 04:52:40 PM PDT 24 Jun 25 04:52:45 PM PDT 24 92115071 ps
T385 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1811942489 Jun 25 04:53:08 PM PDT 24 Jun 25 04:53:23 PM PDT 24 3818271686 ps
T386 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4193663373 Jun 25 04:52:55 PM PDT 24 Jun 25 04:53:01 PM PDT 24 126447256 ps
T387 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.302461118 Jun 25 04:53:02 PM PDT 24 Jun 25 04:53:16 PM PDT 24 5561933687 ps
T106 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3300167793 Jun 25 04:52:59 PM PDT 24 Jun 25 04:54:15 PM PDT 24 1271586150 ps
T108 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4195248600 Jun 25 04:53:07 PM PDT 24 Jun 25 04:53:46 PM PDT 24 426557491 ps
T388 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2288975777 Jun 25 04:53:08 PM PDT 24 Jun 25 04:53:13 PM PDT 24 391933807 ps
T389 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1087178411 Jun 25 04:53:02 PM PDT 24 Jun 25 04:53:10 PM PDT 24 456755667 ps
T97 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.894021076 Jun 25 04:52:50 PM PDT 24 Jun 25 04:53:06 PM PDT 24 1723039849 ps
T390 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3846931254 Jun 25 04:53:00 PM PDT 24 Jun 25 04:53:16 PM PDT 24 7632555826 ps
T391 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3208948163 Jun 25 04:52:57 PM PDT 24 Jun 25 04:53:16 PM PDT 24 7601633375 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4231456027 Jun 25 04:52:43 PM PDT 24 Jun 25 04:52:49 PM PDT 24 347877157 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3497433135 Jun 25 04:53:08 PM PDT 24 Jun 25 04:54:07 PM PDT 24 19622604820 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2593024463 Jun 25 04:53:15 PM PDT 24 Jun 25 04:53:28 PM PDT 24 6046793758 ps
T111 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2049613403 Jun 25 04:52:43 PM PDT 24 Jun 25 04:53:59 PM PDT 24 2116927072 ps
T109 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2102918042 Jun 25 04:53:08 PM PDT 24 Jun 25 04:54:20 PM PDT 24 415120404 ps
T72 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1204847488 Jun 25 04:52:50 PM PDT 24 Jun 25 04:53:16 PM PDT 24 888383051 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3355472304 Jun 25 04:52:40 PM PDT 24 Jun 25 04:52:48 PM PDT 24 381138622 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.137268887 Jun 25 04:52:50 PM PDT 24 Jun 25 04:52:59 PM PDT 24 4545301271 ps
T396 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1987917582 Jun 25 04:53:08 PM PDT 24 Jun 25 04:53:22 PM PDT 24 1435067515 ps
T397 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1804394000 Jun 25 04:53:11 PM PDT 24 Jun 25 04:53:24 PM PDT 24 1284354905 ps
T398 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2755607702 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:07 PM PDT 24 332827816 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.794598287 Jun 25 04:52:41 PM PDT 24 Jun 25 04:52:55 PM PDT 24 6528269695 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.451871143 Jun 25 04:53:09 PM PDT 24 Jun 25 04:53:26 PM PDT 24 3187009330 ps
T401 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.326754062 Jun 25 04:52:43 PM PDT 24 Jun 25 04:52:51 PM PDT 24 342667165 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1168651222 Jun 25 04:53:10 PM PDT 24 Jun 25 04:54:25 PM PDT 24 2001817566 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.114780442 Jun 25 04:52:42 PM PDT 24 Jun 25 04:52:54 PM PDT 24 11195207267 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3994418936 Jun 25 04:52:52 PM PDT 24 Jun 25 04:52:58 PM PDT 24 378795806 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1836667463 Jun 25 04:52:55 PM PDT 24 Jun 25 04:53:15 PM PDT 24 1910817269 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4148409538 Jun 25 04:52:41 PM PDT 24 Jun 25 04:52:49 PM PDT 24 1331532674 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2991172845 Jun 25 04:52:43 PM PDT 24 Jun 25 04:53:05 PM PDT 24 2051681744 ps
T73 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1726939597 Jun 25 04:53:06 PM PDT 24 Jun 25 04:53:53 PM PDT 24 12003267952 ps
T407 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.380885900 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:11 PM PDT 24 214717151 ps
T408 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2703279415 Jun 25 04:53:08 PM PDT 24 Jun 25 04:53:17 PM PDT 24 1264106929 ps
T409 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.408996073 Jun 25 04:53:02 PM PDT 24 Jun 25 04:53:14 PM PDT 24 4638355668 ps
T410 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.371343629 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:49 PM PDT 24 6291535629 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2969002035 Jun 25 04:52:40 PM PDT 24 Jun 25 04:52:55 PM PDT 24 1362169963 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3067683114 Jun 25 04:52:42 PM PDT 24 Jun 25 04:52:57 PM PDT 24 2816704919 ps
T77 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4267328391 Jun 25 04:53:14 PM PDT 24 Jun 25 04:53:25 PM PDT 24 1698680004 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3418304226 Jun 25 04:53:10 PM PDT 24 Jun 25 04:53:19 PM PDT 24 1818876037 ps
T414 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2574236353 Jun 25 04:53:10 PM PDT 24 Jun 25 04:53:16 PM PDT 24 86623197 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.599886077 Jun 25 04:53:03 PM PDT 24 Jun 25 04:53:42 PM PDT 24 202096810 ps
T415 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.325747265 Jun 25 04:53:00 PM PDT 24 Jun 25 04:53:14 PM PDT 24 4965291398 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3774517069 Jun 25 04:52:42 PM PDT 24 Jun 25 04:53:03 PM PDT 24 1449772258 ps
T74 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3503831986 Jun 25 04:52:39 PM PDT 24 Jun 25 04:52:51 PM PDT 24 7610821313 ps
T416 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.738149279 Jun 25 04:52:52 PM PDT 24 Jun 25 04:53:34 PM PDT 24 4171862532 ps
T75 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1657151629 Jun 25 04:52:57 PM PDT 24 Jun 25 04:54:16 PM PDT 24 63823569866 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2578316608 Jun 25 04:52:42 PM PDT 24 Jun 25 04:53:00 PM PDT 24 8493778565 ps
T418 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3219290655 Jun 25 04:52:41 PM PDT 24 Jun 25 04:52:57 PM PDT 24 6718994022 ps
T112 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2705209694 Jun 25 04:53:10 PM PDT 24 Jun 25 04:53:54 PM PDT 24 5914014978 ps
T419 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3257346389 Jun 25 04:53:12 PM PDT 24 Jun 25 04:53:17 PM PDT 24 85523791 ps
T420 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.799632297 Jun 25 04:53:01 PM PDT 24 Jun 25 04:53:18 PM PDT 24 6164209869 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1878678650 Jun 25 04:52:51 PM PDT 24 Jun 25 04:53:11 PM PDT 24 401294377 ps
T422 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3111908826 Jun 25 04:53:07 PM PDT 24 Jun 25 04:53:13 PM PDT 24 87442897 ps
T423 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.802166287 Jun 25 04:52:51 PM PDT 24 Jun 25 04:53:08 PM PDT 24 7336076502 ps
T424 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3964822174 Jun 25 04:52:50 PM PDT 24 Jun 25 04:53:07 PM PDT 24 2180237655 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1580505513 Jun 25 04:53:08 PM PDT 24 Jun 25 04:54:01 PM PDT 24 5976069886 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3046997050 Jun 25 04:52:51 PM PDT 24 Jun 25 04:53:06 PM PDT 24 3535610283 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.938552830 Jun 25 04:53:10 PM PDT 24 Jun 25 04:53:27 PM PDT 24 5272682952 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2586492024 Jun 25 04:53:11 PM PDT 24 Jun 25 04:53:20 PM PDT 24 393069114 ps
T429 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1910830255 Jun 25 04:53:08 PM PDT 24 Jun 25 04:54:47 PM PDT 24 56038823345 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1813543775 Jun 25 04:52:43 PM PDT 24 Jun 25 04:52:52 PM PDT 24 2238720364 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1131925679 Jun 25 04:52:49 PM PDT 24 Jun 25 04:53:07 PM PDT 24 13926431876 ps
T432 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3266858263 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:20 PM PDT 24 1477853600 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2393891114 Jun 25 04:53:00 PM PDT 24 Jun 25 04:53:19 PM PDT 24 8219418418 ps
T434 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2486952806 Jun 25 04:53:00 PM PDT 24 Jun 25 04:53:10 PM PDT 24 749585457 ps
T435 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4076189847 Jun 25 04:52:55 PM PDT 24 Jun 25 04:53:35 PM PDT 24 1303322847 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1708549436 Jun 25 04:52:54 PM PDT 24 Jun 25 04:53:10 PM PDT 24 9518853336 ps
T437 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.813708451 Jun 25 04:52:58 PM PDT 24 Jun 25 04:53:06 PM PDT 24 1705501050 ps
T79 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3819073181 Jun 25 04:52:51 PM PDT 24 Jun 25 04:53:35 PM PDT 24 9017313619 ps
T438 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3271661848 Jun 25 04:53:11 PM PDT 24 Jun 25 04:53:44 PM PDT 24 2049499846 ps
T439 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1408275577 Jun 25 04:53:00 PM PDT 24 Jun 25 04:53:15 PM PDT 24 1064806380 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3077899268 Jun 25 04:52:42 PM PDT 24 Jun 25 04:52:50 PM PDT 24 341669133 ps
T80 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.397015843 Jun 25 04:52:59 PM PDT 24 Jun 25 04:54:02 PM PDT 24 7540385251 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1492944104 Jun 25 04:52:40 PM PDT 24 Jun 25 04:52:46 PM PDT 24 164946969 ps
T76 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4003366631 Jun 25 04:53:02 PM PDT 24 Jun 25 04:53:32 PM PDT 24 2183389017 ps
T442 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.926878572 Jun 25 04:52:58 PM PDT 24 Jun 25 04:53:47 PM PDT 24 24397092341 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1908878811 Jun 25 04:53:11 PM PDT 24 Jun 25 04:53:24 PM PDT 24 4933460229 ps
T444 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2388489891 Jun 25 04:53:00 PM PDT 24 Jun 25 04:53:17 PM PDT 24 1915065244 ps
T445 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3393482683 Jun 25 04:53:01 PM PDT 24 Jun 25 04:53:07 PM PDT 24 90242689 ps
T446 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.823911468 Jun 25 04:53:10 PM PDT 24 Jun 25 04:53:21 PM PDT 24 2817111090 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4043766864 Jun 25 04:52:43 PM PDT 24 Jun 25 04:52:57 PM PDT 24 7497275085 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3284747705 Jun 25 04:53:12 PM PDT 24 Jun 25 04:53:21 PM PDT 24 1291812688 ps
T449 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4210936740 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:50 PM PDT 24 11152102511 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.343327478 Jun 25 04:52:43 PM PDT 24 Jun 25 04:52:55 PM PDT 24 2033632786 ps
T110 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.520394677 Jun 25 04:52:58 PM PDT 24 Jun 25 04:54:15 PM PDT 24 1514133718 ps
T115 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1067776551 Jun 25 04:53:00 PM PDT 24 Jun 25 04:54:17 PM PDT 24 5351674415 ps
T451 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2763409233 Jun 25 04:53:08 PM PDT 24 Jun 25 04:53:19 PM PDT 24 1268787696 ps
T452 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3656483117 Jun 25 04:53:11 PM PDT 24 Jun 25 04:53:25 PM PDT 24 987457334 ps
T113 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1450681750 Jun 25 04:52:52 PM PDT 24 Jun 25 04:54:08 PM PDT 24 15549314153 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3063986280 Jun 25 04:52:54 PM PDT 24 Jun 25 04:53:05 PM PDT 24 7718170009 ps
T454 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3840379985 Jun 25 04:53:02 PM PDT 24 Jun 25 04:53:47 PM PDT 24 15155160754 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1380866847 Jun 25 04:52:39 PM PDT 24 Jun 25 04:52:56 PM PDT 24 6048772272 ps
T456 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2292611464 Jun 25 04:52:43 PM PDT 24 Jun 25 04:52:59 PM PDT 24 3442475214 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3932855725 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:14 PM PDT 24 5323761319 ps
T458 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1059231563 Jun 25 04:53:14 PM PDT 24 Jun 25 04:53:28 PM PDT 24 14957475505 ps
T459 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3504409629 Jun 25 04:52:51 PM PDT 24 Jun 25 04:53:06 PM PDT 24 4285937428 ps
T460 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3602261461 Jun 25 04:52:50 PM PDT 24 Jun 25 04:53:00 PM PDT 24 1192859342 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1015412545 Jun 25 04:52:41 PM PDT 24 Jun 25 04:53:53 PM PDT 24 422783549 ps
T462 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4005005004 Jun 25 04:52:43 PM PDT 24 Jun 25 04:53:54 PM PDT 24 1708583806 ps
T463 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1009670882 Jun 25 04:52:48 PM PDT 24 Jun 25 04:52:58 PM PDT 24 4341763097 ps
T464 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3856368319 Jun 25 04:52:52 PM PDT 24 Jun 25 04:53:02 PM PDT 24 3663374743 ps
T465 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.620389078 Jun 25 04:52:50 PM PDT 24 Jun 25 04:53:34 PM PDT 24 5816379375 ps
T466 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3987205529 Jun 25 04:52:59 PM PDT 24 Jun 25 04:53:17 PM PDT 24 16327098194 ps
T467 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2735781072 Jun 25 04:53:13 PM PDT 24 Jun 25 04:53:28 PM PDT 24 1660517388 ps

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.48737737
Short name T3
Test name
Test status
Simulation time 62618656471 ps
CPU time 10699.2 seconds
Started Jun 25 04:54:14 PM PDT 24
Finished Jun 25 07:52:36 PM PDT 24
Peak memory 234212 kb
Host smart-cb7fed70-f7ef-4906-80ac-7712ff29c922
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48737737 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.48737737
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3517508618
Short name T14
Test name
Test status
Simulation time 79871314414 ps
CPU time 257.84 seconds
Started Jun 25 04:54:41 PM PDT 24
Finished Jun 25 04:59:01 PM PDT 24
Peak memory 237464 kb
Host smart-896e3b50-b5ed-4cb1-9f0c-249c38a94056
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517508618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3517508618
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1556807867
Short name T41
Test name
Test status
Simulation time 10705885207 ps
CPU time 204.47 seconds
Started Jun 25 04:54:07 PM PDT 24
Finished Jun 25 04:57:32 PM PDT 24
Peak memory 212520 kb
Host smart-24190112-add8-40e1-9c4e-a3b42c5c6ffe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556807867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1556807867
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1318862452
Short name T53
Test name
Test status
Simulation time 5765762003 ps
CPU time 75.65 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:54:17 PM PDT 24
Peak memory 218844 kb
Host smart-addfc3e3-73d3-4ac0-88ca-5bef1d60d813
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318862452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1318862452
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.869533415
Short name T10
Test name
Test status
Simulation time 390446687 ps
CPU time 10.45 seconds
Started Jun 25 04:54:28 PM PDT 24
Finished Jun 25 04:54:39 PM PDT 24
Peak memory 213924 kb
Host smart-e46e9f2e-d6f2-4fae-b2f6-4205b5937e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869533415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.869533415
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1613548217
Short name T26
Test name
Test status
Simulation time 3101948564 ps
CPU time 104.65 seconds
Started Jun 25 04:53:16 PM PDT 24
Finished Jun 25 04:55:01 PM PDT 24
Peak memory 236808 kb
Host smart-3dee04be-bfed-41a0-a567-113d6e840d42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613548217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1613548217
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.32328139
Short name T62
Test name
Test status
Simulation time 7956357356 ps
CPU time 32.58 seconds
Started Jun 25 04:52:55 PM PDT 24
Finished Jun 25 04:53:29 PM PDT 24
Peak memory 218704 kb
Host smart-cb71092c-d6fc-4058-8b48-2f46d401fa23
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32328139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pass
thru_mem_tl_intg_err.32328139
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3739261335
Short name T52
Test name
Test status
Simulation time 465181596 ps
CPU time 71.59 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:54:23 PM PDT 24
Peak memory 212312 kb
Host smart-bccddc4a-32db-47e3-a3d4-dc6777712958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739261335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3739261335
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1385588495
Short name T57
Test name
Test status
Simulation time 1977454140 ps
CPU time 7.56 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:53:53 PM PDT 24
Peak memory 211196 kb
Host smart-2261f8a6-df54-472e-bb38-14fcde600a65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385588495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1385588495
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1985114480
Short name T44
Test name
Test status
Simulation time 42733630607 ps
CPU time 184.9 seconds
Started Jun 25 04:53:25 PM PDT 24
Finished Jun 25 04:56:31 PM PDT 24
Peak memory 225280 kb
Host smart-9d4f85c2-9561-407b-b7a3-888d0402f5d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985114480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1985114480
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1823127568
Short name T4
Test name
Test status
Simulation time 2256174740 ps
CPU time 17.78 seconds
Started Jun 25 04:53:25 PM PDT 24
Finished Jun 25 04:53:44 PM PDT 24
Peak memory 211816 kb
Host smart-7de636cc-a2d5-4754-b232-78b58f25195a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823127568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1823127568
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3036990714
Short name T159
Test name
Test status
Simulation time 168775317 ps
CPU time 9.8 seconds
Started Jun 25 04:54:29 PM PDT 24
Finished Jun 25 04:54:39 PM PDT 24
Peak memory 211924 kb
Host smart-d40e0ce4-190e-4e73-bf60-9751db0bbec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036990714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3036990714
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1450681750
Short name T113
Test name
Test status
Simulation time 15549314153 ps
CPU time 75.19 seconds
Started Jun 25 04:52:52 PM PDT 24
Finished Jun 25 04:54:08 PM PDT 24
Peak memory 211436 kb
Host smart-6d192105-7d16-4a04-be86-3203098407a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450681750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1450681750
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2724846240
Short name T37
Test name
Test status
Simulation time 144127819973 ps
CPU time 8554.06 seconds
Started Jun 25 04:55:06 PM PDT 24
Finished Jun 25 07:17:43 PM PDT 24
Peak memory 235768 kb
Host smart-45ee586a-65f6-4bbc-b9b6-8c5be0d45a09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724846240 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2724846240
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1722473599
Short name T65
Test name
Test status
Simulation time 1583071217 ps
CPU time 12.74 seconds
Started Jun 25 04:52:57 PM PDT 24
Finished Jun 25 04:53:11 PM PDT 24
Peak memory 210564 kb
Host smart-af15e926-555e-42a0-ab25-be35a1d1604e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722473599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1722473599
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1067776551
Short name T115
Test name
Test status
Simulation time 5351674415 ps
CPU time 74.86 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:54:17 PM PDT 24
Peak memory 212508 kb
Host smart-126bdb6a-f284-4c2b-aa21-468a6ea7c8fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067776551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1067776551
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1157180686
Short name T98
Test name
Test status
Simulation time 1519935109 ps
CPU time 8.05 seconds
Started Jun 25 04:54:19 PM PDT 24
Finished Jun 25 04:54:28 PM PDT 24
Peak memory 211236 kb
Host smart-8b9a52e4-b4eb-49c6-8643-f1c5096c7f4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157180686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1157180686
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.511101768
Short name T13
Test name
Test status
Simulation time 91795814821 ps
CPU time 1789.3 seconds
Started Jun 25 04:53:42 PM PDT 24
Finished Jun 25 05:23:33 PM PDT 24
Peak memory 236900 kb
Host smart-a4cd598f-3c89-4648-958e-6905bfee8bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511101768 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.511101768
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.433095105
Short name T21
Test name
Test status
Simulation time 26157503758 ps
CPU time 27.51 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:54:13 PM PDT 24
Peak memory 212260 kb
Host smart-7f18e9ce-1a85-46d1-b240-f8cda12d8a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433095105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.433095105
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3355472304
Short name T394
Test name
Test status
Simulation time 381138622 ps
CPU time 6.92 seconds
Started Jun 25 04:52:40 PM PDT 24
Finished Jun 25 04:52:48 PM PDT 24
Peak memory 217744 kb
Host smart-7d8cb576-5cf1-47ba-945c-d447f2c38d79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355472304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3355472304
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.114780442
Short name T402
Test name
Test status
Simulation time 11195207267 ps
CPU time 11.42 seconds
Started Jun 25 04:52:42 PM PDT 24
Finished Jun 25 04:52:54 PM PDT 24
Peak memory 219204 kb
Host smart-73c009bc-fc58-4986-868f-97ba3bc2303d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114780442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.114780442
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1380866847
Short name T455
Test name
Test status
Simulation time 6048772272 ps
CPU time 16.17 seconds
Started Jun 25 04:52:39 PM PDT 24
Finished Jun 25 04:52:56 PM PDT 24
Peak memory 210656 kb
Host smart-dd0a6d4b-3374-475a-b45d-3a8c23ad98e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380866847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1380866847
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4148409538
Short name T405
Test name
Test status
Simulation time 1331532674 ps
CPU time 7.31 seconds
Started Jun 25 04:52:41 PM PDT 24
Finished Jun 25 04:52:49 PM PDT 24
Peak memory 218784 kb
Host smart-b79774c3-1dc2-4c81-9caa-60f3cf06c929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148409538 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4148409538
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.326754062
Short name T401
Test name
Test status
Simulation time 342667165 ps
CPU time 6.45 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:52:51 PM PDT 24
Peak memory 210564 kb
Host smart-00e37200-6ea5-4296-b1f0-4fa50b43551e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326754062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.326754062
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1492944104
Short name T441
Test name
Test status
Simulation time 164946969 ps
CPU time 4.47 seconds
Started Jun 25 04:52:40 PM PDT 24
Finished Jun 25 04:52:46 PM PDT 24
Peak memory 210460 kb
Host smart-8a0b014f-8e9d-43b2-ba52-1904152c3844
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492944104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1492944104
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1314096255
Short name T376
Test name
Test status
Simulation time 496258168 ps
CPU time 6.06 seconds
Started Jun 25 04:52:41 PM PDT 24
Finished Jun 25 04:52:48 PM PDT 24
Peak memory 208812 kb
Host smart-de47bf45-a84a-43b9-84fb-aca5f8278849
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314096255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1314096255
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2974581428
Short name T61
Test name
Test status
Simulation time 32651054616 ps
CPU time 72.17 seconds
Started Jun 25 04:52:38 PM PDT 24
Finished Jun 25 04:53:51 PM PDT 24
Peak memory 210660 kb
Host smart-84319c77-9da4-476f-a01b-03e3abaa7a8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974581428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2974581428
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.894455100
Short name T93
Test name
Test status
Simulation time 333378258 ps
CPU time 4.3 seconds
Started Jun 25 04:52:38 PM PDT 24
Finished Jun 25 04:52:43 PM PDT 24
Peak memory 210652 kb
Host smart-1dbf127c-d1c0-4f85-b1dd-ff1c62a60d52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894455100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.894455100
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2991172845
Short name T406
Test name
Test status
Simulation time 2051681744 ps
CPU time 20.33 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:53:05 PM PDT 24
Peak memory 218840 kb
Host smart-f1433896-15ec-4ace-b8a7-5e2cc0ea0a24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991172845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2991172845
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4005005004
Short name T462
Test name
Test status
Simulation time 1708583806 ps
CPU time 69.56 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:53:54 PM PDT 24
Peak memory 218888 kb
Host smart-164708fe-93be-4012-9776-e8bd6ea332a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005005004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4005005004
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2687191392
Short name T67
Test name
Test status
Simulation time 1787186180 ps
CPU time 14.75 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:52:59 PM PDT 24
Peak memory 210560 kb
Host smart-bb2ede35-881a-4541-8cf2-a10d2f3b4783
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687191392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2687191392
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.794598287
Short name T399
Test name
Test status
Simulation time 6528269695 ps
CPU time 12.79 seconds
Started Jun 25 04:52:41 PM PDT 24
Finished Jun 25 04:52:55 PM PDT 24
Peak memory 210652 kb
Host smart-bbbd4a55-9f02-4386-9f80-1d7b70f95cc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794598287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.794598287
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3077899268
Short name T440
Test name
Test status
Simulation time 341669133 ps
CPU time 6.06 seconds
Started Jun 25 04:52:42 PM PDT 24
Finished Jun 25 04:52:50 PM PDT 24
Peak memory 218660 kb
Host smart-04fb998d-6a61-4a3c-b9c3-11ac077b079f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077899268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3077899268
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2578316608
Short name T417
Test name
Test status
Simulation time 8493778565 ps
CPU time 16.75 seconds
Started Jun 25 04:52:42 PM PDT 24
Finished Jun 25 04:53:00 PM PDT 24
Peak memory 218948 kb
Host smart-bfb9574b-ff44-43cf-8a08-904627a9b04f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578316608 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2578316608
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3219290655
Short name T418
Test name
Test status
Simulation time 6718994022 ps
CPU time 14.65 seconds
Started Jun 25 04:52:41 PM PDT 24
Finished Jun 25 04:52:57 PM PDT 24
Peak memory 210648 kb
Host smart-728a065b-3e32-4773-b2d0-83ba13a7ca72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219290655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3219290655
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2836710385
Short name T384
Test name
Test status
Simulation time 92115071 ps
CPU time 4.17 seconds
Started Jun 25 04:52:40 PM PDT 24
Finished Jun 25 04:52:45 PM PDT 24
Peak memory 210432 kb
Host smart-6eddaed8-5c88-4bda-b0e8-b342c2b0a59e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836710385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2836710385
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4231456027
Short name T392
Test name
Test status
Simulation time 347877157 ps
CPU time 4.27 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:52:49 PM PDT 24
Peak memory 210516 kb
Host smart-ec5cbad9-73ae-4e25-837a-e25c316601e6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231456027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4231456027
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2455515500
Short name T91
Test name
Test status
Simulation time 10703855507 ps
CPU time 85.72 seconds
Started Jun 25 04:52:39 PM PDT 24
Finished Jun 25 04:54:05 PM PDT 24
Peak memory 210688 kb
Host smart-9fcb4b53-8bd8-41ef-8647-82f858655d01
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455515500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2455515500
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2292611464
Short name T456
Test name
Test status
Simulation time 3442475214 ps
CPU time 14.6 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:52:59 PM PDT 24
Peak memory 218860 kb
Host smart-2e170414-7f69-45dc-b16d-6be049d08a20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292611464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2292611464
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1779804407
Short name T375
Test name
Test status
Simulation time 1683521676 ps
CPU time 17.82 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:53:02 PM PDT 24
Peak memory 219128 kb
Host smart-e992387b-e177-421e-ae80-eb349f04f0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779804407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1779804407
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1015412545
Short name T461
Test name
Test status
Simulation time 422783549 ps
CPU time 71.62 seconds
Started Jun 25 04:52:41 PM PDT 24
Finished Jun 25 04:53:53 PM PDT 24
Peak memory 212244 kb
Host smart-386e7b9b-5287-4cf9-a4fe-7a6ca267ccf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015412545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1015412545
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1087178411
Short name T389
Test name
Test status
Simulation time 456755667 ps
CPU time 6.18 seconds
Started Jun 25 04:53:02 PM PDT 24
Finished Jun 25 04:53:10 PM PDT 24
Peak memory 218888 kb
Host smart-faa39632-42e6-4ac6-83a2-d0e9462d87ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087178411 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1087178411
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.813708451
Short name T437
Test name
Test status
Simulation time 1705501050 ps
CPU time 6.37 seconds
Started Jun 25 04:52:58 PM PDT 24
Finished Jun 25 04:53:06 PM PDT 24
Peak memory 210520 kb
Host smart-99eee12c-6da6-4f1d-b571-a0685e891563
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813708451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.813708451
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4003366631
Short name T76
Test name
Test status
Simulation time 2183389017 ps
CPU time 28.49 seconds
Started Jun 25 04:53:02 PM PDT 24
Finished Jun 25 04:53:32 PM PDT 24
Peak memory 210660 kb
Host smart-034c51c2-d4f5-4b84-9c8d-37eaa8250cbb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003366631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4003366631
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2755607702
Short name T398
Test name
Test status
Simulation time 332827816 ps
CPU time 6.81 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:07 PM PDT 24
Peak memory 210628 kb
Host smart-40b20f9c-5a4d-4e67-8fc1-0895c234ca2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755607702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2755607702
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.799632297
Short name T420
Test name
Test status
Simulation time 6164209869 ps
CPU time 15.67 seconds
Started Jun 25 04:53:01 PM PDT 24
Finished Jun 25 04:53:18 PM PDT 24
Peak memory 218896 kb
Host smart-53929f87-40da-4df2-a6cb-206446f3f323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799632297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.799632297
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3300167793
Short name T106
Test name
Test status
Simulation time 1271586150 ps
CPU time 73.47 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:54:15 PM PDT 24
Peak memory 211952 kb
Host smart-321da735-bae0-428b-a44d-1ca47dcad293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300167793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3300167793
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.946160650
Short name T383
Test name
Test status
Simulation time 609074915 ps
CPU time 8.81 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:53:11 PM PDT 24
Peak memory 219300 kb
Host smart-616e527e-9b79-4e67-9122-2127c69f25c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946160650 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.946160650
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2388489891
Short name T444
Test name
Test status
Simulation time 1915065244 ps
CPU time 15.15 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:53:17 PM PDT 24
Peak memory 218348 kb
Host smart-52e5432e-a557-4edd-8d06-69736c778f7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388489891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2388489891
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.397015843
Short name T80
Test name
Test status
Simulation time 7540385251 ps
CPU time 60.89 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:54:02 PM PDT 24
Peak memory 210632 kb
Host smart-903ef806-3d8c-4a63-9ca0-4a24e6a485ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397015843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.397015843
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3987205529
Short name T466
Test name
Test status
Simulation time 16327098194 ps
CPU time 15.68 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:17 PM PDT 24
Peak memory 210712 kb
Host smart-10b539aa-0b27-4c05-99b1-273e82cbb30a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987205529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3987205529
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1408275577
Short name T439
Test name
Test status
Simulation time 1064806380 ps
CPU time 13.01 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:53:15 PM PDT 24
Peak memory 218928 kb
Host smart-285597f4-7267-41e9-adb1-5056e69f3f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408275577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1408275577
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3393482683
Short name T445
Test name
Test status
Simulation time 90242689 ps
CPU time 4.48 seconds
Started Jun 25 04:53:01 PM PDT 24
Finished Jun 25 04:53:07 PM PDT 24
Peak memory 212616 kb
Host smart-31432622-6733-4607-af0d-4332d1f99117
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393482683 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3393482683
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2393891114
Short name T433
Test name
Test status
Simulation time 8219418418 ps
CPU time 16.63 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:53:19 PM PDT 24
Peak memory 218784 kb
Host smart-4f11944a-b4b3-401f-b1a5-d9d88a02002c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393891114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2393891114
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4210936740
Short name T449
Test name
Test status
Simulation time 11152102511 ps
CPU time 49.6 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:50 PM PDT 24
Peak memory 210660 kb
Host smart-88f3b7ec-4466-444f-9872-2d7a723309f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210936740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4210936740
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.325747265
Short name T415
Test name
Test status
Simulation time 4965291398 ps
CPU time 11.68 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:53:14 PM PDT 24
Peak memory 210888 kb
Host smart-8ea2fc50-61d9-4571-9c3e-b6701bd64a51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325747265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.325747265
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2486952806
Short name T434
Test name
Test status
Simulation time 749585457 ps
CPU time 7.65 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:53:10 PM PDT 24
Peak memory 218844 kb
Host smart-c0ae6ec8-a7d6-4a66-afc9-223c907c389a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486952806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2486952806
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3840379985
Short name T454
Test name
Test status
Simulation time 15155160754 ps
CPU time 43.75 seconds
Started Jun 25 04:53:02 PM PDT 24
Finished Jun 25 04:53:47 PM PDT 24
Peak memory 218868 kb
Host smart-76ebf5b3-0df2-45f5-a534-6b7a2fd18199
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840379985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3840379985
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1804394000
Short name T397
Test name
Test status
Simulation time 1284354905 ps
CPU time 11.15 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 04:53:24 PM PDT 24
Peak memory 218896 kb
Host smart-764ed267-90db-4753-b88a-f66409cc97fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804394000 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1804394000
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.845128160
Short name T100
Test name
Test status
Simulation time 1321184984 ps
CPU time 12.25 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:14 PM PDT 24
Peak memory 217636 kb
Host smart-7be6651f-443d-4f26-89ec-c992e9fb03b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845128160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.845128160
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.371343629
Short name T410
Test name
Test status
Simulation time 6291535629 ps
CPU time 47.45 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:49 PM PDT 24
Peak memory 210664 kb
Host smart-544e2215-ce77-4b90-a8e7-65d4591952df
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371343629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.371343629
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.823911468
Short name T446
Test name
Test status
Simulation time 2817111090 ps
CPU time 9.83 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:53:21 PM PDT 24
Peak memory 218140 kb
Host smart-90e7d67b-ca4d-4aa8-aeac-025b229c1d41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823911468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.823911468
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3846931254
Short name T390
Test name
Test status
Simulation time 7632555826 ps
CPU time 14.68 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:53:16 PM PDT 24
Peak memory 218896 kb
Host smart-1bbcbcc3-ee10-4ab7-a74d-4acc858bb984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846931254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3846931254
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.520394677
Short name T110
Test name
Test status
Simulation time 1514133718 ps
CPU time 74.64 seconds
Started Jun 25 04:52:58 PM PDT 24
Finished Jun 25 04:54:15 PM PDT 24
Peak memory 212168 kb
Host smart-0324965b-363f-4657-b526-4891cf441090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520394677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.520394677
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2586492024
Short name T428
Test name
Test status
Simulation time 393069114 ps
CPU time 7.43 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 04:53:20 PM PDT 24
Peak memory 218880 kb
Host smart-75cffc0f-59f4-467d-80fd-473fe52cd4ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586492024 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2586492024
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2735781072
Short name T467
Test name
Test status
Simulation time 1660517388 ps
CPU time 14.25 seconds
Started Jun 25 04:53:13 PM PDT 24
Finished Jun 25 04:53:28 PM PDT 24
Peak memory 218612 kb
Host smart-8f78a2ce-7c82-431b-9b32-4b97fc9a9f49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735781072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2735781072
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.350734235
Short name T60
Test name
Test status
Simulation time 1094297721 ps
CPU time 35.1 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 04:53:47 PM PDT 24
Peak memory 210596 kb
Host smart-32769d83-fea0-4c09-97f8-a48e87c7a35c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350734235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.350734235
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1908878811
Short name T443
Test name
Test status
Simulation time 4933460229 ps
CPU time 11.99 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 04:53:24 PM PDT 24
Peak memory 211280 kb
Host smart-9a0d7e84-a70a-4be1-b802-22666f50b709
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908878811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1908878811
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2763409233
Short name T451
Test name
Test status
Simulation time 1268787696 ps
CPU time 10.49 seconds
Started Jun 25 04:53:08 PM PDT 24
Finished Jun 25 04:53:19 PM PDT 24
Peak memory 218840 kb
Host smart-b0782e45-ec38-48b1-abe4-eeb6e6202afe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763409233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2763409233
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2705209694
Short name T112
Test name
Test status
Simulation time 5914014978 ps
CPU time 43.29 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:53:54 PM PDT 24
Peak memory 212392 kb
Host smart-0fd3d551-405c-43f4-9740-687b070c5987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705209694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2705209694
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3284747705
Short name T448
Test name
Test status
Simulation time 1291812688 ps
CPU time 8.3 seconds
Started Jun 25 04:53:12 PM PDT 24
Finished Jun 25 04:53:21 PM PDT 24
Peak memory 212792 kb
Host smart-ce728f80-a45f-4607-be8e-6363040e7b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284747705 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3284747705
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1947318756
Short name T71
Test name
Test status
Simulation time 3551095476 ps
CPU time 9.38 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:53:21 PM PDT 24
Peak memory 218512 kb
Host smart-61868d70-8f9f-475a-b01d-e7f27927e647
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947318756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1947318756
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1580505513
Short name T425
Test name
Test status
Simulation time 5976069886 ps
CPU time 52.6 seconds
Started Jun 25 04:53:08 PM PDT 24
Finished Jun 25 04:54:01 PM PDT 24
Peak memory 210632 kb
Host smart-863a2170-1a4e-4cca-b5e3-1406fedae00d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580505513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1580505513
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.938552830
Short name T427
Test name
Test status
Simulation time 5272682952 ps
CPU time 16.62 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:53:27 PM PDT 24
Peak memory 210992 kb
Host smart-b87da966-1d85-475e-b2cd-95e99ae9eb51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938552830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.938552830
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1841721495
Short name T368
Test name
Test status
Simulation time 8258078619 ps
CPU time 19.3 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:53:31 PM PDT 24
Peak memory 218912 kb
Host smart-8275c402-55f9-4621-856d-12b53e95bc0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841721495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1841721495
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4195248600
Short name T108
Test name
Test status
Simulation time 426557491 ps
CPU time 37.99 seconds
Started Jun 25 04:53:07 PM PDT 24
Finished Jun 25 04:53:46 PM PDT 24
Peak memory 213108 kb
Host smart-3e15aed6-3add-4369-aeae-3c105dc11392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195248600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4195248600
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1059231563
Short name T458
Test name
Test status
Simulation time 14957475505 ps
CPU time 12.87 seconds
Started Jun 25 04:53:14 PM PDT 24
Finished Jun 25 04:53:28 PM PDT 24
Peak memory 218888 kb
Host smart-75fbcd87-d3a3-41ce-aee9-7684edb66c2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059231563 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1059231563
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4267328391
Short name T77
Test name
Test status
Simulation time 1698680004 ps
CPU time 10.51 seconds
Started Jun 25 04:53:14 PM PDT 24
Finished Jun 25 04:53:25 PM PDT 24
Peak memory 218636 kb
Host smart-b9d804c4-d2e9-482b-8ce4-75c5abd948ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267328391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4267328391
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1910830255
Short name T429
Test name
Test status
Simulation time 56038823345 ps
CPU time 98.42 seconds
Started Jun 25 04:53:08 PM PDT 24
Finished Jun 25 04:54:47 PM PDT 24
Peak memory 210620 kb
Host smart-d9d18e09-d4ab-4a09-909c-530f68594b31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910830255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1910830255
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3111908826
Short name T422
Test name
Test status
Simulation time 87442897 ps
CPU time 4.21 seconds
Started Jun 25 04:53:07 PM PDT 24
Finished Jun 25 04:53:13 PM PDT 24
Peak memory 210620 kb
Host smart-19c1a159-ec9d-47c7-8951-4f963ddec5b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111908826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3111908826
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.451871143
Short name T400
Test name
Test status
Simulation time 3187009330 ps
CPU time 16.4 seconds
Started Jun 25 04:53:09 PM PDT 24
Finished Jun 25 04:53:26 PM PDT 24
Peak memory 218900 kb
Host smart-d45373ad-2292-43ce-aebd-c811b6fcc4b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451871143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.451871143
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1168651222
Short name T107
Test name
Test status
Simulation time 2001817566 ps
CPU time 74.41 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:54:25 PM PDT 24
Peak memory 218800 kb
Host smart-aa57bf53-15d8-4bd0-ab11-164c8d50a1b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168651222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1168651222
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2288975777
Short name T388
Test name
Test status
Simulation time 391933807 ps
CPU time 4.9 seconds
Started Jun 25 04:53:08 PM PDT 24
Finished Jun 25 04:53:13 PM PDT 24
Peak memory 218892 kb
Host smart-d4807072-5026-4b36-b1eb-87795cb089da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288975777 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2288975777
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1811942489
Short name T385
Test name
Test status
Simulation time 3818271686 ps
CPU time 14.31 seconds
Started Jun 25 04:53:08 PM PDT 24
Finished Jun 25 04:53:23 PM PDT 24
Peak memory 218644 kb
Host smart-eff7ed3c-b970-4ece-b3bf-e042c29e4d18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811942489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1811942489
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3497433135
Short name T105
Test name
Test status
Simulation time 19622604820 ps
CPU time 57.55 seconds
Started Jun 25 04:53:08 PM PDT 24
Finished Jun 25 04:54:07 PM PDT 24
Peak memory 210740 kb
Host smart-338726fd-6137-47ea-b3ea-a30b19bb0f1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497433135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3497433135
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2728659579
Short name T95
Test name
Test status
Simulation time 90311406 ps
CPU time 6.03 seconds
Started Jun 25 04:53:09 PM PDT 24
Finished Jun 25 04:53:16 PM PDT 24
Peak memory 218780 kb
Host smart-60d2ef9a-b2ae-48ab-bb6e-c20bf73a60b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728659579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2728659579
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3405653157
Short name T367
Test name
Test status
Simulation time 600372624 ps
CPU time 9.74 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:53:20 PM PDT 24
Peak memory 216704 kb
Host smart-16d97e7c-93cc-4e16-a92b-f0100662c5b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405653157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3405653157
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2593024463
Short name T393
Test name
Test status
Simulation time 6046793758 ps
CPU time 13 seconds
Started Jun 25 04:53:15 PM PDT 24
Finished Jun 25 04:53:28 PM PDT 24
Peak memory 218856 kb
Host smart-f5dee1a3-8fa6-4fab-b324-af199f5d104f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593024463 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2593024463
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3257346389
Short name T419
Test name
Test status
Simulation time 85523791 ps
CPU time 4.26 seconds
Started Jun 25 04:53:12 PM PDT 24
Finished Jun 25 04:53:17 PM PDT 24
Peak memory 210592 kb
Host smart-49b5bbd4-d56b-47cd-bd1c-6cecb0ad1ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257346389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3257346389
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3271661848
Short name T438
Test name
Test status
Simulation time 2049499846 ps
CPU time 31.99 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 04:53:44 PM PDT 24
Peak memory 210504 kb
Host smart-8b0c79c0-0e90-45ee-a959-4757010d7d9b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271661848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3271661848
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1987917582
Short name T396
Test name
Test status
Simulation time 1435067515 ps
CPU time 12.93 seconds
Started Jun 25 04:53:08 PM PDT 24
Finished Jun 25 04:53:22 PM PDT 24
Peak memory 210656 kb
Host smart-eb4c4eb5-4468-4f46-a75b-2acd7c961648
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987917582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1987917582
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.7152992
Short name T371
Test name
Test status
Simulation time 165183252 ps
CPU time 11.51 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:53:22 PM PDT 24
Peak memory 215456 kb
Host smart-d1192d0e-1bf1-4634-a64d-8d5f4a886a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7152992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.7152992
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2102918042
Short name T109
Test name
Test status
Simulation time 415120404 ps
CPU time 70.68 seconds
Started Jun 25 04:53:08 PM PDT 24
Finished Jun 25 04:54:20 PM PDT 24
Peak memory 218800 kb
Host smart-a0bce239-aef9-4da3-b19f-2a543d80040f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102918042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2102918042
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3418304226
Short name T413
Test name
Test status
Simulation time 1818876037 ps
CPU time 7.5 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:53:19 PM PDT 24
Peak memory 212188 kb
Host smart-e2b86572-7f20-4731-a637-919f3985e67b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418304226 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3418304226
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2703279415
Short name T408
Test name
Test status
Simulation time 1264106929 ps
CPU time 8.06 seconds
Started Jun 25 04:53:08 PM PDT 24
Finished Jun 25 04:53:17 PM PDT 24
Peak memory 218452 kb
Host smart-1829f7d7-1f28-4724-8e55-a578eafb3c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703279415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2703279415
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1726939597
Short name T73
Test name
Test status
Simulation time 12003267952 ps
CPU time 46.98 seconds
Started Jun 25 04:53:06 PM PDT 24
Finished Jun 25 04:53:53 PM PDT 24
Peak memory 218832 kb
Host smart-bd8b5f20-9e8f-4051-9168-545ffe1ba505
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726939597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1726939597
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2574236353
Short name T414
Test name
Test status
Simulation time 86623197 ps
CPU time 4.36 seconds
Started Jun 25 04:53:10 PM PDT 24
Finished Jun 25 04:53:16 PM PDT 24
Peak memory 210744 kb
Host smart-8635e500-e143-4596-9400-81ed7b64ae71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574236353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2574236353
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3656483117
Short name T452
Test name
Test status
Simulation time 987457334 ps
CPU time 13.11 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 04:53:25 PM PDT 24
Peak memory 218844 kb
Host smart-350f9b91-db8b-4a25-a310-ff7fb4141e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656483117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3656483117
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.777294067
Short name T51
Test name
Test status
Simulation time 156530541 ps
CPU time 36.57 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 04:53:49 PM PDT 24
Peak memory 211832 kb
Host smart-d9ebee5a-bdd5-4542-afa6-c8a9b8b6afca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777294067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.777294067
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3503831986
Short name T74
Test name
Test status
Simulation time 7610821313 ps
CPU time 11.48 seconds
Started Jun 25 04:52:39 PM PDT 24
Finished Jun 25 04:52:51 PM PDT 24
Peak memory 218792 kb
Host smart-6f3c4307-1e70-4b8c-a104-f8732b52681e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503831986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3503831986
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1813543775
Short name T430
Test name
Test status
Simulation time 2238720364 ps
CPU time 8.21 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:52:52 PM PDT 24
Peak memory 210660 kb
Host smart-18e9419a-632e-4163-b6f9-1469ae4a57f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813543775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1813543775
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1181969572
Short name T380
Test name
Test status
Simulation time 4752329321 ps
CPU time 12.4 seconds
Started Jun 25 04:52:41 PM PDT 24
Finished Jun 25 04:52:54 PM PDT 24
Peak memory 218800 kb
Host smart-05f95bb0-4b0f-4208-a45a-8f7dc9cb7fef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181969572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1181969572
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4043766864
Short name T447
Test name
Test status
Simulation time 7497275085 ps
CPU time 11.9 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:52:57 PM PDT 24
Peak memory 219008 kb
Host smart-1640b5f3-134c-44ee-8cb8-77cc4e898ba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043766864 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4043766864
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.343327478
Short name T450
Test name
Test status
Simulation time 2033632786 ps
CPU time 10.16 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:52:55 PM PDT 24
Peak memory 210820 kb
Host smart-17ab8687-f5c3-47ae-8c66-f903dd126ab9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343327478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.343327478
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1717431771
Short name T377
Test name
Test status
Simulation time 127509102 ps
CPU time 5.13 seconds
Started Jun 25 04:52:42 PM PDT 24
Finished Jun 25 04:52:48 PM PDT 24
Peak memory 210432 kb
Host smart-dfa3e9e9-2f8b-47d5-9900-b9d5274d6c38
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717431771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1717431771
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2591524528
Short name T378
Test name
Test status
Simulation time 2497654912 ps
CPU time 12.17 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:52:57 PM PDT 24
Peak memory 210780 kb
Host smart-96a3d1f7-a76a-4f06-a30c-305d1630626f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591524528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2591524528
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.71278892
Short name T54
Test name
Test status
Simulation time 44863987554 ps
CPU time 86.56 seconds
Started Jun 25 04:52:41 PM PDT 24
Finished Jun 25 04:54:08 PM PDT 24
Peak memory 209192 kb
Host smart-51e86aab-076f-44e5-8684-00c55357d0ae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71278892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.71278892
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3067683114
Short name T412
Test name
Test status
Simulation time 2816704919 ps
CPU time 13.3 seconds
Started Jun 25 04:52:42 PM PDT 24
Finished Jun 25 04:52:57 PM PDT 24
Peak memory 210652 kb
Host smart-992cc232-6f19-4daf-b25f-50bfc4fe4ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067683114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3067683114
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2425187438
Short name T382
Test name
Test status
Simulation time 1309028593 ps
CPU time 17 seconds
Started Jun 25 04:52:39 PM PDT 24
Finished Jun 25 04:52:57 PM PDT 24
Peak memory 216680 kb
Host smart-915aab94-95bb-43ad-8037-4a0d93ab0d79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425187438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2425187438
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2049613403
Short name T111
Test name
Test status
Simulation time 2116927072 ps
CPU time 74.75 seconds
Started Jun 25 04:52:43 PM PDT 24
Finished Jun 25 04:53:59 PM PDT 24
Peak memory 218828 kb
Host smart-66929b56-6b67-4597-8184-dd68e870e9ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049613403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2049613403
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3063986280
Short name T453
Test name
Test status
Simulation time 7718170009 ps
CPU time 9.82 seconds
Started Jun 25 04:52:54 PM PDT 24
Finished Jun 25 04:53:05 PM PDT 24
Peak memory 210656 kb
Host smart-31100e34-f062-444c-92a4-6811c2f523bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063986280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3063986280
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.137268887
Short name T395
Test name
Test status
Simulation time 4545301271 ps
CPU time 7.41 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:52:59 PM PDT 24
Peak memory 210660 kb
Host smart-86b9ba7c-3604-44c0-a604-ab16033605ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137268887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.137268887
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1836667463
Short name T404
Test name
Test status
Simulation time 1910817269 ps
CPU time 18.04 seconds
Started Jun 25 04:52:55 PM PDT 24
Finished Jun 25 04:53:15 PM PDT 24
Peak memory 210588 kb
Host smart-28eb6e46-bc4a-414e-ac99-a48503711cd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836667463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1836667463
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3602261461
Short name T460
Test name
Test status
Simulation time 1192859342 ps
CPU time 7.99 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:53:00 PM PDT 24
Peak memory 218876 kb
Host smart-a9022c70-3515-4882-9e3c-e5c65a3efb18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602261461 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3602261461
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3179931996
Short name T64
Test name
Test status
Simulation time 692117090 ps
CPU time 8.37 seconds
Started Jun 25 04:52:54 PM PDT 24
Finished Jun 25 04:53:03 PM PDT 24
Peak memory 217348 kb
Host smart-7f797d0b-513c-46c8-8c5b-b6cf531045b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179931996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3179931996
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1009670882
Short name T463
Test name
Test status
Simulation time 4341763097 ps
CPU time 9.32 seconds
Started Jun 25 04:52:48 PM PDT 24
Finished Jun 25 04:52:58 PM PDT 24
Peak memory 210516 kb
Host smart-2b92ea3c-0bf7-4c7e-b180-f965996ad83d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009670882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1009670882
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2157212331
Short name T374
Test name
Test status
Simulation time 4875357429 ps
CPU time 10.88 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:53:03 PM PDT 24
Peak memory 210520 kb
Host smart-f270b3c6-743d-4e9a-880d-a4b0b9aee1cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157212331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2157212331
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3774517069
Short name T78
Test name
Test status
Simulation time 1449772258 ps
CPU time 18.7 seconds
Started Jun 25 04:52:42 PM PDT 24
Finished Jun 25 04:53:03 PM PDT 24
Peak memory 210596 kb
Host smart-940f216a-a405-46e3-9363-6b4f6b04bd91
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774517069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3774517069
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4110103958
Short name T96
Test name
Test status
Simulation time 1399574261 ps
CPU time 8.64 seconds
Started Jun 25 04:52:49 PM PDT 24
Finished Jun 25 04:52:58 PM PDT 24
Peak memory 218040 kb
Host smart-39bc2150-04f8-410e-8c78-bc503de03c02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110103958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4110103958
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2969002035
Short name T411
Test name
Test status
Simulation time 1362169963 ps
CPU time 14.04 seconds
Started Jun 25 04:52:40 PM PDT 24
Finished Jun 25 04:52:55 PM PDT 24
Peak memory 218832 kb
Host smart-f0efdd5e-6904-4a7a-89e1-995d09149bed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969002035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2969002035
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.620389078
Short name T465
Test name
Test status
Simulation time 5816379375 ps
CPU time 42.17 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:53:34 PM PDT 24
Peak memory 218884 kb
Host smart-d5e36c37-ed39-4c93-b8e9-f9068f64735d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620389078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.620389078
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2866880628
Short name T101
Test name
Test status
Simulation time 5126357406 ps
CPU time 11.47 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:53:03 PM PDT 24
Peak memory 218668 kb
Host smart-0763616d-5b62-414b-b86a-a4b17e7b9eb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866880628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2866880628
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3994418936
Short name T403
Test name
Test status
Simulation time 378795806 ps
CPU time 4.5 seconds
Started Jun 25 04:52:52 PM PDT 24
Finished Jun 25 04:52:58 PM PDT 24
Peak memory 217448 kb
Host smart-a4c8dca2-af6e-4552-8f0b-1a1ac1618d85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994418936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3994418936
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3197817474
Short name T59
Test name
Test status
Simulation time 2512329352 ps
CPU time 14.48 seconds
Started Jun 25 04:52:49 PM PDT 24
Finished Jun 25 04:53:04 PM PDT 24
Peak memory 217776 kb
Host smart-2bac509f-fdb2-4b22-ad27-5c8bee4985c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197817474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3197817474
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3046997050
Short name T426
Test name
Test status
Simulation time 3535610283 ps
CPU time 13.38 seconds
Started Jun 25 04:52:51 PM PDT 24
Finished Jun 25 04:53:06 PM PDT 24
Peak memory 218812 kb
Host smart-750200b1-63f0-458a-b36a-84d0ce4a6b35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046997050 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3046997050
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1131925679
Short name T431
Test name
Test status
Simulation time 13926431876 ps
CPU time 17.16 seconds
Started Jun 25 04:52:49 PM PDT 24
Finished Jun 25 04:53:07 PM PDT 24
Peak memory 218768 kb
Host smart-2b78be5d-9d5d-4565-a8d4-253def7b1c26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131925679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1131925679
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.87284856
Short name T369
Test name
Test status
Simulation time 85889918 ps
CPU time 4.37 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:52:56 PM PDT 24
Peak memory 210452 kb
Host smart-37d302ce-650d-44a1-9471-538717e8bb07
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87284856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_
mem_partial_access.87284856
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1708549436
Short name T436
Test name
Test status
Simulation time 9518853336 ps
CPU time 15 seconds
Started Jun 25 04:52:54 PM PDT 24
Finished Jun 25 04:53:10 PM PDT 24
Peak memory 210520 kb
Host smart-cb76667b-754e-4d2e-8114-09ea175ba195
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708549436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1708549436
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1878678650
Short name T421
Test name
Test status
Simulation time 401294377 ps
CPU time 18.6 seconds
Started Jun 25 04:52:51 PM PDT 24
Finished Jun 25 04:53:11 PM PDT 24
Peak memory 210596 kb
Host smart-51794d0f-6c46-4cfb-a131-30385ce36dac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878678650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1878678650
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.343966470
Short name T94
Test name
Test status
Simulation time 126206486 ps
CPU time 5.04 seconds
Started Jun 25 04:52:53 PM PDT 24
Finished Jun 25 04:52:59 PM PDT 24
Peak memory 210620 kb
Host smart-0824fa21-5221-4649-9156-73334ef16496
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343966470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.343966470
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4224725154
Short name T370
Test name
Test status
Simulation time 5630376139 ps
CPU time 14.45 seconds
Started Jun 25 04:52:54 PM PDT 24
Finished Jun 25 04:53:09 PM PDT 24
Peak memory 218900 kb
Host smart-7ce0aeab-01cb-415f-a625-185779de798c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224725154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4224725154
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4076189847
Short name T435
Test name
Test status
Simulation time 1303322847 ps
CPU time 39.06 seconds
Started Jun 25 04:52:55 PM PDT 24
Finished Jun 25 04:53:35 PM PDT 24
Peak memory 210916 kb
Host smart-5b4a7bff-7d04-478c-9543-a39eeb0ae630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076189847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4076189847
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2300956848
Short name T373
Test name
Test status
Simulation time 1016007453 ps
CPU time 4.65 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:52:57 PM PDT 24
Peak memory 218852 kb
Host smart-87b35f9d-e954-488c-a218-41e79dda16bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300956848 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2300956848
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3856368319
Short name T464
Test name
Test status
Simulation time 3663374743 ps
CPU time 8.8 seconds
Started Jun 25 04:52:52 PM PDT 24
Finished Jun 25 04:53:02 PM PDT 24
Peak memory 211068 kb
Host smart-4d61bfc5-ece4-4f97-bda5-503878889cbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856368319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3856368319
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3819073181
Short name T79
Test name
Test status
Simulation time 9017313619 ps
CPU time 42.62 seconds
Started Jun 25 04:52:51 PM PDT 24
Finished Jun 25 04:53:35 PM PDT 24
Peak memory 218144 kb
Host smart-9182baff-6da6-430b-beb8-c7f98a6e6007
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819073181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3819073181
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3964822174
Short name T424
Test name
Test status
Simulation time 2180237655 ps
CPU time 15.95 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:53:07 PM PDT 24
Peak memory 218836 kb
Host smart-60fba970-da45-43a2-b4bf-ebd59b01eb7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964822174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3964822174
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.120951032
Short name T372
Test name
Test status
Simulation time 821861167 ps
CPU time 10.27 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:53:02 PM PDT 24
Peak memory 218844 kb
Host smart-e0d79679-6a50-494a-9309-b31a5d9470be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120951032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.120951032
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.802166287
Short name T423
Test name
Test status
Simulation time 7336076502 ps
CPU time 14.89 seconds
Started Jun 25 04:52:51 PM PDT 24
Finished Jun 25 04:53:08 PM PDT 24
Peak memory 218880 kb
Host smart-96219786-f06e-47e4-b544-be69caf93840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802166287 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.802166287
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4193663373
Short name T386
Test name
Test status
Simulation time 126447256 ps
CPU time 5.01 seconds
Started Jun 25 04:52:55 PM PDT 24
Finished Jun 25 04:53:01 PM PDT 24
Peak memory 217512 kb
Host smart-7152c3d4-f8fa-4b63-bfb1-70cd8aae7b51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193663373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4193663373
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.894021076
Short name T97
Test name
Test status
Simulation time 1723039849 ps
CPU time 14.61 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:53:06 PM PDT 24
Peak memory 210652 kb
Host smart-7133dea7-1cdd-4c5d-a739-ce5b6b3b6e01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894021076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.894021076
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3504409629
Short name T459
Test name
Test status
Simulation time 4285937428 ps
CPU time 13.06 seconds
Started Jun 25 04:52:51 PM PDT 24
Finished Jun 25 04:53:06 PM PDT 24
Peak memory 218892 kb
Host smart-b23fa77c-41c1-4578-b1dc-c768202441be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504409629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3504409629
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.738149279
Short name T416
Test name
Test status
Simulation time 4171862532 ps
CPU time 41.32 seconds
Started Jun 25 04:52:52 PM PDT 24
Finished Jun 25 04:53:34 PM PDT 24
Peak memory 218892 kb
Host smart-e6ea6758-3500-4bcc-937f-4131ab3b0698
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738149279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.738149279
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4120570344
Short name T379
Test name
Test status
Simulation time 1155954564 ps
CPU time 11.72 seconds
Started Jun 25 04:52:58 PM PDT 24
Finished Jun 25 04:53:12 PM PDT 24
Peak memory 218884 kb
Host smart-598bac0b-ec15-413c-8ef6-144501a325e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120570344 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4120570344
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.302461118
Short name T387
Test name
Test status
Simulation time 5561933687 ps
CPU time 12.49 seconds
Started Jun 25 04:53:02 PM PDT 24
Finished Jun 25 04:53:16 PM PDT 24
Peak memory 218700 kb
Host smart-8e768cef-aec2-4121-a17a-fa4ca8ef73f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302461118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.302461118
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1204847488
Short name T72
Test name
Test status
Simulation time 888383051 ps
CPU time 24.66 seconds
Started Jun 25 04:52:50 PM PDT 24
Finished Jun 25 04:53:16 PM PDT 24
Peak memory 210596 kb
Host smart-89a7f241-3c27-4afc-9dae-9c6240f5d507
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204847488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1204847488
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3346153543
Short name T66
Test name
Test status
Simulation time 3785323800 ps
CPU time 10.94 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:12 PM PDT 24
Peak memory 210740 kb
Host smart-ce15387a-9676-4e3b-99b6-84751b24f789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346153543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3346153543
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3266858263
Short name T432
Test name
Test status
Simulation time 1477853600 ps
CPU time 18.82 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:20 PM PDT 24
Peak memory 218828 kb
Host smart-dcf3c80a-d13c-4444-b552-a871f7d4186f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266858263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3266858263
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.408996073
Short name T409
Test name
Test status
Simulation time 4638355668 ps
CPU time 11.39 seconds
Started Jun 25 04:53:02 PM PDT 24
Finished Jun 25 04:53:14 PM PDT 24
Peak memory 218884 kb
Host smart-893a347e-12b4-43af-8c7c-8714cd5d9c56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408996073 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.408996073
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4000598014
Short name T92
Test name
Test status
Simulation time 25649687681 ps
CPU time 14.62 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:53:17 PM PDT 24
Peak memory 218792 kb
Host smart-369d3158-795b-4d4a-8a7e-7362e28a60c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000598014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4000598014
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1657151629
Short name T75
Test name
Test status
Simulation time 63823569866 ps
CPU time 77.7 seconds
Started Jun 25 04:52:57 PM PDT 24
Finished Jun 25 04:54:16 PM PDT 24
Peak memory 210664 kb
Host smart-006a0ac0-5885-4196-a6e1-7780f6243d0f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657151629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1657151629
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3932855725
Short name T457
Test name
Test status
Simulation time 5323761319 ps
CPU time 13.17 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:14 PM PDT 24
Peak memory 210792 kb
Host smart-8d60aa7e-4a72-4619-8e61-c3620364e552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932855725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3932855725
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3208948163
Short name T391
Test name
Test status
Simulation time 7601633375 ps
CPU time 17.52 seconds
Started Jun 25 04:52:57 PM PDT 24
Finished Jun 25 04:53:16 PM PDT 24
Peak memory 218892 kb
Host smart-8082f563-2d7c-4dd5-93a5-6a4817698d03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208948163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3208948163
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.599886077
Short name T114
Test name
Test status
Simulation time 202096810 ps
CPU time 38.02 seconds
Started Jun 25 04:53:03 PM PDT 24
Finished Jun 25 04:53:42 PM PDT 24
Peak memory 212152 kb
Host smart-a2643882-6e6d-4cb4-9070-233d9fbd8045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599886077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.599886077
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3427120141
Short name T381
Test name
Test status
Simulation time 5161544128 ps
CPU time 12.44 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:14 PM PDT 24
Peak memory 218948 kb
Host smart-ea74b01a-c097-4177-9a9d-f1515e515380
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427120141 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3427120141
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2595833797
Short name T102
Test name
Test status
Simulation time 25573229539 ps
CPU time 60.82 seconds
Started Jun 25 04:52:58 PM PDT 24
Finished Jun 25 04:54:01 PM PDT 24
Peak memory 210664 kb
Host smart-57b8154b-9efc-42dd-9f10-b134923e5cd3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595833797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2595833797
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.832933828
Short name T63
Test name
Test status
Simulation time 3547789406 ps
CPU time 16.12 seconds
Started Jun 25 04:53:00 PM PDT 24
Finished Jun 25 04:53:18 PM PDT 24
Peak memory 218852 kb
Host smart-e8edb236-f3b3-4c3f-be30-80525e4c3af3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832933828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.832933828
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.380885900
Short name T407
Test name
Test status
Simulation time 214717151 ps
CPU time 9.78 seconds
Started Jun 25 04:52:59 PM PDT 24
Finished Jun 25 04:53:11 PM PDT 24
Peak memory 218828 kb
Host smart-c3992644-86bc-4ede-a076-29cc644e2567
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380885900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.380885900
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.926878572
Short name T442
Test name
Test status
Simulation time 24397092341 ps
CPU time 47.16 seconds
Started Jun 25 04:52:58 PM PDT 24
Finished Jun 25 04:53:47 PM PDT 24
Peak memory 218852 kb
Host smart-f65b58a3-5c73-4762-8459-bdc898ebcf1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926878572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.926878572
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2557598514
Short name T350
Test name
Test status
Simulation time 2923355328 ps
CPU time 12.53 seconds
Started Jun 25 04:53:18 PM PDT 24
Finished Jun 25 04:53:32 PM PDT 24
Peak memory 211256 kb
Host smart-70f93955-c708-456b-98ef-01a29031cb3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557598514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2557598514
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3123949292
Short name T358
Test name
Test status
Simulation time 49595960400 ps
CPU time 452.72 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 233828 kb
Host smart-bde5bf38-a47f-40d6-aaa8-2b1b4813fcc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123949292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3123949292
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3138118033
Short name T298
Test name
Test status
Simulation time 11388771357 ps
CPU time 26.09 seconds
Started Jun 25 04:53:09 PM PDT 24
Finished Jun 25 04:53:36 PM PDT 24
Peak memory 212320 kb
Host smart-737baebf-1062-4137-85d5-4b2e66078e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138118033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3138118033
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2597564365
Short name T86
Test name
Test status
Simulation time 4316897686 ps
CPU time 17.47 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 04:53:30 PM PDT 24
Peak memory 211300 kb
Host smart-4b51d345-1921-4b2e-886e-176d7ccd6b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597564365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2597564365
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2782716461
Short name T19
Test name
Test status
Simulation time 2332162588 ps
CPU time 104.17 seconds
Started Jun 25 04:53:16 PM PDT 24
Finished Jun 25 04:55:02 PM PDT 24
Peak memory 251840 kb
Host smart-4d010cef-3360-4091-89c0-1d8ad8c87a4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782716461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2782716461
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4284194598
Short name T147
Test name
Test status
Simulation time 5568950260 ps
CPU time 25.67 seconds
Started Jun 25 04:53:11 PM PDT 24
Finished Jun 25 04:53:38 PM PDT 24
Peak memory 213644 kb
Host smart-4189f740-be0e-4dba-8107-e2c91b222f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284194598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4284194598
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4223290785
Short name T292
Test name
Test status
Simulation time 20558357828 ps
CPU time 84.71 seconds
Started Jun 25 04:53:09 PM PDT 24
Finished Jun 25 04:54:35 PM PDT 24
Peak memory 217936 kb
Host smart-3b57ce75-9793-4f10-8724-0205a8a32362
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223290785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4223290785
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4291319825
Short name T50
Test name
Test status
Simulation time 24943687198 ps
CPU time 957.87 seconds
Started Jun 25 04:53:16 PM PDT 24
Finished Jun 25 05:09:15 PM PDT 24
Peak memory 235764 kb
Host smart-0f77527f-4ac3-433f-ac2d-872d2c2c834a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291319825 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.4291319825
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.233876681
Short name T214
Test name
Test status
Simulation time 4300321487 ps
CPU time 10.44 seconds
Started Jun 25 04:53:18 PM PDT 24
Finished Jun 25 04:53:30 PM PDT 24
Peak memory 211252 kb
Host smart-fdb5606e-6d8f-44e5-8ccf-4ed07b973191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233876681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.233876681
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3107356126
Short name T247
Test name
Test status
Simulation time 1995526322 ps
CPU time 121.63 seconds
Started Jun 25 04:53:18 PM PDT 24
Finished Jun 25 04:55:21 PM PDT 24
Peak memory 228464 kb
Host smart-2e9ab035-4756-4d0f-b550-9c31b3f01829
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107356126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3107356126
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.591639427
Short name T168
Test name
Test status
Simulation time 175526007 ps
CPU time 9.59 seconds
Started Jun 25 04:53:18 PM PDT 24
Finished Jun 25 04:53:29 PM PDT 24
Peak memory 211968 kb
Host smart-b99c59b3-4aa5-4519-9b27-c3e8c4ba62a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591639427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.591639427
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4077236829
Short name T316
Test name
Test status
Simulation time 1585329569 ps
CPU time 14.53 seconds
Started Jun 25 04:53:19 PM PDT 24
Finished Jun 25 04:53:35 PM PDT 24
Peak memory 211236 kb
Host smart-4ad526b2-3c5c-4171-943d-5c85ed2db22a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077236829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4077236829
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3928068221
Short name T17
Test name
Test status
Simulation time 6997156724 ps
CPU time 62.55 seconds
Started Jun 25 04:53:16 PM PDT 24
Finished Jun 25 04:54:21 PM PDT 24
Peak memory 237524 kb
Host smart-09d8bb08-dbe7-4388-beb2-d184cc072557
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928068221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3928068221
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1601634930
Short name T248
Test name
Test status
Simulation time 2721946157 ps
CPU time 26.11 seconds
Started Jun 25 04:53:16 PM PDT 24
Finished Jun 25 04:53:43 PM PDT 24
Peak memory 213848 kb
Host smart-cb19788e-d653-464e-b3b4-87c69b425f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601634930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1601634930
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1745344599
Short name T301
Test name
Test status
Simulation time 15396940841 ps
CPU time 37.08 seconds
Started Jun 25 04:53:16 PM PDT 24
Finished Jun 25 04:53:55 PM PDT 24
Peak memory 216240 kb
Host smart-21a094b4-200f-4c75-b8a8-4b55b5fd8b87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745344599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1745344599
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1669107599
Short name T195
Test name
Test status
Simulation time 1205309240 ps
CPU time 11.44 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:53:57 PM PDT 24
Peak memory 211196 kb
Host smart-465fab2c-b722-4ad5-92d0-7aab0ec24c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669107599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1669107599
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.423085239
Short name T297
Test name
Test status
Simulation time 1744617925 ps
CPU time 56.63 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:54:42 PM PDT 24
Peak memory 212352 kb
Host smart-71be9b48-8cd1-4dea-a6a4-253f446ce837
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423085239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.423085239
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2031213219
Short name T302
Test name
Test status
Simulation time 418192482 ps
CPU time 5.44 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:53:59 PM PDT 24
Peak memory 211308 kb
Host smart-0f5b04d0-1db7-4e44-987e-7f66762f6e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031213219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2031213219
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1880280632
Short name T70
Test name
Test status
Simulation time 4371350720 ps
CPU time 28.68 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:54:22 PM PDT 24
Peak memory 213852 kb
Host smart-4a304098-0f54-4384-9f75-d148b03cdd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880280632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1880280632
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2714528180
Short name T135
Test name
Test status
Simulation time 19264160349 ps
CPU time 39.81 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:54:25 PM PDT 24
Peak memory 213600 kb
Host smart-819379fe-3cda-49a5-94e8-f1eccf74f2ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714528180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2714528180
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3611578422
Short name T250
Test name
Test status
Simulation time 689704349 ps
CPU time 5.75 seconds
Started Jun 25 04:53:45 PM PDT 24
Finished Jun 25 04:53:52 PM PDT 24
Peak memory 211176 kb
Host smart-5db84b30-2558-4b93-9f96-aef0add95d33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611578422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3611578422
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2333309758
Short name T236
Test name
Test status
Simulation time 16528943765 ps
CPU time 241.96 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:57:47 PM PDT 24
Peak memory 234808 kb
Host smart-d98967c3-6f00-4195-b61b-2ca6976fd6f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333309758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2333309758
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.70521309
Short name T228
Test name
Test status
Simulation time 174099498 ps
CPU time 9.59 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:53:54 PM PDT 24
Peak memory 211880 kb
Host smart-a34e8d55-f944-4f60-8a01-a3d9246f8ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70521309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.70521309
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3401670642
Short name T252
Test name
Test status
Simulation time 4047363541 ps
CPU time 16.91 seconds
Started Jun 25 04:53:46 PM PDT 24
Finished Jun 25 04:54:04 PM PDT 24
Peak memory 211300 kb
Host smart-5f8191e6-87e4-44d9-8a55-52ce84a07ab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401670642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3401670642
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3590437684
Short name T238
Test name
Test status
Simulation time 4631877715 ps
CPU time 17.43 seconds
Started Jun 25 04:53:43 PM PDT 24
Finished Jun 25 04:54:02 PM PDT 24
Peak memory 214372 kb
Host smart-14222a70-e777-4832-bd1b-037cd9d9cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590437684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3590437684
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1993092256
Short name T88
Test name
Test status
Simulation time 9839477762 ps
CPU time 43.33 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:54:28 PM PDT 24
Peak memory 215568 kb
Host smart-2de2e04b-c132-499d-8084-e9b42dda194e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993092256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1993092256
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2872718484
Short name T16
Test name
Test status
Simulation time 42227149994 ps
CPU time 114.09 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:55:39 PM PDT 24
Peak memory 212412 kb
Host smart-bc9777bd-dd28-4101-bf0a-2104e18bb782
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872718484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2872718484
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.367029829
Short name T344
Test name
Test status
Simulation time 4245336031 ps
CPU time 22.55 seconds
Started Jun 25 04:53:43 PM PDT 24
Finished Jun 25 04:54:06 PM PDT 24
Peak memory 211880 kb
Host smart-2a4c0189-9725-4d05-8ff4-0f7dd65371dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367029829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.367029829
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2631721670
Short name T1
Test name
Test status
Simulation time 547042260 ps
CPU time 8.68 seconds
Started Jun 25 04:53:45 PM PDT 24
Finished Jun 25 04:53:54 PM PDT 24
Peak memory 211232 kb
Host smart-93fdcb75-8c7e-4cf7-913e-8c9a209ffd54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2631721670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2631721670
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4007108452
Short name T218
Test name
Test status
Simulation time 8233133274 ps
CPU time 31.63 seconds
Started Jun 25 04:53:45 PM PDT 24
Finished Jun 25 04:54:18 PM PDT 24
Peak memory 214308 kb
Host smart-057e1763-c3d7-40a7-98c1-bc4b92b6a1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007108452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4007108452
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1673366878
Short name T126
Test name
Test status
Simulation time 2304288434 ps
CPU time 32.64 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:54:27 PM PDT 24
Peak memory 213760 kb
Host smart-366dbd6c-1fc1-4e23-bdd1-6e9642394ec1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673366878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1673366878
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.310792037
Short name T169
Test name
Test status
Simulation time 1725658551 ps
CPU time 14.33 seconds
Started Jun 25 04:53:42 PM PDT 24
Finished Jun 25 04:53:57 PM PDT 24
Peak memory 211188 kb
Host smart-28326b5b-163b-4c41-a80a-c157f18e0f25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310792037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.310792037
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4026325870
Short name T261
Test name
Test status
Simulation time 28424225405 ps
CPU time 92.22 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:55:18 PM PDT 24
Peak memory 237472 kb
Host smart-6454379b-86ec-4cf9-98a9-fcd3786f1480
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026325870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4026325870
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.468262892
Short name T22
Test name
Test status
Simulation time 830401103 ps
CPU time 9.63 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:53:55 PM PDT 24
Peak memory 211952 kb
Host smart-db6e7b73-4abd-46c7-8433-3aace1e09dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468262892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.468262892
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.348560483
Short name T196
Test name
Test status
Simulation time 6026064863 ps
CPU time 9.33 seconds
Started Jun 25 04:53:53 PM PDT 24
Finished Jun 25 04:54:04 PM PDT 24
Peak memory 211368 kb
Host smart-0b00f305-91c9-47c9-b885-b37f0f87229c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=348560483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.348560483
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1130109002
Short name T260
Test name
Test status
Simulation time 6174007073 ps
CPU time 26.67 seconds
Started Jun 25 04:53:45 PM PDT 24
Finished Jun 25 04:54:13 PM PDT 24
Peak memory 213992 kb
Host smart-84c72bd7-2f44-4342-91b7-610b0703212f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130109002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1130109002
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2519587679
Short name T327
Test name
Test status
Simulation time 288635222 ps
CPU time 8.8 seconds
Started Jun 25 04:53:44 PM PDT 24
Finished Jun 25 04:53:54 PM PDT 24
Peak memory 211112 kb
Host smart-ad469506-7b9c-4e77-8f75-924e23328fda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519587679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2519587679
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3882058007
Short name T155
Test name
Test status
Simulation time 1244080999 ps
CPU time 11.29 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:54:04 PM PDT 24
Peak memory 211272 kb
Host smart-f2d8f6f3-388b-4a01-9459-4b1d41503594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882058007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3882058007
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3443961071
Short name T177
Test name
Test status
Simulation time 71131749469 ps
CPU time 198.43 seconds
Started Jun 25 04:53:43 PM PDT 24
Finished Jun 25 04:57:03 PM PDT 24
Peak memory 234088 kb
Host smart-387c5d28-a5e6-4998-9b4e-af28b6819f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443961071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3443961071
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3583871369
Short name T262
Test name
Test status
Simulation time 13793764254 ps
CPU time 31.13 seconds
Started Jun 25 04:53:43 PM PDT 24
Finished Jun 25 04:54:15 PM PDT 24
Peak memory 212168 kb
Host smart-e44a8ea0-df30-4f7b-8ac8-4f41835951a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583871369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3583871369
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1335890604
Short name T303
Test name
Test status
Simulation time 4783659121 ps
CPU time 12.62 seconds
Started Jun 25 04:53:42 PM PDT 24
Finished Jun 25 04:53:55 PM PDT 24
Peak memory 211296 kb
Host smart-bf952a70-f5c0-42cb-b571-0d8826427381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335890604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1335890604
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3546252879
Short name T116
Test name
Test status
Simulation time 3234589858 ps
CPU time 20.98 seconds
Started Jun 25 04:53:43 PM PDT 24
Finished Jun 25 04:54:05 PM PDT 24
Peak memory 212972 kb
Host smart-1cc96c81-b8af-400a-a5bc-a82876661211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546252879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3546252879
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3312991451
Short name T191
Test name
Test status
Simulation time 16290468657 ps
CPU time 35.89 seconds
Started Jun 25 04:53:45 PM PDT 24
Finished Jun 25 04:54:22 PM PDT 24
Peak memory 214304 kb
Host smart-91377cbf-9167-4ce3-9f18-3596506e9218
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312991451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3312991451
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.322755257
Short name T194
Test name
Test status
Simulation time 182761136 ps
CPU time 4.4 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:53:58 PM PDT 24
Peak memory 211192 kb
Host smart-00fd8bad-5cc9-47d6-b216-a71d83c4197a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322755257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.322755257
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3153083668
Short name T239
Test name
Test status
Simulation time 2030684598 ps
CPU time 130.16 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:56:04 PM PDT 24
Peak memory 228124 kb
Host smart-847f72b7-4bd0-4c6a-a960-bee466843fb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153083668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3153083668
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1850617475
Short name T82
Test name
Test status
Simulation time 170518609 ps
CPU time 9.43 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:54:03 PM PDT 24
Peak memory 211936 kb
Host smart-c9b1b0ab-928c-4673-9ce0-749b82b0ba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850617475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1850617475
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2018015623
Short name T85
Test name
Test status
Simulation time 11626793949 ps
CPU time 15.77 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:54:10 PM PDT 24
Peak memory 211632 kb
Host smart-0e8a1c44-f026-4c28-92de-853175ddeb8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018015623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2018015623
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2703868671
Short name T306
Test name
Test status
Simulation time 3220507312 ps
CPU time 31.34 seconds
Started Jun 25 04:53:51 PM PDT 24
Finished Jun 25 04:54:23 PM PDT 24
Peak memory 213220 kb
Host smart-2a17c402-c4bd-4ad5-83cb-918bbadc949a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703868671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2703868671
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3980290340
Short name T171
Test name
Test status
Simulation time 21924071228 ps
CPU time 41.43 seconds
Started Jun 25 04:53:53 PM PDT 24
Finished Jun 25 04:54:36 PM PDT 24
Peak memory 214292 kb
Host smart-83464f2e-09c3-4508-a9d3-275d04b80356
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980290340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3980290340
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3476711827
Short name T117
Test name
Test status
Simulation time 4398922958 ps
CPU time 12.63 seconds
Started Jun 25 04:53:54 PM PDT 24
Finished Jun 25 04:54:08 PM PDT 24
Peak memory 211248 kb
Host smart-7c3888e0-2e28-42b6-a16f-6f05294d4c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476711827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3476711827
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3136376852
Short name T245
Test name
Test status
Simulation time 26355944711 ps
CPU time 327.51 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:59:22 PM PDT 24
Peak memory 233932 kb
Host smart-70e302c9-e4be-4ee3-9eae-90018d63e458
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136376852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3136376852
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3878573694
Short name T224
Test name
Test status
Simulation time 2668537506 ps
CPU time 25.54 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:54:19 PM PDT 24
Peak memory 211884 kb
Host smart-ac533add-1bbf-476a-b9a2-f6c1b81aab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878573694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3878573694
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1413425959
Short name T36
Test name
Test status
Simulation time 5576143921 ps
CPU time 14.64 seconds
Started Jun 25 04:53:53 PM PDT 24
Finished Jun 25 04:54:10 PM PDT 24
Peak memory 211292 kb
Host smart-e50b457c-7ea9-4e97-af5a-6a0b1f9f0de8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413425959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1413425959
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.118865244
Short name T7
Test name
Test status
Simulation time 3050682863 ps
CPU time 26.61 seconds
Started Jun 25 04:53:53 PM PDT 24
Finished Jun 25 04:54:22 PM PDT 24
Peak memory 213328 kb
Host smart-68688453-0ac6-4b01-b786-bafe7caf20a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118865244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.118865244
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.876114057
Short name T128
Test name
Test status
Simulation time 2876180674 ps
CPU time 29.2 seconds
Started Jun 25 04:53:50 PM PDT 24
Finished Jun 25 04:54:20 PM PDT 24
Peak memory 213184 kb
Host smart-8aedd04f-96bc-4f43-9bb0-7580cceea33b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876114057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.876114057
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3223393854
Short name T263
Test name
Test status
Simulation time 416708674 ps
CPU time 4.36 seconds
Started Jun 25 04:53:53 PM PDT 24
Finished Jun 25 04:54:00 PM PDT 24
Peak memory 211252 kb
Host smart-c75eeceb-4b5e-441d-b0ec-2db302756cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223393854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3223393854
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1403536297
Short name T319
Test name
Test status
Simulation time 42543693174 ps
CPU time 360.94 seconds
Started Jun 25 04:53:54 PM PDT 24
Finished Jun 25 04:59:56 PM PDT 24
Peak memory 238484 kb
Host smart-d324df8b-3a8b-49b1-86b9-6ae94724b943
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403536297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1403536297
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2667579312
Short name T312
Test name
Test status
Simulation time 2953683864 ps
CPU time 25.82 seconds
Started Jun 25 04:53:55 PM PDT 24
Finished Jun 25 04:54:22 PM PDT 24
Peak memory 211744 kb
Host smart-b6a86020-b265-43c1-a6fe-80f5597dac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667579312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2667579312
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.167435036
Short name T251
Test name
Test status
Simulation time 2942923111 ps
CPU time 13.75 seconds
Started Jun 25 04:53:53 PM PDT 24
Finished Jun 25 04:54:09 PM PDT 24
Peak memory 211356 kb
Host smart-5b7ad07a-0461-4db4-8c83-3c181664480b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167435036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.167435036
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2282955069
Short name T295
Test name
Test status
Simulation time 1328907610 ps
CPU time 16.06 seconds
Started Jun 25 04:53:55 PM PDT 24
Finished Jun 25 04:54:12 PM PDT 24
Peak memory 213604 kb
Host smart-10a02a1e-f3a1-4492-a741-b6d114c69ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282955069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2282955069
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1538031300
Short name T184
Test name
Test status
Simulation time 39506626625 ps
CPU time 103.18 seconds
Started Jun 25 04:53:54 PM PDT 24
Finished Jun 25 04:55:39 PM PDT 24
Peak memory 217188 kb
Host smart-536ebe2b-47fb-4b5e-82cd-69eb58674832
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538031300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1538031300
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.930567432
Short name T272
Test name
Test status
Simulation time 1197048906 ps
CPU time 11.96 seconds
Started Jun 25 04:53:54 PM PDT 24
Finished Jun 25 04:54:08 PM PDT 24
Peak memory 211188 kb
Host smart-065fdcde-1791-4baf-8fb2-f8b877115278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930567432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.930567432
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3163939857
Short name T237
Test name
Test status
Simulation time 1533464811 ps
CPU time 97.04 seconds
Started Jun 25 04:53:53 PM PDT 24
Finished Jun 25 04:55:32 PM PDT 24
Peak memory 236384 kb
Host smart-ae2149ee-f898-4e76-9cdf-86681b1a78cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163939857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3163939857
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2826475545
Short name T186
Test name
Test status
Simulation time 3566506076 ps
CPU time 30.04 seconds
Started Jun 25 04:53:53 PM PDT 24
Finished Jun 25 04:54:25 PM PDT 24
Peak memory 211296 kb
Host smart-b1d1e48d-ce9f-4419-9e1d-e1594537f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826475545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2826475545
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4123286619
Short name T274
Test name
Test status
Simulation time 11059852357 ps
CPU time 17.17 seconds
Started Jun 25 04:53:54 PM PDT 24
Finished Jun 25 04:54:13 PM PDT 24
Peak memory 211292 kb
Host smart-10c0ecc7-4c3a-4f02-90ee-f1684e92a31b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123286619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4123286619
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.869862700
Short name T90
Test name
Test status
Simulation time 1888384431 ps
CPU time 20.21 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:54:14 PM PDT 24
Peak memory 213440 kb
Host smart-7b91c133-6b57-41e9-ba22-a355993bbbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869862700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.869862700
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2031773189
Short name T8
Test name
Test status
Simulation time 8855898674 ps
CPU time 72.11 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:55:06 PM PDT 24
Peak memory 216120 kb
Host smart-329ba733-dedb-4654-a737-e5aaab4f4168
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031773189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2031773189
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2060230952
Short name T364
Test name
Test status
Simulation time 801035590239 ps
CPU time 2840.68 seconds
Started Jun 25 04:53:54 PM PDT 24
Finished Jun 25 05:41:17 PM PDT 24
Peak memory 244100 kb
Host smart-9acc8258-7fa1-45bf-94dd-9b9f015fe4ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060230952 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2060230952
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1320481337
Short name T241
Test name
Test status
Simulation time 1796123985 ps
CPU time 7.16 seconds
Started Jun 25 04:54:02 PM PDT 24
Finished Jun 25 04:54:10 PM PDT 24
Peak memory 211192 kb
Host smart-e080f8a3-fc0f-49b0-91ea-bfeda969b00c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320481337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1320481337
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1041021923
Short name T289
Test name
Test status
Simulation time 1595767472 ps
CPU time 97.98 seconds
Started Jun 25 04:53:53 PM PDT 24
Finished Jun 25 04:55:32 PM PDT 24
Peak memory 237716 kb
Host smart-af0766fe-a3dc-4f17-8e7a-598fc19674a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041021923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1041021923
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.464768915
Short name T313
Test name
Test status
Simulation time 168598190 ps
CPU time 10.03 seconds
Started Jun 25 04:53:51 PM PDT 24
Finished Jun 25 04:54:03 PM PDT 24
Peak memory 211864 kb
Host smart-b69919e4-6dc7-4171-b107-7218ad156f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464768915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.464768915
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4137053777
Short name T181
Test name
Test status
Simulation time 190158012 ps
CPU time 5.61 seconds
Started Jun 25 04:53:54 PM PDT 24
Finished Jun 25 04:54:01 PM PDT 24
Peak memory 211228 kb
Host smart-c5bfed6e-8ebe-4f76-827a-922e9dd5e6c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137053777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4137053777
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2070104496
Short name T282
Test name
Test status
Simulation time 15325042026 ps
CPU time 34.08 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 04:54:27 PM PDT 24
Peak memory 214016 kb
Host smart-f8face41-5bfb-43a9-bf11-c7bb7cc6f3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070104496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2070104496
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1538697225
Short name T311
Test name
Test status
Simulation time 512773074 ps
CPU time 12.09 seconds
Started Jun 25 04:53:50 PM PDT 24
Finished Jun 25 04:54:03 PM PDT 24
Peak memory 211216 kb
Host smart-151425c5-2830-4974-89c5-ab5c67182a3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538697225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1538697225
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.569778060
Short name T45
Test name
Test status
Simulation time 79524768715 ps
CPU time 3279.81 seconds
Started Jun 25 04:53:52 PM PDT 24
Finished Jun 25 05:48:34 PM PDT 24
Peak memory 252220 kb
Host smart-e6497cf0-6f51-4a23-9b9e-e4ad1d9ca66a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569778060 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.569778060
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1164919284
Short name T273
Test name
Test status
Simulation time 1983286264 ps
CPU time 16.59 seconds
Started Jun 25 04:53:20 PM PDT 24
Finished Jun 25 04:53:38 PM PDT 24
Peak memory 211192 kb
Host smart-f7e5dc4f-4f29-4e07-9d9f-dc09705ae8cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164919284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1164919284
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1613897260
Short name T202
Test name
Test status
Simulation time 70323738609 ps
CPU time 347.77 seconds
Started Jun 25 04:53:19 PM PDT 24
Finished Jun 25 04:59:08 PM PDT 24
Peak memory 237864 kb
Host smart-28986fde-6e6a-4e80-80f2-61642fb7423a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613897260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1613897260
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1266968284
Short name T227
Test name
Test status
Simulation time 692533762 ps
CPU time 9.59 seconds
Started Jun 25 04:53:16 PM PDT 24
Finished Jun 25 04:53:27 PM PDT 24
Peak memory 211792 kb
Host smart-252e1bbc-0ae1-4ced-81bc-e97bc618d484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266968284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1266968284
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.104099122
Short name T200
Test name
Test status
Simulation time 732868355 ps
CPU time 8.21 seconds
Started Jun 25 04:53:16 PM PDT 24
Finished Jun 25 04:53:26 PM PDT 24
Peak memory 211228 kb
Host smart-fdf64cd8-9066-4c22-b675-05da69aa863e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104099122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.104099122
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.667999133
Short name T18
Test name
Test status
Simulation time 1778009777 ps
CPU time 61.53 seconds
Started Jun 25 04:53:15 PM PDT 24
Finished Jun 25 04:54:18 PM PDT 24
Peak memory 236564 kb
Host smart-e6a9b0f1-8f51-4b96-8ace-987003933523
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667999133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.667999133
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.921199548
Short name T320
Test name
Test status
Simulation time 177640096 ps
CPU time 9.82 seconds
Started Jun 25 04:53:20 PM PDT 24
Finished Jun 25 04:53:31 PM PDT 24
Peak memory 213264 kb
Host smart-544404f5-7760-424f-8394-fd1c146eb773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921199548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.921199548
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3417671816
Short name T356
Test name
Test status
Simulation time 28300418456 ps
CPU time 61.35 seconds
Started Jun 25 04:53:19 PM PDT 24
Finished Jun 25 04:54:21 PM PDT 24
Peak memory 215680 kb
Host smart-a9b8f546-d97e-4f9b-9776-989cfa8d90e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417671816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3417671816
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.250596996
Short name T345
Test name
Test status
Simulation time 1086619168 ps
CPU time 11.21 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:54:17 PM PDT 24
Peak memory 211184 kb
Host smart-c2e211a7-e27b-4214-be67-c150352db0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250596996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.250596996
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4064795281
Short name T211
Test name
Test status
Simulation time 77803895287 ps
CPU time 164.65 seconds
Started Jun 25 04:54:05 PM PDT 24
Finished Jun 25 04:56:51 PM PDT 24
Peak memory 237708 kb
Host smart-ad77158f-4f50-4f9d-a5d9-99d9a2f2f773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064795281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4064795281
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2938752096
Short name T270
Test name
Test status
Simulation time 201131329 ps
CPU time 9.45 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:54:15 PM PDT 24
Peak memory 211800 kb
Host smart-6064ad94-7359-4e67-9ffe-b7df483d12ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938752096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2938752096
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.74012751
Short name T283
Test name
Test status
Simulation time 7884795923 ps
CPU time 17.01 seconds
Started Jun 25 04:54:03 PM PDT 24
Finished Jun 25 04:54:22 PM PDT 24
Peak memory 211288 kb
Host smart-1b7f3207-4f3f-4c5f-8bcb-60da49372abd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74012751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.74012751
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2415663601
Short name T58
Test name
Test status
Simulation time 8398433438 ps
CPU time 38.53 seconds
Started Jun 25 04:54:05 PM PDT 24
Finished Jun 25 04:54:45 PM PDT 24
Peak memory 214064 kb
Host smart-977a7557-b892-414f-a3c2-86fccf121a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415663601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2415663601
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3667240234
Short name T323
Test name
Test status
Simulation time 28564723927 ps
CPU time 64.08 seconds
Started Jun 25 04:54:07 PM PDT 24
Finished Jun 25 04:55:12 PM PDT 24
Peak memory 215560 kb
Host smart-95dba467-791a-400a-a9c9-cd2e042b4a3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667240234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3667240234
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1956526235
Short name T308
Test name
Test status
Simulation time 1307227824 ps
CPU time 12.13 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:54:17 PM PDT 24
Peak memory 211188 kb
Host smart-ca99d453-79b2-4fe4-9de5-b534c979770d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956526235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1956526235
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.385145344
Short name T366
Test name
Test status
Simulation time 24496544956 ps
CPU time 23.35 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:54:29 PM PDT 24
Peak memory 212256 kb
Host smart-aa9eb4d3-8d1b-4e24-af12-cbdac996ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385145344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.385145344
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1190026311
Short name T136
Test name
Test status
Simulation time 1417396512 ps
CPU time 13.35 seconds
Started Jun 25 04:54:02 PM PDT 24
Finished Jun 25 04:54:16 PM PDT 24
Peak memory 211224 kb
Host smart-0318aa2f-38f5-4c2a-ab63-83309b91f3d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190026311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1190026311
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.817481074
Short name T120
Test name
Test status
Simulation time 15720376108 ps
CPU time 30.69 seconds
Started Jun 25 04:54:01 PM PDT 24
Finished Jun 25 04:54:33 PM PDT 24
Peak memory 214452 kb
Host smart-408a852b-d001-4a1d-82ed-a14817a16c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817481074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.817481074
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1582290512
Short name T173
Test name
Test status
Simulation time 48551619175 ps
CPU time 69.7 seconds
Started Jun 25 04:54:03 PM PDT 24
Finished Jun 25 04:55:14 PM PDT 24
Peak memory 217164 kb
Host smart-39c8c230-5789-4f2a-a5e5-668eb7e79bf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582290512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1582290512
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.564902569
Short name T125
Test name
Test status
Simulation time 3832289534 ps
CPU time 16.12 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:54:21 PM PDT 24
Peak memory 211252 kb
Host smart-9690371e-15ab-4ef1-ac3c-7e78430e78d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564902569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.564902569
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2496461726
Short name T293
Test name
Test status
Simulation time 38782004509 ps
CPU time 377.41 seconds
Started Jun 25 04:54:05 PM PDT 24
Finished Jun 25 05:00:24 PM PDT 24
Peak memory 233692 kb
Host smart-05c663aa-16d5-4fc3-9049-72f849410722
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496461726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2496461726
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.886723893
Short name T216
Test name
Test status
Simulation time 4062447909 ps
CPU time 33.34 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:54:38 PM PDT 24
Peak memory 211820 kb
Host smart-15485ee1-3cdf-4845-8eeb-d1714c5ff986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886723893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.886723893
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1476195554
Short name T266
Test name
Test status
Simulation time 7966168776 ps
CPU time 16.09 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:54:21 PM PDT 24
Peak memory 211288 kb
Host smart-8e8421ab-0b87-44ec-84c2-05bed7269c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476195554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1476195554
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1647858476
Short name T226
Test name
Test status
Simulation time 2413013786 ps
CPU time 17.27 seconds
Started Jun 25 04:54:06 PM PDT 24
Finished Jun 25 04:54:25 PM PDT 24
Peak memory 211700 kb
Host smart-7c1ed1fd-b28b-4e45-98a2-9443305a9ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647858476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1647858476
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3387118778
Short name T118
Test name
Test status
Simulation time 15573343770 ps
CPU time 54.38 seconds
Started Jun 25 04:54:05 PM PDT 24
Finished Jun 25 04:55:01 PM PDT 24
Peak memory 217220 kb
Host smart-968e55f5-8172-45bc-8742-75866165d552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387118778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3387118778
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3563091142
Short name T249
Test name
Test status
Simulation time 102897774391 ps
CPU time 2197.67 seconds
Started Jun 25 04:54:03 PM PDT 24
Finished Jun 25 05:30:42 PM PDT 24
Peak memory 232928 kb
Host smart-4382124f-82c4-4fc6-a906-00aa502e05f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563091142 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3563091142
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1512481865
Short name T154
Test name
Test status
Simulation time 1991772992 ps
CPU time 16.14 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:54:21 PM PDT 24
Peak memory 211196 kb
Host smart-66e5ead6-378c-4ce4-980e-93e7238bdeae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512481865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1512481865
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3773016773
Short name T190
Test name
Test status
Simulation time 49269754070 ps
CPU time 203.08 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:57:28 PM PDT 24
Peak memory 237772 kb
Host smart-3802d3a7-c0f0-417c-b6db-f5fbafe018ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773016773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3773016773
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3332493283
Short name T276
Test name
Test status
Simulation time 45053815727 ps
CPU time 32.78 seconds
Started Jun 25 04:54:00 PM PDT 24
Finished Jun 25 04:54:34 PM PDT 24
Peak memory 212084 kb
Host smart-d9439bbc-20ce-4342-9871-63879098b37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332493283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3332493283
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3632203241
Short name T104
Test name
Test status
Simulation time 1685494981 ps
CPU time 14.9 seconds
Started Jun 25 04:54:04 PM PDT 24
Finished Jun 25 04:54:20 PM PDT 24
Peak memory 211240 kb
Host smart-3298c2f1-7431-47d6-8cfb-c9451f6cadf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3632203241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3632203241
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3600614394
Short name T122
Test name
Test status
Simulation time 3711022140 ps
CPU time 16.63 seconds
Started Jun 25 04:54:03 PM PDT 24
Finished Jun 25 04:54:21 PM PDT 24
Peak memory 213072 kb
Host smart-44c7ff6e-fbc3-4729-9601-5d99307d5327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600614394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3600614394
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3164382816
Short name T258
Test name
Test status
Simulation time 8504321816 ps
CPU time 48.16 seconds
Started Jun 25 04:54:05 PM PDT 24
Finished Jun 25 04:54:55 PM PDT 24
Peak memory 213888 kb
Host smart-9c346028-7ff5-4217-901a-75bebb79ce7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164382816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3164382816
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1671246606
Short name T48
Test name
Test status
Simulation time 92685694766 ps
CPU time 1768.35 seconds
Started Jun 25 04:54:06 PM PDT 24
Finished Jun 25 05:23:36 PM PDT 24
Peak memory 236268 kb
Host smart-182a5fd1-22e6-450f-a186-2e947d36ac02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671246606 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1671246606
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3473774836
Short name T141
Test name
Test status
Simulation time 405993474 ps
CPU time 6.42 seconds
Started Jun 25 04:54:18 PM PDT 24
Finished Jun 25 04:54:25 PM PDT 24
Peak memory 211188 kb
Host smart-aec42d27-cfe1-4359-9b7f-9aa4672a4e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473774836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3473774836
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4043641218
Short name T314
Test name
Test status
Simulation time 2497307571 ps
CPU time 172.82 seconds
Started Jun 25 04:54:17 PM PDT 24
Finished Jun 25 04:57:11 PM PDT 24
Peak memory 228516 kb
Host smart-d2f8b961-4b2d-4217-98e2-1abf14b6d7f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043641218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4043641218
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3954539023
Short name T265
Test name
Test status
Simulation time 15034942939 ps
CPU time 26.4 seconds
Started Jun 25 04:54:15 PM PDT 24
Finished Jun 25 04:54:42 PM PDT 24
Peak memory 212520 kb
Host smart-64e90d84-4ff3-4dbf-9618-f67ea1ed8bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954539023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3954539023
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.981738961
Short name T355
Test name
Test status
Simulation time 832140177 ps
CPU time 9.43 seconds
Started Jun 25 04:54:17 PM PDT 24
Finished Jun 25 04:54:27 PM PDT 24
Peak memory 211240 kb
Host smart-2e0ff857-b167-4ddf-9171-f4f8fbba23cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981738961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.981738961
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2062051047
Short name T331
Test name
Test status
Simulation time 4183447599 ps
CPU time 28.04 seconds
Started Jun 25 04:54:16 PM PDT 24
Finished Jun 25 04:54:45 PM PDT 24
Peak memory 213528 kb
Host smart-416f15b6-257a-42b6-96b0-af73da990d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062051047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2062051047
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4252851845
Short name T279
Test name
Test status
Simulation time 31917729301 ps
CPU time 56.02 seconds
Started Jun 25 04:54:18 PM PDT 24
Finished Jun 25 04:55:15 PM PDT 24
Peak memory 216332 kb
Host smart-eee6784b-b0f0-48bd-a70c-2e1642b19091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252851845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4252851845
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2700899937
Short name T329
Test name
Test status
Simulation time 8191715082 ps
CPU time 16.15 seconds
Started Jun 25 04:54:15 PM PDT 24
Finished Jun 25 04:54:32 PM PDT 24
Peak memory 211256 kb
Host smart-126f17d0-5312-4f52-8def-bb48824334ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700899937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2700899937
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4265256361
Short name T156
Test name
Test status
Simulation time 8812352703 ps
CPU time 165.57 seconds
Started Jun 25 04:54:14 PM PDT 24
Finished Jun 25 04:57:01 PM PDT 24
Peak memory 237816 kb
Host smart-64237daa-0c21-4991-877c-f434967e9063
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265256361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4265256361
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1803605200
Short name T134
Test name
Test status
Simulation time 1121149064 ps
CPU time 16.36 seconds
Started Jun 25 04:54:18 PM PDT 24
Finished Jun 25 04:54:35 PM PDT 24
Peak memory 211844 kb
Host smart-ff5cd4dd-b836-4760-bc6d-ba8d6b2553b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803605200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1803605200
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.695852888
Short name T33
Test name
Test status
Simulation time 96665221 ps
CPU time 5.61 seconds
Started Jun 25 04:54:19 PM PDT 24
Finished Jun 25 04:54:26 PM PDT 24
Peak memory 211240 kb
Host smart-cbd96f7f-ad39-4dbd-a9b5-54b2e3edabbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695852888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.695852888
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1050825063
Short name T165
Test name
Test status
Simulation time 2094821730 ps
CPU time 26.02 seconds
Started Jun 25 04:54:17 PM PDT 24
Finished Jun 25 04:54:44 PM PDT 24
Peak memory 213200 kb
Host smart-e335d707-c787-4018-b80d-2d23d71bdd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050825063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1050825063
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.421002859
Short name T175
Test name
Test status
Simulation time 15520665373 ps
CPU time 61.56 seconds
Started Jun 25 04:54:15 PM PDT 24
Finished Jun 25 04:55:17 PM PDT 24
Peak memory 217092 kb
Host smart-cebee314-2a43-45e7-add5-870560efae3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421002859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.421002859
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4182126709
Short name T349
Test name
Test status
Simulation time 1437668981 ps
CPU time 9.06 seconds
Started Jun 25 04:54:16 PM PDT 24
Finished Jun 25 04:54:27 PM PDT 24
Peak memory 211196 kb
Host smart-a225b922-6bfb-4672-aca9-bab169995707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182126709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4182126709
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2014577419
Short name T20
Test name
Test status
Simulation time 26572001004 ps
CPU time 209 seconds
Started Jun 25 04:54:17 PM PDT 24
Finished Jun 25 04:57:47 PM PDT 24
Peak memory 225604 kb
Host smart-132d201d-1931-4f95-9353-440095b4a43c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014577419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2014577419
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2322598030
Short name T242
Test name
Test status
Simulation time 2479452913 ps
CPU time 23.98 seconds
Started Jun 25 04:54:15 PM PDT 24
Finished Jun 25 04:54:40 PM PDT 24
Peak memory 211268 kb
Host smart-4a0efb5b-4374-485d-9ac3-2f649f71f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322598030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2322598030
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1047269269
Short name T119
Test name
Test status
Simulation time 190019335 ps
CPU time 5.74 seconds
Started Jun 25 04:54:16 PM PDT 24
Finished Jun 25 04:54:23 PM PDT 24
Peak memory 211316 kb
Host smart-cc5c337d-a832-4e09-9357-b5b4f3b793c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1047269269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1047269269
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3636880562
Short name T148
Test name
Test status
Simulation time 3629189274 ps
CPU time 30.46 seconds
Started Jun 25 04:54:14 PM PDT 24
Finished Jun 25 04:54:45 PM PDT 24
Peak memory 213256 kb
Host smart-dcf9df31-e070-4dee-8b97-47624d9c3d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636880562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3636880562
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1348577367
Short name T87
Test name
Test status
Simulation time 14972225180 ps
CPU time 74.05 seconds
Started Jun 25 04:54:20 PM PDT 24
Finished Jun 25 04:55:35 PM PDT 24
Peak memory 219376 kb
Host smart-61ceb2da-e3b5-4b8f-b187-d808b7e57c89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348577367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1348577367
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2289193911
Short name T353
Test name
Test status
Simulation time 740340920 ps
CPU time 8.05 seconds
Started Jun 25 04:54:18 PM PDT 24
Finished Jun 25 04:54:27 PM PDT 24
Peak memory 211200 kb
Host smart-f29e41d2-100f-4621-af3d-b995aca2d2bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289193911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2289193911
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1298998233
Short name T208
Test name
Test status
Simulation time 68942552811 ps
CPU time 306.14 seconds
Started Jun 25 04:54:13 PM PDT 24
Finished Jun 25 04:59:20 PM PDT 24
Peak memory 237768 kb
Host smart-a572cf82-90ad-4968-b0fc-58a54eea77f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298998233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1298998233
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.996170415
Short name T338
Test name
Test status
Simulation time 6346237375 ps
CPU time 27.34 seconds
Started Jun 25 04:54:18 PM PDT 24
Finished Jun 25 04:54:46 PM PDT 24
Peak memory 212452 kb
Host smart-b9670291-0d52-457b-b680-e94c53044923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996170415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.996170415
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1941693292
Short name T347
Test name
Test status
Simulation time 374434262 ps
CPU time 5.92 seconds
Started Jun 25 04:54:22 PM PDT 24
Finished Jun 25 04:54:29 PM PDT 24
Peak memory 211236 kb
Host smart-ece338e4-adfd-439e-81e5-595b546f49ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941693292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1941693292
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1997085822
Short name T68
Test name
Test status
Simulation time 1262090287 ps
CPU time 19.2 seconds
Started Jun 25 04:54:16 PM PDT 24
Finished Jun 25 04:54:37 PM PDT 24
Peak memory 213860 kb
Host smart-86010e37-f5dd-44a8-98f2-bd0af4488dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997085822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1997085822
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1515818440
Short name T30
Test name
Test status
Simulation time 1916865715 ps
CPU time 12.44 seconds
Started Jun 25 04:54:15 PM PDT 24
Finished Jun 25 04:54:29 PM PDT 24
Peak memory 211248 kb
Host smart-3b78719f-860b-4db2-9f1b-d32189bdb6de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515818440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1515818440
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2348620660
Short name T360
Test name
Test status
Simulation time 854351508 ps
CPU time 6.02 seconds
Started Jun 25 04:54:16 PM PDT 24
Finished Jun 25 04:54:23 PM PDT 24
Peak memory 211248 kb
Host smart-87d9fad6-89f1-4fdb-9d2a-0fa71514528c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348620660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2348620660
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.387289653
Short name T149
Test name
Test status
Simulation time 3856185962 ps
CPU time 156.25 seconds
Started Jun 25 04:54:15 PM PDT 24
Finished Jun 25 04:56:53 PM PDT 24
Peak memory 234800 kb
Host smart-897d3c03-81be-4c48-b887-82572081f8ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387289653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.387289653
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.356695497
Short name T291
Test name
Test status
Simulation time 2987313629 ps
CPU time 14.44 seconds
Started Jun 25 04:54:16 PM PDT 24
Finished Jun 25 04:54:31 PM PDT 24
Peak memory 211296 kb
Host smart-db198879-9627-4058-87eb-70de60b3eb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356695497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.356695497
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1605840880
Short name T342
Test name
Test status
Simulation time 16781232294 ps
CPU time 32.44 seconds
Started Jun 25 04:54:18 PM PDT 24
Finished Jun 25 04:54:52 PM PDT 24
Peak memory 214424 kb
Host smart-51ea494f-d414-46ee-855b-394fe1210494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605840880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1605840880
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1544713359
Short name T225
Test name
Test status
Simulation time 10574945574 ps
CPU time 89.94 seconds
Started Jun 25 04:54:16 PM PDT 24
Finished Jun 25 04:55:47 PM PDT 24
Peak memory 216324 kb
Host smart-09663023-a381-455f-bd87-5cc5e452e422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544713359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1544713359
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.787768885
Short name T164
Test name
Test status
Simulation time 1601770050 ps
CPU time 13.31 seconds
Started Jun 25 04:54:16 PM PDT 24
Finished Jun 25 04:54:30 PM PDT 24
Peak memory 211184 kb
Host smart-3c839c25-9688-4223-82d4-e12665d87d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787768885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.787768885
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1863539728
Short name T40
Test name
Test status
Simulation time 41418920367 ps
CPU time 359.07 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 05:00:26 PM PDT 24
Peak memory 237768 kb
Host smart-f4ff6dc2-569b-4277-8503-2cd53f5a537a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863539728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1863539728
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2448374338
Short name T222
Test name
Test status
Simulation time 2528170774 ps
CPU time 24.4 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 04:54:51 PM PDT 24
Peak memory 211296 kb
Host smart-dfe37ad7-a545-4b3e-a9d1-ebc552d6fc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448374338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2448374338
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1755619501
Short name T296
Test name
Test status
Simulation time 645467351 ps
CPU time 9.49 seconds
Started Jun 25 04:54:18 PM PDT 24
Finished Jun 25 04:54:29 PM PDT 24
Peak memory 211244 kb
Host smart-61da1195-b37b-4bd7-8346-67e987ea18f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755619501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1755619501
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2882876724
Short name T213
Test name
Test status
Simulation time 191049500 ps
CPU time 10.56 seconds
Started Jun 25 04:54:17 PM PDT 24
Finished Jun 25 04:54:29 PM PDT 24
Peak memory 213560 kb
Host smart-f0ee8d9c-b9b5-4fea-843b-7bd4d4bbdd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882876724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2882876724
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4153531693
Short name T130
Test name
Test status
Simulation time 1442552584 ps
CPU time 12.94 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 04:54:40 PM PDT 24
Peak memory 211248 kb
Host smart-9b94794f-02c2-4619-86f4-69c2260d9a2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153531693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4153531693
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1385163102
Short name T11
Test name
Test status
Simulation time 76661839271 ps
CPU time 2999.15 seconds
Started Jun 25 04:54:18 PM PDT 24
Finished Jun 25 05:44:18 PM PDT 24
Peak memory 252156 kb
Host smart-2d3611a6-b28d-4a2b-b6c3-60389e2dd479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385163102 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1385163102
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3931903022
Short name T288
Test name
Test status
Simulation time 9837874541 ps
CPU time 14.69 seconds
Started Jun 25 04:53:16 PM PDT 24
Finished Jun 25 04:53:32 PM PDT 24
Peak memory 211256 kb
Host smart-d597bb48-c06e-49c8-bf7f-60ba5d10bc3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931903022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3931903022
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2662602649
Short name T254
Test name
Test status
Simulation time 63975884302 ps
CPU time 212.14 seconds
Started Jun 25 04:53:19 PM PDT 24
Finished Jun 25 04:56:52 PM PDT 24
Peak memory 237704 kb
Host smart-2b8ba317-8ddb-41b5-bc12-e712b9c256ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662602649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2662602649
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.138775131
Short name T309
Test name
Test status
Simulation time 2005668273 ps
CPU time 15.96 seconds
Started Jun 25 04:53:19 PM PDT 24
Finished Jun 25 04:53:36 PM PDT 24
Peak memory 211916 kb
Host smart-06e6eea6-9cf1-41c5-8f9d-42e241b7515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138775131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.138775131
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1415512541
Short name T305
Test name
Test status
Simulation time 2204673635 ps
CPU time 16.87 seconds
Started Jun 25 04:53:17 PM PDT 24
Finished Jun 25 04:53:35 PM PDT 24
Peak memory 211284 kb
Host smart-c3070526-4672-4701-969e-20cb508ce001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415512541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1415512541
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1925131008
Short name T264
Test name
Test status
Simulation time 19828518918 ps
CPU time 21.98 seconds
Started Jun 25 04:53:19 PM PDT 24
Finished Jun 25 04:53:42 PM PDT 24
Peak memory 214104 kb
Host smart-400e68d9-87a6-4511-9a7b-55796f4a01c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925131008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1925131008
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2154760675
Short name T31
Test name
Test status
Simulation time 880883831 ps
CPU time 17.89 seconds
Started Jun 25 04:53:19 PM PDT 24
Finished Jun 25 04:53:38 PM PDT 24
Peak memory 214784 kb
Host smart-a70c66ec-12b3-4bcb-b5a6-9310695fa009
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154760675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2154760675
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2782774322
Short name T55
Test name
Test status
Simulation time 16336252967 ps
CPU time 11.54 seconds
Started Jun 25 04:54:27 PM PDT 24
Finished Jun 25 04:54:39 PM PDT 24
Peak memory 211304 kb
Host smart-b6c43b0a-6cad-4773-81f9-d02622f3c092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782774322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2782774322
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4255615104
Short name T328
Test name
Test status
Simulation time 51232275070 ps
CPU time 294.12 seconds
Started Jun 25 04:54:24 PM PDT 24
Finished Jun 25 04:59:19 PM PDT 24
Peak memory 212380 kb
Host smart-c1d65d8b-fa1b-4f32-a6ed-1cf0b0f3108c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255615104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4255615104
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.412747153
Short name T42
Test name
Test status
Simulation time 1379325635 ps
CPU time 15.55 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 04:54:42 PM PDT 24
Peak memory 211868 kb
Host smart-9353074f-98c3-478a-8334-3df0e234c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412747153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.412747153
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2409003358
Short name T124
Test name
Test status
Simulation time 381195984 ps
CPU time 5.56 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 04:54:32 PM PDT 24
Peak memory 211232 kb
Host smart-7a28ef6e-9633-4263-a037-a239bdfc189a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409003358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2409003358
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.865500451
Short name T142
Test name
Test status
Simulation time 10224357778 ps
CPU time 30.71 seconds
Started Jun 25 04:54:18 PM PDT 24
Finished Jun 25 04:54:50 PM PDT 24
Peak memory 214140 kb
Host smart-35bb3007-f244-4ec1-b844-2033df1c51a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865500451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.865500451
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2003542763
Short name T146
Test name
Test status
Simulation time 15535343774 ps
CPU time 78.06 seconds
Started Jun 25 04:54:23 PM PDT 24
Finished Jun 25 04:55:42 PM PDT 24
Peak memory 216624 kb
Host smart-c0b55cd9-b3f0-4cfa-a513-43e61272e8a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003542763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2003542763
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.4223350519
Short name T351
Test name
Test status
Simulation time 70473988306 ps
CPU time 4431.17 seconds
Started Jun 25 04:54:24 PM PDT 24
Finished Jun 25 06:08:16 PM PDT 24
Peak memory 235820 kb
Host smart-ef42526b-2f4f-4bc1-b910-03769f2017c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223350519 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.4223350519
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1133919552
Short name T324
Test name
Test status
Simulation time 2175745611 ps
CPU time 10.77 seconds
Started Jun 25 04:54:26 PM PDT 24
Finished Jun 25 04:54:38 PM PDT 24
Peak memory 211332 kb
Host smart-63eb4260-1d82-430f-bc44-883fae8afd76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133919552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1133919552
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3964749031
Short name T204
Test name
Test status
Simulation time 75868582949 ps
CPU time 132.96 seconds
Started Jun 25 04:54:24 PM PDT 24
Finished Jun 25 04:56:38 PM PDT 24
Peak memory 237268 kb
Host smart-05a81f79-8cfb-4dfc-af7c-5f30ea2b0473
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964749031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3964749031
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2973809290
Short name T9
Test name
Test status
Simulation time 4867598200 ps
CPU time 12.15 seconds
Started Jun 25 04:54:28 PM PDT 24
Finished Jun 25 04:54:41 PM PDT 24
Peak memory 211304 kb
Host smart-c4e7f602-e9c6-429c-9523-c1d6762eb952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973809290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2973809290
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1751460772
Short name T221
Test name
Test status
Simulation time 628741270 ps
CPU time 10.21 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 04:54:37 PM PDT 24
Peak memory 213440 kb
Host smart-fe587b70-2de0-4c97-b41a-4d0d95ce3513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751460772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1751460772
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2087169800
Short name T220
Test name
Test status
Simulation time 3953119020 ps
CPU time 36.14 seconds
Started Jun 25 04:54:24 PM PDT 24
Finished Jun 25 04:55:01 PM PDT 24
Peak memory 213768 kb
Host smart-0e8c54c4-fd56-4175-b46a-dc54ba295366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087169800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2087169800
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1001631985
Short name T294
Test name
Test status
Simulation time 4981873883 ps
CPU time 12.15 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 04:54:38 PM PDT 24
Peak memory 211260 kb
Host smart-e1d2acd3-af2e-46ff-bffd-4c4909529055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001631985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1001631985
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3585344189
Short name T201
Test name
Test status
Simulation time 53759804975 ps
CPU time 323.28 seconds
Started Jun 25 04:54:24 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 234832 kb
Host smart-519ee4b3-b97a-4a88-82da-b06b016436c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585344189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3585344189
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.208274880
Short name T256
Test name
Test status
Simulation time 2556404851 ps
CPU time 24.06 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 04:54:50 PM PDT 24
Peak memory 211996 kb
Host smart-2ffc4ab4-4794-4c61-8451-8f7c86f396c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208274880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.208274880
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1313040093
Short name T337
Test name
Test status
Simulation time 1540466684 ps
CPU time 5.77 seconds
Started Jun 25 04:54:26 PM PDT 24
Finished Jun 25 04:54:33 PM PDT 24
Peak memory 211244 kb
Host smart-1a943be4-e9a5-4975-b103-7b23786ff336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313040093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1313040093
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4239250743
Short name T32
Test name
Test status
Simulation time 3638588032 ps
CPU time 15.02 seconds
Started Jun 25 04:54:29 PM PDT 24
Finished Jun 25 04:54:45 PM PDT 24
Peak memory 213684 kb
Host smart-442491c1-8067-4cbf-b6a2-5f5c64dc86b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239250743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4239250743
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.583553342
Short name T131
Test name
Test status
Simulation time 4042335283 ps
CPU time 25.45 seconds
Started Jun 25 04:54:26 PM PDT 24
Finished Jun 25 04:54:53 PM PDT 24
Peak memory 211348 kb
Host smart-bc598f2f-2004-4eb3-9b4e-b7ebae0db703
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583553342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.583553342
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1451441396
Short name T290
Test name
Test status
Simulation time 6009841613 ps
CPU time 13.6 seconds
Started Jun 25 04:54:23 PM PDT 24
Finished Jun 25 04:54:37 PM PDT 24
Peak memory 211308 kb
Host smart-58a2dbfa-1a4f-4203-b52f-081e8a34ae75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451441396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1451441396
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2991000164
Short name T182
Test name
Test status
Simulation time 31628009867 ps
CPU time 233.22 seconds
Started Jun 25 04:54:24 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 228480 kb
Host smart-e365d613-f41c-4d5f-a7cf-c94d466276d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991000164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2991000164
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3675252767
Short name T322
Test name
Test status
Simulation time 2775904432 ps
CPU time 26.14 seconds
Started Jun 25 04:54:24 PM PDT 24
Finished Jun 25 04:54:51 PM PDT 24
Peak memory 211912 kb
Host smart-cb875af6-3a32-4f70-9083-ea6053bcc4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675252767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3675252767
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.403168117
Short name T277
Test name
Test status
Simulation time 2136648124 ps
CPU time 17.85 seconds
Started Jun 25 04:54:27 PM PDT 24
Finished Jun 25 04:54:46 PM PDT 24
Peak memory 211236 kb
Host smart-a291b820-f68b-442b-a90a-bdc1456ba1a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403168117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.403168117
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1654290896
Short name T357
Test name
Test status
Simulation time 595215675 ps
CPU time 15.71 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 04:54:42 PM PDT 24
Peak memory 213836 kb
Host smart-c9ada352-0fe6-436d-9445-a2cfc6ce263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654290896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1654290896
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1939750989
Short name T284
Test name
Test status
Simulation time 462709787 ps
CPU time 24.13 seconds
Started Jun 25 04:54:26 PM PDT 24
Finished Jun 25 04:54:52 PM PDT 24
Peak memory 215228 kb
Host smart-67b5309c-efa5-4081-8664-dd9423bce824
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939750989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1939750989
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1566802074
Short name T234
Test name
Test status
Simulation time 1977136909 ps
CPU time 15.91 seconds
Started Jun 25 04:54:27 PM PDT 24
Finished Jun 25 04:54:44 PM PDT 24
Peak memory 211236 kb
Host smart-3f31ed25-7838-4869-8e12-7f97245e4679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566802074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1566802074
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.318134140
Short name T35
Test name
Test status
Simulation time 390708864962 ps
CPU time 379.16 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 237772 kb
Host smart-4223643f-a066-4b0e-ad97-148d59553ff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318134140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.318134140
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.681032303
Short name T185
Test name
Test status
Simulation time 2396293845 ps
CPU time 24.86 seconds
Started Jun 25 04:54:27 PM PDT 24
Finished Jun 25 04:54:53 PM PDT 24
Peak memory 211356 kb
Host smart-ae05d705-823e-4c2b-b97d-ff8c4780a257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681032303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.681032303
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2476956558
Short name T99
Test name
Test status
Simulation time 1138995847 ps
CPU time 7.57 seconds
Started Jun 25 04:54:26 PM PDT 24
Finished Jun 25 04:54:35 PM PDT 24
Peak memory 211212 kb
Host smart-71560fa1-c159-4de9-ac38-c90cb708a447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2476956558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2476956558
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.547672970
Short name T158
Test name
Test status
Simulation time 188170495 ps
CPU time 10.27 seconds
Started Jun 25 04:54:26 PM PDT 24
Finished Jun 25 04:54:37 PM PDT 24
Peak memory 213280 kb
Host smart-ed4de33a-f816-4b9e-8a3f-cbd853b7a043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547672970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.547672970
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1856567684
Short name T172
Test name
Test status
Simulation time 1553613768 ps
CPU time 21.6 seconds
Started Jun 25 04:54:29 PM PDT 24
Finished Jun 25 04:54:51 PM PDT 24
Peak memory 213720 kb
Host smart-aed046a5-922d-4b37-a72f-d3f905a4eaf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856567684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1856567684
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1745578513
Short name T12
Test name
Test status
Simulation time 133324833147 ps
CPU time 615.67 seconds
Started Jun 25 04:54:25 PM PDT 24
Finished Jun 25 05:04:42 PM PDT 24
Peak memory 235816 kb
Host smart-02b167a2-8c00-4ebe-80e2-8ea46e96be2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745578513 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1745578513
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3313889806
Short name T24
Test name
Test status
Simulation time 493473037 ps
CPU time 7.26 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:54:41 PM PDT 24
Peak memory 211192 kb
Host smart-df78e11b-7fd8-40d7-9713-dec05ed85704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313889806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3313889806
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.338789806
Short name T151
Test name
Test status
Simulation time 58036850300 ps
CPU time 597.16 seconds
Started Jun 25 04:54:38 PM PDT 24
Finished Jun 25 05:04:36 PM PDT 24
Peak memory 234892 kb
Host smart-5eb9c2ef-1f18-45a8-be36-96a2d844cae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338789806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.338789806
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1221712929
Short name T339
Test name
Test status
Simulation time 3613082035 ps
CPU time 29.95 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:55:04 PM PDT 24
Peak memory 211280 kb
Host smart-603916da-33c9-4355-a869-50604718659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221712929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1221712929
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1704916576
Short name T137
Test name
Test status
Simulation time 1022320907 ps
CPU time 11.37 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:54:45 PM PDT 24
Peak memory 211236 kb
Host smart-ac88ffbd-51d2-40bc-8d74-7311ddc69568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704916576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1704916576
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1549398366
Short name T271
Test name
Test status
Simulation time 336244625 ps
CPU time 18.73 seconds
Started Jun 25 04:54:34 PM PDT 24
Finished Jun 25 04:54:54 PM PDT 24
Peak memory 215200 kb
Host smart-fcb3aad2-7e22-4344-a788-8ebab0e5d856
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549398366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1549398366
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.814892719
Short name T49
Test name
Test status
Simulation time 30368431189 ps
CPU time 8461.64 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 07:15:37 PM PDT 24
Peak memory 230464 kb
Host smart-57f4321e-17c7-4866-9e73-fa3aad2c722c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814892719 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.814892719
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1330251945
Short name T23
Test name
Test status
Simulation time 333354280 ps
CPU time 4.35 seconds
Started Jun 25 04:54:35 PM PDT 24
Finished Jun 25 04:54:40 PM PDT 24
Peak memory 211248 kb
Host smart-7d97d4d3-030e-4f44-b3dc-77a529b66819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330251945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1330251945
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1437150756
Short name T207
Test name
Test status
Simulation time 5107096181 ps
CPU time 149.17 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:57:03 PM PDT 24
Peak memory 239828 kb
Host smart-85052b0f-d749-43c3-aca9-51980b06bed7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437150756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1437150756
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3573668780
Short name T197
Test name
Test status
Simulation time 5197886401 ps
CPU time 33.04 seconds
Started Jun 25 04:54:34 PM PDT 24
Finished Jun 25 04:55:08 PM PDT 24
Peak memory 212248 kb
Host smart-5202d1dd-d1d4-49de-b7b2-bcfdca5118dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573668780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3573668780
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1304909564
Short name T229
Test name
Test status
Simulation time 4608789481 ps
CPU time 12.15 seconds
Started Jun 25 04:54:34 PM PDT 24
Finished Jun 25 04:54:48 PM PDT 24
Peak memory 211300 kb
Host smart-a78a6fbe-218e-4e44-acc1-b52bd53174b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1304909564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1304909564
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.506747692
Short name T152
Test name
Test status
Simulation time 4155472045 ps
CPU time 33.37 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:55:07 PM PDT 24
Peak memory 213204 kb
Host smart-6fa736ff-4286-4f7b-a046-12b4410c116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506747692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.506747692
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3108915856
Short name T209
Test name
Test status
Simulation time 699152830 ps
CPU time 11.87 seconds
Started Jun 25 04:54:35 PM PDT 24
Finished Jun 25 04:54:48 PM PDT 24
Peak memory 214164 kb
Host smart-0e0d6528-230b-4074-87c1-835a27f9c126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108915856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3108915856
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1871643813
Short name T25
Test name
Test status
Simulation time 1919013490 ps
CPU time 10.56 seconds
Started Jun 25 04:54:34 PM PDT 24
Finished Jun 25 04:54:46 PM PDT 24
Peak memory 211248 kb
Host smart-43595f30-5247-4e13-b3c4-140466d29865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871643813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1871643813
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3708679085
Short name T192
Test name
Test status
Simulation time 2412287918 ps
CPU time 23.65 seconds
Started Jun 25 04:54:42 PM PDT 24
Finished Jun 25 04:55:07 PM PDT 24
Peak memory 212000 kb
Host smart-f764bb35-928c-4bf6-8f72-661a4aedc5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708679085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3708679085
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3049374734
Short name T163
Test name
Test status
Simulation time 358137427 ps
CPU time 5.36 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:54:40 PM PDT 24
Peak memory 211208 kb
Host smart-52c8f57f-2edd-453c-abd2-26b6a02248aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049374734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3049374734
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2089304086
Short name T176
Test name
Test status
Simulation time 3791779458 ps
CPU time 31.46 seconds
Started Jun 25 04:54:35 PM PDT 24
Finished Jun 25 04:55:08 PM PDT 24
Peak memory 213780 kb
Host smart-98e3887d-b9f2-4a4b-b67a-ad5387170faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089304086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2089304086
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4161109577
Short name T187
Test name
Test status
Simulation time 127372364 ps
CPU time 6.6 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:54:41 PM PDT 24
Peak memory 211248 kb
Host smart-e561242a-c393-4432-97f1-b3417a67e2ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161109577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4161109577
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.4051031930
Short name T47
Test name
Test status
Simulation time 218242096191 ps
CPU time 1495.38 seconds
Started Jun 25 04:54:38 PM PDT 24
Finished Jun 25 05:19:34 PM PDT 24
Peak memory 235816 kb
Host smart-92536800-d8d4-4b3d-b03f-84ed9e1e7663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051031930 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.4051031930
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2223105560
Short name T162
Test name
Test status
Simulation time 1697638593 ps
CPU time 6.9 seconds
Started Jun 25 04:54:32 PM PDT 24
Finished Jun 25 04:54:40 PM PDT 24
Peak memory 211164 kb
Host smart-23971096-ef78-491b-a373-ae87d65bc5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223105560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2223105560
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4108260200
Short name T286
Test name
Test status
Simulation time 1214023953 ps
CPU time 74.51 seconds
Started Jun 25 04:54:38 PM PDT 24
Finished Jun 25 04:55:53 PM PDT 24
Peak memory 232664 kb
Host smart-9a3618a8-0865-4b22-ae46-079070a3fb40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108260200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4108260200
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1896073936
Short name T150
Test name
Test status
Simulation time 1170984559 ps
CPU time 16.74 seconds
Started Jun 25 04:54:32 PM PDT 24
Finished Jun 25 04:54:50 PM PDT 24
Peak memory 212356 kb
Host smart-d9cff845-bf6b-4d43-846e-1ab5ad677dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896073936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1896073936
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2452957329
Short name T103
Test name
Test status
Simulation time 2414676885 ps
CPU time 12.71 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:54:47 PM PDT 24
Peak memory 211376 kb
Host smart-b5dedb11-2ab3-4203-9d6b-3b7ba032fca3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452957329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2452957329
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4244474207
Short name T84
Test name
Test status
Simulation time 8612323063 ps
CPU time 27.56 seconds
Started Jun 25 04:54:42 PM PDT 24
Finished Jun 25 04:55:10 PM PDT 24
Peak memory 214524 kb
Host smart-894e6d76-b496-4fb2-82dc-c9037104a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244474207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4244474207
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2409032669
Short name T230
Test name
Test status
Simulation time 1612337791 ps
CPU time 17.62 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:54:52 PM PDT 24
Peak memory 211236 kb
Host smart-4ab67ec2-9a81-4b93-b15e-963cd07c1eb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409032669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2409032669
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1765459075
Short name T285
Test name
Test status
Simulation time 8730258527 ps
CPU time 15.28 seconds
Started Jun 25 04:54:41 PM PDT 24
Finished Jun 25 04:54:58 PM PDT 24
Peak memory 211260 kb
Host smart-073128a5-232c-48e0-9f5c-ff59278f75e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765459075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1765459075
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.224269132
Short name T310
Test name
Test status
Simulation time 4976728186 ps
CPU time 83.61 seconds
Started Jun 25 04:54:34 PM PDT 24
Finished Jun 25 04:55:59 PM PDT 24
Peak memory 225620 kb
Host smart-5f04143c-463f-4ec5-87ff-d75bba4c1b10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224269132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.224269132
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.804698198
Short name T363
Test name
Test status
Simulation time 2053451725 ps
CPU time 22.67 seconds
Started Jun 25 04:54:38 PM PDT 24
Finished Jun 25 04:55:01 PM PDT 24
Peak memory 211852 kb
Host smart-443bdeae-aff2-49e1-bad3-7c72c2701a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804698198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.804698198
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3759946758
Short name T257
Test name
Test status
Simulation time 5872544766 ps
CPU time 11.59 seconds
Started Jun 25 04:54:34 PM PDT 24
Finished Jun 25 04:54:47 PM PDT 24
Peak memory 211344 kb
Host smart-7ac52f69-8d77-4aeb-8a83-d377c84a0942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759946758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3759946758
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1732809753
Short name T215
Test name
Test status
Simulation time 17375583343 ps
CPU time 34.06 seconds
Started Jun 25 04:54:35 PM PDT 24
Finished Jun 25 04:55:10 PM PDT 24
Peak memory 214628 kb
Host smart-457199c6-39fd-4c97-9037-ce9f4ea08d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732809753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1732809753
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2160125666
Short name T219
Test name
Test status
Simulation time 4342092016 ps
CPU time 16.88 seconds
Started Jun 25 04:54:35 PM PDT 24
Finished Jun 25 04:54:53 PM PDT 24
Peak memory 214856 kb
Host smart-4287b153-2fb5-41c1-89a9-de945f73dbb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160125666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2160125666
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.835047095
Short name T280
Test name
Test status
Simulation time 165111520804 ps
CPU time 6915.94 seconds
Started Jun 25 04:54:32 PM PDT 24
Finished Jun 25 06:49:49 PM PDT 24
Peak memory 237460 kb
Host smart-396ae0ff-e6c9-422a-9586-b0364e5dd27a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835047095 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.835047095
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.114032631
Short name T145
Test name
Test status
Simulation time 6820355970 ps
CPU time 14.07 seconds
Started Jun 25 04:53:28 PM PDT 24
Finished Jun 25 04:53:43 PM PDT 24
Peak memory 211224 kb
Host smart-6b6012cd-0e40-42a8-a2d1-ae533374119a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114032631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.114032631
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3580096596
Short name T174
Test name
Test status
Simulation time 275831536 ps
CPU time 6.77 seconds
Started Jun 25 04:53:24 PM PDT 24
Finished Jun 25 04:53:32 PM PDT 24
Peak memory 211232 kb
Host smart-0ca2b9a8-153c-4748-b676-6b1a06d33762
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580096596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3580096596
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2303963859
Short name T27
Test name
Test status
Simulation time 236262450 ps
CPU time 101.06 seconds
Started Jun 25 04:53:25 PM PDT 24
Finished Jun 25 04:55:07 PM PDT 24
Peak memory 236776 kb
Host smart-547ff1e1-ed35-414b-bbcd-42f515e16bdb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303963859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2303963859
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1635311622
Short name T123
Test name
Test status
Simulation time 681403492 ps
CPU time 15.35 seconds
Started Jun 25 04:53:24 PM PDT 24
Finished Jun 25 04:53:40 PM PDT 24
Peak memory 213424 kb
Host smart-060e6510-c991-4a0d-aa54-cf16d0e9dfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635311622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1635311622
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1418055800
Short name T83
Test name
Test status
Simulation time 12209960559 ps
CPU time 36.18 seconds
Started Jun 25 04:53:27 PM PDT 24
Finished Jun 25 04:54:04 PM PDT 24
Peak memory 213212 kb
Host smart-e1f38019-cd91-40f4-bcbb-0e27decf4c91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418055800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1418055800
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3012973738
Short name T333
Test name
Test status
Simulation time 979975576 ps
CPU time 10.64 seconds
Started Jun 25 04:54:44 PM PDT 24
Finished Jun 25 04:54:55 PM PDT 24
Peak memory 211192 kb
Host smart-5d74db4b-5945-4640-9b3d-82a68d86bc05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012973738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3012973738
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2869977723
Short name T244
Test name
Test status
Simulation time 49250363706 ps
CPU time 446.11 seconds
Started Jun 25 04:54:41 PM PDT 24
Finished Jun 25 05:02:08 PM PDT 24
Peak memory 234836 kb
Host smart-197e8c2b-8cd6-498e-89c4-e2e8e21fa7f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869977723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2869977723
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.336581670
Short name T132
Test name
Test status
Simulation time 1736923684 ps
CPU time 19.8 seconds
Started Jun 25 04:54:42 PM PDT 24
Finished Jun 25 04:55:03 PM PDT 24
Peak memory 212324 kb
Host smart-b1f8a0b1-2a39-4bc3-ba10-09fe04eb663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336581670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.336581670
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2837365303
Short name T232
Test name
Test status
Simulation time 9829529176 ps
CPU time 13.44 seconds
Started Jun 25 04:54:45 PM PDT 24
Finished Jun 25 04:54:59 PM PDT 24
Peak memory 211348 kb
Host smart-18593ab0-02d3-44ea-8037-390beff924a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837365303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2837365303
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.819718730
Short name T203
Test name
Test status
Simulation time 992219317 ps
CPU time 15.65 seconds
Started Jun 25 04:54:33 PM PDT 24
Finished Jun 25 04:54:50 PM PDT 24
Peak memory 213528 kb
Host smart-0486a71d-0a4c-4916-a6b6-bd581504c2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819718730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.819718730
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.898141794
Short name T5
Test name
Test status
Simulation time 24232138633 ps
CPU time 51.36 seconds
Started Jun 25 04:54:35 PM PDT 24
Finished Jun 25 04:55:27 PM PDT 24
Peak memory 214356 kb
Host smart-f9849a46-795b-449b-bf83-36990b7e7a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898141794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.898141794
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3271627787
Short name T161
Test name
Test status
Simulation time 13854260953 ps
CPU time 13.97 seconds
Started Jun 25 04:54:42 PM PDT 24
Finished Jun 25 04:54:57 PM PDT 24
Peak memory 211224 kb
Host smart-5643bca0-4461-457a-b4e3-9ff92ae849e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271627787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3271627787
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.806110690
Short name T43
Test name
Test status
Simulation time 104418657480 ps
CPU time 260.63 seconds
Started Jun 25 04:54:46 PM PDT 24
Finished Jun 25 04:59:07 PM PDT 24
Peak memory 233860 kb
Host smart-464f1ccb-b928-40ae-8d33-100a7e09a085
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806110690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.806110690
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2223643086
Short name T362
Test name
Test status
Simulation time 3767888304 ps
CPU time 20.83 seconds
Started Jun 25 04:54:43 PM PDT 24
Finished Jun 25 04:55:05 PM PDT 24
Peak memory 212168 kb
Host smart-275e891e-0a0e-43ae-9035-f507ea47ad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223643086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2223643086
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1164324520
Short name T359
Test name
Test status
Simulation time 3464892192 ps
CPU time 14.9 seconds
Started Jun 25 04:54:43 PM PDT 24
Finished Jun 25 04:54:59 PM PDT 24
Peak memory 211380 kb
Host smart-9c5d0da2-c800-48e4-81ae-027f696081d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164324520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1164324520
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3246109579
Short name T365
Test name
Test status
Simulation time 207527741 ps
CPU time 10 seconds
Started Jun 25 04:54:47 PM PDT 24
Finished Jun 25 04:54:58 PM PDT 24
Peak memory 212984 kb
Host smart-0bcff5d7-f474-4f4c-9901-b711c66b0782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246109579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3246109579
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2403738378
Short name T315
Test name
Test status
Simulation time 303553288 ps
CPU time 16.3 seconds
Started Jun 25 04:54:41 PM PDT 24
Finished Jun 25 04:54:58 PM PDT 24
Peak memory 214900 kb
Host smart-a9bcc4ab-3f77-4bf6-9160-a0cca7129d4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403738378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2403738378
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1481921949
Short name T281
Test name
Test status
Simulation time 658158602 ps
CPU time 6.82 seconds
Started Jun 25 04:54:42 PM PDT 24
Finished Jun 25 04:54:51 PM PDT 24
Peak memory 211088 kb
Host smart-f1423d06-d0fc-460b-a460-842769ec17ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481921949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1481921949
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3717079945
Short name T217
Test name
Test status
Simulation time 37482786091 ps
CPU time 328.75 seconds
Started Jun 25 04:54:46 PM PDT 24
Finished Jun 25 05:00:16 PM PDT 24
Peak memory 228596 kb
Host smart-367f5705-fac9-4407-b1d3-04292d5c86f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717079945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3717079945
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1581129132
Short name T299
Test name
Test status
Simulation time 2367063037 ps
CPU time 9.44 seconds
Started Jun 25 04:54:42 PM PDT 24
Finished Jun 25 04:54:53 PM PDT 24
Peak memory 212000 kb
Host smart-34589b91-13ce-4b39-bf02-11597d22eef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581129132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1581129132
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3940365965
Short name T166
Test name
Test status
Simulation time 144638752 ps
CPU time 6.46 seconds
Started Jun 25 04:54:44 PM PDT 24
Finished Jun 25 04:54:51 PM PDT 24
Peak memory 211236 kb
Host smart-0451b8cc-433d-4b35-ae6b-d1726815f41f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940365965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3940365965
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3437900997
Short name T346
Test name
Test status
Simulation time 1829015153 ps
CPU time 24.77 seconds
Started Jun 25 04:54:44 PM PDT 24
Finished Jun 25 04:55:10 PM PDT 24
Peak memory 212224 kb
Host smart-df5a7dac-ed11-499f-962c-a774217e7d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437900997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3437900997
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4073703716
Short name T231
Test name
Test status
Simulation time 5848531133 ps
CPU time 55.3 seconds
Started Jun 25 04:54:46 PM PDT 24
Finished Jun 25 04:55:42 PM PDT 24
Peak memory 216760 kb
Host smart-3144f574-118c-4216-a6b9-90bfe91f78c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073703716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4073703716
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1382024634
Short name T56
Test name
Test status
Simulation time 4849104893 ps
CPU time 12.53 seconds
Started Jun 25 04:54:45 PM PDT 24
Finished Jun 25 04:54:58 PM PDT 24
Peak memory 211244 kb
Host smart-6a882714-bfed-429b-a125-3c5737dabe13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382024634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1382024634
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2012257709
Short name T89
Test name
Test status
Simulation time 4606300071 ps
CPU time 78.6 seconds
Started Jun 25 04:54:44 PM PDT 24
Finished Jun 25 04:56:04 PM PDT 24
Peak memory 236536 kb
Host smart-d55e39ad-0acb-4adf-872c-b41b7f875950
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012257709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2012257709
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.664988124
Short name T243
Test name
Test status
Simulation time 13306122392 ps
CPU time 21.31 seconds
Started Jun 25 04:54:43 PM PDT 24
Finished Jun 25 04:55:05 PM PDT 24
Peak memory 212180 kb
Host smart-f633ea19-9b2a-4377-9b90-42cdd608b9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664988124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.664988124
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3975545177
Short name T81
Test name
Test status
Simulation time 3236785706 ps
CPU time 8.27 seconds
Started Jun 25 04:54:47 PM PDT 24
Finished Jun 25 04:54:56 PM PDT 24
Peak memory 211304 kb
Host smart-46fd6f04-ac20-4169-b219-52999a5722da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975545177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3975545177
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4279087550
Short name T157
Test name
Test status
Simulation time 9349790698 ps
CPU time 25.1 seconds
Started Jun 25 04:54:46 PM PDT 24
Finished Jun 25 04:55:12 PM PDT 24
Peak memory 213948 kb
Host smart-b4130f0e-f9f7-4068-8287-5a4cb2dd6837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279087550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4279087550
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.456233866
Short name T2
Test name
Test status
Simulation time 6256390987 ps
CPU time 25.99 seconds
Started Jun 25 04:54:46 PM PDT 24
Finished Jun 25 04:55:13 PM PDT 24
Peak memory 217192 kb
Host smart-2d5bb286-395b-459f-98e8-f1a0f8d61555
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456233866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.456233866
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.139113343
Short name T143
Test name
Test status
Simulation time 2419902856 ps
CPU time 16.27 seconds
Started Jun 25 04:54:46 PM PDT 24
Finished Jun 25 04:55:03 PM PDT 24
Peak memory 211296 kb
Host smart-f24c2afe-8a12-4f87-8d8a-6b8541c2f6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139113343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.139113343
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1519522462
Short name T307
Test name
Test status
Simulation time 26253432408 ps
CPU time 253.58 seconds
Started Jun 25 04:54:41 PM PDT 24
Finished Jun 25 04:58:56 PM PDT 24
Peak memory 213508 kb
Host smart-1cc76c7f-a56a-4d0c-b846-211b18383b5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519522462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1519522462
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2429086264
Short name T39
Test name
Test status
Simulation time 3333050048 ps
CPU time 20.82 seconds
Started Jun 25 04:54:42 PM PDT 24
Finished Jun 25 04:55:04 PM PDT 24
Peak memory 212020 kb
Host smart-a873dccd-57ef-4dac-9dbe-174fa27f56f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429086264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2429086264
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2547592556
Short name T335
Test name
Test status
Simulation time 7398547663 ps
CPU time 16.84 seconds
Started Jun 25 04:54:46 PM PDT 24
Finished Jun 25 04:55:04 PM PDT 24
Peak memory 211304 kb
Host smart-4e45bce4-8ace-4a22-9ca5-fbb15dfc4675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547592556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2547592556
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.830362542
Short name T325
Test name
Test status
Simulation time 189852107 ps
CPU time 10.46 seconds
Started Jun 25 04:54:42 PM PDT 24
Finished Jun 25 04:54:54 PM PDT 24
Peak memory 213328 kb
Host smart-f20467fc-d166-47b6-b409-ba02b2a29ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830362542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.830362542
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4075123632
Short name T121
Test name
Test status
Simulation time 9008889259 ps
CPU time 37.6 seconds
Started Jun 25 04:54:43 PM PDT 24
Finished Jun 25 04:55:22 PM PDT 24
Peak memory 214276 kb
Host smart-fbd5e850-86cd-45ca-9674-3c0cc6f285f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075123632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4075123632
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.353488112
Short name T212
Test name
Test status
Simulation time 378595196 ps
CPU time 4.33 seconds
Started Jun 25 04:54:56 PM PDT 24
Finished Jun 25 04:55:01 PM PDT 24
Peak memory 211192 kb
Host smart-0c3ced83-fba3-4505-a35a-c705966a1d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353488112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.353488112
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1096025158
Short name T255
Test name
Test status
Simulation time 12405393711 ps
CPU time 193.46 seconds
Started Jun 25 04:54:56 PM PDT 24
Finished Jun 25 04:58:10 PM PDT 24
Peak memory 234908 kb
Host smart-892c0ea0-b935-4af3-93cb-c6ccc4f0b93a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096025158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1096025158
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2962411264
Short name T28
Test name
Test status
Simulation time 665406542 ps
CPU time 9.57 seconds
Started Jun 25 04:54:55 PM PDT 24
Finished Jun 25 04:55:06 PM PDT 24
Peak memory 212008 kb
Host smart-ec01b54b-f545-4a9b-9da9-fa35d9ca3049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962411264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2962411264
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2500917513
Short name T354
Test name
Test status
Simulation time 659985283 ps
CPU time 5.31 seconds
Started Jun 25 04:54:54 PM PDT 24
Finished Jun 25 04:55:00 PM PDT 24
Peak memory 211296 kb
Host smart-46ae6feb-8cdf-440e-88aa-dcb34dbf2284
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500917513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2500917513
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.746617946
Short name T183
Test name
Test status
Simulation time 2257422125 ps
CPU time 22.93 seconds
Started Jun 25 04:54:55 PM PDT 24
Finished Jun 25 04:55:19 PM PDT 24
Peak memory 213524 kb
Host smart-76eb9f19-8a92-462f-a9f9-8ec158be1e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746617946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.746617946
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3646702171
Short name T240
Test name
Test status
Simulation time 568663132 ps
CPU time 22.99 seconds
Started Jun 25 04:54:53 PM PDT 24
Finished Jun 25 04:55:18 PM PDT 24
Peak memory 216100 kb
Host smart-134d06eb-2d14-46ec-8844-0682d098f2b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646702171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3646702171
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3061180882
Short name T144
Test name
Test status
Simulation time 2387545620 ps
CPU time 10.98 seconds
Started Jun 25 04:54:54 PM PDT 24
Finished Jun 25 04:55:06 PM PDT 24
Peak memory 211252 kb
Host smart-0c20f4d6-de6c-48c7-98e7-cb746f4257f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061180882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3061180882
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3463650156
Short name T34
Test name
Test status
Simulation time 82220770050 ps
CPU time 231.01 seconds
Started Jun 25 04:54:55 PM PDT 24
Finished Jun 25 04:58:47 PM PDT 24
Peak memory 228348 kb
Host smart-cb79d4a9-5716-4f94-b551-ba4ab28e991f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463650156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3463650156
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.485264608
Short name T233
Test name
Test status
Simulation time 5147241504 ps
CPU time 23.81 seconds
Started Jun 25 04:54:53 PM PDT 24
Finished Jun 25 04:55:18 PM PDT 24
Peak memory 211580 kb
Host smart-b5a7deb1-4cbd-489c-b5a7-5b37999c892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485264608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.485264608
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.205262625
Short name T160
Test name
Test status
Simulation time 12959650256 ps
CPU time 17.94 seconds
Started Jun 25 04:54:56 PM PDT 24
Finished Jun 25 04:55:15 PM PDT 24
Peak memory 211300 kb
Host smart-568e9acb-2a57-4521-ae82-d4196040ebce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205262625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.205262625
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3857790797
Short name T210
Test name
Test status
Simulation time 42071298540 ps
CPU time 38.49 seconds
Started Jun 25 04:54:52 PM PDT 24
Finished Jun 25 04:55:32 PM PDT 24
Peak memory 214024 kb
Host smart-02480091-34a7-44de-b70b-0eea26b8f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857790797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3857790797
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1517069487
Short name T246
Test name
Test status
Simulation time 1936828569 ps
CPU time 28.55 seconds
Started Jun 25 04:54:52 PM PDT 24
Finished Jun 25 04:55:22 PM PDT 24
Peak memory 216020 kb
Host smart-d68456f2-e12f-4708-aa6c-7c59cd2b7796
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517069487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1517069487
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1170024782
Short name T46
Test name
Test status
Simulation time 152933864221 ps
CPU time 929.56 seconds
Started Jun 25 04:54:54 PM PDT 24
Finished Jun 25 05:10:25 PM PDT 24
Peak memory 235760 kb
Host smart-2c1eabb2-1f6a-40e8-87c4-1262da15ee14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170024782 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1170024782
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1255233914
Short name T278
Test name
Test status
Simulation time 1178854866 ps
CPU time 10.84 seconds
Started Jun 25 04:54:53 PM PDT 24
Finished Jun 25 04:55:05 PM PDT 24
Peak memory 211192 kb
Host smart-9037902d-f0be-42f2-a1ba-1a330cc7623a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255233914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1255233914
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4277964058
Short name T15
Test name
Test status
Simulation time 29682506775 ps
CPU time 270.24 seconds
Started Jun 25 04:54:54 PM PDT 24
Finished Jun 25 04:59:26 PM PDT 24
Peak memory 240204 kb
Host smart-85c119c6-ca96-47cc-a833-0e8666abdffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277964058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4277964058
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3645391201
Short name T287
Test name
Test status
Simulation time 6822948793 ps
CPU time 27.55 seconds
Started Jun 25 04:54:53 PM PDT 24
Finished Jun 25 04:55:22 PM PDT 24
Peak memory 211384 kb
Host smart-e892cbce-dd5f-40cb-a75f-ea6dc0aa197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645391201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3645391201
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1402466651
Short name T304
Test name
Test status
Simulation time 1996176850 ps
CPU time 15.92 seconds
Started Jun 25 04:54:55 PM PDT 24
Finished Jun 25 04:55:12 PM PDT 24
Peak memory 211232 kb
Host smart-c84ab4e5-3632-4fa3-9f74-b2849bec46e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402466651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1402466651
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2510789669
Short name T336
Test name
Test status
Simulation time 1946763867 ps
CPU time 21.94 seconds
Started Jun 25 04:54:54 PM PDT 24
Finished Jun 25 04:55:17 PM PDT 24
Peak memory 213260 kb
Host smart-d4704d97-d5bc-4e82-b0f4-5d81c3006af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510789669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2510789669
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1643891227
Short name T352
Test name
Test status
Simulation time 2686772141 ps
CPU time 13.19 seconds
Started Jun 25 04:54:52 PM PDT 24
Finished Jun 25 04:55:07 PM PDT 24
Peak memory 211180 kb
Host smart-d067b4ee-dc1d-45f0-a15d-81f815aca5ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643891227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1643891227
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1974160280
Short name T332
Test name
Test status
Simulation time 2037306663 ps
CPU time 10.81 seconds
Started Jun 25 04:55:05 PM PDT 24
Finished Jun 25 04:55:17 PM PDT 24
Peak memory 211264 kb
Host smart-1554da04-936f-4418-a97d-ebf1aa91b738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974160280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1974160280
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1860779204
Short name T198
Test name
Test status
Simulation time 20587547224 ps
CPU time 187.11 seconds
Started Jun 25 04:54:55 PM PDT 24
Finished Jun 25 04:58:03 PM PDT 24
Peak memory 237820 kb
Host smart-f2beb7e1-89ee-4fae-94c6-d3e4ad8f2fb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860779204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1860779204
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1547643149
Short name T330
Test name
Test status
Simulation time 6898734278 ps
CPU time 29.57 seconds
Started Jun 25 04:54:54 PM PDT 24
Finished Jun 25 04:55:24 PM PDT 24
Peak memory 212488 kb
Host smart-2b29c734-6ffc-4f3f-84b5-7d2358784df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547643149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1547643149
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1686781110
Short name T341
Test name
Test status
Simulation time 8525937987 ps
CPU time 16.97 seconds
Started Jun 25 04:54:57 PM PDT 24
Finished Jun 25 04:55:15 PM PDT 24
Peak memory 211376 kb
Host smart-97a3a1d1-298c-41f9-ae51-05597be7b53d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686781110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1686781110
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1901247601
Short name T6
Test name
Test status
Simulation time 272765783 ps
CPU time 12.37 seconds
Started Jun 25 04:54:52 PM PDT 24
Finished Jun 25 04:55:06 PM PDT 24
Peak memory 213036 kb
Host smart-d6317425-6c35-441e-8592-e4763697c39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901247601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1901247601
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2737128465
Short name T170
Test name
Test status
Simulation time 3454781840 ps
CPU time 31.03 seconds
Started Jun 25 04:54:54 PM PDT 24
Finished Jun 25 04:55:26 PM PDT 24
Peak memory 214000 kb
Host smart-9c1267a8-5d8b-4a17-ba83-b2330b775a8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737128465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2737128465
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2687351876
Short name T361
Test name
Test status
Simulation time 1544009400 ps
CPU time 14.33 seconds
Started Jun 25 04:55:04 PM PDT 24
Finished Jun 25 04:55:21 PM PDT 24
Peak memory 211152 kb
Host smart-004e9153-de36-4555-bacc-14e880763d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687351876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2687351876
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.46282304
Short name T205
Test name
Test status
Simulation time 43021920543 ps
CPU time 132.38 seconds
Started Jun 25 04:55:05 PM PDT 24
Finished Jun 25 04:57:19 PM PDT 24
Peak memory 212548 kb
Host smart-90fd797e-e877-47a7-9488-00d4b63dee94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46282304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_co
rrupt_sig_fatal_chk.46282304
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2204749548
Short name T193
Test name
Test status
Simulation time 639243991 ps
CPU time 9.88 seconds
Started Jun 25 04:55:06 PM PDT 24
Finished Jun 25 04:55:18 PM PDT 24
Peak memory 211908 kb
Host smart-40ed1569-896c-4305-941a-5e0e1820b38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204749548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2204749548
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.141185912
Short name T223
Test name
Test status
Simulation time 394184652 ps
CPU time 5.74 seconds
Started Jun 25 04:55:07 PM PDT 24
Finished Jun 25 04:55:14 PM PDT 24
Peak memory 211316 kb
Host smart-97c36af9-ad98-4f6e-ac95-a8d48a6c1e29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141185912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.141185912
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.737300677
Short name T140
Test name
Test status
Simulation time 1913369506 ps
CPU time 23.71 seconds
Started Jun 25 04:55:04 PM PDT 24
Finished Jun 25 04:55:29 PM PDT 24
Peak memory 213872 kb
Host smart-20eaec98-a235-4f9b-81b8-67e894af2940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737300677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.737300677
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1318746663
Short name T340
Test name
Test status
Simulation time 643047790 ps
CPU time 11.31 seconds
Started Jun 25 04:55:04 PM PDT 24
Finished Jun 25 04:55:18 PM PDT 24
Peak memory 212212 kb
Host smart-10eb21aa-35df-4422-b992-029779631e66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318746663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1318746663
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3651717398
Short name T127
Test name
Test status
Simulation time 88893242 ps
CPU time 4.28 seconds
Started Jun 25 04:53:25 PM PDT 24
Finished Jun 25 04:53:31 PM PDT 24
Peak memory 211164 kb
Host smart-678a2ade-0243-41dc-86c1-ff23b7eae3a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651717398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3651717398
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3183860805
Short name T343
Test name
Test status
Simulation time 101532203458 ps
CPU time 297.31 seconds
Started Jun 25 04:53:27 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 224720 kb
Host smart-59a2598d-5b6b-45e8-8dad-710f810a73d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183860805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3183860805
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1394091524
Short name T334
Test name
Test status
Simulation time 179444337 ps
CPU time 9.67 seconds
Started Jun 25 04:53:26 PM PDT 24
Finished Jun 25 04:53:37 PM PDT 24
Peak memory 211804 kb
Host smart-b9f95c81-aee2-4491-bf8f-1e75a6d45c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394091524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1394091524
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.392484854
Short name T206
Test name
Test status
Simulation time 419645376 ps
CPU time 5.58 seconds
Started Jun 25 04:53:28 PM PDT 24
Finished Jun 25 04:53:34 PM PDT 24
Peak memory 211292 kb
Host smart-e0851b6f-f4ed-440f-95ed-aad8ab5a4250
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=392484854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.392484854
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2301450336
Short name T317
Test name
Test status
Simulation time 1481384865 ps
CPU time 19.46 seconds
Started Jun 25 04:53:25 PM PDT 24
Finished Jun 25 04:53:46 PM PDT 24
Peak memory 213920 kb
Host smart-35903b93-0916-439b-b0e5-c8151b947d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301450336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2301450336
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1722774067
Short name T129
Test name
Test status
Simulation time 194031895 ps
CPU time 12.14 seconds
Started Jun 25 04:53:24 PM PDT 24
Finished Jun 25 04:53:38 PM PDT 24
Peak memory 214836 kb
Host smart-b427a830-af14-4123-b952-7caeb206e1e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722774067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1722774067
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4057578879
Short name T318
Test name
Test status
Simulation time 1804786391 ps
CPU time 10.1 seconds
Started Jun 25 04:53:35 PM PDT 24
Finished Jun 25 04:53:46 PM PDT 24
Peak memory 211184 kb
Host smart-2c6e0455-6cdf-4112-8453-b6c27ba36c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057578879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4057578879
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.183274255
Short name T178
Test name
Test status
Simulation time 166102969556 ps
CPU time 390.24 seconds
Started Jun 25 04:53:41 PM PDT 24
Finished Jun 25 05:00:11 PM PDT 24
Peak memory 236924 kb
Host smart-a96f113b-d952-488a-8ad9-6d9c0a047c96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183274255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.183274255
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1687639389
Short name T189
Test name
Test status
Simulation time 347794225 ps
CPU time 9.74 seconds
Started Jun 25 04:53:35 PM PDT 24
Finished Jun 25 04:53:46 PM PDT 24
Peak memory 211892 kb
Host smart-9ca7eb57-6d32-4f7e-8c8a-9cb76d5debb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687639389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1687639389
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.374153941
Short name T348
Test name
Test status
Simulation time 7504696551 ps
CPU time 15.88 seconds
Started Jun 25 04:53:36 PM PDT 24
Finished Jun 25 04:53:53 PM PDT 24
Peak memory 211296 kb
Host smart-6948e80c-2935-420b-874a-8d8d0551b9de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374153941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.374153941
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4125836909
Short name T139
Test name
Test status
Simulation time 757984815 ps
CPU time 10.56 seconds
Started Jun 25 04:53:25 PM PDT 24
Finished Jun 25 04:53:36 PM PDT 24
Peak memory 213696 kb
Host smart-a9f5768e-78a3-4a63-bd7d-3c94c336f4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125836909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4125836909
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1891102172
Short name T29
Test name
Test status
Simulation time 8584954969 ps
CPU time 56.97 seconds
Started Jun 25 04:53:28 PM PDT 24
Finished Jun 25 04:54:26 PM PDT 24
Peak memory 216636 kb
Host smart-a5f97399-452c-480a-ab2a-67c4e8048d4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891102172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1891102172
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3188021312
Short name T326
Test name
Test status
Simulation time 80914088886 ps
CPU time 707.93 seconds
Started Jun 25 04:53:36 PM PDT 24
Finished Jun 25 05:05:25 PM PDT 24
Peak memory 235756 kb
Host smart-6a2446d1-565a-4f54-bcfc-bc85d07b1e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188021312 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3188021312
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1092218014
Short name T253
Test name
Test status
Simulation time 1023896930 ps
CPU time 10.86 seconds
Started Jun 25 04:53:34 PM PDT 24
Finished Jun 25 04:53:46 PM PDT 24
Peak memory 211200 kb
Host smart-446a6228-9ab1-460e-99fb-08b0a68415fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092218014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1092218014
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3363728794
Short name T268
Test name
Test status
Simulation time 5153394161 ps
CPU time 188.93 seconds
Started Jun 25 04:53:34 PM PDT 24
Finished Jun 25 04:56:44 PM PDT 24
Peak memory 237760 kb
Host smart-7d32a59e-9c45-4ccc-be5c-179d99aa46b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363728794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3363728794
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.353592502
Short name T269
Test name
Test status
Simulation time 3926840871 ps
CPU time 31.7 seconds
Started Jun 25 04:53:34 PM PDT 24
Finished Jun 25 04:54:07 PM PDT 24
Peak memory 211820 kb
Host smart-59573efa-4322-4cf6-bfad-92c45450868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353592502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.353592502
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2680681977
Short name T321
Test name
Test status
Simulation time 528942367 ps
CPU time 8.78 seconds
Started Jun 25 04:53:34 PM PDT 24
Finished Jun 25 04:53:44 PM PDT 24
Peak memory 211236 kb
Host smart-ce895848-9a39-432f-abb4-35b1b24a420b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2680681977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2680681977
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1072039874
Short name T180
Test name
Test status
Simulation time 5235747249 ps
CPU time 29.47 seconds
Started Jun 25 04:53:35 PM PDT 24
Finished Jun 25 04:54:06 PM PDT 24
Peak memory 213732 kb
Host smart-dffb593a-b5a2-48be-8453-9538cf324bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072039874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1072039874
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2129705210
Short name T300
Test name
Test status
Simulation time 388328989 ps
CPU time 6.62 seconds
Started Jun 25 04:53:36 PM PDT 24
Finished Jun 25 04:53:44 PM PDT 24
Peak memory 211256 kb
Host smart-3a6ef6ad-c86d-4d20-8eef-4369b850984a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129705210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2129705210
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2198374587
Short name T153
Test name
Test status
Simulation time 5053231507 ps
CPU time 12.13 seconds
Started Jun 25 04:53:34 PM PDT 24
Finished Jun 25 04:53:47 PM PDT 24
Peak memory 211256 kb
Host smart-7c2131c6-7cdd-467e-abff-fd275269f38b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198374587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2198374587
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1070725915
Short name T167
Test name
Test status
Simulation time 3491885412 ps
CPU time 121.16 seconds
Started Jun 25 04:53:40 PM PDT 24
Finished Jun 25 04:55:42 PM PDT 24
Peak memory 240832 kb
Host smart-df8a70f3-b5ae-4674-aac8-c71510bafc39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070725915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1070725915
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1412962389
Short name T188
Test name
Test status
Simulation time 18085012570 ps
CPU time 25.13 seconds
Started Jun 25 04:53:36 PM PDT 24
Finished Jun 25 04:54:02 PM PDT 24
Peak memory 212240 kb
Host smart-4e6c9377-de72-4b22-81d0-9b5af070240e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412962389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1412962389
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2414578856
Short name T133
Test name
Test status
Simulation time 10328532196 ps
CPU time 11.95 seconds
Started Jun 25 04:53:34 PM PDT 24
Finished Jun 25 04:53:47 PM PDT 24
Peak memory 211300 kb
Host smart-fa24c1db-f05e-4a2a-b9b1-07364e4a9ffc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414578856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2414578856
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2238645170
Short name T69
Test name
Test status
Simulation time 7248075477 ps
CPU time 35.45 seconds
Started Jun 25 04:53:37 PM PDT 24
Finished Jun 25 04:54:13 PM PDT 24
Peak memory 213324 kb
Host smart-9b2ee321-ec1f-40ea-a840-d3efc7e82c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238645170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2238645170
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1476929975
Short name T199
Test name
Test status
Simulation time 3830176758 ps
CPU time 13.49 seconds
Started Jun 25 04:53:35 PM PDT 24
Finished Jun 25 04:53:50 PM PDT 24
Peak memory 211364 kb
Host smart-307afef0-eca4-4698-b0cd-82c154cb2d23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476929975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1476929975
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3854183219
Short name T267
Test name
Test status
Simulation time 65318260587 ps
CPU time 1251.3 seconds
Started Jun 25 04:53:35 PM PDT 24
Finished Jun 25 05:14:27 PM PDT 24
Peak memory 235760 kb
Host smart-168852c2-382e-4ed6-bec0-bc32f8666662
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854183219 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3854183219
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.734175781
Short name T275
Test name
Test status
Simulation time 1829295874 ps
CPU time 13.33 seconds
Started Jun 25 04:53:43 PM PDT 24
Finished Jun 25 04:53:58 PM PDT 24
Peak memory 211164 kb
Host smart-6421b790-f234-4af9-bd34-a6ed1309a35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734175781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.734175781
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2214817047
Short name T235
Test name
Test status
Simulation time 5260318395 ps
CPU time 86.37 seconds
Started Jun 25 04:53:37 PM PDT 24
Finished Jun 25 04:55:04 PM PDT 24
Peak memory 237964 kb
Host smart-0f0e209b-68da-4899-acbd-13ca80caa404
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214817047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2214817047
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3800623242
Short name T38
Test name
Test status
Simulation time 175602534 ps
CPU time 9.57 seconds
Started Jun 25 04:53:36 PM PDT 24
Finished Jun 25 04:53:47 PM PDT 24
Peak memory 211808 kb
Host smart-a434d973-bbac-4c5f-a006-41d0652baa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800623242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3800623242
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2926489200
Short name T179
Test name
Test status
Simulation time 4496126219 ps
CPU time 11.75 seconds
Started Jun 25 04:53:35 PM PDT 24
Finished Jun 25 04:53:48 PM PDT 24
Peak memory 211292 kb
Host smart-d1cc0d11-94af-4f47-a7fc-c7b7f6cabf49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926489200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2926489200
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2818210263
Short name T138
Test name
Test status
Simulation time 1767793543 ps
CPU time 13.51 seconds
Started Jun 25 04:53:34 PM PDT 24
Finished Jun 25 04:53:48 PM PDT 24
Peak memory 213676 kb
Host smart-4687570e-fdc1-42ca-80a0-9157af707aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818210263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2818210263
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.223662105
Short name T259
Test name
Test status
Simulation time 4799367817 ps
CPU time 26.14 seconds
Started Jun 25 04:53:38 PM PDT 24
Finished Jun 25 04:54:05 PM PDT 24
Peak memory 217856 kb
Host smart-51d7cc5d-7eea-4697-be4d-363368ee4ca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223662105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.223662105
Directory /workspace/9.rom_ctrl_stress_all/latest
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