Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 96.89 92.56 97.67 100.00 98.97 97.45 98.37


Total test records in report: 463
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T303 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3727787908 Jun 26 05:46:23 PM PDT 24 Jun 26 05:49:54 PM PDT 24 87740359700 ps
T304 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.991012210 Jun 26 05:45:32 PM PDT 24 Jun 26 05:45:50 PM PDT 24 2745027811 ps
T305 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.737385367 Jun 26 05:45:13 PM PDT 24 Jun 26 05:47:41 PM PDT 24 10002436225 ps
T306 /workspace/coverage/default/6.rom_ctrl_smoke.1756766896 Jun 26 05:45:19 PM PDT 24 Jun 26 05:45:39 PM PDT 24 4711076215 ps
T307 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3683629420 Jun 26 05:45:48 PM PDT 24 Jun 26 05:46:04 PM PDT 24 3165179273 ps
T308 /workspace/coverage/default/26.rom_ctrl_smoke.2741285123 Jun 26 05:46:04 PM PDT 24 Jun 26 05:46:37 PM PDT 24 3511485147 ps
T309 /workspace/coverage/default/32.rom_ctrl_alert_test.2887342122 Jun 26 05:46:11 PM PDT 24 Jun 26 05:46:24 PM PDT 24 1587876785 ps
T310 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.658834949 Jun 26 05:46:22 PM PDT 24 Jun 26 05:46:46 PM PDT 24 2279711098 ps
T311 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2941875684 Jun 26 05:45:46 PM PDT 24 Jun 26 05:46:21 PM PDT 24 8718054237 ps
T312 /workspace/coverage/default/48.rom_ctrl_alert_test.1822873928 Jun 26 05:46:46 PM PDT 24 Jun 26 05:47:01 PM PDT 24 2240825868 ps
T313 /workspace/coverage/default/47.rom_ctrl_smoke.1444388995 Jun 26 05:46:34 PM PDT 24 Jun 26 05:47:02 PM PDT 24 2988679503 ps
T314 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1418367463 Jun 26 05:45:18 PM PDT 24 Jun 26 05:46:58 PM PDT 24 1470275259 ps
T23 /workspace/coverage/default/1.rom_ctrl_sec_cm.302549435 Jun 26 05:45:13 PM PDT 24 Jun 26 05:46:18 PM PDT 24 1724196766 ps
T315 /workspace/coverage/default/37.rom_ctrl_alert_test.1338668697 Jun 26 05:46:24 PM PDT 24 Jun 26 05:46:37 PM PDT 24 5071184832 ps
T316 /workspace/coverage/default/20.rom_ctrl_stress_all.945882891 Jun 26 05:45:46 PM PDT 24 Jun 26 05:46:07 PM PDT 24 5267250576 ps
T24 /workspace/coverage/default/2.rom_ctrl_sec_cm.2551779267 Jun 26 05:45:09 PM PDT 24 Jun 26 05:46:56 PM PDT 24 1875875600 ps
T317 /workspace/coverage/default/14.rom_ctrl_alert_test.3610197010 Jun 26 05:45:32 PM PDT 24 Jun 26 05:45:41 PM PDT 24 458407889 ps
T318 /workspace/coverage/default/0.rom_ctrl_alert_test.1186927887 Jun 26 05:45:12 PM PDT 24 Jun 26 05:45:20 PM PDT 24 347163178 ps
T319 /workspace/coverage/default/18.rom_ctrl_stress_all.1692845046 Jun 26 05:45:45 PM PDT 24 Jun 26 05:46:07 PM PDT 24 394021193 ps
T320 /workspace/coverage/default/42.rom_ctrl_stress_all.2624676445 Jun 26 05:46:32 PM PDT 24 Jun 26 05:47:06 PM PDT 24 3189471509 ps
T321 /workspace/coverage/default/46.rom_ctrl_smoke.2930830309 Jun 26 05:46:38 PM PDT 24 Jun 26 05:47:10 PM PDT 24 7516410697 ps
T322 /workspace/coverage/default/7.rom_ctrl_stress_all.141448293 Jun 26 05:45:23 PM PDT 24 Jun 26 05:46:29 PM PDT 24 4731009099 ps
T323 /workspace/coverage/default/15.rom_ctrl_smoke.1430802945 Jun 26 05:45:42 PM PDT 24 Jun 26 05:46:11 PM PDT 24 5145245751 ps
T324 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1993506582 Jun 26 05:46:23 PM PDT 24 Jun 26 05:46:30 PM PDT 24 380838484 ps
T325 /workspace/coverage/default/4.rom_ctrl_smoke.581203403 Jun 26 05:45:21 PM PDT 24 Jun 26 05:45:58 PM PDT 24 26729883835 ps
T326 /workspace/coverage/default/38.rom_ctrl_stress_all.910122138 Jun 26 05:46:23 PM PDT 24 Jun 26 05:46:51 PM PDT 24 895759700 ps
T327 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.476048823 Jun 26 05:46:06 PM PDT 24 Jun 26 05:46:26 PM PDT 24 12270631977 ps
T328 /workspace/coverage/default/35.rom_ctrl_stress_all.2283499686 Jun 26 05:46:15 PM PDT 24 Jun 26 05:46:23 PM PDT 24 124129728 ps
T329 /workspace/coverage/default/25.rom_ctrl_alert_test.348302754 Jun 26 05:46:04 PM PDT 24 Jun 26 05:46:22 PM PDT 24 6683992416 ps
T330 /workspace/coverage/default/13.rom_ctrl_smoke.3556139086 Jun 26 05:45:34 PM PDT 24 Jun 26 05:45:46 PM PDT 24 744286894 ps
T331 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2648393894 Jun 26 05:46:04 PM PDT 24 Jun 26 05:49:10 PM PDT 24 10979772338 ps
T332 /workspace/coverage/default/17.rom_ctrl_smoke.2771284461 Jun 26 05:45:40 PM PDT 24 Jun 26 05:46:23 PM PDT 24 14507888848 ps
T333 /workspace/coverage/default/16.rom_ctrl_smoke.2100256317 Jun 26 05:45:39 PM PDT 24 Jun 26 05:45:55 PM PDT 24 764499410 ps
T334 /workspace/coverage/default/35.rom_ctrl_alert_test.1779563681 Jun 26 05:46:16 PM PDT 24 Jun 26 05:46:23 PM PDT 24 593407129 ps
T335 /workspace/coverage/default/15.rom_ctrl_stress_all.2776769434 Jun 26 05:45:40 PM PDT 24 Jun 26 05:46:09 PM PDT 24 463370379 ps
T336 /workspace/coverage/default/46.rom_ctrl_alert_test.1305633550 Jun 26 05:46:37 PM PDT 24 Jun 26 05:46:55 PM PDT 24 7845544720 ps
T337 /workspace/coverage/default/39.rom_ctrl_smoke.1804639800 Jun 26 05:46:21 PM PDT 24 Jun 26 05:46:34 PM PDT 24 552431756 ps
T338 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2381655657 Jun 26 05:46:17 PM PDT 24 Jun 26 05:46:36 PM PDT 24 4305486827 ps
T339 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1652746955 Jun 26 05:46:01 PM PDT 24 Jun 26 05:49:40 PM PDT 24 26123995326 ps
T340 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3978484419 Jun 26 05:46:42 PM PDT 24 Jun 26 05:48:22 PM PDT 24 3133221023 ps
T35 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1151335790 Jun 26 05:46:45 PM PDT 24 Jun 26 05:54:07 PM PDT 24 39929286406 ps
T341 /workspace/coverage/default/10.rom_ctrl_smoke.2129743702 Jun 26 05:45:18 PM PDT 24 Jun 26 05:45:46 PM PDT 24 3088977048 ps
T342 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4138292879 Jun 26 05:45:19 PM PDT 24 Jun 26 05:45:32 PM PDT 24 4131156785 ps
T343 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.916942046 Jun 26 05:46:42 PM PDT 24 Jun 26 05:47:17 PM PDT 24 47321370803 ps
T344 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1957764388 Jun 26 05:45:26 PM PDT 24 Jun 26 05:45:54 PM PDT 24 4637136808 ps
T345 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4010387685 Jun 26 05:45:31 PM PDT 24 Jun 26 05:45:49 PM PDT 24 4300376971 ps
T112 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2518461987 Jun 26 05:46:05 PM PDT 24 Jun 26 05:46:17 PM PDT 24 2440131407 ps
T346 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.256833304 Jun 26 05:46:15 PM PDT 24 Jun 26 05:46:46 PM PDT 24 12117149857 ps
T347 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3281704934 Jun 26 05:46:11 PM PDT 24 Jun 26 05:48:21 PM PDT 24 13346754079 ps
T348 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1563356036 Jun 26 05:45:21 PM PDT 24 Jun 26 05:48:38 PM PDT 24 35262642861 ps
T349 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4167275536 Jun 26 05:46:00 PM PDT 24 Jun 26 06:40:18 PM PDT 24 62439175923 ps
T350 /workspace/coverage/default/19.rom_ctrl_alert_test.4033821467 Jun 26 05:45:43 PM PDT 24 Jun 26 05:45:56 PM PDT 24 2707680218 ps
T351 /workspace/coverage/default/46.rom_ctrl_stress_all.852477391 Jun 26 05:46:37 PM PDT 24 Jun 26 05:46:57 PM PDT 24 1843427008 ps
T352 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.92447868 Jun 26 05:45:13 PM PDT 24 Jun 26 05:45:26 PM PDT 24 2840803416 ps
T353 /workspace/coverage/default/17.rom_ctrl_stress_all.525564288 Jun 26 05:45:37 PM PDT 24 Jun 26 05:45:45 PM PDT 24 335238133 ps
T354 /workspace/coverage/default/33.rom_ctrl_alert_test.1909352807 Jun 26 05:46:08 PM PDT 24 Jun 26 05:46:16 PM PDT 24 89114555 ps
T355 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2935113160 Jun 26 05:46:09 PM PDT 24 Jun 26 05:46:42 PM PDT 24 3504192048 ps
T356 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3998765739 Jun 26 05:45:23 PM PDT 24 Jun 26 05:45:33 PM PDT 24 1030136601 ps
T357 /workspace/coverage/default/14.rom_ctrl_smoke.3462290820 Jun 26 05:45:31 PM PDT 24 Jun 26 05:46:06 PM PDT 24 4906210970 ps
T358 /workspace/coverage/default/45.rom_ctrl_alert_test.3179548510 Jun 26 05:46:38 PM PDT 24 Jun 26 05:46:57 PM PDT 24 15108416072 ps
T359 /workspace/coverage/default/21.rom_ctrl_alert_test.3658608347 Jun 26 05:45:55 PM PDT 24 Jun 26 05:46:13 PM PDT 24 3378112436 ps
T360 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4191147767 Jun 26 05:45:28 PM PDT 24 Jun 26 05:45:45 PM PDT 24 1718871222 ps
T361 /workspace/coverage/default/20.rom_ctrl_smoke.1578911333 Jun 26 05:45:47 PM PDT 24 Jun 26 05:46:19 PM PDT 24 4086389942 ps
T362 /workspace/coverage/default/31.rom_ctrl_smoke.1538634126 Jun 26 05:46:15 PM PDT 24 Jun 26 05:46:49 PM PDT 24 3181559847 ps
T363 /workspace/coverage/default/25.rom_ctrl_smoke.1880489321 Jun 26 05:46:02 PM PDT 24 Jun 26 05:46:28 PM PDT 24 2254414365 ps
T364 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2256957614 Jun 26 05:46:16 PM PDT 24 Jun 26 05:50:06 PM PDT 24 55089890747 ps
T365 /workspace/coverage/default/3.rom_ctrl_stress_all.3887720561 Jun 26 05:45:11 PM PDT 24 Jun 26 05:45:42 PM PDT 24 7048121419 ps
T366 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2137888996 Jun 26 05:46:12 PM PDT 24 Jun 26 05:46:32 PM PDT 24 4780346426 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.360779361 Jun 26 05:44:44 PM PDT 24 Jun 26 05:44:53 PM PDT 24 8217111316 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2826520836 Jun 26 05:44:46 PM PDT 24 Jun 26 05:45:06 PM PDT 24 3703613948 ps
T52 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.690206984 Jun 26 05:44:55 PM PDT 24 Jun 26 05:45:17 PM PDT 24 8564625130 ps
T369 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4128078549 Jun 26 05:45:00 PM PDT 24 Jun 26 05:45:21 PM PDT 24 2091020631 ps
T53 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.807688510 Jun 26 05:44:52 PM PDT 24 Jun 26 05:45:07 PM PDT 24 2785864372 ps
T54 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.185430530 Jun 26 05:45:10 PM PDT 24 Jun 26 05:45:27 PM PDT 24 1758815485 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1279038745 Jun 26 05:44:46 PM PDT 24 Jun 26 05:45:03 PM PDT 24 6791219360 ps
T371 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4149525124 Jun 26 05:44:58 PM PDT 24 Jun 26 05:45:14 PM PDT 24 5729178128 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.469046144 Jun 26 05:44:50 PM PDT 24 Jun 26 05:45:02 PM PDT 24 509644481 ps
T104 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4077599726 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:13 PM PDT 24 1955124829 ps
T372 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3711412725 Jun 26 05:45:03 PM PDT 24 Jun 26 05:45:11 PM PDT 24 502930446 ps
T105 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2211503761 Jun 26 05:45:08 PM PDT 24 Jun 26 05:45:17 PM PDT 24 3546290457 ps
T373 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3686134637 Jun 26 05:45:03 PM PDT 24 Jun 26 05:45:22 PM PDT 24 8936637323 ps
T65 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.261451458 Jun 26 05:45:10 PM PDT 24 Jun 26 05:45:16 PM PDT 24 346923454 ps
T374 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2112891951 Jun 26 05:45:08 PM PDT 24 Jun 26 05:45:27 PM PDT 24 1434347930 ps
T66 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.860246199 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:18 PM PDT 24 2008970128 ps
T67 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2345648686 Jun 26 05:45:10 PM PDT 24 Jun 26 05:45:45 PM PDT 24 2225643913 ps
T48 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3580677195 Jun 26 05:45:09 PM PDT 24 Jun 26 05:45:59 PM PDT 24 2159346470 ps
T49 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3530874660 Jun 26 05:44:59 PM PDT 24 Jun 26 05:45:42 PM PDT 24 2159123079 ps
T68 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3580381217 Jun 26 05:44:46 PM PDT 24 Jun 26 05:45:04 PM PDT 24 5891964890 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2161594047 Jun 26 05:44:46 PM PDT 24 Jun 26 05:44:58 PM PDT 24 3599331205 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3580944838 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:19 PM PDT 24 1491020940 ps
T69 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.588555826 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:33 PM PDT 24 3368700096 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2050058591 Jun 26 05:44:44 PM PDT 24 Jun 26 05:44:58 PM PDT 24 5209455395 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2148321508 Jun 26 05:45:12 PM PDT 24 Jun 26 05:45:30 PM PDT 24 6778236598 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4020688235 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:17 PM PDT 24 1467651004 ps
T379 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4038306478 Jun 26 05:45:08 PM PDT 24 Jun 26 05:45:23 PM PDT 24 9861195874 ps
T107 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3312687530 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:16 PM PDT 24 4778720446 ps
T380 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.627185702 Jun 26 05:45:13 PM PDT 24 Jun 26 05:46:25 PM PDT 24 11058371376 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.77260585 Jun 26 05:44:50 PM PDT 24 Jun 26 05:45:59 PM PDT 24 6214508941 ps
T108 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2349940118 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:17 PM PDT 24 1145258484 ps
T50 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1512738745 Jun 26 05:45:08 PM PDT 24 Jun 26 05:45:51 PM PDT 24 2257684375 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1450243938 Jun 26 05:44:51 PM PDT 24 Jun 26 05:45:00 PM PDT 24 472926824 ps
T383 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1892190331 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:21 PM PDT 24 1914359586 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2975606121 Jun 26 05:44:44 PM PDT 24 Jun 26 05:44:56 PM PDT 24 1195450932 ps
T117 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.800279870 Jun 26 05:45:03 PM PDT 24 Jun 26 05:46:20 PM PDT 24 1299532056 ps
T109 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.940031468 Jun 26 05:45:07 PM PDT 24 Jun 26 05:45:23 PM PDT 24 1932588599 ps
T110 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2842229913 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:17 PM PDT 24 1405977487 ps
T385 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.76938506 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:22 PM PDT 24 5420941103 ps
T111 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2534898676 Jun 26 05:45:03 PM PDT 24 Jun 26 05:45:14 PM PDT 24 1299254156 ps
T122 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2542929889 Jun 26 05:44:53 PM PDT 24 Jun 26 05:45:36 PM PDT 24 1118231883 ps
T118 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2566132859 Jun 26 05:45:12 PM PDT 24 Jun 26 05:46:35 PM PDT 24 5102021425 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.457330614 Jun 26 05:44:51 PM PDT 24 Jun 26 05:44:59 PM PDT 24 346800347 ps
T70 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1808082418 Jun 26 05:45:00 PM PDT 24 Jun 26 05:45:07 PM PDT 24 334218237 ps
T387 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2213354430 Jun 26 05:45:06 PM PDT 24 Jun 26 05:45:20 PM PDT 24 22516525147 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4227293982 Jun 26 05:44:46 PM PDT 24 Jun 26 05:45:06 PM PDT 24 1676056657 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.789022616 Jun 26 05:44:50 PM PDT 24 Jun 26 05:45:01 PM PDT 24 553314525 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1335774854 Jun 26 05:45:12 PM PDT 24 Jun 26 05:45:21 PM PDT 24 518548196 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2388638369 Jun 26 05:45:13 PM PDT 24 Jun 26 05:46:58 PM PDT 24 53287126908 ps
T72 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.812971709 Jun 26 05:45:12 PM PDT 24 Jun 26 05:45:29 PM PDT 24 2504057899 ps
T391 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3054555532 Jun 26 05:45:11 PM PDT 24 Jun 26 05:45:20 PM PDT 24 1142166630 ps
T392 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2864553895 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:14 PM PDT 24 3832545132 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3214386519 Jun 26 05:44:48 PM PDT 24 Jun 26 05:44:54 PM PDT 24 490232425 ps
T81 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3137291416 Jun 26 05:45:03 PM PDT 24 Jun 26 05:45:34 PM PDT 24 540044225 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1095924158 Jun 26 05:44:57 PM PDT 24 Jun 26 05:45:16 PM PDT 24 1642044014 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3762528437 Jun 26 05:44:40 PM PDT 24 Jun 26 05:44:55 PM PDT 24 1373627624 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3930444648 Jun 26 05:44:52 PM PDT 24 Jun 26 05:45:10 PM PDT 24 1948755370 ps
T397 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1227986410 Jun 26 05:45:14 PM PDT 24 Jun 26 05:45:25 PM PDT 24 168688460 ps
T124 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.434913892 Jun 26 05:44:45 PM PDT 24 Jun 26 05:45:24 PM PDT 24 791316377 ps
T82 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3847998213 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:20 PM PDT 24 3504675106 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1212216844 Jun 26 05:44:41 PM PDT 24 Jun 26 05:44:56 PM PDT 24 8072578454 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3970235993 Jun 26 05:44:57 PM PDT 24 Jun 26 05:45:06 PM PDT 24 292883622 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3438408838 Jun 26 05:44:44 PM PDT 24 Jun 26 05:44:55 PM PDT 24 700241718 ps
T400 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.986718049 Jun 26 05:45:11 PM PDT 24 Jun 26 05:45:19 PM PDT 24 193925164 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3872428333 Jun 26 05:44:53 PM PDT 24 Jun 26 05:45:07 PM PDT 24 1902127997 ps
T115 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.430717257 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:56 PM PDT 24 3908457440 ps
T125 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2132126560 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:54 PM PDT 24 9121010800 ps
T402 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.715816282 Jun 26 05:45:10 PM PDT 24 Jun 26 05:45:40 PM PDT 24 556771673 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2670965752 Jun 26 05:44:54 PM PDT 24 Jun 26 05:45:09 PM PDT 24 1032006445 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1798378123 Jun 26 05:44:45 PM PDT 24 Jun 26 05:44:52 PM PDT 24 639163501 ps
T405 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2808497254 Jun 26 05:44:52 PM PDT 24 Jun 26 05:45:15 PM PDT 24 389747815 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1750225864 Jun 26 05:44:49 PM PDT 24 Jun 26 05:44:57 PM PDT 24 168190508 ps
T84 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1145794642 Jun 26 05:45:01 PM PDT 24 Jun 26 05:46:30 PM PDT 24 10297294616 ps
T119 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1602130141 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:42 PM PDT 24 200912476 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2893854055 Jun 26 05:44:44 PM PDT 24 Jun 26 05:44:59 PM PDT 24 5553514185 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1413931461 Jun 26 05:44:52 PM PDT 24 Jun 26 05:45:33 PM PDT 24 342582515 ps
T409 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.370038161 Jun 26 05:45:08 PM PDT 24 Jun 26 05:45:29 PM PDT 24 4323304597 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4241055553 Jun 26 05:44:45 PM PDT 24 Jun 26 05:45:41 PM PDT 24 13105338056 ps
T85 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.914408340 Jun 26 05:45:08 PM PDT 24 Jun 26 05:46:06 PM PDT 24 124955128013 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1275006678 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:11 PM PDT 24 1884170454 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2120631231 Jun 26 05:44:51 PM PDT 24 Jun 26 05:45:24 PM PDT 24 546520196 ps
T126 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1248431938 Jun 26 05:44:52 PM PDT 24 Jun 26 05:45:38 PM PDT 24 17404151855 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1503413468 Jun 26 05:44:44 PM PDT 24 Jun 26 05:45:14 PM PDT 24 2250232937 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2176229114 Jun 26 05:45:07 PM PDT 24 Jun 26 05:45:24 PM PDT 24 7818632251 ps
T412 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2406574336 Jun 26 05:44:45 PM PDT 24 Jun 26 05:44:58 PM PDT 24 906319866 ps
T413 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2581601392 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:45 PM PDT 24 2241390614 ps
T87 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.228078140 Jun 26 05:44:43 PM PDT 24 Jun 26 05:44:58 PM PDT 24 4570347124 ps
T88 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2141611417 Jun 26 05:44:52 PM PDT 24 Jun 26 05:45:04 PM PDT 24 537195217 ps
T414 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1614361657 Jun 26 05:44:54 PM PDT 24 Jun 26 05:45:18 PM PDT 24 2446911544 ps
T415 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2008433894 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:18 PM PDT 24 2603405683 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1958906460 Jun 26 05:44:48 PM PDT 24 Jun 26 05:45:00 PM PDT 24 1353641013 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3822300729 Jun 26 05:44:55 PM PDT 24 Jun 26 05:46:29 PM PDT 24 10694679225 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.98115732 Jun 26 05:44:47 PM PDT 24 Jun 26 05:44:55 PM PDT 24 209610735 ps
T419 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3816897796 Jun 26 05:45:10 PM PDT 24 Jun 26 05:45:29 PM PDT 24 7167414817 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.623554321 Jun 26 05:45:13 PM PDT 24 Jun 26 05:45:21 PM PDT 24 333890699 ps
T421 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1725972858 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:11 PM PDT 24 1419655436 ps
T422 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1505322074 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:14 PM PDT 24 1669745621 ps
T423 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.936435763 Jun 26 05:45:12 PM PDT 24 Jun 26 05:45:23 PM PDT 24 276370276 ps
T424 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.919089095 Jun 26 05:44:52 PM PDT 24 Jun 26 05:45:10 PM PDT 24 1676099023 ps
T425 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1107516707 Jun 26 05:45:13 PM PDT 24 Jun 26 05:45:25 PM PDT 24 1090714970 ps
T426 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2277788644 Jun 26 05:45:05 PM PDT 24 Jun 26 05:46:46 PM PDT 24 59309063737 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1589115353 Jun 26 05:44:52 PM PDT 24 Jun 26 05:45:04 PM PDT 24 2899844994 ps
T428 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4100355547 Jun 26 05:45:02 PM PDT 24 Jun 26 05:45:21 PM PDT 24 14161172171 ps
T429 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3752209225 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:13 PM PDT 24 1391567134 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4075798193 Jun 26 05:44:53 PM PDT 24 Jun 26 05:45:06 PM PDT 24 761678848 ps
T89 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.803528998 Jun 26 05:45:12 PM PDT 24 Jun 26 05:46:30 PM PDT 24 109661299585 ps
T431 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3771004406 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:20 PM PDT 24 6671993272 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.556667545 Jun 26 05:44:44 PM PDT 24 Jun 26 05:45:03 PM PDT 24 8533855444 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1292688609 Jun 26 05:44:51 PM PDT 24 Jun 26 05:45:06 PM PDT 24 152031918 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3078737020 Jun 26 05:45:05 PM PDT 24 Jun 26 05:45:18 PM PDT 24 177786403 ps
T434 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.61558105 Jun 26 05:45:08 PM PDT 24 Jun 26 05:45:23 PM PDT 24 1612636459 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.258142238 Jun 26 05:45:09 PM PDT 24 Jun 26 05:45:18 PM PDT 24 291579296 ps
T436 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.969872856 Jun 26 05:45:04 PM PDT 24 Jun 26 05:46:18 PM PDT 24 7964019700 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3915031799 Jun 26 05:44:54 PM PDT 24 Jun 26 05:45:11 PM PDT 24 1585260529 ps
T438 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3382335502 Jun 26 05:45:12 PM PDT 24 Jun 26 05:45:21 PM PDT 24 833988970 ps
T439 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2805529931 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:10 PM PDT 24 275893938 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2885303958 Jun 26 05:44:45 PM PDT 24 Jun 26 05:45:02 PM PDT 24 1817635517 ps
T441 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1405599762 Jun 26 05:45:03 PM PDT 24 Jun 26 05:45:21 PM PDT 24 15604115426 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3066134566 Jun 26 05:44:40 PM PDT 24 Jun 26 05:44:49 PM PDT 24 630265506 ps
T120 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3254038995 Jun 26 05:44:52 PM PDT 24 Jun 26 05:46:07 PM PDT 24 1048687268 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2642842800 Jun 26 05:45:11 PM PDT 24 Jun 26 05:45:58 PM PDT 24 2147944661 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2102503882 Jun 26 05:45:00 PM PDT 24 Jun 26 05:45:44 PM PDT 24 11209080505 ps
T121 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1339349738 Jun 26 05:45:07 PM PDT 24 Jun 26 05:45:55 PM PDT 24 1737193251 ps
T445 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1645201865 Jun 26 05:45:01 PM PDT 24 Jun 26 05:46:18 PM PDT 24 3191126005 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2033027112 Jun 26 05:44:50 PM PDT 24 Jun 26 05:45:10 PM PDT 24 2199674305 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3538308287 Jun 26 05:44:44 PM PDT 24 Jun 26 05:45:34 PM PDT 24 8636791583 ps
T93 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3083550539 Jun 26 05:45:04 PM PDT 24 Jun 26 05:45:20 PM PDT 24 1607143174 ps
T448 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1458428574 Jun 26 05:45:00 PM PDT 24 Jun 26 05:46:03 PM PDT 24 29719897706 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1030080643 Jun 26 05:44:53 PM PDT 24 Jun 26 05:45:01 PM PDT 24 174763122 ps
T449 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3800230849 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:20 PM PDT 24 5549488021 ps
T450 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1017167085 Jun 26 05:45:03 PM PDT 24 Jun 26 05:45:23 PM PDT 24 4339976492 ps
T451 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4243712107 Jun 26 05:45:08 PM PDT 24 Jun 26 05:45:18 PM PDT 24 2885119638 ps
T452 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1221760706 Jun 26 05:45:09 PM PDT 24 Jun 26 05:45:23 PM PDT 24 969021809 ps
T453 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1753683101 Jun 26 05:44:45 PM PDT 24 Jun 26 05:45:04 PM PDT 24 31783538905 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1778564045 Jun 26 05:45:11 PM PDT 24 Jun 26 05:45:59 PM PDT 24 1784415549 ps
T455 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3706602406 Jun 26 05:44:57 PM PDT 24 Jun 26 05:45:13 PM PDT 24 5890321600 ps
T123 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2308204398 Jun 26 05:45:03 PM PDT 24 Jun 26 05:46:18 PM PDT 24 1783263058 ps
T456 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.802106432 Jun 26 05:45:09 PM PDT 24 Jun 26 05:45:28 PM PDT 24 3533141364 ps
T457 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3053822341 Jun 26 05:45:01 PM PDT 24 Jun 26 05:45:14 PM PDT 24 4417987017 ps
T458 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3716363015 Jun 26 05:44:53 PM PDT 24 Jun 26 05:45:09 PM PDT 24 2613283986 ps
T459 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1135315403 Jun 26 05:45:05 PM PDT 24 Jun 26 05:45:23 PM PDT 24 14050676700 ps
T460 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.535881384 Jun 26 05:44:44 PM PDT 24 Jun 26 05:44:55 PM PDT 24 825209631 ps
T461 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1628873058 Jun 26 05:45:11 PM PDT 24 Jun 26 05:45:30 PM PDT 24 2458806200 ps
T462 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.566471629 Jun 26 05:45:12 PM PDT 24 Jun 26 05:45:58 PM PDT 24 1225086108 ps
T463 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2856512703 Jun 26 05:44:52 PM PDT 24 Jun 26 05:45:00 PM PDT 24 174778100 ps

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1115520961
Short name T5
Test name
Test status
Simulation time 47178987465 ps
CPU time 5986.13 seconds
Started Jun 26 05:45:25 PM PDT 24
Finished Jun 26 07:25:14 PM PDT 24
Peak memory 235840 kb
Host smart-3ae75dd5-482d-4532-aac1-e3c895f63897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115520961 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1115520961
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1402630502
Short name T13
Test name
Test status
Simulation time 22056703683 ps
CPU time 138.85 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:47:35 PM PDT 24
Peak memory 237816 kb
Host smart-a13dceab-ff7a-4c56-9ac4-a9f096146f2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402630502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1402630502
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3643012869
Short name T6
Test name
Test status
Simulation time 5674247701 ps
CPU time 127.74 seconds
Started Jun 26 05:46:39 PM PDT 24
Finished Jun 26 05:48:48 PM PDT 24
Peak memory 234148 kb
Host smart-2f22572e-90c0-4ef7-8df1-51c2cd68b5fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643012869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3643012869
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.800279870
Short name T117
Test name
Test status
Simulation time 1299532056 ps
CPU time 74.19 seconds
Started Jun 26 05:45:03 PM PDT 24
Finished Jun 26 05:46:20 PM PDT 24
Peak memory 218920 kb
Host smart-58ad65d4-cdd1-4517-b8bf-82453d908bea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800279870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.800279870
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1135251632
Short name T9
Test name
Test status
Simulation time 9196770611 ps
CPU time 54.05 seconds
Started Jun 26 05:45:19 PM PDT 24
Finished Jun 26 05:46:15 PM PDT 24
Peak memory 236908 kb
Host smart-cf257b0f-87d7-4e63-850a-1d68325edb8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135251632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1135251632
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2029196752
Short name T36
Test name
Test status
Simulation time 124852794296 ps
CPU time 1243.68 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 06:06:56 PM PDT 24
Peak memory 230884 kb
Host smart-ab69287c-ab3d-4f4d-ba03-31e55a2b7b5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029196752 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2029196752
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.261451458
Short name T65
Test name
Test status
Simulation time 346923454 ps
CPU time 4.3 seconds
Started Jun 26 05:45:10 PM PDT 24
Finished Jun 26 05:45:16 PM PDT 24
Peak memory 210732 kb
Host smart-55b0cf4b-2860-4daa-b74c-a2db84bda350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261451458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.261451458
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2566132859
Short name T118
Test name
Test status
Simulation time 5102021425 ps
CPU time 79.2 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:46:35 PM PDT 24
Peak memory 218920 kb
Host smart-6c831b10-9dc4-4556-b3e8-9fed60978baf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566132859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2566132859
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1602130141
Short name T119
Test name
Test status
Simulation time 200912476 ps
CPU time 37.18 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:42 PM PDT 24
Peak memory 211136 kb
Host smart-3589708f-092c-4cc3-b13d-d98ddfdf8c33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602130141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1602130141
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.882910970
Short name T19
Test name
Test status
Simulation time 10240947529 ps
CPU time 16.55 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:46:22 PM PDT 24
Peak memory 211356 kb
Host smart-eaab9e78-9ce7-41e2-bc95-a6faa7b57156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882910970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.882910970
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2557625523
Short name T59
Test name
Test status
Simulation time 9849856462 ps
CPU time 94.32 seconds
Started Jun 26 05:46:30 PM PDT 24
Finished Jun 26 05:48:05 PM PDT 24
Peak memory 219412 kb
Host smart-e9d213e9-9c76-4425-85f9-9b6423567445
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557625523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2557625523
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.433539248
Short name T61
Test name
Test status
Simulation time 1888069014 ps
CPU time 15.97 seconds
Started Jun 26 05:45:34 PM PDT 24
Finished Jun 26 05:45:51 PM PDT 24
Peak memory 211908 kb
Host smart-52601319-69ed-431f-ab3e-feae1ac4713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433539248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.433539248
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4168047686
Short name T187
Test name
Test status
Simulation time 3117517541 ps
CPU time 27.72 seconds
Started Jun 26 05:45:24 PM PDT 24
Finished Jun 26 05:45:54 PM PDT 24
Peak memory 212492 kb
Host smart-a978d3ba-b4a7-4033-a80a-c7f98aa14b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168047686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4168047686
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1912029856
Short name T40
Test name
Test status
Simulation time 13790617569 ps
CPU time 18.35 seconds
Started Jun 26 05:45:42 PM PDT 24
Finished Jun 26 05:46:01 PM PDT 24
Peak memory 212324 kb
Host smart-fe79b62c-09f9-4957-83f2-75f27481c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912029856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1912029856
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.803528998
Short name T89
Test name
Test status
Simulation time 109661299585 ps
CPU time 74.76 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:46:30 PM PDT 24
Peak memory 210776 kb
Host smart-2b3a3ad3-f48f-414e-80c1-c22d3f9ed5dc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803528998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.803528998
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1212216844
Short name T83
Test name
Test status
Simulation time 8072578454 ps
CPU time 14.52 seconds
Started Jun 26 05:44:41 PM PDT 24
Finished Jun 26 05:44:56 PM PDT 24
Peak memory 218808 kb
Host smart-e3d1a668-11fa-46c0-b4a7-85eb1fcf50bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212216844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1212216844
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4077599726
Short name T104
Test name
Test status
Simulation time 1955124829 ps
CPU time 9.93 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:13 PM PDT 24
Peak memory 210680 kb
Host smart-48e36769-0409-4a37-bd8c-9773d24af0e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077599726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4077599726
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.282369789
Short name T94
Test name
Test status
Simulation time 112973689 ps
CPU time 5.37 seconds
Started Jun 26 05:45:47 PM PDT 24
Finished Jun 26 05:45:54 PM PDT 24
Peak memory 211328 kb
Host smart-be94d4e2-b241-4356-895d-6ad8e5d77872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282369789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.282369789
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2690026047
Short name T34
Test name
Test status
Simulation time 90519958175 ps
CPU time 1747.95 seconds
Started Jun 26 05:46:23 PM PDT 24
Finished Jun 26 06:15:32 PM PDT 24
Peak memory 236184 kb
Host smart-45d3dc3d-4a83-4c49-a61f-1d2ef3c158c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690026047 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2690026047
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2161594047
Short name T375
Test name
Test status
Simulation time 3599331205 ps
CPU time 10.02 seconds
Started Jun 26 05:44:46 PM PDT 24
Finished Jun 26 05:44:58 PM PDT 24
Peak memory 217960 kb
Host smart-116257c0-c9d9-4ad0-a0ff-4d62354e320f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161594047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2161594047
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3580381217
Short name T68
Test name
Test status
Simulation time 5891964890 ps
CPU time 16.2 seconds
Started Jun 26 05:44:46 PM PDT 24
Finished Jun 26 05:45:04 PM PDT 24
Peak memory 210756 kb
Host smart-44ff0e47-1315-4a1a-b0f2-b9514e70b02f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580381217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3580381217
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2893854055
Short name T407
Test name
Test status
Simulation time 5553514185 ps
CPU time 13.15 seconds
Started Jun 26 05:44:44 PM PDT 24
Finished Jun 26 05:44:59 PM PDT 24
Peak memory 218976 kb
Host smart-aa855e1e-7b8f-4f3e-ac0e-9566cee15206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893854055 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2893854055
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.228078140
Short name T87
Test name
Test status
Simulation time 4570347124 ps
CPU time 13.2 seconds
Started Jun 26 05:44:43 PM PDT 24
Finished Jun 26 05:44:58 PM PDT 24
Peak memory 218920 kb
Host smart-b50af7ed-1e8d-4b52-9c1e-5f7ab2c436d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228078140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.228078140
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2050058591
Short name T377
Test name
Test status
Simulation time 5209455395 ps
CPU time 12.03 seconds
Started Jun 26 05:44:44 PM PDT 24
Finished Jun 26 05:44:58 PM PDT 24
Peak memory 210460 kb
Host smart-6f5b48e0-31bd-410f-b4d8-e2c472e2f872
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050058591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2050058591
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3066134566
Short name T442
Test name
Test status
Simulation time 630265506 ps
CPU time 8.06 seconds
Started Jun 26 05:44:40 PM PDT 24
Finished Jun 26 05:44:49 PM PDT 24
Peak memory 210540 kb
Host smart-0aa60a04-c2c9-4828-bb7d-86aec064424b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066134566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3066134566
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4241055553
Short name T116
Test name
Test status
Simulation time 13105338056 ps
CPU time 53.85 seconds
Started Jun 26 05:44:45 PM PDT 24
Finished Jun 26 05:45:41 PM PDT 24
Peak memory 210764 kb
Host smart-1eaade94-3b1f-4c44-8844-f6e229550db9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241055553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4241055553
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.535881384
Short name T460
Test name
Test status
Simulation time 825209631 ps
CPU time 9.5 seconds
Started Jun 26 05:44:44 PM PDT 24
Finished Jun 26 05:44:55 PM PDT 24
Peak memory 218820 kb
Host smart-66b0531d-ae88-4133-8159-33896acc2132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535881384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.535881384
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2826520836
Short name T368
Test name
Test status
Simulation time 3703613948 ps
CPU time 17.28 seconds
Started Jun 26 05:44:46 PM PDT 24
Finished Jun 26 05:45:06 PM PDT 24
Peak memory 218652 kb
Host smart-b43edb9b-778c-4ba8-a1e0-0ff3f97eaa3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826520836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2826520836
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.434913892
Short name T124
Test name
Test status
Simulation time 791316377 ps
CPU time 36.82 seconds
Started Jun 26 05:44:45 PM PDT 24
Finished Jun 26 05:45:24 PM PDT 24
Peak memory 211904 kb
Host smart-6a201ea9-f6f5-4706-b841-b35b0a5abac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434913892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.434913892
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.556667545
Short name T90
Test name
Test status
Simulation time 8533855444 ps
CPU time 16.63 seconds
Started Jun 26 05:44:44 PM PDT 24
Finished Jun 26 05:45:03 PM PDT 24
Peak memory 218528 kb
Host smart-cfeae29c-2f38-432c-b79d-9358dea43fd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556667545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.556667545
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1798378123
Short name T404
Test name
Test status
Simulation time 639163501 ps
CPU time 4.39 seconds
Started Jun 26 05:44:45 PM PDT 24
Finished Jun 26 05:44:52 PM PDT 24
Peak memory 210728 kb
Host smart-34ac3780-0b6c-4f25-8e14-84c6e77d6c2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798378123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1798378123
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3762528437
Short name T395
Test name
Test status
Simulation time 1373627624 ps
CPU time 13.3 seconds
Started Jun 26 05:44:40 PM PDT 24
Finished Jun 26 05:44:55 PM PDT 24
Peak memory 218144 kb
Host smart-3659b26f-4496-481a-aeee-87ca39d3e213
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762528437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3762528437
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3438408838
Short name T399
Test name
Test status
Simulation time 700241718 ps
CPU time 8.56 seconds
Started Jun 26 05:44:44 PM PDT 24
Finished Jun 26 05:44:55 PM PDT 24
Peak memory 212624 kb
Host smart-0936d848-423e-402d-bc61-8b8be9cad1f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438408838 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3438408838
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.457330614
Short name T386
Test name
Test status
Simulation time 346800347 ps
CPU time 4.31 seconds
Started Jun 26 05:44:51 PM PDT 24
Finished Jun 26 05:44:59 PM PDT 24
Peak memory 217840 kb
Host smart-2237f8de-3a7e-448a-8cac-d3613e94758b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457330614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.457330614
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2975606121
Short name T384
Test name
Test status
Simulation time 1195450932 ps
CPU time 11.12 seconds
Started Jun 26 05:44:44 PM PDT 24
Finished Jun 26 05:44:56 PM PDT 24
Peak memory 210596 kb
Host smart-4b793c91-e0ca-4bcb-b26a-1375da4dcbe4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975606121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2975606121
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1279038745
Short name T370
Test name
Test status
Simulation time 6791219360 ps
CPU time 14.47 seconds
Started Jun 26 05:44:46 PM PDT 24
Finished Jun 26 05:45:03 PM PDT 24
Peak memory 210588 kb
Host smart-14b5495a-3275-4c52-8ba9-3afdb6a179be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279038745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1279038745
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2120631231
Short name T411
Test name
Test status
Simulation time 546520196 ps
CPU time 29.2 seconds
Started Jun 26 05:44:51 PM PDT 24
Finished Jun 26 05:45:24 PM PDT 24
Peak memory 211012 kb
Host smart-61a2f59e-7539-465e-99c8-0e12b5ed37e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120631231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2120631231
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2406574336
Short name T412
Test name
Test status
Simulation time 906319866 ps
CPU time 11.46 seconds
Started Jun 26 05:44:45 PM PDT 24
Finished Jun 26 05:44:58 PM PDT 24
Peak memory 218804 kb
Host smart-29f0c2fc-9c57-4ecb-94e3-188570d64c50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406574336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2406574336
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4227293982
Short name T388
Test name
Test status
Simulation time 1676056657 ps
CPU time 17.55 seconds
Started Jun 26 05:44:46 PM PDT 24
Finished Jun 26 05:45:06 PM PDT 24
Peak memory 218928 kb
Host smart-2193651f-0788-487c-a469-a9942a76c912
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227293982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4227293982
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3538308287
Short name T447
Test name
Test status
Simulation time 8636791583 ps
CPU time 47.5 seconds
Started Jun 26 05:44:44 PM PDT 24
Finished Jun 26 05:45:34 PM PDT 24
Peak memory 218920 kb
Host smart-77abccdb-ff0b-4e47-9f54-a7a09d278ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538308287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3538308287
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4020688235
Short name T378
Test name
Test status
Simulation time 1467651004 ps
CPU time 12.97 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:17 PM PDT 24
Peak memory 212956 kb
Host smart-c33ede97-8f66-4062-903a-b7b43bf34e80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020688235 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4020688235
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4243712107
Short name T451
Test name
Test status
Simulation time 2885119638 ps
CPU time 8.45 seconds
Started Jun 26 05:45:08 PM PDT 24
Finished Jun 26 05:45:18 PM PDT 24
Peak memory 210708 kb
Host smart-6f4ee8ae-8605-408c-ab6f-c5230e711061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243712107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4243712107
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2277788644
Short name T426
Test name
Test status
Simulation time 59309063737 ps
CPU time 99.01 seconds
Started Jun 26 05:45:05 PM PDT 24
Finished Jun 26 05:46:46 PM PDT 24
Peak memory 210804 kb
Host smart-c9d36a77-bfe6-464d-8ffe-13fb02e624f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277788644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2277788644
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1892190331
Short name T383
Test name
Test status
Simulation time 1914359586 ps
CPU time 17.13 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:21 PM PDT 24
Peak memory 218868 kb
Host smart-c92fcd96-026e-4c55-86a6-0f591b770e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892190331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1892190331
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2308204398
Short name T123
Test name
Test status
Simulation time 1783263058 ps
CPU time 71.55 seconds
Started Jun 26 05:45:03 PM PDT 24
Finished Jun 26 05:46:18 PM PDT 24
Peak memory 218932 kb
Host smart-ee897d39-0e0d-4695-b769-561c0d67dfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308204398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2308204398
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1135315403
Short name T459
Test name
Test status
Simulation time 14050676700 ps
CPU time 15.88 seconds
Started Jun 26 05:45:05 PM PDT 24
Finished Jun 26 05:45:23 PM PDT 24
Peak memory 219016 kb
Host smart-8a47d9ce-9280-4d55-b365-01d8a91218ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135315403 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1135315403
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1017167085
Short name T450
Test name
Test status
Simulation time 4339976492 ps
CPU time 16.82 seconds
Started Jun 26 05:45:03 PM PDT 24
Finished Jun 26 05:45:23 PM PDT 24
Peak memory 210736 kb
Host smart-030267df-1df2-4f7d-96eb-07d5ac9654bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017167085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1017167085
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1458428574
Short name T448
Test name
Test status
Simulation time 29719897706 ps
CPU time 61.25 seconds
Started Jun 26 05:45:00 PM PDT 24
Finished Jun 26 05:46:03 PM PDT 24
Peak memory 210708 kb
Host smart-5fa0fb23-0940-4e4b-8c0e-5b36e963ce12
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458428574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1458428574
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.860246199
Short name T66
Test name
Test status
Simulation time 2008970128 ps
CPU time 13.92 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:18 PM PDT 24
Peak memory 210656 kb
Host smart-cf4b367a-f3b2-4d0c-9adf-7da5d296e8f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860246199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.860246199
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3580944838
Short name T376
Test name
Test status
Simulation time 1491020940 ps
CPU time 14.24 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:19 PM PDT 24
Peak memory 218924 kb
Host smart-f5de046f-9313-499a-b431-c16ed173d6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580944838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3580944838
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2864553895
Short name T392
Test name
Test status
Simulation time 3832545132 ps
CPU time 11.46 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:14 PM PDT 24
Peak memory 218980 kb
Host smart-10a50aff-a73d-40f9-a0ac-e036030ce885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864553895 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2864553895
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1808082418
Short name T70
Test name
Test status
Simulation time 334218237 ps
CPU time 4.24 seconds
Started Jun 26 05:45:00 PM PDT 24
Finished Jun 26 05:45:07 PM PDT 24
Peak memory 210556 kb
Host smart-a19baf84-df30-4e47-b7eb-68f8703a57e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808082418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1808082418
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1145794642
Short name T84
Test name
Test status
Simulation time 10297294616 ps
CPU time 86.2 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:46:30 PM PDT 24
Peak memory 210688 kb
Host smart-5fe8e33f-211f-41ac-9335-0027e5b90d69
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145794642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1145794642
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1725972858
Short name T421
Test name
Test status
Simulation time 1419655436 ps
CPU time 6.85 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:11 PM PDT 24
Peak memory 210724 kb
Host smart-5d04eb6a-bc67-472f-918b-6b6a7e55844a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725972858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1725972858
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.76938506
Short name T385
Test name
Test status
Simulation time 5420941103 ps
CPU time 16.48 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:22 PM PDT 24
Peak memory 219012 kb
Host smart-7d44cc85-e878-4823-ad71-9682cc5457b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76938506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.76938506
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2132126560
Short name T125
Test name
Test status
Simulation time 9121010800 ps
CPU time 48.64 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:54 PM PDT 24
Peak memory 218996 kb
Host smart-79094abe-f395-40c4-8bf8-110a1ab16707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132126560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2132126560
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3711412725
Short name T372
Test name
Test status
Simulation time 502930446 ps
CPU time 4.65 seconds
Started Jun 26 05:45:03 PM PDT 24
Finished Jun 26 05:45:11 PM PDT 24
Peak memory 218996 kb
Host smart-3346487f-0752-4ef9-ad8a-4f7089f5c326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711412725 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3711412725
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2534898676
Short name T111
Test name
Test status
Simulation time 1299254156 ps
CPU time 8.1 seconds
Started Jun 26 05:45:03 PM PDT 24
Finished Jun 26 05:45:14 PM PDT 24
Peak memory 218768 kb
Host smart-638d4936-97a0-4d33-97a0-091c31b835e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534898676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2534898676
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.969872856
Short name T436
Test name
Test status
Simulation time 7964019700 ps
CPU time 71.38 seconds
Started Jun 26 05:45:04 PM PDT 24
Finished Jun 26 05:46:18 PM PDT 24
Peak memory 210728 kb
Host smart-bd745c81-7b04-40fe-932a-968447a5381c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969872856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.969872856
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2211503761
Short name T105
Test name
Test status
Simulation time 3546290457 ps
CPU time 7.43 seconds
Started Jun 26 05:45:08 PM PDT 24
Finished Jun 26 05:45:17 PM PDT 24
Peak memory 210804 kb
Host smart-fc266d24-5aa2-42d2-8d6b-28a1d3f1802b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211503761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2211503761
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4128078549
Short name T369
Test name
Test status
Simulation time 2091020631 ps
CPU time 19.98 seconds
Started Jun 26 05:45:00 PM PDT 24
Finished Jun 26 05:45:21 PM PDT 24
Peak memory 218864 kb
Host smart-93e074cf-9203-4b18-a8f0-d61071bbc554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128078549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4128078549
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2581601392
Short name T413
Test name
Test status
Simulation time 2241390614 ps
CPU time 39.68 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:45 PM PDT 24
Peak memory 212428 kb
Host smart-c7deafc1-2977-4386-aba6-142014a1bb48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581601392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2581601392
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3054555532
Short name T391
Test name
Test status
Simulation time 1142166630 ps
CPU time 4.67 seconds
Started Jun 26 05:45:11 PM PDT 24
Finished Jun 26 05:45:20 PM PDT 24
Peak memory 218968 kb
Host smart-0cf483b4-a1f9-4457-bd86-f74d6ea7ee4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054555532 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3054555532
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.258142238
Short name T435
Test name
Test status
Simulation time 291579296 ps
CPU time 6.32 seconds
Started Jun 26 05:45:09 PM PDT 24
Finished Jun 26 05:45:18 PM PDT 24
Peak memory 210704 kb
Host smart-d4afed0a-bbf5-4346-9ce8-13b06ae35c2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258142238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.258142238
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2148321508
Short name T106
Test name
Test status
Simulation time 6778236598 ps
CPU time 14.09 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:45:30 PM PDT 24
Peak memory 211144 kb
Host smart-61552199-cf3a-43c8-a13a-29981a09d71a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148321508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2148321508
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1227986410
Short name T397
Test name
Test status
Simulation time 168688460 ps
CPU time 7.04 seconds
Started Jun 26 05:45:14 PM PDT 24
Finished Jun 26 05:45:25 PM PDT 24
Peak memory 219244 kb
Host smart-fd443b5f-ef33-4c9b-8b9c-2c35e24f2a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227986410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1227986410
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2642842800
Short name T443
Test name
Test status
Simulation time 2147944661 ps
CPU time 42.9 seconds
Started Jun 26 05:45:11 PM PDT 24
Finished Jun 26 05:45:58 PM PDT 24
Peak memory 219008 kb
Host smart-223942ac-5485-4e38-a375-f32f6c0f5ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642842800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2642842800
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3382335502
Short name T438
Test name
Test status
Simulation time 833988970 ps
CPU time 5.25 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:45:21 PM PDT 24
Peak memory 219004 kb
Host smart-e63c9e31-7bcf-4e3d-a174-00e6bd5243ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382335502 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3382335502
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2388638369
Short name T71
Test name
Test status
Simulation time 53287126908 ps
CPU time 100.77 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:46:58 PM PDT 24
Peak memory 210684 kb
Host smart-fd57cdd4-f1a9-43c9-a68f-84cea8e0c98a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388638369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2388638369
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.940031468
Short name T109
Test name
Test status
Simulation time 1932588599 ps
CPU time 15.15 seconds
Started Jun 26 05:45:07 PM PDT 24
Finished Jun 26 05:45:23 PM PDT 24
Peak memory 210680 kb
Host smart-5ae7d8fb-fcfa-4fdc-8e8a-91b8be21a5ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940031468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.940031468
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2112891951
Short name T374
Test name
Test status
Simulation time 1434347930 ps
CPU time 17.21 seconds
Started Jun 26 05:45:08 PM PDT 24
Finished Jun 26 05:45:27 PM PDT 24
Peak memory 218864 kb
Host smart-f088faae-d1cf-467a-a559-6822e04c5722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112891951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2112891951
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1512738745
Short name T50
Test name
Test status
Simulation time 2257684375 ps
CPU time 41.88 seconds
Started Jun 26 05:45:08 PM PDT 24
Finished Jun 26 05:45:51 PM PDT 24
Peak memory 218976 kb
Host smart-55761f72-b7b1-457a-baf7-a3bdf9efd704
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512738745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1512738745
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4038306478
Short name T379
Test name
Test status
Simulation time 9861195874 ps
CPU time 13.23 seconds
Started Jun 26 05:45:08 PM PDT 24
Finished Jun 26 05:45:23 PM PDT 24
Peak memory 218952 kb
Host smart-12976cc6-2d9f-4c47-8bdd-59b5f211a803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038306478 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4038306478
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1107516707
Short name T425
Test name
Test status
Simulation time 1090714970 ps
CPU time 7.85 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:45:25 PM PDT 24
Peak memory 217920 kb
Host smart-dcf982db-3918-43ae-9a59-70a3b0e5f63f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107516707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1107516707
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2345648686
Short name T67
Test name
Test status
Simulation time 2225643913 ps
CPU time 31.7 seconds
Started Jun 26 05:45:10 PM PDT 24
Finished Jun 26 05:45:45 PM PDT 24
Peak memory 210624 kb
Host smart-f39c18b3-71f8-4df8-96bb-20139523296f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345648686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2345648686
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2213354430
Short name T387
Test name
Test status
Simulation time 22516525147 ps
CPU time 12.47 seconds
Started Jun 26 05:45:06 PM PDT 24
Finished Jun 26 05:45:20 PM PDT 24
Peak memory 210832 kb
Host smart-6e1eb2ec-704d-40bb-adac-2a16df237be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213354430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2213354430
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.370038161
Short name T409
Test name
Test status
Simulation time 4323304597 ps
CPU time 19.96 seconds
Started Jun 26 05:45:08 PM PDT 24
Finished Jun 26 05:45:29 PM PDT 24
Peak memory 219032 kb
Host smart-a41cf0d6-8f45-44d3-a3da-0b3fdabc8648
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370038161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.370038161
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3580677195
Short name T48
Test name
Test status
Simulation time 2159346470 ps
CPU time 47.61 seconds
Started Jun 26 05:45:09 PM PDT 24
Finished Jun 26 05:45:59 PM PDT 24
Peak memory 218976 kb
Host smart-f5127414-fcb0-4202-a2f6-410295d094b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580677195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3580677195
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.986718049
Short name T400
Test name
Test status
Simulation time 193925164 ps
CPU time 4.74 seconds
Started Jun 26 05:45:11 PM PDT 24
Finished Jun 26 05:45:19 PM PDT 24
Peak memory 219000 kb
Host smart-c523d580-c652-4ef6-89f0-870a1b8c3eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986718049 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.986718049
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1628873058
Short name T461
Test name
Test status
Simulation time 2458806200 ps
CPU time 15.22 seconds
Started Jun 26 05:45:11 PM PDT 24
Finished Jun 26 05:45:30 PM PDT 24
Peak memory 210620 kb
Host smart-081294fc-42ff-46aa-a9dc-9c0839880a04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628873058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1628873058
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.627185702
Short name T380
Test name
Test status
Simulation time 11058371376 ps
CPU time 68.13 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:46:25 PM PDT 24
Peak memory 210796 kb
Host smart-7196c41d-4039-4498-a50c-9930b73a374d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627185702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.627185702
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.812971709
Short name T72
Test name
Test status
Simulation time 2504057899 ps
CPU time 12.64 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:45:29 PM PDT 24
Peak memory 210856 kb
Host smart-3c8ae3de-cec3-4f6d-a7bb-b1bfd2b4600a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812971709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.812971709
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1221760706
Short name T452
Test name
Test status
Simulation time 969021809 ps
CPU time 11.21 seconds
Started Jun 26 05:45:09 PM PDT 24
Finished Jun 26 05:45:23 PM PDT 24
Peak memory 218960 kb
Host smart-bc20914f-8a94-41f1-95a9-1a2b3f8ad960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221760706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1221760706
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.61558105
Short name T434
Test name
Test status
Simulation time 1612636459 ps
CPU time 13.97 seconds
Started Jun 26 05:45:08 PM PDT 24
Finished Jun 26 05:45:23 PM PDT 24
Peak memory 218924 kb
Host smart-1985e358-8547-4ddb-be8c-bae115eb3472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61558105 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.61558105
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2176229114
Short name T92
Test name
Test status
Simulation time 7818632251 ps
CPU time 15.37 seconds
Started Jun 26 05:45:07 PM PDT 24
Finished Jun 26 05:45:24 PM PDT 24
Peak memory 218920 kb
Host smart-98748a77-0bfe-42fe-96e0-72d8e7e577fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176229114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2176229114
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.914408340
Short name T85
Test name
Test status
Simulation time 124955128013 ps
CPU time 56 seconds
Started Jun 26 05:45:08 PM PDT 24
Finished Jun 26 05:46:06 PM PDT 24
Peak memory 210796 kb
Host smart-0b1b24c5-8e9e-4e41-8436-6006dccaf52b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914408340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.914408340
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.623554321
Short name T420
Test name
Test status
Simulation time 333890699 ps
CPU time 4.28 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:45:21 PM PDT 24
Peak memory 210652 kb
Host smart-66c66a27-ae05-44ac-a9e0-6e6f1cf763bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623554321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.623554321
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.802106432
Short name T456
Test name
Test status
Simulation time 3533141364 ps
CPU time 17.24 seconds
Started Jun 26 05:45:09 PM PDT 24
Finished Jun 26 05:45:28 PM PDT 24
Peak memory 219036 kb
Host smart-6a16c94d-1e5c-45db-8711-483f827c6477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802106432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.802106432
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.566471629
Short name T462
Test name
Test status
Simulation time 1225086108 ps
CPU time 41.56 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:45:58 PM PDT 24
Peak memory 211856 kb
Host smart-e1cd7e10-e026-41a4-b3d4-a2894fb7c32c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566471629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.566471629
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.936435763
Short name T423
Test name
Test status
Simulation time 276370276 ps
CPU time 6.33 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:45:23 PM PDT 24
Peak memory 219028 kb
Host smart-8b26156f-bfaf-4a8d-96fb-eb9f36817c94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936435763 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.936435763
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.185430530
Short name T54
Test name
Test status
Simulation time 1758815485 ps
CPU time 14.35 seconds
Started Jun 26 05:45:10 PM PDT 24
Finished Jun 26 05:45:27 PM PDT 24
Peak memory 218860 kb
Host smart-0c4df376-0abb-4c66-a923-a455a8cb50c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185430530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.185430530
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.715816282
Short name T402
Test name
Test status
Simulation time 556771673 ps
CPU time 27.39 seconds
Started Jun 26 05:45:10 PM PDT 24
Finished Jun 26 05:45:40 PM PDT 24
Peak memory 210708 kb
Host smart-69631425-0c45-42ab-9775-9b37fc7cbfb2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715816282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.715816282
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1335774854
Short name T390
Test name
Test status
Simulation time 518548196 ps
CPU time 4.18 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:45:21 PM PDT 24
Peak memory 210796 kb
Host smart-0706e8d6-456c-44d5-95df-163a73c209fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335774854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1335774854
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3816897796
Short name T419
Test name
Test status
Simulation time 7167414817 ps
CPU time 16.94 seconds
Started Jun 26 05:45:10 PM PDT 24
Finished Jun 26 05:45:29 PM PDT 24
Peak memory 218996 kb
Host smart-b024dde3-7054-4c40-9457-6abccfc2ec94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816897796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3816897796
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1778564045
Short name T454
Test name
Test status
Simulation time 1784415549 ps
CPU time 44.82 seconds
Started Jun 26 05:45:11 PM PDT 24
Finished Jun 26 05:45:59 PM PDT 24
Peak memory 218912 kb
Host smart-d7f66109-4056-4fb0-9b9d-7859846a3743
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778564045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1778564045
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2885303958
Short name T440
Test name
Test status
Simulation time 1817635517 ps
CPU time 14.69 seconds
Started Jun 26 05:44:45 PM PDT 24
Finished Jun 26 05:45:02 PM PDT 24
Peak memory 210728 kb
Host smart-d5c22b92-c66b-451b-8770-db11f86b08c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885303958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2885303958
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2033027112
Short name T446
Test name
Test status
Simulation time 2199674305 ps
CPU time 16.57 seconds
Started Jun 26 05:44:50 PM PDT 24
Finished Jun 26 05:45:10 PM PDT 24
Peak memory 217188 kb
Host smart-b591eb07-ee4f-4ab6-98f9-2442f409e4db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033027112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2033027112
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1450243938
Short name T382
Test name
Test status
Simulation time 472926824 ps
CPU time 5.72 seconds
Started Jun 26 05:44:51 PM PDT 24
Finished Jun 26 05:45:00 PM PDT 24
Peak memory 217736 kb
Host smart-f55506a9-83b0-416e-8519-fcb5fbb94923
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450243938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1450243938
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1958906460
Short name T416
Test name
Test status
Simulation time 1353641013 ps
CPU time 8.61 seconds
Started Jun 26 05:44:48 PM PDT 24
Finished Jun 26 05:45:00 PM PDT 24
Peak memory 218888 kb
Host smart-ac09c825-d6b4-4c02-a1b1-60a77933377f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958906460 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1958906460
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2141611417
Short name T88
Test name
Test status
Simulation time 537195217 ps
CPU time 7.49 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:45:04 PM PDT 24
Peak memory 217348 kb
Host smart-6eb1c653-6f8e-40b4-9b8c-5f35020608c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141611417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2141611417
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.789022616
Short name T389
Test name
Test status
Simulation time 553314525 ps
CPU time 7.45 seconds
Started Jun 26 05:44:50 PM PDT 24
Finished Jun 26 05:45:01 PM PDT 24
Peak memory 210572 kb
Host smart-60f25740-3952-41cd-9009-213932399faa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789022616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.789022616
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1750225864
Short name T406
Test name
Test status
Simulation time 168190508 ps
CPU time 4.45 seconds
Started Jun 26 05:44:49 PM PDT 24
Finished Jun 26 05:44:57 PM PDT 24
Peak memory 210520 kb
Host smart-1e914a2c-c328-4a7b-8b71-ccd55ba5e22e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750225864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1750225864
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1503413468
Short name T86
Test name
Test status
Simulation time 2250232937 ps
CPU time 28.36 seconds
Started Jun 26 05:44:44 PM PDT 24
Finished Jun 26 05:45:14 PM PDT 24
Peak memory 210796 kb
Host smart-fd21b50d-dade-4933-b123-af09c3f57de0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503413468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1503413468
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1753683101
Short name T453
Test name
Test status
Simulation time 31783538905 ps
CPU time 16.28 seconds
Started Jun 26 05:44:45 PM PDT 24
Finished Jun 26 05:45:04 PM PDT 24
Peak memory 210932 kb
Host smart-20036cf3-1c57-4043-bc57-af7f95d2ab90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753683101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1753683101
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1292688609
Short name T432
Test name
Test status
Simulation time 152031918 ps
CPU time 11.03 seconds
Started Jun 26 05:44:51 PM PDT 24
Finished Jun 26 05:45:06 PM PDT 24
Peak memory 219244 kb
Host smart-b92f07e7-5990-47c8-bb2e-b01963b43f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292688609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1292688609
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1248431938
Short name T126
Test name
Test status
Simulation time 17404151855 ps
CPU time 42 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:45:38 PM PDT 24
Peak memory 218868 kb
Host smart-6c2cc402-4a59-4dd9-b19c-77faff59c0e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248431938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1248431938
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1589115353
Short name T427
Test name
Test status
Simulation time 2899844994 ps
CPU time 8.32 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:45:04 PM PDT 24
Peak memory 217712 kb
Host smart-b3b7a3f9-23ef-458f-bcb1-94234d7cc505
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589115353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1589115353
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3970235993
Short name T398
Test name
Test status
Simulation time 292883622 ps
CPU time 6.72 seconds
Started Jun 26 05:44:57 PM PDT 24
Finished Jun 26 05:45:06 PM PDT 24
Peak memory 217544 kb
Host smart-e273914a-10af-44fd-9638-aaef51657348
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970235993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3970235993
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.469046144
Short name T64
Test name
Test status
Simulation time 509644481 ps
CPU time 8.27 seconds
Started Jun 26 05:44:50 PM PDT 24
Finished Jun 26 05:45:02 PM PDT 24
Peak memory 218868 kb
Host smart-03a7ccba-0424-4f15-9de4-6cf458032a31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469046144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.469046144
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3716363015
Short name T458
Test name
Test status
Simulation time 2613283986 ps
CPU time 12.19 seconds
Started Jun 26 05:44:53 PM PDT 24
Finished Jun 26 05:45:09 PM PDT 24
Peak memory 219032 kb
Host smart-5b222f94-ef66-47a7-8a08-e676fa796800
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716363015 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3716363015
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.919089095
Short name T424
Test name
Test status
Simulation time 1676099023 ps
CPU time 13.82 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:45:10 PM PDT 24
Peak memory 210620 kb
Host smart-d959274f-8909-4ab4-9311-b4a2d797bf3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919089095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.919089095
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3214386519
Short name T393
Test name
Test status
Simulation time 490232425 ps
CPU time 4.23 seconds
Started Jun 26 05:44:48 PM PDT 24
Finished Jun 26 05:44:54 PM PDT 24
Peak memory 210552 kb
Host smart-5073ab87-e86e-4dae-bf3a-967cb6a8a927
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214386519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3214386519
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.360779361
Short name T367
Test name
Test status
Simulation time 8217111316 ps
CPU time 8.44 seconds
Started Jun 26 05:44:44 PM PDT 24
Finished Jun 26 05:44:53 PM PDT 24
Peak memory 210896 kb
Host smart-6ba7e0e2-0b63-4188-8f48-16d12c4dacd5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360779361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
360779361
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.77260585
Short name T381
Test name
Test status
Simulation time 6214508941 ps
CPU time 64.86 seconds
Started Jun 26 05:44:50 PM PDT 24
Finished Jun 26 05:45:59 PM PDT 24
Peak memory 218976 kb
Host smart-4979517f-561e-4fb1-b8f4-be96e2975f72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77260585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pass
thru_mem_tl_intg_err.77260585
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.690206984
Short name T52
Test name
Test status
Simulation time 8564625130 ps
CPU time 18.83 seconds
Started Jun 26 05:44:55 PM PDT 24
Finished Jun 26 05:45:17 PM PDT 24
Peak memory 211008 kb
Host smart-2dcc42fb-e16a-4928-9f48-3bf9337362aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690206984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.690206984
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.98115732
Short name T418
Test name
Test status
Simulation time 209610735 ps
CPU time 6.26 seconds
Started Jun 26 05:44:47 PM PDT 24
Finished Jun 26 05:44:55 PM PDT 24
Peak memory 218956 kb
Host smart-5ef1cc79-fe2f-4c85-9876-95b7d3356cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98115732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.98115732
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1413931461
Short name T408
Test name
Test status
Simulation time 342582515 ps
CPU time 37.22 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:45:33 PM PDT 24
Peak memory 218928 kb
Host smart-11c3d5fc-cf6b-4012-a03f-82bb28003fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413931461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1413931461
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2856512703
Short name T463
Test name
Test status
Simulation time 174778100 ps
CPU time 4.54 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:45:00 PM PDT 24
Peak memory 210584 kb
Host smart-bbd922ad-dc32-427d-a374-5921eef3d5b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856512703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2856512703
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3930444648
Short name T396
Test name
Test status
Simulation time 1948755370 ps
CPU time 14.5 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:45:10 PM PDT 24
Peak memory 218620 kb
Host smart-5128a7fa-dceb-4dfa-85d5-e522e2103515
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930444648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3930444648
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.807688510
Short name T53
Test name
Test status
Simulation time 2785864372 ps
CPU time 10.66 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:45:07 PM PDT 24
Peak memory 217576 kb
Host smart-fd2035bf-91ea-4851-b24e-c40784697601
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807688510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.807688510
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2670965752
Short name T403
Test name
Test status
Simulation time 1032006445 ps
CPU time 10.49 seconds
Started Jun 26 05:44:54 PM PDT 24
Finished Jun 26 05:45:09 PM PDT 24
Peak memory 219000 kb
Host smart-5c8d702e-ff6a-4df2-bbe4-dbc93994dd06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670965752 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2670965752
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1030080643
Short name T91
Test name
Test status
Simulation time 174763122 ps
CPU time 4.27 seconds
Started Jun 26 05:44:53 PM PDT 24
Finished Jun 26 05:45:01 PM PDT 24
Peak memory 218004 kb
Host smart-5dcfa77e-ed23-47b6-a4e8-f921509595f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030080643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1030080643
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4075798193
Short name T430
Test name
Test status
Simulation time 761678848 ps
CPU time 8.78 seconds
Started Jun 26 05:44:53 PM PDT 24
Finished Jun 26 05:45:06 PM PDT 24
Peak memory 210568 kb
Host smart-e753a90d-25dc-450d-a275-34c3ba207506
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075798193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4075798193
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3872428333
Short name T401
Test name
Test status
Simulation time 1902127997 ps
CPU time 9.92 seconds
Started Jun 26 05:44:53 PM PDT 24
Finished Jun 26 05:45:07 PM PDT 24
Peak memory 210560 kb
Host smart-7cc8aabb-0490-4a14-b9f4-27c9d0726ddb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872428333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3872428333
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3822300729
Short name T417
Test name
Test status
Simulation time 10694679225 ps
CPU time 89.91 seconds
Started Jun 26 05:44:55 PM PDT 24
Finished Jun 26 05:46:29 PM PDT 24
Peak memory 210768 kb
Host smart-dc38e3d1-d870-4864-9afa-179494dd2aea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822300729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3822300729
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3915031799
Short name T437
Test name
Test status
Simulation time 1585260529 ps
CPU time 13.16 seconds
Started Jun 26 05:44:54 PM PDT 24
Finished Jun 26 05:45:11 PM PDT 24
Peak memory 210776 kb
Host smart-c8116c0d-b028-4570-a9f8-bc604838ce4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915031799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3915031799
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1095924158
Short name T394
Test name
Test status
Simulation time 1642044014 ps
CPU time 16.42 seconds
Started Jun 26 05:44:57 PM PDT 24
Finished Jun 26 05:45:16 PM PDT 24
Peak memory 218852 kb
Host smart-9b0bb228-491c-4834-8ec6-bf6130483c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095924158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1095924158
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2542929889
Short name T122
Test name
Test status
Simulation time 1118231883 ps
CPU time 39.04 seconds
Started Jun 26 05:44:53 PM PDT 24
Finished Jun 26 05:45:36 PM PDT 24
Peak memory 218940 kb
Host smart-cd192df6-4420-437c-908d-8db97dc28819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542929889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2542929889
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1505322074
Short name T422
Test name
Test status
Simulation time 1669745621 ps
CPU time 9.73 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:14 PM PDT 24
Peak memory 218884 kb
Host smart-ac1eabd5-e642-46f1-af7f-716c49119bb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505322074 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1505322074
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3706602406
Short name T455
Test name
Test status
Simulation time 5890321600 ps
CPU time 12.87 seconds
Started Jun 26 05:44:57 PM PDT 24
Finished Jun 26 05:45:13 PM PDT 24
Peak memory 218720 kb
Host smart-593d9f63-d94a-4675-b9e4-b81876c4bc0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706602406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3706602406
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2808497254
Short name T405
Test name
Test status
Simulation time 389747815 ps
CPU time 19.49 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:45:15 PM PDT 24
Peak memory 210624 kb
Host smart-4d77659d-5ea8-4419-b493-2d02128d8ce4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808497254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2808497254
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4100355547
Short name T428
Test name
Test status
Simulation time 14161172171 ps
CPU time 15.21 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:21 PM PDT 24
Peak memory 210984 kb
Host smart-2d9c76d4-c5c3-4bcf-87b1-6fa0b1e70758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100355547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4100355547
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1614361657
Short name T414
Test name
Test status
Simulation time 2446911544 ps
CPU time 19.77 seconds
Started Jun 26 05:44:54 PM PDT 24
Finished Jun 26 05:45:18 PM PDT 24
Peak memory 219032 kb
Host smart-ddfa8458-a49e-41f6-aa68-3bacf8baf331
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614361657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1614361657
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3254038995
Short name T120
Test name
Test status
Simulation time 1048687268 ps
CPU time 71.15 seconds
Started Jun 26 05:44:52 PM PDT 24
Finished Jun 26 05:46:07 PM PDT 24
Peak memory 212300 kb
Host smart-13ebd191-6d52-462b-bd9c-e6d24fd4acdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254038995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3254038995
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4149525124
Short name T371
Test name
Test status
Simulation time 5729178128 ps
CPU time 13.07 seconds
Started Jun 26 05:44:58 PM PDT 24
Finished Jun 26 05:45:14 PM PDT 24
Peak memory 219052 kb
Host smart-cd820f7d-0191-4c55-b37a-c166acff0333
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149525124 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4149525124
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1405599762
Short name T441
Test name
Test status
Simulation time 15604115426 ps
CPU time 15.02 seconds
Started Jun 26 05:45:03 PM PDT 24
Finished Jun 26 05:45:21 PM PDT 24
Peak memory 210768 kb
Host smart-8cf5ccb5-0345-4dd0-8278-e9d103ea0eab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405599762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1405599762
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2102503882
Short name T444
Test name
Test status
Simulation time 11209080505 ps
CPU time 40.72 seconds
Started Jun 26 05:45:00 PM PDT 24
Finished Jun 26 05:45:44 PM PDT 24
Peak memory 210784 kb
Host smart-d477aec8-5568-42d1-8ba3-c01b7adc7b1b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102503882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2102503882
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3053822341
Short name T457
Test name
Test status
Simulation time 4417987017 ps
CPU time 10.64 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:14 PM PDT 24
Peak memory 210968 kb
Host smart-820f6043-92c2-4ac4-ae94-9a926e6faa5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053822341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3053822341
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2008433894
Short name T415
Test name
Test status
Simulation time 2603405683 ps
CPU time 14.11 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:18 PM PDT 24
Peak memory 215596 kb
Host smart-273b4da5-5465-4960-b374-ecadc2e32d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008433894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2008433894
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1645201865
Short name T445
Test name
Test status
Simulation time 3191126005 ps
CPU time 75.69 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:46:18 PM PDT 24
Peak memory 212316 kb
Host smart-7843ad65-78de-45a8-933f-97a5c59b134f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645201865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1645201865
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3752209225
Short name T429
Test name
Test status
Simulation time 1391567134 ps
CPU time 9.11 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:13 PM PDT 24
Peak memory 218940 kb
Host smart-fbf3b059-5968-429f-8408-8aa664260946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752209225 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3752209225
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3083550539
Short name T93
Test name
Test status
Simulation time 1607143174 ps
CPU time 12.98 seconds
Started Jun 26 05:45:04 PM PDT 24
Finished Jun 26 05:45:20 PM PDT 24
Peak memory 218764 kb
Host smart-82916967-8b3c-45e5-a203-d97b5a6e9bf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083550539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3083550539
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3137291416
Short name T81
Test name
Test status
Simulation time 540044225 ps
CPU time 28.11 seconds
Started Jun 26 05:45:03 PM PDT 24
Finished Jun 26 05:45:34 PM PDT 24
Peak memory 210700 kb
Host smart-65c7470d-b12c-499c-99e3-b4c0ded45fcf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137291416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3137291416
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1275006678
Short name T410
Test name
Test status
Simulation time 1884170454 ps
CPU time 5.84 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:11 PM PDT 24
Peak memory 218120 kb
Host smart-fe2efd4c-40d1-4a62-98da-f808406a76c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275006678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1275006678
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3078737020
Short name T433
Test name
Test status
Simulation time 177786403 ps
CPU time 10.78 seconds
Started Jun 26 05:45:05 PM PDT 24
Finished Jun 26 05:45:18 PM PDT 24
Peak memory 218956 kb
Host smart-421139a3-a6af-4e55-9891-d8312aaa81a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078737020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3078737020
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3530874660
Short name T49
Test name
Test status
Simulation time 2159123079 ps
CPU time 41.69 seconds
Started Jun 26 05:44:59 PM PDT 24
Finished Jun 26 05:45:42 PM PDT 24
Peak memory 218912 kb
Host smart-a0886fcc-52d5-4035-a9cb-6028dc452f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530874660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3530874660
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2805529931
Short name T439
Test name
Test status
Simulation time 275893938 ps
CPU time 5.32 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:10 PM PDT 24
Peak memory 218988 kb
Host smart-56c2a6ca-30b1-49b4-a1ab-f1b106b3ab09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805529931 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2805529931
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3847998213
Short name T82
Test name
Test status
Simulation time 3504675106 ps
CPU time 14.9 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:20 PM PDT 24
Peak memory 210616 kb
Host smart-3f4ec998-abd5-45ee-be7c-c971d4bee709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847998213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3847998213
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.430717257
Short name T115
Test name
Test status
Simulation time 3908457440 ps
CPU time 51.21 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:56 PM PDT 24
Peak memory 210788 kb
Host smart-b4f63dda-fb1b-4ed9-8e28-89c823b1b010
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430717257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.430717257
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2842229913
Short name T110
Test name
Test status
Simulation time 1405977487 ps
CPU time 12.49 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:17 PM PDT 24
Peak memory 218928 kb
Host smart-dab923bc-abf7-4478-8680-5b8a2f63d7ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842229913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2842229913
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3800230849
Short name T449
Test name
Test status
Simulation time 5549488021 ps
CPU time 16.95 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:20 PM PDT 24
Peak memory 218916 kb
Host smart-125b075f-840c-4b70-9998-2d9f6f1ec66d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800230849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3800230849
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1339349738
Short name T121
Test name
Test status
Simulation time 1737193251 ps
CPU time 45.55 seconds
Started Jun 26 05:45:07 PM PDT 24
Finished Jun 26 05:45:55 PM PDT 24
Peak memory 211860 kb
Host smart-a68b0bd6-9238-4368-804c-9ed404a578ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339349738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1339349738
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3686134637
Short name T373
Test name
Test status
Simulation time 8936637323 ps
CPU time 15.75 seconds
Started Jun 26 05:45:03 PM PDT 24
Finished Jun 26 05:45:22 PM PDT 24
Peak memory 218952 kb
Host smart-7c0bfa41-738e-4b32-83bf-e9476e6ee89a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686134637 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3686134637
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3312687530
Short name T107
Test name
Test status
Simulation time 4778720446 ps
CPU time 10.94 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:16 PM PDT 24
Peak memory 210676 kb
Host smart-2881e4fc-412e-4032-995c-262a492e1732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312687530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3312687530
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.588555826
Short name T69
Test name
Test status
Simulation time 3368700096 ps
CPU time 27.97 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:33 PM PDT 24
Peak memory 210800 kb
Host smart-bb7a2a68-28b2-4c6b-ba52-8a4034e31a67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588555826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.588555826
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2349940118
Short name T108
Test name
Test status
Simulation time 1145258484 ps
CPU time 11.12 seconds
Started Jun 26 05:45:02 PM PDT 24
Finished Jun 26 05:45:17 PM PDT 24
Peak memory 218896 kb
Host smart-121bbc9e-5303-44ef-96a7-1155397a7bfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349940118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2349940118
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3771004406
Short name T431
Test name
Test status
Simulation time 6671993272 ps
CPU time 15.78 seconds
Started Jun 26 05:45:01 PM PDT 24
Finished Jun 26 05:45:20 PM PDT 24
Peak memory 219016 kb
Host smart-6a3e58f5-af92-4bb3-ab49-4a12ff807417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771004406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3771004406
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1186927887
Short name T318
Test name
Test status
Simulation time 347163178 ps
CPU time 4.23 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:45:20 PM PDT 24
Peak memory 211308 kb
Host smart-abe632a4-484b-4396-b3bb-c5f451a6c157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186927887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1186927887
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3172455929
Short name T175
Test name
Test status
Simulation time 6164577131 ps
CPU time 26.71 seconds
Started Jun 26 05:45:10 PM PDT 24
Finished Jun 26 05:45:41 PM PDT 24
Peak memory 211480 kb
Host smart-90ebb41d-7786-45cf-855b-f48a3cf84761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172455929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3172455929
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2528045420
Short name T114
Test name
Test status
Simulation time 1274996627 ps
CPU time 12.58 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:45:29 PM PDT 24
Peak memory 211272 kb
Host smart-19e1dc2e-a5fd-4463-969d-599fecc93ac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528045420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2528045420
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1696209424
Short name T17
Test name
Test status
Simulation time 462349940 ps
CPU time 54.25 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:46:10 PM PDT 24
Peak memory 237812 kb
Host smart-fe11c6a8-10f7-4c56-844d-b26519db5220
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696209424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1696209424
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3258582297
Short name T143
Test name
Test status
Simulation time 4430321468 ps
CPU time 22.86 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:45:39 PM PDT 24
Peak memory 213844 kb
Host smart-46d74ca2-95ea-493f-ba11-37641c76aa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258582297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3258582297
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2086738371
Short name T214
Test name
Test status
Simulation time 4706892409 ps
CPU time 27.39 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:45:44 PM PDT 24
Peak memory 215476 kb
Host smart-d59c51e4-920c-4f6c-b0de-665232b2f65d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086738371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2086738371
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2180294320
Short name T255
Test name
Test status
Simulation time 2757777164 ps
CPU time 8.85 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:45:25 PM PDT 24
Peak memory 211272 kb
Host smart-1c107625-810b-4118-9631-6107398ab204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180294320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2180294320
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.411740147
Short name T27
Test name
Test status
Simulation time 46381373602 ps
CPU time 136.36 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:47:33 PM PDT 24
Peak memory 225132 kb
Host smart-857da4be-bcd6-4051-a9db-a78af1bd0a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411740147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.411740147
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2123682186
Short name T301
Test name
Test status
Simulation time 2883892970 ps
CPU time 25.75 seconds
Started Jun 26 05:45:09 PM PDT 24
Finished Jun 26 05:45:37 PM PDT 24
Peak memory 212528 kb
Host smart-f093b4a4-8031-4667-8d0b-7fa39f0486f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123682186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2123682186
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1010294235
Short name T199
Test name
Test status
Simulation time 3754542244 ps
CPU time 16.51 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:45:34 PM PDT 24
Peak memory 211616 kb
Host smart-2b3e9647-8fe6-49bb-a5a9-1bb8da7c58f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010294235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1010294235
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.302549435
Short name T23
Test name
Test status
Simulation time 1724196766 ps
CPU time 60.37 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:46:18 PM PDT 24
Peak memory 236804 kb
Host smart-67f7659f-10d8-4180-9f42-380d11523b75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302549435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.302549435
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3693669172
Short name T197
Test name
Test status
Simulation time 189797884 ps
CPU time 10.05 seconds
Started Jun 26 05:45:10 PM PDT 24
Finished Jun 26 05:45:24 PM PDT 24
Peak memory 213284 kb
Host smart-85605435-9aa5-47b6-b120-4d54df8813fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693669172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3693669172
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3166380815
Short name T158
Test name
Test status
Simulation time 13697892320 ps
CPU time 97.56 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:46:54 PM PDT 24
Peak memory 216788 kb
Host smart-a66be6ba-3819-49ec-bb7f-348e96163e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166380815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3166380815
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1307622295
Short name T185
Test name
Test status
Simulation time 346579099 ps
CPU time 4.19 seconds
Started Jun 26 05:45:28 PM PDT 24
Finished Jun 26 05:45:34 PM PDT 24
Peak memory 211244 kb
Host smart-6db9d279-2e98-446e-a5db-d4e9b9fd1ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307622295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1307622295
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2751206201
Short name T30
Test name
Test status
Simulation time 137764184109 ps
CPU time 211.64 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:48:55 PM PDT 24
Peak memory 233988 kb
Host smart-99adad6b-01f8-4a6c-9ff6-f54c35bf7c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751206201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2751206201
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.689998897
Short name T182
Test name
Test status
Simulation time 706163319 ps
CPU time 6.78 seconds
Started Jun 26 05:45:19 PM PDT 24
Finished Jun 26 05:45:28 PM PDT 24
Peak memory 211240 kb
Host smart-f9f0a6e1-abe9-4679-912b-2fb6c1ff9720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=689998897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.689998897
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2129743702
Short name T341
Test name
Test status
Simulation time 3088977048 ps
CPU time 26.62 seconds
Started Jun 26 05:45:18 PM PDT 24
Finished Jun 26 05:45:46 PM PDT 24
Peak memory 213156 kb
Host smart-29952b63-eed2-4af3-8a84-797b8fc5deda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129743702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2129743702
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.159610984
Short name T162
Test name
Test status
Simulation time 7863808783 ps
CPU time 73.91 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:46:38 PM PDT 24
Peak memory 217808 kb
Host smart-a0b3bfcb-6baf-4c57-9406-d4c6b86e5f9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159610984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.159610984
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1123033046
Short name T215
Test name
Test status
Simulation time 1479376417 ps
CPU time 12.78 seconds
Started Jun 26 05:45:26 PM PDT 24
Finished Jun 26 05:45:42 PM PDT 24
Peak memory 211268 kb
Host smart-07c716bd-319d-48ea-8b56-26877dd024ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123033046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1123033046
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.735827996
Short name T42
Test name
Test status
Simulation time 34654374563 ps
CPU time 399.02 seconds
Started Jun 26 05:45:24 PM PDT 24
Finished Jun 26 05:52:06 PM PDT 24
Peak memory 228480 kb
Host smart-34cb4af4-0220-4d8c-972c-5f3e96b5d5c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735827996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.735827996
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1957764388
Short name T344
Test name
Test status
Simulation time 4637136808 ps
CPU time 24.8 seconds
Started Jun 26 05:45:26 PM PDT 24
Finished Jun 26 05:45:54 PM PDT 24
Peak memory 211332 kb
Host smart-070090d9-faa7-4635-a4fb-424a900f2f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957764388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1957764388
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3301510151
Short name T273
Test name
Test status
Simulation time 4012615365 ps
CPU time 15.71 seconds
Started Jun 26 05:45:29 PM PDT 24
Finished Jun 26 05:45:46 PM PDT 24
Peak memory 211412 kb
Host smart-7263a60c-89a7-43a6-a190-fd87731b1efc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301510151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3301510151
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2365699381
Short name T238
Test name
Test status
Simulation time 8511446349 ps
CPU time 26 seconds
Started Jun 26 05:45:22 PM PDT 24
Finished Jun 26 05:45:50 PM PDT 24
Peak memory 214248 kb
Host smart-36cd3941-2f04-4d4b-859b-17a8063fdeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365699381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2365699381
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3234728854
Short name T12
Test name
Test status
Simulation time 376393635 ps
CPU time 20.05 seconds
Started Jun 26 05:45:26 PM PDT 24
Finished Jun 26 05:45:48 PM PDT 24
Peak memory 215276 kb
Host smart-34ae3b19-6194-4f1a-8bba-93b2a59c536b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234728854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3234728854
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1483762415
Short name T229
Test name
Test status
Simulation time 6956428209 ps
CPU time 15.37 seconds
Started Jun 26 05:45:31 PM PDT 24
Finished Jun 26 05:45:48 PM PDT 24
Peak memory 211344 kb
Host smart-d6edc0b3-5e01-476f-a01f-2f48e8484b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483762415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1483762415
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3613554659
Short name T298
Test name
Test status
Simulation time 4765377397 ps
CPU time 150.84 seconds
Started Jun 26 05:45:27 PM PDT 24
Finished Jun 26 05:48:00 PM PDT 24
Peak memory 237892 kb
Host smart-059d0857-2d75-4124-a513-f6a56eade371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613554659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3613554659
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4191147767
Short name T360
Test name
Test status
Simulation time 1718871222 ps
CPU time 14.77 seconds
Started Jun 26 05:45:28 PM PDT 24
Finished Jun 26 05:45:45 PM PDT 24
Peak memory 211352 kb
Host smart-67578b7c-b593-4523-bf2e-5620eb2c1d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191147767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4191147767
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3673382441
Short name T188
Test name
Test status
Simulation time 4113785441 ps
CPU time 36.87 seconds
Started Jun 26 05:45:25 PM PDT 24
Finished Jun 26 05:46:05 PM PDT 24
Peak memory 213640 kb
Host smart-f5bcba91-992f-4ca9-ada3-c3ad773cf566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673382441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3673382441
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2834116779
Short name T275
Test name
Test status
Simulation time 20462283826 ps
CPU time 81.49 seconds
Started Jun 26 05:45:25 PM PDT 24
Finished Jun 26 05:46:49 PM PDT 24
Peak memory 218724 kb
Host smart-2321f641-3e11-40fe-b471-7b8ae08c9d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834116779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2834116779
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1447898653
Short name T265
Test name
Test status
Simulation time 1549567224 ps
CPU time 9.22 seconds
Started Jun 26 05:45:31 PM PDT 24
Finished Jun 26 05:45:42 PM PDT 24
Peak memory 211276 kb
Host smart-f8e72490-bb77-400d-aeae-0748ea4b4fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447898653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1447898653
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2015621304
Short name T138
Test name
Test status
Simulation time 27106429616 ps
CPU time 147.64 seconds
Started Jun 26 05:45:35 PM PDT 24
Finished Jun 26 05:48:04 PM PDT 24
Peak memory 228664 kb
Host smart-e0218cde-96f6-4868-9e9e-0a4ae1bca99c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015621304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2015621304
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3267008464
Short name T252
Test name
Test status
Simulation time 665369675 ps
CPU time 9.6 seconds
Started Jun 26 05:45:33 PM PDT 24
Finished Jun 26 05:45:44 PM PDT 24
Peak memory 211944 kb
Host smart-c7f22e5c-1862-43b9-a10d-60c54bf720fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267008464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3267008464
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.991012210
Short name T304
Test name
Test status
Simulation time 2745027811 ps
CPU time 17.61 seconds
Started Jun 26 05:45:32 PM PDT 24
Finished Jun 26 05:45:50 PM PDT 24
Peak memory 211316 kb
Host smart-513504d3-a6c4-479b-bc1e-d8880fe57954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991012210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.991012210
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3556139086
Short name T330
Test name
Test status
Simulation time 744286894 ps
CPU time 10.77 seconds
Started Jun 26 05:45:34 PM PDT 24
Finished Jun 26 05:45:46 PM PDT 24
Peak memory 213600 kb
Host smart-658f8e77-0f96-40d4-b119-0100de415706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556139086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3556139086
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2342697044
Short name T51
Test name
Test status
Simulation time 8238578761 ps
CPU time 35.61 seconds
Started Jun 26 05:45:30 PM PDT 24
Finished Jun 26 05:46:07 PM PDT 24
Peak memory 213568 kb
Host smart-9f2848d2-41a5-4248-ab77-80a7575e653b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342697044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2342697044
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3610197010
Short name T317
Test name
Test status
Simulation time 458407889 ps
CPU time 6.74 seconds
Started Jun 26 05:45:32 PM PDT 24
Finished Jun 26 05:45:41 PM PDT 24
Peak memory 211284 kb
Host smart-ceb0025b-17cc-43db-8b9b-795935efb79e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610197010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3610197010
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3380065294
Short name T172
Test name
Test status
Simulation time 64507427367 ps
CPU time 356.61 seconds
Started Jun 26 05:45:36 PM PDT 24
Finished Jun 26 05:51:34 PM PDT 24
Peak memory 212804 kb
Host smart-583000f9-6633-4b0a-b0ab-7abc652f9a8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380065294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3380065294
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2678955690
Short name T294
Test name
Test status
Simulation time 823642355 ps
CPU time 15.07 seconds
Started Jun 26 05:45:30 PM PDT 24
Finished Jun 26 05:45:46 PM PDT 24
Peak memory 211960 kb
Host smart-162d5c18-440b-4fde-a297-1200ac377e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678955690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2678955690
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4010387685
Short name T345
Test name
Test status
Simulation time 4300376971 ps
CPU time 17.09 seconds
Started Jun 26 05:45:31 PM PDT 24
Finished Jun 26 05:45:49 PM PDT 24
Peak memory 211332 kb
Host smart-aee7f771-c4c3-40cb-bb2d-19744a8a3620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010387685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4010387685
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3462290820
Short name T357
Test name
Test status
Simulation time 4906210970 ps
CPU time 34.36 seconds
Started Jun 26 05:45:31 PM PDT 24
Finished Jun 26 05:46:06 PM PDT 24
Peak memory 212768 kb
Host smart-56b845b6-a174-416c-bf06-0d6491114a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462290820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3462290820
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3214985295
Short name T159
Test name
Test status
Simulation time 10152321485 ps
CPU time 40.34 seconds
Started Jun 26 05:45:32 PM PDT 24
Finished Jun 26 05:46:14 PM PDT 24
Peak memory 217860 kb
Host smart-21476bb3-8111-44d2-a9ff-ac2ea0cffcd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214985295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3214985295
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.371091667
Short name T57
Test name
Test status
Simulation time 88892304 ps
CPU time 4.37 seconds
Started Jun 26 05:45:38 PM PDT 24
Finished Jun 26 05:45:43 PM PDT 24
Peak memory 211288 kb
Host smart-bda92789-388b-47c9-92da-da8577b4cdf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371091667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.371091667
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1760368138
Short name T279
Test name
Test status
Simulation time 31029777776 ps
CPU time 349.23 seconds
Started Jun 26 05:45:38 PM PDT 24
Finished Jun 26 05:51:28 PM PDT 24
Peak memory 225120 kb
Host smart-753444d5-1023-4e68-b8b1-c58ff63dbb84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760368138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1760368138
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4002271004
Short name T129
Test name
Test status
Simulation time 13920171190 ps
CPU time 31.9 seconds
Started Jun 26 05:45:37 PM PDT 24
Finished Jun 26 05:46:10 PM PDT 24
Peak memory 211296 kb
Host smart-c582dabe-362b-4909-889a-705900e3a2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002271004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4002271004
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2330883237
Short name T209
Test name
Test status
Simulation time 1332336423 ps
CPU time 13.54 seconds
Started Jun 26 05:45:37 PM PDT 24
Finished Jun 26 05:45:51 PM PDT 24
Peak memory 211328 kb
Host smart-e5cc2a6c-4dc5-4a39-81aa-1cfd41659d2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330883237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2330883237
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1430802945
Short name T323
Test name
Test status
Simulation time 5145245751 ps
CPU time 28 seconds
Started Jun 26 05:45:42 PM PDT 24
Finished Jun 26 05:46:11 PM PDT 24
Peak memory 214168 kb
Host smart-4205446c-6902-4822-8cb5-8254e69a86a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430802945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1430802945
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2776769434
Short name T335
Test name
Test status
Simulation time 463370379 ps
CPU time 28.02 seconds
Started Jun 26 05:45:40 PM PDT 24
Finished Jun 26 05:46:09 PM PDT 24
Peak memory 215348 kb
Host smart-4b4cac33-7d47-499f-95c8-c45d93ad80bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776769434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2776769434
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2848491635
Short name T253
Test name
Test status
Simulation time 944668684 ps
CPU time 10.18 seconds
Started Jun 26 05:45:39 PM PDT 24
Finished Jun 26 05:45:50 PM PDT 24
Peak memory 211504 kb
Host smart-5c2167b2-3948-4606-81ac-439e80ab8133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848491635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2848491635
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3406294100
Short name T216
Test name
Test status
Simulation time 59627275616 ps
CPU time 98.34 seconds
Started Jun 26 05:45:37 PM PDT 24
Finished Jun 26 05:47:17 PM PDT 24
Peak memory 236788 kb
Host smart-d83dc8ae-6433-4207-b23e-5240c0ea715a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406294100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3406294100
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2360595375
Short name T186
Test name
Test status
Simulation time 24391979798 ps
CPU time 15.88 seconds
Started Jun 26 05:45:43 PM PDT 24
Finished Jun 26 05:46:00 PM PDT 24
Peak memory 211316 kb
Host smart-d4a67280-6131-4b43-ba12-a89cd1a7bc8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360595375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2360595375
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2100256317
Short name T333
Test name
Test status
Simulation time 764499410 ps
CPU time 15.44 seconds
Started Jun 26 05:45:39 PM PDT 24
Finished Jun 26 05:45:55 PM PDT 24
Peak memory 212540 kb
Host smart-289ac784-ccb4-4369-8f9e-db998446b3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100256317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2100256317
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2248702450
Short name T272
Test name
Test status
Simulation time 22790664909 ps
CPU time 66.09 seconds
Started Jun 26 05:45:40 PM PDT 24
Finished Jun 26 05:46:48 PM PDT 24
Peak memory 217212 kb
Host smart-681eefa5-f11f-409a-afe4-d4d2bc7ad4cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248702450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2248702450
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3972968421
Short name T44
Test name
Test status
Simulation time 211194287095 ps
CPU time 1245.12 seconds
Started Jun 26 05:45:38 PM PDT 24
Finished Jun 26 06:06:24 PM PDT 24
Peak memory 235860 kb
Host smart-7fadadef-41cd-4420-bbb1-c6da22b774df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972968421 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3972968421
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1384134345
Short name T300
Test name
Test status
Simulation time 3461684918 ps
CPU time 14.27 seconds
Started Jun 26 05:45:45 PM PDT 24
Finished Jun 26 05:46:01 PM PDT 24
Peak memory 211272 kb
Host smart-47c9ca8e-c96b-43d0-88c8-e9fd8d3aaecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384134345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1384134345
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1605188691
Short name T140
Test name
Test status
Simulation time 65072639660 ps
CPU time 208.42 seconds
Started Jun 26 05:45:38 PM PDT 24
Finished Jun 26 05:49:08 PM PDT 24
Peak memory 212636 kb
Host smart-10d7f2e4-609b-4166-8a56-d8c51b9e1f3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605188691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1605188691
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2768133005
Short name T261
Test name
Test status
Simulation time 2964296780 ps
CPU time 27.22 seconds
Started Jun 26 05:45:41 PM PDT 24
Finished Jun 26 05:46:09 PM PDT 24
Peak memory 211996 kb
Host smart-61bd8c38-91f9-4075-b047-160290915b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768133005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2768133005
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4231607258
Short name T102
Test name
Test status
Simulation time 10627839739 ps
CPU time 15.69 seconds
Started Jun 26 05:45:40 PM PDT 24
Finished Jun 26 05:45:57 PM PDT 24
Peak memory 211372 kb
Host smart-93e5a08f-1640-4559-9f1d-f84a6e1e416f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231607258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4231607258
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2771284461
Short name T332
Test name
Test status
Simulation time 14507888848 ps
CPU time 41.44 seconds
Started Jun 26 05:45:40 PM PDT 24
Finished Jun 26 05:46:23 PM PDT 24
Peak memory 213504 kb
Host smart-97d02e8c-1f7d-4d62-ae54-e7ba1b92f053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771284461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2771284461
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.525564288
Short name T353
Test name
Test status
Simulation time 335238133 ps
CPU time 6.99 seconds
Started Jun 26 05:45:37 PM PDT 24
Finished Jun 26 05:45:45 PM PDT 24
Peak memory 211300 kb
Host smart-c6d0ea1b-83d5-4450-902d-6e9b1a094636
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525564288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.525564288
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2337381625
Short name T179
Test name
Test status
Simulation time 2047123049 ps
CPU time 16.06 seconds
Started Jun 26 05:45:44 PM PDT 24
Finished Jun 26 05:46:01 PM PDT 24
Peak memory 211272 kb
Host smart-10618bc0-536a-4c3c-81c4-3d80d2863f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337381625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2337381625
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.808010058
Short name T95
Test name
Test status
Simulation time 37982346480 ps
CPU time 402.65 seconds
Started Jun 26 05:45:45 PM PDT 24
Finished Jun 26 05:52:29 PM PDT 24
Peak memory 224812 kb
Host smart-559b5843-18da-47ef-806e-16543594528d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808010058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.808010058
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2941875684
Short name T311
Test name
Test status
Simulation time 8718054237 ps
CPU time 34.1 seconds
Started Jun 26 05:45:46 PM PDT 24
Finished Jun 26 05:46:21 PM PDT 24
Peak memory 212304 kb
Host smart-18543a34-f02c-49cb-bf6b-266bec335676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941875684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2941875684
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3558932733
Short name T100
Test name
Test status
Simulation time 1114921953 ps
CPU time 10.57 seconds
Started Jun 26 05:45:53 PM PDT 24
Finished Jun 26 05:46:05 PM PDT 24
Peak memory 213848 kb
Host smart-0a77027e-2950-412e-9583-1249adb5765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558932733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3558932733
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1692845046
Short name T319
Test name
Test status
Simulation time 394021193 ps
CPU time 21.52 seconds
Started Jun 26 05:45:45 PM PDT 24
Finished Jun 26 05:46:07 PM PDT 24
Peak memory 215312 kb
Host smart-ffbbd8e6-e06a-4946-a33e-53515e1912bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692845046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1692845046
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3571676227
Short name T43
Test name
Test status
Simulation time 36932270657 ps
CPU time 328.61 seconds
Started Jun 26 05:45:52 PM PDT 24
Finished Jun 26 05:51:21 PM PDT 24
Peak memory 229196 kb
Host smart-0e61a954-68d7-49b2-853d-adfb594b2e16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571676227 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3571676227
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4033821467
Short name T350
Test name
Test status
Simulation time 2707680218 ps
CPU time 11.7 seconds
Started Jun 26 05:45:43 PM PDT 24
Finished Jun 26 05:45:56 PM PDT 24
Peak memory 211368 kb
Host smart-96f874e1-096b-4d87-ac1d-e5c8d2ef09c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033821467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4033821467
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.919054011
Short name T274
Test name
Test status
Simulation time 22033562399 ps
CPU time 243.16 seconds
Started Jun 26 05:45:55 PM PDT 24
Finished Jun 26 05:49:59 PM PDT 24
Peak memory 233748 kb
Host smart-850223cf-f997-4036-abd4-4a618e923aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919054011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.919054011
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4078559142
Short name T133
Test name
Test status
Simulation time 6598600182 ps
CPU time 29.96 seconds
Started Jun 26 05:45:45 PM PDT 24
Finished Jun 26 05:46:16 PM PDT 24
Peak memory 218588 kb
Host smart-fef140ff-ea66-42cd-b9cd-acacee6298f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078559142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4078559142
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3683629420
Short name T307
Test name
Test status
Simulation time 3165179273 ps
CPU time 14.93 seconds
Started Jun 26 05:45:48 PM PDT 24
Finished Jun 26 05:46:04 PM PDT 24
Peak memory 211368 kb
Host smart-b94ddc14-7b6e-424f-b87b-091d655e64c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3683629420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3683629420
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1119599805
Short name T183
Test name
Test status
Simulation time 190655082 ps
CPU time 10.48 seconds
Started Jun 26 05:45:46 PM PDT 24
Finished Jun 26 05:45:58 PM PDT 24
Peak memory 213876 kb
Host smart-78d495d3-2fbf-4041-9233-d2cb76bec6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119599805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1119599805
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2095506959
Short name T132
Test name
Test status
Simulation time 4231598791 ps
CPU time 35.97 seconds
Started Jun 26 05:45:55 PM PDT 24
Finished Jun 26 05:46:32 PM PDT 24
Peak memory 214012 kb
Host smart-0d77ee74-3ab6-48ab-b28b-6f7adae30b28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095506959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2095506959
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3992195956
Short name T47
Test name
Test status
Simulation time 58809380017 ps
CPU time 3510.97 seconds
Started Jun 26 05:45:48 PM PDT 24
Finished Jun 26 06:44:20 PM PDT 24
Peak memory 236092 kb
Host smart-7dd4c758-0c41-49ec-8d9a-80e55fdd74fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992195956 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3992195956
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.105033142
Short name T234
Test name
Test status
Simulation time 2544391995 ps
CPU time 8.1 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:45:25 PM PDT 24
Peak memory 211244 kb
Host smart-e91417a7-d64d-419c-8651-138c449831fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105033142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.105033142
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.630880708
Short name T29
Test name
Test status
Simulation time 111512105652 ps
CPU time 306.5 seconds
Started Jun 26 05:45:12 PM PDT 24
Finished Jun 26 05:50:22 PM PDT 24
Peak memory 228436 kb
Host smart-76c6a269-d022-445d-b9a5-4f8965222f3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630880708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.630880708
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4162197719
Short name T221
Test name
Test status
Simulation time 2534824339 ps
CPU time 24.89 seconds
Started Jun 26 05:45:14 PM PDT 24
Finished Jun 26 05:45:42 PM PDT 24
Peak memory 212008 kb
Host smart-ed6ede6f-2b9c-4835-946d-23b7f9dc8c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162197719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4162197719
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2059045765
Short name T134
Test name
Test status
Simulation time 1707516156 ps
CPU time 14.26 seconds
Started Jun 26 05:45:10 PM PDT 24
Finished Jun 26 05:45:28 PM PDT 24
Peak memory 211176 kb
Host smart-bf9244f6-2c4f-4326-82e5-df0d973b51bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059045765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2059045765
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2551779267
Short name T24
Test name
Test status
Simulation time 1875875600 ps
CPU time 105.7 seconds
Started Jun 26 05:45:09 PM PDT 24
Finished Jun 26 05:46:56 PM PDT 24
Peak memory 238576 kb
Host smart-3ce8fd00-e4a5-4cc9-98af-a9fc5f30aabe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551779267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2551779267
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1809715562
Short name T128
Test name
Test status
Simulation time 2637680974 ps
CPU time 24 seconds
Started Jun 26 05:45:09 PM PDT 24
Finished Jun 26 05:45:35 PM PDT 24
Peak memory 213424 kb
Host smart-38734445-6fc5-4810-8685-3281ce7e4edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809715562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1809715562
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3788214749
Short name T103
Test name
Test status
Simulation time 1518236345 ps
CPU time 24.37 seconds
Started Jun 26 05:45:09 PM PDT 24
Finished Jun 26 05:45:36 PM PDT 24
Peak memory 216744 kb
Host smart-c83dfe15-1e34-4421-8e79-82eff60428db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788214749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3788214749
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.41717070
Short name T97
Test name
Test status
Simulation time 3043435657 ps
CPU time 9.7 seconds
Started Jun 26 05:45:54 PM PDT 24
Finished Jun 26 05:46:05 PM PDT 24
Peak memory 211276 kb
Host smart-a4176696-4146-4a90-925d-073ff053324e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41717070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.41717070
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3286071859
Short name T220
Test name
Test status
Simulation time 3357628957 ps
CPU time 90.52 seconds
Started Jun 26 05:45:54 PM PDT 24
Finished Jun 26 05:47:26 PM PDT 24
Peak memory 225968 kb
Host smart-a64182ee-6c2f-41fa-9594-eb50e862b34a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286071859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3286071859
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.415891708
Short name T233
Test name
Test status
Simulation time 666540215 ps
CPU time 9.36 seconds
Started Jun 26 05:45:52 PM PDT 24
Finished Jun 26 05:46:02 PM PDT 24
Peak memory 212080 kb
Host smart-85e10239-069c-481a-966f-82c9b45deec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415891708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.415891708
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.29682896
Short name T60
Test name
Test status
Simulation time 2083225488 ps
CPU time 18.03 seconds
Started Jun 26 05:45:52 PM PDT 24
Finished Jun 26 05:46:11 PM PDT 24
Peak memory 211264 kb
Host smart-4c75e6f4-9389-48d3-8dbb-eafdbf36d7b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29682896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.29682896
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1578911333
Short name T361
Test name
Test status
Simulation time 4086389942 ps
CPU time 30.24 seconds
Started Jun 26 05:45:47 PM PDT 24
Finished Jun 26 05:46:19 PM PDT 24
Peak memory 213260 kb
Host smart-ae3d7ffe-a724-4b0f-8cb0-27a5b8256726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578911333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1578911333
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.945882891
Short name T316
Test name
Test status
Simulation time 5267250576 ps
CPU time 20.04 seconds
Started Jun 26 05:45:46 PM PDT 24
Finished Jun 26 05:46:07 PM PDT 24
Peak memory 213836 kb
Host smart-51873097-cbc9-488d-93b9-74f19d4c1c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945882891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.945882891
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3658608347
Short name T359
Test name
Test status
Simulation time 3378112436 ps
CPU time 16.62 seconds
Started Jun 26 05:45:55 PM PDT 24
Finished Jun 26 05:46:13 PM PDT 24
Peak memory 211328 kb
Host smart-6c336654-a96e-488e-b727-96de980b43bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658608347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3658608347
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2077658159
Short name T151
Test name
Test status
Simulation time 1015015922 ps
CPU time 95.15 seconds
Started Jun 26 05:45:56 PM PDT 24
Finished Jun 26 05:47:32 PM PDT 24
Peak memory 236808 kb
Host smart-646e8361-e155-4bff-9cce-6a1308b1424a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077658159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2077658159
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1502653423
Short name T264
Test name
Test status
Simulation time 8145559390 ps
CPU time 23.1 seconds
Started Jun 26 05:45:51 PM PDT 24
Finished Jun 26 05:46:15 PM PDT 24
Peak memory 212484 kb
Host smart-ec130314-66f4-4036-b11d-bff50ff95dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502653423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1502653423
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1525494845
Short name T14
Test name
Test status
Simulation time 5062168388 ps
CPU time 13.65 seconds
Started Jun 26 05:45:54 PM PDT 24
Finished Jun 26 05:46:09 PM PDT 24
Peak memory 211320 kb
Host smart-4200e2a2-d554-45cf-9972-67ff8f3ee535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525494845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1525494845
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.955074894
Short name T207
Test name
Test status
Simulation time 20900333726 ps
CPU time 31.37 seconds
Started Jun 26 05:45:53 PM PDT 24
Finished Jun 26 05:46:26 PM PDT 24
Peak memory 214476 kb
Host smart-064a1dd1-0fa9-4577-8109-a12212d85405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955074894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.955074894
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2834061619
Short name T270
Test name
Test status
Simulation time 3327878572 ps
CPU time 16.52 seconds
Started Jun 26 05:45:51 PM PDT 24
Finished Jun 26 05:46:08 PM PDT 24
Peak memory 212540 kb
Host smart-a971f1a6-6482-416c-9cf3-77abfcc7bf3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834061619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2834061619
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.104235729
Short name T201
Test name
Test status
Simulation time 1750289962 ps
CPU time 14.51 seconds
Started Jun 26 05:45:53 PM PDT 24
Finished Jun 26 05:46:09 PM PDT 24
Peak memory 211288 kb
Host smart-98fd28b0-e0bc-4ff2-a57e-19f8561d29c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104235729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.104235729
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3154227773
Short name T26
Test name
Test status
Simulation time 22055354897 ps
CPU time 203.97 seconds
Started Jun 26 05:45:51 PM PDT 24
Finished Jun 26 05:49:16 PM PDT 24
Peak memory 237784 kb
Host smart-1513405f-55ef-49e8-abeb-75c52c8428b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154227773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3154227773
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3339135483
Short name T236
Test name
Test status
Simulation time 11210655395 ps
CPU time 26.18 seconds
Started Jun 26 05:45:53 PM PDT 24
Finished Jun 26 05:46:20 PM PDT 24
Peak memory 212204 kb
Host smart-f9cc681a-6a94-4ea5-854a-e973fc78d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339135483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3339135483
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2870261676
Short name T153
Test name
Test status
Simulation time 417213250 ps
CPU time 5.49 seconds
Started Jun 26 05:45:55 PM PDT 24
Finished Jun 26 05:46:02 PM PDT 24
Peak memory 211340 kb
Host smart-0e208f38-71b0-4a02-b3ed-496e81c4d279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870261676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2870261676
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1527426092
Short name T176
Test name
Test status
Simulation time 6178427784 ps
CPU time 18.97 seconds
Started Jun 26 05:45:52 PM PDT 24
Finished Jun 26 05:46:11 PM PDT 24
Peak memory 213816 kb
Host smart-1692d606-4180-42aa-9100-ed41f81bd06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527426092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1527426092
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.635145543
Short name T74
Test name
Test status
Simulation time 286150239 ps
CPU time 16.55 seconds
Started Jun 26 05:45:54 PM PDT 24
Finished Jun 26 05:46:12 PM PDT 24
Peak memory 212052 kb
Host smart-0fd7460f-80db-45a4-840c-2f57181c0438
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635145543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.635145543
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2127279958
Short name T45
Test name
Test status
Simulation time 83373218316 ps
CPU time 1604.85 seconds
Started Jun 26 05:45:53 PM PDT 24
Finished Jun 26 06:12:40 PM PDT 24
Peak memory 236088 kb
Host smart-f867c87f-98b7-4e8c-8aa0-36709ccfcb5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127279958 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2127279958
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2123080935
Short name T245
Test name
Test status
Simulation time 515152527 ps
CPU time 5.02 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:46:10 PM PDT 24
Peak memory 211240 kb
Host smart-c6c3a30a-a013-406a-9ee6-2275f97d7a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123080935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2123080935
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3685011608
Short name T250
Test name
Test status
Simulation time 70338676557 ps
CPU time 168.58 seconds
Started Jun 26 05:46:00 PM PDT 24
Finished Jun 26 05:48:51 PM PDT 24
Peak memory 234824 kb
Host smart-d8a9daa7-58c1-4d8b-8668-c91fbf23a5f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685011608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3685011608
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3495569781
Short name T4
Test name
Test status
Simulation time 3872132398 ps
CPU time 30.79 seconds
Started Jun 26 05:45:59 PM PDT 24
Finished Jun 26 05:46:31 PM PDT 24
Peak memory 212476 kb
Host smart-87d44aec-c408-423b-810a-0a5c0f9bf715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495569781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3495569781
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.4240742410
Short name T257
Test name
Test status
Simulation time 11768225711 ps
CPU time 11.39 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:46:16 PM PDT 24
Peak memory 211620 kb
Host smart-c70983b8-e3a6-4248-8070-cebbfa707ba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240742410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.4240742410
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3367169674
Short name T200
Test name
Test status
Simulation time 1661071234 ps
CPU time 20.24 seconds
Started Jun 26 05:45:54 PM PDT 24
Finished Jun 26 05:46:16 PM PDT 24
Peak memory 214048 kb
Host smart-ce606efd-2ccf-4aed-b401-db43361cd4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367169674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3367169674
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3580058016
Short name T262
Test name
Test status
Simulation time 80610865741 ps
CPU time 54.53 seconds
Started Jun 26 05:45:51 PM PDT 24
Finished Jun 26 05:46:47 PM PDT 24
Peak memory 214280 kb
Host smart-d2e284ef-7607-4e7d-8254-1610bc358964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580058016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3580058016
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.829529334
Short name T21
Test name
Test status
Simulation time 39492775777 ps
CPU time 1535.56 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 06:11:40 PM PDT 24
Peak memory 230600 kb
Host smart-95087e54-ea07-4d4e-ab50-400bcbb939e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829529334 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.829529334
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4198410540
Short name T169
Test name
Test status
Simulation time 500650508 ps
CPU time 5.19 seconds
Started Jun 26 05:46:04 PM PDT 24
Finished Jun 26 05:46:12 PM PDT 24
Peak memory 211256 kb
Host smart-942514bd-ed97-4a2b-93c6-5dbb1a4241a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198410540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4198410540
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1652746955
Short name T339
Test name
Test status
Simulation time 26123995326 ps
CPU time 216.39 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 05:49:40 PM PDT 24
Peak memory 224684 kb
Host smart-45822066-2b66-4788-8cc9-f596f881d3c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652746955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1652746955
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4188267524
Short name T230
Test name
Test status
Simulation time 7761561569 ps
CPU time 34.58 seconds
Started Jun 26 05:46:00 PM PDT 24
Finished Jun 26 05:46:36 PM PDT 24
Peak memory 212492 kb
Host smart-fef169ae-10b2-44dc-b312-18acd2968f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188267524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4188267524
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2257935715
Short name T127
Test name
Test status
Simulation time 1171647409 ps
CPU time 12.13 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:46:17 PM PDT 24
Peak memory 211272 kb
Host smart-496affbb-ce8a-4085-bc7e-5cddba64fffa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257935715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2257935715
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.983680742
Short name T79
Test name
Test status
Simulation time 5241463219 ps
CPU time 22.88 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 05:46:27 PM PDT 24
Peak memory 214364 kb
Host smart-deb8918b-4688-4a41-83d9-3478552e687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983680742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.983680742
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2397096068
Short name T198
Test name
Test status
Simulation time 32426913507 ps
CPU time 43.75 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 05:46:47 PM PDT 24
Peak memory 216116 kb
Host smart-593c2447-d687-4783-aefe-b3855586f908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397096068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2397096068
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4167275536
Short name T349
Test name
Test status
Simulation time 62439175923 ps
CPU time 3256.95 seconds
Started Jun 26 05:46:00 PM PDT 24
Finished Jun 26 06:40:18 PM PDT 24
Peak memory 235876 kb
Host smart-c82d6fab-04cb-4766-ac39-af8bd71413cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167275536 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.4167275536
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.348302754
Short name T329
Test name
Test status
Simulation time 6683992416 ps
CPU time 14.86 seconds
Started Jun 26 05:46:04 PM PDT 24
Finished Jun 26 05:46:22 PM PDT 24
Peak memory 211316 kb
Host smart-44cc3025-9d07-4b71-8cbf-0609d0348cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348302754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.348302754
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3430440455
Short name T203
Test name
Test status
Simulation time 7121951769 ps
CPU time 115.63 seconds
Started Jun 26 05:45:59 PM PDT 24
Finished Jun 26 05:47:56 PM PDT 24
Peak memory 237620 kb
Host smart-39bc6299-b3b5-4a4b-b27f-ecf8b1a2c79b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430440455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3430440455
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.516363725
Short name T142
Test name
Test status
Simulation time 173810268 ps
CPU time 9.52 seconds
Started Jun 26 05:46:00 PM PDT 24
Finished Jun 26 05:46:12 PM PDT 24
Peak memory 211892 kb
Host smart-2411d895-3f3b-404b-b77b-b80d80c7ae6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516363725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.516363725
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.237950729
Short name T156
Test name
Test status
Simulation time 3926527761 ps
CPU time 11.59 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 05:46:15 PM PDT 24
Peak memory 211388 kb
Host smart-7ac6f25e-9738-4995-8683-151a8bc94b91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237950729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.237950729
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1880489321
Short name T363
Test name
Test status
Simulation time 2254414365 ps
CPU time 22.64 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:46:28 PM PDT 24
Peak memory 213680 kb
Host smart-4aac1f40-0b43-488b-bb1f-333e3f6c6fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880489321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1880489321
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3248262311
Short name T266
Test name
Test status
Simulation time 665642215 ps
CPU time 38.34 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 05:46:42 PM PDT 24
Peak memory 216092 kb
Host smart-221d778f-d9d1-4b93-ba7c-1aa78b9ae97d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248262311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3248262311
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.640737321
Short name T271
Test name
Test status
Simulation time 175726160108 ps
CPU time 1776.23 seconds
Started Jun 26 05:45:59 PM PDT 24
Finished Jun 26 06:15:37 PM PDT 24
Peak memory 237240 kb
Host smart-e5f2291d-a8e2-49e9-b33e-71145b7d40b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640737321 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.640737321
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3295684731
Short name T18
Test name
Test status
Simulation time 1898060260 ps
CPU time 7.46 seconds
Started Jun 26 05:46:03 PM PDT 24
Finished Jun 26 05:46:13 PM PDT 24
Peak memory 211308 kb
Host smart-2b615e02-3e0e-47ba-8978-ae3f20a592f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295684731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3295684731
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4081550237
Short name T96
Test name
Test status
Simulation time 7149220694 ps
CPU time 84.85 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:47:29 PM PDT 24
Peak memory 224648 kb
Host smart-a9fd696f-c689-4154-9dad-371052f10a4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081550237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4081550237
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2631731829
Short name T235
Test name
Test status
Simulation time 10274502138 ps
CPU time 24.27 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 05:46:28 PM PDT 24
Peak memory 212372 kb
Host smart-b1e10ecf-9322-4d1c-9a03-eda246cc712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631731829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2631731829
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2518461987
Short name T112
Test name
Test status
Simulation time 2440131407 ps
CPU time 9.29 seconds
Started Jun 26 05:46:05 PM PDT 24
Finished Jun 26 05:46:17 PM PDT 24
Peak memory 211344 kb
Host smart-08e37798-6a61-4edf-8a21-6b2f62e05be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518461987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2518461987
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2741285123
Short name T308
Test name
Test status
Simulation time 3511485147 ps
CPU time 29.93 seconds
Started Jun 26 05:46:04 PM PDT 24
Finished Jun 26 05:46:37 PM PDT 24
Peak memory 213380 kb
Host smart-eecaeb18-3d9c-4f51-b550-d923e4e4922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741285123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2741285123
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2132329510
Short name T219
Test name
Test status
Simulation time 1772748470 ps
CPU time 29.14 seconds
Started Jun 26 05:46:00 PM PDT 24
Finished Jun 26 05:46:32 PM PDT 24
Peak memory 214520 kb
Host smart-2b0e33a3-e759-4fb3-8310-e11ae5bd029d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132329510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2132329510
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3509838699
Short name T222
Test name
Test status
Simulation time 1185596275 ps
CPU time 11.8 seconds
Started Jun 26 05:46:03 PM PDT 24
Finished Jun 26 05:46:18 PM PDT 24
Peak memory 211208 kb
Host smart-b67f1a32-d293-4dbc-b93c-196e10179ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509838699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3509838699
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2648393894
Short name T331
Test name
Test status
Simulation time 10979772338 ps
CPU time 183.51 seconds
Started Jun 26 05:46:04 PM PDT 24
Finished Jun 26 05:49:10 PM PDT 24
Peak memory 237812 kb
Host smart-aff14722-6747-40f8-894b-561863ecf05f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648393894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2648393894
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.753520386
Short name T190
Test name
Test status
Simulation time 2928995879 ps
CPU time 15.57 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:46:20 PM PDT 24
Peak memory 211952 kb
Host smart-80a64d9c-76d7-40e8-8142-4ee7136b227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753520386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.753520386
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3611368840
Short name T3
Test name
Test status
Simulation time 3362374289 ps
CPU time 14.69 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 05:46:19 PM PDT 24
Peak memory 211392 kb
Host smart-2374d6c3-14fa-437f-a9d5-e73ed9dfad93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611368840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3611368840
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.4170976478
Short name T242
Test name
Test status
Simulation time 2641948862 ps
CPU time 28.59 seconds
Started Jun 26 05:45:59 PM PDT 24
Finished Jun 26 05:46:29 PM PDT 24
Peak memory 213916 kb
Host smart-a4271a4d-2b84-4c35-b714-b22a97e4ac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170976478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.4170976478
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2443595583
Short name T167
Test name
Test status
Simulation time 960467509 ps
CPU time 21.92 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 05:46:26 PM PDT 24
Peak memory 216020 kb
Host smart-6ab7a00b-f2ca-4b11-b286-006772e860bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443595583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2443595583
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1111563442
Short name T299
Test name
Test status
Simulation time 30886273950 ps
CPU time 343.98 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:51:49 PM PDT 24
Peak memory 225040 kb
Host smart-e656b5da-9f46-4f9b-9211-6bf0dbda851b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111563442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1111563442
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2092842638
Short name T276
Test name
Test status
Simulation time 693528654 ps
CPU time 9.46 seconds
Started Jun 26 05:46:01 PM PDT 24
Finished Jun 26 05:46:13 PM PDT 24
Peak memory 212076 kb
Host smart-ddd5e4f5-f93a-494a-b60e-70d5235d36d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092842638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2092842638
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1284557947
Short name T249
Test name
Test status
Simulation time 1648445916 ps
CPU time 13.04 seconds
Started Jun 26 05:46:05 PM PDT 24
Finished Jun 26 05:46:21 PM PDT 24
Peak memory 211296 kb
Host smart-f21b9993-5c06-449c-abf3-97ca72298937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1284557947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1284557947
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1450240762
Short name T196
Test name
Test status
Simulation time 1233264413 ps
CPU time 17.28 seconds
Started Jun 26 05:46:00 PM PDT 24
Finished Jun 26 05:46:20 PM PDT 24
Peak memory 211780 kb
Host smart-96055063-d35b-4d83-8fbd-a17cfdd9815d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450240762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1450240762
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1913614052
Short name T226
Test name
Test status
Simulation time 1918717940 ps
CPU time 6.11 seconds
Started Jun 26 05:46:12 PM PDT 24
Finished Jun 26 05:46:20 PM PDT 24
Peak memory 211240 kb
Host smart-d7947983-beda-47ac-b166-32015b654398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913614052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1913614052
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.913441971
Short name T31
Test name
Test status
Simulation time 30921549371 ps
CPU time 307.25 seconds
Started Jun 26 05:46:04 PM PDT 24
Finished Jun 26 05:51:14 PM PDT 24
Peak memory 228212 kb
Host smart-1be5bebc-c311-4577-b358-72ded764d8fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913441971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.913441971
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1013903778
Short name T131
Test name
Test status
Simulation time 1157379450 ps
CPU time 16.94 seconds
Started Jun 26 05:46:08 PM PDT 24
Finished Jun 26 05:46:28 PM PDT 24
Peak memory 211928 kb
Host smart-3a7b1317-dc30-43c7-864c-73b25d565124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013903778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1013903778
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3674638035
Short name T213
Test name
Test status
Simulation time 1244998394 ps
CPU time 7.4 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:46:12 PM PDT 24
Peak memory 211272 kb
Host smart-b690d40c-0545-49ba-ac94-2e7d2447537d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674638035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3674638035
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.232351685
Short name T278
Test name
Test status
Simulation time 4572872859 ps
CPU time 16.36 seconds
Started Jun 26 05:46:02 PM PDT 24
Finished Jun 26 05:46:22 PM PDT 24
Peak memory 214440 kb
Host smart-06f3efea-64fc-4cf5-a3a6-007652f7104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232351685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.232351685
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.745844466
Short name T192
Test name
Test status
Simulation time 439933172 ps
CPU time 14.27 seconds
Started Jun 26 05:46:03 PM PDT 24
Finished Jun 26 05:46:20 PM PDT 24
Peak memory 213280 kb
Host smart-42863924-ba62-4506-982a-4ccc5a241736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745844466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.745844466
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4227242417
Short name T148
Test name
Test status
Simulation time 85749215 ps
CPU time 4.23 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:45:28 PM PDT 24
Peak memory 211216 kb
Host smart-e1c3382c-736d-4fad-abe5-d82dd08b3564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227242417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4227242417
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.737385367
Short name T305
Test name
Test status
Simulation time 10002436225 ps
CPU time 143.45 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:47:41 PM PDT 24
Peak memory 237500 kb
Host smart-d43c2f86-d9e7-4d8f-bd70-abf177ee06e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737385367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.737385367
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2985812058
Short name T285
Test name
Test status
Simulation time 692431921 ps
CPU time 9.3 seconds
Started Jun 26 05:45:22 PM PDT 24
Finished Jun 26 05:45:34 PM PDT 24
Peak memory 211964 kb
Host smart-4d49995a-3a43-4018-a5d0-c96eb2f13d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985812058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2985812058
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.92447868
Short name T352
Test name
Test status
Simulation time 2840803416 ps
CPU time 9.26 seconds
Started Jun 26 05:45:13 PM PDT 24
Finished Jun 26 05:45:26 PM PDT 24
Peak memory 211300 kb
Host smart-137f4021-bfd3-4cbe-93a3-da1f4735821a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92447868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.92447868
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1234186872
Short name T2
Test name
Test status
Simulation time 16103813620 ps
CPU time 30.66 seconds
Started Jun 26 05:45:09 PM PDT 24
Finished Jun 26 05:45:42 PM PDT 24
Peak memory 213892 kb
Host smart-565648f2-6bcc-4280-ba93-49d011bf655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234186872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1234186872
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3887720561
Short name T365
Test name
Test status
Simulation time 7048121419 ps
CPU time 27.19 seconds
Started Jun 26 05:45:11 PM PDT 24
Finished Jun 26 05:45:42 PM PDT 24
Peak memory 215728 kb
Host smart-3d8cfd2b-8be0-4d73-a44d-66608f08f733
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887720561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3887720561
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3084617219
Short name T217
Test name
Test status
Simulation time 10637470464 ps
CPU time 16.94 seconds
Started Jun 26 05:46:11 PM PDT 24
Finished Jun 26 05:46:31 PM PDT 24
Peak memory 211560 kb
Host smart-4b2c3c02-b5cc-4a8e-8ca7-100376a6e797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084617219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3084617219
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2434212786
Short name T259
Test name
Test status
Simulation time 9345110097 ps
CPU time 118.79 seconds
Started Jun 26 05:46:07 PM PDT 24
Finished Jun 26 05:48:08 PM PDT 24
Peak memory 235264 kb
Host smart-4006f9d0-b38f-4682-8bce-efce0f05d029
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434212786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2434212786
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2935113160
Short name T355
Test name
Test status
Simulation time 3504192048 ps
CPU time 29.11 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 05:46:42 PM PDT 24
Peak memory 212124 kb
Host smart-0ba3c194-710f-499d-812f-3cef1b5c7a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935113160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2935113160
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.564297964
Short name T282
Test name
Test status
Simulation time 1602895732 ps
CPU time 14.68 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 05:46:27 PM PDT 24
Peak memory 211332 kb
Host smart-270581a9-bdf7-4b1e-be68-bb1e30dae208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564297964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.564297964
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.4115395923
Short name T248
Test name
Test status
Simulation time 183325876 ps
CPU time 10.13 seconds
Started Jun 26 05:46:15 PM PDT 24
Finished Jun 26 05:46:27 PM PDT 24
Peak memory 212996 kb
Host smart-1ad2f804-e342-48a2-ab8a-d791a0f46d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115395923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.4115395923
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4159314900
Short name T78
Test name
Test status
Simulation time 4445402525 ps
CPU time 37.51 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 05:46:50 PM PDT 24
Peak memory 214140 kb
Host smart-f5afa343-1fda-4e7f-9d70-8689d96bdf83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159314900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4159314900
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.938898241
Short name T7
Test name
Test status
Simulation time 1374500664 ps
CPU time 6.6 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 05:46:19 PM PDT 24
Peak memory 211284 kb
Host smart-466346e0-7038-4ca5-a484-30f395ce6e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938898241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.938898241
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2122436369
Short name T41
Test name
Test status
Simulation time 1611214506 ps
CPU time 91.98 seconds
Started Jun 26 05:46:12 PM PDT 24
Finished Jun 26 05:47:46 PM PDT 24
Peak memory 228536 kb
Host smart-fbcd5940-5996-45e5-bbed-7396d87e0c93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122436369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2122436369
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2137888996
Short name T366
Test name
Test status
Simulation time 4780346426 ps
CPU time 17.36 seconds
Started Jun 26 05:46:12 PM PDT 24
Finished Jun 26 05:46:32 PM PDT 24
Peak memory 212204 kb
Host smart-7cb3b3f5-2e26-48cd-8781-9b1a2427eb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137888996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2137888996
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.476048823
Short name T327
Test name
Test status
Simulation time 12270631977 ps
CPU time 17.26 seconds
Started Jun 26 05:46:06 PM PDT 24
Finished Jun 26 05:46:26 PM PDT 24
Peak memory 211332 kb
Host smart-93a6d9d0-4991-4721-8313-20826c15b74c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476048823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.476048823
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1538634126
Short name T362
Test name
Test status
Simulation time 3181559847 ps
CPU time 31.71 seconds
Started Jun 26 05:46:15 PM PDT 24
Finished Jun 26 05:46:49 PM PDT 24
Peak memory 213324 kb
Host smart-c392b222-3b5c-4043-bb28-1e54e0561a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538634126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1538634126
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3417749285
Short name T33
Test name
Test status
Simulation time 592863425 ps
CPU time 13.61 seconds
Started Jun 26 05:47:51 PM PDT 24
Finished Jun 26 05:48:06 PM PDT 24
Peak memory 211096 kb
Host smart-2e0e510f-cd9c-45c3-bc82-a3988730ae4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417749285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3417749285
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2887342122
Short name T309
Test name
Test status
Simulation time 1587876785 ps
CPU time 9.88 seconds
Started Jun 26 05:46:11 PM PDT 24
Finished Jun 26 05:46:24 PM PDT 24
Peak memory 211228 kb
Host smart-eac3349e-2440-44f8-828e-282e52f10921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887342122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2887342122
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.757658970
Short name T194
Test name
Test status
Simulation time 9348641098 ps
CPU time 151.73 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 05:48:44 PM PDT 24
Peak memory 226604 kb
Host smart-52d93695-9263-46d5-87d0-1fadbc73872a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757658970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.757658970
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.861485941
Short name T205
Test name
Test status
Simulation time 6365789773 ps
CPU time 18.6 seconds
Started Jun 26 05:46:11 PM PDT 24
Finished Jun 26 05:46:32 PM PDT 24
Peak memory 212400 kb
Host smart-f328c561-a345-4bad-bb7a-ac1a18f199aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861485941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.861485941
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2717227984
Short name T281
Test name
Test status
Simulation time 99113415 ps
CPU time 5.9 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 05:46:18 PM PDT 24
Peak memory 211320 kb
Host smart-675741c4-99bd-4791-bede-c86ab1cd4b24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2717227984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2717227984
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4183020068
Short name T75
Test name
Test status
Simulation time 14692831242 ps
CPU time 34.56 seconds
Started Jun 26 05:46:11 PM PDT 24
Finished Jun 26 05:46:48 PM PDT 24
Peak memory 214068 kb
Host smart-6b5108d1-dd2b-487b-9903-ab096da71bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183020068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4183020068
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.747049946
Short name T62
Test name
Test status
Simulation time 639228752 ps
CPU time 10.45 seconds
Started Jun 26 05:46:14 PM PDT 24
Finished Jun 26 05:46:27 PM PDT 24
Peak memory 211180 kb
Host smart-3fb87a1d-2a21-4992-a492-39c794b4ea9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747049946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.747049946
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1909352807
Short name T354
Test name
Test status
Simulation time 89114555 ps
CPU time 4.36 seconds
Started Jun 26 05:46:08 PM PDT 24
Finished Jun 26 05:46:16 PM PDT 24
Peak memory 211284 kb
Host smart-7eaf2bd9-f355-4847-a19d-6c3b0e1bd8c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909352807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1909352807
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3281704934
Short name T347
Test name
Test status
Simulation time 13346754079 ps
CPU time 127.24 seconds
Started Jun 26 05:46:11 PM PDT 24
Finished Jun 26 05:48:21 PM PDT 24
Peak memory 237384 kb
Host smart-923f98eb-cf4e-4660-8f34-561f8b7077c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281704934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3281704934
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3506669177
Short name T184
Test name
Test status
Simulation time 7527720017 ps
CPU time 20.84 seconds
Started Jun 26 05:46:12 PM PDT 24
Finished Jun 26 05:46:35 PM PDT 24
Peak memory 211580 kb
Host smart-aaa1f307-f1ac-4e01-9250-7eb0e8616ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506669177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3506669177
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.890412133
Short name T267
Test name
Test status
Simulation time 6606518117 ps
CPU time 14.63 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 05:46:27 PM PDT 24
Peak memory 211412 kb
Host smart-06a710e5-65d7-4e1e-a998-b901a5b8d891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890412133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.890412133
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2231058630
Short name T277
Test name
Test status
Simulation time 3213089481 ps
CPU time 34.86 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 05:46:47 PM PDT 24
Peak memory 213676 kb
Host smart-76e3c001-e0a2-49bd-a463-252645ef5988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231058630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2231058630
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4078598064
Short name T212
Test name
Test status
Simulation time 222486080 ps
CPU time 15.82 seconds
Started Jun 26 05:46:07 PM PDT 24
Finished Jun 26 05:46:25 PM PDT 24
Peak memory 212328 kb
Host smart-d97da37b-79e7-4e65-9592-4ed945fbc022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078598064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4078598064
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1059424404
Short name T181
Test name
Test status
Simulation time 1027866469 ps
CPU time 10.8 seconds
Started Jun 26 05:46:14 PM PDT 24
Finished Jun 26 05:46:27 PM PDT 24
Peak memory 211244 kb
Host smart-92f2e0ef-f3f1-40b3-848a-d4f51e544a67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059424404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1059424404
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2256957614
Short name T364
Test name
Test status
Simulation time 55089890747 ps
CPU time 227.95 seconds
Started Jun 26 05:46:16 PM PDT 24
Finished Jun 26 05:50:06 PM PDT 24
Peak memory 216712 kb
Host smart-f7038fc1-9421-4fe0-8b01-372393344e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256957614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2256957614
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.256833304
Short name T346
Test name
Test status
Simulation time 12117149857 ps
CPU time 28.53 seconds
Started Jun 26 05:46:15 PM PDT 24
Finished Jun 26 05:46:46 PM PDT 24
Peak memory 211320 kb
Host smart-890c1031-45e7-4c0b-a08f-5adec50d8a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256833304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.256833304
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2020574698
Short name T178
Test name
Test status
Simulation time 4835270601 ps
CPU time 12.15 seconds
Started Jun 26 05:46:13 PM PDT 24
Finished Jun 26 05:46:27 PM PDT 24
Peak memory 211360 kb
Host smart-f553dc1e-f91a-410c-b465-ccf0115dcb7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020574698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2020574698
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.357915586
Short name T193
Test name
Test status
Simulation time 454815643 ps
CPU time 13.69 seconds
Started Jun 26 05:46:11 PM PDT 24
Finished Jun 26 05:46:27 PM PDT 24
Peak memory 212600 kb
Host smart-4fdae558-5945-4b02-9e71-5af1226085da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357915586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.357915586
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1811228822
Short name T223
Test name
Test status
Simulation time 7728640496 ps
CPU time 74.74 seconds
Started Jun 26 05:46:09 PM PDT 24
Finished Jun 26 05:47:27 PM PDT 24
Peak memory 216080 kb
Host smart-e52ac7cd-4b35-4d12-bc9c-5d7d73cbf93e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811228822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1811228822
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1779563681
Short name T334
Test name
Test status
Simulation time 593407129 ps
CPU time 4.2 seconds
Started Jun 26 05:46:16 PM PDT 24
Finished Jun 26 05:46:23 PM PDT 24
Peak memory 211288 kb
Host smart-4ea911cd-7d31-444a-931e-f45e9e787de2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779563681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1779563681
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1672134085
Short name T293
Test name
Test status
Simulation time 1621799133 ps
CPU time 102.3 seconds
Started Jun 26 05:46:13 PM PDT 24
Finished Jun 26 05:47:58 PM PDT 24
Peak memory 234180 kb
Host smart-926464ad-90f6-4349-b620-f50a924310f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672134085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1672134085
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2288509072
Short name T173
Test name
Test status
Simulation time 2516914453 ps
CPU time 16.77 seconds
Started Jun 26 05:46:18 PM PDT 24
Finished Jun 26 05:46:36 PM PDT 24
Peak memory 212504 kb
Host smart-6e94a3b5-2d77-4781-9846-d72e5bff1a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288509072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2288509072
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2381655657
Short name T338
Test name
Test status
Simulation time 4305486827 ps
CPU time 16.76 seconds
Started Jun 26 05:46:17 PM PDT 24
Finished Jun 26 05:46:36 PM PDT 24
Peak memory 211332 kb
Host smart-ad00ac2b-b277-4ff8-8f86-3c0f99448360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2381655657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2381655657
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2222748636
Short name T251
Test name
Test status
Simulation time 4946990068 ps
CPU time 27.08 seconds
Started Jun 26 05:46:13 PM PDT 24
Finished Jun 26 05:46:42 PM PDT 24
Peak memory 213260 kb
Host smart-4bfb40cb-27a5-454c-8dd4-7c986799695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222748636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2222748636
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2283499686
Short name T328
Test name
Test status
Simulation time 124129728 ps
CPU time 6.31 seconds
Started Jun 26 05:46:15 PM PDT 24
Finished Jun 26 05:46:23 PM PDT 24
Peak memory 211360 kb
Host smart-544465f4-ab18-4a31-b8ab-a13cb5c14bee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283499686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2283499686
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.4036965563
Short name T46
Test name
Test status
Simulation time 46524263622 ps
CPU time 1938.87 seconds
Started Jun 26 05:46:15 PM PDT 24
Finished Jun 26 06:18:36 PM PDT 24
Peak memory 244060 kb
Host smart-9106a7d2-2008-4ca6-9234-71e3a827769b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036965563 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.4036965563
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1075684789
Short name T55
Test name
Test status
Simulation time 2566868771 ps
CPU time 12.24 seconds
Started Jun 26 05:46:17 PM PDT 24
Finished Jun 26 05:46:31 PM PDT 24
Peak memory 211340 kb
Host smart-a9bb98da-4adb-438b-979d-8076db9d9c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075684789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1075684789
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1704177827
Short name T149
Test name
Test status
Simulation time 40891378085 ps
CPU time 118 seconds
Started Jun 26 05:46:17 PM PDT 24
Finished Jun 26 05:48:17 PM PDT 24
Peak memory 213612 kb
Host smart-53bfc4d1-4471-4f75-90d0-bb85a4fe24fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704177827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1704177827
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.670072472
Short name T296
Test name
Test status
Simulation time 11886556049 ps
CPU time 26.01 seconds
Started Jun 26 05:46:17 PM PDT 24
Finished Jun 26 05:46:45 PM PDT 24
Peak memory 212420 kb
Host smart-e5f83ec4-12ed-48c3-895c-ae4149f81646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670072472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.670072472
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3867739024
Short name T32
Test name
Test status
Simulation time 3926093395 ps
CPU time 10.93 seconds
Started Jun 26 05:46:17 PM PDT 24
Finished Jun 26 05:46:30 PM PDT 24
Peak memory 211332 kb
Host smart-10570353-4f1a-45d5-a5ff-8f04bd05ac92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867739024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3867739024
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.87339415
Short name T113
Test name
Test status
Simulation time 773362449 ps
CPU time 9.88 seconds
Started Jun 26 05:46:15 PM PDT 24
Finished Jun 26 05:46:27 PM PDT 24
Peak memory 213564 kb
Host smart-e6d8c6d3-8a4b-4c52-9e08-3424a1d9fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87339415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.87339415
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1624285260
Short name T174
Test name
Test status
Simulation time 430643275 ps
CPU time 12.71 seconds
Started Jun 26 05:46:16 PM PDT 24
Finished Jun 26 05:46:31 PM PDT 24
Peak memory 213900 kb
Host smart-c4911e71-6ca9-4e27-870c-d92fb33f9d01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624285260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1624285260
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1338668697
Short name T315
Test name
Test status
Simulation time 5071184832 ps
CPU time 11.74 seconds
Started Jun 26 05:46:24 PM PDT 24
Finished Jun 26 05:46:37 PM PDT 24
Peak memory 211344 kb
Host smart-9fd38655-d2f4-4ff0-b518-c3efe0512c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338668697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1338668697
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2175283868
Short name T135
Test name
Test status
Simulation time 57422957923 ps
CPU time 179.96 seconds
Started Jun 26 05:46:14 PM PDT 24
Finished Jun 26 05:49:16 PM PDT 24
Peak memory 237288 kb
Host smart-d029c387-cea6-485b-8dc2-1b4e80a7f9b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175283868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2175283868
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4270016281
Short name T180
Test name
Test status
Simulation time 1323047986 ps
CPU time 18.51 seconds
Started Jun 26 05:46:16 PM PDT 24
Finished Jun 26 05:46:37 PM PDT 24
Peak memory 212140 kb
Host smart-645f2d0a-73b0-4797-b674-9c4aa25f67ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270016281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4270016281
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.386952260
Short name T155
Test name
Test status
Simulation time 1686015274 ps
CPU time 14.4 seconds
Started Jun 26 05:46:14 PM PDT 24
Finished Jun 26 05:46:30 PM PDT 24
Peak memory 211316 kb
Host smart-79253ec1-9219-4b79-ba4c-a63979e831cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386952260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.386952260
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2551684410
Short name T256
Test name
Test status
Simulation time 1401803424 ps
CPU time 12.99 seconds
Started Jun 26 05:46:15 PM PDT 24
Finished Jun 26 05:46:30 PM PDT 24
Peak memory 213816 kb
Host smart-1a401d8e-3148-4585-9ffb-8e187f0222f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551684410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2551684410
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2540142698
Short name T136
Test name
Test status
Simulation time 2298284799 ps
CPU time 25.48 seconds
Started Jun 26 05:46:16 PM PDT 24
Finished Jun 26 05:46:44 PM PDT 24
Peak memory 213732 kb
Host smart-c5728be3-7ae0-4e68-9c19-821be75a6c7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540142698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2540142698
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1604270162
Short name T177
Test name
Test status
Simulation time 1426281760 ps
CPU time 12.29 seconds
Started Jun 26 05:46:22 PM PDT 24
Finished Jun 26 05:46:36 PM PDT 24
Peak memory 211244 kb
Host smart-6680b652-cabc-4fca-beeb-3144df5f970e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604270162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1604270162
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3727787908
Short name T303
Test name
Test status
Simulation time 87740359700 ps
CPU time 209.99 seconds
Started Jun 26 05:46:23 PM PDT 24
Finished Jun 26 05:49:54 PM PDT 24
Peak memory 228656 kb
Host smart-df357cac-48eb-4f5f-93bc-a848e5e87675
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727787908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3727787908
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3419323081
Short name T157
Test name
Test status
Simulation time 16409240575 ps
CPU time 32.9 seconds
Started Jun 26 05:46:22 PM PDT 24
Finished Jun 26 05:46:56 PM PDT 24
Peak memory 212404 kb
Host smart-7596ae8d-2bff-4925-8812-8236d4d56ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419323081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3419323081
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3916845642
Short name T171
Test name
Test status
Simulation time 9097106082 ps
CPU time 14.66 seconds
Started Jun 26 05:46:24 PM PDT 24
Finished Jun 26 05:46:40 PM PDT 24
Peak memory 211392 kb
Host smart-67afac12-c50f-409a-86fd-2f83a1ce8fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916845642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3916845642
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1638953544
Short name T289
Test name
Test status
Simulation time 10490502664 ps
CPU time 26.51 seconds
Started Jun 26 05:46:21 PM PDT 24
Finished Jun 26 05:46:48 PM PDT 24
Peak memory 213792 kb
Host smart-e455aea2-49c7-4bfb-99f4-84af26313320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638953544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1638953544
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.910122138
Short name T326
Test name
Test status
Simulation time 895759700 ps
CPU time 26.4 seconds
Started Jun 26 05:46:23 PM PDT 24
Finished Jun 26 05:46:51 PM PDT 24
Peak memory 213680 kb
Host smart-a5862c52-b402-4bd9-9867-3f2632e3c5a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910122138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.910122138
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1210001212
Short name T254
Test name
Test status
Simulation time 343941945 ps
CPU time 6.74 seconds
Started Jun 26 05:46:24 PM PDT 24
Finished Jun 26 05:46:32 PM PDT 24
Peak memory 211248 kb
Host smart-ed7286e6-c0a9-41fb-b1f5-d7aecb3115c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210001212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1210001212
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1190633829
Short name T263
Test name
Test status
Simulation time 33665386115 ps
CPU time 215.36 seconds
Started Jun 26 05:46:23 PM PDT 24
Finished Jun 26 05:50:00 PM PDT 24
Peak memory 234940 kb
Host smart-935c8fb8-7a6a-483a-8301-35f61874efb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190633829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1190633829
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2635089200
Short name T191
Test name
Test status
Simulation time 172807714 ps
CPU time 9.26 seconds
Started Jun 26 05:46:22 PM PDT 24
Finished Jun 26 05:46:32 PM PDT 24
Peak memory 211892 kb
Host smart-67417816-63c5-454f-98f4-8d1a8ca23195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635089200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2635089200
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1631510497
Short name T139
Test name
Test status
Simulation time 907436982 ps
CPU time 8.26 seconds
Started Jun 26 05:46:23 PM PDT 24
Finished Jun 26 05:46:33 PM PDT 24
Peak memory 211312 kb
Host smart-d09be6f6-f73d-4a2b-927c-bee70a99a5b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1631510497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1631510497
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1804639800
Short name T337
Test name
Test status
Simulation time 552431756 ps
CPU time 11.75 seconds
Started Jun 26 05:46:21 PM PDT 24
Finished Jun 26 05:46:34 PM PDT 24
Peak memory 213484 kb
Host smart-8e57f8e1-6822-4961-a7f8-d345a6903f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804639800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1804639800
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3848842858
Short name T243
Test name
Test status
Simulation time 40290797818 ps
CPU time 79.34 seconds
Started Jun 26 05:46:23 PM PDT 24
Finished Jun 26 05:47:44 PM PDT 24
Peak memory 219368 kb
Host smart-c4acbc65-c658-41bf-a2c4-6d6d1ab06d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848842858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3848842858
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1062918449
Short name T25
Test name
Test status
Simulation time 1986621600 ps
CPU time 15.39 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:45:39 PM PDT 24
Peak memory 211240 kb
Host smart-cc90cba3-03f9-49af-8603-46615c99532d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062918449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1062918449
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1584473022
Short name T204
Test name
Test status
Simulation time 16429595278 ps
CPU time 182 seconds
Started Jun 26 05:45:24 PM PDT 24
Finished Jun 26 05:48:29 PM PDT 24
Peak memory 233728 kb
Host smart-8658db9d-e686-43a8-ba82-dd06ef290014
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584473022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1584473022
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2835585716
Short name T160
Test name
Test status
Simulation time 2471595751 ps
CPU time 24.36 seconds
Started Jun 26 05:45:22 PM PDT 24
Finished Jun 26 05:45:49 PM PDT 24
Peak memory 211916 kb
Host smart-66e4ba17-58b3-4326-bcb7-a46b1a5b7714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835585716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2835585716
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2707917170
Short name T8
Test name
Test status
Simulation time 4144017677 ps
CPU time 12.23 seconds
Started Jun 26 05:45:18 PM PDT 24
Finished Jun 26 05:45:31 PM PDT 24
Peak memory 211380 kb
Host smart-8375a351-f135-4465-b56e-3f096540ac48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707917170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2707917170
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2164622942
Short name T16
Test name
Test status
Simulation time 423117695 ps
CPU time 99.74 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:47:03 PM PDT 24
Peak memory 236444 kb
Host smart-64e50bb7-2a78-40a9-ab97-21f8cf7a5f4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164622942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2164622942
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.581203403
Short name T325
Test name
Test status
Simulation time 26729883835 ps
CPU time 34.31 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:45:58 PM PDT 24
Peak memory 213952 kb
Host smart-3775bb0f-a84d-427c-967e-b276e4ec451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581203403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.581203403
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3522561894
Short name T11
Test name
Test status
Simulation time 12609077667 ps
CPU time 41.69 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:46:06 PM PDT 24
Peak memory 217888 kb
Host smart-dd564199-a3d5-45b6-9079-9f2fa5948d8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522561894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3522561894
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1107610686
Short name T224
Test name
Test status
Simulation time 195310892 ps
CPU time 4.25 seconds
Started Jun 26 05:46:24 PM PDT 24
Finished Jun 26 05:46:30 PM PDT 24
Peak memory 211216 kb
Host smart-73a938fb-0857-4539-b514-b1ca6b62abce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107610686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1107610686
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.836724923
Short name T218
Test name
Test status
Simulation time 3956111845 ps
CPU time 115.86 seconds
Started Jun 26 05:46:23 PM PDT 24
Finished Jun 26 05:48:21 PM PDT 24
Peak memory 213456 kb
Host smart-80ebfbb4-f11a-4a3a-b878-f5add6b5cf04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836724923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.836724923
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.658834949
Short name T310
Test name
Test status
Simulation time 2279711098 ps
CPU time 23.54 seconds
Started Jun 26 05:46:22 PM PDT 24
Finished Jun 26 05:46:46 PM PDT 24
Peak memory 212504 kb
Host smart-1bdda41b-a724-4a81-bdda-96a742f2c900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658834949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.658834949
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1993506582
Short name T324
Test name
Test status
Simulation time 380838484 ps
CPU time 5.65 seconds
Started Jun 26 05:46:23 PM PDT 24
Finished Jun 26 05:46:30 PM PDT 24
Peak memory 211272 kb
Host smart-ffcd6e60-8c89-4802-a328-7819b0a33381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993506582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1993506582
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.813154878
Short name T225
Test name
Test status
Simulation time 2238109163 ps
CPU time 10.19 seconds
Started Jun 26 05:46:24 PM PDT 24
Finished Jun 26 05:46:36 PM PDT 24
Peak memory 213988 kb
Host smart-5cdfc0ae-4618-46c3-ac75-67bc7b2f26c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813154878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.813154878
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2582318577
Short name T227
Test name
Test status
Simulation time 3946291698 ps
CPU time 20.84 seconds
Started Jun 26 05:46:23 PM PDT 24
Finished Jun 26 05:46:45 PM PDT 24
Peak memory 211268 kb
Host smart-bd010091-a774-4bb8-bd55-5f0a8bff564e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582318577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2582318577
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.341609187
Short name T58
Test name
Test status
Simulation time 2790123059 ps
CPU time 13.21 seconds
Started Jun 26 05:46:29 PM PDT 24
Finished Jun 26 05:46:43 PM PDT 24
Peak memory 211280 kb
Host smart-e25c4391-4324-4898-bfbb-590869de42ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341609187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.341609187
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1573356795
Short name T208
Test name
Test status
Simulation time 20679007190 ps
CPU time 217.34 seconds
Started Jun 26 05:46:31 PM PDT 24
Finished Jun 26 05:50:10 PM PDT 24
Peak memory 233024 kb
Host smart-aedb2fe1-fdb7-46d6-a793-cf04bf616e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573356795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1573356795
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1589695941
Short name T195
Test name
Test status
Simulation time 333851037 ps
CPU time 9.33 seconds
Started Jun 26 05:46:27 PM PDT 24
Finished Jun 26 05:46:37 PM PDT 24
Peak memory 212024 kb
Host smart-d3f719f3-f262-409c-b96c-70bed4e1955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589695941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1589695941
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1224162105
Short name T163
Test name
Test status
Simulation time 7272573621 ps
CPU time 16.12 seconds
Started Jun 26 05:46:27 PM PDT 24
Finished Jun 26 05:46:44 PM PDT 24
Peak memory 211348 kb
Host smart-49eab47e-d166-4171-b5b1-549317f6dee5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224162105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1224162105
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4217290725
Short name T287
Test name
Test status
Simulation time 1203610574 ps
CPU time 14.11 seconds
Started Jun 26 05:56:07 PM PDT 24
Finished Jun 26 05:56:34 PM PDT 24
Peak memory 211968 kb
Host smart-81427bf4-4430-4a14-a845-0ad13421d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217290725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4217290725
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2882568354
Short name T80
Test name
Test status
Simulation time 9422211503 ps
CPU time 87.59 seconds
Started Jun 26 05:46:30 PM PDT 24
Finished Jun 26 05:47:59 PM PDT 24
Peak memory 217168 kb
Host smart-9eb8b492-f012-4b71-b2d7-fc36f7c8daa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882568354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2882568354
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1686725579
Short name T244
Test name
Test status
Simulation time 10730244091 ps
CPU time 16.97 seconds
Started Jun 26 05:46:29 PM PDT 24
Finished Jun 26 05:46:46 PM PDT 24
Peak memory 211272 kb
Host smart-fa41379f-b7e3-4c60-8adf-7168012d7ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686725579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1686725579
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3260593767
Short name T15
Test name
Test status
Simulation time 14698134036 ps
CPU time 80.83 seconds
Started Jun 26 05:46:31 PM PDT 24
Finished Jun 26 05:47:53 PM PDT 24
Peak memory 236792 kb
Host smart-62a29c59-0700-4b04-93ee-5039b558ba7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260593767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3260593767
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3970803719
Short name T166
Test name
Test status
Simulation time 168655030 ps
CPU time 9.63 seconds
Started Jun 26 05:46:34 PM PDT 24
Finished Jun 26 05:46:45 PM PDT 24
Peak memory 212064 kb
Host smart-086eef2f-f0e3-45eb-86f7-5a8c2af8c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970803719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3970803719
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2809519651
Short name T292
Test name
Test status
Simulation time 3698513702 ps
CPU time 15.27 seconds
Started Jun 26 05:46:33 PM PDT 24
Finished Jun 26 05:46:49 PM PDT 24
Peak memory 211412 kb
Host smart-4657ee1c-2890-400d-85d1-d5c966ffdc95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809519651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2809519651
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1199448947
Short name T73
Test name
Test status
Simulation time 1547593364 ps
CPU time 21.1 seconds
Started Jun 26 05:46:29 PM PDT 24
Finished Jun 26 05:46:50 PM PDT 24
Peak memory 213204 kb
Host smart-f1ea1b2d-7123-4b62-b097-18f7933b68e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199448947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1199448947
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2624676445
Short name T320
Test name
Test status
Simulation time 3189471509 ps
CPU time 32.77 seconds
Started Jun 26 05:46:32 PM PDT 24
Finished Jun 26 05:47:06 PM PDT 24
Peak memory 213988 kb
Host smart-8046c7dc-d5ae-4183-86a3-23069f1082b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624676445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2624676445
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3689954386
Short name T145
Test name
Test status
Simulation time 619390728 ps
CPU time 8.05 seconds
Started Jun 26 05:46:32 PM PDT 24
Finished Jun 26 05:46:41 PM PDT 24
Peak memory 211504 kb
Host smart-65d087df-143c-4f03-90d1-f24d25228adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689954386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3689954386
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4195436778
Short name T98
Test name
Test status
Simulation time 38171691939 ps
CPU time 348.14 seconds
Started Jun 26 05:46:30 PM PDT 24
Finished Jun 26 05:52:19 PM PDT 24
Peak memory 234508 kb
Host smart-656950a5-a81f-47aa-b9b3-2b1d8316eade
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195436778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4195436778
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3009615597
Short name T22
Test name
Test status
Simulation time 16077544163 ps
CPU time 31.97 seconds
Started Jun 26 05:46:30 PM PDT 24
Finished Jun 26 05:47:04 PM PDT 24
Peak memory 211356 kb
Host smart-1dce549d-1f11-4594-8160-fb73a2ef63ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009615597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3009615597
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1530105652
Short name T168
Test name
Test status
Simulation time 2515789587 ps
CPU time 12.18 seconds
Started Jun 26 05:46:31 PM PDT 24
Finished Jun 26 05:46:45 PM PDT 24
Peak memory 211388 kb
Host smart-821b7061-068c-4026-ad8a-607a7ced75f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530105652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1530105652
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.464004481
Short name T130
Test name
Test status
Simulation time 8778279547 ps
CPU time 33 seconds
Started Jun 26 05:46:30 PM PDT 24
Finished Jun 26 05:47:04 PM PDT 24
Peak memory 213924 kb
Host smart-21e1f23a-ed30-4116-844d-1457cec3b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464004481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.464004481
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.984603663
Short name T290
Test name
Test status
Simulation time 1755366007 ps
CPU time 9.84 seconds
Started Jun 26 05:46:37 PM PDT 24
Finished Jun 26 05:46:48 PM PDT 24
Peak memory 211284 kb
Host smart-f334f95f-b1ef-43db-91ca-e778074dde0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984603663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.984603663
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.587402470
Short name T63
Test name
Test status
Simulation time 41961647271 ps
CPU time 121.42 seconds
Started Jun 26 05:46:37 PM PDT 24
Finished Jun 26 05:48:40 PM PDT 24
Peak memory 212836 kb
Host smart-b670c275-ba79-4fc0-9de2-e44de2fe6ea9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587402470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.587402470
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.899464724
Short name T165
Test name
Test status
Simulation time 1039919532 ps
CPU time 9.46 seconds
Started Jun 26 05:46:34 PM PDT 24
Finished Jun 26 05:46:44 PM PDT 24
Peak memory 212292 kb
Host smart-4a045e64-a780-4966-87f1-8811337099f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899464724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.899464724
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2251221470
Short name T101
Test name
Test status
Simulation time 93015568 ps
CPU time 5.43 seconds
Started Jun 26 05:46:38 PM PDT 24
Finished Jun 26 05:46:44 PM PDT 24
Peak memory 211308 kb
Host smart-bb51a31a-9944-4d10-9292-8debff45900e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251221470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2251221470
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2562516458
Short name T10
Test name
Test status
Simulation time 423905782 ps
CPU time 12.84 seconds
Started Jun 26 05:46:32 PM PDT 24
Finished Jun 26 05:46:46 PM PDT 24
Peak memory 213444 kb
Host smart-e98ab423-a288-4482-be3d-1e2ecb1c578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562516458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2562516458
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.18664665
Short name T210
Test name
Test status
Simulation time 552217971 ps
CPU time 7.76 seconds
Started Jun 26 05:46:38 PM PDT 24
Finished Jun 26 05:46:47 PM PDT 24
Peak memory 211324 kb
Host smart-1e282524-7b0c-4453-abf2-fb908856f691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18664665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.rom_ctrl_stress_all.18664665
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3179548510
Short name T358
Test name
Test status
Simulation time 15108416072 ps
CPU time 17.63 seconds
Started Jun 26 05:46:38 PM PDT 24
Finished Jun 26 05:46:57 PM PDT 24
Peak memory 211324 kb
Host smart-7f831558-c1ed-41ba-9ceb-508eb058925a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179548510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3179548510
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.916942046
Short name T343
Test name
Test status
Simulation time 47321370803 ps
CPU time 34.9 seconds
Started Jun 26 05:46:42 PM PDT 24
Finished Jun 26 05:47:17 PM PDT 24
Peak memory 211244 kb
Host smart-b9383361-a7de-4f52-8f11-335439e82d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916942046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.916942046
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2103693284
Short name T161
Test name
Test status
Simulation time 922357360 ps
CPU time 6.86 seconds
Started Jun 26 05:46:35 PM PDT 24
Finished Jun 26 05:46:42 PM PDT 24
Peak memory 211220 kb
Host smart-d8fdc86b-ae0e-4333-b816-0d3754c60d63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103693284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2103693284
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2048896014
Short name T189
Test name
Test status
Simulation time 3767362580 ps
CPU time 14.93 seconds
Started Jun 26 05:46:37 PM PDT 24
Finished Jun 26 05:46:53 PM PDT 24
Peak memory 214184 kb
Host smart-a2fee952-2930-47c6-9596-6be66a02fd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048896014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2048896014
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.616886711
Short name T269
Test name
Test status
Simulation time 11133793684 ps
CPU time 29.91 seconds
Started Jun 26 05:46:35 PM PDT 24
Finished Jun 26 05:47:06 PM PDT 24
Peak memory 213716 kb
Host smart-1f7bb778-fb8c-4fd8-8976-cb7c3b8271db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616886711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.616886711
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1305633550
Short name T336
Test name
Test status
Simulation time 7845544720 ps
CPU time 16.59 seconds
Started Jun 26 05:46:37 PM PDT 24
Finished Jun 26 05:46:55 PM PDT 24
Peak memory 211368 kb
Host smart-916e7905-5d97-4171-87a7-a6f8eb98e013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305633550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1305633550
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3978484419
Short name T340
Test name
Test status
Simulation time 3133221023 ps
CPU time 99.29 seconds
Started Jun 26 05:46:42 PM PDT 24
Finished Jun 26 05:48:22 PM PDT 24
Peak memory 233696 kb
Host smart-9c902060-bffa-4594-8ebd-b145a8676496
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978484419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3978484419
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1133328319
Short name T297
Test name
Test status
Simulation time 18116098216 ps
CPU time 30.38 seconds
Started Jun 26 05:46:36 PM PDT 24
Finished Jun 26 05:47:07 PM PDT 24
Peak memory 212260 kb
Host smart-90a8587f-0e7a-4f44-a6b3-e24c331a2a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133328319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1133328319
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3110853938
Short name T202
Test name
Test status
Simulation time 3530382467 ps
CPU time 15.39 seconds
Started Jun 26 05:46:34 PM PDT 24
Finished Jun 26 05:46:51 PM PDT 24
Peak memory 211332 kb
Host smart-76b633c5-4947-43b1-9fba-f50cbaeda134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110853938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3110853938
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2930830309
Short name T321
Test name
Test status
Simulation time 7516410697 ps
CPU time 31.29 seconds
Started Jun 26 05:46:38 PM PDT 24
Finished Jun 26 05:47:10 PM PDT 24
Peak memory 214048 kb
Host smart-cc98e697-4195-4b16-af9c-e6853350f0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930830309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2930830309
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.852477391
Short name T351
Test name
Test status
Simulation time 1843427008 ps
CPU time 19.01 seconds
Started Jun 26 05:46:37 PM PDT 24
Finished Jun 26 05:46:57 PM PDT 24
Peak memory 214956 kb
Host smart-e53ca9a0-c97a-42b5-b22f-c1b438e06bb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852477391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.852477391
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3823237337
Short name T20
Test name
Test status
Simulation time 61653282770 ps
CPU time 2666.08 seconds
Started Jun 26 05:46:34 PM PDT 24
Finished Jun 26 06:31:01 PM PDT 24
Peak memory 252216 kb
Host smart-e0965d5e-b397-4b53-a707-03d8b6f9a5b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823237337 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3823237337
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.139224826
Short name T258
Test name
Test status
Simulation time 2788677173 ps
CPU time 12.39 seconds
Started Jun 26 05:46:43 PM PDT 24
Finished Jun 26 05:46:56 PM PDT 24
Peak memory 211288 kb
Host smart-175873be-1ae5-4ac4-ac3d-c3a710294008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139224826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.139224826
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.671438663
Short name T228
Test name
Test status
Simulation time 21124634871 ps
CPU time 142.81 seconds
Started Jun 26 05:46:43 PM PDT 24
Finished Jun 26 05:49:07 PM PDT 24
Peak memory 239896 kb
Host smart-35d7f036-0f35-4e89-950b-56f813df1c1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671438663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.671438663
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1311254305
Short name T146
Test name
Test status
Simulation time 3497862960 ps
CPU time 28.78 seconds
Started Jun 26 05:46:41 PM PDT 24
Finished Jun 26 05:47:10 PM PDT 24
Peak memory 211964 kb
Host smart-46e81e86-12da-441a-a688-78220bfea60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311254305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1311254305
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2102841750
Short name T237
Test name
Test status
Simulation time 404128152 ps
CPU time 5.29 seconds
Started Jun 26 05:46:48 PM PDT 24
Finished Jun 26 05:46:54 PM PDT 24
Peak memory 211352 kb
Host smart-f486fb09-84a6-4413-9b98-765700ca2074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102841750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2102841750
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1444388995
Short name T313
Test name
Test status
Simulation time 2988679503 ps
CPU time 27.36 seconds
Started Jun 26 05:46:34 PM PDT 24
Finished Jun 26 05:47:02 PM PDT 24
Peak memory 213120 kb
Host smart-adfddc9b-99fb-4ff4-b88d-71be1c612a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444388995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1444388995
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2238301375
Short name T240
Test name
Test status
Simulation time 32115692112 ps
CPU time 75.97 seconds
Started Jun 26 05:46:45 PM PDT 24
Finished Jun 26 05:48:02 PM PDT 24
Peak memory 219432 kb
Host smart-a3d364e2-97ef-44f7-82ff-94e9470be9ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238301375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2238301375
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1151335790
Short name T35
Test name
Test status
Simulation time 39929286406 ps
CPU time 441.15 seconds
Started Jun 26 05:46:45 PM PDT 24
Finished Jun 26 05:54:07 PM PDT 24
Peak memory 225268 kb
Host smart-cc6f0e07-32ce-48c9-bc48-2470de92131b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151335790 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1151335790
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1822873928
Short name T312
Test name
Test status
Simulation time 2240825868 ps
CPU time 13.44 seconds
Started Jun 26 05:46:46 PM PDT 24
Finished Jun 26 05:47:01 PM PDT 24
Peak memory 211316 kb
Host smart-4692c294-16f3-42a9-9623-232f5a62954a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822873928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1822873928
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1098588051
Short name T164
Test name
Test status
Simulation time 101989444163 ps
CPU time 222.12 seconds
Started Jun 26 05:46:44 PM PDT 24
Finished Jun 26 05:50:28 PM PDT 24
Peak memory 226112 kb
Host smart-ed724a16-c533-444e-908b-d42d2e60086b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098588051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1098588051
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3410823304
Short name T1
Test name
Test status
Simulation time 3433644717 ps
CPU time 30.37 seconds
Started Jun 26 05:46:45 PM PDT 24
Finished Jun 26 05:47:17 PM PDT 24
Peak memory 211908 kb
Host smart-50dc9994-2e62-499d-b4dd-2d05b20a14f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410823304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3410823304
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4197272800
Short name T170
Test name
Test status
Simulation time 388955404 ps
CPU time 5.75 seconds
Started Jun 26 05:46:44 PM PDT 24
Finished Jun 26 05:46:50 PM PDT 24
Peak memory 211272 kb
Host smart-23b92f16-f486-468c-afb4-fbffdc053f94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197272800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4197272800
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3743896195
Short name T241
Test name
Test status
Simulation time 7722289916 ps
CPU time 35.81 seconds
Started Jun 26 05:46:44 PM PDT 24
Finished Jun 26 05:47:21 PM PDT 24
Peak memory 213620 kb
Host smart-187c2b1e-8775-4438-8659-8e9da9b05ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743896195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3743896195
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3282552979
Short name T302
Test name
Test status
Simulation time 6447918812 ps
CPU time 53.96 seconds
Started Jun 26 05:46:45 PM PDT 24
Finished Jun 26 05:47:40 PM PDT 24
Peak memory 215144 kb
Host smart-96a9bcf9-aaa8-4ad3-88a9-7fb779a431d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282552979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3282552979
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1405667578
Short name T239
Test name
Test status
Simulation time 168371031 ps
CPU time 4.26 seconds
Started Jun 26 05:46:49 PM PDT 24
Finished Jun 26 05:46:54 PM PDT 24
Peak memory 211212 kb
Host smart-85afcce5-04fb-4b31-9406-383453ccca06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405667578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1405667578
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2601526945
Short name T288
Test name
Test status
Simulation time 160631762789 ps
CPU time 435.13 seconds
Started Jun 26 05:46:45 PM PDT 24
Finished Jun 26 05:54:01 PM PDT 24
Peak memory 237820 kb
Host smart-34ab6a07-79ed-45af-ac1f-c70c2e45b8a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601526945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2601526945
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2407037439
Short name T232
Test name
Test status
Simulation time 3684191587 ps
CPU time 30.5 seconds
Started Jun 26 05:46:52 PM PDT 24
Finished Jun 26 05:47:24 PM PDT 24
Peak memory 212036 kb
Host smart-063c44e8-d464-43fe-a36b-1ca64d3d0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407037439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2407037439
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3346542573
Short name T147
Test name
Test status
Simulation time 13953492291 ps
CPU time 14.44 seconds
Started Jun 26 05:46:44 PM PDT 24
Finished Jun 26 05:47:00 PM PDT 24
Peak memory 211356 kb
Host smart-8e86d0ce-3ce7-478f-9d0f-e0e227a34785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3346542573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3346542573
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.480112305
Short name T99
Test name
Test status
Simulation time 37914649106 ps
CPU time 31.63 seconds
Started Jun 26 05:46:42 PM PDT 24
Finished Jun 26 05:47:15 PM PDT 24
Peak memory 214116 kb
Host smart-769e3a7f-e60a-46ac-b586-4be17df4e4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480112305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.480112305
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3212974513
Short name T144
Test name
Test status
Simulation time 9428502496 ps
CPU time 28.13 seconds
Started Jun 26 05:46:42 PM PDT 24
Finished Jun 26 05:47:11 PM PDT 24
Peak memory 214448 kb
Host smart-20ef1755-40a6-4490-9d14-251299fcf26d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212974513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3212974513
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3428067639
Short name T154
Test name
Test status
Simulation time 2388571706 ps
CPU time 11.66 seconds
Started Jun 26 05:45:24 PM PDT 24
Finished Jun 26 05:45:38 PM PDT 24
Peak memory 211328 kb
Host smart-1bc0fb26-1778-4b8d-a4c9-7c7b5c4c0b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428067639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3428067639
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1418367463
Short name T314
Test name
Test status
Simulation time 1470275259 ps
CPU time 98.21 seconds
Started Jun 26 05:45:18 PM PDT 24
Finished Jun 26 05:46:58 PM PDT 24
Peak memory 228616 kb
Host smart-e90ac520-3701-4894-9781-6af7076d0c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418367463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1418367463
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2001884169
Short name T37
Test name
Test status
Simulation time 168596000 ps
CPU time 9.56 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:45:33 PM PDT 24
Peak memory 211840 kb
Host smart-4983e8a6-8d6b-46da-a1bb-a815f8832331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001884169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2001884169
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3350836356
Short name T247
Test name
Test status
Simulation time 1359031065 ps
CPU time 7.47 seconds
Started Jun 26 05:45:24 PM PDT 24
Finished Jun 26 05:45:35 PM PDT 24
Peak memory 211240 kb
Host smart-84b1ee2d-1de2-4e40-b9cd-e8f1ae6b5063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350836356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3350836356
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.483479399
Short name T231
Test name
Test status
Simulation time 8518099849 ps
CPU time 42.5 seconds
Started Jun 26 05:45:25 PM PDT 24
Finished Jun 26 05:46:10 PM PDT 24
Peak memory 213536 kb
Host smart-c5634c1b-b2c6-40cc-9eba-67fb6e0c1f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483479399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.483479399
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3514867696
Short name T141
Test name
Test status
Simulation time 4439241799 ps
CPU time 40.76 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:46:05 PM PDT 24
Peak memory 216232 kb
Host smart-c04d30f5-fe61-4266-999e-7777c3b9ba4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514867696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3514867696
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3762076397
Short name T295
Test name
Test status
Simulation time 57452376659 ps
CPU time 1120.02 seconds
Started Jun 26 05:45:23 PM PDT 24
Finished Jun 26 06:04:06 PM PDT 24
Peak memory 232200 kb
Host smart-2f7b68d3-f3a8-42fa-931c-13cbd8825684
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762076397 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3762076397
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.812516360
Short name T246
Test name
Test status
Simulation time 337996621 ps
CPU time 6.72 seconds
Started Jun 26 05:45:26 PM PDT 24
Finished Jun 26 05:45:35 PM PDT 24
Peak memory 211268 kb
Host smart-a5a04f95-c3dd-4516-909f-d6f57d97ea7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812516360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.812516360
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1563356036
Short name T348
Test name
Test status
Simulation time 35262642861 ps
CPU time 194.62 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:48:38 PM PDT 24
Peak memory 238668 kb
Host smart-f28edf33-022e-4e04-ac65-7918d3d4922f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563356036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1563356036
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2503282976
Short name T206
Test name
Test status
Simulation time 3965300330 ps
CPU time 30.93 seconds
Started Jun 26 05:45:24 PM PDT 24
Finished Jun 26 05:45:58 PM PDT 24
Peak memory 212080 kb
Host smart-6b81c49a-9b69-4d3a-9bf6-e49b9d68706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503282976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2503282976
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3587768239
Short name T152
Test name
Test status
Simulation time 8186406302 ps
CPU time 16.42 seconds
Started Jun 26 05:45:23 PM PDT 24
Finished Jun 26 05:45:42 PM PDT 24
Peak memory 211384 kb
Host smart-9442bed1-bc67-48e4-88d6-192edfb6c49e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3587768239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3587768239
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1756766896
Short name T306
Test name
Test status
Simulation time 4711076215 ps
CPU time 18.76 seconds
Started Jun 26 05:45:19 PM PDT 24
Finished Jun 26 05:45:39 PM PDT 24
Peak memory 213992 kb
Host smart-a91fbfba-3e24-46f8-b128-3753b95f9b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756766896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1756766896
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2161203386
Short name T211
Test name
Test status
Simulation time 103185478 ps
CPU time 8.41 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:45:31 PM PDT 24
Peak memory 211232 kb
Host smart-6965eec1-29ae-4270-82ed-54d1199fbeff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161203386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2161203386
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1928865956
Short name T56
Test name
Test status
Simulation time 1382402141 ps
CPU time 4.17 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:45:28 PM PDT 24
Peak memory 211276 kb
Host smart-b82a4987-9a28-4530-9694-b3259247b2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928865956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1928865956
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1121510997
Short name T284
Test name
Test status
Simulation time 77852941757 ps
CPU time 301.99 seconds
Started Jun 26 05:45:19 PM PDT 24
Finished Jun 26 05:50:23 PM PDT 24
Peak memory 238824 kb
Host smart-ee999180-7479-40a8-be02-96d77fc902d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121510997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1121510997
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3655115027
Short name T137
Test name
Test status
Simulation time 2739513423 ps
CPU time 26.17 seconds
Started Jun 26 05:45:22 PM PDT 24
Finished Jun 26 05:45:51 PM PDT 24
Peak memory 211932 kb
Host smart-b097fded-47ab-420a-a9fd-9f7950a26b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655115027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3655115027
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.918660684
Short name T260
Test name
Test status
Simulation time 191073515 ps
CPU time 5.35 seconds
Started Jun 26 05:45:20 PM PDT 24
Finished Jun 26 05:45:28 PM PDT 24
Peak memory 211332 kb
Host smart-a5c015dc-48f9-4e8c-b297-ab65507302b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918660684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.918660684
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2222257013
Short name T150
Test name
Test status
Simulation time 9586910533 ps
CPU time 26.54 seconds
Started Jun 26 05:45:26 PM PDT 24
Finished Jun 26 05:45:55 PM PDT 24
Peak memory 214280 kb
Host smart-1a2800d0-83b0-4d2e-bda3-05311a080387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222257013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2222257013
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.141448293
Short name T322
Test name
Test status
Simulation time 4731009099 ps
CPU time 63.66 seconds
Started Jun 26 05:45:23 PM PDT 24
Finished Jun 26 05:46:29 PM PDT 24
Peak memory 216268 kb
Host smart-b5ef5313-2731-4066-87d8-421c5029c70e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141448293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.141448293
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.18101810
Short name T268
Test name
Test status
Simulation time 7621065989 ps
CPU time 16.35 seconds
Started Jun 26 05:45:18 PM PDT 24
Finished Jun 26 05:45:36 PM PDT 24
Peak memory 211344 kb
Host smart-431f818a-4d03-466f-900a-460f9ce7ba12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18101810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.18101810
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3989013710
Short name T28
Test name
Test status
Simulation time 171211747407 ps
CPU time 348.87 seconds
Started Jun 26 05:45:21 PM PDT 24
Finished Jun 26 05:51:13 PM PDT 24
Peak memory 225144 kb
Host smart-5104d7b1-0b8e-45ca-ab39-852e356526ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989013710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3989013710
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3651681053
Short name T39
Test name
Test status
Simulation time 13008025967 ps
CPU time 29.5 seconds
Started Jun 26 05:45:19 PM PDT 24
Finished Jun 26 05:45:51 PM PDT 24
Peak memory 212208 kb
Host smart-5396ddd3-20ef-4c84-9b0c-fd13f87b79da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651681053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3651681053
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3998765739
Short name T356
Test name
Test status
Simulation time 1030136601 ps
CPU time 7.25 seconds
Started Jun 26 05:45:23 PM PDT 24
Finished Jun 26 05:45:33 PM PDT 24
Peak memory 211324 kb
Host smart-31466749-7f46-42bb-a645-487a18128591
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998765739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3998765739
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.327512145
Short name T77
Test name
Test status
Simulation time 7039800277 ps
CPU time 38.2 seconds
Started Jun 26 05:45:23 PM PDT 24
Finished Jun 26 05:46:04 PM PDT 24
Peak memory 213004 kb
Host smart-08b1d591-1b2b-4e59-8903-9b9ae2bd065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327512145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.327512145
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2111619122
Short name T280
Test name
Test status
Simulation time 302022159 ps
CPU time 15.2 seconds
Started Jun 26 05:45:20 PM PDT 24
Finished Jun 26 05:45:38 PM PDT 24
Peak memory 214956 kb
Host smart-1dac7ddc-6406-4108-a4cf-f615e4ddf8a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111619122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2111619122
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4144619186
Short name T291
Test name
Test status
Simulation time 16304112079 ps
CPU time 15.03 seconds
Started Jun 26 05:45:22 PM PDT 24
Finished Jun 26 05:45:40 PM PDT 24
Peak memory 211272 kb
Host smart-895e6257-1a62-4a39-8bf4-fa37960aa0d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144619186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4144619186
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1417310371
Short name T286
Test name
Test status
Simulation time 29371927954 ps
CPU time 298.49 seconds
Started Jun 26 05:45:22 PM PDT 24
Finished Jun 26 05:50:23 PM PDT 24
Peak memory 233788 kb
Host smart-f4130b89-2596-42fa-8a7c-4a95e652bafd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417310371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1417310371
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1292299244
Short name T38
Test name
Test status
Simulation time 168585585 ps
CPU time 9.75 seconds
Started Jun 26 05:45:24 PM PDT 24
Finished Jun 26 05:45:37 PM PDT 24
Peak memory 211980 kb
Host smart-d85f794b-4270-4ec4-9308-47fc2a4ed4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292299244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1292299244
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4138292879
Short name T342
Test name
Test status
Simulation time 4131156785 ps
CPU time 10.5 seconds
Started Jun 26 05:45:19 PM PDT 24
Finished Jun 26 05:45:32 PM PDT 24
Peak memory 211332 kb
Host smart-d6acfbbd-57b1-4e8b-a168-ec3d13848bde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138292879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4138292879
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1153768191
Short name T283
Test name
Test status
Simulation time 187495593 ps
CPU time 10.19 seconds
Started Jun 26 05:45:23 PM PDT 24
Finished Jun 26 05:45:36 PM PDT 24
Peak memory 213844 kb
Host smart-2f2cda24-4d85-4d36-afde-c98fbab7fac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153768191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1153768191
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2107677269
Short name T76
Test name
Test status
Simulation time 2956880110 ps
CPU time 35.59 seconds
Started Jun 26 05:45:18 PM PDT 24
Finished Jun 26 05:45:55 PM PDT 24
Peak memory 214228 kb
Host smart-0824e439-04a5-432b-84dc-a4a516f25dad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107677269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2107677269
Directory /workspace/9.rom_ctrl_stress_all/latest
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