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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.51 96.89 92.56 97.67 100.00 98.97 97.45 99.07


Total test records in report: 467
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T301 /workspace/coverage/default/28.rom_ctrl_stress_all.4144854340 Jun 27 06:58:45 PM PDT 24 Jun 27 06:59:10 PM PDT 24 2902473049 ps
T302 /workspace/coverage/default/33.rom_ctrl_smoke.85406021 Jun 27 06:59:23 PM PDT 24 Jun 27 06:59:50 PM PDT 24 25977408688 ps
T126 /workspace/coverage/default/8.rom_ctrl_stress_all.3213626845 Jun 27 06:57:17 PM PDT 24 Jun 27 06:58:07 PM PDT 24 7544326829 ps
T303 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4000911173 Jun 27 06:59:23 PM PDT 24 Jun 27 06:59:43 PM PDT 24 1444501520 ps
T304 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3932484947 Jun 27 06:59:59 PM PDT 24 Jun 27 07:00:24 PM PDT 24 9718018943 ps
T305 /workspace/coverage/default/14.rom_ctrl_smoke.3443797581 Jun 27 06:57:42 PM PDT 24 Jun 27 06:58:08 PM PDT 24 3638899052 ps
T306 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1485863945 Jun 27 06:58:27 PM PDT 24 Jun 27 06:58:41 PM PDT 24 1056816103 ps
T307 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.971666256 Jun 27 06:58:00 PM PDT 24 Jun 27 06:58:14 PM PDT 24 1159440748 ps
T308 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2806024688 Jun 27 06:59:54 PM PDT 24 Jun 27 07:00:10 PM PDT 24 1746640866 ps
T309 /workspace/coverage/default/8.rom_ctrl_smoke.969603913 Jun 27 06:57:15 PM PDT 24 Jun 27 06:57:45 PM PDT 24 29846569459 ps
T310 /workspace/coverage/default/0.rom_ctrl_alert_test.1539275707 Jun 27 06:57:00 PM PDT 24 Jun 27 06:57:08 PM PDT 24 739764865 ps
T311 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2916642116 Jun 27 06:59:53 PM PDT 24 Jun 27 07:00:24 PM PDT 24 3968890840 ps
T312 /workspace/coverage/default/36.rom_ctrl_alert_test.2916868085 Jun 27 06:59:27 PM PDT 24 Jun 27 06:59:39 PM PDT 24 4242711673 ps
T313 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.87400109 Jun 27 06:58:43 PM PDT 24 Jun 27 06:59:19 PM PDT 24 20831186775 ps
T314 /workspace/coverage/default/6.rom_ctrl_alert_test.1155726451 Jun 27 06:57:19 PM PDT 24 Jun 27 06:57:27 PM PDT 24 384444039 ps
T315 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1735955964 Jun 27 06:57:45 PM PDT 24 Jun 27 06:58:20 PM PDT 24 3933769837 ps
T316 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2822270379 Jun 27 06:59:25 PM PDT 24 Jun 27 07:27:50 PM PDT 24 29245035682 ps
T317 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4001124313 Jun 27 06:59:23 PM PDT 24 Jun 27 06:59:38 PM PDT 24 2986362878 ps
T318 /workspace/coverage/default/37.rom_ctrl_smoke.1692330904 Jun 27 06:59:25 PM PDT 24 Jun 27 06:59:56 PM PDT 24 31222122813 ps
T319 /workspace/coverage/default/13.rom_ctrl_alert_test.3186335592 Jun 27 06:57:45 PM PDT 24 Jun 27 06:57:58 PM PDT 24 2577068911 ps
T320 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.576999650 Jun 27 06:59:04 PM PDT 24 Jun 27 06:59:18 PM PDT 24 7689072984 ps
T321 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2043627693 Jun 27 06:59:38 PM PDT 24 Jun 27 07:02:13 PM PDT 24 11767102121 ps
T322 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3147775080 Jun 27 06:58:30 PM PDT 24 Jun 27 06:58:42 PM PDT 24 798378103 ps
T45 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.662114505 Jun 27 06:59:38 PM PDT 24 Jun 27 07:00:04 PM PDT 24 2268665380 ps
T323 /workspace/coverage/default/19.rom_ctrl_alert_test.49401700 Jun 27 06:58:16 PM PDT 24 Jun 27 06:58:29 PM PDT 24 5719945777 ps
T324 /workspace/coverage/default/4.rom_ctrl_smoke.198909709 Jun 27 06:57:03 PM PDT 24 Jun 27 06:57:43 PM PDT 24 57339108125 ps
T325 /workspace/coverage/default/13.rom_ctrl_stress_all.2471707012 Jun 27 06:57:42 PM PDT 24 Jun 27 06:58:23 PM PDT 24 26739235494 ps
T326 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1874567078 Jun 27 06:59:37 PM PDT 24 Jun 27 06:59:51 PM PDT 24 7585623305 ps
T327 /workspace/coverage/default/15.rom_ctrl_alert_test.4115503013 Jun 27 06:58:01 PM PDT 24 Jun 27 06:58:14 PM PDT 24 1280766545 ps
T328 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1758951332 Jun 27 06:58:45 PM PDT 24 Jun 27 07:03:32 PM PDT 24 28433742591 ps
T329 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.432807050 Jun 27 06:58:44 PM PDT 24 Jun 27 06:59:00 PM PDT 24 20446723823 ps
T330 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2891743731 Jun 27 06:59:04 PM PDT 24 Jun 27 07:16:04 PM PDT 24 26456425350 ps
T331 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.4033248272 Jun 27 06:58:15 PM PDT 24 Jun 27 07:10:50 PM PDT 24 29913945480 ps
T332 /workspace/coverage/default/42.rom_ctrl_alert_test.763904598 Jun 27 06:59:41 PM PDT 24 Jun 27 06:59:58 PM PDT 24 2394471750 ps
T333 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.56290991 Jun 27 07:00:09 PM PDT 24 Jun 27 07:02:42 PM PDT 24 26270813507 ps
T334 /workspace/coverage/default/5.rom_ctrl_alert_test.1820664147 Jun 27 06:57:15 PM PDT 24 Jun 27 06:57:26 PM PDT 24 3324992966 ps
T335 /workspace/coverage/default/21.rom_ctrl_stress_all.4066851958 Jun 27 06:58:33 PM PDT 24 Jun 27 06:59:19 PM PDT 24 44717234599 ps
T336 /workspace/coverage/default/48.rom_ctrl_stress_all.1879145097 Jun 27 06:59:50 PM PDT 24 Jun 27 07:00:27 PM PDT 24 17785059085 ps
T337 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2960544318 Jun 27 06:57:18 PM PDT 24 Jun 27 06:57:25 PM PDT 24 469003555 ps
T338 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2032492632 Jun 27 06:59:42 PM PDT 24 Jun 27 06:59:58 PM PDT 24 1819492398 ps
T339 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.111750721 Jun 27 06:57:14 PM PDT 24 Jun 27 06:57:20 PM PDT 24 1017869526 ps
T340 /workspace/coverage/default/23.rom_ctrl_alert_test.3805930577 Jun 27 06:58:30 PM PDT 24 Jun 27 06:58:41 PM PDT 24 2924306271 ps
T341 /workspace/coverage/default/10.rom_ctrl_alert_test.3649046808 Jun 27 06:57:29 PM PDT 24 Jun 27 06:57:41 PM PDT 24 2592196854 ps
T342 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1922068878 Jun 27 06:59:39 PM PDT 24 Jun 27 06:59:59 PM PDT 24 7568686984 ps
T343 /workspace/coverage/default/2.rom_ctrl_alert_test.3284570298 Jun 27 06:57:00 PM PDT 24 Jun 27 06:57:10 PM PDT 24 1880600755 ps
T344 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3619717445 Jun 27 06:59:05 PM PDT 24 Jun 27 06:59:24 PM PDT 24 9202570219 ps
T345 /workspace/coverage/default/24.rom_ctrl_alert_test.3006434647 Jun 27 06:58:32 PM PDT 24 Jun 27 06:58:46 PM PDT 24 1312003695 ps
T346 /workspace/coverage/default/29.rom_ctrl_stress_all.4143867542 Jun 27 06:59:04 PM PDT 24 Jun 27 07:00:21 PM PDT 24 30891807696 ps
T347 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3411062154 Jun 27 06:59:24 PM PDT 24 Jun 27 06:59:43 PM PDT 24 6120422133 ps
T348 /workspace/coverage/default/3.rom_ctrl_smoke.2428026088 Jun 27 06:57:01 PM PDT 24 Jun 27 06:57:13 PM PDT 24 755632909 ps
T349 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2435222777 Jun 27 06:57:18 PM PDT 24 Jun 27 07:01:34 PM PDT 24 53092576703 ps
T350 /workspace/coverage/default/7.rom_ctrl_smoke.3198489686 Jun 27 06:57:17 PM PDT 24 Jun 27 06:57:42 PM PDT 24 7650757784 ps
T351 /workspace/coverage/default/45.rom_ctrl_alert_test.2137635640 Jun 27 06:59:50 PM PDT 24 Jun 27 07:00:03 PM PDT 24 2392911375 ps
T352 /workspace/coverage/default/17.rom_ctrl_stress_all.3300229438 Jun 27 06:58:16 PM PDT 24 Jun 27 06:58:34 PM PDT 24 15029003106 ps
T353 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.50510439 Jun 27 06:58:16 PM PDT 24 Jun 27 07:00:55 PM PDT 24 309029748724 ps
T24 /workspace/coverage/default/0.rom_ctrl_sec_cm.3720816503 Jun 27 06:57:01 PM PDT 24 Jun 27 06:58:55 PM PDT 24 8818525963 ps
T354 /workspace/coverage/default/9.rom_ctrl_stress_all.1322805666 Jun 27 06:57:15 PM PDT 24 Jun 27 06:58:53 PM PDT 24 64295197520 ps
T355 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.214317335 Jun 27 06:59:51 PM PDT 24 Jun 27 08:33:32 PM PDT 24 319430875058 ps
T356 /workspace/coverage/default/12.rom_ctrl_stress_all.1550701296 Jun 27 06:57:42 PM PDT 24 Jun 27 06:59:07 PM PDT 24 16783991517 ps
T357 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3802340711 Jun 27 06:57:59 PM PDT 24 Jun 27 06:58:17 PM PDT 24 2073837305 ps
T358 /workspace/coverage/default/20.rom_ctrl_smoke.428085286 Jun 27 06:58:16 PM PDT 24 Jun 27 06:58:48 PM PDT 24 3500777832 ps
T359 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4161327157 Jun 27 06:59:39 PM PDT 24 Jun 27 07:07:06 PM PDT 24 43162777697 ps
T360 /workspace/coverage/default/6.rom_ctrl_stress_all.2804586777 Jun 27 06:57:21 PM PDT 24 Jun 27 06:57:50 PM PDT 24 6379143290 ps
T361 /workspace/coverage/default/41.rom_ctrl_smoke.62444105 Jun 27 06:59:39 PM PDT 24 Jun 27 07:00:06 PM PDT 24 11371919381 ps
T362 /workspace/coverage/default/41.rom_ctrl_stress_all.917097807 Jun 27 06:59:39 PM PDT 24 Jun 27 06:59:58 PM PDT 24 480191072 ps
T363 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3467765464 Jun 27 06:58:44 PM PDT 24 Jun 27 06:58:56 PM PDT 24 617106637 ps
T364 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3289605561 Jun 27 06:57:44 PM PDT 24 Jun 27 09:25:04 PM PDT 24 77267874393 ps
T365 /workspace/coverage/default/0.rom_ctrl_stress_all.4043574698 Jun 27 06:56:41 PM PDT 24 Jun 27 06:57:23 PM PDT 24 58943746781 ps
T366 /workspace/coverage/default/1.rom_ctrl_stress_all.3161238770 Jun 27 06:57:00 PM PDT 24 Jun 27 06:57:32 PM PDT 24 7670694651 ps
T367 /workspace/coverage/default/9.rom_ctrl_alert_test.2873709071 Jun 27 06:57:27 PM PDT 24 Jun 27 06:57:41 PM PDT 24 1382872628 ps
T368 /workspace/coverage/default/29.rom_ctrl_alert_test.2672045767 Jun 27 06:59:06 PM PDT 24 Jun 27 06:59:19 PM PDT 24 23918519452 ps
T369 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3765702274 Jun 27 07:00:08 PM PDT 24 Jun 27 07:00:34 PM PDT 24 2506613668 ps
T55 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2371348527 Jun 27 07:01:19 PM PDT 24 Jun 27 07:01:27 PM PDT 24 103584907 ps
T52 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2828573539 Jun 27 07:01:17 PM PDT 24 Jun 27 07:02:01 PM PDT 24 3703358281 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3831198538 Jun 27 07:00:13 PM PDT 24 Jun 27 07:00:30 PM PDT 24 21175183937 ps
T56 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4285097272 Jun 27 07:00:41 PM PDT 24 Jun 27 07:01:09 PM PDT 24 5388075429 ps
T61 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3741272691 Jun 27 07:00:41 PM PDT 24 Jun 27 07:01:43 PM PDT 24 7221720819 ps
T53 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2197813150 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:36 PM PDT 24 987823191 ps
T62 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4239797898 Jun 27 07:00:59 PM PDT 24 Jun 27 07:01:07 PM PDT 24 305239109 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2316411512 Jun 27 07:00:22 PM PDT 24 Jun 27 07:00:36 PM PDT 24 22752849194 ps
T107 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3650819071 Jun 27 07:00:41 PM PDT 24 Jun 27 07:01:30 PM PDT 24 19070117596 ps
T63 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.98706920 Jun 27 07:00:21 PM PDT 24 Jun 27 07:01:12 PM PDT 24 5269266668 ps
T54 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1709668550 Jun 27 07:00:26 PM PDT 24 Jun 27 07:01:09 PM PDT 24 2268627523 ps
T119 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1710189964 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:38 PM PDT 24 330480136 ps
T98 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2252448098 Jun 27 07:00:58 PM PDT 24 Jun 27 07:02:41 PM PDT 24 39978000969 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2011406146 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:53 PM PDT 24 2278481442 ps
T99 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2574883807 Jun 27 07:01:16 PM PDT 24 Jun 27 07:01:32 PM PDT 24 11538573764 ps
T372 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1492963763 Jun 27 07:00:59 PM PDT 24 Jun 27 07:01:14 PM PDT 24 21330362131 ps
T64 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2454012010 Jun 27 07:00:26 PM PDT 24 Jun 27 07:00:41 PM PDT 24 1680771378 ps
T373 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2094861506 Jun 27 07:01:18 PM PDT 24 Jun 27 07:01:27 PM PDT 24 197204129 ps
T374 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1006413092 Jun 27 07:00:22 PM PDT 24 Jun 27 07:00:32 PM PDT 24 1558933372 ps
T116 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2941962757 Jun 27 07:00:57 PM PDT 24 Jun 27 07:02:07 PM PDT 24 2735262196 ps
T65 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.744803126 Jun 27 07:00:40 PM PDT 24 Jun 27 07:00:54 PM PDT 24 6774620214 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1770504706 Jun 27 07:00:08 PM PDT 24 Jun 27 07:00:28 PM PDT 24 1491691918 ps
T376 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2586335384 Jun 27 07:00:59 PM PDT 24 Jun 27 07:01:13 PM PDT 24 1524034176 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1438381962 Jun 27 07:01:18 PM PDT 24 Jun 27 07:03:04 PM PDT 24 91766916267 ps
T115 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2531787458 Jun 27 07:00:07 PM PDT 24 Jun 27 07:01:18 PM PDT 24 411639092 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.528405731 Jun 27 07:01:07 PM PDT 24 Jun 27 07:01:16 PM PDT 24 300041745 ps
T100 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1120778145 Jun 27 07:01:17 PM PDT 24 Jun 27 07:01:34 PM PDT 24 2463375149 ps
T378 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.694477228 Jun 27 07:00:41 PM PDT 24 Jun 27 07:00:47 PM PDT 24 349777907 ps
T379 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.431342666 Jun 27 07:01:01 PM PDT 24 Jun 27 07:01:17 PM PDT 24 3689919506 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2796534738 Jun 27 07:01:17 PM PDT 24 Jun 27 07:01:35 PM PDT 24 8578351736 ps
T380 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1834131430 Jun 27 07:01:17 PM PDT 24 Jun 27 07:01:34 PM PDT 24 938048223 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4029576931 Jun 27 07:00:07 PM PDT 24 Jun 27 07:00:17 PM PDT 24 592648328 ps
T120 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.274012669 Jun 27 07:00:42 PM PDT 24 Jun 27 07:01:21 PM PDT 24 7205006758 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.897787498 Jun 27 07:00:44 PM PDT 24 Jun 27 07:01:02 PM PDT 24 2091364892 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.527555695 Jun 27 07:00:12 PM PDT 24 Jun 27 07:00:30 PM PDT 24 1961680223 ps
T68 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.570543219 Jun 27 07:00:59 PM PDT 24 Jun 27 07:01:42 PM PDT 24 2326922855 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2985373898 Jun 27 07:00:07 PM PDT 24 Jun 27 07:00:24 PM PDT 24 16422235529 ps
T69 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4119824001 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:03 PM PDT 24 168085194 ps
T101 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.238961590 Jun 27 07:00:57 PM PDT 24 Jun 27 07:01:10 PM PDT 24 21116742626 ps
T121 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1578548363 Jun 27 07:01:01 PM PDT 24 Jun 27 07:01:49 PM PDT 24 2144788543 ps
T113 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2675480696 Jun 27 07:00:41 PM PDT 24 Jun 27 07:01:10 PM PDT 24 2154971328 ps
T385 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1370484838 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:07 PM PDT 24 85486469 ps
T386 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4135889710 Jun 27 07:01:19 PM PDT 24 Jun 27 07:01:38 PM PDT 24 8850023069 ps
T77 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1872730528 Jun 27 07:00:43 PM PDT 24 Jun 27 07:02:20 PM PDT 24 12703973202 ps
T387 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.443021028 Jun 27 07:01:16 PM PDT 24 Jun 27 07:01:25 PM PDT 24 86328383 ps
T388 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1615858418 Jun 27 07:01:19 PM PDT 24 Jun 27 07:01:32 PM PDT 24 2148014877 ps
T389 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2088344519 Jun 27 07:01:01 PM PDT 24 Jun 27 07:01:07 PM PDT 24 261433863 ps
T390 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3322894893 Jun 27 07:01:17 PM PDT 24 Jun 27 07:01:36 PM PDT 24 1873824867 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2678603372 Jun 27 07:00:43 PM PDT 24 Jun 27 07:01:05 PM PDT 24 12022530125 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.77294290 Jun 27 07:01:17 PM PDT 24 Jun 27 07:01:32 PM PDT 24 5240479125 ps
T102 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1945583548 Jun 27 07:00:56 PM PDT 24 Jun 27 07:01:05 PM PDT 24 476598564 ps
T393 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.319964821 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:57 PM PDT 24 28765064276 ps
T394 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2760349054 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:10 PM PDT 24 790476485 ps
T395 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2814684711 Jun 27 07:01:17 PM PDT 24 Jun 27 07:02:09 PM PDT 24 5120707764 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.190772432 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:49 PM PDT 24 104826540 ps
T103 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2939346004 Jun 27 07:00:43 PM PDT 24 Jun 27 07:00:49 PM PDT 24 333504272 ps
T397 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.78903721 Jun 27 07:00:41 PM PDT 24 Jun 27 07:01:29 PM PDT 24 8126407073 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2428271422 Jun 27 07:00:07 PM PDT 24 Jun 27 07:00:20 PM PDT 24 4741411818 ps
T398 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2028106727 Jun 27 07:01:19 PM PDT 24 Jun 27 07:01:29 PM PDT 24 637768617 ps
T78 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.650605357 Jun 27 07:01:06 PM PDT 24 Jun 27 07:01:23 PM PDT 24 6689000241 ps
T399 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.760571609 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:05 PM PDT 24 134683870 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2912288581 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:33 PM PDT 24 891165464 ps
T401 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.953661698 Jun 27 07:00:41 PM PDT 24 Jun 27 07:01:29 PM PDT 24 1734119528 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1422306170 Jun 27 07:00:24 PM PDT 24 Jun 27 07:00:43 PM PDT 24 4492156932 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2798773697 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:42 PM PDT 24 31900044002 ps
T404 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.252787965 Jun 27 07:00:41 PM PDT 24 Jun 27 07:00:49 PM PDT 24 333832129 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1676684548 Jun 27 07:00:22 PM PDT 24 Jun 27 07:00:35 PM PDT 24 5413116931 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2739798593 Jun 27 07:01:17 PM PDT 24 Jun 27 07:02:35 PM PDT 24 5672967979 ps
T407 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1993519821 Jun 27 07:00:42 PM PDT 24 Jun 27 07:01:01 PM PDT 24 4202292535 ps
T105 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3617806240 Jun 27 07:00:41 PM PDT 24 Jun 27 07:00:58 PM PDT 24 7119860983 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.167910836 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:43 PM PDT 24 7711586882 ps
T409 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3033481145 Jun 27 07:00:22 PM PDT 24 Jun 27 07:00:38 PM PDT 24 7751587562 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2072553290 Jun 27 07:01:17 PM PDT 24 Jun 27 07:01:32 PM PDT 24 4669198868 ps
T411 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2269548677 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:53 PM PDT 24 1870143538 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4255818001 Jun 27 07:00:07 PM PDT 24 Jun 27 07:00:23 PM PDT 24 6185881880 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4011405415 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:56 PM PDT 24 6514137740 ps
T86 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1536806344 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:03 PM PDT 24 165322932 ps
T414 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3767782638 Jun 27 07:01:07 PM PDT 24 Jun 27 07:02:50 PM PDT 24 52334303280 ps
T415 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.387910969 Jun 27 07:01:00 PM PDT 24 Jun 27 07:01:14 PM PDT 24 1993395905 ps
T122 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.994541921 Jun 27 07:00:24 PM PDT 24 Jun 27 07:01:41 PM PDT 24 1376930965 ps
T416 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1667791654 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:04 PM PDT 24 637294873 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1534455474 Jun 27 07:00:41 PM PDT 24 Jun 27 07:00:53 PM PDT 24 1395538189 ps
T418 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1157837381 Jun 27 07:00:59 PM PDT 24 Jun 27 07:01:05 PM PDT 24 85481886 ps
T419 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.263656234 Jun 27 07:01:16 PM PDT 24 Jun 27 07:01:32 PM PDT 24 5006091109 ps
T117 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.917466228 Jun 27 07:00:59 PM PDT 24 Jun 27 07:02:09 PM PDT 24 1047410502 ps
T84 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2747224080 Jun 27 07:00:22 PM PDT 24 Jun 27 07:00:31 PM PDT 24 738116475 ps
T420 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3401651767 Jun 27 07:00:59 PM PDT 24 Jun 27 07:01:13 PM PDT 24 1475000182 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.422174102 Jun 27 07:00:22 PM PDT 24 Jun 27 07:00:28 PM PDT 24 171259444 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1902972281 Jun 27 07:00:21 PM PDT 24 Jun 27 07:00:30 PM PDT 24 1963401610 ps
T423 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.273149882 Jun 27 07:01:17 PM PDT 24 Jun 27 07:01:34 PM PDT 24 1839024750 ps
T79 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1610921437 Jun 27 07:01:17 PM PDT 24 Jun 27 07:02:08 PM PDT 24 5358889786 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3242513578 Jun 27 07:00:07 PM PDT 24 Jun 27 07:00:13 PM PDT 24 346489022 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2861379783 Jun 27 07:00:24 PM PDT 24 Jun 27 07:00:33 PM PDT 24 1814720651 ps
T426 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1931066862 Jun 27 07:00:21 PM PDT 24 Jun 27 07:00:36 PM PDT 24 681952888 ps
T427 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.397327270 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:19 PM PDT 24 3273130925 ps
T428 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2563502698 Jun 27 07:00:58 PM PDT 24 Jun 27 07:02:07 PM PDT 24 1455011905 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3477501547 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:49 PM PDT 24 89315724 ps
T123 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.7308693 Jun 27 07:01:19 PM PDT 24 Jun 27 07:02:01 PM PDT 24 1734827579 ps
T430 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2607332198 Jun 27 07:01:06 PM PDT 24 Jun 27 07:01:44 PM PDT 24 598350262 ps
T431 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3798158298 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:55 PM PDT 24 3812272230 ps
T432 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2401603181 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:35 PM PDT 24 3920279244 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1395229172 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:49 PM PDT 24 87276080 ps
T87 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2969256855 Jun 27 07:01:00 PM PDT 24 Jun 27 07:02:25 PM PDT 24 19355917284 ps
T434 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1829861883 Jun 27 07:00:57 PM PDT 24 Jun 27 07:01:15 PM PDT 24 6802052327 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3998186644 Jun 27 07:00:22 PM PDT 24 Jun 27 07:00:29 PM PDT 24 88032483 ps
T118 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1102566518 Jun 27 07:01:17 PM PDT 24 Jun 27 07:02:33 PM PDT 24 6895814830 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.661644128 Jun 27 07:00:06 PM PDT 24 Jun 27 07:00:52 PM PDT 24 19179503293 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1966298229 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:40 PM PDT 24 3095639207 ps
T438 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1211614560 Jun 27 07:00:59 PM PDT 24 Jun 27 07:01:29 PM PDT 24 1762146705 ps
T439 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3043452992 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:12 PM PDT 24 6799571820 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2729794012 Jun 27 07:01:20 PM PDT 24 Jun 27 07:01:27 PM PDT 24 168051644 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1999278090 Jun 27 07:00:45 PM PDT 24 Jun 27 07:00:52 PM PDT 24 1211240578 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2999954919 Jun 27 07:00:40 PM PDT 24 Jun 27 07:00:51 PM PDT 24 855167844 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.606157011 Jun 27 07:00:59 PM PDT 24 Jun 27 07:01:17 PM PDT 24 9505607904 ps
T444 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.6572280 Jun 27 07:00:41 PM PDT 24 Jun 27 07:00:59 PM PDT 24 7118135460 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.450168197 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:58 PM PDT 24 3389179983 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.537144489 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:38 PM PDT 24 10013288709 ps
T447 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3379580972 Jun 27 07:01:23 PM PDT 24 Jun 27 07:02:08 PM PDT 24 34354652007 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2453751676 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:31 PM PDT 24 254430756 ps
T449 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2189634380 Jun 27 07:01:02 PM PDT 24 Jun 27 07:01:10 PM PDT 24 2252215032 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3562065898 Jun 27 07:00:23 PM PDT 24 Jun 27 07:01:04 PM PDT 24 285528080 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2409650684 Jun 27 07:01:18 PM PDT 24 Jun 27 07:01:35 PM PDT 24 1824231462 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2749274240 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:31 PM PDT 24 991561162 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3962295981 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:48 PM PDT 24 308117267 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.269997356 Jun 27 07:01:17 PM PDT 24 Jun 27 07:01:29 PM PDT 24 1039573182 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4030672086 Jun 27 07:00:07 PM PDT 24 Jun 27 07:00:24 PM PDT 24 4263058768 ps
T455 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2739733309 Jun 27 07:00:42 PM PDT 24 Jun 27 07:01:04 PM PDT 24 8831835236 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.363846136 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:50 PM PDT 24 252909768 ps
T457 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2246003169 Jun 27 07:00:56 PM PDT 24 Jun 27 07:01:14 PM PDT 24 7665167558 ps
T458 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1625064566 Jun 27 07:00:42 PM PDT 24 Jun 27 07:00:55 PM PDT 24 3056897267 ps
T459 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3751850819 Jun 27 07:01:00 PM PDT 24 Jun 27 07:01:30 PM PDT 24 6749014626 ps
T460 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3577313016 Jun 27 07:01:06 PM PDT 24 Jun 27 07:01:13 PM PDT 24 1709388358 ps
T461 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4272408220 Jun 27 07:01:00 PM PDT 24 Jun 27 07:02:01 PM PDT 24 31499299422 ps
T462 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3266704922 Jun 27 07:01:17 PM PDT 24 Jun 27 07:02:30 PM PDT 24 486748671 ps
T124 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2918059869 Jun 27 07:00:40 PM PDT 24 Jun 27 07:01:58 PM PDT 24 1764270300 ps
T463 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.100396622 Jun 27 07:00:58 PM PDT 24 Jun 27 07:01:06 PM PDT 24 1046278294 ps
T464 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3710763626 Jun 27 07:00:40 PM PDT 24 Jun 27 07:00:46 PM PDT 24 397384929 ps
T88 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3373541075 Jun 27 07:01:00 PM PDT 24 Jun 27 07:01:06 PM PDT 24 346508245 ps
T465 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4105218651 Jun 27 07:00:57 PM PDT 24 Jun 27 07:01:15 PM PDT 24 1931088633 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2117630412 Jun 27 07:00:21 PM PDT 24 Jun 27 07:00:31 PM PDT 24 705385756 ps
T466 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3038872174 Jun 27 07:00:08 PM PDT 24 Jun 27 07:00:20 PM PDT 24 4336801475 ps
T467 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2450488602 Jun 27 07:00:39 PM PDT 24 Jun 27 07:00:48 PM PDT 24 86830558 ps
T82 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.200693960 Jun 27 07:00:07 PM PDT 24 Jun 27 07:00:23 PM PDT 24 9396863654 ps
T85 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1571222070 Jun 27 07:01:20 PM PDT 24 Jun 27 07:01:33 PM PDT 24 1070181683 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3683466032 Jun 27 07:00:23 PM PDT 24 Jun 27 07:00:39 PM PDT 24 1773185371 ps

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3347789080
Short name T2
Test name
Test status
Simulation time 63250749434 ps
CPU time 2203.72 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 07:35:02 PM PDT 24
Peak memory 237104 kb
Host smart-34411c51-0411-4e0a-bb2b-0ad8452c074a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347789080 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3347789080
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4189280953
Short name T33
Test name
Test status
Simulation time 133580179395 ps
CPU time 382.94 seconds
Started Jun 27 06:57:01 PM PDT 24
Finished Jun 27 07:03:26 PM PDT 24
Peak memory 239852 kb
Host smart-60ec7e60-388e-4890-8321-f513cf2ad9fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189280953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4189280953
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1465376666
Short name T11
Test name
Test status
Simulation time 31454215537 ps
CPU time 1981.53 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 07:32:44 PM PDT 24
Peak memory 235816 kb
Host smart-4a659818-c906-4b26-88fa-212f4b1dd381
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465376666 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1465376666
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2941962757
Short name T116
Test name
Test status
Simulation time 2735262196 ps
CPU time 69.72 seconds
Started Jun 27 07:00:57 PM PDT 24
Finished Jun 27 07:02:07 PM PDT 24
Peak memory 219056 kb
Host smart-e2e27c77-416b-4c83-8c4b-88a644f6a616
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941962757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2941962757
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2052604602
Short name T15
Test name
Test status
Simulation time 1169750335 ps
CPU time 56.78 seconds
Started Jun 27 06:57:02 PM PDT 24
Finished Jun 27 06:58:01 PM PDT 24
Peak memory 235880 kb
Host smart-1257ad1c-0695-4aed-b74d-e5fa1974ce80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052604602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2052604602
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2155866981
Short name T7
Test name
Test status
Simulation time 1808205447 ps
CPU time 109.12 seconds
Started Jun 27 06:58:44 PM PDT 24
Finished Jun 27 07:00:35 PM PDT 24
Peak memory 236744 kb
Host smart-13e22063-cebc-40c4-90c5-fb2583bd94ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155866981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2155866981
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.98706920
Short name T63
Test name
Test status
Simulation time 5269266668 ps
CPU time 49.61 seconds
Started Jun 27 07:00:21 PM PDT 24
Finished Jun 27 07:01:12 PM PDT 24
Peak memory 210876 kb
Host smart-faa85b3e-f035-4de6-9c10-a2906085a4de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98706920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.98706920
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.917466228
Short name T117
Test name
Test status
Simulation time 1047410502 ps
CPU time 69.11 seconds
Started Jun 27 07:00:59 PM PDT 24
Finished Jun 27 07:02:09 PM PDT 24
Peak memory 212260 kb
Host smart-1506c30f-5258-4e4e-9a1d-39e0b0d39140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917466228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.917466228
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.631603186
Short name T41
Test name
Test status
Simulation time 880318717421 ps
CPU time 4404.1 seconds
Started Jun 27 06:58:46 PM PDT 24
Finished Jun 27 08:12:13 PM PDT 24
Peak memory 252224 kb
Host smart-34627c46-ee51-484e-8a4c-95663779c7ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631603186 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.631603186
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4232046455
Short name T1
Test name
Test status
Simulation time 4750680937 ps
CPU time 11.3 seconds
Started Jun 27 06:57:18 PM PDT 24
Finished Jun 27 06:57:31 PM PDT 24
Peak memory 211364 kb
Host smart-ca9378e3-e663-4d9c-955d-94f36f014767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232046455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4232046455
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3213626845
Short name T126
Test name
Test status
Simulation time 7544326829 ps
CPU time 48.33 seconds
Started Jun 27 06:57:17 PM PDT 24
Finished Jun 27 06:58:07 PM PDT 24
Peak memory 214576 kb
Host smart-070d9e6a-4cf4-419e-8685-335f38b4b63c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213626845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3213626845
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2266442408
Short name T133
Test name
Test status
Simulation time 260403623 ps
CPU time 11.15 seconds
Started Jun 27 06:58:01 PM PDT 24
Finished Jun 27 06:58:14 PM PDT 24
Peak memory 211972 kb
Host smart-466f848c-7cf3-436c-916a-4e5bdc836f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266442408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2266442408
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1593713378
Short name T44
Test name
Test status
Simulation time 173601040 ps
CPU time 9.86 seconds
Started Jun 27 06:56:40 PM PDT 24
Finished Jun 27 06:56:51 PM PDT 24
Peak memory 212100 kb
Host smart-db15891f-d579-4c8c-92e2-c345c83592c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593713378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1593713378
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.662114505
Short name T45
Test name
Test status
Simulation time 2268665380 ps
CPU time 22.6 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 07:00:04 PM PDT 24
Peak memory 211824 kb
Host smart-76af2e3e-b5a8-4c2b-830f-6aba8ce9df9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662114505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.662114505
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.7308693
Short name T123
Test name
Test status
Simulation time 1734827579 ps
CPU time 39.75 seconds
Started Jun 27 07:01:19 PM PDT 24
Finished Jun 27 07:02:01 PM PDT 24
Peak memory 218972 kb
Host smart-d4654f84-6882-430a-a0ef-61d78362696a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7308693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg
_err.7308693
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4030672086
Short name T80
Test name
Test status
Simulation time 4263058768 ps
CPU time 15.31 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:24 PM PDT 24
Peak memory 218744 kb
Host smart-608f9eba-b2cc-472b-95b1-cbd8e81bf6ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030672086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4030672086
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1015969037
Short name T70
Test name
Test status
Simulation time 4313643427 ps
CPU time 39.2 seconds
Started Jun 27 06:57:04 PM PDT 24
Finished Jun 27 06:57:44 PM PDT 24
Peak memory 213188 kb
Host smart-f0f55072-3f55-4683-b069-af03f4c1d878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015969037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1015969037
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3751850819
Short name T459
Test name
Test status
Simulation time 6749014626 ps
CPU time 28.77 seconds
Started Jun 27 07:01:00 PM PDT 24
Finished Jun 27 07:01:30 PM PDT 24
Peak memory 210760 kb
Host smart-d4754426-3644-4e33-aab2-ed9a9fc191af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751850819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3751850819
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2428271422
Short name T104
Test name
Test status
Simulation time 4741411818 ps
CPU time 11.6 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:20 PM PDT 24
Peak memory 219032 kb
Host smart-bf484fab-4ed6-4832-ba06-5c5d9cabc16b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428271422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2428271422
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.465380327
Short name T89
Test name
Test status
Simulation time 6334161058 ps
CPU time 15.15 seconds
Started Jun 27 06:58:17 PM PDT 24
Finished Jun 27 06:58:35 PM PDT 24
Peak memory 211404 kb
Host smart-39438eb2-dfe8-4f18-bede-586c452ce8bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465380327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.465380327
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3242513578
Short name T424
Test name
Test status
Simulation time 346489022 ps
CPU time 4.46 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:13 PM PDT 24
Peak memory 216556 kb
Host smart-2311399a-3f6a-4715-b452-9dd7772d2c9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242513578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3242513578
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.200693960
Short name T82
Test name
Test status
Simulation time 9396863654 ps
CPU time 15.11 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:23 PM PDT 24
Peak memory 218924 kb
Host smart-c2892687-4d25-4149-8d76-369ea40be682
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200693960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.200693960
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3038872174
Short name T466
Test name
Test status
Simulation time 4336801475 ps
CPU time 10.87 seconds
Started Jun 27 07:00:08 PM PDT 24
Finished Jun 27 07:00:20 PM PDT 24
Peak memory 219064 kb
Host smart-f3c5dd9c-32e5-41fd-8c26-0c26d90abe40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038872174 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3038872174
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4255818001
Short name T412
Test name
Test status
Simulation time 6185881880 ps
CPU time 14.46 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:23 PM PDT 24
Peak memory 210760 kb
Host smart-61a69d3d-efcf-4cbc-86d3-ae657d21dd9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255818001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4255818001
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4029576931
Short name T381
Test name
Test status
Simulation time 592648328 ps
CPU time 8.06 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:17 PM PDT 24
Peak memory 210612 kb
Host smart-29b75960-554d-4486-b0ef-4f109024714f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029576931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4029576931
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2985373898
Short name T384
Test name
Test status
Simulation time 16422235529 ps
CPU time 15.61 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:24 PM PDT 24
Peak memory 210604 kb
Host smart-410804c6-67f7-4409-aa18-0fd3935a2c90
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985373898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2985373898
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.661644128
Short name T436
Test name
Test status
Simulation time 19179503293 ps
CPU time 45.51 seconds
Started Jun 27 07:00:06 PM PDT 24
Finished Jun 27 07:00:52 PM PDT 24
Peak memory 210832 kb
Host smart-f50d3590-e228-4575-aeb2-3aa27c68a414
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661644128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.661644128
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3831198538
Short name T370
Test name
Test status
Simulation time 21175183937 ps
CPU time 16.43 seconds
Started Jun 27 07:00:13 PM PDT 24
Finished Jun 27 07:00:30 PM PDT 24
Peak memory 219084 kb
Host smart-183d911d-2b96-4cf9-b518-91041fe7c670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831198538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3831198538
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2531787458
Short name T115
Test name
Test status
Simulation time 411639092 ps
CPU time 69.17 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:01:18 PM PDT 24
Peak memory 219024 kb
Host smart-9844a540-bcd6-4f60-9bd1-3d673d0ad626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531787458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2531787458
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3683466032
Short name T83
Test name
Test status
Simulation time 1773185371 ps
CPU time 14.38 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:39 PM PDT 24
Peak memory 210768 kb
Host smart-df9234cd-1e93-4977-b671-549417dd082d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683466032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3683466032
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1902972281
Short name T422
Test name
Test status
Simulation time 1963401610 ps
CPU time 7.56 seconds
Started Jun 27 07:00:21 PM PDT 24
Finished Jun 27 07:00:30 PM PDT 24
Peak memory 217508 kb
Host smart-3372c77d-bc34-4bbd-be2a-15636a595ee4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902972281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1902972281
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2798773697
Short name T403
Test name
Test status
Simulation time 31900044002 ps
CPU time 17.24 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:42 PM PDT 24
Peak memory 218908 kb
Host smart-e4bab3df-ce8f-46bd-b060-db2024ca0a90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798773697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2798773697
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3033481145
Short name T409
Test name
Test status
Simulation time 7751587562 ps
CPU time 13.76 seconds
Started Jun 27 07:00:22 PM PDT 24
Finished Jun 27 07:00:38 PM PDT 24
Peak memory 219148 kb
Host smart-921fb77d-970f-4052-9857-7cff3e5d3603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033481145 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3033481145
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2117630412
Short name T81
Test name
Test status
Simulation time 705385756 ps
CPU time 8.6 seconds
Started Jun 27 07:00:21 PM PDT 24
Finished Jun 27 07:00:31 PM PDT 24
Peak memory 210788 kb
Host smart-0222a0ee-8a70-4e7f-8962-c8add181c436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117630412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2117630412
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1006413092
Short name T374
Test name
Test status
Simulation time 1558933372 ps
CPU time 9.37 seconds
Started Jun 27 07:00:22 PM PDT 24
Finished Jun 27 07:00:32 PM PDT 24
Peak memory 210656 kb
Host smart-0259319d-c02c-4517-8cfc-ccb5d46c5fc0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006413092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1006413092
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2453751676
Short name T448
Test name
Test status
Simulation time 254430756 ps
CPU time 5.82 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:31 PM PDT 24
Peak memory 210616 kb
Host smart-9da069f8-5f4c-44e4-97e4-c9231999c156
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453751676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2453751676
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1770504706
Short name T375
Test name
Test status
Simulation time 1491691918 ps
CPU time 18.54 seconds
Started Jun 27 07:00:08 PM PDT 24
Finished Jun 27 07:00:28 PM PDT 24
Peak memory 210796 kb
Host smart-f4fd12c4-e0db-40a9-9c5b-33d67599b13a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770504706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1770504706
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2401603181
Short name T432
Test name
Test status
Simulation time 3920279244 ps
CPU time 9.88 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:35 PM PDT 24
Peak memory 219048 kb
Host smart-4e878b1d-b771-4db7-8364-40cb10201bda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401603181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2401603181
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.527555695
Short name T383
Test name
Test status
Simulation time 1961680223 ps
CPU time 16.79 seconds
Started Jun 27 07:00:12 PM PDT 24
Finished Jun 27 07:00:30 PM PDT 24
Peak memory 219012 kb
Host smart-1a2e726a-0a40-4bf2-a2af-6598e2f747bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527555695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.527555695
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3562065898
Short name T450
Test name
Test status
Simulation time 285528080 ps
CPU time 38.93 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:01:04 PM PDT 24
Peak memory 213420 kb
Host smart-dabb1e89-97cf-4fe2-a8a3-4ce5da8b41b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562065898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3562065898
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.100396622
Short name T463
Test name
Test status
Simulation time 1046278294 ps
CPU time 5.54 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:06 PM PDT 24
Peak memory 219012 kb
Host smart-392892de-818a-4265-bf1c-e1ee18a8b1e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100396622 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.100396622
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.431342666
Short name T379
Test name
Test status
Simulation time 3689919506 ps
CPU time 15.12 seconds
Started Jun 27 07:01:01 PM PDT 24
Finished Jun 27 07:01:17 PM PDT 24
Peak memory 210820 kb
Host smart-aeb871c4-1b92-4744-945f-c61b4944949d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431342666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.431342666
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4272408220
Short name T461
Test name
Test status
Simulation time 31499299422 ps
CPU time 59.36 seconds
Started Jun 27 07:01:00 PM PDT 24
Finished Jun 27 07:02:01 PM PDT 24
Peak memory 210856 kb
Host smart-9e8ec04e-ccfe-42f8-873c-60aede71ba45
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272408220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4272408220
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2246003169
Short name T457
Test name
Test status
Simulation time 7665167558 ps
CPU time 17.31 seconds
Started Jun 27 07:00:56 PM PDT 24
Finished Jun 27 07:01:14 PM PDT 24
Peak memory 219012 kb
Host smart-e3bb26c0-5591-46ec-bd2b-9f25431bcda9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246003169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2246003169
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2760349054
Short name T394
Test name
Test status
Simulation time 790476485 ps
CPU time 10.48 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:10 PM PDT 24
Peak memory 219004 kb
Host smart-7076d922-0627-4794-ae77-c18a63c296af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760349054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2760349054
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1710189964
Short name T119
Test name
Test status
Simulation time 330480136 ps
CPU time 38.64 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:38 PM PDT 24
Peak memory 210956 kb
Host smart-f735dc5c-22d4-414b-aa5a-79be79f50795
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710189964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1710189964
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.760571609
Short name T399
Test name
Test status
Simulation time 134683870 ps
CPU time 5.44 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:05 PM PDT 24
Peak memory 219012 kb
Host smart-386043d9-4e4c-4cbe-86e5-066fcd5cc17a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760571609 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.760571609
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1536806344
Short name T86
Test name
Test status
Simulation time 165322932 ps
CPU time 4.15 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:03 PM PDT 24
Peak memory 210732 kb
Host smart-cb8a93c4-eed1-496e-bef7-739a66fdd31a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536806344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1536806344
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2252448098
Short name T98
Test name
Test status
Simulation time 39978000969 ps
CPU time 101.29 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:02:41 PM PDT 24
Peak memory 210840 kb
Host smart-8196a22a-67ca-401c-8305-57d6ca144b8c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252448098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2252448098
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1945583548
Short name T102
Test name
Test status
Simulation time 476598564 ps
CPU time 7.4 seconds
Started Jun 27 07:00:56 PM PDT 24
Finished Jun 27 07:01:05 PM PDT 24
Peak memory 210844 kb
Host smart-ff5746c7-c8ac-4975-9fdf-42b900756150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945583548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1945583548
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1370484838
Short name T385
Test name
Test status
Simulation time 85486469 ps
CPU time 8.34 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:07 PM PDT 24
Peak memory 219052 kb
Host smart-8f6567db-e8b7-44ad-9a04-75b9647b27a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370484838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1370484838
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3043452992
Short name T439
Test name
Test status
Simulation time 6799571820 ps
CPU time 11.73 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:12 PM PDT 24
Peak memory 219020 kb
Host smart-e0726d78-4ef3-4378-8e98-9bbcacd1d670
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043452992 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3043452992
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3373541075
Short name T88
Test name
Test status
Simulation time 346508245 ps
CPU time 4.24 seconds
Started Jun 27 07:01:00 PM PDT 24
Finished Jun 27 07:01:06 PM PDT 24
Peak memory 210676 kb
Host smart-ee8c3394-4b48-4e0e-afd6-6f6399525148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373541075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3373541075
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1211614560
Short name T438
Test name
Test status
Simulation time 1762146705 ps
CPU time 29 seconds
Started Jun 27 07:00:59 PM PDT 24
Finished Jun 27 07:01:29 PM PDT 24
Peak memory 210680 kb
Host smart-793e3e9c-11b6-40b9-8b10-541167af38f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211614560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1211614560
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1157837381
Short name T418
Test name
Test status
Simulation time 85481886 ps
CPU time 4.27 seconds
Started Jun 27 07:00:59 PM PDT 24
Finished Jun 27 07:01:05 PM PDT 24
Peak memory 210748 kb
Host smart-ff3a4fa5-73a9-4948-b427-861afef8f4db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157837381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1157837381
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.397327270
Short name T427
Test name
Test status
Simulation time 3273130925 ps
CPU time 19.5 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:19 PM PDT 24
Peak memory 219068 kb
Host smart-86ee13fc-ef6b-4f14-a063-2f2eec50e516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397327270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.397327270
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2563502698
Short name T428
Test name
Test status
Simulation time 1455011905 ps
CPU time 68 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:02:07 PM PDT 24
Peak memory 211400 kb
Host smart-55d3cf8e-cf2e-48eb-9b48-38daca89b93f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563502698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2563502698
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2586335384
Short name T376
Test name
Test status
Simulation time 1524034176 ps
CPU time 12.62 seconds
Started Jun 27 07:00:59 PM PDT 24
Finished Jun 27 07:01:13 PM PDT 24
Peak memory 219076 kb
Host smart-f7946939-4fd7-45ae-9a5d-3fbd903b2734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586335384 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2586335384
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1667791654
Short name T416
Test name
Test status
Simulation time 637294873 ps
CPU time 4.33 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:04 PM PDT 24
Peak memory 210764 kb
Host smart-4ea68047-2f34-45d7-8148-eb28a2fe24de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667791654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1667791654
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4119824001
Short name T69
Test name
Test status
Simulation time 168085194 ps
CPU time 4.28 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:03 PM PDT 24
Peak memory 218340 kb
Host smart-237f0653-875f-40fb-b66a-a9ff50d2e98e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119824001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4119824001
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1829861883
Short name T434
Test name
Test status
Simulation time 6802052327 ps
CPU time 16.23 seconds
Started Jun 27 07:00:57 PM PDT 24
Finished Jun 27 07:01:15 PM PDT 24
Peak memory 219088 kb
Host smart-d2864d80-e846-4a67-bc0a-2b1a17530f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829861883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1829861883
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2607332198
Short name T430
Test name
Test status
Simulation time 598350262 ps
CPU time 36.08 seconds
Started Jun 27 07:01:06 PM PDT 24
Finished Jun 27 07:01:44 PM PDT 24
Peak memory 218908 kb
Host smart-7149e5cd-7777-4269-b758-6b4fb1491cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607332198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2607332198
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3577313016
Short name T460
Test name
Test status
Simulation time 1709388358 ps
CPU time 5.39 seconds
Started Jun 27 07:01:06 PM PDT 24
Finished Jun 27 07:01:13 PM PDT 24
Peak memory 218968 kb
Host smart-81d63952-42b4-4e4f-b7bc-2808a5a82df8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577313016 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3577313016
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2189634380
Short name T449
Test name
Test status
Simulation time 2252215032 ps
CPU time 7.62 seconds
Started Jun 27 07:01:02 PM PDT 24
Finished Jun 27 07:01:10 PM PDT 24
Peak memory 218268 kb
Host smart-7f233fe0-3b87-43ea-b993-586b61423bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189634380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2189634380
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2969256855
Short name T87
Test name
Test status
Simulation time 19355917284 ps
CPU time 83.23 seconds
Started Jun 27 07:01:00 PM PDT 24
Finished Jun 27 07:02:25 PM PDT 24
Peak memory 210792 kb
Host smart-9b9eb903-2b89-40d0-9b29-f889f6c344b3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969256855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2969256855
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.238961590
Short name T101
Test name
Test status
Simulation time 21116742626 ps
CPU time 11.12 seconds
Started Jun 27 07:00:57 PM PDT 24
Finished Jun 27 07:01:10 PM PDT 24
Peak memory 219044 kb
Host smart-dbe9c860-8efa-4713-8e89-e43eccac2325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238961590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.238961590
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.606157011
Short name T443
Test name
Test status
Simulation time 9505607904 ps
CPU time 15.87 seconds
Started Jun 27 07:00:59 PM PDT 24
Finished Jun 27 07:01:17 PM PDT 24
Peak memory 219084 kb
Host smart-8a93dd15-8dcd-4424-b180-43a09cab6ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606157011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.606157011
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2197813150
Short name T53
Test name
Test status
Simulation time 987823191 ps
CPU time 36.37 seconds
Started Jun 27 07:00:58 PM PDT 24
Finished Jun 27 07:01:36 PM PDT 24
Peak memory 218956 kb
Host smart-9112cae0-db49-49bb-b3bc-a0e683dad9e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197813150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2197813150
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2094861506
Short name T373
Test name
Test status
Simulation time 197204129 ps
CPU time 5.48 seconds
Started Jun 27 07:01:18 PM PDT 24
Finished Jun 27 07:01:27 PM PDT 24
Peak memory 219020 kb
Host smart-02e86223-cbb5-414a-8d32-e12a16d7b491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094861506 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2094861506
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1571222070
Short name T85
Test name
Test status
Simulation time 1070181683 ps
CPU time 10.72 seconds
Started Jun 27 07:01:20 PM PDT 24
Finished Jun 27 07:01:33 PM PDT 24
Peak memory 210756 kb
Host smart-c0645bb3-7059-4929-b7d4-ce5ec38d619a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571222070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1571222070
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3767782638
Short name T414
Test name
Test status
Simulation time 52334303280 ps
CPU time 102.52 seconds
Started Jun 27 07:01:07 PM PDT 24
Finished Jun 27 07:02:50 PM PDT 24
Peak memory 211780 kb
Host smart-711bb2b7-70d5-45d3-b254-88423a6ee9c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767782638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3767782638
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2729794012
Short name T440
Test name
Test status
Simulation time 168051644 ps
CPU time 4.32 seconds
Started Jun 27 07:01:20 PM PDT 24
Finished Jun 27 07:01:27 PM PDT 24
Peak memory 210804 kb
Host smart-2ca7d7b3-9740-45e4-9315-2d96f9f8cb0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729794012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2729794012
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4105218651
Short name T465
Test name
Test status
Simulation time 1931088633 ps
CPU time 17.34 seconds
Started Jun 27 07:00:57 PM PDT 24
Finished Jun 27 07:01:15 PM PDT 24
Peak memory 219008 kb
Host smart-b3777491-9d6a-4648-8f99-8f583fae9bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105218651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4105218651
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3266704922
Short name T462
Test name
Test status
Simulation time 486748671 ps
CPU time 70.05 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:02:30 PM PDT 24
Peak memory 218996 kb
Host smart-7a6b2f24-9ebe-4bcc-b8d9-3f16f6d07b7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266704922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3266704922
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2371348527
Short name T55
Test name
Test status
Simulation time 103584907 ps
CPU time 4.84 seconds
Started Jun 27 07:01:19 PM PDT 24
Finished Jun 27 07:01:27 PM PDT 24
Peak memory 213392 kb
Host smart-a4650d93-5735-4e03-bf88-20eba7e3ea21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371348527 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2371348527
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.77294290
Short name T392
Test name
Test status
Simulation time 5240479125 ps
CPU time 11.89 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:01:32 PM PDT 24
Peak memory 218976 kb
Host smart-bf5a69b9-215c-4ce9-9edc-a64d2cb6bbfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77294290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.77294290
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1438381962
Short name T66
Test name
Test status
Simulation time 91766916267 ps
CPU time 102.94 seconds
Started Jun 27 07:01:18 PM PDT 24
Finished Jun 27 07:03:04 PM PDT 24
Peak memory 210808 kb
Host smart-71e25d26-a046-487e-b5d9-260e075e0a93
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438381962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1438381962
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1120778145
Short name T100
Test name
Test status
Simulation time 2463375149 ps
CPU time 13.07 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:01:34 PM PDT 24
Peak memory 219060 kb
Host smart-d2dbd6b9-074c-4594-9bbd-29b5a706b9d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120778145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1120778145
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2028106727
Short name T398
Test name
Test status
Simulation time 637768617 ps
CPU time 7.16 seconds
Started Jun 27 07:01:19 PM PDT 24
Finished Jun 27 07:01:29 PM PDT 24
Peak memory 219020 kb
Host smart-50cf0f52-93aa-44b6-bf01-a64d4093af57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028106727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2028106727
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2828573539
Short name T52
Test name
Test status
Simulation time 3703358281 ps
CPU time 41.12 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:02:01 PM PDT 24
Peak memory 212344 kb
Host smart-5bbfb611-0634-49db-aaaa-9f5439564b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828573539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2828573539
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2072553290
Short name T410
Test name
Test status
Simulation time 4669198868 ps
CPU time 11.75 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:01:32 PM PDT 24
Peak memory 219124 kb
Host smart-f832a640-7d3b-4101-ba5e-d9ceb0a05e3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072553290 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2072553290
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2796534738
Short name T67
Test name
Test status
Simulation time 8578351736 ps
CPU time 16.42 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:01:35 PM PDT 24
Peak memory 210856 kb
Host smart-6fe084f6-2922-430e-855d-26e2d5b032ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796534738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2796534738
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2814684711
Short name T395
Test name
Test status
Simulation time 5120707764 ps
CPU time 49.39 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:02:09 PM PDT 24
Peak memory 210844 kb
Host smart-7ae0cee3-c2d5-467c-9f04-23b3d8ee0dfa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814684711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2814684711
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.273149882
Short name T423
Test name
Test status
Simulation time 1839024750 ps
CPU time 14.35 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:01:34 PM PDT 24
Peak memory 210840 kb
Host smart-64ac3695-e1c9-4897-b105-f02841750d75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273149882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.273149882
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1834131430
Short name T380
Test name
Test status
Simulation time 938048223 ps
CPU time 14.36 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:01:34 PM PDT 24
Peak memory 219024 kb
Host smart-7bbe21da-25ed-44c4-98a5-8d0f02fc9511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834131430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1834131430
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3322894893
Short name T390
Test name
Test status
Simulation time 1873824867 ps
CPU time 15.96 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:01:36 PM PDT 24
Peak memory 219092 kb
Host smart-76fe23fb-48fb-4db5-9de8-7dc758ae16f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322894893 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3322894893
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4135889710
Short name T386
Test name
Test status
Simulation time 8850023069 ps
CPU time 16.4 seconds
Started Jun 27 07:01:19 PM PDT 24
Finished Jun 27 07:01:38 PM PDT 24
Peak memory 210720 kb
Host smart-c5de3d00-996c-4c83-ab05-1e7f01b53842
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135889710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4135889710
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3379580972
Short name T447
Test name
Test status
Simulation time 34354652007 ps
CPU time 44.07 seconds
Started Jun 27 07:01:23 PM PDT 24
Finished Jun 27 07:02:08 PM PDT 24
Peak memory 210776 kb
Host smart-6611ed09-1f4c-4958-a8e7-8dba45cd67bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379580972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3379580972
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2574883807
Short name T99
Test name
Test status
Simulation time 11538573764 ps
CPU time 14.2 seconds
Started Jun 27 07:01:16 PM PDT 24
Finished Jun 27 07:01:32 PM PDT 24
Peak memory 219040 kb
Host smart-68eea9eb-0800-455f-8c4b-a6ef48a5a392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574883807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2574883807
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1615858418
Short name T388
Test name
Test status
Simulation time 2148014877 ps
CPU time 9.9 seconds
Started Jun 27 07:01:19 PM PDT 24
Finished Jun 27 07:01:32 PM PDT 24
Peak memory 218984 kb
Host smart-3d11d9ea-5fbd-4300-9ec8-0b47da1cb92d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615858418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1615858418
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2739798593
Short name T406
Test name
Test status
Simulation time 5672967979 ps
CPU time 74.61 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:02:35 PM PDT 24
Peak memory 219088 kb
Host smart-8fdf178a-93a3-4b88-8f64-359ed886d142
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739798593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2739798593
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.263656234
Short name T419
Test name
Test status
Simulation time 5006091109 ps
CPU time 12.86 seconds
Started Jun 27 07:01:16 PM PDT 24
Finished Jun 27 07:01:32 PM PDT 24
Peak memory 219140 kb
Host smart-fffa6c8b-ccb1-4fe1-80e6-54db464c53bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263656234 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.263656234
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2409650684
Short name T451
Test name
Test status
Simulation time 1824231462 ps
CPU time 14.4 seconds
Started Jun 27 07:01:18 PM PDT 24
Finished Jun 27 07:01:35 PM PDT 24
Peak memory 210660 kb
Host smart-1d03dd55-6725-4b5d-b9ed-a5f81ab7ebdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409650684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2409650684
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1610921437
Short name T79
Test name
Test status
Simulation time 5358889786 ps
CPU time 47.73 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:02:08 PM PDT 24
Peak memory 210828 kb
Host smart-918c2035-b563-44a9-95a0-52a50dbd1cd1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610921437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1610921437
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.269997356
Short name T454
Test name
Test status
Simulation time 1039573182 ps
CPU time 10.22 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:01:29 PM PDT 24
Peak memory 210832 kb
Host smart-94a9d329-5794-4c5b-910a-9756e1a1acc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269997356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.269997356
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.443021028
Short name T387
Test name
Test status
Simulation time 86328383 ps
CPU time 6.8 seconds
Started Jun 27 07:01:16 PM PDT 24
Finished Jun 27 07:01:25 PM PDT 24
Peak memory 219028 kb
Host smart-e826b3b4-9426-45a5-a7bf-75f773ff0da0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443021028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.443021028
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1102566518
Short name T118
Test name
Test status
Simulation time 6895814830 ps
CPU time 72.35 seconds
Started Jun 27 07:01:17 PM PDT 24
Finished Jun 27 07:02:33 PM PDT 24
Peak memory 219076 kb
Host smart-e41cf13f-b60c-4166-9ee6-746a030a8aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102566518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1102566518
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2747224080
Short name T84
Test name
Test status
Simulation time 738116475 ps
CPU time 8.63 seconds
Started Jun 27 07:00:22 PM PDT 24
Finished Jun 27 07:00:31 PM PDT 24
Peak memory 218540 kb
Host smart-16ae7ad0-08d1-4662-a10e-f3837d6a212a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747224080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2747224080
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1676684548
Short name T405
Test name
Test status
Simulation time 5413116931 ps
CPU time 11.59 seconds
Started Jun 27 07:00:22 PM PDT 24
Finished Jun 27 07:00:35 PM PDT 24
Peak memory 210772 kb
Host smart-63b40635-ed2b-43d3-90da-c90820842547
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676684548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1676684548
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.167910836
Short name T408
Test name
Test status
Simulation time 7711586882 ps
CPU time 17.84 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:43 PM PDT 24
Peak memory 211040 kb
Host smart-88f20882-dd1c-4033-ba6d-758493fceb7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167910836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.167910836
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.537144489
Short name T446
Test name
Test status
Simulation time 10013288709 ps
CPU time 12.88 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:38 PM PDT 24
Peak memory 219120 kb
Host smart-db864507-6523-4b56-9758-6a955766c961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537144489 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.537144489
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2454012010
Short name T64
Test name
Test status
Simulation time 1680771378 ps
CPU time 13.85 seconds
Started Jun 27 07:00:26 PM PDT 24
Finished Jun 27 07:00:41 PM PDT 24
Peak memory 210708 kb
Host smart-2cfba6f1-6c81-45f6-bd95-79102466f45d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454012010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2454012010
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2912288581
Short name T400
Test name
Test status
Simulation time 891165464 ps
CPU time 7.27 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:33 PM PDT 24
Peak memory 210608 kb
Host smart-33c58542-4f92-4cfc-95a8-1d66f33448fe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912288581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2912288581
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2861379783
Short name T425
Test name
Test status
Simulation time 1814720651 ps
CPU time 7.18 seconds
Started Jun 27 07:00:24 PM PDT 24
Finished Jun 27 07:00:33 PM PDT 24
Peak memory 210588 kb
Host smart-c72d9aff-1751-44ce-a282-b2374c1f5331
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861379783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2861379783
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1966298229
Short name T437
Test name
Test status
Simulation time 3095639207 ps
CPU time 14.81 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:40 PM PDT 24
Peak memory 219044 kb
Host smart-599ee8c9-bc57-4fcd-b2ae-edab97f2e33d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966298229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1966298229
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1931066862
Short name T426
Test name
Test status
Simulation time 681952888 ps
CPU time 13.32 seconds
Started Jun 27 07:00:21 PM PDT 24
Finished Jun 27 07:00:36 PM PDT 24
Peak memory 218920 kb
Host smart-39b29a97-b793-4dc6-99c2-92c052d11fda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931066862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1931066862
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.994541921
Short name T122
Test name
Test status
Simulation time 1376930965 ps
CPU time 75.02 seconds
Started Jun 27 07:00:24 PM PDT 24
Finished Jun 27 07:01:41 PM PDT 24
Peak memory 212228 kb
Host smart-c8ba1883-508a-429e-9dca-48a1ffd0de23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994541921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.994541921
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3477501547
Short name T429
Test name
Test status
Simulation time 89315724 ps
CPU time 4.36 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:49 PM PDT 24
Peak memory 210664 kb
Host smart-807169f8-09fe-479b-9d62-1e889dabb2eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477501547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3477501547
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3710763626
Short name T464
Test name
Test status
Simulation time 397384929 ps
CPU time 4.7 seconds
Started Jun 27 07:00:40 PM PDT 24
Finished Jun 27 07:00:46 PM PDT 24
Peak memory 210768 kb
Host smart-2cdcc817-8057-4ad9-b38f-ee6ff87c66dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710763626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3710763626
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3998186644
Short name T435
Test name
Test status
Simulation time 88032483 ps
CPU time 5.74 seconds
Started Jun 27 07:00:22 PM PDT 24
Finished Jun 27 07:00:29 PM PDT 24
Peak memory 210716 kb
Host smart-61756599-36f4-4617-8400-404d17762b1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998186644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3998186644
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.190772432
Short name T396
Test name
Test status
Simulation time 104826540 ps
CPU time 5.03 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:49 PM PDT 24
Peak memory 214868 kb
Host smart-47a67e6b-aba9-4e4d-8085-98ce8a8d9fa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190772432 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.190772432
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2749274240
Short name T452
Test name
Test status
Simulation time 991561162 ps
CPU time 5.86 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:31 PM PDT 24
Peak memory 218916 kb
Host smart-31449a5a-4ca3-455c-84fd-1fa6ec24e87b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749274240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2749274240
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2316411512
Short name T371
Test name
Test status
Simulation time 22752849194 ps
CPU time 12.65 seconds
Started Jun 27 07:00:22 PM PDT 24
Finished Jun 27 07:00:36 PM PDT 24
Peak memory 210716 kb
Host smart-dc7d9b1f-79a0-4fb4-8ca6-b867586b884f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316411512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2316411512
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.422174102
Short name T421
Test name
Test status
Simulation time 171259444 ps
CPU time 4.21 seconds
Started Jun 27 07:00:22 PM PDT 24
Finished Jun 27 07:00:28 PM PDT 24
Peak memory 210588 kb
Host smart-3f3a6666-8301-43c2-b51a-361fb110e833
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422174102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
422174102
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2011406146
Short name T108
Test name
Test status
Simulation time 2278481442 ps
CPU time 27.88 seconds
Started Jun 27 07:00:23 PM PDT 24
Finished Jun 27 07:00:53 PM PDT 24
Peak memory 210872 kb
Host smart-a307d466-9720-48c7-a2ef-99cd5d4719bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011406146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2011406146
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3962295981
Short name T453
Test name
Test status
Simulation time 308117267 ps
CPU time 4.21 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:48 PM PDT 24
Peak memory 218344 kb
Host smart-72736110-5eec-412d-9836-c3bed86415dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962295981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3962295981
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1422306170
Short name T402
Test name
Test status
Simulation time 4492156932 ps
CPU time 17.88 seconds
Started Jun 27 07:00:24 PM PDT 24
Finished Jun 27 07:00:43 PM PDT 24
Peak memory 219092 kb
Host smart-eab5a9b2-7a9e-44c8-b95d-e5644c0145ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422306170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1422306170
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1709668550
Short name T54
Test name
Test status
Simulation time 2268627523 ps
CPU time 42.19 seconds
Started Jun 27 07:00:26 PM PDT 24
Finished Jun 27 07:01:09 PM PDT 24
Peak memory 219072 kb
Host smart-96d82563-791c-4768-898b-3db4103127fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709668550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1709668550
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1999278090
Short name T441
Test name
Test status
Simulation time 1211240578 ps
CPU time 6.69 seconds
Started Jun 27 07:00:45 PM PDT 24
Finished Jun 27 07:00:52 PM PDT 24
Peak memory 210760 kb
Host smart-eec905d3-c05b-441e-a2d0-093d9f3b0824
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999278090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1999278090
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.450168197
Short name T445
Test name
Test status
Simulation time 3389179983 ps
CPU time 14.09 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:58 PM PDT 24
Peak memory 218288 kb
Host smart-d6def133-4b21-4021-aa50-8e31fe872381
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450168197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.450168197
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1534455474
Short name T417
Test name
Test status
Simulation time 1395538189 ps
CPU time 9.57 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:00:53 PM PDT 24
Peak memory 210692 kb
Host smart-a1c34bcb-6aab-4ef5-a3a3-00b546507ba6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534455474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1534455474
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4011405415
Short name T413
Test name
Test status
Simulation time 6514137740 ps
CPU time 12.03 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:56 PM PDT 24
Peak memory 219112 kb
Host smart-59b2188d-ff09-4321-a476-e7c220435b59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011405415 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4011405415
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1395229172
Short name T433
Test name
Test status
Simulation time 87276080 ps
CPU time 4.32 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:49 PM PDT 24
Peak memory 210940 kb
Host smart-67a7e121-43ca-4394-82f6-d2eb339273a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395229172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1395229172
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2999954919
Short name T442
Test name
Test status
Simulation time 855167844 ps
CPU time 9.27 seconds
Started Jun 27 07:00:40 PM PDT 24
Finished Jun 27 07:00:51 PM PDT 24
Peak memory 210616 kb
Host smart-c8823eac-9f59-4675-9fb7-8d359005f941
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999954919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2999954919
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.363846136
Short name T456
Test name
Test status
Simulation time 252909768 ps
CPU time 5.68 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:50 PM PDT 24
Peak memory 210620 kb
Host smart-242a5a8e-5f8e-479d-ad7f-01d2b9c0353b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363846136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
363846136
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3650819071
Short name T107
Test name
Test status
Simulation time 19070117596 ps
CPU time 47.54 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:01:30 PM PDT 24
Peak memory 210848 kb
Host smart-f4c9ec2c-6a5b-40cf-838b-2d1f5af3ef7a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650819071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3650819071
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3617806240
Short name T105
Test name
Test status
Simulation time 7119860983 ps
CPU time 14.72 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:00:58 PM PDT 24
Peak memory 219008 kb
Host smart-8b1216ee-ce56-44cb-aa56-290cd854c7ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617806240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3617806240
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2678603372
Short name T391
Test name
Test status
Simulation time 12022530125 ps
CPU time 20 seconds
Started Jun 27 07:00:43 PM PDT 24
Finished Jun 27 07:01:05 PM PDT 24
Peak memory 219112 kb
Host smart-2808304b-3f5a-488b-a34c-e19b65c2bdb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678603372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2678603372
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2918059869
Short name T124
Test name
Test status
Simulation time 1764270300 ps
CPU time 76.65 seconds
Started Jun 27 07:00:40 PM PDT 24
Finished Jun 27 07:01:58 PM PDT 24
Peak memory 219020 kb
Host smart-3476442f-cf43-486b-8b13-6fdd888014f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918059869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2918059869
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1993519821
Short name T407
Test name
Test status
Simulation time 4202292535 ps
CPU time 16.43 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:01:01 PM PDT 24
Peak memory 219072 kb
Host smart-79cf4d09-d555-4eef-88a6-8a9e77fd231f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993519821 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1993519821
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.319964821
Short name T393
Test name
Test status
Simulation time 28765064276 ps
CPU time 13.1 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:57 PM PDT 24
Peak memory 218908 kb
Host smart-ea23c2ab-6ad0-4f32-9003-4b6328c6ddc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319964821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.319964821
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2675480696
Short name T113
Test name
Test status
Simulation time 2154971328 ps
CPU time 28.02 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:01:10 PM PDT 24
Peak memory 210824 kb
Host smart-1890a5e5-2590-4673-88ef-1b378e3e1143
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675480696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2675480696
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3798158298
Short name T431
Test name
Test status
Simulation time 3812272230 ps
CPU time 11.41 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:55 PM PDT 24
Peak memory 210920 kb
Host smart-60f7f749-c452-4f90-96af-d2c60aa00525
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798158298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3798158298
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1625064566
Short name T458
Test name
Test status
Simulation time 3056897267 ps
CPU time 11.31 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:55 PM PDT 24
Peak memory 219092 kb
Host smart-dc8df9f3-664f-4acc-8d30-e8488c3abddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625064566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1625064566
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.953661698
Short name T401
Test name
Test status
Simulation time 1734119528 ps
CPU time 45.01 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:01:29 PM PDT 24
Peak memory 218964 kb
Host smart-477de35b-04cc-4872-b408-e00f28537f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953661698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.953661698
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.694477228
Short name T378
Test name
Test status
Simulation time 349777907 ps
CPU time 4.48 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:00:47 PM PDT 24
Peak memory 218968 kb
Host smart-008b51dc-7070-45c0-a947-bbe2777c024e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694477228 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.694477228
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.744803126
Short name T65
Test name
Test status
Simulation time 6774620214 ps
CPU time 11.99 seconds
Started Jun 27 07:00:40 PM PDT 24
Finished Jun 27 07:00:54 PM PDT 24
Peak memory 218952 kb
Host smart-d1776e74-c322-48cf-ba0e-0943f06ff976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744803126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.744803126
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4285097272
Short name T56
Test name
Test status
Simulation time 5388075429 ps
CPU time 27.39 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:01:09 PM PDT 24
Peak memory 210852 kb
Host smart-43152296-262e-4234-b089-e73000b977eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285097272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.4285097272
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2939346004
Short name T103
Test name
Test status
Simulation time 333504272 ps
CPU time 4.34 seconds
Started Jun 27 07:00:43 PM PDT 24
Finished Jun 27 07:00:49 PM PDT 24
Peak memory 218452 kb
Host smart-d1211e55-5989-4ff8-8b9d-eb1a01adb183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939346004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2939346004
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2450488602
Short name T467
Test name
Test status
Simulation time 86830558 ps
CPU time 7.22 seconds
Started Jun 27 07:00:39 PM PDT 24
Finished Jun 27 07:00:48 PM PDT 24
Peak memory 219028 kb
Host smart-b62f987c-8b8d-45f8-896b-35e3438951e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450488602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2450488602
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.78903721
Short name T397
Test name
Test status
Simulation time 8126407073 ps
CPU time 46.2 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:01:29 PM PDT 24
Peak memory 212468 kb
Host smart-51b48ca0-6687-4a42-9bdd-5d97d2d5966a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78903721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg
_err.78903721
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.897787498
Short name T382
Test name
Test status
Simulation time 2091364892 ps
CPU time 16.03 seconds
Started Jun 27 07:00:44 PM PDT 24
Finished Jun 27 07:01:02 PM PDT 24
Peak memory 219052 kb
Host smart-ca94a9b3-414b-46e6-ac44-e0faedb724bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897787498 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.897787498
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2269548677
Short name T411
Test name
Test status
Simulation time 1870143538 ps
CPU time 9.68 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:00:53 PM PDT 24
Peak memory 218912 kb
Host smart-8a4039ba-8e65-4c88-8528-e45f18f963a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269548677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2269548677
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1872730528
Short name T77
Test name
Test status
Simulation time 12703973202 ps
CPU time 95.44 seconds
Started Jun 27 07:00:43 PM PDT 24
Finished Jun 27 07:02:20 PM PDT 24
Peak memory 210868 kb
Host smart-4cb3ee00-4656-4703-8b13-02450d006072
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872730528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1872730528
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.6572280
Short name T444
Test name
Test status
Simulation time 7118135460 ps
CPU time 15.77 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:00:59 PM PDT 24
Peak memory 219032 kb
Host smart-bd945ecd-bd43-45f1-b698-3c07b78b7a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6572280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl
_same_csr_outstanding.6572280
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2739733309
Short name T455
Test name
Test status
Simulation time 8831835236 ps
CPU time 20.21 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:01:04 PM PDT 24
Peak memory 219116 kb
Host smart-c5a28935-77bc-4ff1-b6e4-9fc45a0ada04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739733309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2739733309
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.274012669
Short name T120
Test name
Test status
Simulation time 7205006758 ps
CPU time 37.45 seconds
Started Jun 27 07:00:42 PM PDT 24
Finished Jun 27 07:01:21 PM PDT 24
Peak memory 210916 kb
Host smart-932eec86-c27a-49cd-89d7-1266008c6bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274012669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.274012669
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1492963763
Short name T372
Test name
Test status
Simulation time 21330362131 ps
CPU time 13.31 seconds
Started Jun 27 07:00:59 PM PDT 24
Finished Jun 27 07:01:14 PM PDT 24
Peak memory 219136 kb
Host smart-31a0448e-fd3f-4706-9b24-9f873ab1d75f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492963763 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1492963763
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4239797898
Short name T62
Test name
Test status
Simulation time 305239109 ps
CPU time 6.31 seconds
Started Jun 27 07:00:59 PM PDT 24
Finished Jun 27 07:01:07 PM PDT 24
Peak memory 210784 kb
Host smart-ebc8d707-581b-479e-a432-61cabcb3b82f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239797898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4239797898
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3741272691
Short name T61
Test name
Test status
Simulation time 7221720819 ps
CPU time 60.24 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:01:43 PM PDT 24
Peak memory 210860 kb
Host smart-a5b3ae38-1460-4036-befa-bea30a16f3d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741272691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3741272691
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.387910969
Short name T415
Test name
Test status
Simulation time 1993395905 ps
CPU time 11.86 seconds
Started Jun 27 07:01:00 PM PDT 24
Finished Jun 27 07:01:14 PM PDT 24
Peak memory 218960 kb
Host smart-ad535b9c-8403-4ad5-85b2-9aecb97c476c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387910969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.387910969
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.252787965
Short name T404
Test name
Test status
Simulation time 333832129 ps
CPU time 6.44 seconds
Started Jun 27 07:00:41 PM PDT 24
Finished Jun 27 07:00:49 PM PDT 24
Peak memory 219024 kb
Host smart-3bfd8042-5b23-48a5-8c22-7744d153be72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252787965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.252787965
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1578548363
Short name T121
Test name
Test status
Simulation time 2144788543 ps
CPU time 46.71 seconds
Started Jun 27 07:01:01 PM PDT 24
Finished Jun 27 07:01:49 PM PDT 24
Peak memory 218944 kb
Host smart-c5f5a17d-139b-4fc9-860a-1594b5eb32d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578548363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1578548363
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2088344519
Short name T389
Test name
Test status
Simulation time 261433863 ps
CPU time 4.47 seconds
Started Jun 27 07:01:01 PM PDT 24
Finished Jun 27 07:01:07 PM PDT 24
Peak memory 219028 kb
Host smart-240de5da-801c-4e42-9258-729753b22c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088344519 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2088344519
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.650605357
Short name T78
Test name
Test status
Simulation time 6689000241 ps
CPU time 15.55 seconds
Started Jun 27 07:01:06 PM PDT 24
Finished Jun 27 07:01:23 PM PDT 24
Peak memory 210812 kb
Host smart-6a0e8866-d31d-4528-acbe-d9d1f9f29c85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650605357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.650605357
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.570543219
Short name T68
Test name
Test status
Simulation time 2326922855 ps
CPU time 41.21 seconds
Started Jun 27 07:00:59 PM PDT 24
Finished Jun 27 07:01:42 PM PDT 24
Peak memory 210856 kb
Host smart-d9737b48-b939-419b-98a1-2cce4933df14
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570543219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.570543219
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3401651767
Short name T420
Test name
Test status
Simulation time 1475000182 ps
CPU time 12.83 seconds
Started Jun 27 07:00:59 PM PDT 24
Finished Jun 27 07:01:13 PM PDT 24
Peak memory 210836 kb
Host smart-804312ed-fadf-4721-9b9c-9efc1488f128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401651767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3401651767
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.528405731
Short name T377
Test name
Test status
Simulation time 300041745 ps
CPU time 8.2 seconds
Started Jun 27 07:01:07 PM PDT 24
Finished Jun 27 07:01:16 PM PDT 24
Peak memory 215344 kb
Host smart-ce98f25d-d870-4faa-8fb1-a0a40fd71705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528405731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.528405731
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1539275707
Short name T310
Test name
Test status
Simulation time 739764865 ps
CPU time 6.74 seconds
Started Jun 27 06:57:00 PM PDT 24
Finished Jun 27 06:57:08 PM PDT 24
Peak memory 211284 kb
Host smart-722bae23-2727-46d6-8c24-263c9724d797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539275707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1539275707
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3555263895
Short name T236
Test name
Test status
Simulation time 129579520922 ps
CPU time 208.2 seconds
Started Jun 27 06:56:40 PM PDT 24
Finished Jun 27 07:00:09 PM PDT 24
Peak memory 228436 kb
Host smart-ae7f2bb3-a3ed-4b6b-95aa-3bbb0021ced6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555263895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3555263895
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3131660939
Short name T247
Test name
Test status
Simulation time 3242584484 ps
CPU time 8.35 seconds
Started Jun 27 06:56:39 PM PDT 24
Finished Jun 27 06:56:49 PM PDT 24
Peak memory 211380 kb
Host smart-4540ee7f-67b2-4557-b40a-25fbd0e05d9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131660939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3131660939
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3720816503
Short name T24
Test name
Test status
Simulation time 8818525963 ps
CPU time 112.08 seconds
Started Jun 27 06:57:01 PM PDT 24
Finished Jun 27 06:58:55 PM PDT 24
Peak memory 237096 kb
Host smart-ef915ec9-57b0-426b-b2c6-7a42a1388a8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720816503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3720816503
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3024625532
Short name T282
Test name
Test status
Simulation time 691638268 ps
CPU time 9.68 seconds
Started Jun 27 06:56:43 PM PDT 24
Finished Jun 27 06:56:53 PM PDT 24
Peak memory 213480 kb
Host smart-3e4cd38e-1eda-4fe1-a233-d714e0d0163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024625532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3024625532
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4043574698
Short name T365
Test name
Test status
Simulation time 58943746781 ps
CPU time 40.59 seconds
Started Jun 27 06:56:41 PM PDT 24
Finished Jun 27 06:57:23 PM PDT 24
Peak memory 213924 kb
Host smart-17263f36-2533-467e-bf58-8d5de3216bbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043574698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4043574698
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1343021519
Short name T291
Test name
Test status
Simulation time 2089740258 ps
CPU time 16.36 seconds
Started Jun 27 06:57:00 PM PDT 24
Finished Jun 27 06:57:19 PM PDT 24
Peak memory 211248 kb
Host smart-5af9927f-a9fb-4dec-84cf-b6a9977fb916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343021519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1343021519
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3971461254
Short name T39
Test name
Test status
Simulation time 21494179205 ps
CPU time 279.28 seconds
Started Jun 27 06:57:01 PM PDT 24
Finished Jun 27 07:01:43 PM PDT 24
Peak memory 236844 kb
Host smart-dbf92e79-596c-4586-b9d0-38f7ccaf2265
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971461254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3971461254
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1314037299
Short name T245
Test name
Test status
Simulation time 1238361512 ps
CPU time 14.87 seconds
Started Jun 27 06:57:00 PM PDT 24
Finished Jun 27 06:57:17 PM PDT 24
Peak memory 211680 kb
Host smart-2e64e634-5ee8-4b51-aa23-874dcfb92d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314037299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1314037299
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3441823358
Short name T25
Test name
Test status
Simulation time 1669741107 ps
CPU time 15.29 seconds
Started Jun 27 06:57:00 PM PDT 24
Finished Jun 27 06:57:17 PM PDT 24
Peak memory 211320 kb
Host smart-9fa34a44-0e8f-4982-87d6-a2ef6400faaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441823358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3441823358
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3955958963
Short name T16
Test name
Test status
Simulation time 1581714676 ps
CPU time 60.13 seconds
Started Jun 27 06:57:01 PM PDT 24
Finished Jun 27 06:58:03 PM PDT 24
Peak memory 236820 kb
Host smart-dad129f4-b9db-46e1-a07b-f673ffd94d5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955958963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3955958963
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3161238770
Short name T366
Test name
Test status
Simulation time 7670694651 ps
CPU time 31.18 seconds
Started Jun 27 06:57:00 PM PDT 24
Finished Jun 27 06:57:32 PM PDT 24
Peak memory 214156 kb
Host smart-1123a785-ebfa-477d-b157-fbff3067a805
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161238770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3161238770
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3649046808
Short name T341
Test name
Test status
Simulation time 2592196854 ps
CPU time 12.01 seconds
Started Jun 27 06:57:29 PM PDT 24
Finished Jun 27 06:57:41 PM PDT 24
Peak memory 211372 kb
Host smart-c7da5928-b2bb-4b86-8bcc-f998cba55d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649046808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3649046808
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1264866423
Short name T125
Test name
Test status
Simulation time 125459292971 ps
CPU time 156.66 seconds
Started Jun 27 06:57:29 PM PDT 24
Finished Jun 27 07:00:06 PM PDT 24
Peak memory 237832 kb
Host smart-df77ddb1-555e-45f7-b446-12f09373d59d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264866423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1264866423
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.801947448
Short name T93
Test name
Test status
Simulation time 994457978 ps
CPU time 15.67 seconds
Started Jun 27 06:57:30 PM PDT 24
Finished Jun 27 06:57:46 PM PDT 24
Peak memory 211360 kb
Host smart-3e99514f-9d65-44e3-bbee-0c68dc89bf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801947448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.801947448
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1647332576
Short name T223
Test name
Test status
Simulation time 6550174905 ps
CPU time 14.03 seconds
Started Jun 27 06:57:31 PM PDT 24
Finished Jun 27 06:57:46 PM PDT 24
Peak memory 211392 kb
Host smart-ef086927-817a-4ca9-b725-716c85ddb5ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647332576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1647332576
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.985302553
Short name T248
Test name
Test status
Simulation time 573837781 ps
CPU time 10.19 seconds
Started Jun 27 06:57:31 PM PDT 24
Finished Jun 27 06:57:42 PM PDT 24
Peak memory 213868 kb
Host smart-66e0dad9-0278-49c9-8de8-492ff3e21e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985302553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.985302553
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1797796534
Short name T243
Test name
Test status
Simulation time 225595383 ps
CPU time 10.27 seconds
Started Jun 27 06:57:28 PM PDT 24
Finished Jun 27 06:57:39 PM PDT 24
Peak memory 211188 kb
Host smart-5fa2d730-a577-41c9-8b1c-7e226ce62bd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797796534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1797796534
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.224892330
Short name T177
Test name
Test status
Simulation time 4092579851 ps
CPU time 10.74 seconds
Started Jun 27 06:57:43 PM PDT 24
Finished Jun 27 06:57:55 PM PDT 24
Peak memory 211348 kb
Host smart-05d267c1-18f6-4c52-bcc0-dc86b4263565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224892330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.224892330
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1059737541
Short name T296
Test name
Test status
Simulation time 89294151088 ps
CPU time 220.47 seconds
Started Jun 27 06:57:29 PM PDT 24
Finished Jun 27 07:01:10 PM PDT 24
Peak memory 237108 kb
Host smart-3d9e7279-e2fe-4fc3-9d27-63ad1059dbbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059737541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1059737541
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2149736973
Short name T140
Test name
Test status
Simulation time 4334885633 ps
CPU time 21.71 seconds
Started Jun 27 06:57:28 PM PDT 24
Finished Jun 27 06:57:50 PM PDT 24
Peak memory 212368 kb
Host smart-8b67fdea-cfaf-457d-bc80-f32e5f8c455c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149736973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2149736973
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.469801998
Short name T219
Test name
Test status
Simulation time 2093414930 ps
CPU time 8.51 seconds
Started Jun 27 06:57:32 PM PDT 24
Finished Jun 27 06:57:41 PM PDT 24
Peak memory 211356 kb
Host smart-956ba758-6cc5-4d9f-931d-0c38e886b73a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469801998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.469801998
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2232399981
Short name T212
Test name
Test status
Simulation time 2295774506 ps
CPU time 29.45 seconds
Started Jun 27 06:57:31 PM PDT 24
Finished Jun 27 06:58:01 PM PDT 24
Peak memory 213744 kb
Host smart-96d19322-9698-468c-83fd-3d601172c6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232399981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2232399981
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4088948635
Short name T190
Test name
Test status
Simulation time 868301267 ps
CPU time 19.1 seconds
Started Jun 27 06:57:27 PM PDT 24
Finished Jun 27 06:57:47 PM PDT 24
Peak memory 213540 kb
Host smart-b8f2c578-72e2-4fce-94e3-9eabc9bc056c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088948635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4088948635
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3289605561
Short name T364
Test name
Test status
Simulation time 77267874393 ps
CPU time 8837.68 seconds
Started Jun 27 06:57:44 PM PDT 24
Finished Jun 27 09:25:04 PM PDT 24
Peak memory 238376 kb
Host smart-d5df4b1c-a0a1-4dea-9abc-ef9684864f0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289605561 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3289605561
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.408643584
Short name T18
Test name
Test status
Simulation time 287994511 ps
CPU time 4.35 seconds
Started Jun 27 06:57:46 PM PDT 24
Finished Jun 27 06:57:53 PM PDT 24
Peak memory 211296 kb
Host smart-016ff6ea-5769-4c6b-ad0c-200e5bc2e984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408643584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.408643584
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1940808595
Short name T228
Test name
Test status
Simulation time 4614837381 ps
CPU time 66.82 seconds
Started Jun 27 06:57:42 PM PDT 24
Finished Jun 27 06:58:50 PM PDT 24
Peak memory 212620 kb
Host smart-66d4d048-bfc2-47a6-9f03-e671bf1c8d74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940808595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1940808595
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.361498069
Short name T286
Test name
Test status
Simulation time 17027044826 ps
CPU time 33.14 seconds
Started Jun 27 06:57:44 PM PDT 24
Finished Jun 27 06:58:18 PM PDT 24
Peak memory 212292 kb
Host smart-2ee7c5b5-0b0a-429c-9619-c3a785a89efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361498069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.361498069
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.805248339
Short name T152
Test name
Test status
Simulation time 107928281 ps
CPU time 5.79 seconds
Started Jun 27 06:57:43 PM PDT 24
Finished Jun 27 06:57:50 PM PDT 24
Peak memory 211308 kb
Host smart-7f5c92d2-29f8-4429-b92d-3b233c107994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=805248339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.805248339
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2013217182
Short name T284
Test name
Test status
Simulation time 186367849 ps
CPU time 10.22 seconds
Started Jun 27 06:57:43 PM PDT 24
Finished Jun 27 06:57:55 PM PDT 24
Peak memory 213164 kb
Host smart-1c1bd277-d837-4d04-b599-2fce956b974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013217182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2013217182
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1550701296
Short name T356
Test name
Test status
Simulation time 16783991517 ps
CPU time 84.27 seconds
Started Jun 27 06:57:42 PM PDT 24
Finished Jun 27 06:59:07 PM PDT 24
Peak memory 217396 kb
Host smart-119a20af-c58c-4eda-a95c-3537a97e2ec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550701296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1550701296
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3186335592
Short name T319
Test name
Test status
Simulation time 2577068911 ps
CPU time 11.87 seconds
Started Jun 27 06:57:45 PM PDT 24
Finished Jun 27 06:57:58 PM PDT 24
Peak memory 211324 kb
Host smart-6e50066b-4d84-4a12-ae93-550e0c8a7c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186335592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3186335592
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3286856023
Short name T143
Test name
Test status
Simulation time 49420745758 ps
CPU time 226.18 seconds
Started Jun 27 06:57:43 PM PDT 24
Finished Jun 27 07:01:31 PM PDT 24
Peak memory 225708 kb
Host smart-bd5366be-87b0-48a4-aea6-3455de99cace
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286856023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3286856023
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1735955964
Short name T315
Test name
Test status
Simulation time 3933769837 ps
CPU time 33.81 seconds
Started Jun 27 06:57:45 PM PDT 24
Finished Jun 27 06:58:20 PM PDT 24
Peak memory 211872 kb
Host smart-14e15953-727d-439f-a4d9-7a3c86702b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735955964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1735955964
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.226050907
Short name T256
Test name
Test status
Simulation time 18401396737 ps
CPU time 15.15 seconds
Started Jun 27 06:57:43 PM PDT 24
Finished Jun 27 06:58:00 PM PDT 24
Peak memory 211388 kb
Host smart-d10a20bc-e99e-4676-a9d5-330ee93111f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226050907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.226050907
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.439065367
Short name T242
Test name
Test status
Simulation time 2692363821 ps
CPU time 31.15 seconds
Started Jun 27 06:57:42 PM PDT 24
Finished Jun 27 06:58:14 PM PDT 24
Peak memory 213008 kb
Host smart-de2e2f47-4fe0-45a2-b1ea-54a7676f827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439065367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.439065367
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2471707012
Short name T325
Test name
Test status
Simulation time 26739235494 ps
CPU time 39.18 seconds
Started Jun 27 06:57:42 PM PDT 24
Finished Jun 27 06:58:23 PM PDT 24
Peak memory 217164 kb
Host smart-af09f23a-79df-47f8-8a30-bb750d486719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471707012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2471707012
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3190827483
Short name T60
Test name
Test status
Simulation time 2071866865 ps
CPU time 16.6 seconds
Started Jun 27 06:58:00 PM PDT 24
Finished Jun 27 06:58:19 PM PDT 24
Peak memory 211276 kb
Host smart-cced91e4-0d1d-424e-a7eb-4e60bf287931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190827483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3190827483
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.715388895
Short name T153
Test name
Test status
Simulation time 125560836896 ps
CPU time 253.37 seconds
Started Jun 27 06:58:01 PM PDT 24
Finished Jun 27 07:02:16 PM PDT 24
Peak memory 212552 kb
Host smart-ea319f6b-8dc4-42b4-9e19-1fc6e5cfd338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715388895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.715388895
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3802340711
Short name T357
Test name
Test status
Simulation time 2073837305 ps
CPU time 16.85 seconds
Started Jun 27 06:57:59 PM PDT 24
Finished Jun 27 06:58:17 PM PDT 24
Peak memory 211384 kb
Host smart-c3dcbb00-6545-4187-89c0-bb786f6d03ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3802340711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3802340711
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3443797581
Short name T305
Test name
Test status
Simulation time 3638899052 ps
CPU time 24.08 seconds
Started Jun 27 06:57:42 PM PDT 24
Finished Jun 27 06:58:08 PM PDT 24
Peak memory 213624 kb
Host smart-49fcb519-92f9-4fc3-b7ba-7430af38c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443797581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3443797581
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1923160583
Short name T294
Test name
Test status
Simulation time 1011057240 ps
CPU time 14.38 seconds
Started Jun 27 06:57:43 PM PDT 24
Finished Jun 27 06:57:59 PM PDT 24
Peak memory 211208 kb
Host smart-3d2f0695-b816-4209-93bb-2f971be8edc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923160583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1923160583
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4115503013
Short name T327
Test name
Test status
Simulation time 1280766545 ps
CPU time 11.39 seconds
Started Jun 27 06:58:01 PM PDT 24
Finished Jun 27 06:58:14 PM PDT 24
Peak memory 211288 kb
Host smart-2ab3f89c-b8ef-4fb2-8f2b-89bb138d7bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115503013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4115503013
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.654863988
Short name T149
Test name
Test status
Simulation time 44235007961 ps
CPU time 203.56 seconds
Started Jun 27 06:58:01 PM PDT 24
Finished Jun 27 07:01:27 PM PDT 24
Peak memory 234372 kb
Host smart-e9773320-5ca7-4945-95de-f2fc9c501758
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654863988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.654863988
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2728790679
Short name T244
Test name
Test status
Simulation time 3086830218 ps
CPU time 19.05 seconds
Started Jun 27 06:57:59 PM PDT 24
Finished Jun 27 06:58:20 PM PDT 24
Peak memory 212000 kb
Host smart-e4b22805-f746-4f86-8923-cd64b2dcea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728790679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2728790679
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.971666256
Short name T307
Test name
Test status
Simulation time 1159440748 ps
CPU time 11.7 seconds
Started Jun 27 06:58:00 PM PDT 24
Finished Jun 27 06:58:14 PM PDT 24
Peak memory 211328 kb
Host smart-9aea6c3c-db96-43dc-9df1-a2aa9922f8de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971666256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.971666256
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3956461353
Short name T163
Test name
Test status
Simulation time 274326577 ps
CPU time 11.92 seconds
Started Jun 27 06:58:03 PM PDT 24
Finished Jun 27 06:58:16 PM PDT 24
Peak memory 212400 kb
Host smart-4290be4c-742d-42ff-8af8-aa68934ecc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956461353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3956461353
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1134653909
Short name T109
Test name
Test status
Simulation time 280840829 ps
CPU time 17.99 seconds
Started Jun 27 06:58:01 PM PDT 24
Finished Jun 27 06:58:20 PM PDT 24
Peak memory 213536 kb
Host smart-dec6900b-da29-4e1e-90e9-a6c550b66ee4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134653909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1134653909
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1990386470
Short name T49
Test name
Test status
Simulation time 102506881111 ps
CPU time 1003.91 seconds
Started Jun 27 06:58:01 PM PDT 24
Finished Jun 27 07:14:47 PM PDT 24
Peak memory 235852 kb
Host smart-b1dfd293-ea7c-4bc1-95e7-ca0bdbb50cf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990386470 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1990386470
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2381025560
Short name T19
Test name
Test status
Simulation time 333167745 ps
CPU time 4.16 seconds
Started Jun 27 06:58:16 PM PDT 24
Finished Jun 27 06:58:22 PM PDT 24
Peak memory 211200 kb
Host smart-c8df286a-7489-48e1-ac26-af056fcc4727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381025560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2381025560
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2619737022
Short name T36
Test name
Test status
Simulation time 19300494541 ps
CPU time 177.31 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 07:01:16 PM PDT 24
Peak memory 228660 kb
Host smart-8e122923-f334-437c-85da-a80ba2e9675e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619737022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2619737022
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3849860834
Short name T21
Test name
Test status
Simulation time 31154902165 ps
CPU time 29.29 seconds
Started Jun 27 06:58:14 PM PDT 24
Finished Jun 27 06:58:45 PM PDT 24
Peak memory 212328 kb
Host smart-a51c9133-860b-4e19-ad98-5e4badf1905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849860834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3849860834
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.841046724
Short name T269
Test name
Test status
Simulation time 3532666271 ps
CPU time 15.28 seconds
Started Jun 27 06:58:00 PM PDT 24
Finished Jun 27 06:58:17 PM PDT 24
Peak memory 211332 kb
Host smart-115c8b28-e4ab-43bd-8a40-86efd4a27ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841046724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.841046724
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.771016152
Short name T142
Test name
Test status
Simulation time 5479008732 ps
CPU time 25.36 seconds
Started Jun 27 06:58:01 PM PDT 24
Finished Jun 27 06:58:28 PM PDT 24
Peak memory 213568 kb
Host smart-82cc3221-4643-4a55-b633-ff2312243db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771016152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.771016152
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.185248512
Short name T92
Test name
Test status
Simulation time 668209166 ps
CPU time 36.87 seconds
Started Jun 27 06:58:01 PM PDT 24
Finished Jun 27 06:58:39 PM PDT 24
Peak memory 216004 kb
Host smart-a9c531bf-abc9-4906-8959-c1f4a3a95be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185248512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.185248512
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3439000909
Short name T150
Test name
Test status
Simulation time 896563849 ps
CPU time 9.24 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 06:58:27 PM PDT 24
Peak memory 211208 kb
Host smart-fa805c9b-32b3-4b0a-9b72-eb3846fcc54c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439000909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3439000909
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1480875169
Short name T173
Test name
Test status
Simulation time 2449808088 ps
CPU time 75.82 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 06:59:33 PM PDT 24
Peak memory 237788 kb
Host smart-86f4adcb-1a5d-48b0-a4f1-3d903213fa03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480875169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1480875169
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1339980981
Short name T209
Test name
Test status
Simulation time 3513495957 ps
CPU time 30.11 seconds
Started Jun 27 06:58:14 PM PDT 24
Finished Jun 27 06:58:46 PM PDT 24
Peak memory 212028 kb
Host smart-826325a3-7884-4366-b590-9740d96effc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339980981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1339980981
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3803814839
Short name T208
Test name
Test status
Simulation time 1900750799 ps
CPU time 16.44 seconds
Started Jun 27 06:58:14 PM PDT 24
Finished Jun 27 06:58:32 PM PDT 24
Peak memory 211332 kb
Host smart-6fd40184-df64-4620-8299-42c5bc13b06a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803814839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3803814839
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2075866071
Short name T252
Test name
Test status
Simulation time 5676177345 ps
CPU time 18.01 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 06:58:36 PM PDT 24
Peak memory 213716 kb
Host smart-34531502-eec6-4fc4-8c09-f41d63c95756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075866071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2075866071
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3300229438
Short name T352
Test name
Test status
Simulation time 15029003106 ps
CPU time 14.8 seconds
Started Jun 27 06:58:16 PM PDT 24
Finished Jun 27 06:58:34 PM PDT 24
Peak memory 211280 kb
Host smart-016f65ed-8ffb-4c66-8328-3abc24c7e5d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300229438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3300229438
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1901667014
Short name T227
Test name
Test status
Simulation time 680128634 ps
CPU time 8.52 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 06:58:25 PM PDT 24
Peak memory 211264 kb
Host smart-0909aac6-96e6-46ff-ac78-a339b2487c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901667014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1901667014
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3355669125
Short name T251
Test name
Test status
Simulation time 204919515462 ps
CPU time 192.62 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 07:01:30 PM PDT 24
Peak memory 213648 kb
Host smart-f44c0954-97ef-4cd0-98f5-7d51312d6c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355669125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3355669125
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3738181368
Short name T254
Test name
Test status
Simulation time 55972893252 ps
CPU time 35.38 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 06:58:53 PM PDT 24
Peak memory 212232 kb
Host smart-ae1ef895-31e8-4d2e-9656-9b326b0d7a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738181368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3738181368
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3312163062
Short name T31
Test name
Test status
Simulation time 97260003 ps
CPU time 5.29 seconds
Started Jun 27 06:58:16 PM PDT 24
Finished Jun 27 06:58:24 PM PDT 24
Peak memory 211352 kb
Host smart-0684cccc-d728-40b2-879b-4fc6aa6ba54a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312163062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3312163062
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2029302149
Short name T28
Test name
Test status
Simulation time 9502537478 ps
CPU time 21.46 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 06:58:39 PM PDT 24
Peak memory 212668 kb
Host smart-117975e7-c17c-4eb0-b596-06ffacc118f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029302149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2029302149
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1032796313
Short name T181
Test name
Test status
Simulation time 2569166147 ps
CPU time 26.22 seconds
Started Jun 27 06:58:14 PM PDT 24
Finished Jun 27 06:58:43 PM PDT 24
Peak memory 213404 kb
Host smart-407a48a1-2405-467c-93a7-edcb41cc3fbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032796313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1032796313
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.49401700
Short name T323
Test name
Test status
Simulation time 5719945777 ps
CPU time 10.7 seconds
Started Jun 27 06:58:16 PM PDT 24
Finished Jun 27 06:58:29 PM PDT 24
Peak memory 211356 kb
Host smart-60316cec-cf68-40a4-8ee8-780383570176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49401700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.49401700
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3651061560
Short name T192
Test name
Test status
Simulation time 94539376513 ps
CPU time 265.37 seconds
Started Jun 27 06:58:14 PM PDT 24
Finished Jun 27 07:02:41 PM PDT 24
Peak memory 237864 kb
Host smart-1e1cd290-2a26-4ffe-86c8-460716f5e7d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651061560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3651061560
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4156428892
Short name T218
Test name
Test status
Simulation time 6531466168 ps
CPU time 19.58 seconds
Started Jun 27 06:58:14 PM PDT 24
Finished Jun 27 06:58:36 PM PDT 24
Peak memory 212664 kb
Host smart-cbb0da3f-70e7-453e-94a4-0150a8a5c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156428892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4156428892
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1339199499
Short name T13
Test name
Test status
Simulation time 14028069663 ps
CPU time 24.4 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 06:58:42 PM PDT 24
Peak memory 213712 kb
Host smart-2308dbae-bff3-40ce-b441-0e749f737d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339199499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1339199499
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.657896435
Short name T273
Test name
Test status
Simulation time 3330079664 ps
CPU time 30.78 seconds
Started Jun 27 06:58:14 PM PDT 24
Finished Jun 27 06:58:47 PM PDT 24
Peak memory 215052 kb
Host smart-d2cee752-fcf7-4167-9eae-1caeb7033bc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657896435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.657896435
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2045476240
Short name T47
Test name
Test status
Simulation time 39862019371 ps
CPU time 416.16 seconds
Started Jun 27 06:58:14 PM PDT 24
Finished Jun 27 07:05:12 PM PDT 24
Peak memory 227896 kb
Host smart-a3df3537-e100-489c-a910-cf2aa4449c47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045476240 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2045476240
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3284570298
Short name T343
Test name
Test status
Simulation time 1880600755 ps
CPU time 9.31 seconds
Started Jun 27 06:57:00 PM PDT 24
Finished Jun 27 06:57:10 PM PDT 24
Peak memory 211280 kb
Host smart-5918359a-800b-48d1-a223-a92e666b1f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284570298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3284570298
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1374036258
Short name T259
Test name
Test status
Simulation time 8198126567 ps
CPU time 166.58 seconds
Started Jun 27 06:57:02 PM PDT 24
Finished Jun 27 06:59:51 PM PDT 24
Peak memory 237864 kb
Host smart-38ef18e9-95f9-473b-9dc3-c6e54c2646fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374036258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1374036258
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3021924646
Short name T225
Test name
Test status
Simulation time 15633102295 ps
CPU time 31.21 seconds
Started Jun 27 06:57:02 PM PDT 24
Finished Jun 27 06:57:35 PM PDT 24
Peak memory 212652 kb
Host smart-1827d399-d8a5-4491-8058-5f7b5dc6a620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021924646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3021924646
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2328374165
Short name T267
Test name
Test status
Simulation time 4941330044 ps
CPU time 16.73 seconds
Started Jun 27 06:57:00 PM PDT 24
Finished Jun 27 06:57:18 PM PDT 24
Peak memory 211400 kb
Host smart-e05c6177-f216-4245-a1c5-23dfa6c2d03e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328374165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2328374165
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1562411893
Short name T23
Test name
Test status
Simulation time 1718467600 ps
CPU time 60.21 seconds
Started Jun 27 06:57:00 PM PDT 24
Finished Jun 27 06:58:03 PM PDT 24
Peak memory 236616 kb
Host smart-acd53b35-8d77-4b16-9db1-7fd4fd4301a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562411893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1562411893
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3011563005
Short name T293
Test name
Test status
Simulation time 10547519624 ps
CPU time 34.32 seconds
Started Jun 27 06:57:02 PM PDT 24
Finished Jun 27 06:57:39 PM PDT 24
Peak memory 214016 kb
Host smart-b3a46013-974b-4aad-ae32-5beb21b5fb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011563005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3011563005
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.913916497
Short name T234
Test name
Test status
Simulation time 21383490889 ps
CPU time 53.65 seconds
Started Jun 27 06:57:02 PM PDT 24
Finished Jun 27 06:57:58 PM PDT 24
Peak memory 219448 kb
Host smart-b0bb9157-d52d-4594-afd9-beb8c1253625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913916497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.913916497
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2319566445
Short name T96
Test name
Test status
Simulation time 216726995 ps
CPU time 5.88 seconds
Started Jun 27 06:58:28 PM PDT 24
Finished Jun 27 06:58:35 PM PDT 24
Peak memory 211288 kb
Host smart-e4a01799-a649-4c88-ac38-e3179a60c5fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319566445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2319566445
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.50510439
Short name T353
Test name
Test status
Simulation time 309029748724 ps
CPU time 156.44 seconds
Started Jun 27 06:58:16 PM PDT 24
Finished Jun 27 07:00:55 PM PDT 24
Peak memory 237836 kb
Host smart-d1b3e50a-87a8-469e-8ef2-84c78601a5e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50510439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_co
rrupt_sig_fatal_chk.50510439
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3504993495
Short name T226
Test name
Test status
Simulation time 3506114471 ps
CPU time 29.68 seconds
Started Jun 27 06:58:16 PM PDT 24
Finished Jun 27 06:58:48 PM PDT 24
Peak memory 211388 kb
Host smart-9e571fb6-3121-4f1b-a227-5658ec646564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504993495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3504993495
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.171325025
Short name T238
Test name
Test status
Simulation time 2107564329 ps
CPU time 17.07 seconds
Started Jun 27 06:58:16 PM PDT 24
Finished Jun 27 06:58:36 PM PDT 24
Peak memory 211340 kb
Host smart-4e4fb3f3-ac48-4c83-bc09-fbe025938bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171325025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.171325025
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.428085286
Short name T358
Test name
Test status
Simulation time 3500777832 ps
CPU time 29.58 seconds
Started Jun 27 06:58:16 PM PDT 24
Finished Jun 27 06:58:48 PM PDT 24
Peak memory 213156 kb
Host smart-2cdbdd49-fbc6-45ca-ac4e-c760329a7c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428085286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.428085286
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2508995021
Short name T4
Test name
Test status
Simulation time 2853010742 ps
CPU time 48.44 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 06:59:06 PM PDT 24
Peak memory 216292 kb
Host smart-dc2127e2-b964-47e1-aa33-b3973e5e66b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508995021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2508995021
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.4033248272
Short name T331
Test name
Test status
Simulation time 29913945480 ps
CPU time 751.49 seconds
Started Jun 27 06:58:15 PM PDT 24
Finished Jun 27 07:10:50 PM PDT 24
Peak memory 234652 kb
Host smart-00e0c292-83c3-4b77-9c00-f959e17c97fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033248272 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.4033248272
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4267380554
Short name T261
Test name
Test status
Simulation time 3130854137 ps
CPU time 13.6 seconds
Started Jun 27 06:58:29 PM PDT 24
Finished Jun 27 06:58:44 PM PDT 24
Peak memory 211376 kb
Host smart-ebfc95ad-bf66-4257-b71b-8a2947e51511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267380554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4267380554
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3170072339
Short name T151
Test name
Test status
Simulation time 26576455746 ps
CPU time 90.6 seconds
Started Jun 27 06:58:28 PM PDT 24
Finished Jun 27 07:00:00 PM PDT 24
Peak memory 237892 kb
Host smart-c09c2cf6-391c-41f2-a808-1d2e50b36533
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170072339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3170072339
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1562066643
Short name T289
Test name
Test status
Simulation time 594800823 ps
CPU time 9.35 seconds
Started Jun 27 06:58:28 PM PDT 24
Finished Jun 27 06:58:38 PM PDT 24
Peak memory 211892 kb
Host smart-e56e1653-4312-4a05-a930-9464fd4b4b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562066643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1562066643
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1087744014
Short name T280
Test name
Test status
Simulation time 1937399549 ps
CPU time 16.38 seconds
Started Jun 27 06:58:29 PM PDT 24
Finished Jun 27 06:58:47 PM PDT 24
Peak memory 211368 kb
Host smart-9b3b767d-09ef-47d4-ba97-10be2782df04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087744014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1087744014
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2122205398
Short name T12
Test name
Test status
Simulation time 6631211515 ps
CPU time 22.86 seconds
Started Jun 27 06:58:30 PM PDT 24
Finished Jun 27 06:58:54 PM PDT 24
Peak memory 213776 kb
Host smart-b978a3bb-ce36-4160-b640-912cd571488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122205398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2122205398
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4066851958
Short name T335
Test name
Test status
Simulation time 44717234599 ps
CPU time 44.92 seconds
Started Jun 27 06:58:33 PM PDT 24
Finished Jun 27 06:59:19 PM PDT 24
Peak memory 215724 kb
Host smart-667b3d8f-03ad-40e7-8b2c-755b4660ec00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066851958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4066851958
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3529851342
Short name T51
Test name
Test status
Simulation time 45870465861 ps
CPU time 1458.78 seconds
Started Jun 27 06:58:29 PM PDT 24
Finished Jun 27 07:22:50 PM PDT 24
Peak memory 236048 kb
Host smart-cb421df6-6cfb-4ded-a7b1-b74b499d560e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529851342 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3529851342
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3588449892
Short name T161
Test name
Test status
Simulation time 1752796973 ps
CPU time 12.14 seconds
Started Jun 27 06:58:30 PM PDT 24
Finished Jun 27 06:58:44 PM PDT 24
Peak memory 211316 kb
Host smart-04dc6186-a628-4f83-b52a-93f8d58b4ba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588449892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3588449892
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3905761257
Short name T169
Test name
Test status
Simulation time 10938636786 ps
CPU time 154.63 seconds
Started Jun 27 06:58:29 PM PDT 24
Finished Jun 27 07:01:06 PM PDT 24
Peak memory 237476 kb
Host smart-c42f8eba-ebc2-4593-aaef-8707b8b6e121
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905761257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3905761257
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1485863945
Short name T306
Test name
Test status
Simulation time 1056816103 ps
CPU time 13.12 seconds
Started Jun 27 06:58:27 PM PDT 24
Finished Jun 27 06:58:41 PM PDT 24
Peak memory 211924 kb
Host smart-0e637caa-c24b-4685-94c0-18e7304b9135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485863945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1485863945
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3334251467
Short name T144
Test name
Test status
Simulation time 1183042235 ps
CPU time 11.92 seconds
Started Jun 27 06:58:27 PM PDT 24
Finished Jun 27 06:58:40 PM PDT 24
Peak memory 211328 kb
Host smart-59c6a942-e6af-49d3-8107-50575d341c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3334251467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3334251467
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.499668865
Short name T170
Test name
Test status
Simulation time 11665477918 ps
CPU time 18.67 seconds
Started Jun 27 06:58:27 PM PDT 24
Finished Jun 27 06:58:47 PM PDT 24
Peak memory 214172 kb
Host smart-1ea27720-f36f-4ee4-a9eb-f8fc984788da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499668865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.499668865
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2329769222
Short name T27
Test name
Test status
Simulation time 4072422112 ps
CPU time 66.16 seconds
Started Jun 27 06:58:27 PM PDT 24
Finished Jun 27 06:59:34 PM PDT 24
Peak memory 216924 kb
Host smart-78ec5f5a-3437-476e-adee-a4a3174645e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329769222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2329769222
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3805930577
Short name T340
Test name
Test status
Simulation time 2924306271 ps
CPU time 9.18 seconds
Started Jun 27 06:58:30 PM PDT 24
Finished Jun 27 06:58:41 PM PDT 24
Peak memory 211356 kb
Host smart-42dc0bd4-5859-4db5-a462-128738da1c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805930577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3805930577
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1893227697
Short name T40
Test name
Test status
Simulation time 41820460566 ps
CPU time 237.13 seconds
Started Jun 27 06:58:31 PM PDT 24
Finished Jun 27 07:02:29 PM PDT 24
Peak memory 213560 kb
Host smart-e4f55b67-c31f-4735-bbe9-850e36619cef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893227697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1893227697
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.519081498
Short name T186
Test name
Test status
Simulation time 6980048449 ps
CPU time 29.06 seconds
Started Jun 27 06:58:29 PM PDT 24
Finished Jun 27 06:59:00 PM PDT 24
Peak memory 212540 kb
Host smart-580e954f-bc3c-45a1-8048-41d755f8c384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519081498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.519081498
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3147775080
Short name T322
Test name
Test status
Simulation time 798378103 ps
CPU time 9.71 seconds
Started Jun 27 06:58:30 PM PDT 24
Finished Jun 27 06:58:42 PM PDT 24
Peak memory 211348 kb
Host smart-4794225f-013f-4320-911d-42e6c139dac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147775080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3147775080
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.124725496
Short name T199
Test name
Test status
Simulation time 2397521115 ps
CPU time 23.08 seconds
Started Jun 27 06:58:27 PM PDT 24
Finished Jun 27 06:58:50 PM PDT 24
Peak memory 213360 kb
Host smart-ec26af50-bd88-4e21-97b4-c6a83b37d1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124725496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.124725496
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.973182219
Short name T235
Test name
Test status
Simulation time 26384729915 ps
CPU time 44.52 seconds
Started Jun 27 06:58:32 PM PDT 24
Finished Jun 27 06:59:18 PM PDT 24
Peak memory 217184 kb
Host smart-8f874c53-e85e-479a-80ab-5b26c9e4f799
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973182219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.973182219
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1797441129
Short name T285
Test name
Test status
Simulation time 444074010688 ps
CPU time 3191.9 seconds
Started Jun 27 06:58:28 PM PDT 24
Finished Jun 27 07:51:42 PM PDT 24
Peak memory 247980 kb
Host smart-ad8a48e8-3084-4b14-9e73-0fcdaaa680e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797441129 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1797441129
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3006434647
Short name T345
Test name
Test status
Simulation time 1312003695 ps
CPU time 12.33 seconds
Started Jun 27 06:58:32 PM PDT 24
Finished Jun 27 06:58:46 PM PDT 24
Peak memory 211280 kb
Host smart-42676831-ada5-4975-a893-7861fa0d5f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006434647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3006434647
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3226014108
Short name T166
Test name
Test status
Simulation time 35730029465 ps
CPU time 112.48 seconds
Started Jun 27 06:58:30 PM PDT 24
Finished Jun 27 07:00:24 PM PDT 24
Peak memory 213080 kb
Host smart-6078663a-577b-4a5b-b47b-eb52d7403332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226014108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3226014108
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1297289938
Short name T138
Test name
Test status
Simulation time 1322216489 ps
CPU time 14.51 seconds
Started Jun 27 06:58:28 PM PDT 24
Finished Jun 27 06:58:45 PM PDT 24
Peak memory 211884 kb
Host smart-4c217cd4-bdae-4415-9cab-420fde4ba3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297289938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1297289938
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.626805908
Short name T174
Test name
Test status
Simulation time 1779799352 ps
CPU time 15.57 seconds
Started Jun 27 06:58:30 PM PDT 24
Finished Jun 27 06:58:47 PM PDT 24
Peak memory 211296 kb
Host smart-8e2c8801-c1e1-44d8-902e-4cdfcc36fb8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626805908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.626805908
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.596677536
Short name T215
Test name
Test status
Simulation time 14199437973 ps
CPU time 34.32 seconds
Started Jun 27 06:58:31 PM PDT 24
Finished Jun 27 06:59:07 PM PDT 24
Peak memory 213960 kb
Host smart-5ea92c06-e5d1-4665-b7f2-dd84ee946e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596677536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.596677536
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4168967105
Short name T9
Test name
Test status
Simulation time 14046093122 ps
CPU time 45.74 seconds
Started Jun 27 06:58:28 PM PDT 24
Finished Jun 27 06:59:15 PM PDT 24
Peak memory 214304 kb
Host smart-c8ecdc19-d483-4615-81f5-097617f54ac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168967105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4168967105
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1210696660
Short name T58
Test name
Test status
Simulation time 1585076158 ps
CPU time 13.46 seconds
Started Jun 27 06:58:43 PM PDT 24
Finished Jun 27 06:58:57 PM PDT 24
Peak memory 211280 kb
Host smart-1fc58ed3-ab3e-493b-b146-09e71ccfccdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210696660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1210696660
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3926089186
Short name T42
Test name
Test status
Simulation time 347950144 ps
CPU time 9.37 seconds
Started Jun 27 06:58:44 PM PDT 24
Finished Jun 27 06:58:55 PM PDT 24
Peak memory 212116 kb
Host smart-9dfabf51-59bf-4462-8e48-9a7e5480e62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926089186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3926089186
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4143055187
Short name T135
Test name
Test status
Simulation time 1556298226 ps
CPU time 10.23 seconds
Started Jun 27 06:58:43 PM PDT 24
Finished Jun 27 06:58:55 PM PDT 24
Peak memory 211312 kb
Host smart-d3840c6f-3695-412d-97c4-c04aecd67a95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143055187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4143055187
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1614075256
Short name T76
Test name
Test status
Simulation time 4210634600 ps
CPU time 39.35 seconds
Started Jun 27 06:58:32 PM PDT 24
Finished Jun 27 06:59:13 PM PDT 24
Peak memory 213620 kb
Host smart-98a35a41-4e19-41dd-ae7f-b31d077cb238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614075256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1614075256
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3981073167
Short name T207
Test name
Test status
Simulation time 8091343473 ps
CPU time 19.49 seconds
Started Jun 27 06:58:30 PM PDT 24
Finished Jun 27 06:58:51 PM PDT 24
Peak memory 211444 kb
Host smart-c7e4f592-3698-49a5-973e-4dca47a7c1a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981073167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3981073167
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3064393543
Short name T240
Test name
Test status
Simulation time 1269640632 ps
CPU time 11.89 seconds
Started Jun 27 06:58:44 PM PDT 24
Finished Jun 27 06:58:57 PM PDT 24
Peak memory 211260 kb
Host smart-7630e88f-d1dc-48f1-a0b3-beb49aa19ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064393543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3064393543
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.472192539
Short name T237
Test name
Test status
Simulation time 796458560953 ps
CPU time 448.45 seconds
Started Jun 27 06:58:45 PM PDT 24
Finished Jun 27 07:06:15 PM PDT 24
Peak memory 233784 kb
Host smart-d688bf2b-0f6d-4d8b-83d0-0fc61b3e307e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472192539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.472192539
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.87400109
Short name T313
Test name
Test status
Simulation time 20831186775 ps
CPU time 34.2 seconds
Started Jun 27 06:58:43 PM PDT 24
Finished Jun 27 06:59:19 PM PDT 24
Peak memory 211412 kb
Host smart-09fc099a-9ea0-4ea7-ad54-da6631296ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87400109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.87400109
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.432807050
Short name T329
Test name
Test status
Simulation time 20446723823 ps
CPU time 13.99 seconds
Started Jun 27 06:58:44 PM PDT 24
Finished Jun 27 06:59:00 PM PDT 24
Peak memory 211388 kb
Host smart-5a82e976-1576-4758-bec6-882a17960eb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432807050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.432807050
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.39017221
Short name T72
Test name
Test status
Simulation time 3423519365 ps
CPU time 22.76 seconds
Started Jun 27 06:58:43 PM PDT 24
Finished Jun 27 06:59:08 PM PDT 24
Peak memory 213404 kb
Host smart-bb7a4bfa-1243-4d87-bf0f-90c8a75f0e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39017221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.39017221
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.502708689
Short name T299
Test name
Test status
Simulation time 9631235471 ps
CPU time 29.1 seconds
Started Jun 27 06:58:45 PM PDT 24
Finished Jun 27 06:59:15 PM PDT 24
Peak memory 214840 kb
Host smart-7c90c249-e378-4a5a-aa0b-32b7cd5568d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502708689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.502708689
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.266457302
Short name T147
Test name
Test status
Simulation time 171686425 ps
CPU time 4.26 seconds
Started Jun 27 06:58:45 PM PDT 24
Finished Jun 27 06:58:51 PM PDT 24
Peak memory 211276 kb
Host smart-d43d4e29-dcfd-48ff-bd53-c69bd1b09f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266457302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.266457302
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2530034749
Short name T191
Test name
Test status
Simulation time 27238664295 ps
CPU time 177.29 seconds
Started Jun 27 06:58:46 PM PDT 24
Finished Jun 27 07:01:45 PM PDT 24
Peak memory 238888 kb
Host smart-f76f9e1d-9553-4c64-9fc9-f2b93208479d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530034749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2530034749
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3616723904
Short name T249
Test name
Test status
Simulation time 16852923067 ps
CPU time 28.99 seconds
Started Jun 27 06:58:45 PM PDT 24
Finished Jun 27 06:59:16 PM PDT 24
Peak memory 212356 kb
Host smart-6a88cef4-19bb-4e76-9954-44dcd18fe8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616723904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3616723904
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1654971564
Short name T266
Test name
Test status
Simulation time 542760097 ps
CPU time 5.82 seconds
Started Jun 27 06:58:43 PM PDT 24
Finished Jun 27 06:58:50 PM PDT 24
Peak memory 211332 kb
Host smart-869e7621-54de-4e6e-8214-a76d9f455e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1654971564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1654971564
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1594092259
Short name T165
Test name
Test status
Simulation time 16519574632 ps
CPU time 37.45 seconds
Started Jun 27 06:58:43 PM PDT 24
Finished Jun 27 06:59:21 PM PDT 24
Peak memory 214244 kb
Host smart-b464f9b4-316f-417a-b175-fefe5346717b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594092259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1594092259
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3177396394
Short name T112
Test name
Test status
Simulation time 5236936478 ps
CPU time 46.54 seconds
Started Jun 27 06:58:45 PM PDT 24
Finished Jun 27 06:59:33 PM PDT 24
Peak memory 216708 kb
Host smart-064efa0a-34ae-490f-bad6-a0ddace2cde4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177396394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3177396394
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.943743241
Short name T184
Test name
Test status
Simulation time 7424522579 ps
CPU time 17.47 seconds
Started Jun 27 06:58:46 PM PDT 24
Finished Jun 27 06:59:06 PM PDT 24
Peak memory 211344 kb
Host smart-2cc22480-2740-40e8-9246-58b0badf2dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943743241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.943743241
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1758951332
Short name T328
Test name
Test status
Simulation time 28433742591 ps
CPU time 285.18 seconds
Started Jun 27 06:58:45 PM PDT 24
Finished Jun 27 07:03:32 PM PDT 24
Peak memory 237876 kb
Host smart-39e01ff4-6dd0-4427-b6a8-6ff3636e2e0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758951332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1758951332
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3467765464
Short name T363
Test name
Test status
Simulation time 617106637 ps
CPU time 9.75 seconds
Started Jun 27 06:58:44 PM PDT 24
Finished Jun 27 06:58:56 PM PDT 24
Peak memory 211860 kb
Host smart-f38f8dec-7199-4f63-986f-322779a56355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467765464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3467765464
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.691673670
Short name T130
Test name
Test status
Simulation time 7352568550 ps
CPU time 16.44 seconds
Started Jun 27 06:58:45 PM PDT 24
Finished Jun 27 06:59:04 PM PDT 24
Peak memory 211388 kb
Host smart-b66e2e04-9b6d-450e-aef0-fa7613963efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691673670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.691673670
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2294577128
Short name T255
Test name
Test status
Simulation time 7861682617 ps
CPU time 40.89 seconds
Started Jun 27 06:58:41 PM PDT 24
Finished Jun 27 06:59:23 PM PDT 24
Peak memory 212676 kb
Host smart-3ec065cf-2664-40d8-bddf-75537af38d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294577128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2294577128
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4144854340
Short name T301
Test name
Test status
Simulation time 2902473049 ps
CPU time 23.91 seconds
Started Jun 27 06:58:45 PM PDT 24
Finished Jun 27 06:59:10 PM PDT 24
Peak memory 216428 kb
Host smart-d0ec2b5f-98c1-4e8b-9863-1f4ee755ee6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144854340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4144854340
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2672045767
Short name T368
Test name
Test status
Simulation time 23918519452 ps
CPU time 11.84 seconds
Started Jun 27 06:59:06 PM PDT 24
Finished Jun 27 06:59:19 PM PDT 24
Peak memory 211380 kb
Host smart-8e85f57e-4ae2-421f-b4bc-6e3861dbb186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672045767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2672045767
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3110186301
Short name T220
Test name
Test status
Simulation time 8054641579 ps
CPU time 164.7 seconds
Started Jun 27 06:59:07 PM PDT 24
Finished Jun 27 07:01:53 PM PDT 24
Peak memory 234288 kb
Host smart-146889ab-6534-4954-9f9c-64888a138179
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110186301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3110186301
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.263049540
Short name T281
Test name
Test status
Simulation time 18866754043 ps
CPU time 31.99 seconds
Started Jun 27 06:59:06 PM PDT 24
Finished Jun 27 06:59:40 PM PDT 24
Peak memory 211880 kb
Host smart-9c25b5fc-ee88-4337-9334-06aa7b214614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263049540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.263049540
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1185613754
Short name T179
Test name
Test status
Simulation time 2774726078 ps
CPU time 9.4 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 06:59:14 PM PDT 24
Peak memory 211408 kb
Host smart-b2de5773-9134-4d06-a105-f512dbc278b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185613754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1185613754
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1945270625
Short name T277
Test name
Test status
Simulation time 7375803205 ps
CPU time 22.71 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 06:59:29 PM PDT 24
Peak memory 213868 kb
Host smart-75cf0084-4ed4-4260-ad12-0e37a9a652af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945270625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1945270625
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4143867542
Short name T346
Test name
Test status
Simulation time 30891807696 ps
CPU time 75.79 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 07:00:21 PM PDT 24
Peak memory 219384 kb
Host smart-4a7c8d13-627e-4657-9f78-010682d30efe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143867542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4143867542
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.305336528
Short name T59
Test name
Test status
Simulation time 1929617523 ps
CPU time 10.4 seconds
Started Jun 27 06:57:00 PM PDT 24
Finished Jun 27 06:57:11 PM PDT 24
Peak memory 211324 kb
Host smart-77ec080b-6ecf-4de4-ad28-08c63700f9cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305336528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.305336528
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2251396042
Short name T22
Test name
Test status
Simulation time 4354721616 ps
CPU time 33.72 seconds
Started Jun 27 06:57:01 PM PDT 24
Finished Jun 27 06:57:37 PM PDT 24
Peak memory 212320 kb
Host smart-eb5e2bd9-6f60-400c-8f8a-2565d6c616a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251396042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2251396042
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2562511405
Short name T287
Test name
Test status
Simulation time 1202601550 ps
CPU time 12.14 seconds
Started Jun 27 06:57:02 PM PDT 24
Finished Jun 27 06:57:16 PM PDT 24
Peak memory 211332 kb
Host smart-67fdb25b-6bbb-4fd4-86cd-2d80e49301cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562511405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2562511405
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2428026088
Short name T348
Test name
Test status
Simulation time 755632909 ps
CPU time 10.29 seconds
Started Jun 27 06:57:01 PM PDT 24
Finished Jun 27 06:57:13 PM PDT 24
Peak memory 214000 kb
Host smart-4e054e0f-2915-4b33-bee0-45e778460285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428026088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2428026088
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2298975466
Short name T176
Test name
Test status
Simulation time 2622960720 ps
CPU time 40.58 seconds
Started Jun 27 06:57:04 PM PDT 24
Finished Jun 27 06:57:46 PM PDT 24
Peak memory 216712 kb
Host smart-5623d47b-891d-4e0c-aca5-4b57641ed383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298975466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2298975466
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1288185152
Short name T114
Test name
Test status
Simulation time 173079893891 ps
CPU time 1879.95 seconds
Started Jun 27 06:57:01 PM PDT 24
Finished Jun 27 07:28:23 PM PDT 24
Peak memory 238212 kb
Host smart-9b2eb61d-f2f3-4991-bba3-905df3141ab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288185152 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1288185152
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1285835233
Short name T146
Test name
Test status
Simulation time 164862826 ps
CPU time 4.25 seconds
Started Jun 27 06:59:07 PM PDT 24
Finished Jun 27 06:59:12 PM PDT 24
Peak memory 211288 kb
Host smart-6a1e1d66-2867-4faf-b850-2b157d289f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285835233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1285835233
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2197868772
Short name T264
Test name
Test status
Simulation time 987620499 ps
CPU time 55.63 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 07:00:01 PM PDT 24
Peak memory 212464 kb
Host smart-9156addf-e91b-402a-a6fc-c179027c8ae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197868772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2197868772
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2940930832
Short name T274
Test name
Test status
Simulation time 8244629205 ps
CPU time 21.48 seconds
Started Jun 27 06:59:07 PM PDT 24
Finished Jun 27 06:59:30 PM PDT 24
Peak memory 212400 kb
Host smart-49bbb014-dc8f-454e-b1b0-1bccae880b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940930832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2940930832
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.576999650
Short name T320
Test name
Test status
Simulation time 7689072984 ps
CPU time 12.38 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 06:59:18 PM PDT 24
Peak memory 211380 kb
Host smart-cf858f57-2747-4493-8de3-645a89ed55d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576999650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.576999650
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.856618715
Short name T205
Test name
Test status
Simulation time 2233234856 ps
CPU time 22.85 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 06:59:28 PM PDT 24
Peak memory 213376 kb
Host smart-5a6ec36a-a09e-4d94-82cb-f1293662e298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856618715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.856618715
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3100288788
Short name T110
Test name
Test status
Simulation time 7119896475 ps
CPU time 15.71 seconds
Started Jun 27 06:59:06 PM PDT 24
Finished Jun 27 06:59:24 PM PDT 24
Peak memory 210964 kb
Host smart-fdf495a8-457a-468b-9c2d-703c28a31d29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100288788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3100288788
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2891743731
Short name T330
Test name
Test status
Simulation time 26456425350 ps
CPU time 1018.04 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 07:16:04 PM PDT 24
Peak memory 235824 kb
Host smart-94ea11cc-1a45-4379-b0be-2dbb8d7e875a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891743731 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2891743731
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3500057234
Short name T57
Test name
Test status
Simulation time 85714618 ps
CPU time 4.33 seconds
Started Jun 27 06:59:05 PM PDT 24
Finished Jun 27 06:59:11 PM PDT 24
Peak memory 211284 kb
Host smart-2c7461a2-745e-4383-b8e7-8ac33718e38b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500057234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3500057234
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2290106914
Short name T290
Test name
Test status
Simulation time 11373399186 ps
CPU time 130.3 seconds
Started Jun 27 06:59:05 PM PDT 24
Finished Jun 27 07:01:17 PM PDT 24
Peak memory 232848 kb
Host smart-20eb9a8e-795e-4863-b8c2-f3ce513bd7e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290106914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2290106914
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.41754520
Short name T134
Test name
Test status
Simulation time 13119999923 ps
CPU time 29.71 seconds
Started Jun 27 06:59:06 PM PDT 24
Finished Jun 27 06:59:37 PM PDT 24
Peak memory 212224 kb
Host smart-de3d205b-b7ac-4b95-8b12-aea89b26c184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41754520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.41754520
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3619717445
Short name T344
Test name
Test status
Simulation time 9202570219 ps
CPU time 17.17 seconds
Started Jun 27 06:59:05 PM PDT 24
Finished Jun 27 06:59:24 PM PDT 24
Peak memory 211348 kb
Host smart-4766d315-b981-4d12-842f-88cb936a057d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619717445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3619717445
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2287637425
Short name T202
Test name
Test status
Simulation time 4353596023 ps
CPU time 22.1 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 06:59:28 PM PDT 24
Peak memory 213932 kb
Host smart-d52d693d-f5ef-46f4-bbdc-31ea1f5e84f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287637425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2287637425
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2137315432
Short name T182
Test name
Test status
Simulation time 2496170101 ps
CPU time 32.19 seconds
Started Jun 27 06:59:05 PM PDT 24
Finished Jun 27 06:59:38 PM PDT 24
Peak memory 216080 kb
Host smart-34f052b4-e464-4d80-bfe9-fa68b57647f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137315432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2137315432
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1940861149
Short name T231
Test name
Test status
Simulation time 1474040378 ps
CPU time 12.45 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 06:59:18 PM PDT 24
Peak memory 211260 kb
Host smart-a972cb61-6e18-471d-b868-09e838c7e6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940861149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1940861149
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.212078405
Short name T38
Test name
Test status
Simulation time 54543661933 ps
CPU time 261.98 seconds
Started Jun 27 06:59:06 PM PDT 24
Finished Jun 27 07:03:30 PM PDT 24
Peak memory 237936 kb
Host smart-3b0949e5-4576-435a-85f7-6aeff8d9acfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212078405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.212078405
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2898394817
Short name T193
Test name
Test status
Simulation time 2488464432 ps
CPU time 24.12 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 06:59:30 PM PDT 24
Peak memory 212000 kb
Host smart-512c9b90-65e5-487a-8e3c-3306adcf4f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898394817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2898394817
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3600975758
Short name T106
Test name
Test status
Simulation time 1167983321 ps
CPU time 12.3 seconds
Started Jun 27 06:59:06 PM PDT 24
Finished Jun 27 06:59:19 PM PDT 24
Peak memory 211352 kb
Host smart-d9fa38a7-9dad-4079-bc23-4bf210848993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3600975758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3600975758
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3980134534
Short name T26
Test name
Test status
Simulation time 15093486085 ps
CPU time 30.64 seconds
Started Jun 27 06:59:06 PM PDT 24
Finished Jun 27 06:59:38 PM PDT 24
Peak memory 214088 kb
Host smart-e09f4495-403f-4df2-b8c9-0c3e840f4a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980134534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3980134534
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3885870014
Short name T75
Test name
Test status
Simulation time 2124492436 ps
CPU time 20.88 seconds
Started Jun 27 06:59:04 PM PDT 24
Finished Jun 27 06:59:26 PM PDT 24
Peak memory 212140 kb
Host smart-6693a135-ad3c-4b04-98dd-4df469cd44b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885870014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3885870014
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3895746373
Short name T203
Test name
Test status
Simulation time 5623122576 ps
CPU time 12.44 seconds
Started Jun 27 06:59:24 PM PDT 24
Finished Jun 27 06:59:38 PM PDT 24
Peak memory 211336 kb
Host smart-b07b1720-55e0-4dbb-a4aa-5d3b3110b053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895746373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3895746373
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1332951368
Short name T3
Test name
Test status
Simulation time 1347219270 ps
CPU time 99.17 seconds
Started Jun 27 06:59:25 PM PDT 24
Finished Jun 27 07:01:06 PM PDT 24
Peak memory 233732 kb
Host smart-40f2f0c5-ebc1-4b53-afa9-9eccfa283a90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332951368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1332951368
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4000911173
Short name T303
Test name
Test status
Simulation time 1444501520 ps
CPU time 18.58 seconds
Started Jun 27 06:59:23 PM PDT 24
Finished Jun 27 06:59:43 PM PDT 24
Peak memory 211904 kb
Host smart-69b00786-254c-4f64-9063-e544518263b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000911173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4000911173
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.797350300
Short name T162
Test name
Test status
Simulation time 11590996486 ps
CPU time 16.16 seconds
Started Jun 27 06:59:23 PM PDT 24
Finished Jun 27 06:59:40 PM PDT 24
Peak memory 211380 kb
Host smart-c0395cac-386d-4cde-949b-be91e240ab33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797350300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.797350300
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.85406021
Short name T302
Test name
Test status
Simulation time 25977408688 ps
CPU time 25.1 seconds
Started Jun 27 06:59:23 PM PDT 24
Finished Jun 27 06:59:50 PM PDT 24
Peak memory 214448 kb
Host smart-53c1bdce-43fd-4929-8304-f56808109779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85406021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.85406021
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4088306850
Short name T260
Test name
Test status
Simulation time 4890002671 ps
CPU time 29.61 seconds
Started Jun 27 06:59:25 PM PDT 24
Finished Jun 27 06:59:57 PM PDT 24
Peak memory 213856 kb
Host smart-9745402f-1abe-460e-b08f-20f733a803ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088306850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4088306850
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1992765011
Short name T46
Test name
Test status
Simulation time 45869105935 ps
CPU time 3600.97 seconds
Started Jun 27 06:59:24 PM PDT 24
Finished Jun 27 07:59:27 PM PDT 24
Peak memory 235864 kb
Host smart-b3a1f181-572c-4c09-9e3b-8e207b3de4a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992765011 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1992765011
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3784836640
Short name T224
Test name
Test status
Simulation time 14530755038 ps
CPU time 13.87 seconds
Started Jun 27 06:59:24 PM PDT 24
Finished Jun 27 06:59:40 PM PDT 24
Peak memory 211344 kb
Host smart-311bb941-61e1-4b6f-8b19-8c9484c7ff62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784836640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3784836640
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3218817004
Short name T185
Test name
Test status
Simulation time 20094147562 ps
CPU time 159.78 seconds
Started Jun 27 06:59:24 PM PDT 24
Finished Jun 27 07:02:05 PM PDT 24
Peak memory 228312 kb
Host smart-6bcf7c2d-f723-49c8-bc40-2c731bd0e0d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218817004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3218817004
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3424876904
Short name T201
Test name
Test status
Simulation time 168336235 ps
CPU time 9.58 seconds
Started Jun 27 06:59:22 PM PDT 24
Finished Jun 27 06:59:33 PM PDT 24
Peak memory 211872 kb
Host smart-af2cde7a-3832-4a30-8182-3e7ffce63852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424876904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3424876904
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3411062154
Short name T347
Test name
Test status
Simulation time 6120422133 ps
CPU time 17.13 seconds
Started Jun 27 06:59:24 PM PDT 24
Finished Jun 27 06:59:43 PM PDT 24
Peak memory 211396 kb
Host smart-e359a516-7689-4da1-aa3a-66899990a2c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411062154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3411062154
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2337931842
Short name T246
Test name
Test status
Simulation time 281559850 ps
CPU time 10.03 seconds
Started Jun 27 06:59:22 PM PDT 24
Finished Jun 27 06:59:33 PM PDT 24
Peak memory 213456 kb
Host smart-f7050dfa-95a0-4363-9bff-6299b1439bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337931842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2337931842
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.210783422
Short name T187
Test name
Test status
Simulation time 8025897719 ps
CPU time 36.18 seconds
Started Jun 27 06:59:24 PM PDT 24
Finished Jun 27 07:00:02 PM PDT 24
Peak memory 217184 kb
Host smart-33aeaaa0-7025-4004-a3cb-b2888bde1d77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210783422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.210783422
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3878211963
Short name T250
Test name
Test status
Simulation time 5522906593 ps
CPU time 12.88 seconds
Started Jun 27 06:59:25 PM PDT 24
Finished Jun 27 06:59:39 PM PDT 24
Peak memory 211380 kb
Host smart-8ac0a176-3ded-4746-bc47-debb04420aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878211963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3878211963
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1777861327
Short name T35
Test name
Test status
Simulation time 239801387011 ps
CPU time 382.04 seconds
Started Jun 27 06:59:24 PM PDT 24
Finished Jun 27 07:05:48 PM PDT 24
Peak memory 234268 kb
Host smart-65de3a6e-933b-4d88-a36d-7cc2b9a36351
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777861327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1777861327
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4241356164
Short name T91
Test name
Test status
Simulation time 10943682106 ps
CPU time 15.99 seconds
Started Jun 27 06:59:25 PM PDT 24
Finished Jun 27 06:59:43 PM PDT 24
Peak memory 212336 kb
Host smart-4098d70c-5fbe-4a31-a5c3-6f2dd2f1f787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241356164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4241356164
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.585050113
Short name T298
Test name
Test status
Simulation time 1135532476 ps
CPU time 11.75 seconds
Started Jun 27 06:59:25 PM PDT 24
Finished Jun 27 06:59:39 PM PDT 24
Peak memory 211320 kb
Host smart-dd23acf7-369d-4ab7-bb2e-f8d7f8c6c935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585050113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.585050113
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3430187405
Short name T175
Test name
Test status
Simulation time 3533821664 ps
CPU time 24.27 seconds
Started Jun 27 06:59:23 PM PDT 24
Finished Jun 27 06:59:48 PM PDT 24
Peak memory 212328 kb
Host smart-893f5417-5f3a-45ff-b48a-d3360c4efed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430187405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3430187405
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.705154988
Short name T200
Test name
Test status
Simulation time 16455035023 ps
CPU time 74.33 seconds
Started Jun 27 06:59:25 PM PDT 24
Finished Jun 27 07:00:41 PM PDT 24
Peak memory 217128 kb
Host smart-e675f792-485c-48f7-be8b-019908919b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705154988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.705154988
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2822270379
Short name T316
Test name
Test status
Simulation time 29245035682 ps
CPU time 1702.76 seconds
Started Jun 27 06:59:25 PM PDT 24
Finished Jun 27 07:27:50 PM PDT 24
Peak memory 235820 kb
Host smart-a1e0b53a-4f0c-4929-81bc-8b1240095da5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822270379 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2822270379
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2916868085
Short name T312
Test name
Test status
Simulation time 4242711673 ps
CPU time 11.1 seconds
Started Jun 27 06:59:27 PM PDT 24
Finished Jun 27 06:59:39 PM PDT 24
Peak memory 211372 kb
Host smart-deedbc45-6843-4700-a6e1-8f6abf89a155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916868085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2916868085
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.537166301
Short name T158
Test name
Test status
Simulation time 296621872904 ps
CPU time 398.52 seconds
Started Jun 27 06:59:26 PM PDT 24
Finished Jun 27 07:06:06 PM PDT 24
Peak memory 212612 kb
Host smart-5483f4d7-da6a-49c2-b2da-089962c3611f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537166301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.537166301
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4001124313
Short name T317
Test name
Test status
Simulation time 2986362878 ps
CPU time 13.69 seconds
Started Jun 27 06:59:23 PM PDT 24
Finished Jun 27 06:59:38 PM PDT 24
Peak memory 211972 kb
Host smart-c3533eaa-5904-4d9c-b988-b1b9f5cbca3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001124313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4001124313
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1310690868
Short name T141
Test name
Test status
Simulation time 2858246471 ps
CPU time 13.34 seconds
Started Jun 27 06:59:24 PM PDT 24
Finished Jun 27 06:59:39 PM PDT 24
Peak memory 211348 kb
Host smart-f0e13377-054d-471b-9a41-13e045984683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310690868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1310690868
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2557740264
Short name T95
Test name
Test status
Simulation time 751137419 ps
CPU time 10.56 seconds
Started Jun 27 06:59:21 PM PDT 24
Finished Jun 27 06:59:32 PM PDT 24
Peak memory 213804 kb
Host smart-9d7e9beb-eb11-4efd-837e-1b643114ba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557740264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2557740264
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1457672081
Short name T8
Test name
Test status
Simulation time 4582800095 ps
CPU time 41.92 seconds
Started Jun 27 06:59:24 PM PDT 24
Finished Jun 27 07:00:08 PM PDT 24
Peak memory 215680 kb
Host smart-23cdb295-f4c1-4e19-96e6-f6ef959cbdca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457672081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1457672081
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2814823416
Short name T48
Test name
Test status
Simulation time 67792193248 ps
CPU time 2529.1 seconds
Started Jun 27 06:59:25 PM PDT 24
Finished Jun 27 07:41:36 PM PDT 24
Peak memory 239228 kb
Host smart-b9b5a1da-b87f-46f2-9cf1-2804eae240e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814823416 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2814823416
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3737175952
Short name T160
Test name
Test status
Simulation time 213420198 ps
CPU time 5.88 seconds
Started Jun 27 06:59:37 PM PDT 24
Finished Jun 27 06:59:44 PM PDT 24
Peak memory 211240 kb
Host smart-6646ba04-d016-4ad3-9e27-85f4062bd476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737175952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3737175952
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3264784950
Short name T221
Test name
Test status
Simulation time 3415646899 ps
CPU time 105.67 seconds
Started Jun 27 06:59:36 PM PDT 24
Finished Jun 27 07:01:23 PM PDT 24
Peak memory 238396 kb
Host smart-c088f6a3-05eb-45ca-ae45-8ae97c39dc8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264784950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3264784950
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3053722526
Short name T268
Test name
Test status
Simulation time 3543050300 ps
CPU time 20.57 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 07:00:02 PM PDT 24
Peak memory 211992 kb
Host smart-e20c70b3-5a34-4562-b958-0fb697db572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053722526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3053722526
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1051105963
Short name T257
Test name
Test status
Simulation time 1739300653 ps
CPU time 14.41 seconds
Started Jun 27 06:59:41 PM PDT 24
Finished Jun 27 06:59:58 PM PDT 24
Peak memory 211328 kb
Host smart-fca99ec0-430a-4d42-8f1f-5c796348e0e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051105963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1051105963
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1692330904
Short name T318
Test name
Test status
Simulation time 31222122813 ps
CPU time 28.76 seconds
Started Jun 27 06:59:25 PM PDT 24
Finished Jun 27 06:59:56 PM PDT 24
Peak memory 212956 kb
Host smart-a75d3bd5-b332-43bc-9447-759ebebf681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692330904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1692330904
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3206530307
Short name T278
Test name
Test status
Simulation time 1185572443 ps
CPU time 14.14 seconds
Started Jun 27 06:59:22 PM PDT 24
Finished Jun 27 06:59:37 PM PDT 24
Peak memory 211328 kb
Host smart-bbe83e80-39c3-4f43-a520-02b8366a6d0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206530307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3206530307
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2312854760
Short name T263
Test name
Test status
Simulation time 3608613426 ps
CPU time 10.11 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 06:59:52 PM PDT 24
Peak memory 211552 kb
Host smart-22fcb4c2-047c-45e1-867a-98a9d7f9cbf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312854760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2312854760
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2043627693
Short name T321
Test name
Test status
Simulation time 11767102121 ps
CPU time 152.77 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 07:02:13 PM PDT 24
Peak memory 236912 kb
Host smart-43ae8bd2-16b2-49f0-b668-5544db069be8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043627693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2043627693
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2297960917
Short name T137
Test name
Test status
Simulation time 2051202953 ps
CPU time 16.9 seconds
Started Jun 27 06:59:37 PM PDT 24
Finished Jun 27 06:59:55 PM PDT 24
Peak memory 211948 kb
Host smart-28b6a6e3-e5c0-4317-a40b-ff150a6dde53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297960917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2297960917
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1622872837
Short name T232
Test name
Test status
Simulation time 12127438836 ps
CPU time 14.21 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 06:59:56 PM PDT 24
Peak memory 211388 kb
Host smart-aecdec4f-439d-4eee-9cd7-3a0b4ab63f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622872837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1622872837
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2964439483
Short name T292
Test name
Test status
Simulation time 4148170754 ps
CPU time 33.63 seconds
Started Jun 27 06:59:40 PM PDT 24
Finished Jun 27 07:00:17 PM PDT 24
Peak memory 214032 kb
Host smart-25464f4e-cb69-4115-90ac-eab83162a20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964439483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2964439483
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4165039161
Short name T253
Test name
Test status
Simulation time 186446106 ps
CPU time 10.38 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 06:59:52 PM PDT 24
Peak memory 214752 kb
Host smart-e8a61088-b132-4fdb-bd5f-0ef498210a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165039161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4165039161
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3263276402
Short name T29
Test name
Test status
Simulation time 1582543895 ps
CPU time 6.98 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 06:59:50 PM PDT 24
Peak memory 211296 kb
Host smart-f8e4480d-4959-4800-adca-888d911ee30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263276402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3263276402
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3143431803
Short name T216
Test name
Test status
Simulation time 79535708894 ps
CPU time 376.76 seconds
Started Jun 27 06:59:41 PM PDT 24
Finished Jun 27 07:06:00 PM PDT 24
Peak memory 237904 kb
Host smart-2d4461d2-2d07-4ba7-a696-8a86b1a62f22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143431803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3143431803
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.564207686
Short name T43
Test name
Test status
Simulation time 693241148 ps
CPU time 9.63 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 06:59:53 PM PDT 24
Peak memory 211960 kb
Host smart-32fc89d9-0c17-4d2e-a8bf-f0bbdb85056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564207686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.564207686
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1874567078
Short name T326
Test name
Test status
Simulation time 7585623305 ps
CPU time 11.71 seconds
Started Jun 27 06:59:37 PM PDT 24
Finished Jun 27 06:59:51 PM PDT 24
Peak memory 211392 kb
Host smart-e8f377bf-77b3-404b-bd4a-aba9874e3da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874567078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1874567078
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1182714456
Short name T204
Test name
Test status
Simulation time 23251308235 ps
CPU time 28.71 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 07:00:10 PM PDT 24
Peak memory 214396 kb
Host smart-20feaaeb-dfe5-48f0-8bab-04facc52f3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182714456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1182714456
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1442851197
Short name T132
Test name
Test status
Simulation time 306357077 ps
CPU time 16.12 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 06:59:58 PM PDT 24
Peak memory 214452 kb
Host smart-d4c6d035-a3b1-4f41-93e4-9d84be8f7863
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442851197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1442851197
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2682590127
Short name T167
Test name
Test status
Simulation time 337278328 ps
CPU time 6.83 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 06:57:23 PM PDT 24
Peak memory 211228 kb
Host smart-16f47024-e49a-4e93-98cc-134020f3c2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682590127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2682590127
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2564026530
Short name T154
Test name
Test status
Simulation time 172455859228 ps
CPU time 204.09 seconds
Started Jun 27 06:57:16 PM PDT 24
Finished Jun 27 07:00:42 PM PDT 24
Peak memory 237852 kb
Host smart-7802251a-ff96-4f3b-89fa-d10fce217ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564026530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2564026530
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2577787861
Short name T262
Test name
Test status
Simulation time 842589005 ps
CPU time 12.47 seconds
Started Jun 27 06:57:19 PM PDT 24
Finished Jun 27 06:57:32 PM PDT 24
Peak memory 211984 kb
Host smart-68e0c7a8-6046-403c-9416-a89cc43f3eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577787861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2577787861
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.111750721
Short name T339
Test name
Test status
Simulation time 1017869526 ps
CPU time 5.64 seconds
Started Jun 27 06:57:14 PM PDT 24
Finished Jun 27 06:57:20 PM PDT 24
Peak memory 211320 kb
Host smart-6c74d569-c13e-4842-a597-fccf11dfc1a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111750721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.111750721
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1776322040
Short name T17
Test name
Test status
Simulation time 2844756445 ps
CPU time 54.67 seconds
Started Jun 27 06:57:19 PM PDT 24
Finished Jun 27 06:58:15 PM PDT 24
Peak memory 235672 kb
Host smart-0f1273d8-d8d1-4032-b5ba-8fadf3ae25c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776322040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1776322040
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.198909709
Short name T324
Test name
Test status
Simulation time 57339108125 ps
CPU time 37.95 seconds
Started Jun 27 06:57:03 PM PDT 24
Finished Jun 27 06:57:43 PM PDT 24
Peak memory 214212 kb
Host smart-0fdbeb85-2a76-410d-8e7a-7a9bf3f2855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198909709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.198909709
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3038654205
Short name T206
Test name
Test status
Simulation time 44814847856 ps
CPU time 75.05 seconds
Started Jun 27 06:57:04 PM PDT 24
Finished Jun 27 06:58:20 PM PDT 24
Peak memory 219764 kb
Host smart-d2e7827f-228f-4ff3-821d-8fddaf0a6f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038654205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3038654205
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3215732329
Short name T214
Test name
Test status
Simulation time 563532314 ps
CPU time 7.97 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 06:59:50 PM PDT 24
Peak memory 211304 kb
Host smart-fc53e555-8e20-4b34-86b0-77106df253c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215732329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3215732329
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1111071677
Short name T197
Test name
Test status
Simulation time 148849320965 ps
CPU time 360.09 seconds
Started Jun 27 06:59:36 PM PDT 24
Finished Jun 27 07:05:37 PM PDT 24
Peak memory 236956 kb
Host smart-9f2a7805-5148-46e0-9653-868b60ac3ade
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111071677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1111071677
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1877119356
Short name T145
Test name
Test status
Simulation time 14858911444 ps
CPU time 15.76 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 06:59:57 PM PDT 24
Peak memory 211408 kb
Host smart-b1bef925-84b0-4118-a98a-9d573a1b9fec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1877119356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1877119356
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.613634722
Short name T213
Test name
Test status
Simulation time 182961001 ps
CPU time 9.87 seconds
Started Jun 27 06:59:37 PM PDT 24
Finished Jun 27 06:59:49 PM PDT 24
Peak memory 214052 kb
Host smart-d86275cd-a643-4b0d-a9bc-f2584a50ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613634722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.613634722
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1647374211
Short name T279
Test name
Test status
Simulation time 4998576924 ps
CPU time 13.37 seconds
Started Jun 27 06:59:37 PM PDT 24
Finished Jun 27 06:59:52 PM PDT 24
Peak memory 211396 kb
Host smart-80677584-9fa8-4894-9981-6ac5fb8b6fa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647374211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1647374211
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.430022208
Short name T148
Test name
Test status
Simulation time 3612169277 ps
CPU time 7.85 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 06:59:49 PM PDT 24
Peak memory 211348 kb
Host smart-8b0bfb32-9d35-457a-bc3e-45a457b0fda1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430022208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.430022208
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1611192032
Short name T34
Test name
Test status
Simulation time 34407487591 ps
CPU time 309.56 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 07:04:50 PM PDT 24
Peak memory 240360 kb
Host smart-e78c36b7-51eb-4c25-bc4c-d56f33e8fdae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611192032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1611192032
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1729957317
Short name T6
Test name
Test status
Simulation time 1377893284 ps
CPU time 13.74 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 06:59:56 PM PDT 24
Peak memory 212436 kb
Host smart-416f5d9f-753e-423e-b5f9-cad9935c9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729957317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1729957317
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2032492632
Short name T338
Test name
Test status
Simulation time 1819492398 ps
CPU time 13.76 seconds
Started Jun 27 06:59:42 PM PDT 24
Finished Jun 27 06:59:58 PM PDT 24
Peak memory 211348 kb
Host smart-85a15262-d3f4-41c1-8556-9641d5296105
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032492632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2032492632
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.62444105
Short name T361
Test name
Test status
Simulation time 11371919381 ps
CPU time 22.78 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 07:00:06 PM PDT 24
Peak memory 213940 kb
Host smart-751e238a-a195-47bc-ac3a-3ba0a53398fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62444105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.62444105
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.917097807
Short name T362
Test name
Test status
Simulation time 480191072 ps
CPU time 14.72 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 06:59:58 PM PDT 24
Peak memory 213736 kb
Host smart-a8d356c9-e679-4335-b22a-6c618f346a93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917097807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.917097807
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.763904598
Short name T332
Test name
Test status
Simulation time 2394471750 ps
CPU time 14.84 seconds
Started Jun 27 06:59:41 PM PDT 24
Finished Jun 27 06:59:58 PM PDT 24
Peak memory 211276 kb
Host smart-f4bae663-cae1-4aa7-8eb7-9b8f3b613f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763904598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.763904598
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1529006184
Short name T230
Test name
Test status
Simulation time 483154369996 ps
CPU time 466.71 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 07:07:29 PM PDT 24
Peak memory 213676 kb
Host smart-9affe7c6-5504-496b-b777-9d8ef0507066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529006184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1529006184
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.231160199
Short name T129
Test name
Test status
Simulation time 4115058537 ps
CPU time 21.44 seconds
Started Jun 27 06:59:42 PM PDT 24
Finished Jun 27 07:00:05 PM PDT 24
Peak memory 211388 kb
Host smart-236d88d9-42ba-4ca3-b5e5-2bb496a53fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231160199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.231160199
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3385178466
Short name T288
Test name
Test status
Simulation time 3806425093 ps
CPU time 11.09 seconds
Started Jun 27 06:59:37 PM PDT 24
Finished Jun 27 06:59:51 PM PDT 24
Peak memory 211404 kb
Host smart-8e311fb7-2da1-4068-a23c-25ca23865aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3385178466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3385178466
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4183060861
Short name T73
Test name
Test status
Simulation time 3079008618 ps
CPU time 31.5 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 07:00:13 PM PDT 24
Peak memory 213396 kb
Host smart-80651f33-43c4-44ad-aa0f-ca4e0891aa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183060861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4183060861
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2505673255
Short name T241
Test name
Test status
Simulation time 3576875027 ps
CPU time 23.27 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 07:00:05 PM PDT 24
Peak memory 213392 kb
Host smart-67b37d99-3f29-42cc-82c2-c0fdba9a3772
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505673255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2505673255
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2532629425
Short name T271
Test name
Test status
Simulation time 2403528207 ps
CPU time 8.36 seconds
Started Jun 27 06:59:42 PM PDT 24
Finished Jun 27 06:59:52 PM PDT 24
Peak memory 211360 kb
Host smart-cf8469c1-4e69-4e58-b2d3-9c3a96f1f686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532629425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2532629425
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4161327157
Short name T359
Test name
Test status
Simulation time 43162777697 ps
CPU time 443.28 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 07:07:06 PM PDT 24
Peak memory 232848 kb
Host smart-c82b0854-1fb2-4683-9fc5-95885a59b9f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161327157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4161327157
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1826279438
Short name T272
Test name
Test status
Simulation time 11930146262 ps
CPU time 23.21 seconds
Started Jun 27 06:59:40 PM PDT 24
Finished Jun 27 07:00:06 PM PDT 24
Peak memory 211440 kb
Host smart-a4446c7a-bc02-4a27-9ae9-34608afffc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826279438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1826279438
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1922068878
Short name T342
Test name
Test status
Simulation time 7568686984 ps
CPU time 16.92 seconds
Started Jun 27 06:59:39 PM PDT 24
Finished Jun 27 06:59:59 PM PDT 24
Peak memory 211392 kb
Host smart-6618dbe8-e423-4464-9acf-d9b72c2f8966
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922068878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1922068878
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.484300951
Short name T71
Test name
Test status
Simulation time 746582616 ps
CPU time 10.01 seconds
Started Jun 27 06:59:42 PM PDT 24
Finished Jun 27 06:59:54 PM PDT 24
Peak memory 213472 kb
Host smart-266fd716-1698-47d0-addb-b49f5645ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484300951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.484300951
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.752540629
Short name T168
Test name
Test status
Simulation time 796953571 ps
CPU time 9.82 seconds
Started Jun 27 06:59:38 PM PDT 24
Finished Jun 27 06:59:52 PM PDT 24
Peak memory 211352 kb
Host smart-554db255-bcd0-43c3-83d4-d0c4feb77b9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752540629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.752540629
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2484527574
Short name T20
Test name
Test status
Simulation time 32680433252 ps
CPU time 1360.52 seconds
Started Jun 27 06:59:41 PM PDT 24
Finished Jun 27 07:22:24 PM PDT 24
Peak memory 235916 kb
Host smart-604477af-ae64-4022-8e09-34186c9da5e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484527574 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2484527574
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3689105886
Short name T32
Test name
Test status
Simulation time 417258065 ps
CPU time 4.22 seconds
Started Jun 27 06:59:51 PM PDT 24
Finished Jun 27 06:59:57 PM PDT 24
Peak memory 211288 kb
Host smart-98ba4055-5103-41cc-a3c4-3ffa573ebf83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689105886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3689105886
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1013460964
Short name T217
Test name
Test status
Simulation time 7303142497 ps
CPU time 98.75 seconds
Started Jun 27 06:59:50 PM PDT 24
Finished Jun 27 07:01:30 PM PDT 24
Peak memory 237844 kb
Host smart-b37485a8-4771-4bdd-8c73-10d873299575
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013460964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1013460964
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3932484947
Short name T304
Test name
Test status
Simulation time 9718018943 ps
CPU time 23.9 seconds
Started Jun 27 06:59:59 PM PDT 24
Finished Jun 27 07:00:24 PM PDT 24
Peak memory 212352 kb
Host smart-73ec08e9-1b16-4aa8-acb4-985a44bfd5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932484947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3932484947
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2806024688
Short name T308
Test name
Test status
Simulation time 1746640866 ps
CPU time 14.68 seconds
Started Jun 27 06:59:54 PM PDT 24
Finished Jun 27 07:00:10 PM PDT 24
Peak memory 211348 kb
Host smart-3804d9b2-8d79-45ea-b47f-f9c17c4e87dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806024688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2806024688
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2170146795
Short name T222
Test name
Test status
Simulation time 7029661432 ps
CPU time 19.04 seconds
Started Jun 27 06:59:59 PM PDT 24
Finished Jun 27 07:00:19 PM PDT 24
Peak memory 214272 kb
Host smart-2a979a74-007d-4c58-aa72-8da6494b412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170146795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2170146795
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3749715614
Short name T233
Test name
Test status
Simulation time 8990362446 ps
CPU time 29.68 seconds
Started Jun 27 06:59:50 PM PDT 24
Finished Jun 27 07:00:22 PM PDT 24
Peak memory 212828 kb
Host smart-82aed6f9-2e73-4d55-b79c-fbcc382f58fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749715614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3749715614
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.214317335
Short name T355
Test name
Test status
Simulation time 319430875058 ps
CPU time 5618.47 seconds
Started Jun 27 06:59:51 PM PDT 24
Finished Jun 27 08:33:32 PM PDT 24
Peak memory 235852 kb
Host smart-36a72ba6-1535-4b71-ad34-604c6e21cb6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214317335 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.214317335
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2137635640
Short name T351
Test name
Test status
Simulation time 2392911375 ps
CPU time 11.59 seconds
Started Jun 27 06:59:50 PM PDT 24
Finished Jun 27 07:00:03 PM PDT 24
Peak memory 211336 kb
Host smart-10d09385-403d-4a19-b774-def4b6e23f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137635640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2137635640
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2370261170
Short name T10
Test name
Test status
Simulation time 9688141397 ps
CPU time 154.65 seconds
Started Jun 27 06:59:52 PM PDT 24
Finished Jun 27 07:02:28 PM PDT 24
Peak memory 234824 kb
Host smart-79189b96-51b0-4a24-b546-3453cf2a95df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370261170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2370261170
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2916642116
Short name T311
Test name
Test status
Simulation time 3968890840 ps
CPU time 30.09 seconds
Started Jun 27 06:59:53 PM PDT 24
Finished Jun 27 07:00:24 PM PDT 24
Peak memory 212344 kb
Host smart-f9a4eb9c-51e4-479e-b2a2-50df6187a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916642116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2916642116
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2338964004
Short name T111
Test name
Test status
Simulation time 1133588867 ps
CPU time 6.88 seconds
Started Jun 27 06:59:52 PM PDT 24
Finished Jun 27 07:00:00 PM PDT 24
Peak memory 211360 kb
Host smart-33608b14-5a4b-47be-a04d-3883425226e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338964004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2338964004
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1457718443
Short name T157
Test name
Test status
Simulation time 5436729179 ps
CPU time 31.85 seconds
Started Jun 27 06:59:52 PM PDT 24
Finished Jun 27 07:00:25 PM PDT 24
Peak memory 214172 kb
Host smart-daa1f48c-9282-4ec0-8e4e-680c8f25c9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457718443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1457718443
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1027449975
Short name T275
Test name
Test status
Simulation time 32680278868 ps
CPU time 84.5 seconds
Started Jun 27 06:59:51 PM PDT 24
Finished Jun 27 07:01:17 PM PDT 24
Peak memory 216324 kb
Host smart-b7245932-4e72-42f2-989f-1f279562aa7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027449975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1027449975
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1345862145
Short name T295
Test name
Test status
Simulation time 1824959387 ps
CPU time 15.06 seconds
Started Jun 27 06:59:51 PM PDT 24
Finished Jun 27 07:00:08 PM PDT 24
Peak memory 211300 kb
Host smart-e330645c-1545-45cd-841b-db6d9c56e7f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345862145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1345862145
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.255278781
Short name T239
Test name
Test status
Simulation time 7793644673 ps
CPU time 213.44 seconds
Started Jun 27 06:59:51 PM PDT 24
Finished Jun 27 07:03:26 PM PDT 24
Peak memory 237504 kb
Host smart-48fd80f3-9f52-42c9-abe8-7b4d6c260203
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255278781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.255278781
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4113802509
Short name T270
Test name
Test status
Simulation time 25449046838 ps
CPU time 22.35 seconds
Started Jun 27 06:59:53 PM PDT 24
Finished Jun 27 07:00:16 PM PDT 24
Peak memory 215984 kb
Host smart-b6ad9dd3-8f0c-4e90-8d3e-97f56da5a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113802509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4113802509
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3974114230
Short name T198
Test name
Test status
Simulation time 820831387 ps
CPU time 5.12 seconds
Started Jun 27 06:59:54 PM PDT 24
Finished Jun 27 07:00:00 PM PDT 24
Peak memory 211336 kb
Host smart-c66e695b-c6c0-4098-9ee0-3b4b0cc741f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974114230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3974114230
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3039250086
Short name T210
Test name
Test status
Simulation time 6561710089 ps
CPU time 28.96 seconds
Started Jun 27 06:59:50 PM PDT 24
Finished Jun 27 07:00:21 PM PDT 24
Peak memory 213656 kb
Host smart-9038103c-b554-4937-9e4c-9c4f1332cd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039250086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3039250086
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.44398796
Short name T74
Test name
Test status
Simulation time 197161233369 ps
CPU time 148.01 seconds
Started Jun 27 07:00:00 PM PDT 24
Finished Jun 27 07:02:29 PM PDT 24
Peak memory 219408 kb
Host smart-a04ff772-7c02-4087-85b3-a3b0276d95bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44398796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.rom_ctrl_stress_all.44398796
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2370862618
Short name T164
Test name
Test status
Simulation time 346766035 ps
CPU time 4.24 seconds
Started Jun 27 06:59:59 PM PDT 24
Finished Jun 27 07:00:04 PM PDT 24
Peak memory 211212 kb
Host smart-cada6468-9a4c-4595-89d7-16657cbdd9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370862618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2370862618
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1020969678
Short name T94
Test name
Test status
Simulation time 58559302640 ps
CPU time 168.71 seconds
Started Jun 27 06:59:59 PM PDT 24
Finished Jun 27 07:02:48 PM PDT 24
Peak memory 228648 kb
Host smart-cac59d7c-88f0-429b-8159-da1a1279b2dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020969678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1020969678
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1648181714
Short name T283
Test name
Test status
Simulation time 2651975574 ps
CPU time 25.01 seconds
Started Jun 27 06:59:52 PM PDT 24
Finished Jun 27 07:00:18 PM PDT 24
Peak memory 211876 kb
Host smart-e16a97d1-3b81-4774-8e2a-ccb40ecd66fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648181714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1648181714
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3742170260
Short name T5
Test name
Test status
Simulation time 546792453 ps
CPU time 8.89 seconds
Started Jun 27 06:59:59 PM PDT 24
Finished Jun 27 07:00:09 PM PDT 24
Peak memory 211328 kb
Host smart-1d7f8298-e353-4018-8a2c-92d51571b6ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742170260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3742170260
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.862264552
Short name T196
Test name
Test status
Simulation time 613922732 ps
CPU time 13.91 seconds
Started Jun 27 06:59:53 PM PDT 24
Finished Jun 27 07:00:08 PM PDT 24
Peak memory 213692 kb
Host smart-16253c7f-38c4-45de-84cd-e7c7ea4fb44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862264552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.862264552
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3195371028
Short name T211
Test name
Test status
Simulation time 751632386 ps
CPU time 11.24 seconds
Started Jun 27 06:59:50 PM PDT 24
Finished Jun 27 07:00:03 PM PDT 24
Peak memory 211248 kb
Host smart-1f742d51-3f20-4f61-a134-b68138830876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195371028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3195371028
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2478645903
Short name T171
Test name
Test status
Simulation time 823879969 ps
CPU time 9.16 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:17 PM PDT 24
Peak memory 211320 kb
Host smart-2c090b70-58fc-40a3-aea5-a5ab113a3871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478645903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2478645903
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1053171494
Short name T90
Test name
Test status
Simulation time 60036709603 ps
CPU time 215.22 seconds
Started Jun 27 07:00:08 PM PDT 24
Finished Jun 27 07:03:44 PM PDT 24
Peak memory 212668 kb
Host smart-f6548934-4a50-41bd-90a8-95545a7bec8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053171494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1053171494
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4118994651
Short name T131
Test name
Test status
Simulation time 3962885334 ps
CPU time 33.22 seconds
Started Jun 27 07:00:12 PM PDT 24
Finished Jun 27 07:00:46 PM PDT 24
Peak memory 211992 kb
Host smart-2d734e9d-45b6-4f7a-8915-5a34a6c58362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118994651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4118994651
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.911134399
Short name T136
Test name
Test status
Simulation time 5409689128 ps
CPU time 16.96 seconds
Started Jun 27 07:00:05 PM PDT 24
Finished Jun 27 07:00:23 PM PDT 24
Peak memory 211336 kb
Host smart-bdfb1e7c-f3de-4597-a988-b20d46e5199f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911134399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.911134399
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1632365235
Short name T128
Test name
Test status
Simulation time 1187961721 ps
CPU time 10.12 seconds
Started Jun 27 06:59:53 PM PDT 24
Finished Jun 27 07:00:05 PM PDT 24
Peak memory 213832 kb
Host smart-9e855b7e-db23-4665-8e78-311a615ed1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632365235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1632365235
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1879145097
Short name T336
Test name
Test status
Simulation time 17785059085 ps
CPU time 35.27 seconds
Started Jun 27 06:59:50 PM PDT 24
Finished Jun 27 07:00:27 PM PDT 24
Peak memory 214980 kb
Host smart-060ef655-602a-4679-b48c-d9e52a725e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879145097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1879145097
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1695227065
Short name T50
Test name
Test status
Simulation time 603976417941 ps
CPU time 3820.26 seconds
Started Jun 27 07:00:12 PM PDT 24
Finished Jun 27 08:03:54 PM PDT 24
Peak memory 241936 kb
Host smart-45a72cd5-e4dd-43b1-8dd8-3cb7741a2e0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695227065 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1695227065
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1434409902
Short name T155
Test name
Test status
Simulation time 1513384106 ps
CPU time 13.58 seconds
Started Jun 27 07:00:08 PM PDT 24
Finished Jun 27 07:00:23 PM PDT 24
Peak memory 211264 kb
Host smart-1efe8007-4aee-41fa-85c7-a1e89d51dae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434409902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1434409902
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.56290991
Short name T333
Test name
Test status
Simulation time 26270813507 ps
CPU time 151.34 seconds
Started Jun 27 07:00:09 PM PDT 24
Finished Jun 27 07:02:42 PM PDT 24
Peak memory 227540 kb
Host smart-af939c3a-4540-4721-a016-5bdd71cbedfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56290991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_co
rrupt_sig_fatal_chk.56290991
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3765702274
Short name T369
Test name
Test status
Simulation time 2506613668 ps
CPU time 24.49 seconds
Started Jun 27 07:00:08 PM PDT 24
Finished Jun 27 07:00:34 PM PDT 24
Peak memory 211996 kb
Host smart-14bdcd43-abb4-462c-b960-ef64884bb3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765702274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3765702274
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1844650701
Short name T139
Test name
Test status
Simulation time 103678548 ps
CPU time 5.84 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:14 PM PDT 24
Peak memory 211312 kb
Host smart-a37d4534-c461-4ed1-a493-8174c6d221be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844650701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1844650701
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3545072092
Short name T30
Test name
Test status
Simulation time 3834008307 ps
CPU time 15.97 seconds
Started Jun 27 07:00:06 PM PDT 24
Finished Jun 27 07:00:23 PM PDT 24
Peak memory 213908 kb
Host smart-dfa5a369-91de-4c3f-8370-277e4fea6522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545072092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3545072092
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.369403583
Short name T188
Test name
Test status
Simulation time 210563924 ps
CPU time 10.3 seconds
Started Jun 27 07:00:07 PM PDT 24
Finished Jun 27 07:00:19 PM PDT 24
Peak memory 214500 kb
Host smart-088c58a4-0e48-45d7-abf4-3f3e8e393456
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369403583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.369403583
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1820664147
Short name T334
Test name
Test status
Simulation time 3324992966 ps
CPU time 9.31 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 06:57:26 PM PDT 24
Peak memory 211344 kb
Host smart-2ef8d6fd-94ac-4448-8fd0-c3630587b891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820664147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1820664147
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3918752809
Short name T229
Test name
Test status
Simulation time 95371220285 ps
CPU time 232.49 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 07:01:09 PM PDT 24
Peak memory 228364 kb
Host smart-9592d7e8-ec72-4b08-889f-ed91f5cc6c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918752809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3918752809
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2263631124
Short name T159
Test name
Test status
Simulation time 2284473164 ps
CPU time 23.93 seconds
Started Jun 27 06:57:14 PM PDT 24
Finished Jun 27 06:57:39 PM PDT 24
Peak memory 211976 kb
Host smart-1a9c0282-1b4b-4238-b9b1-31bb124e1bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263631124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2263631124
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1804943888
Short name T156
Test name
Test status
Simulation time 5742944060 ps
CPU time 10.94 seconds
Started Jun 27 06:57:14 PM PDT 24
Finished Jun 27 06:57:27 PM PDT 24
Peak memory 211408 kb
Host smart-cf0087ff-6510-482e-b627-4be541f4fbfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1804943888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1804943888
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2390889981
Short name T258
Test name
Test status
Simulation time 369118592 ps
CPU time 9.89 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 06:57:26 PM PDT 24
Peak memory 213564 kb
Host smart-e5fc76f0-13ca-48e2-8f89-f0ade0464a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390889981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2390889981
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1654656524
Short name T297
Test name
Test status
Simulation time 91540501436 ps
CPU time 109.94 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 06:59:06 PM PDT 24
Peak memory 217224 kb
Host smart-9606cc33-cd6d-44b5-b1b9-33122ec5aea1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654656524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1654656524
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1155726451
Short name T314
Test name
Test status
Simulation time 384444039 ps
CPU time 6.88 seconds
Started Jun 27 06:57:19 PM PDT 24
Finished Jun 27 06:57:27 PM PDT 24
Peak memory 211300 kb
Host smart-0386538c-aaee-4520-ae74-4c720ba7dd31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155726451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1155726451
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3055035140
Short name T37
Test name
Test status
Simulation time 8819270395 ps
CPU time 177.98 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 07:00:15 PM PDT 24
Peak memory 234940 kb
Host smart-b1b9b702-1c37-4319-ae92-12896a719c0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055035140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3055035140
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1959553664
Short name T178
Test name
Test status
Simulation time 6806254175 ps
CPU time 19.57 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 06:57:36 PM PDT 24
Peak memory 212468 kb
Host smart-84efbba7-2a13-47fd-93ea-6b2638d7a315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959553664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1959553664
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1956742224
Short name T183
Test name
Test status
Simulation time 3290761072 ps
CPU time 14.17 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 06:57:31 PM PDT 24
Peak memory 211380 kb
Host smart-f5251974-6452-4181-b5b7-e6dca4bf1e78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956742224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1956742224
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1121737508
Short name T180
Test name
Test status
Simulation time 761035997 ps
CPU time 10.14 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 06:57:26 PM PDT 24
Peak memory 213736 kb
Host smart-c0cd6de6-44d4-475a-ba08-d1a8caa38d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121737508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1121737508
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2804586777
Short name T360
Test name
Test status
Simulation time 6379143290 ps
CPU time 28.58 seconds
Started Jun 27 06:57:21 PM PDT 24
Finished Jun 27 06:57:50 PM PDT 24
Peak memory 215248 kb
Host smart-bbb941c7-4343-4728-a3da-f91e8cbe9944
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804586777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2804586777
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4165500101
Short name T300
Test name
Test status
Simulation time 3204490039 ps
CPU time 13.83 seconds
Started Jun 27 06:57:19 PM PDT 24
Finished Jun 27 06:57:34 PM PDT 24
Peak memory 211356 kb
Host smart-8b9442ee-02c8-49d6-9d84-9fa03cd57904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165500101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4165500101
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1131460980
Short name T276
Test name
Test status
Simulation time 1740138019 ps
CPU time 109.89 seconds
Started Jun 27 06:57:18 PM PDT 24
Finished Jun 27 06:59:10 PM PDT 24
Peak memory 228340 kb
Host smart-4e1911d4-d4bb-40b5-9f20-f229b95f709f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131460980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1131460980
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2140922684
Short name T194
Test name
Test status
Simulation time 692884149 ps
CPU time 9.38 seconds
Started Jun 27 06:57:17 PM PDT 24
Finished Jun 27 06:57:28 PM PDT 24
Peak memory 211964 kb
Host smart-85039a4f-777a-44ca-9674-82e763ea519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140922684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2140922684
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2960544318
Short name T337
Test name
Test status
Simulation time 469003555 ps
CPU time 5.97 seconds
Started Jun 27 06:57:18 PM PDT 24
Finished Jun 27 06:57:25 PM PDT 24
Peak memory 211340 kb
Host smart-fda27c62-3dc1-4433-8518-3ac353931997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2960544318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2960544318
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3198489686
Short name T350
Test name
Test status
Simulation time 7650757784 ps
CPU time 23.5 seconds
Started Jun 27 06:57:17 PM PDT 24
Finished Jun 27 06:57:42 PM PDT 24
Peak memory 214488 kb
Host smart-2c4dddea-0d1f-4427-9f7a-305545b28f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198489686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3198489686
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.745181089
Short name T195
Test name
Test status
Simulation time 11558206534 ps
CPU time 33.76 seconds
Started Jun 27 06:57:14 PM PDT 24
Finished Jun 27 06:57:50 PM PDT 24
Peak memory 214888 kb
Host smart-5e8984e2-1215-4fb9-846d-f1a04066f4bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745181089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.745181089
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2435222777
Short name T349
Test name
Test status
Simulation time 53092576703 ps
CPU time 255.1 seconds
Started Jun 27 06:57:18 PM PDT 24
Finished Jun 27 07:01:34 PM PDT 24
Peak memory 228680 kb
Host smart-5a2af256-b92b-44be-bada-c27599a5ebd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435222777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2435222777
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2653716534
Short name T172
Test name
Test status
Simulation time 10391521231 ps
CPU time 23.8 seconds
Started Jun 27 06:57:14 PM PDT 24
Finished Jun 27 06:57:38 PM PDT 24
Peak memory 212232 kb
Host smart-a90f1a79-b95d-4fe4-8066-6eee0a47b61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653716534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2653716534
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2366128159
Short name T189
Test name
Test status
Simulation time 2913198120 ps
CPU time 14.41 seconds
Started Jun 27 06:57:13 PM PDT 24
Finished Jun 27 06:57:29 PM PDT 24
Peak memory 211392 kb
Host smart-abb20966-960d-4e93-ba4a-6e3040edeadc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2366128159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2366128159
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.969603913
Short name T309
Test name
Test status
Simulation time 29846569459 ps
CPU time 28.5 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 06:57:45 PM PDT 24
Peak memory 213764 kb
Host smart-47bd0f7b-987b-49f6-908c-6eef53e6f09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969603913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.969603913
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2873709071
Short name T367
Test name
Test status
Simulation time 1382872628 ps
CPU time 13.03 seconds
Started Jun 27 06:57:27 PM PDT 24
Finished Jun 27 06:57:41 PM PDT 24
Peak memory 211252 kb
Host smart-a5a73b5d-73a1-4a15-a888-3ba629b16ff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873709071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2873709071
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2510453013
Short name T97
Test name
Test status
Simulation time 2111809369 ps
CPU time 127.66 seconds
Started Jun 27 06:57:14 PM PDT 24
Finished Jun 27 06:59:24 PM PDT 24
Peak memory 236300 kb
Host smart-e9cd42da-77a8-4229-8f3c-3ca45777edc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510453013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2510453013
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1658181706
Short name T127
Test name
Test status
Simulation time 6870845667 ps
CPU time 33.12 seconds
Started Jun 27 06:57:30 PM PDT 24
Finished Jun 27 06:58:04 PM PDT 24
Peak memory 212580 kb
Host smart-1fba3c40-80b8-492f-a1f8-06449154581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658181706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1658181706
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2100844559
Short name T265
Test name
Test status
Simulation time 1533928046 ps
CPU time 9.81 seconds
Started Jun 27 06:57:14 PM PDT 24
Finished Jun 27 06:57:25 PM PDT 24
Peak memory 211324 kb
Host smart-ec64de1d-36ac-46ea-b5a1-5f84dbf67eb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100844559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2100844559
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.631959533
Short name T14
Test name
Test status
Simulation time 3740331442 ps
CPU time 30.69 seconds
Started Jun 27 06:57:19 PM PDT 24
Finished Jun 27 06:57:51 PM PDT 24
Peak memory 213096 kb
Host smart-e52edbc9-a106-4efb-b8c2-30066fa6a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631959533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.631959533
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1322805666
Short name T354
Test name
Test status
Simulation time 64295197520 ps
CPU time 96.46 seconds
Started Jun 27 06:57:15 PM PDT 24
Finished Jun 27 06:58:53 PM PDT 24
Peak memory 219408 kb
Host smart-d82e783d-3c46-49cc-a08a-97a519620463
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322805666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1322805666
Directory /workspace/9.rom_ctrl_stress_all/latest
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