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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 91.99 97.67 100.00 98.62 97.45 98.37


Total test records in report: 462
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T300 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2292533801 Jun 28 04:49:13 PM PDT 24 Jun 28 04:49:23 PM PDT 24 475793468 ps
T52 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3141820674 Jun 28 04:49:34 PM PDT 24 Jun 28 04:50:07 PM PDT 24 15497718324 ps
T301 /workspace/coverage/default/13.rom_ctrl_stress_all.1022746637 Jun 28 04:48:58 PM PDT 24 Jun 28 04:49:52 PM PDT 24 11248210988 ps
T302 /workspace/coverage/default/31.rom_ctrl_stress_all.3154740177 Jun 28 04:49:34 PM PDT 24 Jun 28 04:50:06 PM PDT 24 5795954021 ps
T303 /workspace/coverage/default/36.rom_ctrl_smoke.1142756376 Jun 28 04:49:35 PM PDT 24 Jun 28 04:49:47 PM PDT 24 815390354 ps
T304 /workspace/coverage/default/39.rom_ctrl_smoke.3907575634 Jun 28 04:49:41 PM PDT 24 Jun 28 04:50:16 PM PDT 24 18172349464 ps
T305 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2050259055 Jun 28 04:49:08 PM PDT 24 Jun 28 04:51:36 PM PDT 24 6155480770 ps
T306 /workspace/coverage/default/49.rom_ctrl_alert_test.4290615666 Jun 28 04:49:54 PM PDT 24 Jun 28 04:50:10 PM PDT 24 6595170863 ps
T307 /workspace/coverage/default/32.rom_ctrl_stress_all.2605850518 Jun 28 04:49:36 PM PDT 24 Jun 28 04:50:32 PM PDT 24 25125590792 ps
T308 /workspace/coverage/default/10.rom_ctrl_stress_all.4275800481 Jun 28 04:49:07 PM PDT 24 Jun 28 04:50:13 PM PDT 24 5460107022 ps
T309 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4218218214 Jun 28 04:49:37 PM PDT 24 Jun 28 04:49:45 PM PDT 24 390893666 ps
T310 /workspace/coverage/default/33.rom_ctrl_alert_test.2730907221 Jun 28 04:49:39 PM PDT 24 Jun 28 04:49:51 PM PDT 24 1139463750 ps
T311 /workspace/coverage/default/1.rom_ctrl_alert_test.232184310 Jun 28 04:49:04 PM PDT 24 Jun 28 04:49:17 PM PDT 24 3388567428 ps
T312 /workspace/coverage/default/17.rom_ctrl_smoke.1343021846 Jun 28 04:49:10 PM PDT 24 Jun 28 04:49:43 PM PDT 24 3952360594 ps
T313 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.289574073 Jun 28 04:49:24 PM PDT 24 Jun 28 04:49:32 PM PDT 24 100478808 ps
T314 /workspace/coverage/default/30.rom_ctrl_stress_all.2894962904 Jun 28 04:49:18 PM PDT 24 Jun 28 04:49:40 PM PDT 24 8807565595 ps
T315 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2887634247 Jun 28 04:49:30 PM PDT 24 Jun 28 04:52:42 PM PDT 24 20851248584 ps
T316 /workspace/coverage/default/22.rom_ctrl_smoke.3146871275 Jun 28 04:49:12 PM PDT 24 Jun 28 04:49:39 PM PDT 24 11308332546 ps
T317 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2277618328 Jun 28 04:49:27 PM PDT 24 Jun 28 04:49:51 PM PDT 24 8907322356 ps
T318 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1565796542 Jun 28 04:49:47 PM PDT 24 Jun 28 04:50:51 PM PDT 24 1634337222 ps
T319 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1349233267 Jun 28 04:49:05 PM PDT 24 Jun 28 04:55:38 PM PDT 24 120512954822 ps
T320 /workspace/coverage/default/5.rom_ctrl_smoke.3611769703 Jun 28 04:49:07 PM PDT 24 Jun 28 04:49:40 PM PDT 24 7030329964 ps
T321 /workspace/coverage/default/31.rom_ctrl_smoke.2646751914 Jun 28 04:49:37 PM PDT 24 Jun 28 04:50:10 PM PDT 24 3102459010 ps
T322 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.256088875 Jun 28 04:49:46 PM PDT 24 Jun 28 04:49:56 PM PDT 24 693786581 ps
T115 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1759805403 Jun 28 04:49:46 PM PDT 24 Jun 28 05:12:37 PM PDT 24 178182039347 ps
T323 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2971319446 Jun 28 04:49:06 PM PDT 24 Jun 28 04:49:22 PM PDT 24 4817445951 ps
T324 /workspace/coverage/default/31.rom_ctrl_alert_test.251596390 Jun 28 04:49:36 PM PDT 24 Jun 28 04:49:50 PM PDT 24 1286467959 ps
T325 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.280036538 Jun 28 04:49:37 PM PDT 24 Jun 28 04:56:45 PM PDT 24 79562034900 ps
T326 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2168977862 Jun 28 04:49:10 PM PDT 24 Jun 28 04:49:51 PM PDT 24 17292466864 ps
T327 /workspace/coverage/default/33.rom_ctrl_smoke.1275818778 Jun 28 04:49:42 PM PDT 24 Jun 28 04:50:19 PM PDT 24 3861089713 ps
T328 /workspace/coverage/default/12.rom_ctrl_stress_all.2509072024 Jun 28 04:49:05 PM PDT 24 Jun 28 04:50:06 PM PDT 24 23399895150 ps
T329 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2502346515 Jun 28 04:49:05 PM PDT 24 Jun 28 04:51:55 PM PDT 24 8859860104 ps
T330 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1578340203 Jun 28 04:49:36 PM PDT 24 Jun 28 04:49:56 PM PDT 24 4181376780 ps
T331 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1978744641 Jun 28 04:49:06 PM PDT 24 Jun 28 04:52:15 PM PDT 24 35189998877 ps
T332 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.487642188 Jun 28 04:49:56 PM PDT 24 Jun 28 04:50:08 PM PDT 24 3499829609 ps
T333 /workspace/coverage/default/3.rom_ctrl_smoke.3590610259 Jun 28 04:49:00 PM PDT 24 Jun 28 04:49:38 PM PDT 24 8785961201 ps
T334 /workspace/coverage/default/40.rom_ctrl_alert_test.3298432012 Jun 28 04:49:50 PM PDT 24 Jun 28 04:50:09 PM PDT 24 4201286780 ps
T335 /workspace/coverage/default/30.rom_ctrl_alert_test.2320166982 Jun 28 04:49:31 PM PDT 24 Jun 28 04:49:39 PM PDT 24 1277937176 ps
T336 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.853328326 Jun 28 04:49:36 PM PDT 24 Jun 28 04:52:55 PM PDT 24 11544483049 ps
T337 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3257891831 Jun 28 04:49:58 PM PDT 24 Jun 28 04:50:17 PM PDT 24 2013641836 ps
T338 /workspace/coverage/default/18.rom_ctrl_alert_test.3160756146 Jun 28 04:49:11 PM PDT 24 Jun 28 04:49:22 PM PDT 24 3301304290 ps
T339 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.98430644 Jun 28 04:49:18 PM PDT 24 Jun 28 04:53:45 PM PDT 24 52119174144 ps
T340 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3731825673 Jun 28 04:49:43 PM PDT 24 Jun 28 04:49:56 PM PDT 24 168250789 ps
T341 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1671627291 Jun 28 04:49:10 PM PDT 24 Jun 28 04:49:29 PM PDT 24 4644327565 ps
T342 /workspace/coverage/default/32.rom_ctrl_alert_test.411334221 Jun 28 04:49:34 PM PDT 24 Jun 28 04:49:48 PM PDT 24 5292575600 ps
T343 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3099393714 Jun 28 04:49:01 PM PDT 24 Jun 28 04:49:15 PM PDT 24 10475788641 ps
T344 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3629003563 Jun 28 04:49:17 PM PDT 24 Jun 28 05:16:46 PM PDT 24 39047633393 ps
T345 /workspace/coverage/default/37.rom_ctrl_smoke.3831432850 Jun 28 04:49:39 PM PDT 24 Jun 28 04:50:06 PM PDT 24 2833249023 ps
T346 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3904972193 Jun 28 04:49:08 PM PDT 24 Jun 28 04:49:38 PM PDT 24 11798400977 ps
T347 /workspace/coverage/default/8.rom_ctrl_stress_all.3584911136 Jun 28 04:49:06 PM PDT 24 Jun 28 04:50:05 PM PDT 24 11907288644 ps
T348 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2473211872 Jun 28 04:49:53 PM PDT 24 Jun 28 04:50:07 PM PDT 24 2824020326 ps
T349 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1568156427 Jun 28 04:49:52 PM PDT 24 Jun 28 04:52:53 PM PDT 24 67693162129 ps
T350 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.813960811 Jun 28 04:49:03 PM PDT 24 Jun 28 04:49:35 PM PDT 24 3937719363 ps
T351 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2744870572 Jun 28 04:49:19 PM PDT 24 Jun 28 04:49:25 PM PDT 24 568193217 ps
T352 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2235081161 Jun 28 04:49:07 PM PDT 24 Jun 28 04:50:39 PM PDT 24 5829675615 ps
T353 /workspace/coverage/default/11.rom_ctrl_smoke.3539913971 Jun 28 04:49:07 PM PDT 24 Jun 28 04:49:35 PM PDT 24 2743474885 ps
T354 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2210598984 Jun 28 04:49:07 PM PDT 24 Jun 28 04:49:43 PM PDT 24 60157913321 ps
T355 /workspace/coverage/default/19.rom_ctrl_stress_all.204770690 Jun 28 04:49:07 PM PDT 24 Jun 28 04:49:17 PM PDT 24 288985306 ps
T356 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.525887489 Jun 28 04:49:33 PM PDT 24 Jun 28 04:50:05 PM PDT 24 3362645058 ps
T357 /workspace/coverage/default/21.rom_ctrl_alert_test.3437745094 Jun 28 04:49:31 PM PDT 24 Jun 28 04:49:40 PM PDT 24 788143306 ps
T358 /workspace/coverage/default/44.rom_ctrl_stress_all.812039307 Jun 28 04:49:45 PM PDT 24 Jun 28 04:50:51 PM PDT 24 5767109154 ps
T359 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3430054595 Jun 28 04:49:04 PM PDT 24 Jun 28 04:49:10 PM PDT 24 95090439 ps
T360 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2627111375 Jun 28 04:49:18 PM PDT 24 Jun 28 04:50:35 PM PDT 24 4939941410 ps
T361 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1930851901 Jun 28 04:49:06 PM PDT 24 Jun 28 04:54:46 PM PDT 24 125341700088 ps
T362 /workspace/coverage/default/15.rom_ctrl_stress_all.3516920892 Jun 28 04:49:10 PM PDT 24 Jun 28 04:50:09 PM PDT 24 24632285624 ps
T363 /workspace/coverage/default/45.rom_ctrl_smoke.3942739950 Jun 28 04:49:42 PM PDT 24 Jun 28 04:50:16 PM PDT 24 6868979219 ps
T364 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.993682063 Jun 28 04:49:11 PM PDT 24 Jun 28 04:49:40 PM PDT 24 13760328792 ps
T71 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2105420123 Jun 28 05:31:00 PM PDT 24 Jun 28 05:31:19 PM PDT 24 854484385 ps
T72 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2518143079 Jun 28 05:31:07 PM PDT 24 Jun 28 05:31:16 PM PDT 24 268705131 ps
T73 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.132148930 Jun 28 05:31:34 PM PDT 24 Jun 28 05:32:37 PM PDT 24 7494431707 ps
T68 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3574202897 Jun 28 05:31:33 PM PDT 24 Jun 28 05:32:45 PM PDT 24 291134548 ps
T365 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3092782203 Jun 28 05:31:36 PM PDT 24 Jun 28 05:31:51 PM PDT 24 988870472 ps
T366 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.177383498 Jun 28 05:31:07 PM PDT 24 Jun 28 05:31:19 PM PDT 24 570552622 ps
T76 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1820592856 Jun 28 05:30:56 PM PDT 24 Jun 28 05:32:21 PM PDT 24 10279508840 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.550887075 Jun 28 05:30:55 PM PDT 24 Jun 28 05:31:12 PM PDT 24 8339541050 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2320707864 Jun 28 05:30:57 PM PDT 24 Jun 28 05:31:13 PM PDT 24 7246303021 ps
T77 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2416770566 Jun 28 05:31:10 PM PDT 24 Jun 28 05:31:50 PM PDT 24 3615940511 ps
T109 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3633501459 Jun 28 05:30:55 PM PDT 24 Jun 28 05:31:06 PM PDT 24 1245647445 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2611190900 Jun 28 05:30:54 PM PDT 24 Jun 28 05:31:05 PM PDT 24 1088473202 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.769316694 Jun 28 05:31:24 PM PDT 24 Jun 28 05:31:30 PM PDT 24 87963990 ps
T369 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2057921223 Jun 28 05:31:25 PM PDT 24 Jun 28 05:31:41 PM PDT 24 4326273350 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2669271577 Jun 28 05:30:57 PM PDT 24 Jun 28 05:31:07 PM PDT 24 1045583736 ps
T102 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4037413172 Jun 28 05:31:25 PM PDT 24 Jun 28 05:31:39 PM PDT 24 5804856011 ps
T78 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2801209627 Jun 28 05:30:55 PM PDT 24 Jun 28 05:31:07 PM PDT 24 6173914035 ps
T371 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4216187496 Jun 28 05:31:08 PM PDT 24 Jun 28 05:31:19 PM PDT 24 143952386 ps
T112 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3806440853 Jun 28 05:31:26 PM PDT 24 Jun 28 05:31:38 PM PDT 24 13973494902 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.949902680 Jun 28 05:30:56 PM PDT 24 Jun 28 05:32:09 PM PDT 24 7170870342 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1616041325 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:02 PM PDT 24 526639550 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2929712123 Jun 28 05:31:02 PM PDT 24 Jun 28 05:31:09 PM PDT 24 674815959 ps
T79 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2824712003 Jun 28 05:31:39 PM PDT 24 Jun 28 05:32:09 PM PDT 24 2569499760 ps
T103 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.227350883 Jun 28 05:31:10 PM PDT 24 Jun 28 05:31:18 PM PDT 24 424524442 ps
T374 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2669872345 Jun 28 05:31:25 PM PDT 24 Jun 28 05:31:43 PM PDT 24 15581004593 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3349440572 Jun 28 05:31:10 PM PDT 24 Jun 28 05:31:28 PM PDT 24 2633451678 ps
T376 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.298714248 Jun 28 05:31:23 PM PDT 24 Jun 28 05:31:34 PM PDT 24 542981540 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2931873791 Jun 28 05:30:57 PM PDT 24 Jun 28 05:31:14 PM PDT 24 14175361326 ps
T81 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3625970990 Jun 28 05:31:28 PM PDT 24 Jun 28 05:32:31 PM PDT 24 7261347589 ps
T82 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1744863554 Jun 28 05:31:24 PM PDT 24 Jun 28 05:31:39 PM PDT 24 6382249613 ps
T104 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1392147637 Jun 28 05:31:26 PM PDT 24 Jun 28 05:31:39 PM PDT 24 1224878125 ps
T83 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2342766045 Jun 28 05:31:25 PM PDT 24 Jun 28 05:31:32 PM PDT 24 1147142256 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2274776250 Jun 28 05:31:08 PM PDT 24 Jun 28 05:31:15 PM PDT 24 352727986 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3525202093 Jun 28 05:31:08 PM PDT 24 Jun 28 05:31:17 PM PDT 24 185666028 ps
T70 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.723559754 Jun 28 05:31:36 PM PDT 24 Jun 28 05:32:14 PM PDT 24 700275236 ps
T105 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1949438155 Jun 28 05:31:06 PM PDT 24 Jun 28 05:31:11 PM PDT 24 346344669 ps
T378 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1455007957 Jun 28 05:31:37 PM PDT 24 Jun 28 05:31:45 PM PDT 24 1621786154 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2125119296 Jun 28 05:30:57 PM PDT 24 Jun 28 05:31:09 PM PDT 24 4086935658 ps
T380 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.757216947 Jun 28 05:31:23 PM PDT 24 Jun 28 05:31:44 PM PDT 24 3867552839 ps
T381 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2845128248 Jun 28 05:31:10 PM PDT 24 Jun 28 05:31:26 PM PDT 24 3727084320 ps
T382 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2617911104 Jun 28 05:31:34 PM PDT 24 Jun 28 05:31:52 PM PDT 24 3578795315 ps
T383 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3496467559 Jun 28 05:31:22 PM PDT 24 Jun 28 05:31:36 PM PDT 24 1533356181 ps
T117 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2601016206 Jun 28 05:31:08 PM PDT 24 Jun 28 05:31:48 PM PDT 24 1455065718 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1112282576 Jun 28 05:31:09 PM PDT 24 Jun 28 05:31:25 PM PDT 24 11788327156 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1987717449 Jun 28 05:30:46 PM PDT 24 Jun 28 05:32:03 PM PDT 24 7360821838 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4197479356 Jun 28 05:31:24 PM PDT 24 Jun 28 05:31:40 PM PDT 24 3195705477 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1073849726 Jun 28 05:31:24 PM PDT 24 Jun 28 05:31:37 PM PDT 24 4972023141 ps
T385 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4268853537 Jun 28 05:31:24 PM PDT 24 Jun 28 05:31:40 PM PDT 24 1742574107 ps
T89 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1911823620 Jun 28 05:31:23 PM PDT 24 Jun 28 05:32:38 PM PDT 24 8975592170 ps
T107 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3407997571 Jun 28 05:31:28 PM PDT 24 Jun 28 05:31:38 PM PDT 24 941657385 ps
T386 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1442696878 Jun 28 05:31:26 PM PDT 24 Jun 28 05:32:37 PM PDT 24 1423308568 ps
T387 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2207200128 Jun 28 05:31:08 PM PDT 24 Jun 28 05:31:14 PM PDT 24 543046404 ps
T90 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1201556740 Jun 28 05:31:26 PM PDT 24 Jun 28 05:31:44 PM PDT 24 10972666128 ps
T108 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3001916235 Jun 28 05:31:22 PM PDT 24 Jun 28 05:31:34 PM PDT 24 4482494333 ps
T388 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3288328249 Jun 28 05:31:24 PM PDT 24 Jun 28 05:31:30 PM PDT 24 88897589 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3916984380 Jun 28 05:30:58 PM PDT 24 Jun 28 05:31:03 PM PDT 24 153206432 ps
T390 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.530036990 Jun 28 05:31:06 PM PDT 24 Jun 28 05:31:17 PM PDT 24 940554325 ps
T391 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.181257727 Jun 28 05:31:33 PM PDT 24 Jun 28 05:31:50 PM PDT 24 3583677001 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2787367718 Jun 28 05:31:08 PM PDT 24 Jun 28 05:31:21 PM PDT 24 5193909128 ps
T119 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1842053987 Jun 28 05:31:09 PM PDT 24 Jun 28 05:31:55 PM PDT 24 7134999601 ps
T393 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4245191046 Jun 28 05:31:23 PM PDT 24 Jun 28 05:31:40 PM PDT 24 23992574440 ps
T394 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3888782561 Jun 28 05:31:36 PM PDT 24 Jun 28 05:31:45 PM PDT 24 2117981000 ps
T120 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.598576726 Jun 28 05:30:57 PM PDT 24 Jun 28 05:32:13 PM PDT 24 415527887 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4055091313 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:12 PM PDT 24 6282111968 ps
T96 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3712149706 Jun 28 05:31:22 PM PDT 24 Jun 28 05:32:06 PM PDT 24 8065930725 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3996396546 Jun 28 05:31:09 PM PDT 24 Jun 28 05:32:47 PM PDT 24 12067456479 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4148621471 Jun 28 05:31:25 PM PDT 24 Jun 28 05:31:37 PM PDT 24 5399304548 ps
T122 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4012380995 Jun 28 05:31:10 PM PDT 24 Jun 28 05:32:23 PM PDT 24 3597645203 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3288031203 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:10 PM PDT 24 1229594985 ps
T399 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2238618280 Jun 28 05:31:22 PM PDT 24 Jun 28 05:31:31 PM PDT 24 1922286252 ps
T123 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2254493603 Jun 28 05:31:26 PM PDT 24 Jun 28 05:32:46 PM PDT 24 7503113397 ps
T400 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3338927340 Jun 28 05:31:22 PM PDT 24 Jun 28 05:31:40 PM PDT 24 1901382291 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3737553852 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:04 PM PDT 24 438209397 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3408118717 Jun 28 05:31:23 PM PDT 24 Jun 28 05:31:28 PM PDT 24 333973753 ps
T402 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1552654286 Jun 28 05:31:25 PM PDT 24 Jun 28 05:32:31 PM PDT 24 19760031693 ps
T403 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2789313762 Jun 28 05:31:26 PM PDT 24 Jun 28 05:31:35 PM PDT 24 6096615712 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1691521916 Jun 28 05:30:51 PM PDT 24 Jun 28 05:30:56 PM PDT 24 126654338 ps
T405 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4112394759 Jun 28 05:31:24 PM PDT 24 Jun 28 05:31:47 PM PDT 24 2115243003 ps
T125 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1065395274 Jun 28 05:31:25 PM PDT 24 Jun 28 05:32:41 PM PDT 24 16321768729 ps
T406 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1806207638 Jun 28 05:31:33 PM PDT 24 Jun 28 05:32:21 PM PDT 24 5521470221 ps
T407 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2146444316 Jun 28 05:31:26 PM PDT 24 Jun 28 05:31:32 PM PDT 24 171248916 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2695022607 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:11 PM PDT 24 4296080752 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3254720051 Jun 28 05:30:46 PM PDT 24 Jun 28 05:30:58 PM PDT 24 3911907923 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2615398710 Jun 28 05:31:23 PM PDT 24 Jun 28 05:31:36 PM PDT 24 1092546928 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3941974420 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:04 PM PDT 24 1700255781 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4247960404 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:10 PM PDT 24 1282201555 ps
T412 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2979206739 Jun 28 05:31:25 PM PDT 24 Jun 28 05:31:37 PM PDT 24 1091420613 ps
T413 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2595884868 Jun 28 05:31:33 PM PDT 24 Jun 28 05:31:45 PM PDT 24 1238414803 ps
T414 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3502124905 Jun 28 05:31:22 PM PDT 24 Jun 28 05:31:30 PM PDT 24 341310404 ps
T93 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.760272289 Jun 28 05:31:09 PM PDT 24 Jun 28 05:31:21 PM PDT 24 1116020940 ps
T415 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.237398497 Jun 28 05:31:25 PM PDT 24 Jun 28 05:31:37 PM PDT 24 288777242 ps
T416 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1573817468 Jun 28 05:31:26 PM PDT 24 Jun 28 05:32:00 PM PDT 24 2226185910 ps
T417 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1565180324 Jun 28 05:31:33 PM PDT 24 Jun 28 05:31:46 PM PDT 24 1241819398 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3745064030 Jun 28 05:30:48 PM PDT 24 Jun 28 05:31:04 PM PDT 24 7008114504 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.47578749 Jun 28 05:30:57 PM PDT 24 Jun 28 05:31:03 PM PDT 24 88094675 ps
T419 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2780513123 Jun 28 05:31:09 PM PDT 24 Jun 28 05:31:17 PM PDT 24 342222271 ps
T420 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.978934040 Jun 28 05:31:34 PM PDT 24 Jun 28 05:31:46 PM PDT 24 1002455054 ps
T421 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3755132299 Jun 28 05:31:09 PM PDT 24 Jun 28 05:31:15 PM PDT 24 461522703 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2581429256 Jun 28 05:31:28 PM PDT 24 Jun 28 05:31:33 PM PDT 24 193645036 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.695320508 Jun 28 05:30:56 PM PDT 24 Jun 28 05:32:08 PM PDT 24 51211166201 ps
T424 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.800720740 Jun 28 05:31:24 PM PDT 24 Jun 28 05:31:39 PM PDT 24 5949313797 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.320798512 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:05 PM PDT 24 170465878 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2801048183 Jun 28 05:30:52 PM PDT 24 Jun 28 05:32:15 PM PDT 24 36582165809 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2476987348 Jun 28 05:31:21 PM PDT 24 Jun 28 05:31:32 PM PDT 24 2869765893 ps
T427 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.227911293 Jun 28 05:31:23 PM PDT 24 Jun 28 05:32:22 PM PDT 24 14113395365 ps
T428 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1142323707 Jun 28 05:30:47 PM PDT 24 Jun 28 05:30:53 PM PDT 24 259924573 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1994353802 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:12 PM PDT 24 7608672965 ps
T126 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1923417555 Jun 28 05:31:33 PM PDT 24 Jun 28 05:32:48 PM PDT 24 675128633 ps
T430 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.76062057 Jun 28 05:31:34 PM PDT 24 Jun 28 05:31:51 PM PDT 24 7483614121 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.809098495 Jun 28 05:31:09 PM PDT 24 Jun 28 05:31:27 PM PDT 24 8877416124 ps
T432 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3166253665 Jun 28 05:31:23 PM PDT 24 Jun 28 05:32:13 PM PDT 24 2079657775 ps
T433 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.124471971 Jun 28 05:31:34 PM PDT 24 Jun 28 05:31:40 PM PDT 24 421326228 ps
T434 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2331974402 Jun 28 05:31:25 PM PDT 24 Jun 28 05:32:26 PM PDT 24 19145280421 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.495776899 Jun 28 05:30:55 PM PDT 24 Jun 28 05:31:03 PM PDT 24 468785314 ps
T436 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3203116554 Jun 28 05:31:09 PM PDT 24 Jun 28 05:31:26 PM PDT 24 16345452824 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2763294589 Jun 28 05:31:22 PM PDT 24 Jun 28 05:32:12 PM PDT 24 19828480650 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2409439440 Jun 28 05:31:08 PM PDT 24 Jun 28 05:31:49 PM PDT 24 582504547 ps
T439 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3290995858 Jun 28 05:31:36 PM PDT 24 Jun 28 05:31:56 PM PDT 24 1666370203 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2471951045 Jun 28 05:31:23 PM PDT 24 Jun 28 05:32:01 PM PDT 24 507730455 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3017897567 Jun 28 05:31:08 PM PDT 24 Jun 28 05:31:19 PM PDT 24 5105541921 ps
T441 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2456887209 Jun 28 05:31:25 PM PDT 24 Jun 28 05:33:01 PM PDT 24 77557235476 ps
T442 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.701888405 Jun 28 05:31:25 PM PDT 24 Jun 28 05:31:31 PM PDT 24 341458264 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1649466166 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:13 PM PDT 24 2006973695 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3726198056 Jun 28 05:31:08 PM PDT 24 Jun 28 05:31:16 PM PDT 24 411637111 ps
T445 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1804827544 Jun 28 05:31:35 PM PDT 24 Jun 28 05:31:44 PM PDT 24 223808136 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2870728200 Jun 28 05:30:44 PM PDT 24 Jun 28 05:31:01 PM PDT 24 5876365343 ps
T447 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4065094294 Jun 28 05:31:23 PM PDT 24 Jun 28 05:31:39 PM PDT 24 7505811839 ps
T448 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2207082818 Jun 28 05:31:33 PM PDT 24 Jun 28 05:31:39 PM PDT 24 85532821 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1664505929 Jun 28 05:30:58 PM PDT 24 Jun 28 05:31:10 PM PDT 24 2056806799 ps
T121 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.547851949 Jun 28 05:31:26 PM PDT 24 Jun 28 05:32:40 PM PDT 24 558137903 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.379012659 Jun 28 05:30:57 PM PDT 24 Jun 28 05:31:15 PM PDT 24 3651587366 ps
T124 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1571634877 Jun 28 05:30:57 PM PDT 24 Jun 28 05:32:16 PM PDT 24 6841213365 ps
T451 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4227051941 Jun 28 05:31:34 PM PDT 24 Jun 28 05:31:40 PM PDT 24 1032238228 ps
T452 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3749350746 Jun 28 05:30:56 PM PDT 24 Jun 28 05:31:14 PM PDT 24 3928137477 ps
T118 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.282994691 Jun 28 05:31:24 PM PDT 24 Jun 28 05:32:47 PM PDT 24 2492504576 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4090598303 Jun 28 05:31:10 PM PDT 24 Jun 28 05:31:24 PM PDT 24 1558787927 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3257480733 Jun 28 05:30:55 PM PDT 24 Jun 28 05:31:07 PM PDT 24 1024740625 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2363421821 Jun 28 05:30:46 PM PDT 24 Jun 28 05:31:02 PM PDT 24 1621571703 ps
T456 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4045448999 Jun 28 05:31:23 PM PDT 24 Jun 28 05:32:07 PM PDT 24 14457430712 ps
T457 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1775330623 Jun 28 05:31:09 PM PDT 24 Jun 28 05:31:37 PM PDT 24 2226573160 ps
T458 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3949825593 Jun 28 05:31:32 PM PDT 24 Jun 28 05:31:50 PM PDT 24 2130720252 ps
T459 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1480697626 Jun 28 05:31:09 PM PDT 24 Jun 28 05:31:50 PM PDT 24 10177972020 ps
T460 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.743135080 Jun 28 05:31:07 PM PDT 24 Jun 28 05:31:22 PM PDT 24 5758862203 ps
T461 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1838122096 Jun 28 05:31:23 PM PDT 24 Jun 28 05:32:38 PM PDT 24 3557748142 ps
T462 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.149314308 Jun 28 05:30:57 PM PDT 24 Jun 28 05:31:13 PM PDT 24 6993431846 ps

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1991429784
Short name T8
Test name
Test status
Simulation time 11616046367 ps
CPU time 126.39 seconds
Started Jun 28 04:49:27 PM PDT 24
Finished Jun 28 04:51:34 PM PDT 24
Peak memory 218864 kb
Host smart-63ec5962-a188-4e79-a646-791b77fe0004
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991429784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1991429784
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.951692752
Short name T19
Test name
Test status
Simulation time 119400964724 ps
CPU time 1252.47 seconds
Started Jun 28 04:49:45 PM PDT 24
Finished Jun 28 05:10:39 PM PDT 24
Peak memory 235760 kb
Host smart-fa6b1e10-d8da-4962-9151-f9e550e3adff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951692752 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.951692752
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2482302731
Short name T28
Test name
Test status
Simulation time 2507820675 ps
CPU time 141.32 seconds
Started Jun 28 04:49:02 PM PDT 24
Finished Jun 28 04:51:24 PM PDT 24
Peak memory 212552 kb
Host smart-f3fd7897-6675-4a16-a2c9-76b90aae7d63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482302731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2482302731
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2957790276
Short name T37
Test name
Test status
Simulation time 22996703286 ps
CPU time 300.88 seconds
Started Jun 28 04:49:25 PM PDT 24
Finished Jun 28 04:54:28 PM PDT 24
Peak memory 225000 kb
Host smart-8789461c-9510-4068-a77e-dc79ec988147
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957790276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2957790276
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1929771505
Short name T14
Test name
Test status
Simulation time 347133349 ps
CPU time 4.42 seconds
Started Jun 28 04:49:17 PM PDT 24
Finished Jun 28 04:49:22 PM PDT 24
Peak memory 211196 kb
Host smart-4ffa9021-c617-420b-9710-cd22d434cac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929771505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1929771505
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.949902680
Short name T69
Test name
Test status
Simulation time 7170870342 ps
CPU time 72.41 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:32:09 PM PDT 24
Peak memory 219072 kb
Host smart-11ebf12e-46c2-4e3f-ad65-2c865fe80fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949902680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.949902680
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.761070004
Short name T16
Test name
Test status
Simulation time 1497929028 ps
CPU time 16.58 seconds
Started Jun 28 04:49:58 PM PDT 24
Finished Jun 28 04:50:17 PM PDT 24
Peak memory 213496 kb
Host smart-221f528c-a09e-4f4c-9e67-da90d804b6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761070004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.761070004
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4151289363
Short name T36
Test name
Test status
Simulation time 3326816984 ps
CPU time 59.99 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:50:07 PM PDT 24
Peak memory 235724 kb
Host smart-e48bf915-c079-484e-bd2c-e78ab697c325
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151289363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4151289363
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2342766045
Short name T83
Test name
Test status
Simulation time 1147142256 ps
CPU time 6.19 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:31:32 PM PDT 24
Peak memory 210740 kb
Host smart-0a01c89a-2901-4735-9d54-eb3369b74786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342766045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2342766045
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.547851949
Short name T121
Test name
Test status
Simulation time 558137903 ps
CPU time 72.47 seconds
Started Jun 28 05:31:26 PM PDT 24
Finished Jun 28 05:32:40 PM PDT 24
Peak memory 212264 kb
Host smart-3c313d22-661a-469f-84f2-9fb1f2cf8315
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547851949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.547851949
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2105420123
Short name T71
Test name
Test status
Simulation time 854484385 ps
CPU time 18.51 seconds
Started Jun 28 05:31:00 PM PDT 24
Finished Jun 28 05:31:19 PM PDT 24
Peak memory 210684 kb
Host smart-4db20e4d-2878-4b08-80ae-69d771532ccb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105420123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2105420123
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3470859998
Short name T33
Test name
Test status
Simulation time 294629644 ps
CPU time 9.09 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 04:49:22 PM PDT 24
Peak memory 212180 kb
Host smart-6dd5335d-864c-4de2-a87c-3a6d78724aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470859998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3470859998
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.54304041
Short name T176
Test name
Test status
Simulation time 13622965681 ps
CPU time 25.43 seconds
Started Jun 28 04:49:17 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 214212 kb
Host smart-2f0a4a39-fecf-4784-8705-442eb0621ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54304041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.54304041
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3141820674
Short name T52
Test name
Test status
Simulation time 15497718324 ps
CPU time 31.51 seconds
Started Jun 28 04:49:34 PM PDT 24
Finished Jun 28 04:50:07 PM PDT 24
Peak memory 212152 kb
Host smart-8714a0f8-1132-405d-8013-6422d2f2696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141820674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3141820674
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.181925181
Short name T15
Test name
Test status
Simulation time 4883746991 ps
CPU time 11.05 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:20 PM PDT 24
Peak memory 211304 kb
Host smart-a28f9c1a-23a7-4ece-b2f5-8da02422b042
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181925181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.181925181
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3279677058
Short name T43
Test name
Test status
Simulation time 202244310960 ps
CPU time 459 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:56:46 PM PDT 24
Peak memory 212656 kb
Host smart-3f71f81d-bf60-42f8-a077-c6fc2605160b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279677058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3279677058
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2801048183
Short name T95
Test name
Test status
Simulation time 36582165809 ps
CPU time 82.23 seconds
Started Jun 28 05:30:52 PM PDT 24
Finished Jun 28 05:32:15 PM PDT 24
Peak memory 210752 kb
Host smart-f1169376-edb3-42e1-b9cf-56d9994848f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801048183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2801048183
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1987717449
Short name T116
Test name
Test status
Simulation time 7360821838 ps
CPU time 76.48 seconds
Started Jun 28 05:30:46 PM PDT 24
Finished Jun 28 05:32:03 PM PDT 24
Peak memory 212528 kb
Host smart-7d96d47e-4607-4e82-bae2-56a559d52c32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987717449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1987717449
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.672848292
Short name T65
Test name
Test status
Simulation time 6040811804 ps
CPU time 10.42 seconds
Started Jun 28 04:49:09 PM PDT 24
Finished Jun 28 04:49:22 PM PDT 24
Peak memory 211312 kb
Host smart-a21de52b-8b7b-463f-b372-33a6ee0e5436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672848292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.672848292
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.238951549
Short name T56
Test name
Test status
Simulation time 52437737830 ps
CPU time 1644.98 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 05:16:32 PM PDT 24
Peak memory 231008 kb
Host smart-79ba9610-49ce-4c26-96eb-747d032b3351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238951549 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.238951549
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.495776899
Short name T435
Test name
Test status
Simulation time 468785314 ps
CPU time 7.47 seconds
Started Jun 28 05:30:55 PM PDT 24
Finished Jun 28 05:31:03 PM PDT 24
Peak memory 210708 kb
Host smart-2bbc530d-2f31-4839-aff6-19a1a00397ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495776899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.495776899
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1691521916
Short name T404
Test name
Test status
Simulation time 126654338 ps
CPU time 4.44 seconds
Started Jun 28 05:30:51 PM PDT 24
Finished Jun 28 05:30:56 PM PDT 24
Peak memory 210772 kb
Host smart-363a299e-729a-466d-b729-f6030f5a86bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691521916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1691521916
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2363421821
Short name T455
Test name
Test status
Simulation time 1621571703 ps
CPU time 15.28 seconds
Started Jun 28 05:30:46 PM PDT 24
Finished Jun 28 05:31:02 PM PDT 24
Peak memory 210704 kb
Host smart-b79a8333-e670-47d9-a82b-cf8800c6bd5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363421821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2363421821
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1616041325
Short name T372
Test name
Test status
Simulation time 526639550 ps
CPU time 4.66 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:02 PM PDT 24
Peak memory 218984 kb
Host smart-29edc047-0d09-47d7-bc65-eac241a3313a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616041325 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1616041325
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3254720051
Short name T408
Test name
Test status
Simulation time 3911907923 ps
CPU time 10.72 seconds
Started Jun 28 05:30:46 PM PDT 24
Finished Jun 28 05:30:58 PM PDT 24
Peak memory 218780 kb
Host smart-65262a63-2ccb-4303-93ec-72fdc40823ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254720051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3254720051
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3745064030
Short name T418
Test name
Test status
Simulation time 7008114504 ps
CPU time 14.75 seconds
Started Jun 28 05:30:48 PM PDT 24
Finished Jun 28 05:31:04 PM PDT 24
Peak memory 210704 kb
Host smart-53a066c8-d388-4543-9a5c-717ed724ad1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745064030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3745064030
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1142323707
Short name T428
Test name
Test status
Simulation time 259924573 ps
CPU time 4.86 seconds
Started Jun 28 05:30:47 PM PDT 24
Finished Jun 28 05:30:53 PM PDT 24
Peak memory 210620 kb
Host smart-474f3de0-0d31-425e-a18a-560446553acd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142323707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1142323707
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4247960404
Short name T411
Test name
Test status
Simulation time 1282201555 ps
CPU time 11.85 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:10 PM PDT 24
Peak memory 218960 kb
Host smart-db6ecc5d-f554-4d9d-800a-992c5f781baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247960404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4247960404
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2870728200
Short name T446
Test name
Test status
Simulation time 5876365343 ps
CPU time 16.06 seconds
Started Jun 28 05:30:44 PM PDT 24
Finished Jun 28 05:31:01 PM PDT 24
Peak memory 219084 kb
Host smart-6ff4e7a2-7843-4053-ac09-d80faf002f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870728200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2870728200
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.47578749
Short name T94
Test name
Test status
Simulation time 88094675 ps
CPU time 4.24 seconds
Started Jun 28 05:30:57 PM PDT 24
Finished Jun 28 05:31:03 PM PDT 24
Peak memory 210564 kb
Host smart-c6cfb86b-0249-4ee0-b40d-51323f1cf0f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47578749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasi
ng.47578749
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3749350746
Short name T452
Test name
Test status
Simulation time 3928137477 ps
CPU time 15.84 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:14 PM PDT 24
Peak memory 210896 kb
Host smart-b9e2dab0-522e-4fc3-b9e5-1f7e2b0cde9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749350746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3749350746
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.320798512
Short name T425
Test name
Test status
Simulation time 170465878 ps
CPU time 7.2 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:05 PM PDT 24
Peak memory 210560 kb
Host smart-352348c5-4f82-46b7-bfae-7e645bda40aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320798512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.320798512
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2320707864
Short name T368
Test name
Test status
Simulation time 7246303021 ps
CPU time 14.4 seconds
Started Jun 28 05:30:57 PM PDT 24
Finished Jun 28 05:31:13 PM PDT 24
Peak memory 219124 kb
Host smart-97b9574c-68ac-462c-8e18-2a1e40bd841d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320707864 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2320707864
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3257480733
Short name T454
Test name
Test status
Simulation time 1024740625 ps
CPU time 10.46 seconds
Started Jun 28 05:30:55 PM PDT 24
Finished Jun 28 05:31:07 PM PDT 24
Peak memory 218904 kb
Host smart-643cb2c2-cc87-4e56-a5ee-a4f4d9f5a6d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257480733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3257480733
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2929712123
Short name T373
Test name
Test status
Simulation time 674815959 ps
CPU time 6.42 seconds
Started Jun 28 05:31:02 PM PDT 24
Finished Jun 28 05:31:09 PM PDT 24
Peak memory 210604 kb
Host smart-befd0231-c951-40d0-a90f-5f225a6d7b6e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929712123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2929712123
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.550887075
Short name T367
Test name
Test status
Simulation time 8339541050 ps
CPU time 15.88 seconds
Started Jun 28 05:30:55 PM PDT 24
Finished Jun 28 05:31:12 PM PDT 24
Peak memory 210700 kb
Host smart-f727def7-4755-4d9d-abbc-6f0edff9e823
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550887075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
550887075
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.695320508
Short name T423
Test name
Test status
Simulation time 51211166201 ps
CPU time 69.58 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:32:08 PM PDT 24
Peak memory 210844 kb
Host smart-341759c4-c7d9-4218-b99d-1af7ed02abdc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695320508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.695320508
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3941974420
Short name T410
Test name
Test status
Simulation time 1700255781 ps
CPU time 7.43 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:04 PM PDT 24
Peak memory 210660 kb
Host smart-2074a34b-e046-43ba-83a6-e6a88ed21399
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941974420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3941974420
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3737553852
Short name T401
Test name
Test status
Simulation time 438209397 ps
CPU time 6.93 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:04 PM PDT 24
Peak memory 219004 kb
Host smart-2adbe911-f136-45ce-a9c1-8368821363ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737553852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3737553852
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4065094294
Short name T447
Test name
Test status
Simulation time 7505811839 ps
CPU time 15.2 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:31:39 PM PDT 24
Peak memory 219036 kb
Host smart-d9aa5e4c-388f-4f79-9e3b-3aa3ed3b4f46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065094294 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4065094294
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3408118717
Short name T97
Test name
Test status
Simulation time 333973753 ps
CPU time 4.29 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:31:28 PM PDT 24
Peak memory 210772 kb
Host smart-777684d5-0e20-48e6-ae80-1e7705ef07cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408118717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3408118717
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1552654286
Short name T402
Test name
Test status
Simulation time 19760031693 ps
CPU time 64.63 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:32:31 PM PDT 24
Peak memory 211016 kb
Host smart-5fc5808e-a9f0-4a07-9c45-a7a6f8a44835
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552654286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1552654286
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.4037413172
Short name T102
Test name
Test status
Simulation time 5804856011 ps
CPU time 12.29 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:31:39 PM PDT 24
Peak memory 210880 kb
Host smart-b0349940-7dd3-47ab-b575-b5287f998e2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037413172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.4037413172
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.757216947
Short name T380
Test name
Test status
Simulation time 3867552839 ps
CPU time 19.53 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:31:44 PM PDT 24
Peak memory 219072 kb
Host smart-b6f10540-4df6-4526-b305-24afb32e0bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757216947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.757216947
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2471951045
Short name T440
Test name
Test status
Simulation time 507730455 ps
CPU time 37.33 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:32:01 PM PDT 24
Peak memory 218972 kb
Host smart-c52703ee-5cfb-4449-bc9c-4296d2b03f93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471951045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2471951045
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2669872345
Short name T374
Test name
Test status
Simulation time 15581004593 ps
CPU time 16.71 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:31:43 PM PDT 24
Peak memory 219056 kb
Host smart-b7adb4f0-c624-4689-8d3e-b2a4a5af303d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669872345 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2669872345
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.769316694
Short name T111
Test name
Test status
Simulation time 87963990 ps
CPU time 4.39 seconds
Started Jun 28 05:31:24 PM PDT 24
Finished Jun 28 05:31:30 PM PDT 24
Peak memory 210768 kb
Host smart-eac505db-63f7-4368-903c-b855f2909b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769316694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.769316694
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.227911293
Short name T427
Test name
Test status
Simulation time 14113395365 ps
CPU time 58.27 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:32:22 PM PDT 24
Peak memory 210816 kb
Host smart-179c3836-b2f8-488b-842a-000010a7ba44
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227911293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.227911293
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2146444316
Short name T407
Test name
Test status
Simulation time 171248916 ps
CPU time 4.39 seconds
Started Jun 28 05:31:26 PM PDT 24
Finished Jun 28 05:31:32 PM PDT 24
Peak memory 218756 kb
Host smart-f7259cfa-3944-4041-93bc-737ad44dec7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146444316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2146444316
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2057921223
Short name T369
Test name
Test status
Simulation time 4326273350 ps
CPU time 14.08 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:31:41 PM PDT 24
Peak memory 219064 kb
Host smart-e2d212eb-e3eb-4183-9c3b-c4a3a7ac81b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057921223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2057921223
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2979206739
Short name T412
Test name
Test status
Simulation time 1091420613 ps
CPU time 10.89 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 215436 kb
Host smart-cd79456a-1efb-4321-98a0-287844f07a62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979206739 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2979206739
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2615398710
Short name T409
Test name
Test status
Simulation time 1092546928 ps
CPU time 11.68 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:31:36 PM PDT 24
Peak memory 218908 kb
Host smart-64afacb4-7b48-4b7e-85dc-8a954d91f846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615398710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2615398710
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1573817468
Short name T416
Test name
Test status
Simulation time 2226185910 ps
CPU time 33.57 seconds
Started Jun 28 05:31:26 PM PDT 24
Finished Jun 28 05:32:00 PM PDT 24
Peak memory 211016 kb
Host smart-bca45de3-356c-46e0-8d3d-83f8b5e125aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573817468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1573817468
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3288328249
Short name T388
Test name
Test status
Simulation time 88897589 ps
CPU time 4.3 seconds
Started Jun 28 05:31:24 PM PDT 24
Finished Jun 28 05:31:30 PM PDT 24
Peak memory 210808 kb
Host smart-46c2a82b-418c-4d9e-b56e-a51b5531afc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288328249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3288328249
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4112394759
Short name T405
Test name
Test status
Simulation time 2115243003 ps
CPU time 21.37 seconds
Started Jun 28 05:31:24 PM PDT 24
Finished Jun 28 05:31:47 PM PDT 24
Peak memory 216736 kb
Host smart-ebe48d45-b6f5-4e9d-bb7d-b1a3e4b6ded3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112394759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4112394759
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1838122096
Short name T461
Test name
Test status
Simulation time 3557748142 ps
CPU time 72.7 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:32:38 PM PDT 24
Peak memory 212284 kb
Host smart-bb1b57ed-4d53-43af-95c1-df5fa1037dea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838122096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1838122096
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2581429256
Short name T422
Test name
Test status
Simulation time 193645036 ps
CPU time 4.94 seconds
Started Jun 28 05:31:28 PM PDT 24
Finished Jun 28 05:31:33 PM PDT 24
Peak memory 214008 kb
Host smart-308114d8-5d90-4b1b-8370-a628bca7eab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581429256 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2581429256
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3712149706
Short name T96
Test name
Test status
Simulation time 8065930725 ps
CPU time 43.45 seconds
Started Jun 28 05:31:22 PM PDT 24
Finished Jun 28 05:32:06 PM PDT 24
Peak memory 211844 kb
Host smart-7fd37579-7d5a-4eb1-867f-5f66df05e953
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712149706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3712149706
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3407997571
Short name T107
Test name
Test status
Simulation time 941657385 ps
CPU time 9.26 seconds
Started Jun 28 05:31:28 PM PDT 24
Finished Jun 28 05:31:38 PM PDT 24
Peak memory 210832 kb
Host smart-4d551437-3d09-4afc-b343-eb31798c9dba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407997571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3407997571
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3502124905
Short name T414
Test name
Test status
Simulation time 341310404 ps
CPU time 7.43 seconds
Started Jun 28 05:31:22 PM PDT 24
Finished Jun 28 05:31:30 PM PDT 24
Peak memory 219020 kb
Host smart-ae1192dd-a96f-4028-8314-052deb8b0bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502124905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3502124905
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2254493603
Short name T123
Test name
Test status
Simulation time 7503113397 ps
CPU time 78.7 seconds
Started Jun 28 05:31:26 PM PDT 24
Finished Jun 28 05:32:46 PM PDT 24
Peak memory 218888 kb
Host smart-138ed5c1-dbd5-4ccf-8fcb-614a51ae1d31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254493603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2254493603
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.800720740
Short name T424
Test name
Test status
Simulation time 5949313797 ps
CPU time 13.08 seconds
Started Jun 28 05:31:24 PM PDT 24
Finished Jun 28 05:31:39 PM PDT 24
Peak memory 219056 kb
Host smart-b1f6ea97-0b1f-460c-908c-dcd9e1d5eee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800720740 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.800720740
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3806440853
Short name T112
Test name
Test status
Simulation time 13973494902 ps
CPU time 11 seconds
Started Jun 28 05:31:26 PM PDT 24
Finished Jun 28 05:31:38 PM PDT 24
Peak memory 218912 kb
Host smart-51683462-ef69-4802-8d06-3c60f82cb4d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806440853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3806440853
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2763294589
Short name T437
Test name
Test status
Simulation time 19828480650 ps
CPU time 48.6 seconds
Started Jun 28 05:31:22 PM PDT 24
Finished Jun 28 05:32:12 PM PDT 24
Peak memory 218968 kb
Host smart-496ccae6-915a-4cd7-b7a7-c4a56dc04748
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763294589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2763294589
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4197479356
Short name T106
Test name
Test status
Simulation time 3195705477 ps
CPU time 14.84 seconds
Started Jun 28 05:31:24 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 219024 kb
Host smart-224df736-f997-4257-8384-7aa578ee631a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197479356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4197479356
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1073849726
Short name T384
Test name
Test status
Simulation time 4972023141 ps
CPU time 11.42 seconds
Started Jun 28 05:31:24 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 219080 kb
Host smart-cc434af6-3ff4-4d29-a3ff-341cfd521910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073849726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1073849726
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3166253665
Short name T432
Test name
Test status
Simulation time 2079657775 ps
CPU time 48.75 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:32:13 PM PDT 24
Peak memory 212008 kb
Host smart-3ce2e9e1-a995-4441-ab6c-59dfb422ecf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166253665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3166253665
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2476987348
Short name T426
Test name
Test status
Simulation time 2869765893 ps
CPU time 9.82 seconds
Started Jun 28 05:31:21 PM PDT 24
Finished Jun 28 05:31:32 PM PDT 24
Peak memory 219044 kb
Host smart-48202549-b05a-4022-8394-680f5fba51a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476987348 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2476987348
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2238618280
Short name T399
Test name
Test status
Simulation time 1922286252 ps
CPU time 8.43 seconds
Started Jun 28 05:31:22 PM PDT 24
Finished Jun 28 05:31:31 PM PDT 24
Peak memory 218820 kb
Host smart-584acb42-890e-406b-809e-63c1ca57bb57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238618280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2238618280
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1911823620
Short name T89
Test name
Test status
Simulation time 8975592170 ps
CPU time 74.69 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:32:38 PM PDT 24
Peak memory 211840 kb
Host smart-c043d818-e99c-43c4-aef3-a01aff6bb91c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911823620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1911823620
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2789313762
Short name T403
Test name
Test status
Simulation time 6096615712 ps
CPU time 7.08 seconds
Started Jun 28 05:31:26 PM PDT 24
Finished Jun 28 05:31:35 PM PDT 24
Peak memory 210568 kb
Host smart-bc04d658-9edf-4aae-b72d-3ca312013e1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789313762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2789313762
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.298714248
Short name T376
Test name
Test status
Simulation time 542981540 ps
CPU time 9.94 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:31:34 PM PDT 24
Peak memory 219008 kb
Host smart-bda2cb40-4a09-400f-8e1b-027af1ace2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298714248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.298714248
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.282994691
Short name T118
Test name
Test status
Simulation time 2492504576 ps
CPU time 80.75 seconds
Started Jun 28 05:31:24 PM PDT 24
Finished Jun 28 05:32:47 PM PDT 24
Peak memory 212116 kb
Host smart-9f8cafdb-b3bc-47ea-91f1-9c4adaeb0696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282994691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.282994691
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3949825593
Short name T458
Test name
Test status
Simulation time 2130720252 ps
CPU time 17.14 seconds
Started Jun 28 05:31:32 PM PDT 24
Finished Jun 28 05:31:50 PM PDT 24
Peak memory 219000 kb
Host smart-66c668ea-e6ba-43d6-a4ab-bc4b144e0b74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949825593 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3949825593
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4227051941
Short name T451
Test name
Test status
Simulation time 1032238228 ps
CPU time 5.45 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 218048 kb
Host smart-070878ed-8367-4601-bc79-b0b6b73ed591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227051941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4227051941
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3625970990
Short name T81
Test name
Test status
Simulation time 7261347589 ps
CPU time 62.45 seconds
Started Jun 28 05:31:28 PM PDT 24
Finished Jun 28 05:32:31 PM PDT 24
Peak memory 210816 kb
Host smart-76c8f285-38f5-45e7-9b88-267021f8856d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625970990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3625970990
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1804827544
Short name T445
Test name
Test status
Simulation time 223808136 ps
CPU time 7.7 seconds
Started Jun 28 05:31:35 PM PDT 24
Finished Jun 28 05:31:44 PM PDT 24
Peak memory 218960 kb
Host smart-26796f7f-9ad8-4afb-ad8b-fe53defe36a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804827544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1804827544
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.237398497
Short name T415
Test name
Test status
Simulation time 288777242 ps
CPU time 10.46 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 218980 kb
Host smart-47fb2309-19c3-4bd7-b302-aa4001579bbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237398497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.237398497
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1065395274
Short name T125
Test name
Test status
Simulation time 16321768729 ps
CPU time 74.52 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:32:41 PM PDT 24
Peak memory 219048 kb
Host smart-49bfeda6-4c2f-4681-a9d4-8608500f02af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065395274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1065395274
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.978934040
Short name T420
Test name
Test status
Simulation time 1002455054 ps
CPU time 11.3 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:46 PM PDT 24
Peak memory 219248 kb
Host smart-7d8a12c3-2dc8-4ace-be28-dbf8e6681b07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978934040 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.978934040
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1455007957
Short name T378
Test name
Test status
Simulation time 1621786154 ps
CPU time 6.92 seconds
Started Jun 28 05:31:37 PM PDT 24
Finished Jun 28 05:31:45 PM PDT 24
Peak memory 218084 kb
Host smart-090ae5b8-67e2-4701-b031-439bf21af818
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455007957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1455007957
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2824712003
Short name T79
Test name
Test status
Simulation time 2569499760 ps
CPU time 28.89 seconds
Started Jun 28 05:31:39 PM PDT 24
Finished Jun 28 05:32:09 PM PDT 24
Peak memory 210612 kb
Host smart-8b3c4b72-c8d0-4118-8a13-d00c624e1b19
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824712003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2824712003
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1565180324
Short name T417
Test name
Test status
Simulation time 1241819398 ps
CPU time 11.23 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:31:46 PM PDT 24
Peak memory 218964 kb
Host smart-67499956-bc67-4d98-a3e7-7b407ba8c455
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565180324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1565180324
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3092782203
Short name T365
Test name
Test status
Simulation time 988870472 ps
CPU time 13.96 seconds
Started Jun 28 05:31:36 PM PDT 24
Finished Jun 28 05:31:51 PM PDT 24
Peak memory 218904 kb
Host smart-5609d23b-6d63-42c7-af48-095620a3559a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092782203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3092782203
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.723559754
Short name T70
Test name
Test status
Simulation time 700275236 ps
CPU time 37.05 seconds
Started Jun 28 05:31:36 PM PDT 24
Finished Jun 28 05:32:14 PM PDT 24
Peak memory 211940 kb
Host smart-1acd2cad-fff6-4e4a-b681-f365285d8545
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723559754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.723559754
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2595884868
Short name T413
Test name
Test status
Simulation time 1238414803 ps
CPU time 11.76 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:31:45 PM PDT 24
Peak memory 218948 kb
Host smart-f4248e95-db43-491e-88ac-4e4e2b99dfa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595884868 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2595884868
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.76062057
Short name T430
Test name
Test status
Simulation time 7483614121 ps
CPU time 15.25 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:51 PM PDT 24
Peak memory 210768 kb
Host smart-691880c6-4173-4e04-89c5-530e8b507ead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76062057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.76062057
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1806207638
Short name T406
Test name
Test status
Simulation time 5521470221 ps
CPU time 47.55 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:32:21 PM PDT 24
Peak memory 210664 kb
Host smart-a342188e-ee14-4d05-965c-e77af1a51510
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806207638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1806207638
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2207082818
Short name T448
Test name
Test status
Simulation time 85532821 ps
CPU time 4.51 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:31:39 PM PDT 24
Peak memory 210800 kb
Host smart-0f8948c0-a349-4112-a27d-94921d62d399
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207082818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2207082818
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3290995858
Short name T439
Test name
Test status
Simulation time 1666370203 ps
CPU time 18.58 seconds
Started Jun 28 05:31:36 PM PDT 24
Finished Jun 28 05:31:56 PM PDT 24
Peak memory 218996 kb
Host smart-fdbfc770-0b11-404f-8a07-e7c2fee345e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290995858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3290995858
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1923417555
Short name T126
Test name
Test status
Simulation time 675128633 ps
CPU time 73.7 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:32:48 PM PDT 24
Peak memory 211280 kb
Host smart-dbe11098-ed40-4e08-8d12-2b49dbaae9c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923417555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1923417555
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.124471971
Short name T433
Test name
Test status
Simulation time 421326228 ps
CPU time 5.19 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 219000 kb
Host smart-2d17f9ae-5c87-4f8c-b178-9716c39ea98b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124471971 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.124471971
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3888782561
Short name T394
Test name
Test status
Simulation time 2117981000 ps
CPU time 7.76 seconds
Started Jun 28 05:31:36 PM PDT 24
Finished Jun 28 05:31:45 PM PDT 24
Peak memory 210708 kb
Host smart-9b954c8d-38a8-4bca-ae6e-35dedd056e61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888782561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3888782561
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.132148930
Short name T73
Test name
Test status
Simulation time 7494431707 ps
CPU time 62 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:32:37 PM PDT 24
Peak memory 210840 kb
Host smart-7d6a66d6-1ce1-4647-a17b-2b1faff59cb3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132148930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.132148930
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.181257727
Short name T391
Test name
Test status
Simulation time 3583677001 ps
CPU time 16.51 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:31:50 PM PDT 24
Peak memory 210820 kb
Host smart-ef61f462-11fa-4d6d-b946-cd3f0aec27f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181257727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.181257727
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2617911104
Short name T382
Test name
Test status
Simulation time 3578795315 ps
CPU time 16.52 seconds
Started Jun 28 05:31:34 PM PDT 24
Finished Jun 28 05:31:52 PM PDT 24
Peak memory 219084 kb
Host smart-117ee311-bd30-4c7d-a0da-3db9ca38e7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617911104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2617911104
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3574202897
Short name T68
Test name
Test status
Simulation time 291134548 ps
CPU time 71.39 seconds
Started Jun 28 05:31:33 PM PDT 24
Finished Jun 28 05:32:45 PM PDT 24
Peak memory 213336 kb
Host smart-d2d1502f-4e36-4e35-a51e-2dbfcedc1131
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574202897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3574202897
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2125119296
Short name T379
Test name
Test status
Simulation time 4086935658 ps
CPU time 10.94 seconds
Started Jun 28 05:30:57 PM PDT 24
Finished Jun 28 05:31:09 PM PDT 24
Peak memory 210832 kb
Host smart-e1fb05c3-b12b-4f9b-87d6-239e0853cd27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125119296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2125119296
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3633501459
Short name T109
Test name
Test status
Simulation time 1245647445 ps
CPU time 10.87 seconds
Started Jun 28 05:30:55 PM PDT 24
Finished Jun 28 05:31:06 PM PDT 24
Peak memory 218372 kb
Host smart-aee72890-d499-46b6-96e1-3265e9981cc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633501459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3633501459
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2695022607
Short name T92
Test name
Test status
Simulation time 4296080752 ps
CPU time 13.62 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:11 PM PDT 24
Peak memory 218328 kb
Host smart-39def988-82d7-4d69-8694-d23d1b516fe6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695022607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2695022607
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2669271577
Short name T370
Test name
Test status
Simulation time 1045583736 ps
CPU time 8.24 seconds
Started Jun 28 05:30:57 PM PDT 24
Finished Jun 28 05:31:07 PM PDT 24
Peak memory 219060 kb
Host smart-d11536da-1e4f-4288-b75c-d2945e98e1c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669271577 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2669271577
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2931873791
Short name T80
Test name
Test status
Simulation time 14175361326 ps
CPU time 15.26 seconds
Started Jun 28 05:30:57 PM PDT 24
Finished Jun 28 05:31:14 PM PDT 24
Peak memory 210816 kb
Host smart-eeaaaecd-b3a0-4621-a3b1-9cc21fcb7119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931873791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2931873791
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3288031203
Short name T398
Test name
Test status
Simulation time 1229594985 ps
CPU time 11.46 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:10 PM PDT 24
Peak memory 210636 kb
Host smart-d4913532-2359-4aee-a5e4-6680cd733ad1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288031203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3288031203
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4055091313
Short name T395
Test name
Test status
Simulation time 6282111968 ps
CPU time 13.97 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:12 PM PDT 24
Peak memory 210704 kb
Host smart-f5cd5d73-569b-4554-af6e-c3ec36d5179d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055091313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4055091313
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2801209627
Short name T78
Test name
Test status
Simulation time 6173914035 ps
CPU time 11.55 seconds
Started Jun 28 05:30:55 PM PDT 24
Finished Jun 28 05:31:07 PM PDT 24
Peak memory 211128 kb
Host smart-032cf6ea-26f0-4585-83d8-bbd86096c327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801209627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2801209627
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1664505929
Short name T449
Test name
Test status
Simulation time 2056806799 ps
CPU time 10.71 seconds
Started Jun 28 05:30:58 PM PDT 24
Finished Jun 28 05:31:10 PM PDT 24
Peak memory 218896 kb
Host smart-aefa85ff-7f37-4591-bcb5-4de5046e34a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664505929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1664505929
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.598576726
Short name T120
Test name
Test status
Simulation time 415527887 ps
CPU time 74.26 seconds
Started Jun 28 05:30:57 PM PDT 24
Finished Jun 28 05:32:13 PM PDT 24
Peak memory 213240 kb
Host smart-589889dc-2898-4dc9-8e83-1ee85301c4d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598576726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.598576726
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.760272289
Short name T93
Test name
Test status
Simulation time 1116020940 ps
CPU time 10.5 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:31:21 PM PDT 24
Peak memory 218908 kb
Host smart-43889ff5-f215-49fa-958b-975d07053476
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760272289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.760272289
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.149314308
Short name T462
Test name
Test status
Simulation time 6993431846 ps
CPU time 14.09 seconds
Started Jun 28 05:30:57 PM PDT 24
Finished Jun 28 05:31:13 PM PDT 24
Peak memory 218836 kb
Host smart-0c576bd3-7c55-492d-853c-b99a1cd2e910
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149314308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.149314308
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2611190900
Short name T110
Test name
Test status
Simulation time 1088473202 ps
CPU time 11.41 seconds
Started Jun 28 05:30:54 PM PDT 24
Finished Jun 28 05:31:05 PM PDT 24
Peak memory 210752 kb
Host smart-1c74725d-e753-47d4-ba73-40ff0d0db125
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611190900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2611190900
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2274776250
Short name T377
Test name
Test status
Simulation time 352727986 ps
CPU time 7.14 seconds
Started Jun 28 05:31:08 PM PDT 24
Finished Jun 28 05:31:15 PM PDT 24
Peak memory 219060 kb
Host smart-29b6294b-966d-47e8-832d-d2179325a000
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274776250 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2274776250
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1649466166
Short name T443
Test name
Test status
Simulation time 2006973695 ps
CPU time 15.9 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:13 PM PDT 24
Peak memory 218968 kb
Host smart-ce5df64c-a2a9-49ed-8532-c0fb1738aea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649466166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1649466166
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3916984380
Short name T389
Test name
Test status
Simulation time 153206432 ps
CPU time 4.27 seconds
Started Jun 28 05:30:58 PM PDT 24
Finished Jun 28 05:31:03 PM PDT 24
Peak memory 210592 kb
Host smart-10920926-3fa4-4a76-a4ef-5b66698d7e63
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916984380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3916984380
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1994353802
Short name T429
Test name
Test status
Simulation time 7608672965 ps
CPU time 15.53 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:31:12 PM PDT 24
Peak memory 210644 kb
Host smart-853ada5e-483a-4ae7-82e0-0ceb7217cdf8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994353802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1994353802
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1820592856
Short name T76
Test name
Test status
Simulation time 10279508840 ps
CPU time 84.62 seconds
Started Jun 28 05:30:56 PM PDT 24
Finished Jun 28 05:32:21 PM PDT 24
Peak memory 211860 kb
Host smart-c6ad6fd5-f8ce-4c08-8975-675a258dc53c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820592856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1820592856
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4090598303
Short name T453
Test name
Test status
Simulation time 1558787927 ps
CPU time 13.5 seconds
Started Jun 28 05:31:10 PM PDT 24
Finished Jun 28 05:31:24 PM PDT 24
Peak memory 210832 kb
Host smart-f786b960-e59d-455b-8014-e8daaedf189a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090598303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4090598303
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.379012659
Short name T450
Test name
Test status
Simulation time 3651587366 ps
CPU time 16.56 seconds
Started Jun 28 05:30:57 PM PDT 24
Finished Jun 28 05:31:15 PM PDT 24
Peak memory 219076 kb
Host smart-f119fa5d-7c65-437a-a423-d0ad703a210e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379012659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.379012659
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1571634877
Short name T124
Test name
Test status
Simulation time 6841213365 ps
CPU time 77.32 seconds
Started Jun 28 05:30:57 PM PDT 24
Finished Jun 28 05:32:16 PM PDT 24
Peak memory 219072 kb
Host smart-02846d1e-09f6-4629-a101-5f1633a78954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571634877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1571634877
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3017897567
Short name T91
Test name
Test status
Simulation time 5105541921 ps
CPU time 11.23 seconds
Started Jun 28 05:31:08 PM PDT 24
Finished Jun 28 05:31:19 PM PDT 24
Peak memory 210748 kb
Host smart-0d09d6c7-dcd1-40be-9b66-fc460e82889b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017897567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3017897567
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.743135080
Short name T460
Test name
Test status
Simulation time 5758862203 ps
CPU time 14.02 seconds
Started Jun 28 05:31:07 PM PDT 24
Finished Jun 28 05:31:22 PM PDT 24
Peak memory 210720 kb
Host smart-7a3fb6a3-7f16-4bcb-87e6-eb2d6111f084
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743135080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.743135080
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3525202093
Short name T87
Test name
Test status
Simulation time 185666028 ps
CPU time 7.7 seconds
Started Jun 28 05:31:08 PM PDT 24
Finished Jun 28 05:31:17 PM PDT 24
Peak memory 218668 kb
Host smart-27e18a22-c2c6-495b-81cf-faf04d8f8be3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525202093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3525202093
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.809098495
Short name T431
Test name
Test status
Simulation time 8877416124 ps
CPU time 16.81 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:31:27 PM PDT 24
Peak memory 219100 kb
Host smart-cd2e8f78-4c8c-4d15-87cc-dc31b40d26fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809098495 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.809098495
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1112282576
Short name T88
Test name
Test status
Simulation time 11788327156 ps
CPU time 14.89 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:31:25 PM PDT 24
Peak memory 210832 kb
Host smart-fdf4c74d-96dc-4bdc-96db-a8d1441d5209
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112282576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1112282576
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2787367718
Short name T392
Test name
Test status
Simulation time 5193909128 ps
CPU time 10.84 seconds
Started Jun 28 05:31:08 PM PDT 24
Finished Jun 28 05:31:21 PM PDT 24
Peak memory 210648 kb
Host smart-fbcd8363-d34c-4112-b768-ee39cd6e4ac6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787367718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2787367718
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3726198056
Short name T444
Test name
Test status
Simulation time 411637111 ps
CPU time 7.1 seconds
Started Jun 28 05:31:08 PM PDT 24
Finished Jun 28 05:31:16 PM PDT 24
Peak memory 210596 kb
Host smart-92379fa8-b131-48a0-8322-28b044d576df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726198056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3726198056
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3996396546
Short name T396
Test name
Test status
Simulation time 12067456479 ps
CPU time 96.33 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:32:47 PM PDT 24
Peak memory 210732 kb
Host smart-ef47f562-fcba-4b0d-b366-d610df5d4721
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996396546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3996396546
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.227350883
Short name T103
Test name
Test status
Simulation time 424524442 ps
CPU time 7.05 seconds
Started Jun 28 05:31:10 PM PDT 24
Finished Jun 28 05:31:18 PM PDT 24
Peak memory 210832 kb
Host smart-02c1f1d2-2dad-4592-9471-b7bcc394215b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227350883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.227350883
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3349440572
Short name T375
Test name
Test status
Simulation time 2633451678 ps
CPU time 16.64 seconds
Started Jun 28 05:31:10 PM PDT 24
Finished Jun 28 05:31:28 PM PDT 24
Peak memory 219068 kb
Host smart-29b54a08-a81e-4224-a91f-17c3099fbcc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349440572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3349440572
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1842053987
Short name T119
Test name
Test status
Simulation time 7134999601 ps
CPU time 45.05 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:31:55 PM PDT 24
Peak memory 219016 kb
Host smart-30eaa9aa-45d6-4213-a8b4-460252352210
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842053987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1842053987
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2845128248
Short name T381
Test name
Test status
Simulation time 3727084320 ps
CPU time 14.31 seconds
Started Jun 28 05:31:10 PM PDT 24
Finished Jun 28 05:31:26 PM PDT 24
Peak memory 219128 kb
Host smart-731bf4bd-1e3b-40a8-bfbd-0565f80d0a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845128248 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2845128248
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2780513123
Short name T419
Test name
Test status
Simulation time 342222271 ps
CPU time 6.46 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:31:17 PM PDT 24
Peak memory 210700 kb
Host smart-ca195950-bc40-46f1-ba96-73b6ebc0d89e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780513123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2780513123
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1775330623
Short name T457
Test name
Test status
Simulation time 2226573160 ps
CPU time 27.63 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 210736 kb
Host smart-d4191891-1025-489d-baa0-b6ed22f31a2d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775330623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1775330623
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.530036990
Short name T390
Test name
Test status
Simulation time 940554325 ps
CPU time 10.15 seconds
Started Jun 28 05:31:06 PM PDT 24
Finished Jun 28 05:31:17 PM PDT 24
Peak memory 210828 kb
Host smart-633c4c69-4e54-46fb-8a98-27a9e7e910a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530036990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.530036990
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.177383498
Short name T366
Test name
Test status
Simulation time 570552622 ps
CPU time 11.1 seconds
Started Jun 28 05:31:07 PM PDT 24
Finished Jun 28 05:31:19 PM PDT 24
Peak memory 218888 kb
Host smart-c7386edb-b79d-4731-b75e-141395e28b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177383498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.177383498
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4012380995
Short name T122
Test name
Test status
Simulation time 3597645203 ps
CPU time 71.82 seconds
Started Jun 28 05:31:10 PM PDT 24
Finished Jun 28 05:32:23 PM PDT 24
Peak memory 219036 kb
Host smart-43f410cf-8447-44c1-b682-339e90a7c733
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012380995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4012380995
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2518143079
Short name T72
Test name
Test status
Simulation time 268705131 ps
CPU time 7.69 seconds
Started Jun 28 05:31:07 PM PDT 24
Finished Jun 28 05:31:16 PM PDT 24
Peak memory 215804 kb
Host smart-eb26010d-c20a-45c4-ae77-2648034a7cc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518143079 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2518143079
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2207200128
Short name T387
Test name
Test status
Simulation time 543046404 ps
CPU time 5.27 seconds
Started Jun 28 05:31:08 PM PDT 24
Finished Jun 28 05:31:14 PM PDT 24
Peak memory 217872 kb
Host smart-71de6089-304b-4bb0-a66a-bf3c52903609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207200128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2207200128
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1480697626
Short name T459
Test name
Test status
Simulation time 10177972020 ps
CPU time 39.96 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:31:50 PM PDT 24
Peak memory 210772 kb
Host smart-ea185d2c-8bec-43f5-b29a-31b9f2844183
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480697626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1480697626
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1949438155
Short name T105
Test name
Test status
Simulation time 346344669 ps
CPU time 4.53 seconds
Started Jun 28 05:31:06 PM PDT 24
Finished Jun 28 05:31:11 PM PDT 24
Peak memory 210832 kb
Host smart-5c9a8388-f4cc-4a58-a2f0-4137107fbcc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949438155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1949438155
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4216187496
Short name T371
Test name
Test status
Simulation time 143952386 ps
CPU time 10.07 seconds
Started Jun 28 05:31:08 PM PDT 24
Finished Jun 28 05:31:19 PM PDT 24
Peak memory 214780 kb
Host smart-7aebe39b-25a1-4ded-b91e-9b47d3317055
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216187496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4216187496
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2601016206
Short name T117
Test name
Test status
Simulation time 1455065718 ps
CPU time 38.47 seconds
Started Jun 28 05:31:08 PM PDT 24
Finished Jun 28 05:31:48 PM PDT 24
Peak memory 211252 kb
Host smart-5d93b4dd-a826-4f2d-a4fe-888e65cbd43f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601016206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2601016206
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4268853537
Short name T385
Test name
Test status
Simulation time 1742574107 ps
CPU time 13.97 seconds
Started Jun 28 05:31:24 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 214892 kb
Host smart-2acf4179-5b10-4808-b3fc-c2634d218597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268853537 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4268853537
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3755132299
Short name T421
Test name
Test status
Simulation time 461522703 ps
CPU time 4.36 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:31:15 PM PDT 24
Peak memory 217960 kb
Host smart-0f4bb173-5c93-4d24-84fe-b64ae1602a03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755132299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3755132299
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2416770566
Short name T77
Test name
Test status
Simulation time 3615940511 ps
CPU time 38.43 seconds
Started Jun 28 05:31:10 PM PDT 24
Finished Jun 28 05:31:50 PM PDT 24
Peak memory 210824 kb
Host smart-95f4bab2-0a91-47f1-90bb-71edbb89e6f2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416770566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2416770566
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1392147637
Short name T104
Test name
Test status
Simulation time 1224878125 ps
CPU time 11.67 seconds
Started Jun 28 05:31:26 PM PDT 24
Finished Jun 28 05:31:39 PM PDT 24
Peak memory 210832 kb
Host smart-7f17950a-181b-446b-b75f-ffe3abb6d38d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392147637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1392147637
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3203116554
Short name T436
Test name
Test status
Simulation time 16345452824 ps
CPU time 16.3 seconds
Started Jun 28 05:31:09 PM PDT 24
Finished Jun 28 05:31:26 PM PDT 24
Peak memory 219076 kb
Host smart-0f5b7649-d5c0-4fbd-b1aa-c36c1c8641b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203116554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3203116554
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2409439440
Short name T438
Test name
Test status
Simulation time 582504547 ps
CPU time 39.89 seconds
Started Jun 28 05:31:08 PM PDT 24
Finished Jun 28 05:31:49 PM PDT 24
Peak memory 219004 kb
Host smart-ad544848-2c4c-4020-8d4f-3bcdccded5f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409439440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2409439440
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3496467559
Short name T383
Test name
Test status
Simulation time 1533356181 ps
CPU time 13.74 seconds
Started Jun 28 05:31:22 PM PDT 24
Finished Jun 28 05:31:36 PM PDT 24
Peak memory 218984 kb
Host smart-ebbd4f96-7ae6-4bda-967b-a96e66e051b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496467559 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3496467559
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4148621471
Short name T397
Test name
Test status
Simulation time 5399304548 ps
CPU time 9.85 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:31:37 PM PDT 24
Peak memory 218880 kb
Host smart-4dea8b93-7283-4d34-addc-f7277a0c3942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148621471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4148621471
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2331974402
Short name T434
Test name
Test status
Simulation time 19145280421 ps
CPU time 60.01 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:32:26 PM PDT 24
Peak memory 210824 kb
Host smart-d4b46cd5-bf57-48d5-8f01-1575cc00db69
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331974402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2331974402
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1744863554
Short name T82
Test name
Test status
Simulation time 6382249613 ps
CPU time 13.81 seconds
Started Jun 28 05:31:24 PM PDT 24
Finished Jun 28 05:31:39 PM PDT 24
Peak memory 210832 kb
Host smart-fca4fd9c-2530-4f31-bd8a-8da119fb44b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744863554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1744863554
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3338927340
Short name T400
Test name
Test status
Simulation time 1901382291 ps
CPU time 17.62 seconds
Started Jun 28 05:31:22 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 219040 kb
Host smart-00e69f83-f20a-4f7c-99af-d6c691cc7dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338927340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3338927340
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1442696878
Short name T386
Test name
Test status
Simulation time 1423308568 ps
CPU time 69.68 seconds
Started Jun 28 05:31:26 PM PDT 24
Finished Jun 28 05:32:37 PM PDT 24
Peak memory 211936 kb
Host smart-f91a9a7e-cf6f-426e-81dd-e23351a16b15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442696878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1442696878
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.701888405
Short name T442
Test name
Test status
Simulation time 341458264 ps
CPU time 4.55 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:31:31 PM PDT 24
Peak memory 219000 kb
Host smart-f082f4b8-3307-400a-87dd-170c6e96a2db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701888405 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.701888405
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1201556740
Short name T90
Test name
Test status
Simulation time 10972666128 ps
CPU time 16.46 seconds
Started Jun 28 05:31:26 PM PDT 24
Finished Jun 28 05:31:44 PM PDT 24
Peak memory 210832 kb
Host smart-8f310213-49e6-4754-8e39-41d2cc55e342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201556740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1201556740
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2456887209
Short name T441
Test name
Test status
Simulation time 77557235476 ps
CPU time 94.55 seconds
Started Jun 28 05:31:25 PM PDT 24
Finished Jun 28 05:33:01 PM PDT 24
Peak memory 210840 kb
Host smart-4d1bce64-5dfc-44af-9efe-076c260de2bb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456887209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2456887209
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3001916235
Short name T108
Test name
Test status
Simulation time 4482494333 ps
CPU time 10.89 seconds
Started Jun 28 05:31:22 PM PDT 24
Finished Jun 28 05:31:34 PM PDT 24
Peak memory 219024 kb
Host smart-7faa14bd-d5ea-4d7f-a8da-0012ae001d89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001916235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3001916235
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4245191046
Short name T393
Test name
Test status
Simulation time 23992574440 ps
CPU time 16.49 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:31:40 PM PDT 24
Peak memory 219084 kb
Host smart-6c2c4ee2-28f4-4f98-a711-c501904ab0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245191046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4245191046
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4045448999
Short name T456
Test name
Test status
Simulation time 14457430712 ps
CPU time 42.76 seconds
Started Jun 28 05:31:23 PM PDT 24
Finished Jun 28 05:32:07 PM PDT 24
Peak memory 212260 kb
Host smart-168adf02-8d3a-4e9e-844f-14fb2b4a7419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045448999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4045448999
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1712214380
Short name T267
Test name
Test status
Simulation time 1960994607 ps
CPU time 15.39 seconds
Started Jun 28 04:48:58 PM PDT 24
Finished Jun 28 04:49:15 PM PDT 24
Peak memory 211268 kb
Host smart-15bf59d5-6020-4cec-84d9-f0a9378f9fbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712214380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1712214380
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1193071158
Short name T162
Test name
Test status
Simulation time 12968261253 ps
CPU time 122.58 seconds
Started Jun 28 04:49:13 PM PDT 24
Finished Jun 28 04:51:17 PM PDT 24
Peak memory 232752 kb
Host smart-d263cf51-ea90-4bc2-9712-f0bc71f897f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193071158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1193071158
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3904972193
Short name T346
Test name
Test status
Simulation time 11798400977 ps
CPU time 27.49 seconds
Started Jun 28 04:49:08 PM PDT 24
Finished Jun 28 04:49:38 PM PDT 24
Peak memory 212160 kb
Host smart-72810251-5bba-4cc7-a772-1b3a15b5a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904972193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3904972193
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.329205098
Short name T172
Test name
Test status
Simulation time 4291975352 ps
CPU time 17.12 seconds
Started Jun 28 04:48:47 PM PDT 24
Finished Jun 28 04:49:05 PM PDT 24
Peak memory 211304 kb
Host smart-a462fbdd-0454-44a2-881a-1254415ab917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329205098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.329205098
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4038708934
Short name T35
Test name
Test status
Simulation time 1549818727 ps
CPU time 51.75 seconds
Started Jun 28 04:49:00 PM PDT 24
Finished Jun 28 04:49:52 PM PDT 24
Peak memory 235652 kb
Host smart-300eada6-7ac1-4fd3-aaa4-486d782be0b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038708934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4038708934
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3362573744
Short name T196
Test name
Test status
Simulation time 992720912 ps
CPU time 17.8 seconds
Started Jun 28 04:48:52 PM PDT 24
Finished Jun 28 04:49:11 PM PDT 24
Peak memory 213464 kb
Host smart-71b46689-ece1-49e6-b2d7-e757eeaf111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362573744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3362573744
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3124858427
Short name T210
Test name
Test status
Simulation time 66105349304 ps
CPU time 52.45 seconds
Started Jun 28 04:48:55 PM PDT 24
Finished Jun 28 04:49:49 PM PDT 24
Peak memory 217164 kb
Host smart-b00c78a6-06f1-413c-8092-df70a6e884c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124858427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3124858427
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.232184310
Short name T311
Test name
Test status
Simulation time 3388567428 ps
CPU time 11.6 seconds
Started Jun 28 04:49:04 PM PDT 24
Finished Jun 28 04:49:17 PM PDT 24
Peak memory 211344 kb
Host smart-65eff85d-4f92-4861-939b-98cfc102830c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232184310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.232184310
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4027725006
Short name T4
Test name
Test status
Simulation time 1706307279 ps
CPU time 59.72 seconds
Started Jun 28 04:48:54 PM PDT 24
Finished Jun 28 04:49:54 PM PDT 24
Peak memory 237728 kb
Host smart-4872253a-f478-4b32-995e-e204979868b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027725006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4027725006
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4167193795
Short name T224
Test name
Test status
Simulation time 675146073 ps
CPU time 13.56 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:20 PM PDT 24
Peak memory 212108 kb
Host smart-3034425c-ba8c-43d6-bdbc-1f9f876407bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167193795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4167193795
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1103180997
Short name T183
Test name
Test status
Simulation time 1916999758 ps
CPU time 10.57 seconds
Started Jun 28 04:49:03 PM PDT 24
Finished Jun 28 04:49:14 PM PDT 24
Peak memory 211228 kb
Host smart-47517887-f1de-4cda-a655-e535544a7212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103180997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1103180997
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2245349589
Short name T29
Test name
Test status
Simulation time 1405181206 ps
CPU time 106.31 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:50:54 PM PDT 24
Peak memory 236860 kb
Host smart-2cb52187-1308-4769-9470-63d10f05aa48
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245349589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2245349589
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.654576753
Short name T230
Test name
Test status
Simulation time 3394550851 ps
CPU time 28.39 seconds
Started Jun 28 04:48:54 PM PDT 24
Finished Jun 28 04:49:24 PM PDT 24
Peak memory 213480 kb
Host smart-4fc268b0-9851-4abe-96fa-07869aaef1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654576753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.654576753
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3621197626
Short name T280
Test name
Test status
Simulation time 22405943074 ps
CPU time 68.92 seconds
Started Jun 28 04:48:56 PM PDT 24
Finished Jun 28 04:50:07 PM PDT 24
Peak memory 215552 kb
Host smart-dd352338-ff64-413b-9e7e-a6e309c78a28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621197626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3621197626
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2711307761
Short name T75
Test name
Test status
Simulation time 749321356 ps
CPU time 9.05 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:18 PM PDT 24
Peak memory 211268 kb
Host smart-a00abaab-45c2-4576-a09f-78835e6835b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711307761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2711307761
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1978744641
Short name T331
Test name
Test status
Simulation time 35189998877 ps
CPU time 186.47 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:52:15 PM PDT 24
Peak memory 237860 kb
Host smart-21a9e217-2edc-4fee-8af5-07407a8ae4c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978744641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1978744641
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.434968659
Short name T276
Test name
Test status
Simulation time 1865365799 ps
CPU time 15.56 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:25 PM PDT 24
Peak memory 211852 kb
Host smart-26eba154-ed90-4c04-b51a-a908ba4aabf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434968659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.434968659
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3259614335
Short name T211
Test name
Test status
Simulation time 272652242 ps
CPU time 7.51 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:15 PM PDT 24
Peak memory 211312 kb
Host smart-b27bb693-0813-4051-b403-9d482b57e286
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259614335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3259614335
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1634876239
Short name T161
Test name
Test status
Simulation time 610715879 ps
CPU time 14.32 seconds
Started Jun 28 04:49:08 PM PDT 24
Finished Jun 28 04:49:25 PM PDT 24
Peak memory 212748 kb
Host smart-76472915-a9d4-400a-a708-5f3ac9936498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634876239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1634876239
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4275800481
Short name T308
Test name
Test status
Simulation time 5460107022 ps
CPU time 63.01 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:50:13 PM PDT 24
Peak memory 216164 kb
Host smart-3bc59a97-9b14-4af5-8608-a5f2c8931e5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275800481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4275800481
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2389253512
Short name T181
Test name
Test status
Simulation time 4764914548 ps
CPU time 15.19 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:22 PM PDT 24
Peak memory 211300 kb
Host smart-260c57d8-e9db-4f7b-acb3-a46d89befd30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389253512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2389253512
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2050259055
Short name T305
Test name
Test status
Simulation time 6155480770 ps
CPU time 145.62 seconds
Started Jun 28 04:49:08 PM PDT 24
Finished Jun 28 04:51:36 PM PDT 24
Peak memory 237568 kb
Host smart-3e31ad63-71a4-4398-a438-cc4c4979f0ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050259055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2050259055
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.813960811
Short name T350
Test name
Test status
Simulation time 3937719363 ps
CPU time 31.42 seconds
Started Jun 28 04:49:03 PM PDT 24
Finished Jun 28 04:49:35 PM PDT 24
Peak memory 211892 kb
Host smart-716d97b9-a1b2-4762-b797-38c9d46f2228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813960811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.813960811
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1239926272
Short name T173
Test name
Test status
Simulation time 1441304668 ps
CPU time 14.12 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:21 PM PDT 24
Peak memory 211312 kb
Host smart-58c779b4-6079-488f-95bc-608c7b08276f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239926272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1239926272
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3539913971
Short name T353
Test name
Test status
Simulation time 2743474885 ps
CPU time 25.69 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:35 PM PDT 24
Peak memory 213472 kb
Host smart-c49160e9-a9cb-4d93-a8ac-99c4291b8933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539913971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3539913971
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.985148663
Short name T247
Test name
Test status
Simulation time 12753244266 ps
CPU time 27.34 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:37 PM PDT 24
Peak memory 214620 kb
Host smart-59af71f8-6e9e-4837-81a7-68ae63a3b206
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985148663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.985148663
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2982899921
Short name T287
Test name
Test status
Simulation time 1548672881 ps
CPU time 6.74 seconds
Started Jun 28 04:49:23 PM PDT 24
Finished Jun 28 04:49:31 PM PDT 24
Peak memory 211268 kb
Host smart-906920e3-ba2b-4be2-9dba-bc8c753ccb5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982899921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2982899921
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1979530902
Short name T227
Test name
Test status
Simulation time 1844673374 ps
CPU time 9.31 seconds
Started Jun 28 04:49:14 PM PDT 24
Finished Jun 28 04:49:24 PM PDT 24
Peak memory 211908 kb
Host smart-4614ebec-3bb2-49a6-af14-7477588eec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979530902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1979530902
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2435809124
Short name T13
Test name
Test status
Simulation time 5557708791 ps
CPU time 19.84 seconds
Started Jun 28 04:49:09 PM PDT 24
Finished Jun 28 04:49:31 PM PDT 24
Peak memory 214328 kb
Host smart-722d6c8d-bdda-403f-9e91-e80eb9b50477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435809124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2435809124
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2509072024
Short name T328
Test name
Test status
Simulation time 23399895150 ps
CPU time 59.09 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:50:06 PM PDT 24
Peak memory 219396 kb
Host smart-7f9d13d2-22de-44ce-a0a2-2f8d874c3a3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509072024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2509072024
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2260600588
Short name T154
Test name
Test status
Simulation time 305981425 ps
CPU time 5.32 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 04:49:18 PM PDT 24
Peak memory 211216 kb
Host smart-5e2681a3-0c6e-43cd-a7cb-0ade4c9da87c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260600588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2260600588
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1019979535
Short name T147
Test name
Test status
Simulation time 23429579811 ps
CPU time 131.41 seconds
Started Jun 28 04:49:18 PM PDT 24
Finished Jun 28 04:51:30 PM PDT 24
Peak memory 234476 kb
Host smart-9640b460-b1b2-460a-8d6b-60c3cb7bdd73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019979535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1019979535
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4176886428
Short name T216
Test name
Test status
Simulation time 4671586236 ps
CPU time 16.67 seconds
Started Jun 28 04:49:19 PM PDT 24
Finished Jun 28 04:49:37 PM PDT 24
Peak memory 212316 kb
Host smart-f92f3fa3-c17e-4b58-b554-cba9b74c9616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176886428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4176886428
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2171392370
Short name T201
Test name
Test status
Simulation time 6502777123 ps
CPU time 11.91 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 04:49:24 PM PDT 24
Peak memory 211592 kb
Host smart-58be9cc8-a4f3-4d05-b3f3-db8c1eee2ab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171392370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2171392370
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.4043163800
Short name T63
Test name
Test status
Simulation time 10373103970 ps
CPU time 29.47 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 214140 kb
Host smart-e4c71d51-7cda-45f3-b1d0-1e4ca024ff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043163800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.4043163800
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1022746637
Short name T301
Test name
Test status
Simulation time 11248210988 ps
CPU time 52.71 seconds
Started Jun 28 04:48:58 PM PDT 24
Finished Jun 28 04:49:52 PM PDT 24
Peak memory 214380 kb
Host smart-d358f822-75bb-4037-b610-be071600033c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022746637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1022746637
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.618402598
Short name T142
Test name
Test status
Simulation time 253532309 ps
CPU time 5.69 seconds
Started Jun 28 04:49:13 PM PDT 24
Finished Jun 28 04:49:20 PM PDT 24
Peak memory 211268 kb
Host smart-0fc9c9dd-28ae-49ce-a0bd-05c528ea365c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618402598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.618402598
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2310676871
Short name T189
Test name
Test status
Simulation time 9710289198 ps
CPU time 162.29 seconds
Started Jun 28 04:49:23 PM PDT 24
Finished Jun 28 04:52:07 PM PDT 24
Peak memory 234828 kb
Host smart-a820f2cb-a9e5-4a6c-ad12-6999d76ba79a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310676871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2310676871
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3224626010
Short name T199
Test name
Test status
Simulation time 1630453837 ps
CPU time 13.95 seconds
Started Jun 28 04:49:12 PM PDT 24
Finished Jun 28 04:49:27 PM PDT 24
Peak memory 211312 kb
Host smart-14f5ad98-b260-4867-aa34-1b6cf0ea843d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224626010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3224626010
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3935617114
Short name T84
Test name
Test status
Simulation time 3119138920 ps
CPU time 30.37 seconds
Started Jun 28 04:49:12 PM PDT 24
Finished Jun 28 04:49:44 PM PDT 24
Peak memory 213080 kb
Host smart-7c402b53-c773-42c3-b8b5-9f354093c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935617114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3935617114
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2684060946
Short name T259
Test name
Test status
Simulation time 3800625935 ps
CPU time 50.79 seconds
Started Jun 28 04:49:09 PM PDT 24
Finished Jun 28 04:50:02 PM PDT 24
Peak memory 216156 kb
Host smart-2d945895-167b-4301-8a5f-5e1cc71ea21b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684060946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2684060946
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1938612960
Short name T192
Test name
Test status
Simulation time 1279767116 ps
CPU time 12.15 seconds
Started Jun 28 04:49:12 PM PDT 24
Finished Jun 28 04:49:26 PM PDT 24
Peak memory 211188 kb
Host smart-b0dcee99-75e2-4dc3-b528-11a6f742f8e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938612960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1938612960
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.98430644
Short name T339
Test name
Test status
Simulation time 52119174144 ps
CPU time 266.09 seconds
Started Jun 28 04:49:18 PM PDT 24
Finished Jun 28 04:53:45 PM PDT 24
Peak memory 225628 kb
Host smart-380533ea-b8a4-4d7c-b28a-8ceab72f467c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98430644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_co
rrupt_sig_fatal_chk.98430644
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2955252799
Short name T187
Test name
Test status
Simulation time 1765060146 ps
CPU time 8.15 seconds
Started Jun 28 04:49:22 PM PDT 24
Finished Jun 28 04:49:32 PM PDT 24
Peak memory 211312 kb
Host smart-aaabe22a-194d-4910-ace7-46a40d5b4d40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955252799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2955252799
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1103431625
Short name T234
Test name
Test status
Simulation time 1355726089 ps
CPU time 11.64 seconds
Started Jun 28 04:49:21 PM PDT 24
Finished Jun 28 04:49:33 PM PDT 24
Peak memory 213416 kb
Host smart-90c33975-827e-4003-a385-88b620876ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103431625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1103431625
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3516920892
Short name T362
Test name
Test status
Simulation time 24632285624 ps
CPU time 56.73 seconds
Started Jun 28 04:49:10 PM PDT 24
Finished Jun 28 04:50:09 PM PDT 24
Peak memory 215016 kb
Host smart-72e85fdc-6646-4a8d-9b38-9d1c6d226294
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516920892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3516920892
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1619230489
Short name T177
Test name
Test status
Simulation time 3836569166 ps
CPU time 8.25 seconds
Started Jun 28 04:49:18 PM PDT 24
Finished Jun 28 04:49:27 PM PDT 24
Peak memory 211328 kb
Host smart-371a4a47-476c-405f-9b8c-7deb015b54cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619230489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1619230489
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1878135862
Short name T45
Test name
Test status
Simulation time 28895577542 ps
CPU time 112.53 seconds
Started Jun 28 04:49:13 PM PDT 24
Finished Jun 28 04:51:07 PM PDT 24
Peak memory 232820 kb
Host smart-2ebb6017-d1bc-4781-bd2c-238bb1d8b87a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878135862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1878135862
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.301922612
Short name T283
Test name
Test status
Simulation time 8187712222 ps
CPU time 22.34 seconds
Started Jun 28 04:49:10 PM PDT 24
Finished Jun 28 04:49:34 PM PDT 24
Peak memory 211656 kb
Host smart-cdeed3c1-1719-41e4-847e-926acd15a9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301922612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.301922612
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1671627291
Short name T341
Test name
Test status
Simulation time 4644327565 ps
CPU time 17.11 seconds
Started Jun 28 04:49:10 PM PDT 24
Finished Jun 28 04:49:29 PM PDT 24
Peak memory 211296 kb
Host smart-da692f96-fb17-497a-9d0a-dd3dd146ae9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671627291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1671627291
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2736861546
Short name T236
Test name
Test status
Simulation time 10234797206 ps
CPU time 24.55 seconds
Started Jun 28 04:49:22 PM PDT 24
Finished Jun 28 04:49:49 PM PDT 24
Peak memory 213400 kb
Host smart-27977745-f6b0-4536-ab3d-5ff849a1ae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736861546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2736861546
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.598381226
Short name T255
Test name
Test status
Simulation time 1232700866 ps
CPU time 22.63 seconds
Started Jun 28 04:49:13 PM PDT 24
Finished Jun 28 04:49:37 PM PDT 24
Peak memory 213984 kb
Host smart-fefd2b53-e762-429e-9b0d-1a702bcf8a7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598381226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.598381226
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3433852634
Short name T1
Test name
Test status
Simulation time 128985567 ps
CPU time 5.04 seconds
Started Jun 28 04:49:19 PM PDT 24
Finished Jun 28 04:49:25 PM PDT 24
Peak memory 211268 kb
Host smart-46b9a7e8-8b64-4201-94ba-2ee8e44e1457
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433852634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3433852634
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3777059021
Short name T51
Test name
Test status
Simulation time 17013660705 ps
CPU time 252.79 seconds
Started Jun 28 04:49:23 PM PDT 24
Finished Jun 28 04:53:37 PM PDT 24
Peak memory 237716 kb
Host smart-ff69efca-407e-49d2-b26e-2401d74b1f5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777059021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3777059021
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3014431237
Short name T212
Test name
Test status
Simulation time 25487396218 ps
CPU time 23.13 seconds
Started Jun 28 04:49:16 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 211312 kb
Host smart-11151f3f-d555-4682-9d01-82abbcaa65b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014431237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3014431237
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2292533801
Short name T300
Test name
Test status
Simulation time 475793468 ps
CPU time 8.92 seconds
Started Jun 28 04:49:13 PM PDT 24
Finished Jun 28 04:49:23 PM PDT 24
Peak memory 211388 kb
Host smart-6815b9c9-0f4e-4b59-ab3f-d0cef971003c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2292533801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2292533801
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1343021846
Short name T312
Test name
Test status
Simulation time 3952360594 ps
CPU time 30.98 seconds
Started Jun 28 04:49:10 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 213196 kb
Host smart-9ef83e86-45d7-45f4-a85e-f155197a116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343021846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1343021846
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2506382169
Short name T166
Test name
Test status
Simulation time 20148509122 ps
CPU time 90.13 seconds
Started Jun 28 04:49:21 PM PDT 24
Finished Jun 28 04:50:52 PM PDT 24
Peak memory 219472 kb
Host smart-f2067707-6c33-4f4f-b845-c6fa369df454
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506382169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2506382169
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3160756146
Short name T338
Test name
Test status
Simulation time 3301304290 ps
CPU time 9.55 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 04:49:22 PM PDT 24
Peak memory 211288 kb
Host smart-ed5f29d3-091d-449e-a17a-609a586352a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160756146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3160756146
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.864024495
Short name T141
Test name
Test status
Simulation time 4290743116 ps
CPU time 142.47 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 04:51:35 PM PDT 24
Peak memory 238148 kb
Host smart-93b7b4c6-7002-415d-bf93-b1290ee182ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864024495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.864024495
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2695806246
Short name T17
Test name
Test status
Simulation time 657344467 ps
CPU time 14.01 seconds
Started Jun 28 04:49:12 PM PDT 24
Finished Jun 28 04:49:27 PM PDT 24
Peak memory 212136 kb
Host smart-396c5e31-c84e-4857-b1ea-c20893bb6ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695806246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2695806246
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1715539915
Short name T114
Test name
Test status
Simulation time 5664429281 ps
CPU time 13.25 seconds
Started Jun 28 04:49:19 PM PDT 24
Finished Jun 28 04:49:34 PM PDT 24
Peak memory 211320 kb
Host smart-d8de5aba-617e-4cac-86f9-986e8d916a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715539915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1715539915
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.396357159
Short name T197
Test name
Test status
Simulation time 14529817367 ps
CPU time 34.2 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:49:42 PM PDT 24
Peak memory 214304 kb
Host smart-c9f9afc0-626a-420d-89bb-d77d1fa11ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396357159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.396357159
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1220134541
Short name T218
Test name
Test status
Simulation time 410307671 ps
CPU time 12.72 seconds
Started Jun 28 04:49:13 PM PDT 24
Finished Jun 28 04:49:27 PM PDT 24
Peak memory 213696 kb
Host smart-ccebaea3-39b7-4e06-95ff-6e0ec93611cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220134541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1220134541
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.249703270
Short name T221
Test name
Test status
Simulation time 6932881798 ps
CPU time 13.86 seconds
Started Jun 28 04:49:19 PM PDT 24
Finished Jun 28 04:49:33 PM PDT 24
Peak memory 211328 kb
Host smart-677c8783-5b81-4074-9da9-1115358baf53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249703270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.249703270
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.455412630
Short name T136
Test name
Test status
Simulation time 96299457908 ps
CPU time 260.89 seconds
Started Jun 28 04:49:27 PM PDT 24
Finished Jun 28 04:53:49 PM PDT 24
Peak memory 233768 kb
Host smart-c2e26646-9990-4532-91f5-61b5af22a6c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455412630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.455412630
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2168977862
Short name T326
Test name
Test status
Simulation time 17292466864 ps
CPU time 33.96 seconds
Started Jun 28 04:49:10 PM PDT 24
Finished Jun 28 04:49:51 PM PDT 24
Peak memory 212404 kb
Host smart-cf1650ce-9449-4b15-a22f-7bcc364b59d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168977862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2168977862
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4225464637
Short name T6
Test name
Test status
Simulation time 2117228753 ps
CPU time 17.04 seconds
Started Jun 28 04:49:13 PM PDT 24
Finished Jun 28 04:49:31 PM PDT 24
Peak memory 211312 kb
Host smart-8a72ae16-0481-439f-bf8c-ee26b34adb26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225464637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4225464637
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2764322192
Short name T285
Test name
Test status
Simulation time 6975896032 ps
CPU time 20.59 seconds
Started Jun 28 04:49:19 PM PDT 24
Finished Jun 28 04:49:41 PM PDT 24
Peak memory 213528 kb
Host smart-c838f6fc-85dc-4417-9a23-613eebecdd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764322192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2764322192
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.204770690
Short name T355
Test name
Test status
Simulation time 288985306 ps
CPU time 7.36 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:17 PM PDT 24
Peak memory 211252 kb
Host smart-1b9cf82d-562d-4d94-b479-99a171dc1525
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204770690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.204770690
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3104400191
Short name T21
Test name
Test status
Simulation time 96861264630 ps
CPU time 899.73 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 05:04:12 PM PDT 24
Peak memory 235724 kb
Host smart-29a6e4bb-f3bf-4c92-bad1-8466b13bb712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104400191 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3104400191
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4120270653
Short name T12
Test name
Test status
Simulation time 1749212873 ps
CPU time 14.99 seconds
Started Jun 28 04:49:00 PM PDT 24
Finished Jun 28 04:49:16 PM PDT 24
Peak memory 211268 kb
Host smart-fd78feab-11cc-40db-b93d-e107fe684b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120270653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4120270653
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3085301913
Short name T281
Test name
Test status
Simulation time 305297826607 ps
CPU time 313.94 seconds
Started Jun 28 04:49:04 PM PDT 24
Finished Jun 28 04:54:19 PM PDT 24
Peak memory 224636 kb
Host smart-caeca55b-5710-41bc-aaef-aeace7751d08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085301913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3085301913
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.942648731
Short name T198
Test name
Test status
Simulation time 2338403458 ps
CPU time 22.91 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:33 PM PDT 24
Peak memory 211940 kb
Host smart-19b41f09-10a6-4b68-81b1-96b47008b52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942648731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.942648731
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.333564746
Short name T137
Test name
Test status
Simulation time 10495517198 ps
CPU time 15.69 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:26 PM PDT 24
Peak memory 211288 kb
Host smart-42f2b012-489e-41fe-b0d9-3d6aceb4663c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333564746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.333564746
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3049349616
Short name T178
Test name
Test status
Simulation time 7559392198 ps
CPU time 21.73 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:28 PM PDT 24
Peak memory 213028 kb
Host smart-c542be79-3def-47c0-8412-f0c15002f583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049349616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3049349616
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3848712527
Short name T11
Test name
Test status
Simulation time 25786315357 ps
CPU time 55.55 seconds
Started Jun 28 04:49:10 PM PDT 24
Finished Jun 28 04:50:08 PM PDT 24
Peak memory 216864 kb
Host smart-d0078dc2-e9e5-4af4-a1ba-a88cca7064e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848712527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3848712527
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.250242744
Short name T146
Test name
Test status
Simulation time 1077426091 ps
CPU time 10.89 seconds
Started Jun 28 04:49:19 PM PDT 24
Finished Jun 28 04:49:31 PM PDT 24
Peak memory 211148 kb
Host smart-568d1484-57af-40a2-becf-a123b1c4046d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250242744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.250242744
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3723088118
Short name T295
Test name
Test status
Simulation time 67627562653 ps
CPU time 320.18 seconds
Started Jun 28 04:49:23 PM PDT 24
Finished Jun 28 04:54:45 PM PDT 24
Peak memory 228472 kb
Host smart-bc48cfd4-f4dc-46bb-ad09-d83208b48ad2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723088118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3723088118
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.25893360
Short name T194
Test name
Test status
Simulation time 1119305676 ps
CPU time 16.51 seconds
Started Jun 28 04:49:12 PM PDT 24
Finished Jun 28 04:49:34 PM PDT 24
Peak memory 212136 kb
Host smart-d4ff8e14-2121-4aae-93a4-640ff7ddf6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25893360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.25893360
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2300878167
Short name T175
Test name
Test status
Simulation time 1203363720 ps
CPU time 12.16 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 04:49:25 PM PDT 24
Peak memory 211276 kb
Host smart-e3e9924a-4208-4c8c-b8e9-2f7605ae4f25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2300878167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2300878167
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3704971063
Short name T86
Test name
Test status
Simulation time 369081363 ps
CPU time 10.2 seconds
Started Jun 28 04:49:08 PM PDT 24
Finished Jun 28 04:49:20 PM PDT 24
Peak memory 213916 kb
Host smart-68e9e0b3-d286-4e29-860e-c803595616df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704971063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3704971063
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.156740319
Short name T100
Test name
Test status
Simulation time 883031196 ps
CPU time 29.7 seconds
Started Jun 28 04:49:25 PM PDT 24
Finished Jun 28 04:49:56 PM PDT 24
Peak memory 213968 kb
Host smart-4932ee5c-f616-4e2a-a6c8-6b81cf7e8b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156740319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.156740319
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3437745094
Short name T357
Test name
Test status
Simulation time 788143306 ps
CPU time 8.78 seconds
Started Jun 28 04:49:31 PM PDT 24
Finished Jun 28 04:49:40 PM PDT 24
Peak memory 211268 kb
Host smart-4a1c28ee-de93-4fbe-ad0a-78128a8eec01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437745094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3437745094
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2036681623
Short name T242
Test name
Test status
Simulation time 18031603413 ps
CPU time 160.09 seconds
Started Jun 28 04:49:12 PM PDT 24
Finished Jun 28 04:51:54 PM PDT 24
Peak memory 225692 kb
Host smart-d88051b3-90bb-488a-bf74-ebc4c6717241
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036681623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2036681623
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1006918652
Short name T38
Test name
Test status
Simulation time 506338520 ps
CPU time 13.02 seconds
Started Jun 28 04:49:27 PM PDT 24
Finished Jun 28 04:49:41 PM PDT 24
Peak memory 211948 kb
Host smart-370bbde4-04f9-499e-b21b-5aa8e819928b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006918652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1006918652
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2744870572
Short name T351
Test name
Test status
Simulation time 568193217 ps
CPU time 5.41 seconds
Started Jun 28 04:49:19 PM PDT 24
Finished Jun 28 04:49:25 PM PDT 24
Peak memory 211312 kb
Host smart-26c5f105-17dd-48a9-bcdf-22399e95af14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744870572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2744870572
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3575953646
Short name T246
Test name
Test status
Simulation time 1536162155 ps
CPU time 21.97 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:49:29 PM PDT 24
Peak memory 213112 kb
Host smart-ce961e91-74e1-40ff-aa4b-fed638b10ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575953646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3575953646
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1173518618
Short name T127
Test name
Test status
Simulation time 4359950647 ps
CPU time 41.23 seconds
Started Jun 28 04:49:08 PM PDT 24
Finished Jun 28 04:49:52 PM PDT 24
Peak memory 216772 kb
Host smart-a385c1cc-bb40-406e-a770-2c70f6e70945
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173518618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1173518618
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2455984760
Short name T64
Test name
Test status
Simulation time 10861562904 ps
CPU time 13.95 seconds
Started Jun 28 04:49:10 PM PDT 24
Finished Jun 28 04:49:26 PM PDT 24
Peak memory 210240 kb
Host smart-c4278943-f0df-4f25-9542-5213f68a657d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455984760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2455984760
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2627111375
Short name T360
Test name
Test status
Simulation time 4939941410 ps
CPU time 77.02 seconds
Started Jun 28 04:49:18 PM PDT 24
Finished Jun 28 04:50:35 PM PDT 24
Peak memory 233768 kb
Host smart-90ea1273-4dae-4645-abee-9a633ee98b64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627111375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2627111375
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.993682063
Short name T364
Test name
Test status
Simulation time 13760328792 ps
CPU time 27.11 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 04:49:40 PM PDT 24
Peak memory 212308 kb
Host smart-2a3490f9-1bb8-4075-b669-2329baf81f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993682063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.993682063
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3146871275
Short name T316
Test name
Test status
Simulation time 11308332546 ps
CPU time 24.99 seconds
Started Jun 28 04:49:12 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 213952 kb
Host smart-7339411e-befe-4799-942e-55a69be19ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146871275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3146871275
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3555704414
Short name T40
Test name
Test status
Simulation time 3930206878 ps
CPU time 53.02 seconds
Started Jun 28 04:49:19 PM PDT 24
Finished Jun 28 04:50:13 PM PDT 24
Peak memory 216412 kb
Host smart-fe69f51d-7e9e-4b33-aa08-961b731c0f86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555704414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3555704414
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3629003563
Short name T344
Test name
Test status
Simulation time 39047633393 ps
CPU time 1648.4 seconds
Started Jun 28 04:49:17 PM PDT 24
Finished Jun 28 05:16:46 PM PDT 24
Peak memory 236676 kb
Host smart-bef27944-5255-404e-b662-fed20a6483fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629003563 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3629003563
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3478071123
Short name T232
Test name
Test status
Simulation time 1044010574 ps
CPU time 10.41 seconds
Started Jun 28 04:49:17 PM PDT 24
Finished Jun 28 04:49:28 PM PDT 24
Peak memory 211184 kb
Host smart-00b3f4ae-f098-4860-b39a-0640ea95c12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478071123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3478071123
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1398634152
Short name T44
Test name
Test status
Simulation time 364135473858 ps
CPU time 295.02 seconds
Started Jun 28 04:49:16 PM PDT 24
Finished Jun 28 04:54:12 PM PDT 24
Peak memory 212624 kb
Host smart-a0ebf297-71c5-4f6c-beb0-5fd27fd15084
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398634152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1398634152
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1542807735
Short name T159
Test name
Test status
Simulation time 2736201523 ps
CPU time 25.67 seconds
Started Jun 28 04:49:25 PM PDT 24
Finished Jun 28 04:49:53 PM PDT 24
Peak memory 211372 kb
Host smart-93198405-0043-4500-b0e7-175ecba1bbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542807735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1542807735
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3283715659
Short name T238
Test name
Test status
Simulation time 1120462648 ps
CPU time 11.42 seconds
Started Jun 28 04:49:17 PM PDT 24
Finished Jun 28 04:49:29 PM PDT 24
Peak memory 211228 kb
Host smart-14514f70-9dd2-4f1c-87b9-a4f881be662d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3283715659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3283715659
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3271936287
Short name T258
Test name
Test status
Simulation time 360456919 ps
CPU time 12.25 seconds
Started Jun 28 04:49:29 PM PDT 24
Finished Jun 28 04:49:42 PM PDT 24
Peak memory 213540 kb
Host smart-dfb4075b-c70c-461d-934c-793160dd62bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271936287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3271936287
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.504075605
Short name T254
Test name
Test status
Simulation time 3994299393 ps
CPU time 46.69 seconds
Started Jun 28 04:49:16 PM PDT 24
Finished Jun 28 04:50:04 PM PDT 24
Peak memory 216872 kb
Host smart-c835513e-567f-4d10-9de8-94517fa664fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504075605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.504075605
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1482618880
Short name T55
Test name
Test status
Simulation time 42069325886 ps
CPU time 1584.34 seconds
Started Jun 28 04:49:27 PM PDT 24
Finished Jun 28 05:15:52 PM PDT 24
Peak memory 232468 kb
Host smart-2ee32373-7db8-459f-9ca2-28fdf128eebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482618880 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1482618880
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1036995203
Short name T219
Test name
Test status
Simulation time 7503938466 ps
CPU time 14.43 seconds
Started Jun 28 04:49:20 PM PDT 24
Finished Jun 28 04:49:35 PM PDT 24
Peak memory 211328 kb
Host smart-27f91ec5-e8bc-4015-9ba5-5b2589f76981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036995203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1036995203
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.277957774
Short name T174
Test name
Test status
Simulation time 7926515318 ps
CPU time 118.61 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 04:51:11 PM PDT 24
Peak memory 226528 kb
Host smart-ae6802f6-5e67-4d62-93b1-ef033429373e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277957774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.277957774
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3848063455
Short name T205
Test name
Test status
Simulation time 2073793878 ps
CPU time 10.79 seconds
Started Jun 28 04:49:28 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 211904 kb
Host smart-dbee5100-8136-44ad-bdd8-54a1ffab2311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848063455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3848063455
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1949096261
Short name T168
Test name
Test status
Simulation time 3142928650 ps
CPU time 12.6 seconds
Started Jun 28 04:49:20 PM PDT 24
Finished Jun 28 04:49:33 PM PDT 24
Peak memory 211344 kb
Host smart-2626ad77-b1d7-4266-a0be-01b23b3e88e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1949096261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1949096261
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3053633091
Short name T215
Test name
Test status
Simulation time 9660533617 ps
CPU time 25.27 seconds
Started Jun 28 04:49:17 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 213656 kb
Host smart-053899bb-6ef2-42a8-87ac-90dc6981091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053633091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3053633091
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2498532904
Short name T203
Test name
Test status
Simulation time 8894833983 ps
CPU time 29.41 seconds
Started Jun 28 04:49:18 PM PDT 24
Finished Jun 28 04:49:48 PM PDT 24
Peak memory 214496 kb
Host smart-1f714e20-191a-42eb-805f-ce897ed37c5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498532904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2498532904
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2987818898
Short name T49
Test name
Test status
Simulation time 170351985 ps
CPU time 9.6 seconds
Started Jun 28 04:49:16 PM PDT 24
Finished Jun 28 04:49:27 PM PDT 24
Peak memory 211840 kb
Host smart-a0f8b630-97c1-46db-8dbb-48450c595e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987818898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2987818898
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3367379975
Short name T206
Test name
Test status
Simulation time 7430747689 ps
CPU time 16.03 seconds
Started Jun 28 04:49:23 PM PDT 24
Finished Jun 28 04:49:40 PM PDT 24
Peak memory 211344 kb
Host smart-968aa470-e1e6-4570-b678-036b2a21a613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367379975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3367379975
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3560425459
Short name T268
Test name
Test status
Simulation time 3724610731 ps
CPU time 21.5 seconds
Started Jun 28 04:49:28 PM PDT 24
Finished Jun 28 04:49:50 PM PDT 24
Peak memory 213688 kb
Host smart-3fe3988e-87e8-451b-8b5d-5964e39f8097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560425459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3560425459
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.724572019
Short name T24
Test name
Test status
Simulation time 669369806 ps
CPU time 15.62 seconds
Started Jun 28 04:49:26 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 215032 kb
Host smart-0a4a7b82-fa6d-4719-9f64-3e2e79a2e52c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724572019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.724572019
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3152247162
Short name T5
Test name
Test status
Simulation time 2912719825 ps
CPU time 12.13 seconds
Started Jun 28 04:49:31 PM PDT 24
Finished Jun 28 04:49:44 PM PDT 24
Peak memory 211256 kb
Host smart-2ca67e80-6c2c-4e95-9b17-2b3774487726
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152247162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3152247162
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2124835519
Short name T253
Test name
Test status
Simulation time 1282994273 ps
CPU time 85.26 seconds
Started Jun 28 04:49:28 PM PDT 24
Finished Jun 28 04:50:54 PM PDT 24
Peak memory 236788 kb
Host smart-43d22fab-0301-48ba-8929-a73a7b23a694
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124835519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2124835519
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2277618328
Short name T317
Test name
Test status
Simulation time 8907322356 ps
CPU time 23.13 seconds
Started Jun 28 04:49:27 PM PDT 24
Finished Jun 28 04:49:51 PM PDT 24
Peak memory 212260 kb
Host smart-1fe88adf-e5ff-43bd-98c1-80c3492a4d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277618328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2277618328
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3281501787
Short name T170
Test name
Test status
Simulation time 1265691302 ps
CPU time 12.45 seconds
Started Jun 28 04:49:25 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 211236 kb
Host smart-3cc3e951-6bb9-4d26-a450-2d98ddf5db55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281501787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3281501787
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3484539228
Short name T145
Test name
Test status
Simulation time 363401094 ps
CPU time 10.03 seconds
Started Jun 28 04:49:23 PM PDT 24
Finished Jun 28 04:49:34 PM PDT 24
Peak memory 212760 kb
Host smart-2e9b24ff-b51e-498c-b3a3-2606cd27b8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484539228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3484539228
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1134224986
Short name T128
Test name
Test status
Simulation time 2655876758 ps
CPU time 47.3 seconds
Started Jun 28 04:49:27 PM PDT 24
Finished Jun 28 04:50:15 PM PDT 24
Peak memory 218696 kb
Host smart-e81dda33-a163-4858-93bd-7b648c39c2b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134224986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1134224986
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1694676546
Short name T185
Test name
Test status
Simulation time 1816537885 ps
CPU time 15.54 seconds
Started Jun 28 04:49:26 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 211184 kb
Host smart-465db84d-aeff-43a0-961f-e6547b8da2f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694676546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1694676546
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2873069013
Short name T250
Test name
Test status
Simulation time 76664988133 ps
CPU time 187.2 seconds
Started Jun 28 04:49:25 PM PDT 24
Finished Jun 28 04:52:34 PM PDT 24
Peak memory 228592 kb
Host smart-8d92e9ef-fc67-4f2c-b856-667490eda58a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873069013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2873069013
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.525887489
Short name T356
Test name
Test status
Simulation time 3362645058 ps
CPU time 30.48 seconds
Started Jun 28 04:49:33 PM PDT 24
Finished Jun 28 04:50:05 PM PDT 24
Peak memory 211396 kb
Host smart-472ae870-2cab-4157-a239-445aab8b094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525887489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.525887489
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1216234342
Short name T284
Test name
Test status
Simulation time 4137251723 ps
CPU time 11.39 seconds
Started Jun 28 04:49:28 PM PDT 24
Finished Jun 28 04:49:40 PM PDT 24
Peak memory 211372 kb
Host smart-a68486cf-4846-4fb5-8905-1b2b2e5cee49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216234342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1216234342
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.229502532
Short name T164
Test name
Test status
Simulation time 10142907899 ps
CPU time 17.35 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:49:55 PM PDT 24
Peak memory 213764 kb
Host smart-37c858c4-a01d-4e96-8e24-613e966f3115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229502532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.229502532
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.256694971
Short name T270
Test name
Test status
Simulation time 7134534730 ps
CPU time 20.4 seconds
Started Jun 28 04:49:30 PM PDT 24
Finished Jun 28 04:49:51 PM PDT 24
Peak memory 211520 kb
Host smart-86f4fede-4cd9-4783-a15e-7d67273607d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256694971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.256694971
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.940103197
Short name T290
Test name
Test status
Simulation time 416696983 ps
CPU time 4.33 seconds
Started Jun 28 04:49:30 PM PDT 24
Finished Jun 28 04:49:35 PM PDT 24
Peak memory 211184 kb
Host smart-764f3a7b-8932-48d3-98f6-4c76e9454b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940103197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.940103197
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2887634247
Short name T315
Test name
Test status
Simulation time 20851248584 ps
CPU time 191.76 seconds
Started Jun 28 04:49:30 PM PDT 24
Finished Jun 28 04:52:42 PM PDT 24
Peak memory 235964 kb
Host smart-e5f6bf2e-317a-4874-85af-b0a23af60bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887634247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2887634247
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1602063823
Short name T193
Test name
Test status
Simulation time 170332969 ps
CPU time 9.6 seconds
Started Jun 28 04:49:19 PM PDT 24
Finished Jun 28 04:49:29 PM PDT 24
Peak memory 211312 kb
Host smart-0dc75361-bb05-431f-8548-167b1b486d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602063823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1602063823
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.651019532
Short name T26
Test name
Test status
Simulation time 794251480 ps
CPU time 9.73 seconds
Started Jun 28 04:49:28 PM PDT 24
Finished Jun 28 04:49:38 PM PDT 24
Peak memory 211312 kb
Host smart-931cbc1c-ac39-4411-856a-7bb927e53122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651019532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.651019532
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.4047438670
Short name T228
Test name
Test status
Simulation time 11802394168 ps
CPU time 28.16 seconds
Started Jun 28 04:49:15 PM PDT 24
Finished Jun 28 04:49:44 PM PDT 24
Peak memory 213940 kb
Host smart-551a32d6-19f5-4352-a8eb-d0de94ecc4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047438670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.4047438670
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.629558925
Short name T139
Test name
Test status
Simulation time 870977091 ps
CPU time 15.57 seconds
Started Jun 28 04:49:30 PM PDT 24
Finished Jun 28 04:49:46 PM PDT 24
Peak memory 214016 kb
Host smart-fc116a95-9a15-463d-8be6-79c6c47066c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629558925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.629558925
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2540634508
Short name T53
Test name
Test status
Simulation time 25339902280 ps
CPU time 1479.62 seconds
Started Jun 28 04:49:18 PM PDT 24
Finished Jun 28 05:13:58 PM PDT 24
Peak memory 228716 kb
Host smart-5f37436e-b2b5-4d0e-b7ab-88b8667b2443
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540634508 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2540634508
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3290152871
Short name T18
Test name
Test status
Simulation time 5337477487 ps
CPU time 11.27 seconds
Started Jun 28 04:49:32 PM PDT 24
Finished Jun 28 04:49:44 PM PDT 24
Peak memory 211328 kb
Host smart-f8bc4331-f1e5-47a0-b3af-4abff370f198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290152871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3290152871
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2716914134
Short name T169
Test name
Test status
Simulation time 2438617275 ps
CPU time 113.92 seconds
Started Jun 28 04:49:33 PM PDT 24
Finished Jun 28 04:51:28 PM PDT 24
Peak memory 228064 kb
Host smart-a67b892b-9572-47b8-bcc7-70365f2c963e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716914134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2716914134
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3825447650
Short name T263
Test name
Test status
Simulation time 15018384724 ps
CPU time 32.31 seconds
Started Jun 28 04:49:27 PM PDT 24
Finished Jun 28 04:50:00 PM PDT 24
Peak memory 211372 kb
Host smart-6e7e0b46-013b-4315-9660-71c23fd40904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825447650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3825447650
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.946238901
Short name T237
Test name
Test status
Simulation time 445219644 ps
CPU time 7.97 seconds
Started Jun 28 04:49:27 PM PDT 24
Finished Jun 28 04:49:36 PM PDT 24
Peak memory 210728 kb
Host smart-6a256dd5-b0f6-4162-8924-3facb0a92129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946238901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.946238901
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2498704783
Short name T113
Test name
Test status
Simulation time 1825937325 ps
CPU time 20.72 seconds
Started Jun 28 04:49:29 PM PDT 24
Finished Jun 28 04:49:51 PM PDT 24
Peak memory 212116 kb
Host smart-bbb50d59-7887-4605-be63-83eaff960d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498704783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2498704783
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2632621272
Short name T143
Test name
Test status
Simulation time 2934399515 ps
CPU time 9.15 seconds
Started Jun 28 04:48:57 PM PDT 24
Finished Jun 28 04:49:08 PM PDT 24
Peak memory 211328 kb
Host smart-c352ea03-44be-4952-97be-f44d403ba0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632621272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2632621272
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.977725170
Short name T298
Test name
Test status
Simulation time 11330788580 ps
CPU time 22.23 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:29 PM PDT 24
Peak memory 212224 kb
Host smart-7a22315e-5c1b-48d0-a5f0-5f098dbcba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977725170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.977725170
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3099393714
Short name T343
Test name
Test status
Simulation time 10475788641 ps
CPU time 12.9 seconds
Started Jun 28 04:49:01 PM PDT 24
Finished Jun 28 04:49:15 PM PDT 24
Peak memory 211256 kb
Host smart-53402638-e2fc-4332-8790-99c9c1658371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099393714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3099393714
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3631516603
Short name T30
Test name
Test status
Simulation time 22587377973 ps
CPU time 108.02 seconds
Started Jun 28 04:49:08 PM PDT 24
Finished Jun 28 04:50:58 PM PDT 24
Peak memory 236296 kb
Host smart-e01c1bbc-eef6-4211-b9c7-89a145972617
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631516603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3631516603
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3590610259
Short name T333
Test name
Test status
Simulation time 8785961201 ps
CPU time 36.48 seconds
Started Jun 28 04:49:00 PM PDT 24
Finished Jun 28 04:49:38 PM PDT 24
Peak memory 213696 kb
Host smart-39bbd3be-407d-4343-b718-cc20d45df0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590610259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3590610259
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.699813890
Short name T23
Test name
Test status
Simulation time 62961193360 ps
CPU time 68.17 seconds
Started Jun 28 04:49:04 PM PDT 24
Finished Jun 28 04:50:13 PM PDT 24
Peak memory 217176 kb
Host smart-5a239d26-3705-4896-aa0c-1d17251ada66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699813890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.699813890
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2320166982
Short name T335
Test name
Test status
Simulation time 1277937176 ps
CPU time 6.93 seconds
Started Jun 28 04:49:31 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 211272 kb
Host smart-a1ff01d3-f60c-4f47-90b1-09c57eb4ddc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320166982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2320166982
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1568156427
Short name T349
Test name
Test status
Simulation time 67693162129 ps
CPU time 179.47 seconds
Started Jun 28 04:49:52 PM PDT 24
Finished Jun 28 04:52:53 PM PDT 24
Peak memory 228212 kb
Host smart-49196dca-859a-4ab4-86ca-075bd112d19f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568156427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1568156427
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2762616477
Short name T50
Test name
Test status
Simulation time 831116555 ps
CPU time 9.17 seconds
Started Jun 28 04:49:32 PM PDT 24
Finished Jun 28 04:49:42 PM PDT 24
Peak memory 211812 kb
Host smart-1274c153-a890-461d-8883-ed857250e2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762616477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2762616477
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.289574073
Short name T313
Test name
Test status
Simulation time 100478808 ps
CPU time 5.57 seconds
Started Jun 28 04:49:24 PM PDT 24
Finished Jun 28 04:49:32 PM PDT 24
Peak memory 211236 kb
Host smart-e7372da1-d168-4f4e-94d3-5a731a611983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289574073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.289574073
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.113347634
Short name T257
Test name
Test status
Simulation time 2095528897 ps
CPU time 15.05 seconds
Started Jun 28 04:49:22 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 212152 kb
Host smart-e0e4aea9-968e-48f8-bb96-c70535060db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113347634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.113347634
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2894962904
Short name T314
Test name
Test status
Simulation time 8807565595 ps
CPU time 21.58 seconds
Started Jun 28 04:49:18 PM PDT 24
Finished Jun 28 04:49:40 PM PDT 24
Peak memory 219320 kb
Host smart-c1927ef0-5aec-4669-b395-4af6f8f3af0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894962904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2894962904
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.251596390
Short name T324
Test name
Test status
Simulation time 1286467959 ps
CPU time 11.79 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:49:50 PM PDT 24
Peak memory 211184 kb
Host smart-a2ecb1cc-6e96-4823-a17e-e5ee5384da40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251596390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.251596390
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2205924824
Short name T27
Test name
Test status
Simulation time 2777879854 ps
CPU time 157.92 seconds
Started Jun 28 04:49:37 PM PDT 24
Finished Jun 28 04:52:17 PM PDT 24
Peak memory 213252 kb
Host smart-9ef80e3b-a71e-439c-80ba-d4895a80f81f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205924824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2205924824
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2253181585
Short name T245
Test name
Test status
Simulation time 3480069618 ps
CPU time 29.87 seconds
Started Jun 28 04:49:44 PM PDT 24
Finished Jun 28 04:50:16 PM PDT 24
Peak memory 211988 kb
Host smart-37497550-ccb2-4b6b-9177-8733c1cb6b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253181585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2253181585
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3765327414
Short name T130
Test name
Test status
Simulation time 4536113650 ps
CPU time 14.28 seconds
Started Jun 28 04:49:53 PM PDT 24
Finished Jun 28 04:50:09 PM PDT 24
Peak memory 211304 kb
Host smart-0db66f1d-9c57-4488-a09a-b501eb770388
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765327414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3765327414
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2646751914
Short name T321
Test name
Test status
Simulation time 3102459010 ps
CPU time 31.11 seconds
Started Jun 28 04:49:37 PM PDT 24
Finished Jun 28 04:50:10 PM PDT 24
Peak memory 212936 kb
Host smart-f37d9d2c-89b9-4501-93f9-4145d205c0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646751914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2646751914
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3154740177
Short name T302
Test name
Test status
Simulation time 5795954021 ps
CPU time 30.74 seconds
Started Jun 28 04:49:34 PM PDT 24
Finished Jun 28 04:50:06 PM PDT 24
Peak memory 215592 kb
Host smart-60a017e3-309b-47a2-873d-b46a1cf47d9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154740177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3154740177
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.411334221
Short name T342
Test name
Test status
Simulation time 5292575600 ps
CPU time 12.28 seconds
Started Jun 28 04:49:34 PM PDT 24
Finished Jun 28 04:49:48 PM PDT 24
Peak memory 211324 kb
Host smart-b000cbe6-c98c-4e3d-9558-885636543661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411334221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.411334221
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1513604067
Short name T208
Test name
Test status
Simulation time 3005797196 ps
CPU time 105.11 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:51:23 PM PDT 24
Peak memory 237840 kb
Host smart-a17d062c-df6d-4cf9-a818-fbda0bed45d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513604067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1513604067
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1578340203
Short name T330
Test name
Test status
Simulation time 4181376780 ps
CPU time 17.7 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:49:56 PM PDT 24
Peak memory 211304 kb
Host smart-f6d129a2-d6bb-497b-8336-7a810ae7d9f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578340203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1578340203
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.947810175
Short name T299
Test name
Test status
Simulation time 8897024174 ps
CPU time 22.94 seconds
Started Jun 28 04:49:52 PM PDT 24
Finished Jun 28 04:50:16 PM PDT 24
Peak memory 214060 kb
Host smart-35dd4f6e-de4d-47a6-83c7-ba3c31b628f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947810175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.947810175
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2605850518
Short name T307
Test name
Test status
Simulation time 25125590792 ps
CPU time 53.13 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:50:32 PM PDT 24
Peak memory 214180 kb
Host smart-a100f198-1be0-4409-a1a5-15123a16f9b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605850518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2605850518
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3331424676
Short name T20
Test name
Test status
Simulation time 62329398767 ps
CPU time 8322.35 seconds
Started Jun 28 04:49:32 PM PDT 24
Finished Jun 28 07:08:16 PM PDT 24
Peak memory 235772 kb
Host smart-069cb41e-2226-44ab-afdf-7aa074a7d43b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331424676 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3331424676
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2730907221
Short name T310
Test name
Test status
Simulation time 1139463750 ps
CPU time 11.11 seconds
Started Jun 28 04:49:39 PM PDT 24
Finished Jun 28 04:49:51 PM PDT 24
Peak memory 211268 kb
Host smart-461787d0-5b7e-44c6-90d4-1b5cabb0011f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730907221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2730907221
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.853328326
Short name T336
Test name
Test status
Simulation time 11544483049 ps
CPU time 196.8 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:52:55 PM PDT 24
Peak memory 213568 kb
Host smart-b0d91a4f-b132-48e1-b94c-dbc483819a69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853328326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.853328326
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.746677297
Short name T2
Test name
Test status
Simulation time 2288972418 ps
CPU time 23.55 seconds
Started Jun 28 04:49:42 PM PDT 24
Finished Jun 28 04:50:09 PM PDT 24
Peak memory 212056 kb
Host smart-a2603ad4-d5e9-4476-8565-83e779150b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746677297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.746677297
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.750836145
Short name T251
Test name
Test status
Simulation time 1495151667 ps
CPU time 7.68 seconds
Started Jun 28 04:49:31 PM PDT 24
Finished Jun 28 04:49:40 PM PDT 24
Peak memory 211276 kb
Host smart-f2ecf7b4-b8cb-43cd-893a-8979dda42497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750836145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.750836145
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1275818778
Short name T327
Test name
Test status
Simulation time 3861089713 ps
CPU time 33.1 seconds
Started Jun 28 04:49:42 PM PDT 24
Finished Jun 28 04:50:19 PM PDT 24
Peak memory 213212 kb
Host smart-9e4a0d4e-fb63-4254-a527-997e9b9e5ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275818778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1275818778
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2704220486
Short name T156
Test name
Test status
Simulation time 6980172622 ps
CPU time 31.94 seconds
Started Jun 28 04:49:37 PM PDT 24
Finished Jun 28 04:50:11 PM PDT 24
Peak memory 217340 kb
Host smart-4a350df3-5bc6-499c-b08a-9851074e8680
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704220486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2704220486
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2617432502
Short name T153
Test name
Test status
Simulation time 985161360 ps
CPU time 10.55 seconds
Started Jun 28 04:49:58 PM PDT 24
Finished Jun 28 04:50:10 PM PDT 24
Peak memory 211244 kb
Host smart-144b1958-add8-4975-9726-094bdfef63c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617432502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2617432502
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4108359682
Short name T25
Test name
Test status
Simulation time 2215643624 ps
CPU time 141.35 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:51:59 PM PDT 24
Peak memory 237728 kb
Host smart-66390dd1-8566-4969-8af4-c6a6c7e994e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108359682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4108359682
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2030756428
Short name T39
Test name
Test status
Simulation time 3589668897 ps
CPU time 23.26 seconds
Started Jun 28 04:49:38 PM PDT 24
Finished Jun 28 04:50:03 PM PDT 24
Peak memory 211920 kb
Host smart-605bc74f-e4ee-4ab0-bfcb-e5a4ca7b3a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030756428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2030756428
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2231864694
Short name T10
Test name
Test status
Simulation time 2072181087 ps
CPU time 8.91 seconds
Started Jun 28 04:49:34 PM PDT 24
Finished Jun 28 04:49:44 PM PDT 24
Peak memory 211312 kb
Host smart-c9f7eff7-b882-4e7b-901a-619d7d8ce8a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231864694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2231864694
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3467755487
Short name T165
Test name
Test status
Simulation time 4321580453 ps
CPU time 34.06 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:50:12 PM PDT 24
Peak memory 212136 kb
Host smart-189c91fa-05bf-45c1-9e03-c390c4f848c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467755487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3467755487
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.705421930
Short name T155
Test name
Test status
Simulation time 2953898534 ps
CPU time 30.8 seconds
Started Jun 28 04:49:40 PM PDT 24
Finished Jun 28 04:50:12 PM PDT 24
Peak memory 213348 kb
Host smart-b4350343-53f3-4cb1-8ead-83859c981851
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705421930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.705421930
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1503079092
Short name T241
Test name
Test status
Simulation time 10731431247 ps
CPU time 8.18 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:49:46 PM PDT 24
Peak memory 211328 kb
Host smart-e1183378-16c6-4369-a3c9-6e1c9ae06087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503079092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1503079092
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1854647755
Short name T190
Test name
Test status
Simulation time 40610119707 ps
CPU time 379.81 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:55:58 PM PDT 24
Peak memory 237828 kb
Host smart-d403888e-8eec-494d-96e1-c6065b3a169c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854647755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1854647755
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3225187156
Short name T34
Test name
Test status
Simulation time 5105509259 ps
CPU time 24.95 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:50:01 PM PDT 24
Peak memory 212120 kb
Host smart-645bd87c-c0c4-41f4-9bc9-ddcc5f5d318d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225187156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3225187156
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.608368128
Short name T286
Test name
Test status
Simulation time 99195091 ps
CPU time 5.59 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:49:44 PM PDT 24
Peak memory 211244 kb
Host smart-1751351b-c37d-4c11-9b1f-a9bade0871f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=608368128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.608368128
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1856679519
Short name T22
Test name
Test status
Simulation time 696928269 ps
CPU time 10.45 seconds
Started Jun 28 04:49:37 PM PDT 24
Finished Jun 28 04:49:50 PM PDT 24
Peak memory 213596 kb
Host smart-3e0536f9-2c9b-4eb3-b86a-4790ade62621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856679519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1856679519
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1535572102
Short name T223
Test name
Test status
Simulation time 42724129546 ps
CPU time 98.72 seconds
Started Jun 28 04:49:33 PM PDT 24
Finished Jun 28 04:51:13 PM PDT 24
Peak memory 216764 kb
Host smart-429c4134-3a34-434e-837e-d0be5f43a7c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535572102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1535572102
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2144893401
Short name T213
Test name
Test status
Simulation time 1160241528 ps
CPU time 9.03 seconds
Started Jun 28 04:49:33 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 211196 kb
Host smart-ebc51b50-5978-466a-a404-c580d32d09bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144893401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2144893401
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3808779462
Short name T151
Test name
Test status
Simulation time 2945832173 ps
CPU time 101.62 seconds
Started Jun 28 04:49:38 PM PDT 24
Finished Jun 28 04:51:22 PM PDT 24
Peak memory 236456 kb
Host smart-5f14ae6b-4779-4fae-ad80-d4de47fd2b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808779462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3808779462
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2710136939
Short name T260
Test name
Test status
Simulation time 4343186411 ps
CPU time 33.94 seconds
Started Jun 28 04:49:33 PM PDT 24
Finished Jun 28 04:50:08 PM PDT 24
Peak memory 212164 kb
Host smart-6b976fe4-fb9d-4cf4-b28d-dd6bbc806fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710136939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2710136939
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3146426891
Short name T233
Test name
Test status
Simulation time 1399165292 ps
CPU time 11.89 seconds
Started Jun 28 04:49:50 PM PDT 24
Finished Jun 28 04:50:03 PM PDT 24
Peak memory 211328 kb
Host smart-0aabd3b7-3e8c-4e5b-aabc-ed030a9145a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146426891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3146426891
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1142756376
Short name T303
Test name
Test status
Simulation time 815390354 ps
CPU time 9.97 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:49:47 PM PDT 24
Peak memory 213812 kb
Host smart-23e9d12a-5b87-4542-9dd4-a56bbf4b4e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142756376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1142756376
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3943065375
Short name T244
Test name
Test status
Simulation time 34460404290 ps
CPU time 69.12 seconds
Started Jun 28 04:49:39 PM PDT 24
Finished Jun 28 04:50:50 PM PDT 24
Peak memory 217408 kb
Host smart-78e0804a-e46d-4e71-8441-181c3dcbb4c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943065375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3943065375
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1042773192
Short name T66
Test name
Test status
Simulation time 4835508861 ps
CPU time 14.93 seconds
Started Jun 28 04:49:37 PM PDT 24
Finished Jun 28 04:49:54 PM PDT 24
Peak memory 211328 kb
Host smart-f3fe48a1-6a95-4cb1-8108-7bc0eb7f5448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042773192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1042773192
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2734630650
Short name T249
Test name
Test status
Simulation time 1305349298 ps
CPU time 77.38 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:50:54 PM PDT 24
Peak memory 212404 kb
Host smart-f9d6956d-0a05-4bc0-9ba3-b2a862179cac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734630650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2734630650
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.850093862
Short name T235
Test name
Test status
Simulation time 20095084090 ps
CPU time 30.1 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:50:07 PM PDT 24
Peak memory 212480 kb
Host smart-4a480d19-c17a-41c6-a8a5-634f30380a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850093862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.850093862
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4218218214
Short name T309
Test name
Test status
Simulation time 390893666 ps
CPU time 5.57 seconds
Started Jun 28 04:49:37 PM PDT 24
Finished Jun 28 04:49:45 PM PDT 24
Peak memory 211316 kb
Host smart-3e9f6508-b303-49df-9702-fb16a2a2c9ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4218218214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4218218214
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3831432850
Short name T345
Test name
Test status
Simulation time 2833249023 ps
CPU time 25.02 seconds
Started Jun 28 04:49:39 PM PDT 24
Finished Jun 28 04:50:06 PM PDT 24
Peak memory 213504 kb
Host smart-df3cb1c8-18d9-40b6-9ca6-470543ba67cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831432850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3831432850
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4092286183
Short name T42
Test name
Test status
Simulation time 2420835528 ps
CPU time 34.41 seconds
Started Jun 28 04:49:39 PM PDT 24
Finished Jun 28 04:50:15 PM PDT 24
Peak memory 215900 kb
Host smart-d3992fb3-6ccd-45c4-9230-fb90c4ab84a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092286183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4092286183
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1586400587
Short name T54
Test name
Test status
Simulation time 33471060188 ps
CPU time 1250.41 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 05:10:28 PM PDT 24
Peak memory 235808 kb
Host smart-62863d46-9479-44cf-a304-afc530183666
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586400587 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1586400587
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.802733898
Short name T32
Test name
Test status
Simulation time 556544148 ps
CPU time 7.5 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:49:52 PM PDT 24
Peak memory 211384 kb
Host smart-3f8f8c20-49a0-490f-8fc6-80e1b8441766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802733898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.802733898
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.280036538
Short name T325
Test name
Test status
Simulation time 79562034900 ps
CPU time 425.27 seconds
Started Jun 28 04:49:37 PM PDT 24
Finished Jun 28 04:56:45 PM PDT 24
Peak memory 237808 kb
Host smart-18a54fb1-c6bd-4c2b-87ae-9debf3249d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280036538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.280036538
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1123769681
Short name T214
Test name
Test status
Simulation time 3730506526 ps
CPU time 28.31 seconds
Started Jun 28 04:49:38 PM PDT 24
Finished Jun 28 04:50:08 PM PDT 24
Peak memory 212240 kb
Host smart-c73ef129-b948-4ff9-a8e2-4886fd8cee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123769681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1123769681
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2012451133
Short name T98
Test name
Test status
Simulation time 101474469 ps
CPU time 5.72 seconds
Started Jun 28 04:49:36 PM PDT 24
Finished Jun 28 04:49:44 PM PDT 24
Peak memory 211312 kb
Host smart-c875fbca-dab2-464d-8e43-0f71d92eaa9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012451133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2012451133
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3033876175
Short name T291
Test name
Test status
Simulation time 4649713891 ps
CPU time 30.41 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:50:07 PM PDT 24
Peak memory 213604 kb
Host smart-b63d3df9-3f22-4072-9355-1aa670121dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033876175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3033876175
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3002020995
Short name T273
Test name
Test status
Simulation time 15185623919 ps
CPU time 65.55 seconds
Started Jun 28 04:49:37 PM PDT 24
Finished Jun 28 04:50:44 PM PDT 24
Peak memory 219396 kb
Host smart-94861ead-b0af-477d-ace3-c210cb1e1a30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002020995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3002020995
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3736861754
Short name T74
Test name
Test status
Simulation time 4392515389 ps
CPU time 17.24 seconds
Started Jun 28 04:49:35 PM PDT 24
Finished Jun 28 04:49:54 PM PDT 24
Peak memory 211256 kb
Host smart-c65fb276-2b71-472a-97b2-adf16d49822f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736861754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3736861754
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2853492162
Short name T163
Test name
Test status
Simulation time 74431398789 ps
CPU time 191.41 seconds
Started Jun 28 04:49:39 PM PDT 24
Finished Jun 28 04:52:52 PM PDT 24
Peak memory 224908 kb
Host smart-c6d1c061-9f39-4c5f-831c-2d813fef14c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853492162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2853492162
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.256088875
Short name T322
Test name
Test status
Simulation time 693786581 ps
CPU time 9.4 seconds
Started Jun 28 04:49:46 PM PDT 24
Finished Jun 28 04:49:56 PM PDT 24
Peak memory 211784 kb
Host smart-f71bd62b-59d6-4e66-86f0-24fedad1782a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256088875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.256088875
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4205937567
Short name T188
Test name
Test status
Simulation time 2266823183 ps
CPU time 11.79 seconds
Started Jun 28 04:49:38 PM PDT 24
Finished Jun 28 04:49:52 PM PDT 24
Peak memory 211296 kb
Host smart-f34c2717-14d2-45b2-941c-c5b956f31e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205937567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4205937567
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3907575634
Short name T304
Test name
Test status
Simulation time 18172349464 ps
CPU time 32.85 seconds
Started Jun 28 04:49:41 PM PDT 24
Finished Jun 28 04:50:16 PM PDT 24
Peak memory 213832 kb
Host smart-02330617-eee9-4d9b-b61d-4d2554e77f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907575634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3907575634
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2683776527
Short name T271
Test name
Test status
Simulation time 5270738836 ps
CPU time 24.12 seconds
Started Jun 28 04:49:46 PM PDT 24
Finished Jun 28 04:50:11 PM PDT 24
Peak memory 213668 kb
Host smart-76937fac-95ec-4735-aae1-debdf3e5d43b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683776527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2683776527
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2627083048
Short name T288
Test name
Test status
Simulation time 1886057095 ps
CPU time 7.26 seconds
Started Jun 28 04:49:09 PM PDT 24
Finished Jun 28 04:49:19 PM PDT 24
Peak memory 211268 kb
Host smart-c13f2b94-dc56-4ea2-8bc8-c1792c45bc6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627083048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2627083048
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1008324799
Short name T46
Test name
Test status
Simulation time 5716471324 ps
CPU time 113.89 seconds
Started Jun 28 04:49:03 PM PDT 24
Finished Jun 28 04:50:57 PM PDT 24
Peak memory 233688 kb
Host smart-805b8680-d879-4edd-98e7-d2e8d87c4ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008324799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1008324799
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3727004211
Short name T209
Test name
Test status
Simulation time 1077048526 ps
CPU time 17.03 seconds
Started Jun 28 04:49:08 PM PDT 24
Finished Jun 28 04:49:27 PM PDT 24
Peak memory 211956 kb
Host smart-c1dd2aba-9dff-4538-a2c9-dce3f3d1f6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727004211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3727004211
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1374963065
Short name T3
Test name
Test status
Simulation time 383940780 ps
CPU time 5.62 seconds
Started Jun 28 04:49:01 PM PDT 24
Finished Jun 28 04:49:08 PM PDT 24
Peak memory 211244 kb
Host smart-d4a37803-f3bb-4614-a2d0-5ea840764dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374963065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1374963065
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2321862003
Short name T31
Test name
Test status
Simulation time 431251008 ps
CPU time 101.42 seconds
Started Jun 28 04:49:01 PM PDT 24
Finished Jun 28 04:50:43 PM PDT 24
Peak memory 237252 kb
Host smart-622da32c-587d-4a00-8b35-4180f1b8aadf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321862003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2321862003
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2167298899
Short name T134
Test name
Test status
Simulation time 4039949670 ps
CPU time 28.3 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:35 PM PDT 24
Peak memory 214032 kb
Host smart-e9997491-0618-4974-afdf-ca379fdf802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167298899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2167298899
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.321320143
Short name T248
Test name
Test status
Simulation time 1552515117 ps
CPU time 21.25 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:28 PM PDT 24
Peak memory 213564 kb
Host smart-623f634a-d0e3-4ea5-be8e-b3d35d8a0498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321320143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.321320143
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3298432012
Short name T334
Test name
Test status
Simulation time 4201286780 ps
CPU time 16.66 seconds
Started Jun 28 04:49:50 PM PDT 24
Finished Jun 28 04:50:09 PM PDT 24
Peak memory 211300 kb
Host smart-78d4dbf2-f51a-429c-acb1-5067c501072d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298432012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3298432012
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1565796542
Short name T318
Test name
Test status
Simulation time 1634337222 ps
CPU time 62.84 seconds
Started Jun 28 04:49:47 PM PDT 24
Finished Jun 28 04:50:51 PM PDT 24
Peak memory 237800 kb
Host smart-abeb0385-d23f-4044-aef9-54dfbc783e34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565796542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1565796542
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1607105921
Short name T61
Test name
Test status
Simulation time 69942429884 ps
CPU time 31.83 seconds
Started Jun 28 04:49:54 PM PDT 24
Finished Jun 28 04:50:28 PM PDT 24
Peak memory 212284 kb
Host smart-5124d938-0e71-4366-a3c9-8f9fc9bff264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607105921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1607105921
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1519111888
Short name T149
Test name
Test status
Simulation time 468744922 ps
CPU time 8.8 seconds
Started Jun 28 04:49:56 PM PDT 24
Finished Jun 28 04:50:06 PM PDT 24
Peak memory 211312 kb
Host smart-4d4aad14-ce27-4ca7-9b4f-798e71a23191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519111888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1519111888
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3586652850
Short name T289
Test name
Test status
Simulation time 9114475116 ps
CPU time 44.66 seconds
Started Jun 28 04:49:46 PM PDT 24
Finished Jun 28 04:50:32 PM PDT 24
Peak memory 213456 kb
Host smart-9153b93b-a089-4f32-922b-f1e3ebbb20ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586652850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3586652850
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2467978360
Short name T140
Test name
Test status
Simulation time 28563938039 ps
CPU time 56.68 seconds
Started Jun 28 04:49:39 PM PDT 24
Finished Jun 28 04:50:37 PM PDT 24
Peak memory 213820 kb
Host smart-1243988e-4f27-4800-876c-025e30e667de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467978360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2467978360
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.685915276
Short name T138
Test name
Test status
Simulation time 3520652350 ps
CPU time 14.58 seconds
Started Jun 28 04:49:55 PM PDT 24
Finished Jun 28 04:50:12 PM PDT 24
Peak memory 211328 kb
Host smart-7179f8a0-cb48-46ec-8d96-417ca65968fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685915276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.685915276
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2546441809
Short name T278
Test name
Test status
Simulation time 4938082093 ps
CPU time 88.15 seconds
Started Jun 28 04:49:46 PM PDT 24
Finished Jun 28 04:51:15 PM PDT 24
Peak memory 234792 kb
Host smart-f86735c1-b94e-4512-a60a-b458e8a0062c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546441809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2546441809
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.888923136
Short name T243
Test name
Test status
Simulation time 3446004632 ps
CPU time 30.8 seconds
Started Jun 28 04:49:50 PM PDT 24
Finished Jun 28 04:50:23 PM PDT 24
Peak memory 211888 kb
Host smart-159e74fa-c969-490b-9240-f304aa0d06d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888923136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.888923136
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3544997399
Short name T217
Test name
Test status
Simulation time 1119234516 ps
CPU time 11.43 seconds
Started Jun 28 04:49:52 PM PDT 24
Finished Jun 28 04:50:05 PM PDT 24
Peak memory 211312 kb
Host smart-4777fa85-0c28-4f28-9db4-69e2038e71e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3544997399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3544997399
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3970447579
Short name T62
Test name
Test status
Simulation time 3357370341 ps
CPU time 13.32 seconds
Started Jun 28 04:49:58 PM PDT 24
Finished Jun 28 04:50:13 PM PDT 24
Peak memory 213640 kb
Host smart-7775243d-de06-464a-895b-ee8e44a07c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970447579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3970447579
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3962875182
Short name T282
Test name
Test status
Simulation time 13780138586 ps
CPU time 35.96 seconds
Started Jun 28 04:49:43 PM PDT 24
Finished Jun 28 04:50:22 PM PDT 24
Peak memory 215588 kb
Host smart-de436552-3346-4eea-aa73-a91903805bb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962875182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3962875182
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.742621003
Short name T58
Test name
Test status
Simulation time 170711693473 ps
CPU time 2304.8 seconds
Started Jun 28 04:50:00 PM PDT 24
Finished Jun 28 05:28:27 PM PDT 24
Peak memory 235764 kb
Host smart-1ca698ee-a731-4dba-970a-3c13e185f7a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742621003 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.742621003
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1017776736
Short name T7
Test name
Test status
Simulation time 90066247 ps
CPU time 4.1 seconds
Started Jun 28 04:49:48 PM PDT 24
Finished Jun 28 04:49:52 PM PDT 24
Peak memory 211244 kb
Host smart-1c8d3eb4-9fe8-4940-a38a-f47bf7475d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017776736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1017776736
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2577929969
Short name T179
Test name
Test status
Simulation time 37720338184 ps
CPU time 203.74 seconds
Started Jun 28 04:49:58 PM PDT 24
Finished Jun 28 04:53:24 PM PDT 24
Peak memory 228028 kb
Host smart-f57c9641-1e24-4b9a-9e17-5c18c736df2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577929969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2577929969
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3405092692
Short name T101
Test name
Test status
Simulation time 11766179942 ps
CPU time 27.15 seconds
Started Jun 28 04:49:49 PM PDT 24
Finished Jun 28 04:50:17 PM PDT 24
Peak memory 212236 kb
Host smart-f5943686-e97b-4f7d-995a-e41343a0d248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405092692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3405092692
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1576540001
Short name T157
Test name
Test status
Simulation time 99367462 ps
CPU time 5.68 seconds
Started Jun 28 04:49:51 PM PDT 24
Finished Jun 28 04:49:59 PM PDT 24
Peak memory 211312 kb
Host smart-b7dffb4d-5dcf-4192-947b-cad30ed71c29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1576540001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1576540001
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3314162245
Short name T85
Test name
Test status
Simulation time 1099968307 ps
CPU time 16.85 seconds
Started Jun 28 04:49:51 PM PDT 24
Finished Jun 28 04:50:09 PM PDT 24
Peak memory 212412 kb
Host smart-ef495090-5b17-42d2-a64b-a430bc3b32c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314162245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3314162245
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1381705261
Short name T275
Test name
Test status
Simulation time 1581199976 ps
CPU time 24.02 seconds
Started Jun 28 04:49:43 PM PDT 24
Finished Jun 28 04:50:10 PM PDT 24
Peak memory 216840 kb
Host smart-b171f83d-e386-4830-b05d-e778d2faae91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381705261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1381705261
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1507503388
Short name T220
Test name
Test status
Simulation time 2713118760 ps
CPU time 9.1 seconds
Started Jun 28 04:50:00 PM PDT 24
Finished Jun 28 04:50:11 PM PDT 24
Peak memory 211260 kb
Host smart-64f5e0b2-6bf0-45a1-84ad-e4a0af523f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507503388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1507503388
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1500838380
Short name T226
Test name
Test status
Simulation time 94891501528 ps
CPU time 291.73 seconds
Started Jun 28 04:49:43 PM PDT 24
Finished Jun 28 04:54:37 PM PDT 24
Peak memory 237836 kb
Host smart-ff9389da-f4af-4478-b3e0-622c911782e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500838380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1500838380
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3731825673
Short name T340
Test name
Test status
Simulation time 168250789 ps
CPU time 9.85 seconds
Started Jun 28 04:49:43 PM PDT 24
Finished Jun 28 04:49:56 PM PDT 24
Peak memory 211780 kb
Host smart-f98ba34e-a51b-4d50-8e1e-d64539e2ab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731825673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3731825673
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2473211872
Short name T348
Test name
Test status
Simulation time 2824020326 ps
CPU time 12.23 seconds
Started Jun 28 04:49:53 PM PDT 24
Finished Jun 28 04:50:07 PM PDT 24
Peak memory 211308 kb
Host smart-102c3a8f-b588-44c8-b81b-9ebc71664999
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473211872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2473211872
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.590471571
Short name T60
Test name
Test status
Simulation time 14135473022 ps
CPU time 33.21 seconds
Started Jun 28 04:49:47 PM PDT 24
Finished Jun 28 04:50:21 PM PDT 24
Peak memory 213964 kb
Host smart-2f9b862a-d2ca-4350-bf77-8a9ceda441b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590471571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.590471571
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4288820471
Short name T133
Test name
Test status
Simulation time 2234345258 ps
CPU time 30.51 seconds
Started Jun 28 04:49:47 PM PDT 24
Finished Jun 28 04:50:18 PM PDT 24
Peak memory 217084 kb
Host smart-1b32f939-1f1f-44c8-9c7c-5c6120ccaca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288820471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4288820471
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2510308998
Short name T57
Test name
Test status
Simulation time 59482930964 ps
CPU time 3663.79 seconds
Started Jun 28 04:49:42 PM PDT 24
Finished Jun 28 05:50:49 PM PDT 24
Peak memory 235724 kb
Host smart-93e60d9b-c7cd-4967-bda5-0f4596858e12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510308998 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2510308998
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2320456402
Short name T47
Test name
Test status
Simulation time 1707732224 ps
CPU time 14.45 seconds
Started Jun 28 04:49:54 PM PDT 24
Finished Jun 28 04:50:10 PM PDT 24
Peak memory 211268 kb
Host smart-50c34f6b-bf0c-4025-af83-e71ce3fc0721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320456402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2320456402
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4266867017
Short name T186
Test name
Test status
Simulation time 2209507060 ps
CPU time 105.13 seconds
Started Jun 28 04:49:42 PM PDT 24
Finished Jun 28 04:51:30 PM PDT 24
Peak memory 234884 kb
Host smart-ddfbefbc-5c97-433f-b0eb-7fa192465357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266867017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.4266867017
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3704899442
Short name T294
Test name
Test status
Simulation time 8832519088 ps
CPU time 34.61 seconds
Started Jun 28 04:49:42 PM PDT 24
Finished Jun 28 04:50:19 PM PDT 24
Peak memory 212080 kb
Host smart-1e131d48-02f9-48e4-a9af-0a0739fab05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704899442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3704899442
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2623038727
Short name T9
Test name
Test status
Simulation time 7537071346 ps
CPU time 7.91 seconds
Started Jun 28 04:49:51 PM PDT 24
Finished Jun 28 04:50:00 PM PDT 24
Peak memory 211288 kb
Host smart-2842af8e-a094-4775-b4b7-aa9660d746a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623038727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2623038727
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.812039307
Short name T358
Test name
Test status
Simulation time 5767109154 ps
CPU time 64.81 seconds
Started Jun 28 04:49:45 PM PDT 24
Finished Jun 28 04:50:51 PM PDT 24
Peak memory 219400 kb
Host smart-af1c314e-44a3-4986-9239-3f5ef9792dba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812039307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.812039307
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3860987260
Short name T274
Test name
Test status
Simulation time 2079402650 ps
CPU time 16.9 seconds
Started Jun 28 04:49:43 PM PDT 24
Finished Jun 28 04:50:03 PM PDT 24
Peak memory 211192 kb
Host smart-0f347b3f-91eb-4b6c-8128-40a9947df863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860987260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3860987260
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1760913150
Short name T204
Test name
Test status
Simulation time 36427967643 ps
CPU time 163.1 seconds
Started Jun 28 04:49:53 PM PDT 24
Finished Jun 28 04:52:38 PM PDT 24
Peak memory 212680 kb
Host smart-354a819d-d2a7-4676-8452-b529db44e114
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760913150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1760913150
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2283385620
Short name T150
Test name
Test status
Simulation time 4679031269 ps
CPU time 24.41 seconds
Started Jun 28 04:49:42 PM PDT 24
Finished Jun 28 04:50:10 PM PDT 24
Peak memory 212340 kb
Host smart-542be9dc-4170-4436-95c8-3b0463b84e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283385620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2283385620
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3017591675
Short name T180
Test name
Test status
Simulation time 15319642477 ps
CPU time 16.9 seconds
Started Jun 28 04:49:54 PM PDT 24
Finished Jun 28 04:50:13 PM PDT 24
Peak memory 211372 kb
Host smart-b1534b0a-92f6-4947-82f3-ddd7d2170153
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017591675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3017591675
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3942739950
Short name T363
Test name
Test status
Simulation time 6868979219 ps
CPU time 30.77 seconds
Started Jun 28 04:49:42 PM PDT 24
Finished Jun 28 04:50:16 PM PDT 24
Peak memory 214404 kb
Host smart-4567007d-656a-42d5-b0b0-7511bb5ba6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942739950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3942739950
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.510020517
Short name T207
Test name
Test status
Simulation time 3313246479 ps
CPU time 31.48 seconds
Started Jun 28 04:49:49 PM PDT 24
Finished Jun 28 04:50:22 PM PDT 24
Peak memory 212732 kb
Host smart-efa47199-5826-48d8-b0a3-9e3aceab75cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510020517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.510020517
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1976253580
Short name T262
Test name
Test status
Simulation time 9734035364 ps
CPU time 9.34 seconds
Started Jun 28 04:49:47 PM PDT 24
Finished Jun 28 04:49:57 PM PDT 24
Peak memory 211256 kb
Host smart-b8cff960-7c6f-4d83-8c75-317771ddc155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976253580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1976253580
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1841087154
Short name T41
Test name
Test status
Simulation time 60697449394 ps
CPU time 222.22 seconds
Started Jun 28 04:49:55 PM PDT 24
Finished Jun 28 04:53:39 PM PDT 24
Peak memory 237828 kb
Host smart-d0736764-4e37-4afd-bc14-260e8f2aac41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841087154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1841087154
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3257891831
Short name T337
Test name
Test status
Simulation time 2013641836 ps
CPU time 16.94 seconds
Started Jun 28 04:49:58 PM PDT 24
Finished Jun 28 04:50:17 PM PDT 24
Peak memory 211984 kb
Host smart-be386d37-9a20-4c86-9514-081e35cbafdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257891831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3257891831
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2770498851
Short name T293
Test name
Test status
Simulation time 1603814478 ps
CPU time 14.15 seconds
Started Jun 28 04:49:44 PM PDT 24
Finished Jun 28 04:50:00 PM PDT 24
Peak memory 211316 kb
Host smart-af1ad20d-b175-4e83-8bbf-db732c7b2ff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770498851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2770498851
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.917922198
Short name T297
Test name
Test status
Simulation time 24034790038 ps
CPU time 32.11 seconds
Started Jun 28 04:49:48 PM PDT 24
Finished Jun 28 04:50:22 PM PDT 24
Peak memory 214188 kb
Host smart-85a2a715-c28e-4a40-aec7-d1ce04784c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917922198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.917922198
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.261521825
Short name T202
Test name
Test status
Simulation time 291415727 ps
CPU time 11.79 seconds
Started Jun 28 04:49:49 PM PDT 24
Finished Jun 28 04:50:03 PM PDT 24
Peak memory 213908 kb
Host smart-88479b2f-4e4d-4df6-bec7-03433fd4f50b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261521825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.261521825
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1759805403
Short name T115
Test name
Test status
Simulation time 178182039347 ps
CPU time 1369.77 seconds
Started Jun 28 04:49:46 PM PDT 24
Finished Jun 28 05:12:37 PM PDT 24
Peak memory 235900 kb
Host smart-e2a47467-6975-4748-af1d-870e774b7be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759805403 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1759805403
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.947238687
Short name T167
Test name
Test status
Simulation time 2790068427 ps
CPU time 12.47 seconds
Started Jun 28 04:49:42 PM PDT 24
Finished Jun 28 04:49:57 PM PDT 24
Peak memory 211252 kb
Host smart-9a177888-cf01-4206-97b0-ee73242f0791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947238687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.947238687
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3272387212
Short name T158
Test name
Test status
Simulation time 43248309611 ps
CPU time 392.38 seconds
Started Jun 28 04:49:52 PM PDT 24
Finished Jun 28 04:56:26 PM PDT 24
Peak memory 212480 kb
Host smart-55750313-9284-41b8-ae63-d7dbf942cbcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272387212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3272387212
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3499797259
Short name T292
Test name
Test status
Simulation time 2188364598 ps
CPU time 22.5 seconds
Started Jun 28 04:49:57 PM PDT 24
Finished Jun 28 04:50:21 PM PDT 24
Peak memory 212052 kb
Host smart-76041ef2-db3b-4604-a82f-8c224cd2ad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499797259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3499797259
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1636354092
Short name T67
Test name
Test status
Simulation time 5741400626 ps
CPU time 13.66 seconds
Started Jun 28 04:49:54 PM PDT 24
Finished Jun 28 04:50:09 PM PDT 24
Peak memory 211372 kb
Host smart-417308e7-e407-48f3-a147-20bf8cf7616a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1636354092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1636354092
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1033837006
Short name T191
Test name
Test status
Simulation time 369125450 ps
CPU time 9.85 seconds
Started Jun 28 04:49:55 PM PDT 24
Finished Jun 28 04:50:06 PM PDT 24
Peak memory 213348 kb
Host smart-421a7d98-c202-4386-af11-99ba801c2166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033837006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1033837006
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1778795841
Short name T277
Test name
Test status
Simulation time 867309117 ps
CPU time 13.99 seconds
Started Jun 28 04:49:49 PM PDT 24
Finished Jun 28 04:50:05 PM PDT 24
Peak memory 213664 kb
Host smart-49e94101-4277-455c-b40b-b0d3540e7166
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778795841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1778795841
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1086695275
Short name T261
Test name
Test status
Simulation time 1736019615 ps
CPU time 13.56 seconds
Started Jun 28 04:49:49 PM PDT 24
Finished Jun 28 04:50:05 PM PDT 24
Peak memory 211264 kb
Host smart-f9004c4c-82a4-4e55-a58b-b9d353c3cdba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086695275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1086695275
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3188675660
Short name T231
Test name
Test status
Simulation time 1250447705 ps
CPU time 74.44 seconds
Started Jun 28 04:49:56 PM PDT 24
Finished Jun 28 04:51:12 PM PDT 24
Peak memory 232684 kb
Host smart-42d5476a-b939-4c4b-88e8-82c668d8eec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188675660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3188675660
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2988854124
Short name T152
Test name
Test status
Simulation time 11484057319 ps
CPU time 25.27 seconds
Started Jun 28 04:49:51 PM PDT 24
Finished Jun 28 04:50:18 PM PDT 24
Peak memory 212172 kb
Host smart-17d6415a-ca8e-4e62-b86d-14a289600aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988854124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2988854124
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.487642188
Short name T332
Test name
Test status
Simulation time 3499829609 ps
CPU time 9.11 seconds
Started Jun 28 04:49:56 PM PDT 24
Finished Jun 28 04:50:08 PM PDT 24
Peak memory 211372 kb
Host smart-31067648-9695-48eb-bb85-abf2d5800ee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487642188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.487642188
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3661465157
Short name T229
Test name
Test status
Simulation time 4068888687 ps
CPU time 23.58 seconds
Started Jun 28 04:49:43 PM PDT 24
Finished Jun 28 04:50:09 PM PDT 24
Peak memory 213636 kb
Host smart-004747f8-48d8-4502-8a2a-86d191157f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661465157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3661465157
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2086417147
Short name T184
Test name
Test status
Simulation time 396360280 ps
CPU time 22.55 seconds
Started Jun 28 04:49:52 PM PDT 24
Finished Jun 28 04:50:16 PM PDT 24
Peak memory 215268 kb
Host smart-34020cad-d1a7-4630-9787-2879b7f8b0b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086417147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2086417147
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.4290615666
Short name T306
Test name
Test status
Simulation time 6595170863 ps
CPU time 14.11 seconds
Started Jun 28 04:49:54 PM PDT 24
Finished Jun 28 04:50:10 PM PDT 24
Peak memory 211328 kb
Host smart-b1a1d75d-cb23-47d4-b6f5-3ff597e5eba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290615666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.4290615666
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3361332401
Short name T182
Test name
Test status
Simulation time 4475199596 ps
CPU time 134.77 seconds
Started Jun 28 04:49:46 PM PDT 24
Finished Jun 28 04:52:02 PM PDT 24
Peak memory 212464 kb
Host smart-e34bee1e-f26d-4ad9-945c-3afb5be2f093
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361332401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3361332401
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1842788741
Short name T200
Test name
Test status
Simulation time 3467657381 ps
CPU time 30.67 seconds
Started Jun 28 04:49:58 PM PDT 24
Finished Jun 28 04:50:30 PM PDT 24
Peak memory 211884 kb
Host smart-3962ce03-3b42-4fab-8095-1be50baeacba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842788741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1842788741
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3523804108
Short name T279
Test name
Test status
Simulation time 3308305747 ps
CPU time 14.2 seconds
Started Jun 28 04:49:49 PM PDT 24
Finished Jun 28 04:50:04 PM PDT 24
Peak memory 211372 kb
Host smart-6226b534-f146-46fb-b20d-8e4f2c9a028c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523804108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3523804108
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1890792008
Short name T132
Test name
Test status
Simulation time 47391153865 ps
CPU time 33.79 seconds
Started Jun 28 04:49:52 PM PDT 24
Finished Jun 28 04:50:27 PM PDT 24
Peak memory 213412 kb
Host smart-36fad033-ab27-4a01-a7b0-98f06eaae436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890792008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1890792008
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1852423895
Short name T266
Test name
Test status
Simulation time 3691244014 ps
CPU time 15.95 seconds
Started Jun 28 04:49:52 PM PDT 24
Finished Jun 28 04:50:10 PM PDT 24
Peak memory 214228 kb
Host smart-81bbc844-e9df-42f1-9daa-ad96d0d1e1ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852423895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1852423895
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2330120360
Short name T296
Test name
Test status
Simulation time 1261216187 ps
CPU time 8.52 seconds
Started Jun 28 04:48:54 PM PDT 24
Finished Jun 28 04:49:04 PM PDT 24
Peak memory 211268 kb
Host smart-71c072dd-098d-405f-bef9-04cddcf5e8bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330120360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2330120360
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1349233267
Short name T319
Test name
Test status
Simulation time 120512954822 ps
CPU time 390.45 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:55:38 PM PDT 24
Peak memory 236972 kb
Host smart-4cfa408c-e14c-48d2-acc9-7de5ea1520db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349233267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1349233267
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2210598984
Short name T354
Test name
Test status
Simulation time 60157913321 ps
CPU time 33.3 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 212096 kb
Host smart-2a278b40-7829-4e5b-be80-8fb622360eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210598984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2210598984
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.643561656
Short name T225
Test name
Test status
Simulation time 4445785323 ps
CPU time 17.04 seconds
Started Jun 28 04:49:24 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 211372 kb
Host smart-b3d7ba3e-4ae1-4d87-a0ca-cbfe29506934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643561656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.643561656
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3611769703
Short name T320
Test name
Test status
Simulation time 7030329964 ps
CPU time 29.49 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:40 PM PDT 24
Peak memory 214796 kb
Host smart-8c6d31fd-6fc2-43e7-89b3-0acb9334283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611769703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3611769703
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.611556469
Short name T239
Test name
Test status
Simulation time 1745512654 ps
CPU time 36.84 seconds
Started Jun 28 04:48:56 PM PDT 24
Finished Jun 28 04:49:35 PM PDT 24
Peak memory 215660 kb
Host smart-aa5a76a6-fb67-4c46-bb60-3613f54a99e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611556469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.611556469
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3515870438
Short name T59
Test name
Test status
Simulation time 41280348546 ps
CPU time 5374.74 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 06:18:48 PM PDT 24
Peak memory 235692 kb
Host smart-8a3abdb1-ea66-4672-a6ce-9c077c694e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515870438 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3515870438
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.4029799117
Short name T148
Test name
Test status
Simulation time 10505713755 ps
CPU time 14.02 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:23 PM PDT 24
Peak memory 211272 kb
Host smart-1c8c3300-be07-41e7-8d1f-ea119b412ccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029799117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.4029799117
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3114315593
Short name T131
Test name
Test status
Simulation time 78401731262 ps
CPU time 200.94 seconds
Started Jun 28 04:49:08 PM PDT 24
Finished Jun 28 04:52:31 PM PDT 24
Peak memory 237468 kb
Host smart-13ad9728-b1dc-4a90-90f3-b1c6f27ecd52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114315593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3114315593
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4264496487
Short name T240
Test name
Test status
Simulation time 6124513213 ps
CPU time 31.56 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:39 PM PDT 24
Peak memory 212244 kb
Host smart-65454285-2739-41e7-b797-a0933a31d55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264496487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4264496487
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3430054595
Short name T359
Test name
Test status
Simulation time 95090439 ps
CPU time 5.37 seconds
Started Jun 28 04:49:04 PM PDT 24
Finished Jun 28 04:49:10 PM PDT 24
Peak memory 211492 kb
Host smart-2a2dffae-45a4-4aa9-ba54-f7f6629fa211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3430054595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3430054595
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4271062214
Short name T264
Test name
Test status
Simulation time 590372768 ps
CPU time 13.71 seconds
Started Jun 28 04:49:10 PM PDT 24
Finished Jun 28 04:49:26 PM PDT 24
Peak memory 212612 kb
Host smart-ca71b899-03d7-4581-ae40-e60e22723e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271062214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4271062214
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2258048615
Short name T269
Test name
Test status
Simulation time 6437975500 ps
CPU time 61.5 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:50:12 PM PDT 24
Peak memory 217564 kb
Host smart-2a28d755-362b-4499-9aac-eab152ae2587
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258048615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2258048615
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.459279943
Short name T265
Test name
Test status
Simulation time 1621173379 ps
CPU time 9.27 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:49:17 PM PDT 24
Peak memory 211196 kb
Host smart-28676ec2-8c3f-4c04-b1b5-4ec9286f1699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459279943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.459279943
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1930851901
Short name T361
Test name
Test status
Simulation time 125341700088 ps
CPU time 332.81 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:54:46 PM PDT 24
Peak memory 234828 kb
Host smart-1f893530-7431-4be8-9056-7c34deca1d54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930851901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1930851901
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1790488486
Short name T222
Test name
Test status
Simulation time 1202718248 ps
CPU time 17.16 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:27 PM PDT 24
Peak memory 212012 kb
Host smart-656e5ad0-0c05-4459-83c9-020484fda0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790488486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1790488486
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1630545330
Short name T195
Test name
Test status
Simulation time 1748256993 ps
CPU time 13.14 seconds
Started Jun 28 04:48:58 PM PDT 24
Finished Jun 28 04:49:13 PM PDT 24
Peak memory 211312 kb
Host smart-af6e9d29-aae1-4163-9141-ed6efaddaa02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630545330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1630545330
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1567510620
Short name T129
Test name
Test status
Simulation time 363643013 ps
CPU time 9.84 seconds
Started Jun 28 04:49:04 PM PDT 24
Finished Jun 28 04:49:15 PM PDT 24
Peak memory 213536 kb
Host smart-b6c67975-64f6-4fdc-b8f6-f566befdb21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567510620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1567510620
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.721884892
Short name T256
Test name
Test status
Simulation time 295758614 ps
CPU time 17.1 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:49:25 PM PDT 24
Peak memory 216104 kb
Host smart-1c89ec16-867a-4c1a-8108-783de3d432c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721884892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.721884892
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2523984869
Short name T160
Test name
Test status
Simulation time 1788115339 ps
CPU time 15.09 seconds
Started Jun 28 04:49:04 PM PDT 24
Finished Jun 28 04:49:20 PM PDT 24
Peak memory 211268 kb
Host smart-db7db220-0d97-4880-bb04-dd89837b088a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523984869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2523984869
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2235081161
Short name T352
Test name
Test status
Simulation time 5829675615 ps
CPU time 89.53 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:50:39 PM PDT 24
Peak memory 233972 kb
Host smart-3233d75f-bf0f-43f3-b3e0-e4fa21f3b398
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235081161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2235081161
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3829565448
Short name T272
Test name
Test status
Simulation time 3264654011 ps
CPU time 27.37 seconds
Started Jun 28 04:49:08 PM PDT 24
Finished Jun 28 04:49:38 PM PDT 24
Peak memory 211672 kb
Host smart-f3113d6f-69f1-49d9-b613-2ef63516d99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829565448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3829565448
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1887604773
Short name T48
Test name
Test status
Simulation time 5814910634 ps
CPU time 13.4 seconds
Started Jun 28 04:49:11 PM PDT 24
Finished Jun 28 04:49:26 PM PDT 24
Peak memory 211304 kb
Host smart-30c5321b-2b8a-4e47-8fca-841bca172b77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887604773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1887604773
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1095270339
Short name T135
Test name
Test status
Simulation time 3797962944 ps
CPU time 31.85 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:42 PM PDT 24
Peak memory 213788 kb
Host smart-746bd36d-4a89-41ea-8878-7640fe97c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095270339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1095270339
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3584911136
Short name T347
Test name
Test status
Simulation time 11907288644 ps
CPU time 57.11 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:50:05 PM PDT 24
Peak memory 215224 kb
Host smart-b6adeb0f-d777-4ebb-88ea-50dfde9c5f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584911136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3584911136
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4235234825
Short name T144
Test name
Test status
Simulation time 88824342 ps
CPU time 4.35 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:49:16 PM PDT 24
Peak memory 211200 kb
Host smart-041ae31a-8d24-4b74-b6db-9fa620778c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235234825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4235234825
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2502346515
Short name T329
Test name
Test status
Simulation time 8859860104 ps
CPU time 169.01 seconds
Started Jun 28 04:49:05 PM PDT 24
Finished Jun 28 04:51:55 PM PDT 24
Peak memory 234812 kb
Host smart-391d9775-dff5-4514-a3e4-bc967c5ccbf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502346515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2502346515
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1779486134
Short name T171
Test name
Test status
Simulation time 12792562778 ps
CPU time 23.75 seconds
Started Jun 28 04:49:04 PM PDT 24
Finished Jun 28 04:49:28 PM PDT 24
Peak memory 215312 kb
Host smart-02916d28-81d2-44b3-97d3-b121eed749b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779486134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1779486134
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2971319446
Short name T323
Test name
Test status
Simulation time 4817445951 ps
CPU time 13.13 seconds
Started Jun 28 04:49:06 PM PDT 24
Finished Jun 28 04:49:22 PM PDT 24
Peak memory 211304 kb
Host smart-a93bed77-2863-41c9-9f76-804bab1cb5ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971319446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2971319446
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2267431174
Short name T99
Test name
Test status
Simulation time 10706764801 ps
CPU time 34.18 seconds
Started Jun 28 04:49:09 PM PDT 24
Finished Jun 28 04:49:45 PM PDT 24
Peak memory 213936 kb
Host smart-ef631ff6-743d-4025-ad58-bf55294ac9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267431174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2267431174
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.603869915
Short name T252
Test name
Test status
Simulation time 10943395650 ps
CPU time 30.72 seconds
Started Jun 28 04:49:07 PM PDT 24
Finished Jun 28 04:49:40 PM PDT 24
Peak memory 216368 kb
Host smart-7319ef1b-4d40-420d-baae-a01ddea911b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603869915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.603869915
Directory /workspace/9.rom_ctrl_stress_all/latest
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