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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 96.89 92.13 97.67 100.00 98.62 97.45 99.07


Total test records in report: 465
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T298 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2836922353 Jun 29 04:41:02 PM PDT 24 Jun 29 04:41:27 PM PDT 24 14949286596 ps
T299 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.888343673 Jun 29 04:41:13 PM PDT 24 Jun 29 04:41:28 PM PDT 24 3266488062 ps
T300 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.47349569 Jun 29 04:40:03 PM PDT 24 Jun 29 04:43:53 PM PDT 24 28295410646 ps
T301 /workspace/coverage/default/42.rom_ctrl_stress_all.680726557 Jun 29 04:41:11 PM PDT 24 Jun 29 04:42:03 PM PDT 24 4171740319 ps
T302 /workspace/coverage/default/2.rom_ctrl_smoke.3517003467 Jun 29 04:39:48 PM PDT 24 Jun 29 04:40:17 PM PDT 24 3366624086 ps
T303 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3466315045 Jun 29 04:39:47 PM PDT 24 Jun 29 04:43:44 PM PDT 24 13474338953 ps
T304 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1279210247 Jun 29 04:40:51 PM PDT 24 Jun 29 04:40:58 PM PDT 24 553350590 ps
T305 /workspace/coverage/default/30.rom_ctrl_stress_all.1341972688 Jun 29 04:40:41 PM PDT 24 Jun 29 04:41:24 PM PDT 24 7751243144 ps
T306 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3164342371 Jun 29 04:39:47 PM PDT 24 Jun 29 05:15:26 PM PDT 24 18080049676 ps
T307 /workspace/coverage/default/4.rom_ctrl_smoke.2581297989 Jun 29 04:39:53 PM PDT 24 Jun 29 04:40:19 PM PDT 24 16536641561 ps
T308 /workspace/coverage/default/13.rom_ctrl_stress_all.1328422280 Jun 29 04:40:02 PM PDT 24 Jun 29 04:41:07 PM PDT 24 6575631089 ps
T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.2192784871 Jun 29 04:39:46 PM PDT 24 Jun 29 04:40:48 PM PDT 24 3313238696 ps
T309 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3342818262 Jun 29 04:40:42 PM PDT 24 Jun 29 04:41:07 PM PDT 24 7657937379 ps
T310 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1105596938 Jun 29 04:40:17 PM PDT 24 Jun 29 04:40:27 PM PDT 24 607262563 ps
T311 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.938527905 Jun 29 04:40:03 PM PDT 24 Jun 29 04:40:24 PM PDT 24 3698798309 ps
T312 /workspace/coverage/default/34.rom_ctrl_alert_test.1180652558 Jun 29 04:40:51 PM PDT 24 Jun 29 04:41:00 PM PDT 24 820927665 ps
T313 /workspace/coverage/default/37.rom_ctrl_smoke.4039470598 Jun 29 04:41:00 PM PDT 24 Jun 29 04:41:41 PM PDT 24 6999808548 ps
T314 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2757811429 Jun 29 04:40:03 PM PDT 24 Jun 29 04:40:15 PM PDT 24 2849403581 ps
T315 /workspace/coverage/default/47.rom_ctrl_stress_all.1530552575 Jun 29 04:41:10 PM PDT 24 Jun 29 04:41:28 PM PDT 24 1624581413 ps
T316 /workspace/coverage/default/32.rom_ctrl_alert_test.3842356280 Jun 29 04:40:51 PM PDT 24 Jun 29 04:41:01 PM PDT 24 1781728079 ps
T317 /workspace/coverage/default/35.rom_ctrl_alert_test.883222174 Jun 29 04:40:52 PM PDT 24 Jun 29 04:41:00 PM PDT 24 472328258 ps
T318 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4130074545 Jun 29 04:40:01 PM PDT 24 Jun 29 04:40:08 PM PDT 24 882821622 ps
T319 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.431058808 Jun 29 04:40:17 PM PDT 24 Jun 29 04:40:27 PM PDT 24 334521196 ps
T320 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2230410599 Jun 29 04:40:11 PM PDT 24 Jun 29 04:44:00 PM PDT 24 42931242562 ps
T321 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4008224521 Jun 29 04:39:47 PM PDT 24 Jun 29 04:39:58 PM PDT 24 3010730894 ps
T322 /workspace/coverage/default/37.rom_ctrl_alert_test.1748410874 Jun 29 04:41:01 PM PDT 24 Jun 29 04:41:16 PM PDT 24 3426922047 ps
T323 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.460453202 Jun 29 04:40:43 PM PDT 24 Jun 29 04:40:57 PM PDT 24 1474483399 ps
T324 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1523321566 Jun 29 04:40:11 PM PDT 24 Jun 29 04:40:30 PM PDT 24 1450237832 ps
T325 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1985751280 Jun 29 04:40:43 PM PDT 24 Jun 29 04:43:02 PM PDT 24 25888557370 ps
T326 /workspace/coverage/default/15.rom_ctrl_alert_test.843738151 Jun 29 04:40:05 PM PDT 24 Jun 29 04:40:16 PM PDT 24 3962566438 ps
T327 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2082714334 Jun 29 04:39:55 PM PDT 24 Jun 29 04:40:27 PM PDT 24 7483723377 ps
T328 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1561250012 Jun 29 04:39:47 PM PDT 24 Jun 29 04:40:19 PM PDT 24 3610970429 ps
T329 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3396059547 Jun 29 04:41:16 PM PDT 24 Jun 29 04:41:22 PM PDT 24 602054502 ps
T330 /workspace/coverage/default/22.rom_ctrl_stress_all.666870584 Jun 29 04:40:18 PM PDT 24 Jun 29 04:40:36 PM PDT 24 2502980893 ps
T331 /workspace/coverage/default/17.rom_ctrl_smoke.984745457 Jun 29 04:40:11 PM PDT 24 Jun 29 04:40:52 PM PDT 24 3632599793 ps
T332 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.336604827 Jun 29 04:39:49 PM PDT 24 Jun 29 04:40:21 PM PDT 24 12037930568 ps
T333 /workspace/coverage/default/45.rom_ctrl_alert_test.1392907005 Jun 29 04:41:10 PM PDT 24 Jun 29 04:41:20 PM PDT 24 788581167 ps
T334 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1474149809 Jun 29 04:40:49 PM PDT 24 Jun 29 04:41:20 PM PDT 24 15276942286 ps
T335 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.979092029 Jun 29 04:40:49 PM PDT 24 Jun 29 04:41:04 PM PDT 24 4855590474 ps
T336 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4066450634 Jun 29 04:41:03 PM PDT 24 Jun 29 04:43:13 PM PDT 24 18312095140 ps
T337 /workspace/coverage/default/38.rom_ctrl_stress_all.4036970071 Jun 29 04:41:00 PM PDT 24 Jun 29 04:41:56 PM PDT 24 6422538872 ps
T338 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1770068839 Jun 29 04:40:18 PM PDT 24 Jun 29 05:08:43 PM PDT 24 89600781481 ps
T339 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1276789788 Jun 29 04:41:11 PM PDT 24 Jun 29 04:41:32 PM PDT 24 1934101231 ps
T340 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.600912917 Jun 29 04:40:43 PM PDT 24 Jun 29 04:43:19 PM PDT 24 6356119715 ps
T13 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.577926236 Jun 29 04:41:12 PM PDT 24 Jun 29 06:18:31 PM PDT 24 105827243693 ps
T341 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.550374132 Jun 29 04:40:18 PM PDT 24 Jun 29 04:43:19 PM PDT 24 56011094149 ps
T342 /workspace/coverage/default/21.rom_ctrl_smoke.1710050723 Jun 29 04:40:25 PM PDT 24 Jun 29 04:40:36 PM PDT 24 722333622 ps
T343 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.565067901 Jun 29 04:41:09 PM PDT 24 Jun 29 04:46:17 PM PDT 24 31273331722 ps
T344 /workspace/coverage/default/35.rom_ctrl_smoke.1521330824 Jun 29 04:40:50 PM PDT 24 Jun 29 04:41:23 PM PDT 24 6748981471 ps
T345 /workspace/coverage/default/39.rom_ctrl_smoke.413679173 Jun 29 04:41:00 PM PDT 24 Jun 29 04:41:32 PM PDT 24 8035469337 ps
T346 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2590378648 Jun 29 04:39:53 PM PDT 24 Jun 29 04:40:06 PM PDT 24 1225165628 ps
T347 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.162302342 Jun 29 04:40:10 PM PDT 24 Jun 29 04:42:10 PM PDT 24 32508538479 ps
T348 /workspace/coverage/default/28.rom_ctrl_stress_all.1016960539 Jun 29 04:40:26 PM PDT 24 Jun 29 04:41:33 PM PDT 24 9052928168 ps
T349 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2932817730 Jun 29 04:40:22 PM PDT 24 Jun 29 04:40:53 PM PDT 24 14735232164 ps
T350 /workspace/coverage/default/41.rom_ctrl_stress_all.3844822677 Jun 29 04:41:03 PM PDT 24 Jun 29 04:41:40 PM PDT 24 8229273250 ps
T351 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1047222191 Jun 29 04:40:24 PM PDT 24 Jun 29 04:40:42 PM PDT 24 6850182571 ps
T352 /workspace/coverage/default/48.rom_ctrl_alert_test.2504921989 Jun 29 04:41:12 PM PDT 24 Jun 29 04:41:22 PM PDT 24 852425091 ps
T353 /workspace/coverage/default/34.rom_ctrl_stress_all.2997836553 Jun 29 04:40:48 PM PDT 24 Jun 29 04:41:04 PM PDT 24 6543599568 ps
T354 /workspace/coverage/default/48.rom_ctrl_stress_all.150174513 Jun 29 04:41:12 PM PDT 24 Jun 29 04:41:44 PM PDT 24 1086927336 ps
T355 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4175883662 Jun 29 04:40:43 PM PDT 24 Jun 29 04:40:57 PM PDT 24 2805419515 ps
T356 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1228057275 Jun 29 04:40:34 PM PDT 24 Jun 29 04:41:01 PM PDT 24 2986789413 ps
T357 /workspace/coverage/default/41.rom_ctrl_alert_test.4040929658 Jun 29 04:41:13 PM PDT 24 Jun 29 04:41:30 PM PDT 24 1912341206 ps
T358 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1847773434 Jun 29 04:40:09 PM PDT 24 Jun 29 04:56:40 PM PDT 24 12169464950 ps
T359 /workspace/coverage/default/38.rom_ctrl_alert_test.446157430 Jun 29 04:41:01 PM PDT 24 Jun 29 04:41:11 PM PDT 24 1596347405 ps
T29 /workspace/coverage/default/3.rom_ctrl_sec_cm.297153993 Jun 29 04:39:54 PM PDT 24 Jun 29 04:41:36 PM PDT 24 891402164 ps
T360 /workspace/coverage/default/17.rom_ctrl_stress_all.3329529377 Jun 29 04:40:09 PM PDT 24 Jun 29 04:40:26 PM PDT 24 4537708461 ps
T361 /workspace/coverage/default/0.rom_ctrl_stress_all.266693243 Jun 29 04:39:49 PM PDT 24 Jun 29 04:40:33 PM PDT 24 782478492 ps
T362 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2776482768 Jun 29 04:40:01 PM PDT 24 Jun 29 04:40:16 PM PDT 24 1499926280 ps
T363 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1974600945 Jun 29 04:40:10 PM PDT 24 Jun 29 04:40:28 PM PDT 24 8726315117 ps
T364 /workspace/coverage/default/19.rom_ctrl_alert_test.3290186337 Jun 29 04:40:13 PM PDT 24 Jun 29 04:40:27 PM PDT 24 5550221192 ps
T365 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1405978742 Jun 29 05:34:37 PM PDT 24 Jun 29 05:34:52 PM PDT 24 3447975474 ps
T366 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3434870552 Jun 29 05:34:35 PM PDT 24 Jun 29 05:34:57 PM PDT 24 2009800289 ps
T65 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3889699978 Jun 29 05:34:25 PM PDT 24 Jun 29 05:35:07 PM PDT 24 5130205070 ps
T66 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3101026011 Jun 29 05:34:37 PM PDT 24 Jun 29 05:34:47 PM PDT 24 397656957 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1246701167 Jun 29 05:34:19 PM PDT 24 Jun 29 05:34:27 PM PDT 24 1643695411 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.227593510 Jun 29 05:34:20 PM PDT 24 Jun 29 05:34:37 PM PDT 24 1132428975 ps
T68 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1502541727 Jun 29 05:34:24 PM PDT 24 Jun 29 05:34:44 PM PDT 24 374123184 ps
T69 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1008715041 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:36 PM PDT 24 2791893119 ps
T62 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.47195678 Jun 29 05:34:30 PM PDT 24 Jun 29 05:35:12 PM PDT 24 3725494905 ps
T63 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2387218286 Jun 29 05:34:32 PM PDT 24 Jun 29 05:35:13 PM PDT 24 2730497610 ps
T70 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3398748946 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:43 PM PDT 24 7679579670 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.725286409 Jun 29 05:34:06 PM PDT 24 Jun 29 05:34:47 PM PDT 24 734006950 ps
T71 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1257158505 Jun 29 05:34:22 PM PDT 24 Jun 29 05:34:51 PM PDT 24 2185196325 ps
T72 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2217076966 Jun 29 05:34:33 PM PDT 24 Jun 29 05:34:42 PM PDT 24 2583646809 ps
T73 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.630320483 Jun 29 05:34:30 PM PDT 24 Jun 29 05:34:46 PM PDT 24 3677964095 ps
T368 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.784514530 Jun 29 05:34:34 PM PDT 24 Jun 29 05:34:44 PM PDT 24 5314414177 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1927475344 Jun 29 05:34:10 PM PDT 24 Jun 29 05:34:19 PM PDT 24 820468276 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1839609245 Jun 29 05:34:25 PM PDT 24 Jun 29 05:35:45 PM PDT 24 2350336389 ps
T370 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.819766325 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:48 PM PDT 24 7796209504 ps
T74 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2898847685 Jun 29 05:34:24 PM PDT 24 Jun 29 05:34:38 PM PDT 24 4160318024 ps
T371 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4135441095 Jun 29 05:34:48 PM PDT 24 Jun 29 05:35:07 PM PDT 24 2093242018 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4140573639 Jun 29 05:34:27 PM PDT 24 Jun 29 05:34:37 PM PDT 24 677785541 ps
T75 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3823744923 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:33 PM PDT 24 136967745 ps
T101 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2704627895 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:43 PM PDT 24 1957440223 ps
T110 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1842193853 Jun 29 05:34:22 PM PDT 24 Jun 29 05:35:08 PM PDT 24 32593054096 ps
T79 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.964215958 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:41 PM PDT 24 10170305518 ps
T373 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3788799280 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:30 PM PDT 24 1073712010 ps
T80 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.292349162 Jun 29 05:34:26 PM PDT 24 Jun 29 05:35:20 PM PDT 24 44505191721 ps
T81 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1720428352 Jun 29 05:34:21 PM PDT 24 Jun 29 05:34:26 PM PDT 24 89200709 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4290311556 Jun 29 05:34:30 PM PDT 24 Jun 29 05:34:36 PM PDT 24 333771605 ps
T82 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4084019138 Jun 29 05:34:41 PM PDT 24 Jun 29 05:35:49 PM PDT 24 37307874678 ps
T375 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1428787313 Jun 29 05:34:27 PM PDT 24 Jun 29 05:34:44 PM PDT 24 2119807540 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2295588711 Jun 29 05:34:36 PM PDT 24 Jun 29 05:34:42 PM PDT 24 89090428 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.355999743 Jun 29 05:34:21 PM PDT 24 Jun 29 05:34:38 PM PDT 24 2126849724 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.216136139 Jun 29 05:34:10 PM PDT 24 Jun 29 05:34:25 PM PDT 24 6999773660 ps
T83 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.740361227 Jun 29 05:34:23 PM PDT 24 Jun 29 05:35:14 PM PDT 24 10661503185 ps
T104 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.492585164 Jun 29 05:34:22 PM PDT 24 Jun 29 05:35:11 PM PDT 24 2060542971 ps
T379 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.374846979 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:35 PM PDT 24 6171674795 ps
T380 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.809665743 Jun 29 05:34:29 PM PDT 24 Jun 29 05:34:35 PM PDT 24 1652524606 ps
T84 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3407463680 Jun 29 05:34:28 PM PDT 24 Jun 29 05:35:35 PM PDT 24 39845519628 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2805084874 Jun 29 05:34:27 PM PDT 24 Jun 29 05:34:48 PM PDT 24 741985022 ps
T382 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2088909524 Jun 29 05:34:29 PM PDT 24 Jun 29 05:34:45 PM PDT 24 3775786770 ps
T383 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1230821743 Jun 29 05:34:22 PM PDT 24 Jun 29 05:34:37 PM PDT 24 1533626502 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1587781803 Jun 29 05:34:22 PM PDT 24 Jun 29 05:34:37 PM PDT 24 1475647902 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3764285108 Jun 29 05:34:22 PM PDT 24 Jun 29 05:34:33 PM PDT 24 650887934 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.168390830 Jun 29 05:34:16 PM PDT 24 Jun 29 05:34:31 PM PDT 24 1794822509 ps
T102 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1090315041 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:29 PM PDT 24 347723875 ps
T387 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.212573329 Jun 29 05:34:41 PM PDT 24 Jun 29 05:35:00 PM PDT 24 5940192375 ps
T388 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2727497852 Jun 29 05:34:33 PM PDT 24 Jun 29 05:34:43 PM PDT 24 2466925856 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4037405618 Jun 29 05:34:20 PM PDT 24 Jun 29 05:34:25 PM PDT 24 179063891 ps
T116 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4830294 Jun 29 05:34:26 PM PDT 24 Jun 29 05:35:12 PM PDT 24 2912090780 ps
T105 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1325873569 Jun 29 05:34:26 PM PDT 24 Jun 29 05:35:42 PM PDT 24 14851734716 ps
T390 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2499396928 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:39 PM PDT 24 2874911308 ps
T391 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3109168718 Jun 29 05:34:28 PM PDT 24 Jun 29 05:34:40 PM PDT 24 984895610 ps
T392 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3005212086 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:36 PM PDT 24 3980730256 ps
T85 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.903812092 Jun 29 05:34:28 PM PDT 24 Jun 29 05:34:45 PM PDT 24 7880160217 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1186768809 Jun 29 05:34:10 PM PDT 24 Jun 29 05:34:26 PM PDT 24 9161489535 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.175699569 Jun 29 05:34:26 PM PDT 24 Jun 29 05:35:47 PM PDT 24 2156046000 ps
T103 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3225276892 Jun 29 05:34:14 PM PDT 24 Jun 29 05:34:59 PM PDT 24 2522890041 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3688478983 Jun 29 05:34:46 PM PDT 24 Jun 29 05:34:51 PM PDT 24 175614294 ps
T395 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.809783157 Jun 29 05:34:32 PM PDT 24 Jun 29 05:34:48 PM PDT 24 8701047659 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3775235710 Jun 29 05:34:29 PM PDT 24 Jun 29 05:34:47 PM PDT 24 2243452330 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3008290711 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:36 PM PDT 24 1201862201 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1359506390 Jun 29 05:34:27 PM PDT 24 Jun 29 05:34:34 PM PDT 24 89285693 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3358069295 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:44 PM PDT 24 2170631933 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4126884200 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:41 PM PDT 24 6175666698 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.463156137 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:33 PM PDT 24 108838953 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2164492749 Jun 29 05:34:24 PM PDT 24 Jun 29 05:34:43 PM PDT 24 367161717 ps
T107 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3245930351 Jun 29 05:34:34 PM PDT 24 Jun 29 05:35:20 PM PDT 24 9180575801 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2541877457 Jun 29 05:34:15 PM PDT 24 Jun 29 05:34:30 PM PDT 24 7483468928 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3723832277 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:30 PM PDT 24 434407099 ps
T117 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2394032245 Jun 29 05:34:29 PM PDT 24 Jun 29 05:35:50 PM PDT 24 1868453930 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.756119895 Jun 29 05:34:35 PM PDT 24 Jun 29 05:34:41 PM PDT 24 269083107 ps
T406 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.578847125 Jun 29 05:34:28 PM PDT 24 Jun 29 05:35:48 PM PDT 24 36406321341 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3742120454 Jun 29 05:34:18 PM PDT 24 Jun 29 05:34:35 PM PDT 24 4345213111 ps
T108 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3393462168 Jun 29 05:34:27 PM PDT 24 Jun 29 05:35:40 PM PDT 24 2465879347 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2790518418 Jun 29 05:34:42 PM PDT 24 Jun 29 05:34:48 PM PDT 24 111241928 ps
T409 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.986291224 Jun 29 05:34:19 PM PDT 24 Jun 29 05:34:31 PM PDT 24 6683415562 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3762927740 Jun 29 05:34:27 PM PDT 24 Jun 29 05:35:42 PM PDT 24 33928736370 ps
T411 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1771080736 Jun 29 05:34:30 PM PDT 24 Jun 29 05:34:47 PM PDT 24 18945149215 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1766407677 Jun 29 05:34:11 PM PDT 24 Jun 29 05:34:20 PM PDT 24 105561201 ps
T413 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1127887353 Jun 29 05:34:30 PM PDT 24 Jun 29 05:34:35 PM PDT 24 89151125 ps
T414 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2323394865 Jun 29 05:34:33 PM PDT 24 Jun 29 05:35:19 PM PDT 24 1711987752 ps
T86 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2775575374 Jun 29 05:34:31 PM PDT 24 Jun 29 05:35:50 PM PDT 24 85922840313 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.562613260 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:33 PM PDT 24 2928792725 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.39980073 Jun 29 05:34:24 PM PDT 24 Jun 29 05:34:31 PM PDT 24 210588584 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1133773575 Jun 29 05:34:24 PM PDT 24 Jun 29 05:34:38 PM PDT 24 2842188615 ps
T418 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3824245894 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:41 PM PDT 24 2040184348 ps
T419 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1992924714 Jun 29 05:34:22 PM PDT 24 Jun 29 05:34:34 PM PDT 24 1123729407 ps
T420 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3513291734 Jun 29 05:34:28 PM PDT 24 Jun 29 05:35:07 PM PDT 24 1557993185 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.414817166 Jun 29 05:34:20 PM PDT 24 Jun 29 05:35:40 PM PDT 24 7983819494 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.679755248 Jun 29 05:34:28 PM PDT 24 Jun 29 05:34:43 PM PDT 24 1505069221 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1988033971 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:38 PM PDT 24 2463072561 ps
T423 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2765789165 Jun 29 05:34:20 PM PDT 24 Jun 29 05:34:29 PM PDT 24 2264519539 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.582148168 Jun 29 05:34:14 PM PDT 24 Jun 29 05:34:32 PM PDT 24 6836405285 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.364136008 Jun 29 05:34:16 PM PDT 24 Jun 29 05:34:32 PM PDT 24 8986475168 ps
T426 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1079479478 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:43 PM PDT 24 7167043601 ps
T106 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.208345155 Jun 29 05:34:23 PM PDT 24 Jun 29 05:35:04 PM PDT 24 298253325 ps
T427 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3654816099 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:35 PM PDT 24 5137887923 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.458603552 Jun 29 05:34:11 PM PDT 24 Jun 29 05:34:27 PM PDT 24 1642960999 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4153913997 Jun 29 05:34:28 PM PDT 24 Jun 29 05:34:44 PM PDT 24 6642857145 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2503565343 Jun 29 05:34:16 PM PDT 24 Jun 29 05:34:21 PM PDT 24 98878262 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1312960529 Jun 29 05:34:24 PM PDT 24 Jun 29 05:34:35 PM PDT 24 569478751 ps
T89 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1828240312 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:35 PM PDT 24 3724974690 ps
T431 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4194500003 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:41 PM PDT 24 1663454460 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1137166933 Jun 29 05:34:21 PM PDT 24 Jun 29 05:34:35 PM PDT 24 5937662211 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3108480431 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:42 PM PDT 24 2797137190 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1911784179 Jun 29 05:34:23 PM PDT 24 Jun 29 05:35:39 PM PDT 24 8664992767 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4278586844 Jun 29 05:34:11 PM PDT 24 Jun 29 05:34:51 PM PDT 24 3041846337 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2109474348 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:38 PM PDT 24 1087778391 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1015754384 Jun 29 05:34:15 PM PDT 24 Jun 29 05:34:27 PM PDT 24 1277102774 ps
T437 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2885611121 Jun 29 05:34:34 PM PDT 24 Jun 29 05:34:51 PM PDT 24 22923624866 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2027570640 Jun 29 05:34:24 PM PDT 24 Jun 29 05:34:31 PM PDT 24 663211466 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3443035366 Jun 29 05:34:18 PM PDT 24 Jun 29 05:34:25 PM PDT 24 248481013 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3196176677 Jun 29 05:34:30 PM PDT 24 Jun 29 05:34:45 PM PDT 24 1789997539 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.942783599 Jun 29 05:34:22 PM PDT 24 Jun 29 05:34:40 PM PDT 24 8059356356 ps
T111 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3634404335 Jun 29 05:34:11 PM PDT 24 Jun 29 05:34:51 PM PDT 24 392275699 ps
T442 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4047547257 Jun 29 05:34:22 PM PDT 24 Jun 29 05:36:00 PM PDT 24 25573585016 ps
T115 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2904532772 Jun 29 05:34:30 PM PDT 24 Jun 29 05:35:49 PM PDT 24 8519962190 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2070513417 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:37 PM PDT 24 992759939 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2007451942 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:31 PM PDT 24 89190570 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2130181282 Jun 29 05:34:17 PM PDT 24 Jun 29 05:35:03 PM PDT 24 4488032039 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2608377354 Jun 29 05:34:14 PM PDT 24 Jun 29 05:34:29 PM PDT 24 6853663561 ps
T447 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2568979711 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:38 PM PDT 24 2215885969 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.588048476 Jun 29 05:34:17 PM PDT 24 Jun 29 05:34:29 PM PDT 24 12783513698 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.810668290 Jun 29 05:34:15 PM PDT 24 Jun 29 05:34:21 PM PDT 24 94492776 ps
T112 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1977484249 Jun 29 05:34:15 PM PDT 24 Jun 29 05:34:55 PM PDT 24 900567183 ps
T450 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2761139569 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:52 PM PDT 24 5336013776 ps
T451 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2605807628 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:42 PM PDT 24 10439513160 ps
T452 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1369802037 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:36 PM PDT 24 2179766787 ps
T453 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.132823163 Jun 29 05:34:36 PM PDT 24 Jun 29 05:34:53 PM PDT 24 7479258168 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1143612163 Jun 29 05:34:23 PM PDT 24 Jun 29 05:34:28 PM PDT 24 346245025 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2218330452 Jun 29 05:34:34 PM PDT 24 Jun 29 05:34:43 PM PDT 24 1964574852 ps
T456 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3343510693 Jun 29 05:34:25 PM PDT 24 Jun 29 05:34:38 PM PDT 24 1210716070 ps
T457 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2347112941 Jun 29 05:34:28 PM PDT 24 Jun 29 05:35:50 PM PDT 24 8354216804 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.238695185 Jun 29 05:34:15 PM PDT 24 Jun 29 05:34:25 PM PDT 24 766838783 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3237163463 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:46 PM PDT 24 1092765401 ps
T459 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.732930706 Jun 29 05:34:32 PM PDT 24 Jun 29 05:34:50 PM PDT 24 5028341793 ps
T460 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.803976616 Jun 29 05:34:09 PM PDT 24 Jun 29 05:34:23 PM PDT 24 2875711257 ps
T461 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2138331855 Jun 29 05:34:27 PM PDT 24 Jun 29 05:34:43 PM PDT 24 3532699595 ps
T462 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1560256148 Jun 29 05:34:24 PM PDT 24 Jun 29 05:34:39 PM PDT 24 3090233729 ps
T463 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3354551208 Jun 29 05:34:36 PM PDT 24 Jun 29 05:34:45 PM PDT 24 1008978975 ps
T118 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3518402424 Jun 29 05:34:24 PM PDT 24 Jun 29 05:35:08 PM PDT 24 4891656941 ps
T464 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.461549068 Jun 29 05:34:08 PM PDT 24 Jun 29 05:34:24 PM PDT 24 11048090858 ps
T465 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3230447447 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:45 PM PDT 24 7469221118 ps

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2189148992
Short name T5
Test name
Test status
Simulation time 85455621093 ps
CPU time 3803.48 seconds
Started Jun 29 04:40:25 PM PDT 24
Finished Jun 29 05:43:50 PM PDT 24
Peak memory 252260 kb
Host smart-a4e9970b-0b55-479d-a608-87a9d229a8dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189148992 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2189148992
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.78848046
Short name T17
Test name
Test status
Simulation time 220554120431 ps
CPU time 401.14 seconds
Started Jun 29 04:40:21 PM PDT 24
Finished Jun 29 04:47:03 PM PDT 24
Peak memory 237828 kb
Host smart-6a3c146f-11f9-4379-9a72-d083cfec2602
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78848046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_co
rrupt_sig_fatal_chk.78848046
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3083776684
Short name T4
Test name
Test status
Simulation time 2310138305 ps
CPU time 23.75 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:40:42 PM PDT 24
Peak memory 213136 kb
Host smart-96dccb1e-2095-4768-a86e-a0d0870f59b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083776684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3083776684
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2072192610
Short name T51
Test name
Test status
Simulation time 136391128616 ps
CPU time 215.51 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:43:31 PM PDT 24
Peak memory 236964 kb
Host smart-feeae790-ee79-46c7-8689-9e76009556ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072192610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2072192610
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1839609245
Short name T109
Test name
Test status
Simulation time 2350336389 ps
CPU time 79.56 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:35:45 PM PDT 24
Peak memory 212220 kb
Host smart-4bdb7a66-c39f-418f-baf4-4b12c8a33407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839609245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1839609245
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3534314512
Short name T20
Test name
Test status
Simulation time 206129494 ps
CPU time 100.66 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:41:28 PM PDT 24
Peak memory 238100 kb
Host smart-824bffb0-061a-4966-b39b-55dce3baee35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534314512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3534314512
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1502541727
Short name T68
Test name
Test status
Simulation time 374123184 ps
CPU time 19.34 seconds
Started Jun 29 05:34:24 PM PDT 24
Finished Jun 29 05:34:44 PM PDT 24
Peak memory 210684 kb
Host smart-e2fc775b-7631-4e1e-8e83-8a0fa2e753d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502541727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1502541727
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3393462168
Short name T108
Test name
Test status
Simulation time 2465879347 ps
CPU time 71.51 seconds
Started Jun 29 05:34:27 PM PDT 24
Finished Jun 29 05:35:40 PM PDT 24
Peak memory 212368 kb
Host smart-ca5208c3-adc7-4cf3-bc0c-8a7cbed726ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393462168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3393462168
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2090454605
Short name T91
Test name
Test status
Simulation time 364607517 ps
CPU time 10.11 seconds
Started Jun 29 04:40:06 PM PDT 24
Finished Jun 29 04:40:16 PM PDT 24
Peak memory 213484 kb
Host smart-e5061008-a233-443d-9f13-ca756b81d38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090454605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2090454605
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2806016492
Short name T7
Test name
Test status
Simulation time 15067441772 ps
CPU time 31.3 seconds
Started Jun 29 04:40:10 PM PDT 24
Finished Jun 29 04:40:43 PM PDT 24
Peak memory 212316 kb
Host smart-e5e45de8-097b-41b9-b33f-f8576dea166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806016492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2806016492
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2514193266
Short name T129
Test name
Test status
Simulation time 8707648692 ps
CPU time 16.02 seconds
Started Jun 29 04:39:47 PM PDT 24
Finished Jun 29 04:40:04 PM PDT 24
Peak memory 211312 kb
Host smart-865f2a24-f818-4f74-ad84-e32c1bc9bd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514193266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2514193266
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.230302912
Short name T191
Test name
Test status
Simulation time 17070349889 ps
CPU time 30.6 seconds
Started Jun 29 04:40:01 PM PDT 24
Finished Jun 29 04:40:33 PM PDT 24
Peak memory 212252 kb
Host smart-ea90285a-2fa2-4021-b0b9-be39b7ca9175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230302912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.230302912
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2544175061
Short name T54
Test name
Test status
Simulation time 15667154557 ps
CPU time 31.12 seconds
Started Jun 29 04:40:01 PM PDT 24
Finished Jun 29 04:40:32 PM PDT 24
Peak memory 212300 kb
Host smart-d7acae2c-e2ee-4f42-ac02-551d0c59eb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544175061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2544175061
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3634404335
Short name T111
Test name
Test status
Simulation time 392275699 ps
CPU time 39.57 seconds
Started Jun 29 05:34:11 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 211012 kb
Host smart-d50fdf14-84ef-4ee5-b785-1e50455bf1d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634404335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3634404335
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3225276892
Short name T103
Test name
Test status
Simulation time 2522890041 ps
CPU time 44.65 seconds
Started Jun 29 05:34:14 PM PDT 24
Finished Jun 29 05:34:59 PM PDT 24
Peak memory 211856 kb
Host smart-fb2cc69c-e131-407e-b949-f8c29aaeb163
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225276892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3225276892
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4830294
Short name T116
Test name
Test status
Simulation time 2912090780 ps
CPU time 44.77 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:35:12 PM PDT 24
Peak memory 219004 kb
Host smart-7028bbeb-26b5-4d57-8e33-3d681a3809df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4830294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg
_err.4830294
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1977484249
Short name T112
Test name
Test status
Simulation time 900567183 ps
CPU time 39.69 seconds
Started Jun 29 05:34:15 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 218980 kb
Host smart-37a2411f-16d5-4ef3-98ef-555518ea32ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977484249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1977484249
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3476938946
Short name T22
Test name
Test status
Simulation time 1624302567 ps
CPU time 101.37 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:41:28 PM PDT 24
Peak memory 236756 kb
Host smart-4b20f42f-f099-406c-9af0-19cde7eef16b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476938946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3476938946
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3614823131
Short name T15
Test name
Test status
Simulation time 9613751901 ps
CPU time 33.65 seconds
Started Jun 29 04:40:19 PM PDT 24
Finished Jun 29 04:40:54 PM PDT 24
Peak memory 213240 kb
Host smart-dbb65564-d06a-4f50-9b70-a0f94b4f9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614823131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3614823131
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3084212401
Short name T12
Test name
Test status
Simulation time 403676319079 ps
CPU time 1258.35 seconds
Started Jun 29 04:40:44 PM PDT 24
Finished Jun 29 05:01:43 PM PDT 24
Peak memory 233456 kb
Host smart-06bba5f0-e5ba-4127-9080-17ea0d67e4b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084212401 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3084212401
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.216136139
Short name T378
Test name
Test status
Simulation time 6999773660 ps
CPU time 14.62 seconds
Started Jun 29 05:34:10 PM PDT 24
Finished Jun 29 05:34:25 PM PDT 24
Peak memory 210800 kb
Host smart-ed6cd84d-929d-4c79-84ea-c9fcfe043d24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216136139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.216136139
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1186768809
Short name T393
Test name
Test status
Simulation time 9161489535 ps
CPU time 15.26 seconds
Started Jun 29 05:34:10 PM PDT 24
Finished Jun 29 05:34:26 PM PDT 24
Peak memory 217608 kb
Host smart-f71ee926-82a2-4564-a01b-8669b8826b2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186768809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1186768809
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.238695185
Short name T458
Test name
Test status
Simulation time 766838783 ps
CPU time 9.71 seconds
Started Jun 29 05:34:15 PM PDT 24
Finished Jun 29 05:34:25 PM PDT 24
Peak memory 210772 kb
Host smart-bfc5cce9-9ce6-4842-a8f7-f74cb1a3c028
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238695185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.238695185
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.810668290
Short name T449
Test name
Test status
Simulation time 94492776 ps
CPU time 4.87 seconds
Started Jun 29 05:34:15 PM PDT 24
Finished Jun 29 05:34:21 PM PDT 24
Peak memory 213448 kb
Host smart-b729f2b5-8448-45b6-8231-83b220b5e851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810668290 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.810668290
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.168390830
Short name T386
Test name
Test status
Simulation time 1794822509 ps
CPU time 14.75 seconds
Started Jun 29 05:34:16 PM PDT 24
Finished Jun 29 05:34:31 PM PDT 24
Peak memory 218912 kb
Host smart-a97c9043-183b-47b5-8d2a-a33fa46ccca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168390830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.168390830
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2541877457
Short name T403
Test name
Test status
Simulation time 7483468928 ps
CPU time 15.27 seconds
Started Jun 29 05:34:15 PM PDT 24
Finished Jun 29 05:34:30 PM PDT 24
Peak memory 210576 kb
Host smart-ae698e0d-d83d-4824-adf7-768f73de75e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541877457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2541877457
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3742120454
Short name T407
Test name
Test status
Simulation time 4345213111 ps
CPU time 17.34 seconds
Started Jun 29 05:34:18 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 210676 kb
Host smart-0f047616-c394-4fd0-8d5d-1290348efb9c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742120454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3742120454
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2130181282
Short name T445
Test name
Test status
Simulation time 4488032039 ps
CPU time 45.47 seconds
Started Jun 29 05:34:17 PM PDT 24
Finished Jun 29 05:35:03 PM PDT 24
Peak memory 210852 kb
Host smart-979f1fd2-5751-487f-bf9d-fda7afc5c84e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130181282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2130181282
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.803976616
Short name T460
Test name
Test status
Simulation time 2875711257 ps
CPU time 13.03 seconds
Started Jun 29 05:34:09 PM PDT 24
Finished Jun 29 05:34:23 PM PDT 24
Peak memory 210820 kb
Host smart-08cf83a2-77c0-46d7-aebe-aa61d5f45d1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803976616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.803976616
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.582148168
Short name T424
Test name
Test status
Simulation time 6836405285 ps
CPU time 17.43 seconds
Started Jun 29 05:34:14 PM PDT 24
Finished Jun 29 05:34:32 PM PDT 24
Peak memory 219080 kb
Host smart-bb6243e8-1574-436c-8778-51fbe73a43fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582148168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.582148168
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1133773575
Short name T417
Test name
Test status
Simulation time 2842188615 ps
CPU time 12.96 seconds
Started Jun 29 05:34:24 PM PDT 24
Finished Jun 29 05:34:38 PM PDT 24
Peak memory 210836 kb
Host smart-ace6c90a-3dc6-48f1-94e8-8d85cbe4eaf8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133773575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1133773575
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.364136008
Short name T425
Test name
Test status
Simulation time 8986475168 ps
CPU time 15.69 seconds
Started Jun 29 05:34:16 PM PDT 24
Finished Jun 29 05:34:32 PM PDT 24
Peak memory 218964 kb
Host smart-bddcb345-acc7-4ee0-8456-a809f7fb0105
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364136008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.364136008
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.458603552
Short name T428
Test name
Test status
Simulation time 1642960999 ps
CPU time 15.15 seconds
Started Jun 29 05:34:11 PM PDT 24
Finished Jun 29 05:34:27 PM PDT 24
Peak memory 210772 kb
Host smart-399fe7e8-562a-4bbf-ba10-70cd6a4be593
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458603552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.458603552
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2608377354
Short name T446
Test name
Test status
Simulation time 6853663561 ps
CPU time 14.53 seconds
Started Jun 29 05:34:14 PM PDT 24
Finished Jun 29 05:34:29 PM PDT 24
Peak memory 219132 kb
Host smart-2463458e-4696-4335-957c-8456d054c61e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608377354 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2608377354
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2503565343
Short name T90
Test name
Test status
Simulation time 98878262 ps
CPU time 4.38 seconds
Started Jun 29 05:34:16 PM PDT 24
Finished Jun 29 05:34:21 PM PDT 24
Peak memory 217776 kb
Host smart-f6a12d5b-26f0-455c-8be3-e2dc557d9420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503565343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2503565343
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.588048476
Short name T448
Test name
Test status
Simulation time 12783513698 ps
CPU time 11.53 seconds
Started Jun 29 05:34:17 PM PDT 24
Finished Jun 29 05:34:29 PM PDT 24
Peak memory 210676 kb
Host smart-bc986661-e8c4-41f6-9ffb-87d9a45f4fb1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588048476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.588048476
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1015754384
Short name T436
Test name
Test status
Simulation time 1277102774 ps
CPU time 12.07 seconds
Started Jun 29 05:34:15 PM PDT 24
Finished Jun 29 05:34:27 PM PDT 24
Peak memory 210512 kb
Host smart-3b3e6096-31d0-4f0f-978d-035cedea5067
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015754384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1015754384
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.461549068
Short name T464
Test name
Test status
Simulation time 11048090858 ps
CPU time 15.45 seconds
Started Jun 29 05:34:08 PM PDT 24
Finished Jun 29 05:34:24 PM PDT 24
Peak memory 211116 kb
Host smart-445caa09-83b3-4bbf-9b78-b8db8accbab7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461549068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.461549068
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1927475344
Short name T369
Test name
Test status
Simulation time 820468276 ps
CPU time 8.19 seconds
Started Jun 29 05:34:10 PM PDT 24
Finished Jun 29 05:34:19 PM PDT 24
Peak memory 218952 kb
Host smart-1039fb60-46fa-47bc-bb1d-ecc0d2104f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927475344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1927475344
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.725286409
Short name T64
Test name
Test status
Simulation time 734006950 ps
CPU time 40.22 seconds
Started Jun 29 05:34:06 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 218508 kb
Host smart-dac66c1e-b624-442b-9639-797f46aba1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725286409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.725286409
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.986291224
Short name T409
Test name
Test status
Simulation time 6683415562 ps
CPU time 12.05 seconds
Started Jun 29 05:34:19 PM PDT 24
Finished Jun 29 05:34:31 PM PDT 24
Peak memory 214000 kb
Host smart-94ab0332-ba67-404d-8457-fff19970ff8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986291224 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.986291224
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1008715041
Short name T69
Test name
Test status
Simulation time 2791893119 ps
CPU time 8.45 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 210772 kb
Host smart-f56f4586-ec84-49fe-833d-13f659f4ed7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008715041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1008715041
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3889699978
Short name T65
Test name
Test status
Simulation time 5130205070 ps
CPU time 41.53 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:35:07 PM PDT 24
Peak memory 210668 kb
Host smart-6dad137b-7a50-4150-a2f2-eeede1b4e220
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889699978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3889699978
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1992924714
Short name T419
Test name
Test status
Simulation time 1123729407 ps
CPU time 11.43 seconds
Started Jun 29 05:34:22 PM PDT 24
Finished Jun 29 05:34:34 PM PDT 24
Peak memory 218932 kb
Host smart-6b949ee5-7b73-4a3d-8fa7-893cbc72a42c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992924714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1992924714
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4126884200
Short name T400
Test name
Test status
Simulation time 6175666698 ps
CPU time 17.34 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:41 PM PDT 24
Peak memory 219028 kb
Host smart-1cedb375-a54a-4571-a25d-72af3e95c2ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126884200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4126884200
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.175699569
Short name T114
Test name
Test status
Simulation time 2156046000 ps
CPU time 79.41 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:35:47 PM PDT 24
Peak memory 219044 kb
Host smart-804e460e-a002-4196-8f22-23334c1e4544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175699569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.175699569
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3788799280
Short name T373
Test name
Test status
Simulation time 1073712010 ps
CPU time 6.88 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:30 PM PDT 24
Peak memory 219068 kb
Host smart-30249c46-4161-41ba-ba95-5d596b5d3337
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788799280 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3788799280
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2295588711
Short name T376
Test name
Test status
Simulation time 89090428 ps
CPU time 4.19 seconds
Started Jun 29 05:34:36 PM PDT 24
Finished Jun 29 05:34:42 PM PDT 24
Peak memory 210712 kb
Host smart-c83751cd-6635-4ba3-8ca0-e516ef5a2687
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295588711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2295588711
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.740361227
Short name T83
Test name
Test status
Simulation time 10661503185 ps
CPU time 49.39 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:35:14 PM PDT 24
Peak memory 210736 kb
Host smart-6be6849d-dc71-4227-8fc9-76ac3563f283
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740361227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.740361227
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3823744923
Short name T75
Test name
Test status
Simulation time 136967745 ps
CPU time 6.74 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:33 PM PDT 24
Peak memory 210828 kb
Host smart-a12d898b-43e1-4d9a-bcf8-eeb50a5a140b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823744923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3823744923
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3230447447
Short name T465
Test name
Test status
Simulation time 7469221118 ps
CPU time 17.88 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 219080 kb
Host smart-292270bc-548d-43c8-9e99-2d886dcfec5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230447447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3230447447
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2109474348
Short name T435
Test name
Test status
Simulation time 1087778391 ps
CPU time 11.39 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:38 PM PDT 24
Peak memory 218872 kb
Host smart-37ea0959-c425-46a4-bebd-2c154f15f84f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109474348 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2109474348
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.809783157
Short name T395
Test name
Test status
Simulation time 8701047659 ps
CPU time 15.34 seconds
Started Jun 29 05:34:32 PM PDT 24
Finished Jun 29 05:34:48 PM PDT 24
Peak memory 210776 kb
Host smart-1db9c5c0-a2ff-4240-a406-3f4222d7b1c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809783157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.809783157
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1257158505
Short name T71
Test name
Test status
Simulation time 2185196325 ps
CPU time 27.98 seconds
Started Jun 29 05:34:22 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 210776 kb
Host smart-37d39ce5-2031-4810-843e-f4d57b60495b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257158505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1257158505
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3108480431
Short name T433
Test name
Test status
Simulation time 2797137190 ps
CPU time 14.74 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:42 PM PDT 24
Peak memory 210912 kb
Host smart-7b875f34-b0d1-4bb0-8e1b-67d5ffb08040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108480431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3108480431
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2568979711
Short name T447
Test name
Test status
Simulation time 2215885969 ps
CPU time 11.48 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:38 PM PDT 24
Peak memory 219080 kb
Host smart-76b70b13-290b-4e63-b33a-03ec1ea63a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568979711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2568979711
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2727497852
Short name T388
Test name
Test status
Simulation time 2466925856 ps
CPU time 9.01 seconds
Started Jun 29 05:34:33 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 219100 kb
Host smart-c21ef8e5-6e98-41e4-b7a4-a7a72002f8cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727497852 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2727497852
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.374846979
Short name T379
Test name
Test status
Simulation time 6171674795 ps
CPU time 7.96 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 218904 kb
Host smart-967aff0b-0b39-471c-aece-7d2c77b044ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374846979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.374846979
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2218330452
Short name T455
Test name
Test status
Simulation time 1964574852 ps
CPU time 7.57 seconds
Started Jun 29 05:34:34 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 210840 kb
Host smart-10f8fe61-c5b4-4424-a831-4a838a91c537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218330452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2218330452
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1359506390
Short name T398
Test name
Test status
Simulation time 89285693 ps
CPU time 6.45 seconds
Started Jun 29 05:34:27 PM PDT 24
Finished Jun 29 05:34:34 PM PDT 24
Peak memory 218980 kb
Host smart-d47f5b0d-ce0a-4b2c-8c5a-9cf4ff3d429d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359506390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1359506390
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3518402424
Short name T118
Test name
Test status
Simulation time 4891656941 ps
CPU time 42.94 seconds
Started Jun 29 05:34:24 PM PDT 24
Finished Jun 29 05:35:08 PM PDT 24
Peak memory 218952 kb
Host smart-7e26d27d-13a5-45b5-96d8-23bb93891739
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518402424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3518402424
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.756119895
Short name T405
Test name
Test status
Simulation time 269083107 ps
CPU time 5.56 seconds
Started Jun 29 05:34:35 PM PDT 24
Finished Jun 29 05:34:41 PM PDT 24
Peak memory 218924 kb
Host smart-69f05cb3-de8b-458a-adcd-08552700dc0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756119895 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.756119895
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1127887353
Short name T413
Test name
Test status
Simulation time 89151125 ps
CPU time 4.26 seconds
Started Jun 29 05:34:30 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 217744 kb
Host smart-9cb0896f-825e-4ec7-9ac6-ecd1f84db1da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127887353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1127887353
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2761139569
Short name T450
Test name
Test status
Simulation time 5336013776 ps
CPU time 25.8 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:52 PM PDT 24
Peak memory 210844 kb
Host smart-d1bacf7c-8dc4-4f33-a5e8-a6fab8dadba7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761139569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2761139569
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3101026011
Short name T66
Test name
Test status
Simulation time 397656957 ps
CPU time 8.61 seconds
Started Jun 29 05:34:37 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 210840 kb
Host smart-64ba4240-6b81-404d-ab53-3ad4c5ef1817
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101026011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3101026011
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2088909524
Short name T382
Test name
Test status
Simulation time 3775786770 ps
CPU time 14.64 seconds
Started Jun 29 05:34:29 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 219080 kb
Host smart-687ad541-a984-4d33-b73f-ad198de142a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088909524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2088909524
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2347112941
Short name T457
Test name
Test status
Simulation time 8354216804 ps
CPU time 80.28 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:35:50 PM PDT 24
Peak memory 211464 kb
Host smart-90e9e4ea-61e4-4868-89f8-fd150ad6231a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347112941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2347112941
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.679755248
Short name T421
Test name
Test status
Simulation time 1505069221 ps
CPU time 14.22 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 219060 kb
Host smart-9e6502c2-ef85-427c-adce-0f8e9e758108
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679755248 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.679755248
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1428787313
Short name T375
Test name
Test status
Simulation time 2119807540 ps
CPU time 15.54 seconds
Started Jun 29 05:34:27 PM PDT 24
Finished Jun 29 05:34:44 PM PDT 24
Peak memory 218336 kb
Host smart-da10c921-b18a-4327-9a05-6ad15fd5e88a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428787313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1428787313
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2775575374
Short name T86
Test name
Test status
Simulation time 85922840313 ps
CPU time 79.08 seconds
Started Jun 29 05:34:31 PM PDT 24
Finished Jun 29 05:35:50 PM PDT 24
Peak memory 210844 kb
Host smart-ff9bee1a-4d01-405e-8db0-0905f806bb88
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775575374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2775575374
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3196176677
Short name T440
Test name
Test status
Simulation time 1789997539 ps
CPU time 13.66 seconds
Started Jun 29 05:34:30 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 218964 kb
Host smart-76ba530b-7259-433e-870d-954f023669c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196176677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3196176677
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4135441095
Short name T371
Test name
Test status
Simulation time 2093242018 ps
CPU time 17.79 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:35:07 PM PDT 24
Peak memory 219016 kb
Host smart-a3ffbac4-cabb-4651-8105-33ef10c74c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135441095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4135441095
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.47195678
Short name T62
Test name
Test status
Simulation time 3725494905 ps
CPU time 40.67 seconds
Started Jun 29 05:34:30 PM PDT 24
Finished Jun 29 05:35:12 PM PDT 24
Peak memory 219052 kb
Host smart-faedbf63-31df-4dc6-b280-e8189c2fee6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47195678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_int
g_err.47195678
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2790518418
Short name T408
Test name
Test status
Simulation time 111241928 ps
CPU time 5.31 seconds
Started Jun 29 05:34:42 PM PDT 24
Finished Jun 29 05:34:48 PM PDT 24
Peak memory 219036 kb
Host smart-07c026f1-e74c-406f-b9d2-60082a6ba4bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790518418 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2790518418
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.809665743
Short name T380
Test name
Test status
Simulation time 1652524606 ps
CPU time 4.32 seconds
Started Jun 29 05:34:29 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 217744 kb
Host smart-8096cabb-265c-4cad-9e7a-8fe895114e06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809665743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.809665743
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.292349162
Short name T80
Test name
Test status
Simulation time 44505191721 ps
CPU time 53.09 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:35:20 PM PDT 24
Peak memory 210848 kb
Host smart-16bc746f-570a-4ccc-96d5-62050c7ddfe1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292349162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.292349162
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1771080736
Short name T411
Test name
Test status
Simulation time 18945149215 ps
CPU time 16.59 seconds
Started Jun 29 05:34:30 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 218944 kb
Host smart-d0ebd6fa-af91-4c9b-9108-badbbe2f463e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771080736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1771080736
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3109168718
Short name T391
Test name
Test status
Simulation time 984895610 ps
CPU time 10.21 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:34:40 PM PDT 24
Peak memory 218964 kb
Host smart-343ce0c1-dd11-4bc7-87ca-f422d4005015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109168718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3109168718
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2323394865
Short name T414
Test name
Test status
Simulation time 1711987752 ps
CPU time 45.36 seconds
Started Jun 29 05:34:33 PM PDT 24
Finished Jun 29 05:35:19 PM PDT 24
Peak memory 219008 kb
Host smart-20e44749-8f51-42f1-b2de-34d073ae3254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323394865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2323394865
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.784514530
Short name T368
Test name
Test status
Simulation time 5314414177 ps
CPU time 8.67 seconds
Started Jun 29 05:34:34 PM PDT 24
Finished Jun 29 05:34:44 PM PDT 24
Peak memory 214720 kb
Host smart-c64a4f1b-f2e4-4226-9d4c-7ba40c20fa5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784514530 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.784514530
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.630320483
Short name T73
Test name
Test status
Simulation time 3677964095 ps
CPU time 15.29 seconds
Started Jun 29 05:34:30 PM PDT 24
Finished Jun 29 05:34:46 PM PDT 24
Peak memory 218704 kb
Host smart-0797c3d5-5a95-49cb-929a-f6fe4f3a5f92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630320483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.630320483
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3513291734
Short name T420
Test name
Test status
Simulation time 1557993185 ps
CPU time 38.05 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:35:07 PM PDT 24
Peak memory 210776 kb
Host smart-3d012ce9-3afd-44e2-97d9-384ce8a35c77
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513291734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3513291734
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2217076966
Short name T72
Test name
Test status
Simulation time 2583646809 ps
CPU time 8.03 seconds
Started Jun 29 05:34:33 PM PDT 24
Finished Jun 29 05:34:42 PM PDT 24
Peak memory 210904 kb
Host smart-e37b3c30-666c-42f2-a09b-f0ed3e26b568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217076966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2217076966
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1405978742
Short name T365
Test name
Test status
Simulation time 3447975474 ps
CPU time 13.37 seconds
Started Jun 29 05:34:37 PM PDT 24
Finished Jun 29 05:34:52 PM PDT 24
Peak memory 219076 kb
Host smart-93ea8fe5-619f-4d6d-ad4f-9d2c3049965f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405978742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1405978742
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2904532772
Short name T115
Test name
Test status
Simulation time 8519962190 ps
CPU time 78.17 seconds
Started Jun 29 05:34:30 PM PDT 24
Finished Jun 29 05:35:49 PM PDT 24
Peak memory 211608 kb
Host smart-741d9b7a-d5c7-43c9-92ce-bb39011f47fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904532772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2904532772
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2885611121
Short name T437
Test name
Test status
Simulation time 22923624866 ps
CPU time 15.65 seconds
Started Jun 29 05:34:34 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 219064 kb
Host smart-58fe95de-c662-431b-af54-029d7e602304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885611121 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2885611121
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.903812092
Short name T85
Test name
Test status
Simulation time 7880160217 ps
CPU time 15.92 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 218876 kb
Host smart-99d865f6-2d55-47b1-81b7-20a25abab687
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903812092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.903812092
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4084019138
Short name T82
Test name
Test status
Simulation time 37307874678 ps
CPU time 67 seconds
Started Jun 29 05:34:41 PM PDT 24
Finished Jun 29 05:35:49 PM PDT 24
Peak memory 210776 kb
Host smart-18271d7a-7b6b-4971-b03c-fb6a1615e90a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084019138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4084019138
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3688478983
Short name T394
Test name
Test status
Simulation time 175614294 ps
CPU time 4.58 seconds
Started Jun 29 05:34:46 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 218504 kb
Host smart-e75b39ae-7814-4e60-ba01-9746b0734bb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688478983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3688478983
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3434870552
Short name T366
Test name
Test status
Simulation time 2009800289 ps
CPU time 20.43 seconds
Started Jun 29 05:34:35 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 218968 kb
Host smart-228809ed-a256-4b89-8987-8266558cb1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434870552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3434870552
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2387218286
Short name T63
Test name
Test status
Simulation time 2730497610 ps
CPU time 40.32 seconds
Started Jun 29 05:34:32 PM PDT 24
Finished Jun 29 05:35:13 PM PDT 24
Peak memory 211896 kb
Host smart-7cd2bea2-a62d-4ab3-8589-db4e892c68c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387218286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2387218286
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3775235710
Short name T396
Test name
Test status
Simulation time 2243452330 ps
CPU time 17.02 seconds
Started Jun 29 05:34:29 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 219108 kb
Host smart-13f0aec6-ff54-48c4-98af-1b22ba228245
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775235710 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3775235710
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.964215958
Short name T79
Test name
Test status
Simulation time 10170305518 ps
CPU time 13.68 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:41 PM PDT 24
Peak memory 210840 kb
Host smart-1978176b-ce88-445d-bb45-1b4dbf713533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964215958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.964215958
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3407463680
Short name T84
Test name
Test status
Simulation time 39845519628 ps
CPU time 66.8 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:35:35 PM PDT 24
Peak memory 210776 kb
Host smart-c239b318-4317-4e6d-8b75-091f10c29de9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407463680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3407463680
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4153913997
Short name T429
Test name
Test status
Simulation time 6642857145 ps
CPU time 14.01 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:34:44 PM PDT 24
Peak memory 218968 kb
Host smart-1c9f8015-18a4-4143-a32e-ef4669115a2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153913997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4153913997
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.212573329
Short name T387
Test name
Test status
Simulation time 5940192375 ps
CPU time 17.48 seconds
Started Jun 29 05:34:41 PM PDT 24
Finished Jun 29 05:35:00 PM PDT 24
Peak memory 219080 kb
Host smart-c0bb66bb-e6ee-4bb8-aa1d-858de3cf53f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212573329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.212573329
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3245930351
Short name T107
Test name
Test status
Simulation time 9180575801 ps
CPU time 44.03 seconds
Started Jun 29 05:34:34 PM PDT 24
Finished Jun 29 05:35:20 PM PDT 24
Peak memory 212020 kb
Host smart-5da9ccff-31f9-4547-87f9-ac2e79e5740e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245930351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3245930351
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4290311556
Short name T374
Test name
Test status
Simulation time 333771605 ps
CPU time 4.45 seconds
Started Jun 29 05:34:30 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 210708 kb
Host smart-57d1b51a-37e6-4e82-bdb8-fb671de4f92d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290311556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4290311556
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3008290711
Short name T397
Test name
Test status
Simulation time 1201862201 ps
CPU time 11.91 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 210728 kb
Host smart-2ce83676-73b8-45aa-9ff2-23e7164ac4dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008290711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3008290711
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1587781803
Short name T384
Test name
Test status
Simulation time 1475647902 ps
CPU time 14.49 seconds
Started Jun 29 05:34:22 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 210680 kb
Host smart-bad31c7a-0f33-4901-bdb9-0608e9cfdb9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587781803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1587781803
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.39980073
Short name T416
Test name
Test status
Simulation time 210588584 ps
CPU time 5.29 seconds
Started Jun 29 05:34:24 PM PDT 24
Finished Jun 29 05:34:31 PM PDT 24
Peak memory 219044 kb
Host smart-1f5deda3-9769-4d63-8e0c-1835b66a741b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39980073 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.39980073
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1720428352
Short name T81
Test name
Test status
Simulation time 89200709 ps
CPU time 4.24 seconds
Started Jun 29 05:34:21 PM PDT 24
Finished Jun 29 05:34:26 PM PDT 24
Peak memory 210776 kb
Host smart-2c27a43c-2b77-478f-bf8b-692334244cc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720428352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1720428352
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.942783599
Short name T441
Test name
Test status
Simulation time 8059356356 ps
CPU time 16.64 seconds
Started Jun 29 05:34:22 PM PDT 24
Finished Jun 29 05:34:40 PM PDT 24
Peak memory 210668 kb
Host smart-617fa7bd-13ff-4756-9f20-4f3057082d51
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942783599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.942783599
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1143612163
Short name T454
Test name
Test status
Simulation time 346245025 ps
CPU time 4.1 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:28 PM PDT 24
Peak memory 210484 kb
Host smart-770ef118-2868-44d6-a203-713f9ba0e141
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143612163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1143612163
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4278586844
Short name T434
Test name
Test status
Simulation time 3041846337 ps
CPU time 39.63 seconds
Started Jun 29 05:34:11 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 210844 kb
Host smart-404dbaa7-8b84-48e8-b90e-c0c002f97368
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278586844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4278586844
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3443035366
Short name T439
Test name
Test status
Simulation time 248481013 ps
CPU time 6.28 seconds
Started Jun 29 05:34:18 PM PDT 24
Finished Jun 29 05:34:25 PM PDT 24
Peak memory 210836 kb
Host smart-2b598f5f-85de-465b-bede-e8e73fc075f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443035366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3443035366
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1766407677
Short name T412
Test name
Test status
Simulation time 105561201 ps
CPU time 8.88 seconds
Started Jun 29 05:34:11 PM PDT 24
Finished Jun 29 05:34:20 PM PDT 24
Peak memory 219008 kb
Host smart-6b40742b-39c0-42bb-b4c4-e1e4c57ad5de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766407677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1766407677
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1246701167
Short name T67
Test name
Test status
Simulation time 1643695411 ps
CPU time 7.52 seconds
Started Jun 29 05:34:19 PM PDT 24
Finished Jun 29 05:34:27 PM PDT 24
Peak memory 218488 kb
Host smart-1e430bcc-f4f7-4d1e-a60b-c5ee5cb5b1b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246701167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1246701167
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.355999743
Short name T377
Test name
Test status
Simulation time 2126849724 ps
CPU time 16.76 seconds
Started Jun 29 05:34:21 PM PDT 24
Finished Jun 29 05:34:38 PM PDT 24
Peak memory 210772 kb
Host smart-f6efef74-36a1-49ec-be81-24b52266a8ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355999743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.355999743
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3398748946
Short name T70
Test name
Test status
Simulation time 7679579670 ps
CPU time 18.35 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 218888 kb
Host smart-79fac78a-809b-4517-b103-59cc352479c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398748946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3398748946
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3654816099
Short name T427
Test name
Test status
Simulation time 5137887923 ps
CPU time 9.21 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 219008 kb
Host smart-fa6a3b3d-2e40-471b-b8bb-f177f565e135
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654816099 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3654816099
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1828240312
Short name T89
Test name
Test status
Simulation time 3724974690 ps
CPU time 11.12 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 218968 kb
Host smart-8b2a72b7-7bd3-4c31-b5ec-eefb73fce752
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828240312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1828240312
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2070513417
Short name T443
Test name
Test status
Simulation time 992759939 ps
CPU time 10.32 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 210644 kb
Host smart-3fff0bdb-3d7e-4061-a075-a4809dd2950c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070513417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2070513417
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4140573639
Short name T372
Test name
Test status
Simulation time 677785541 ps
CPU time 8.14 seconds
Started Jun 29 05:34:27 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 210612 kb
Host smart-74670a9e-00c3-45f0-893e-302dd812829d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140573639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4140573639
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3237163463
Short name T88
Test name
Test status
Simulation time 1092765401 ps
CPU time 18.73 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:46 PM PDT 24
Peak memory 210680 kb
Host smart-cfcc3623-0d80-47ac-873e-cac8ccb5ae06
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237163463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3237163463
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2138331855
Short name T461
Test name
Test status
Simulation time 3532699595 ps
CPU time 15.1 seconds
Started Jun 29 05:34:27 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 219004 kb
Host smart-26dce982-f8c9-48a5-adf2-81b03c83ccea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138331855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2138331855
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.227593510
Short name T367
Test name
Test status
Simulation time 1132428975 ps
CPU time 16.1 seconds
Started Jun 29 05:34:20 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 219012 kb
Host smart-037ec4bb-5339-4972-b61b-9c542d8efa8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227593510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.227593510
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2394032245
Short name T117
Test name
Test status
Simulation time 1868453930 ps
CPU time 79.38 seconds
Started Jun 29 05:34:29 PM PDT 24
Finished Jun 29 05:35:50 PM PDT 24
Peak memory 219008 kb
Host smart-ac71d55c-f484-4001-b102-8c29e6887c75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394032245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2394032245
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2027570640
Short name T438
Test name
Test status
Simulation time 663211466 ps
CPU time 5.36 seconds
Started Jun 29 05:34:24 PM PDT 24
Finished Jun 29 05:34:31 PM PDT 24
Peak memory 210632 kb
Host smart-b78feab3-0195-443d-a60b-ed6cae3682e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027570640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2027570640
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3723832277
Short name T404
Test name
Test status
Simulation time 434407099 ps
CPU time 6.24 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:30 PM PDT 24
Peak memory 210772 kb
Host smart-7c7a8488-9c27-4f4c-ba1e-a8084ce26266
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723832277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3723832277
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2898847685
Short name T74
Test name
Test status
Simulation time 4160318024 ps
CPU time 13.31 seconds
Started Jun 29 05:34:24 PM PDT 24
Finished Jun 29 05:34:38 PM PDT 24
Peak memory 218644 kb
Host smart-7c1798ee-b5be-44ee-9666-5b31008967df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898847685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2898847685
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1560256148
Short name T462
Test name
Test status
Simulation time 3090233729 ps
CPU time 14.02 seconds
Started Jun 29 05:34:24 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 219052 kb
Host smart-08b0f496-cd8c-4826-b580-2ceed88b4658
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560256148 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1560256148
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.4037405618
Short name T389
Test name
Test status
Simulation time 179063891 ps
CPU time 4.34 seconds
Started Jun 29 05:34:20 PM PDT 24
Finished Jun 29 05:34:25 PM PDT 24
Peak memory 210680 kb
Host smart-e524acd1-2935-4df8-89c1-a65a48f72536
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037405618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.4037405618
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1988033971
Short name T422
Test name
Test status
Simulation time 2463072561 ps
CPU time 14.69 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:38 PM PDT 24
Peak memory 210708 kb
Host smart-d2f7e7ec-1dc9-475b-b231-0903f77c28a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988033971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1988033971
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.562613260
Short name T415
Test name
Test status
Simulation time 2928792725 ps
CPU time 8.92 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:33 PM PDT 24
Peak memory 210668 kb
Host smart-302332c3-bbcb-4881-98a5-c0a7c4d7c9cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562613260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
562613260
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3762927740
Short name T410
Test name
Test status
Simulation time 33928736370 ps
CPU time 74.23 seconds
Started Jun 29 05:34:27 PM PDT 24
Finished Jun 29 05:35:42 PM PDT 24
Peak memory 210844 kb
Host smart-97bca3e7-48a0-4c56-8149-b5fb39e21bb7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762927740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3762927740
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2007451942
Short name T444
Test name
Test status
Simulation time 89190570 ps
CPU time 4.54 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:31 PM PDT 24
Peak memory 210808 kb
Host smart-81af8654-ea76-417a-860d-976348c5d2d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007451942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2007451942
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3764285108
Short name T385
Test name
Test status
Simulation time 650887934 ps
CPU time 10.31 seconds
Started Jun 29 05:34:22 PM PDT 24
Finished Jun 29 05:34:33 PM PDT 24
Peak memory 218964 kb
Host smart-78f2e8b1-2ee1-40f7-a2d6-1a92686a3e29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764285108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3764285108
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.492585164
Short name T104
Test name
Test status
Simulation time 2060542971 ps
CPU time 47.99 seconds
Started Jun 29 05:34:22 PM PDT 24
Finished Jun 29 05:35:11 PM PDT 24
Peak memory 219012 kb
Host smart-197909db-2eb2-4913-b21d-ea8809dd566b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492585164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.492585164
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3354551208
Short name T463
Test name
Test status
Simulation time 1008978975 ps
CPU time 7.53 seconds
Started Jun 29 05:34:36 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 218924 kb
Host smart-0ba356ab-dcbe-4fdf-bf7f-4f4627a281e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354551208 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3354551208
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2704627895
Short name T101
Test name
Test status
Simulation time 1957440223 ps
CPU time 15.34 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 210688 kb
Host smart-d295870a-a1b2-4594-b529-0a219f30cdd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704627895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2704627895
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1911784179
Short name T87
Test name
Test status
Simulation time 8664992767 ps
CPU time 75.75 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:35:39 PM PDT 24
Peak memory 210812 kb
Host smart-24c20bee-e36e-4038-8bba-b851291a12df
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911784179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1911784179
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.4194500003
Short name T431
Test name
Test status
Simulation time 1663454460 ps
CPU time 13.41 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:41 PM PDT 24
Peak memory 210776 kb
Host smart-259b5b52-630f-4af4-98c7-c538562e167c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194500003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.4194500003
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1369802037
Short name T452
Test name
Test status
Simulation time 2179766787 ps
CPU time 10.21 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 219076 kb
Host smart-0c18b270-c958-49e1-90a2-162b60e38c67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369802037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1369802037
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1842193853
Short name T110
Test name
Test status
Simulation time 32593054096 ps
CPU time 45.72 seconds
Started Jun 29 05:34:22 PM PDT 24
Finished Jun 29 05:35:08 PM PDT 24
Peak memory 219044 kb
Host smart-5d07d32f-00c3-4cdc-abeb-6a8de831d7c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842193853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1842193853
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.463156137
Short name T401
Test name
Test status
Simulation time 108838953 ps
CPU time 5.13 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:33 PM PDT 24
Peak memory 218976 kb
Host smart-d8380263-6939-43c8-99e1-51b958560b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463156137 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.463156137
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3005212086
Short name T392
Test name
Test status
Simulation time 3980730256 ps
CPU time 10.43 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 210776 kb
Host smart-51ba4ef4-99e4-4f1c-8f89-50e1d9fb13f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005212086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3005212086
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2164492749
Short name T402
Test name
Test status
Simulation time 367161717 ps
CPU time 18.79 seconds
Started Jun 29 05:34:24 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 210780 kb
Host smart-8e9b1aef-8012-49ff-b3bf-b49e76212105
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164492749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2164492749
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2605807628
Short name T451
Test name
Test status
Simulation time 10439513160 ps
CPU time 15.87 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:42 PM PDT 24
Peak memory 210976 kb
Host smart-0f31b41e-7a4f-4e27-b967-089d2736e44d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605807628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2605807628
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1312960529
Short name T430
Test name
Test status
Simulation time 569478751 ps
CPU time 10.31 seconds
Started Jun 29 05:34:24 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 216576 kb
Host smart-01bf0230-ba8f-411b-a87b-2e242f7e6bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312960529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1312960529
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.208345155
Short name T106
Test name
Test status
Simulation time 298253325 ps
CPU time 39.21 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:35:04 PM PDT 24
Peak memory 212184 kb
Host smart-3e1af32d-ef3f-4c9f-a4e9-9da0c2a35aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208345155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.208345155
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2765789165
Short name T423
Test name
Test status
Simulation time 2264519539 ps
CPU time 8.23 seconds
Started Jun 29 05:34:20 PM PDT 24
Finished Jun 29 05:34:29 PM PDT 24
Peak memory 219064 kb
Host smart-9d5aaaa5-690c-4386-a035-c0b48cf24269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765789165 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2765789165
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1079479478
Short name T426
Test name
Test status
Simulation time 7167043601 ps
CPU time 16.15 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 218876 kb
Host smart-46af3cec-4572-4f6f-bc03-663b98a039b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079479478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1079479478
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.578847125
Short name T406
Test name
Test status
Simulation time 36406321341 ps
CPU time 79.42 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:35:48 PM PDT 24
Peak memory 210860 kb
Host smart-c0b68762-fe27-406c-9e36-1a1c12f93880
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578847125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.578847125
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3358069295
Short name T399
Test name
Test status
Simulation time 2170631933 ps
CPU time 16.68 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:44 PM PDT 24
Peak memory 211100 kb
Host smart-6b92b3aa-e2c1-4a80-80ff-68955f4e49c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358069295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3358069295
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2499396928
Short name T390
Test name
Test status
Simulation time 2874911308 ps
CPU time 14.69 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 219076 kb
Host smart-7d5e6943-31cf-4e80-a82c-0185cd07198d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499396928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2499396928
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1325873569
Short name T105
Test name
Test status
Simulation time 14851734716 ps
CPU time 75.31 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:35:42 PM PDT 24
Peak memory 212416 kb
Host smart-3600568a-0a2f-454c-a1db-4a997af9039b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325873569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1325873569
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.132823163
Short name T453
Test name
Test status
Simulation time 7479258168 ps
CPU time 15.83 seconds
Started Jun 29 05:34:36 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 219084 kb
Host smart-42163b04-c6a6-4ed9-b132-c25c59c62459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132823163 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.132823163
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3343510693
Short name T456
Test name
Test status
Simulation time 1210716070 ps
CPU time 11.4 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:38 PM PDT 24
Peak memory 210776 kb
Host smart-054b2ff5-6b3b-42fc-b663-5c6eb5bdeaab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343510693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3343510693
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4047547257
Short name T442
Test name
Test status
Simulation time 25573585016 ps
CPU time 98.14 seconds
Started Jun 29 05:34:22 PM PDT 24
Finished Jun 29 05:36:00 PM PDT 24
Peak memory 217920 kb
Host smart-08433822-a5a5-47f6-a71f-85833c8eb57b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047547257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4047547257
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1137166933
Short name T432
Test name
Test status
Simulation time 5937662211 ps
CPU time 13.06 seconds
Started Jun 29 05:34:21 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 211108 kb
Host smart-1ee9a1d8-a237-4094-bc86-5d46f27b1b78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137166933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1137166933
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.732930706
Short name T459
Test name
Test status
Simulation time 5028341793 ps
CPU time 18.23 seconds
Started Jun 29 05:34:32 PM PDT 24
Finished Jun 29 05:34:50 PM PDT 24
Peak memory 219076 kb
Host smart-516dabbf-04c2-4a74-a9b4-ccb40eb32089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732930706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.732930706
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1230821743
Short name T383
Test name
Test status
Simulation time 1533626502 ps
CPU time 14.33 seconds
Started Jun 29 05:34:22 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 219068 kb
Host smart-79676d74-e597-4969-967c-13a8a030ee8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230821743 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1230821743
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3824245894
Short name T418
Test name
Test status
Simulation time 2040184348 ps
CPU time 15.35 seconds
Started Jun 29 05:34:25 PM PDT 24
Finished Jun 29 05:34:41 PM PDT 24
Peak memory 210704 kb
Host smart-b334b237-ded3-4000-9f48-558afc98efbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824245894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3824245894
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2805084874
Short name T381
Test name
Test status
Simulation time 741985022 ps
CPU time 19.23 seconds
Started Jun 29 05:34:27 PM PDT 24
Finished Jun 29 05:34:48 PM PDT 24
Peak memory 210780 kb
Host smart-dad07f4e-ccfa-463f-be94-3df92c4c60e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805084874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2805084874
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1090315041
Short name T102
Test name
Test status
Simulation time 347723875 ps
CPU time 4.49 seconds
Started Jun 29 05:34:23 PM PDT 24
Finished Jun 29 05:34:29 PM PDT 24
Peak memory 218500 kb
Host smart-d796e9db-ab18-4c97-a04d-0dc47cc71d2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090315041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1090315041
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.819766325
Short name T370
Test name
Test status
Simulation time 7796209504 ps
CPU time 20.86 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:48 PM PDT 24
Peak memory 219052 kb
Host smart-ca790e7f-d517-490d-8f46-1fc3b0c9d4c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819766325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.819766325
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.414817166
Short name T113
Test name
Test status
Simulation time 7983819494 ps
CPU time 79.32 seconds
Started Jun 29 05:34:20 PM PDT 24
Finished Jun 29 05:35:40 PM PDT 24
Peak memory 211680 kb
Host smart-dc919ed2-8dc9-4647-8f56-d6f834c5bf98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414817166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.414817166
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.634874137
Short name T150
Test name
Test status
Simulation time 7966685168 ps
CPU time 13.87 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:40:01 PM PDT 24
Peak memory 211276 kb
Host smart-bfca0ce7-6459-4098-a027-4939860d45b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634874137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.634874137
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.699948411
Short name T162
Test name
Test status
Simulation time 17740673404 ps
CPU time 184.95 seconds
Started Jun 29 04:39:40 PM PDT 24
Finished Jun 29 04:42:45 PM PDT 24
Peak memory 228156 kb
Host smart-ebca0fed-5908-4a69-8bc6-4b2256eb7795
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699948411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.699948411
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.336604827
Short name T332
Test name
Test status
Simulation time 12037930568 ps
CPU time 30.85 seconds
Started Jun 29 04:39:49 PM PDT 24
Finished Jun 29 04:40:21 PM PDT 24
Peak memory 212244 kb
Host smart-98798813-b400-44bf-8d2a-5f3e20faee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336604827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.336604827
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.748986663
Short name T277
Test name
Test status
Simulation time 1519232039 ps
CPU time 8.02 seconds
Started Jun 29 04:39:38 PM PDT 24
Finished Jun 29 04:39:47 PM PDT 24
Peak memory 211336 kb
Host smart-cdb96521-7d26-460c-9c8d-3df957f7ceda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748986663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.748986663
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4127103619
Short name T285
Test name
Test status
Simulation time 608302027 ps
CPU time 13.94 seconds
Started Jun 29 04:39:49 PM PDT 24
Finished Jun 29 04:40:04 PM PDT 24
Peak memory 212928 kb
Host smart-57bd54a7-0a11-49ee-a695-f2d49655b9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127103619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4127103619
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.266693243
Short name T361
Test name
Test status
Simulation time 782478492 ps
CPU time 43.75 seconds
Started Jun 29 04:39:49 PM PDT 24
Finished Jun 29 04:40:33 PM PDT 24
Peak memory 216120 kb
Host smart-14185f41-495f-4c07-add9-ff70b9fea9eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266693243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.266693243
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1083800081
Short name T266
Test name
Test status
Simulation time 9532115727 ps
CPU time 110.96 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:41:38 PM PDT 24
Peak memory 212500 kb
Host smart-28e1fb8c-872f-4277-9f87-4fde09b37fe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083800081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1083800081
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1718195216
Short name T95
Test name
Test status
Simulation time 17776948244 ps
CPU time 35.54 seconds
Started Jun 29 04:39:48 PM PDT 24
Finished Jun 29 04:40:24 PM PDT 24
Peak memory 212240 kb
Host smart-c847e54b-6b8b-4004-b73f-367f3a34f0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718195216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1718195216
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3788536595
Short name T297
Test name
Test status
Simulation time 4646518727 ps
CPU time 12.13 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:39:59 PM PDT 24
Peak memory 211396 kb
Host smart-36fdce82-a017-4934-b09d-eafd9cf39af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788536595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3788536595
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3170560012
Short name T258
Test name
Test status
Simulation time 13595313818 ps
CPU time 25.96 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:40:13 PM PDT 24
Peak memory 214176 kb
Host smart-ffed816d-9749-4aac-be34-799501455cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170560012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3170560012
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3315127864
Short name T152
Test name
Test status
Simulation time 38586212584 ps
CPU time 114.02 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:41:41 PM PDT 24
Peak memory 219288 kb
Host smart-dbb5af8b-e1f4-4635-bb5b-35575c83168c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315127864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3315127864
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1917854295
Short name T238
Test name
Test status
Simulation time 1525560356 ps
CPU time 13.13 seconds
Started Jun 29 04:40:04 PM PDT 24
Finished Jun 29 04:40:18 PM PDT 24
Peak memory 211180 kb
Host smart-835ea305-ab2f-47cb-9daa-52203cb9908d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917854295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1917854295
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2232539465
Short name T283
Test name
Test status
Simulation time 39748547020 ps
CPU time 349.4 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:45:54 PM PDT 24
Peak memory 212516 kb
Host smart-d626fbbe-6c48-4d7a-b82f-fa49ec922350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232539465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2232539465
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3233622973
Short name T237
Test name
Test status
Simulation time 4160814989 ps
CPU time 31.92 seconds
Started Jun 29 04:40:04 PM PDT 24
Finished Jun 29 04:40:37 PM PDT 24
Peak memory 212120 kb
Host smart-79be7d0c-9461-46a8-a7ae-a3e79b74cdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233622973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3233622973
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1741640128
Short name T48
Test name
Test status
Simulation time 7087907822 ps
CPU time 15.07 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:19 PM PDT 24
Peak memory 211400 kb
Host smart-c4817cac-edf0-44e8-8b6c-eeb8360bc776
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741640128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1741640128
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2554832769
Short name T176
Test name
Test status
Simulation time 179592133 ps
CPU time 10 seconds
Started Jun 29 04:40:04 PM PDT 24
Finished Jun 29 04:40:15 PM PDT 24
Peak memory 213588 kb
Host smart-7ea8ae0e-4b6e-4cd2-b6d3-5b8cb4edaee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554832769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2554832769
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2387263518
Short name T180
Test name
Test status
Simulation time 826556886 ps
CPU time 11.42 seconds
Started Jun 29 04:40:02 PM PDT 24
Finished Jun 29 04:40:14 PM PDT 24
Peak memory 215172 kb
Host smart-4c0efe76-a07a-4e5d-8505-6e645b906f03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387263518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2387263518
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1571743210
Short name T142
Test name
Test status
Simulation time 2078890685 ps
CPU time 16.25 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:20 PM PDT 24
Peak memory 211216 kb
Host smart-0cf353fc-ebef-489a-b82a-42a9d4ae0085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571743210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1571743210
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.859162102
Short name T43
Test name
Test status
Simulation time 87231269769 ps
CPU time 206.31 seconds
Started Jun 29 04:40:02 PM PDT 24
Finished Jun 29 04:43:29 PM PDT 24
Peak memory 237000 kb
Host smart-a4f18c5e-c1d6-4b2e-9591-a450974b42ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859162102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.859162102
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2776482768
Short name T362
Test name
Test status
Simulation time 1499926280 ps
CPU time 13.96 seconds
Started Jun 29 04:40:01 PM PDT 24
Finished Jun 29 04:40:16 PM PDT 24
Peak memory 211268 kb
Host smart-0c122472-3f07-4b75-9804-12da27336953
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776482768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2776482768
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1520945831
Short name T52
Test name
Test status
Simulation time 2440570690 ps
CPU time 20.97 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:25 PM PDT 24
Peak memory 213364 kb
Host smart-db4b26b9-f76a-460c-b04c-b9048f1be46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520945831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1520945831
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.821142711
Short name T140
Test name
Test status
Simulation time 27394339622 ps
CPU time 46.88 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:51 PM PDT 24
Peak memory 214688 kb
Host smart-24c5082e-0ae7-44bb-9762-b6cf1d172a42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821142711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.821142711
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3595313726
Short name T3
Test name
Test status
Simulation time 562463466 ps
CPU time 7.6 seconds
Started Jun 29 04:40:02 PM PDT 24
Finished Jun 29 04:40:10 PM PDT 24
Peak memory 211288 kb
Host smart-1668de86-e940-4c01-87ac-5e5e9a392689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595313726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3595313726
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.47349569
Short name T300
Test name
Test status
Simulation time 28295410646 ps
CPU time 228.69 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:43:53 PM PDT 24
Peak memory 212580 kb
Host smart-f5041439-2215-4344-9f3c-39d3558f1058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47349569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_co
rrupt_sig_fatal_chk.47349569
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1354333921
Short name T181
Test name
Test status
Simulation time 4847536460 ps
CPU time 16.63 seconds
Started Jun 29 04:40:02 PM PDT 24
Finished Jun 29 04:40:19 PM PDT 24
Peak memory 212164 kb
Host smart-7cc6b23a-d1e8-44df-b444-16527224d697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354333921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1354333921
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2492164052
Short name T244
Test name
Test status
Simulation time 1169130505 ps
CPU time 9.14 seconds
Started Jun 29 04:40:02 PM PDT 24
Finished Jun 29 04:40:12 PM PDT 24
Peak memory 211328 kb
Host smart-36acf59b-ea7d-431a-b9a6-4cd753f71bb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492164052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2492164052
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4194769910
Short name T292
Test name
Test status
Simulation time 1271157177 ps
CPU time 19.27 seconds
Started Jun 29 04:40:05 PM PDT 24
Finished Jun 29 04:40:25 PM PDT 24
Peak memory 213188 kb
Host smart-393c9f1b-5a8d-4084-9073-3c08bfc57250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194769910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4194769910
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1664150402
Short name T204
Test name
Test status
Simulation time 7552674297 ps
CPU time 88.03 seconds
Started Jun 29 04:40:05 PM PDT 24
Finished Jun 29 04:41:34 PM PDT 24
Peak memory 215796 kb
Host smart-72aba81e-5da4-4144-855f-e95eeedef226
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664150402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1664150402
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1321368971
Short name T276
Test name
Test status
Simulation time 5196083620 ps
CPU time 12.98 seconds
Started Jun 29 04:40:02 PM PDT 24
Finished Jun 29 04:40:16 PM PDT 24
Peak memory 211268 kb
Host smart-9c6a3864-b0ec-461e-b807-bd3b9603ebca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321368971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1321368971
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2700315898
Short name T261
Test name
Test status
Simulation time 20928522513 ps
CPU time 102.01 seconds
Started Jun 29 04:40:06 PM PDT 24
Finished Jun 29 04:41:48 PM PDT 24
Peak memory 212908 kb
Host smart-16135dbf-32a3-4f14-829b-5d294a8e4ecb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700315898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2700315898
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.938527905
Short name T311
Test name
Test status
Simulation time 3698798309 ps
CPU time 20.15 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:24 PM PDT 24
Peak memory 211868 kb
Host smart-840bc459-a4be-4b75-868f-9ae4c3cc2880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938527905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.938527905
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4130074545
Short name T318
Test name
Test status
Simulation time 882821622 ps
CPU time 6.29 seconds
Started Jun 29 04:40:01 PM PDT 24
Finished Jun 29 04:40:08 PM PDT 24
Peak memory 211340 kb
Host smart-df83328c-2d8c-4082-af38-5835789fde37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130074545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4130074545
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1188839387
Short name T131
Test name
Test status
Simulation time 1614511501 ps
CPU time 21.96 seconds
Started Jun 29 04:40:05 PM PDT 24
Finished Jun 29 04:40:28 PM PDT 24
Peak memory 213704 kb
Host smart-0b0e0fcf-554c-49a9-b9a8-7c92d4e96768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188839387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1188839387
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1328422280
Short name T308
Test name
Test status
Simulation time 6575631089 ps
CPU time 64.41 seconds
Started Jun 29 04:40:02 PM PDT 24
Finished Jun 29 04:41:07 PM PDT 24
Peak memory 216832 kb
Host smart-10abc1eb-33fd-43ce-a6c2-3455d75677fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328422280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1328422280
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.904253168
Short name T11
Test name
Test status
Simulation time 72619345385 ps
CPU time 1469.75 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 05:04:34 PM PDT 24
Peak memory 237536 kb
Host smart-13f7e286-01a1-4ef1-af97-df3f9553c90b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904253168 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.904253168
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2813020415
Short name T24
Test name
Test status
Simulation time 1920051195 ps
CPU time 15.6 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:19 PM PDT 24
Peak memory 211212 kb
Host smart-4af80a69-7c55-4ffa-8700-5f88bc3c7c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813020415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2813020415
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.425337972
Short name T202
Test name
Test status
Simulation time 20853740195 ps
CPU time 207.88 seconds
Started Jun 29 04:40:05 PM PDT 24
Finished Jun 29 04:43:34 PM PDT 24
Peak memory 237748 kb
Host smart-81364c4e-4a2f-4a3c-9356-586312449daa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425337972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.425337972
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3625857164
Short name T26
Test name
Test status
Simulation time 1120922096 ps
CPU time 16.71 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:21 PM PDT 24
Peak memory 212140 kb
Host smart-cc6a13c3-7462-43eb-a286-c1a9d544c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625857164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3625857164
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2757811429
Short name T314
Test name
Test status
Simulation time 2849403581 ps
CPU time 10.07 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:15 PM PDT 24
Peak memory 211328 kb
Host smart-de1894b5-caec-4094-b21e-9cbbe9a90334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757811429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2757811429
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1628113539
Short name T194
Test name
Test status
Simulation time 519453833 ps
CPU time 26.6 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:31 PM PDT 24
Peak memory 216296 kb
Host smart-cfe9a814-1cca-4c4e-8abf-2dffa362860b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628113539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1628113539
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.843738151
Short name T326
Test name
Test status
Simulation time 3962566438 ps
CPU time 10.25 seconds
Started Jun 29 04:40:05 PM PDT 24
Finished Jun 29 04:40:16 PM PDT 24
Peak memory 211276 kb
Host smart-1292b687-fa00-4043-890a-9395448d6855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843738151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.843738151
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.100223209
Short name T279
Test name
Test status
Simulation time 146661090186 ps
CPU time 256.65 seconds
Started Jun 29 04:40:01 PM PDT 24
Finished Jun 29 04:44:18 PM PDT 24
Peak memory 212580 kb
Host smart-783c63ca-8000-4bcd-b0ae-b9f092901351
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100223209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.100223209
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4250596737
Short name T216
Test name
Test status
Simulation time 27787644809 ps
CPU time 19.15 seconds
Started Jun 29 04:40:04 PM PDT 24
Finished Jun 29 04:40:24 PM PDT 24
Peak memory 212240 kb
Host smart-6a7cb5f5-56e2-4e62-a40c-fb161225f287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250596737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4250596737
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.115260043
Short name T270
Test name
Test status
Simulation time 7174935934 ps
CPU time 15.18 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:19 PM PDT 24
Peak memory 211408 kb
Host smart-90a8655e-8609-474b-b055-f99b87ad5732
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115260043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.115260043
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.105791218
Short name T33
Test name
Test status
Simulation time 1480519294 ps
CPU time 19.13 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:23 PM PDT 24
Peak memory 213324 kb
Host smart-6bc6f315-7e60-4e5a-944b-5ea69aa228e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105791218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.105791218
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3986792955
Short name T195
Test name
Test status
Simulation time 680150066 ps
CPU time 31.57 seconds
Started Jun 29 04:40:05 PM PDT 24
Finished Jun 29 04:40:37 PM PDT 24
Peak memory 216376 kb
Host smart-cbde5507-843d-48fc-98b9-81e76bfa0497
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986792955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3986792955
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.595231843
Short name T60
Test name
Test status
Simulation time 50790682141 ps
CPU time 1891.45 seconds
Started Jun 29 04:40:05 PM PDT 24
Finished Jun 29 05:11:37 PM PDT 24
Peak memory 235756 kb
Host smart-388e15e6-bedb-4d59-a193-30333905e237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595231843 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.595231843
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1861463023
Short name T179
Test name
Test status
Simulation time 759647103 ps
CPU time 6.95 seconds
Started Jun 29 04:40:12 PM PDT 24
Finished Jun 29 04:40:20 PM PDT 24
Peak memory 211216 kb
Host smart-4cae9af1-f883-436e-91df-e9984f53a210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861463023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1861463023
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2662289757
Short name T205
Test name
Test status
Simulation time 1317978823 ps
CPU time 85.39 seconds
Started Jun 29 04:40:07 PM PDT 24
Finished Jun 29 04:41:33 PM PDT 24
Peak memory 212508 kb
Host smart-c41bfd3b-a92a-4c14-8840-995f2f68f846
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662289757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2662289757
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1422100401
Short name T97
Test name
Test status
Simulation time 8049672858 ps
CPU time 33.72 seconds
Started Jun 29 04:40:09 PM PDT 24
Finished Jun 29 04:40:44 PM PDT 24
Peak memory 212144 kb
Host smart-a85b1892-b0c2-4f6a-81b6-3a4c8facbf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422100401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1422100401
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2245393241
Short name T133
Test name
Test status
Simulation time 1734286748 ps
CPU time 13.62 seconds
Started Jun 29 04:40:05 PM PDT 24
Finished Jun 29 04:40:19 PM PDT 24
Peak memory 211312 kb
Host smart-dd8d4759-1bf9-4b8f-a03a-fae652a87331
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245393241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2245393241
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4212183657
Short name T214
Test name
Test status
Simulation time 20751121953 ps
CPU time 25.54 seconds
Started Jun 29 04:40:07 PM PDT 24
Finished Jun 29 04:40:33 PM PDT 24
Peak memory 214008 kb
Host smart-3d4a65cb-b7d6-4f37-bd7f-82f64d7f8c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212183657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4212183657
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2194073129
Short name T197
Test name
Test status
Simulation time 25437268360 ps
CPU time 62.35 seconds
Started Jun 29 04:40:07 PM PDT 24
Finished Jun 29 04:41:09 PM PDT 24
Peak memory 217720 kb
Host smart-8010215c-098c-4ca4-b4ac-007767c40049
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194073129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2194073129
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2178541457
Short name T61
Test name
Test status
Simulation time 13857957964 ps
CPU time 532.02 seconds
Started Jun 29 04:40:11 PM PDT 24
Finished Jun 29 04:49:03 PM PDT 24
Peak memory 222584 kb
Host smart-a30f73c6-c3dd-4eee-955c-b72cc5daacf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178541457 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2178541457
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2451135432
Short name T30
Test name
Test status
Simulation time 116169311 ps
CPU time 4.36 seconds
Started Jun 29 04:40:12 PM PDT 24
Finished Jun 29 04:40:17 PM PDT 24
Peak memory 211216 kb
Host smart-a67464ea-f352-43d6-9076-c55a36098984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451135432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2451135432
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.162302342
Short name T347
Test name
Test status
Simulation time 32508538479 ps
CPU time 119.84 seconds
Started Jun 29 04:40:10 PM PDT 24
Finished Jun 29 04:42:10 PM PDT 24
Peak memory 237788 kb
Host smart-01df9b0e-d48a-4284-bcbd-a9faf72a0278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162302342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.162302342
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.862561869
Short name T251
Test name
Test status
Simulation time 1689063281 ps
CPU time 19.7 seconds
Started Jun 29 04:40:11 PM PDT 24
Finished Jun 29 04:40:32 PM PDT 24
Peak memory 211956 kb
Host smart-82014c73-b6e3-4bc4-8993-0dccf6bb51f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862561869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.862561869
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1974600945
Short name T363
Test name
Test status
Simulation time 8726315117 ps
CPU time 17.42 seconds
Started Jun 29 04:40:10 PM PDT 24
Finished Jun 29 04:40:28 PM PDT 24
Peak memory 211400 kb
Host smart-d7aaf3e8-a70c-4475-a99a-1377eaf8e354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1974600945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1974600945
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.984745457
Short name T331
Test name
Test status
Simulation time 3632599793 ps
CPU time 39.95 seconds
Started Jun 29 04:40:11 PM PDT 24
Finished Jun 29 04:40:52 PM PDT 24
Peak memory 213520 kb
Host smart-7cb0f094-e537-46d4-a9ff-1c82da192f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984745457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.984745457
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3329529377
Short name T360
Test name
Test status
Simulation time 4537708461 ps
CPU time 16.07 seconds
Started Jun 29 04:40:09 PM PDT 24
Finished Jun 29 04:40:26 PM PDT 24
Peak memory 211448 kb
Host smart-82f3e38b-63a3-448e-acda-47181bdcaea5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329529377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3329529377
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1847773434
Short name T358
Test name
Test status
Simulation time 12169464950 ps
CPU time 990.12 seconds
Started Jun 29 04:40:09 PM PDT 24
Finished Jun 29 04:56:40 PM PDT 24
Peak memory 233100 kb
Host smart-b70f43e7-da3b-4a7e-8441-e6afb5754ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847773434 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1847773434
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3143805606
Short name T184
Test name
Test status
Simulation time 1883630007 ps
CPU time 7.33 seconds
Started Jun 29 04:40:10 PM PDT 24
Finished Jun 29 04:40:18 PM PDT 24
Peak memory 211200 kb
Host smart-1d740721-aa6b-4482-b4f6-57fcaf2a5596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143805606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3143805606
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2583547167
Short name T227
Test name
Test status
Simulation time 43874126746 ps
CPU time 235.2 seconds
Started Jun 29 04:40:13 PM PDT 24
Finished Jun 29 04:44:09 PM PDT 24
Peak memory 212504 kb
Host smart-0d1868f8-9e4e-4fe6-97fc-e5f24d64c0f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583547167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2583547167
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.94208911
Short name T289
Test name
Test status
Simulation time 65574338814 ps
CPU time 28.86 seconds
Started Jun 29 04:40:10 PM PDT 24
Finished Jun 29 04:40:40 PM PDT 24
Peak memory 212164 kb
Host smart-92b620cb-0235-44d1-b83c-c010608d7cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94208911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.94208911
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3918552394
Short name T213
Test name
Test status
Simulation time 401261256 ps
CPU time 5.54 seconds
Started Jun 29 04:40:10 PM PDT 24
Finished Jun 29 04:40:17 PM PDT 24
Peak memory 211300 kb
Host smart-0846ee7b-7068-4e88-bc4a-0bcf17115334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918552394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3918552394
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2313919709
Short name T96
Test name
Test status
Simulation time 4448340783 ps
CPU time 25.08 seconds
Started Jun 29 04:40:11 PM PDT 24
Finished Jun 29 04:40:37 PM PDT 24
Peak memory 213076 kb
Host smart-26cab852-41f2-4f02-a6ba-1e2d8b7da384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313919709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2313919709
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2790810306
Short name T243
Test name
Test status
Simulation time 2248020460 ps
CPU time 29.75 seconds
Started Jun 29 04:40:09 PM PDT 24
Finished Jun 29 04:40:40 PM PDT 24
Peak memory 215308 kb
Host smart-3ca47037-1946-41f4-a80e-b1c5542ab011
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790810306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2790810306
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3290186337
Short name T364
Test name
Test status
Simulation time 5550221192 ps
CPU time 13.47 seconds
Started Jun 29 04:40:13 PM PDT 24
Finished Jun 29 04:40:27 PM PDT 24
Peak memory 211288 kb
Host smart-9ec5ec6f-5b0b-4250-a269-711b1bcaba67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290186337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3290186337
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.243154845
Short name T236
Test name
Test status
Simulation time 1605740317 ps
CPU time 89.48 seconds
Started Jun 29 04:40:11 PM PDT 24
Finished Jun 29 04:41:41 PM PDT 24
Peak memory 211824 kb
Host smart-7f3963c2-1ddd-4fd5-903f-e66b15bb0c5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243154845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.243154845
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1746597733
Short name T46
Test name
Test status
Simulation time 7528412210 ps
CPU time 17.7 seconds
Started Jun 29 04:40:11 PM PDT 24
Finished Jun 29 04:40:29 PM PDT 24
Peak memory 211396 kb
Host smart-ca7566ec-2100-480c-bd23-30d0d2c66e6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746597733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1746597733
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3608118617
Short name T217
Test name
Test status
Simulation time 521413323 ps
CPU time 15.08 seconds
Started Jun 29 04:40:10 PM PDT 24
Finished Jun 29 04:40:26 PM PDT 24
Peak memory 212580 kb
Host smart-f93baaa4-8c3d-49b8-9e2e-196b42ed3436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608118617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3608118617
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2563684745
Short name T34
Test name
Test status
Simulation time 22188712610 ps
CPU time 89.73 seconds
Started Jun 29 04:40:12 PM PDT 24
Finished Jun 29 04:41:43 PM PDT 24
Peak memory 219316 kb
Host smart-36f8f1cc-3a87-47f1-b0a8-a40b210061a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563684745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2563684745
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1044025353
Short name T98
Test name
Test status
Simulation time 3131335783 ps
CPU time 13.92 seconds
Started Jun 29 04:39:47 PM PDT 24
Finished Jun 29 04:40:02 PM PDT 24
Peak memory 211352 kb
Host smart-66011cf4-0b7f-4189-943f-db7a7b13a685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044025353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1044025353
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3269608914
Short name T119
Test name
Test status
Simulation time 83277708649 ps
CPU time 198.49 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:43:06 PM PDT 24
Peak memory 236696 kb
Host smart-ec1e6f13-06fe-4f3c-89b0-b73e6910c3a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269608914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3269608914
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1561250012
Short name T328
Test name
Test status
Simulation time 3610970429 ps
CPU time 30.76 seconds
Started Jun 29 04:39:47 PM PDT 24
Finished Jun 29 04:40:19 PM PDT 24
Peak memory 211896 kb
Host smart-8c1eda21-0418-4bd1-b2dc-b4d0dffd2aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561250012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1561250012
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1512283697
Short name T245
Test name
Test status
Simulation time 8533899991 ps
CPU time 18.42 seconds
Started Jun 29 04:39:47 PM PDT 24
Finished Jun 29 04:40:06 PM PDT 24
Peak memory 211396 kb
Host smart-4f0e1733-1a7c-4047-95ab-9e357e5aa9f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512283697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1512283697
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2192784871
Short name T28
Test name
Test status
Simulation time 3313238696 ps
CPU time 60.61 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:40:48 PM PDT 24
Peak memory 236884 kb
Host smart-2b454a8e-d811-479c-a0d5-eb05429b1984
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192784871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2192784871
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3517003467
Short name T302
Test name
Test status
Simulation time 3366624086 ps
CPU time 29.1 seconds
Started Jun 29 04:39:48 PM PDT 24
Finished Jun 29 04:40:17 PM PDT 24
Peak memory 213648 kb
Host smart-4c81c8d1-3b8a-43d6-a130-4d89958ea22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517003467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3517003467
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4088544386
Short name T242
Test name
Test status
Simulation time 574468141 ps
CPU time 17.85 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:40:05 PM PDT 24
Peak memory 213708 kb
Host smart-ac5fdee2-3406-4db4-8f5d-1cd0244d1696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088544386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4088544386
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3164342371
Short name T306
Test name
Test status
Simulation time 18080049676 ps
CPU time 2138.53 seconds
Started Jun 29 04:39:47 PM PDT 24
Finished Jun 29 05:15:26 PM PDT 24
Peak memory 227548 kb
Host smart-3c00688a-6ee4-4d43-8fc2-c4c78e5d8765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164342371 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3164342371
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.611422229
Short name T100
Test name
Test status
Simulation time 2579998146 ps
CPU time 8.78 seconds
Started Jun 29 04:40:20 PM PDT 24
Finished Jun 29 04:40:29 PM PDT 24
Peak memory 211348 kb
Host smart-0e6b7738-31b5-46d4-9e0c-43817decc05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611422229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.611422229
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2230410599
Short name T320
Test name
Test status
Simulation time 42931242562 ps
CPU time 228.24 seconds
Started Jun 29 04:40:11 PM PDT 24
Finished Jun 29 04:44:00 PM PDT 24
Peak memory 228524 kb
Host smart-354a7e61-b429-45ed-a4d2-ba1cee54d2b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230410599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2230410599
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1523321566
Short name T324
Test name
Test status
Simulation time 1450237832 ps
CPU time 18.43 seconds
Started Jun 29 04:40:11 PM PDT 24
Finished Jun 29 04:40:30 PM PDT 24
Peak memory 212016 kb
Host smart-90c8a89c-1ff9-4765-b8bd-a38bd9bd5076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523321566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1523321566
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.191186724
Short name T127
Test name
Test status
Simulation time 374813235 ps
CPU time 5.71 seconds
Started Jun 29 04:40:13 PM PDT 24
Finished Jun 29 04:40:19 PM PDT 24
Peak memory 211292 kb
Host smart-b40e5cd9-ae9e-4d46-bc7d-c318c22ed8b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=191186724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.191186724
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4282781009
Short name T241
Test name
Test status
Simulation time 17594335176 ps
CPU time 31.89 seconds
Started Jun 29 04:40:10 PM PDT 24
Finished Jun 29 04:40:42 PM PDT 24
Peak memory 214376 kb
Host smart-8db95a8b-9c95-407a-a9eb-f1e2ab6593a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282781009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4282781009
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.860415806
Short name T76
Test name
Test status
Simulation time 1817541375 ps
CPU time 21.48 seconds
Started Jun 29 04:40:09 PM PDT 24
Finished Jun 29 04:40:31 PM PDT 24
Peak memory 215372 kb
Host smart-7822c26a-0843-43e2-b2aa-db3ca20c3657
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860415806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.860415806
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2420093520
Short name T94
Test name
Test status
Simulation time 170913082 ps
CPU time 5.46 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:40:25 PM PDT 24
Peak memory 211288 kb
Host smart-bd997fa3-a777-4cd2-adc4-d9f1503f3286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420093520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2420093520
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.550374132
Short name T341
Test name
Test status
Simulation time 56011094149 ps
CPU time 179.4 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 237736 kb
Host smart-943b8417-934f-4c3d-836c-c2db883f8efd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550374132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.550374132
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2141506740
Short name T146
Test name
Test status
Simulation time 6857613168 ps
CPU time 21.21 seconds
Started Jun 29 04:40:20 PM PDT 24
Finished Jun 29 04:40:42 PM PDT 24
Peak memory 212348 kb
Host smart-3b4009ad-10d2-4c76-9f34-02b742226930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141506740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2141506740
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1446592819
Short name T157
Test name
Test status
Simulation time 17772867306 ps
CPU time 16.58 seconds
Started Jun 29 04:40:25 PM PDT 24
Finished Jun 29 04:40:42 PM PDT 24
Peak memory 211324 kb
Host smart-fcfdb44e-afde-4840-b3c7-6743d6f2545f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446592819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1446592819
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1710050723
Short name T342
Test name
Test status
Simulation time 722333622 ps
CPU time 10.35 seconds
Started Jun 29 04:40:25 PM PDT 24
Finished Jun 29 04:40:36 PM PDT 24
Peak memory 213456 kb
Host smart-c7854191-c53a-4cb9-9043-96431ad3a684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710050723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1710050723
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3425799058
Short name T223
Test name
Test status
Simulation time 1651748191 ps
CPU time 21.45 seconds
Started Jun 29 04:40:26 PM PDT 24
Finished Jun 29 04:40:48 PM PDT 24
Peak memory 213504 kb
Host smart-e29db0e9-bf21-44d2-93a3-6e8a6fc89717
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425799058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3425799058
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1770068839
Short name T338
Test name
Test status
Simulation time 89600781481 ps
CPU time 1704.24 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 05:08:43 PM PDT 24
Peak memory 235800 kb
Host smart-d01fb6db-ed30-48d5-a9eb-0550b251a786
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770068839 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1770068839
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.777695797
Short name T201
Test name
Test status
Simulation time 1089981799 ps
CPU time 5.91 seconds
Started Jun 29 04:40:20 PM PDT 24
Finished Jun 29 04:40:27 PM PDT 24
Peak memory 211204 kb
Host smart-1b1f4165-072d-47da-9680-773835c23ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777695797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.777695797
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3937977730
Short name T233
Test name
Test status
Simulation time 4712357186 ps
CPU time 135.74 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:42:35 PM PDT 24
Peak memory 235864 kb
Host smart-7f098466-51a0-4639-83b9-42f4c55fb435
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937977730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3937977730
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1057089071
Short name T278
Test name
Test status
Simulation time 175366507 ps
CPU time 9.5 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:40:29 PM PDT 24
Peak memory 211884 kb
Host smart-5fda380e-eec9-4557-b2d5-9961e22db3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057089071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1057089071
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3686095755
Short name T286
Test name
Test status
Simulation time 1152837806 ps
CPU time 5.49 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:40:24 PM PDT 24
Peak memory 211340 kb
Host smart-93322e42-8976-4c31-a577-0afefcead4a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686095755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3686095755
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2144174157
Short name T189
Test name
Test status
Simulation time 5308440551 ps
CPU time 19.78 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:40:38 PM PDT 24
Peak memory 213264 kb
Host smart-727a69d7-dc3f-4562-9379-e93c3d48dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144174157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2144174157
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.666870584
Short name T330
Test name
Test status
Simulation time 2502980893 ps
CPU time 16.17 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:40:36 PM PDT 24
Peak memory 213508 kb
Host smart-f9eebaac-3ffa-4b4f-9e42-b6d62b9dfa77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666870584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.666870584
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3339729298
Short name T57
Test name
Test status
Simulation time 110259273981 ps
CPU time 4249.25 seconds
Started Jun 29 04:40:19 PM PDT 24
Finished Jun 29 05:51:10 PM PDT 24
Peak memory 235724 kb
Host smart-41556b9f-293c-4745-86c9-65d73f45b070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339729298 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3339729298
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1643896586
Short name T173
Test name
Test status
Simulation time 8693892476 ps
CPU time 16.64 seconds
Started Jun 29 04:40:20 PM PDT 24
Finished Jun 29 04:40:37 PM PDT 24
Peak memory 211348 kb
Host smart-732cee06-d494-4927-b360-4677d241cdfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643896586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1643896586
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.620208538
Short name T44
Test name
Test status
Simulation time 74615343658 ps
CPU time 290.07 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:45:09 PM PDT 24
Peak memory 232960 kb
Host smart-3075ce8f-dadf-4f17-9181-6541f598c9cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620208538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.620208538
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2316637339
Short name T174
Test name
Test status
Simulation time 171532231 ps
CPU time 9.54 seconds
Started Jun 29 04:40:24 PM PDT 24
Finished Jun 29 04:40:35 PM PDT 24
Peak memory 211744 kb
Host smart-21604697-47b7-4e76-993d-f26a13a3631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316637339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2316637339
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2139032981
Short name T130
Test name
Test status
Simulation time 2119224537 ps
CPU time 13.55 seconds
Started Jun 29 04:40:21 PM PDT 24
Finished Jun 29 04:40:35 PM PDT 24
Peak memory 211308 kb
Host smart-ebe2c921-57a9-42a9-8466-ced64cf84b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139032981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2139032981
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2921446299
Short name T240
Test name
Test status
Simulation time 1696495142 ps
CPU time 12.69 seconds
Started Jun 29 04:40:17 PM PDT 24
Finished Jun 29 04:40:30 PM PDT 24
Peak memory 213120 kb
Host smart-7e1a81bf-be68-4ad3-a5ba-a069c143dea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921446299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2921446299
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.416392013
Short name T141
Test name
Test status
Simulation time 8916909603 ps
CPU time 46.25 seconds
Started Jun 29 04:40:19 PM PDT 24
Finished Jun 29 04:41:06 PM PDT 24
Peak memory 215456 kb
Host smart-584a6a70-8876-40cd-ba88-405a7518afc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416392013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.416392013
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1729785343
Short name T145
Test name
Test status
Simulation time 5209390068 ps
CPU time 7.93 seconds
Started Jun 29 04:40:22 PM PDT 24
Finished Jun 29 04:40:30 PM PDT 24
Peak memory 211348 kb
Host smart-67a5c320-7437-4473-a4e7-a3b143656e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729785343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1729785343
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2094918188
Short name T163
Test name
Test status
Simulation time 5845018144 ps
CPU time 69.24 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:41:28 PM PDT 24
Peak memory 237780 kb
Host smart-bdf9a09d-57fc-45d0-b356-50ba3fd5b26d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094918188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2094918188
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.431058808
Short name T319
Test name
Test status
Simulation time 334521196 ps
CPU time 9.6 seconds
Started Jun 29 04:40:17 PM PDT 24
Finished Jun 29 04:40:27 PM PDT 24
Peak memory 211748 kb
Host smart-f4b3a890-d1df-46c9-8ebd-3fe792a57262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431058808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.431058808
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2693116572
Short name T190
Test name
Test status
Simulation time 1316857754 ps
CPU time 11.89 seconds
Started Jun 29 04:40:16 PM PDT 24
Finished Jun 29 04:40:29 PM PDT 24
Peak memory 211340 kb
Host smart-75eaa627-8b99-4bca-9356-ab0eda876e46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693116572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2693116572
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4212974022
Short name T149
Test name
Test status
Simulation time 1341282747 ps
CPU time 15.19 seconds
Started Jun 29 04:40:17 PM PDT 24
Finished Jun 29 04:40:33 PM PDT 24
Peak memory 214536 kb
Host smart-aed037a3-3e01-4868-aa9e-bcdd108973f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212974022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4212974022
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3445470308
Short name T178
Test name
Test status
Simulation time 4448948863 ps
CPU time 52.35 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:41:10 PM PDT 24
Peak memory 213604 kb
Host smart-abf1f2eb-3672-457a-8591-7fb5ec3014b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445470308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3445470308
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.456623093
Short name T137
Test name
Test status
Simulation time 3793838575 ps
CPU time 10.28 seconds
Started Jun 29 04:40:20 PM PDT 24
Finished Jun 29 04:40:32 PM PDT 24
Peak memory 211268 kb
Host smart-dec9347e-98d2-407e-8e82-4ad04591bb1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456623093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.456623093
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2932817730
Short name T349
Test name
Test status
Simulation time 14735232164 ps
CPU time 30.8 seconds
Started Jun 29 04:40:22 PM PDT 24
Finished Jun 29 04:40:53 PM PDT 24
Peak memory 212208 kb
Host smart-d9844a47-a57e-43ce-848e-8cd8f9b207e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932817730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2932817730
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1105596938
Short name T310
Test name
Test status
Simulation time 607262563 ps
CPU time 8.98 seconds
Started Jun 29 04:40:17 PM PDT 24
Finished Jun 29 04:40:27 PM PDT 24
Peak memory 211260 kb
Host smart-bf8f5c45-05ee-4720-93f6-751e485577ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1105596938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1105596938
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.407870100
Short name T31
Test name
Test status
Simulation time 1391964657 ps
CPU time 10.49 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:40:30 PM PDT 24
Peak memory 213236 kb
Host smart-96c988e5-d240-472f-813b-9ffeb12f92a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407870100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.407870100
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1967789368
Short name T259
Test name
Test status
Simulation time 181233163 ps
CPU time 9.69 seconds
Started Jun 29 04:40:24 PM PDT 24
Finished Jun 29 04:40:34 PM PDT 24
Peak memory 213680 kb
Host smart-2781fb88-cd05-4ca0-b386-c6a0a1742064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967789368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1967789368
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2500725450
Short name T290
Test name
Test status
Simulation time 2219098389 ps
CPU time 11.48 seconds
Started Jun 29 04:40:18 PM PDT 24
Finished Jun 29 04:40:31 PM PDT 24
Peak memory 211276 kb
Host smart-4ef5ada2-3a56-4912-9885-9fc9b215e50e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500725450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2500725450
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.262772211
Short name T172
Test name
Test status
Simulation time 30743531650 ps
CPU time 229.98 seconds
Started Jun 29 04:40:21 PM PDT 24
Finished Jun 29 04:44:11 PM PDT 24
Peak memory 212656 kb
Host smart-3f9f6f54-4d53-4da3-b177-bd84e3c2d639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262772211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.262772211
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4192179626
Short name T128
Test name
Test status
Simulation time 432071612 ps
CPU time 12.27 seconds
Started Jun 29 04:40:21 PM PDT 24
Finished Jun 29 04:40:34 PM PDT 24
Peak memory 211904 kb
Host smart-91f5e5ec-a6df-45b8-af08-1dde8af931cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192179626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4192179626
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2967130135
Short name T47
Test name
Test status
Simulation time 17130978100 ps
CPU time 16.49 seconds
Started Jun 29 04:40:23 PM PDT 24
Finished Jun 29 04:40:40 PM PDT 24
Peak memory 211324 kb
Host smart-9c1b554b-478d-45d0-97e4-c7b14206c06c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967130135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2967130135
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3652133477
Short name T169
Test name
Test status
Simulation time 2748247078 ps
CPU time 36.72 seconds
Started Jun 29 04:40:20 PM PDT 24
Finished Jun 29 04:40:58 PM PDT 24
Peak memory 214864 kb
Host smart-3fb62cbd-bf53-47e7-a417-004f6c90592e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652133477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3652133477
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1451767946
Short name T165
Test name
Test status
Simulation time 1991516388 ps
CPU time 8.19 seconds
Started Jun 29 04:40:25 PM PDT 24
Finished Jun 29 04:40:34 PM PDT 24
Peak memory 211288 kb
Host smart-a15e241e-d6b6-4531-af79-b463f674f3ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451767946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1451767946
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2393731300
Short name T252
Test name
Test status
Simulation time 112707708357 ps
CPU time 496.94 seconds
Started Jun 29 04:40:28 PM PDT 24
Finished Jun 29 04:48:45 PM PDT 24
Peak memory 237700 kb
Host smart-1e1e594f-65f6-4e19-a849-d5a0573112e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393731300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2393731300
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2777966955
Short name T187
Test name
Test status
Simulation time 171990774 ps
CPU time 9.65 seconds
Started Jun 29 04:40:27 PM PDT 24
Finished Jun 29 04:40:37 PM PDT 24
Peak memory 211840 kb
Host smart-05b68ab0-f5e0-4376-96c4-174278c32888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777966955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2777966955
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1579364674
Short name T135
Test name
Test status
Simulation time 4458653537 ps
CPU time 11.68 seconds
Started Jun 29 04:40:23 PM PDT 24
Finished Jun 29 04:40:36 PM PDT 24
Peak memory 211324 kb
Host smart-ff62a13c-e418-4564-9053-536b961320cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579364674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1579364674
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3200224095
Short name T269
Test name
Test status
Simulation time 4019652921 ps
CPU time 62.35 seconds
Started Jun 29 04:40:21 PM PDT 24
Finished Jun 29 04:41:24 PM PDT 24
Peak memory 217464 kb
Host smart-0d861bcd-107a-4475-886a-38200542fe3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200224095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3200224095
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.405733322
Short name T123
Test name
Test status
Simulation time 1023975321 ps
CPU time 10.33 seconds
Started Jun 29 04:40:34 PM PDT 24
Finished Jun 29 04:40:45 PM PDT 24
Peak memory 211216 kb
Host smart-6b89d40e-daa8-4db7-8930-398316fdba43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405733322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.405733322
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1942180459
Short name T168
Test name
Test status
Simulation time 16389283365 ps
CPU time 155.92 seconds
Started Jun 29 04:40:33 PM PDT 24
Finished Jun 29 04:43:10 PM PDT 24
Peak memory 236900 kb
Host smart-99481c47-cfed-40fe-b3ef-ec46f24976fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942180459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1942180459
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1228057275
Short name T356
Test name
Test status
Simulation time 2986789413 ps
CPU time 26.41 seconds
Started Jun 29 04:40:34 PM PDT 24
Finished Jun 29 04:41:01 PM PDT 24
Peak memory 211940 kb
Host smart-7af06ed0-16a1-410b-a3e4-1416aca3be7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228057275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1228057275
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1047222191
Short name T351
Test name
Test status
Simulation time 6850182571 ps
CPU time 16.7 seconds
Started Jun 29 04:40:24 PM PDT 24
Finished Jun 29 04:40:42 PM PDT 24
Peak memory 211400 kb
Host smart-f77d0216-78a4-4548-b683-1e8d68d9a570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1047222191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1047222191
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.890226002
Short name T125
Test name
Test status
Simulation time 25250967337 ps
CPU time 35.27 seconds
Started Jun 29 04:40:27 PM PDT 24
Finished Jun 29 04:41:03 PM PDT 24
Peak memory 214136 kb
Host smart-6c252417-5cea-461d-88d0-9d9605fc22a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890226002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.890226002
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1016960539
Short name T348
Test name
Test status
Simulation time 9052928168 ps
CPU time 65.98 seconds
Started Jun 29 04:40:26 PM PDT 24
Finished Jun 29 04:41:33 PM PDT 24
Peak memory 214464 kb
Host smart-983aac2f-6ce1-4eb2-b3ed-73ea98dcf30d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016960539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1016960539
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2773532017
Short name T58
Test name
Test status
Simulation time 13279225108 ps
CPU time 500.54 seconds
Started Jun 29 04:40:34 PM PDT 24
Finished Jun 29 04:48:55 PM PDT 24
Peak memory 224716 kb
Host smart-afbf3143-9cf2-4c6b-848f-85db5284bae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773532017 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2773532017
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.750570512
Short name T288
Test name
Test status
Simulation time 4103114841 ps
CPU time 10.01 seconds
Started Jun 29 04:40:35 PM PDT 24
Finished Jun 29 04:40:45 PM PDT 24
Peak memory 211308 kb
Host smart-0e0ff5ed-96c4-472b-8aba-6cc25341e67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750570512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.750570512
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3580928207
Short name T41
Test name
Test status
Simulation time 2770770665 ps
CPU time 112.45 seconds
Started Jun 29 04:40:37 PM PDT 24
Finished Jun 29 04:42:29 PM PDT 24
Peak memory 228516 kb
Host smart-b0af01ec-c050-49e6-9dae-b154a03117eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580928207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3580928207
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3978273830
Short name T185
Test name
Test status
Simulation time 4531441299 ps
CPU time 23.44 seconds
Started Jun 29 04:40:33 PM PDT 24
Finished Jun 29 04:40:57 PM PDT 24
Peak memory 212292 kb
Host smart-139e9f6f-bc4f-4ff9-a65b-748bad7e6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978273830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3978273830
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4077586601
Short name T273
Test name
Test status
Simulation time 22575648624 ps
CPU time 16.02 seconds
Started Jun 29 04:40:35 PM PDT 24
Finished Jun 29 04:40:51 PM PDT 24
Peak memory 211368 kb
Host smart-a9590846-8cc3-4c8d-8c21-121f366a60fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077586601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4077586601
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2143332849
Short name T14
Test name
Test status
Simulation time 3439422959 ps
CPU time 30.8 seconds
Started Jun 29 04:40:34 PM PDT 24
Finished Jun 29 04:41:05 PM PDT 24
Peak memory 213564 kb
Host smart-8efe5eaa-2dba-409c-8816-c875e615afaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143332849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2143332849
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.50625167
Short name T158
Test name
Test status
Simulation time 3464499012 ps
CPU time 24.45 seconds
Started Jun 29 04:40:36 PM PDT 24
Finished Jun 29 04:41:01 PM PDT 24
Peak memory 213336 kb
Host smart-3d451f63-47fa-4ac7-8a14-65f739074b89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50625167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.rom_ctrl_stress_all.50625167
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3626153405
Short name T23
Test name
Test status
Simulation time 346956133 ps
CPU time 4.26 seconds
Started Jun 29 04:39:55 PM PDT 24
Finished Jun 29 04:40:01 PM PDT 24
Peak memory 211232 kb
Host smart-df0becfd-1d90-4b4e-a68b-fc6b6f97a518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626153405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3626153405
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3466315045
Short name T303
Test name
Test status
Simulation time 13474338953 ps
CPU time 236.62 seconds
Started Jun 29 04:39:47 PM PDT 24
Finished Jun 29 04:43:44 PM PDT 24
Peak memory 236468 kb
Host smart-ed02f396-9c95-4f55-aade-80d7c2c99393
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466315045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3466315045
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2082714334
Short name T327
Test name
Test status
Simulation time 7483723377 ps
CPU time 29.91 seconds
Started Jun 29 04:39:55 PM PDT 24
Finished Jun 29 04:40:27 PM PDT 24
Peak memory 212828 kb
Host smart-e557c3ce-7bb9-4dbf-9c01-59b581c26cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082714334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2082714334
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4008224521
Short name T321
Test name
Test status
Simulation time 3010730894 ps
CPU time 9.96 seconds
Started Jun 29 04:39:47 PM PDT 24
Finished Jun 29 04:39:58 PM PDT 24
Peak memory 211364 kb
Host smart-ec2bff9d-b223-4528-aa89-f37de65c5d93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008224521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4008224521
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.297153993
Short name T29
Test name
Test status
Simulation time 891402164 ps
CPU time 99.54 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:41:36 PM PDT 24
Peak memory 236560 kb
Host smart-f88959bc-d75c-458d-b3dc-88d6cf7ef558
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297153993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.297153993
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1023160916
Short name T295
Test name
Test status
Simulation time 8572353454 ps
CPU time 24.63 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:40:12 PM PDT 24
Peak memory 213404 kb
Host smart-1d54635c-9f83-46cd-be2e-27fabf85d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023160916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1023160916
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.826871013
Short name T249
Test name
Test status
Simulation time 17576756107 ps
CPU time 81.7 seconds
Started Jun 29 04:39:46 PM PDT 24
Finished Jun 29 04:41:08 PM PDT 24
Peak memory 219352 kb
Host smart-ee010290-67b1-4db1-9955-215ed5c721af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826871013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.826871013
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3420787934
Short name T264
Test name
Test status
Simulation time 1761135866 ps
CPU time 15.37 seconds
Started Jun 29 04:40:43 PM PDT 24
Finished Jun 29 04:40:58 PM PDT 24
Peak memory 211288 kb
Host smart-fe0e22ed-1c4f-45a4-bb41-6c768148be34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420787934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3420787934
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2428490853
Short name T291
Test name
Test status
Simulation time 422166346477 ps
CPU time 224.71 seconds
Started Jun 29 04:40:42 PM PDT 24
Finished Jun 29 04:44:27 PM PDT 24
Peak memory 212480 kb
Host smart-f11d84a0-ed7b-4b78-beb7-f1b5ec4856b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428490853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2428490853
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1250989668
Short name T156
Test name
Test status
Simulation time 14049508674 ps
CPU time 30.43 seconds
Started Jun 29 04:40:43 PM PDT 24
Finished Jun 29 04:41:14 PM PDT 24
Peak memory 212228 kb
Host smart-fdee276d-59bd-4f17-a7ab-cdf084281fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250989668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1250989668
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4175883662
Short name T355
Test name
Test status
Simulation time 2805419515 ps
CPU time 13.6 seconds
Started Jun 29 04:40:43 PM PDT 24
Finished Jun 29 04:40:57 PM PDT 24
Peak memory 211324 kb
Host smart-308edff7-b3b7-45b1-9ce7-ba9cc060f963
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4175883662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4175883662
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.924100322
Short name T294
Test name
Test status
Simulation time 3433170515 ps
CPU time 28.52 seconds
Started Jun 29 04:40:43 PM PDT 24
Finished Jun 29 04:41:12 PM PDT 24
Peak memory 211324 kb
Host smart-1ed42451-cc23-41ec-b077-3014f6f648ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924100322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.924100322
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1341972688
Short name T305
Test name
Test status
Simulation time 7751243144 ps
CPU time 42.75 seconds
Started Jun 29 04:40:41 PM PDT 24
Finished Jun 29 04:41:24 PM PDT 24
Peak memory 214328 kb
Host smart-e7dd5b42-c96b-4d6c-9d41-eb377cb6b7d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341972688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1341972688
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2326145326
Short name T38
Test name
Test status
Simulation time 5729646758 ps
CPU time 9.98 seconds
Started Jun 29 04:40:44 PM PDT 24
Finished Jun 29 04:40:54 PM PDT 24
Peak memory 211348 kb
Host smart-34699b3e-c148-4a3c-8ab0-5403269e75dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326145326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2326145326
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1985751280
Short name T325
Test name
Test status
Simulation time 25888557370 ps
CPU time 138.85 seconds
Started Jun 29 04:40:43 PM PDT 24
Finished Jun 29 04:43:02 PM PDT 24
Peak memory 236720 kb
Host smart-25a0b24c-6cef-45b1-a5d6-a37e8ba1ca99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985751280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1985751280
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3342818262
Short name T309
Test name
Test status
Simulation time 7657937379 ps
CPU time 25.24 seconds
Started Jun 29 04:40:42 PM PDT 24
Finished Jun 29 04:41:07 PM PDT 24
Peak memory 212432 kb
Host smart-60678bbf-cee7-456b-99ef-a195c55d702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342818262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3342818262
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2333625340
Short name T267
Test name
Test status
Simulation time 189292837 ps
CPU time 5.62 seconds
Started Jun 29 04:40:44 PM PDT 24
Finished Jun 29 04:40:50 PM PDT 24
Peak memory 211340 kb
Host smart-11d393be-2b3f-4d60-9527-265d873337de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2333625340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2333625340
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4261835543
Short name T138
Test name
Test status
Simulation time 535740552 ps
CPU time 14.12 seconds
Started Jun 29 04:40:41 PM PDT 24
Finished Jun 29 04:40:55 PM PDT 24
Peak memory 211340 kb
Host smart-6a64edd9-c97e-4cdd-b060-60479e4cad83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261835543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4261835543
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2635529885
Short name T280
Test name
Test status
Simulation time 15635778776 ps
CPU time 49.07 seconds
Started Jun 29 04:40:43 PM PDT 24
Finished Jun 29 04:41:33 PM PDT 24
Peak memory 214736 kb
Host smart-b1d5207a-a002-407b-9969-a1a276a6baeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635529885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2635529885
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3842356280
Short name T316
Test name
Test status
Simulation time 1781728079 ps
CPU time 9.81 seconds
Started Jun 29 04:40:51 PM PDT 24
Finished Jun 29 04:41:01 PM PDT 24
Peak memory 211208 kb
Host smart-5069de85-b2ed-4237-91fb-1b363e87b42e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842356280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3842356280
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.600912917
Short name T340
Test name
Test status
Simulation time 6356119715 ps
CPU time 154.69 seconds
Started Jun 29 04:40:43 PM PDT 24
Finished Jun 29 04:43:19 PM PDT 24
Peak memory 227688 kb
Host smart-181c6713-7d76-431b-b7c8-e8bbddea0a3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600912917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.600912917
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3379431304
Short name T234
Test name
Test status
Simulation time 12458650826 ps
CPU time 28.55 seconds
Started Jun 29 04:40:41 PM PDT 24
Finished Jun 29 04:41:10 PM PDT 24
Peak memory 212056 kb
Host smart-878c6080-8806-4dca-8491-ed957a97bc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379431304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3379431304
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.460453202
Short name T323
Test name
Test status
Simulation time 1474483399 ps
CPU time 13.56 seconds
Started Jun 29 04:40:43 PM PDT 24
Finished Jun 29 04:40:57 PM PDT 24
Peak memory 211336 kb
Host smart-36a74868-a097-4b07-8a66-bf16a8ca86e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460453202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.460453202
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3539004132
Short name T122
Test name
Test status
Simulation time 2735958497 ps
CPU time 24.61 seconds
Started Jun 29 04:40:42 PM PDT 24
Finished Jun 29 04:41:07 PM PDT 24
Peak memory 213016 kb
Host smart-cc3c545f-d2e3-4eab-85a6-fc65146856ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539004132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3539004132
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3316519152
Short name T208
Test name
Test status
Simulation time 14066473334 ps
CPU time 39.91 seconds
Started Jun 29 04:40:44 PM PDT 24
Finished Jun 29 04:41:25 PM PDT 24
Peak memory 214280 kb
Host smart-fa546f50-6c2d-45c0-879b-c4efd1f3d245
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316519152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3316519152
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1980969820
Short name T32
Test name
Test status
Simulation time 85711618 ps
CPU time 4.37 seconds
Started Jun 29 04:40:52 PM PDT 24
Finished Jun 29 04:40:57 PM PDT 24
Peak memory 211276 kb
Host smart-dee3576c-4cc5-4f0e-96d6-598d6af3481b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980969820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1980969820
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3078253293
Short name T228
Test name
Test status
Simulation time 29869372873 ps
CPU time 308.31 seconds
Started Jun 29 04:40:50 PM PDT 24
Finished Jun 29 04:45:59 PM PDT 24
Peak memory 228548 kb
Host smart-f05c53b0-cef6-427d-84c5-71d458a37f28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078253293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3078253293
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1474149809
Short name T334
Test name
Test status
Simulation time 15276942286 ps
CPU time 30.16 seconds
Started Jun 29 04:40:49 PM PDT 24
Finished Jun 29 04:41:20 PM PDT 24
Peak memory 212284 kb
Host smart-a6dcdf12-a6bb-4a80-8ce9-14ff830a9be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474149809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1474149809
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1402007853
Short name T188
Test name
Test status
Simulation time 141439543 ps
CPU time 6.5 seconds
Started Jun 29 04:40:50 PM PDT 24
Finished Jun 29 04:40:57 PM PDT 24
Peak memory 211340 kb
Host smart-ea530ae7-4583-4400-bfcc-18bb654e69fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402007853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1402007853
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2034624776
Short name T167
Test name
Test status
Simulation time 700953655 ps
CPU time 10.54 seconds
Started Jun 29 04:40:50 PM PDT 24
Finished Jun 29 04:41:02 PM PDT 24
Peak memory 213612 kb
Host smart-7aa29f65-3542-43a9-b646-d134d99b8b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034624776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2034624776
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3584727453
Short name T268
Test name
Test status
Simulation time 2571652638 ps
CPU time 13.45 seconds
Started Jun 29 04:40:49 PM PDT 24
Finished Jun 29 04:41:03 PM PDT 24
Peak memory 211800 kb
Host smart-d83c989e-901d-4a5d-afd7-c4b5b3b2b028
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584727453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3584727453
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1180652558
Short name T312
Test name
Test status
Simulation time 820927665 ps
CPU time 8.81 seconds
Started Jun 29 04:40:51 PM PDT 24
Finished Jun 29 04:41:00 PM PDT 24
Peak memory 211288 kb
Host smart-183125f2-1219-4f5b-ac91-d314d71b73f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180652558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1180652558
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3496798631
Short name T18
Test name
Test status
Simulation time 3394100857 ps
CPU time 115.93 seconds
Started Jun 29 04:40:53 PM PDT 24
Finished Jun 29 04:42:49 PM PDT 24
Peak memory 238804 kb
Host smart-88af8163-d0a4-410a-89f7-ac07d67d8c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496798631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3496798631
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1273897572
Short name T196
Test name
Test status
Simulation time 2454235950 ps
CPU time 23.27 seconds
Started Jun 29 04:40:50 PM PDT 24
Finished Jun 29 04:41:14 PM PDT 24
Peak memory 212056 kb
Host smart-380d0b66-5e82-4349-bfd4-f37c4d420d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273897572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1273897572
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1730405944
Short name T170
Test name
Test status
Simulation time 3661907329 ps
CPU time 9.69 seconds
Started Jun 29 04:40:51 PM PDT 24
Finished Jun 29 04:41:02 PM PDT 24
Peak memory 211324 kb
Host smart-656600c7-d1ba-4e26-8c6d-fc717ee3bd19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730405944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1730405944
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.314305925
Short name T16
Test name
Test status
Simulation time 9208101984 ps
CPU time 25.84 seconds
Started Jun 29 04:40:48 PM PDT 24
Finished Jun 29 04:41:15 PM PDT 24
Peak memory 214164 kb
Host smart-61d88646-7966-420f-b10e-181fbcda57c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314305925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.314305925
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2997836553
Short name T353
Test name
Test status
Simulation time 6543599568 ps
CPU time 16.05 seconds
Started Jun 29 04:40:48 PM PDT 24
Finished Jun 29 04:41:04 PM PDT 24
Peak memory 211236 kb
Host smart-b1b34e1c-3303-4af9-b1e9-3e7ed8595036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997836553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2997836553
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.883222174
Short name T317
Test name
Test status
Simulation time 472328258 ps
CPU time 7.28 seconds
Started Jun 29 04:40:52 PM PDT 24
Finished Jun 29 04:41:00 PM PDT 24
Peak memory 211212 kb
Host smart-98717db1-e1eb-4a9d-84ab-44b1fd32c657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883222174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.883222174
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3530122150
Short name T253
Test name
Test status
Simulation time 8334958098 ps
CPU time 81.35 seconds
Started Jun 29 04:40:52 PM PDT 24
Finished Jun 29 04:42:14 PM PDT 24
Peak memory 233776 kb
Host smart-a62196b6-aadd-46f0-9370-c975f822285a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530122150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3530122150
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.979092029
Short name T335
Test name
Test status
Simulation time 4855590474 ps
CPU time 15.31 seconds
Started Jun 29 04:40:49 PM PDT 24
Finished Jun 29 04:41:04 PM PDT 24
Peak memory 212324 kb
Host smart-114c81f6-a97b-4142-ac2b-c36d0ecc84d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979092029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.979092029
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.824145815
Short name T271
Test name
Test status
Simulation time 1590747979 ps
CPU time 9.17 seconds
Started Jun 29 04:40:50 PM PDT 24
Finished Jun 29 04:41:00 PM PDT 24
Peak memory 211264 kb
Host smart-67e5c119-f27e-4b53-9fb4-4ecae3fb0bfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824145815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.824145815
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1521330824
Short name T344
Test name
Test status
Simulation time 6748981471 ps
CPU time 32.18 seconds
Started Jun 29 04:40:50 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 214072 kb
Host smart-e0f548f1-8dfc-4dc6-865b-3232888ed51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521330824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1521330824
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2751611316
Short name T78
Test name
Test status
Simulation time 4027965727 ps
CPU time 44.14 seconds
Started Jun 29 04:40:50 PM PDT 24
Finished Jun 29 04:41:35 PM PDT 24
Peak memory 213100 kb
Host smart-0cec0a58-16d7-45c1-837d-8cad9679e2ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751611316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2751611316
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3395520897
Short name T229
Test name
Test status
Simulation time 346835221 ps
CPU time 4.31 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:41:06 PM PDT 24
Peak memory 211200 kb
Host smart-abbf6174-fb65-4c66-80ad-9526681c0025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395520897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3395520897
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3544114857
Short name T210
Test name
Test status
Simulation time 23850429365 ps
CPU time 285.66 seconds
Started Jun 29 04:40:51 PM PDT 24
Finished Jun 29 04:45:37 PM PDT 24
Peak memory 212508 kb
Host smart-a9a2c54b-e821-418b-a2ea-24125d719482
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544114857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3544114857
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2244277939
Short name T27
Test name
Test status
Simulation time 5309887624 ps
CPU time 25 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:41:27 PM PDT 24
Peak memory 212128 kb
Host smart-070576c9-6fc7-476e-83bd-abcc36dbd50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244277939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2244277939
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1279210247
Short name T304
Test name
Test status
Simulation time 553350590 ps
CPU time 6.35 seconds
Started Jun 29 04:40:51 PM PDT 24
Finished Jun 29 04:40:58 PM PDT 24
Peak memory 211336 kb
Host smart-88e6ab1e-2900-4200-add8-9d7f698b7b12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279210247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1279210247
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2828242291
Short name T120
Test name
Test status
Simulation time 6816730755 ps
CPU time 22.04 seconds
Started Jun 29 04:40:49 PM PDT 24
Finished Jun 29 04:41:12 PM PDT 24
Peak memory 214184 kb
Host smart-3c22e5d0-ee3a-4b09-8b19-34d421c49caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828242291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2828242291
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1553862090
Short name T203
Test name
Test status
Simulation time 420345207 ps
CPU time 19.64 seconds
Started Jun 29 04:40:52 PM PDT 24
Finished Jun 29 04:41:12 PM PDT 24
Peak memory 215132 kb
Host smart-b0adaa23-eaa0-4a02-8db1-e17a13dd01e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553862090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1553862090
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1748410874
Short name T322
Test name
Test status
Simulation time 3426922047 ps
CPU time 14.17 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:41:16 PM PDT 24
Peak memory 211348 kb
Host smart-7790e4f9-1b8e-45b6-a9fb-8a1852cce09c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748410874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1748410874
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3237259940
Short name T192
Test name
Test status
Simulation time 15821791745 ps
CPU time 157.28 seconds
Started Jun 29 04:41:00 PM PDT 24
Finished Jun 29 04:43:38 PM PDT 24
Peak memory 225084 kb
Host smart-3603244f-9668-43df-b004-5e9c34e33d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237259940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3237259940
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2836922353
Short name T298
Test name
Test status
Simulation time 14949286596 ps
CPU time 24.95 seconds
Started Jun 29 04:41:02 PM PDT 24
Finished Jun 29 04:41:27 PM PDT 24
Peak memory 213108 kb
Host smart-b67d76ec-3a39-4b50-bc25-ee1ceaa0f677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836922353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2836922353
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1374577538
Short name T1
Test name
Test status
Simulation time 674069165 ps
CPU time 7.45 seconds
Started Jun 29 04:41:03 PM PDT 24
Finished Jun 29 04:41:11 PM PDT 24
Peak memory 211268 kb
Host smart-3fc95759-397d-4f0d-bd6a-936b88579b70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374577538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1374577538
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.4039470598
Short name T313
Test name
Test status
Simulation time 6999808548 ps
CPU time 40.05 seconds
Started Jun 29 04:41:00 PM PDT 24
Finished Jun 29 04:41:41 PM PDT 24
Peak memory 213312 kb
Host smart-d5c64b9c-ba03-474f-8d1a-cdf8cccad1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039470598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4039470598
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3911885646
Short name T215
Test name
Test status
Simulation time 2462936978 ps
CPU time 18.86 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:41:21 PM PDT 24
Peak memory 214252 kb
Host smart-912aadb7-6cf3-4283-9242-f4152e9f11fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911885646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3911885646
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.446157430
Short name T359
Test name
Test status
Simulation time 1596347405 ps
CPU time 9.13 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:41:11 PM PDT 24
Peak memory 211248 kb
Host smart-9af6fc0b-0dff-449e-8a3f-1ef26967ddb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446157430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.446157430
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2214610157
Short name T39
Test name
Test status
Simulation time 23350857358 ps
CPU time 128.65 seconds
Started Jun 29 04:41:05 PM PDT 24
Finished Jun 29 04:43:14 PM PDT 24
Peak memory 237144 kb
Host smart-7f6ec698-11d9-4eb4-9c52-2346b6e9292b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214610157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2214610157
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1054982083
Short name T92
Test name
Test status
Simulation time 8061763152 ps
CPU time 31.65 seconds
Started Jun 29 04:41:02 PM PDT 24
Finished Jun 29 04:41:34 PM PDT 24
Peak memory 212884 kb
Host smart-edd44f88-2eb6-4405-8074-2d1152c3b711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054982083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1054982083
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4220382445
Short name T284
Test name
Test status
Simulation time 430554308 ps
CPU time 7.89 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:41:10 PM PDT 24
Peak memory 211340 kb
Host smart-baac69f4-5a36-44dd-9f8f-6da5b9890cb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220382445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4220382445
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3585845955
Short name T239
Test name
Test status
Simulation time 11025710866 ps
CPU time 30.56 seconds
Started Jun 29 04:41:03 PM PDT 24
Finished Jun 29 04:41:34 PM PDT 24
Peak memory 214428 kb
Host smart-42c5e5a1-f865-4253-99f7-bd9569594a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585845955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3585845955
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4036970071
Short name T337
Test name
Test status
Simulation time 6422538872 ps
CPU time 54.99 seconds
Started Jun 29 04:41:00 PM PDT 24
Finished Jun 29 04:41:56 PM PDT 24
Peak memory 216780 kb
Host smart-62e23c80-2bd3-4066-9d4a-4fb725569015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036970071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4036970071
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4252169029
Short name T59
Test name
Test status
Simulation time 25216542612 ps
CPU time 3062.47 seconds
Started Jun 29 04:41:04 PM PDT 24
Finished Jun 29 05:32:07 PM PDT 24
Peak memory 235648 kb
Host smart-25880c5e-fb0b-4d9b-8ea8-52cf609fbb75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252169029 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4252169029
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.672229847
Short name T207
Test name
Test status
Simulation time 10514025990 ps
CPU time 15.78 seconds
Started Jun 29 04:41:03 PM PDT 24
Finished Jun 29 04:41:19 PM PDT 24
Peak memory 211348 kb
Host smart-fa4e9ca3-d262-4cb2-84ff-ee177add00d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672229847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.672229847
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.670020592
Short name T42
Test name
Test status
Simulation time 1566649338 ps
CPU time 89.4 seconds
Started Jun 29 04:41:02 PM PDT 24
Finished Jun 29 04:42:32 PM PDT 24
Peak memory 214500 kb
Host smart-01a75f76-fcfc-47e4-bce8-ad382136f0d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670020592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.670020592
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1007982572
Short name T209
Test name
Test status
Simulation time 341081530 ps
CPU time 9.53 seconds
Started Jun 29 04:41:03 PM PDT 24
Finished Jun 29 04:41:13 PM PDT 24
Peak memory 211904 kb
Host smart-cf8d1177-4907-4edb-b261-41cbf6f8bd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007982572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1007982572
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2578596572
Short name T121
Test name
Test status
Simulation time 1174264404 ps
CPU time 11.96 seconds
Started Jun 29 04:41:02 PM PDT 24
Finished Jun 29 04:41:14 PM PDT 24
Peak memory 211292 kb
Host smart-479dd45a-e9f7-468c-b135-5a5638acd0a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578596572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2578596572
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.413679173
Short name T345
Test name
Test status
Simulation time 8035469337 ps
CPU time 31.91 seconds
Started Jun 29 04:41:00 PM PDT 24
Finished Jun 29 04:41:32 PM PDT 24
Peak memory 214472 kb
Host smart-78e839bb-51c6-41e1-b4d2-f8007a1e39b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413679173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.413679173
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2108031508
Short name T293
Test name
Test status
Simulation time 10419608091 ps
CPU time 58.67 seconds
Started Jun 29 04:41:00 PM PDT 24
Finished Jun 29 04:41:59 PM PDT 24
Peak memory 216852 kb
Host smart-e73a273e-922e-40c7-b969-13f7b84abbba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108031508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2108031508
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.724805792
Short name T144
Test name
Test status
Simulation time 89150666 ps
CPU time 4.34 seconds
Started Jun 29 04:39:57 PM PDT 24
Finished Jun 29 04:40:02 PM PDT 24
Peak memory 211288 kb
Host smart-ca8f93d4-d049-44d0-a075-1bd3e6551b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724805792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.724805792
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4053749051
Short name T248
Test name
Test status
Simulation time 38050216721 ps
CPU time 367.34 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:46:03 PM PDT 24
Peak memory 240820 kb
Host smart-9f4b43ca-2a9a-4948-b3df-ee1f7458b41d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053749051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4053749051
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3854194590
Short name T35
Test name
Test status
Simulation time 9216200072 ps
CPU time 22.55 seconds
Started Jun 29 04:39:56 PM PDT 24
Finished Jun 29 04:40:20 PM PDT 24
Peak memory 211408 kb
Host smart-98b283c1-d1ef-49bd-bd9e-04ab8d03ffd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854194590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3854194590
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1505744802
Short name T151
Test name
Test status
Simulation time 11964636749 ps
CPU time 11.8 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:40:08 PM PDT 24
Peak memory 211324 kb
Host smart-4b75aa06-2452-4cfc-a10f-28d8b4446921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505744802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1505744802
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1985450919
Short name T21
Test name
Test status
Simulation time 6344142291 ps
CPU time 106.83 seconds
Started Jun 29 04:39:59 PM PDT 24
Finished Jun 29 04:41:46 PM PDT 24
Peak memory 236772 kb
Host smart-32cda5f4-9d0e-4de6-aebb-17d78c7ad13a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985450919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1985450919
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2581297989
Short name T307
Test name
Test status
Simulation time 16536641561 ps
CPU time 24.23 seconds
Started Jun 29 04:39:53 PM PDT 24
Finished Jun 29 04:40:19 PM PDT 24
Peak memory 213836 kb
Host smart-63fb8abc-d260-4d57-a5ef-50f73960c8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581297989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2581297989
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3355810073
Short name T2
Test name
Test status
Simulation time 25355221993 ps
CPU time 27.22 seconds
Started Jun 29 04:39:56 PM PDT 24
Finished Jun 29 04:40:24 PM PDT 24
Peak memory 215748 kb
Host smart-4d0cfa57-6c9b-4918-a620-cc0d0cdce9aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355810073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3355810073
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3153606772
Short name T275
Test name
Test status
Simulation time 521392304 ps
CPU time 5.17 seconds
Started Jun 29 04:41:02 PM PDT 24
Finished Jun 29 04:41:08 PM PDT 24
Peak memory 211212 kb
Host smart-a3bc0ffe-d3c6-4f6b-bce7-3d65f6505d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153606772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3153606772
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4066450634
Short name T336
Test name
Test status
Simulation time 18312095140 ps
CPU time 129.66 seconds
Started Jun 29 04:41:03 PM PDT 24
Finished Jun 29 04:43:13 PM PDT 24
Peak memory 237496 kb
Host smart-869b4f95-1e84-407f-bb6e-6de1136cbeb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066450634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4066450634
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1700950346
Short name T262
Test name
Test status
Simulation time 1085148605 ps
CPU time 16.47 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:41:18 PM PDT 24
Peak memory 211936 kb
Host smart-af87cdec-ea2b-4130-8e3a-e4e590ea93f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700950346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1700950346
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1662405951
Short name T232
Test name
Test status
Simulation time 1197342656 ps
CPU time 10.66 seconds
Started Jun 29 04:41:02 PM PDT 24
Finished Jun 29 04:41:13 PM PDT 24
Peak memory 211264 kb
Host smart-84601ace-8d15-4ad5-883d-0d2da8c928c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662405951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1662405951
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3328930136
Short name T161
Test name
Test status
Simulation time 9758054463 ps
CPU time 34.78 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:41:36 PM PDT 24
Peak memory 214232 kb
Host smart-cdb28c15-39b5-4142-8473-1edac863b1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328930136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3328930136
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1761776026
Short name T143
Test name
Test status
Simulation time 8296970576 ps
CPU time 71.36 seconds
Started Jun 29 04:41:02 PM PDT 24
Finished Jun 29 04:42:14 PM PDT 24
Peak memory 214968 kb
Host smart-112c33c5-f0bf-4f95-8708-69616e3d6cf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761776026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1761776026
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4040929658
Short name T357
Test name
Test status
Simulation time 1912341206 ps
CPU time 15.81 seconds
Started Jun 29 04:41:13 PM PDT 24
Finished Jun 29 04:41:30 PM PDT 24
Peak memory 211224 kb
Host smart-74a91a58-1b8c-47b1-8c8a-c63145e99a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040929658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4040929658
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1731843836
Short name T221
Test name
Test status
Simulation time 2591703739 ps
CPU time 102.56 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:42:45 PM PDT 24
Peak memory 212576 kb
Host smart-df355200-1a8e-4462-bbb3-f0ddb2ce3279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731843836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1731843836
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1101120398
Short name T260
Test name
Test status
Simulation time 25502146908 ps
CPU time 23.48 seconds
Started Jun 29 04:41:00 PM PDT 24
Finished Jun 29 04:41:25 PM PDT 24
Peak memory 212156 kb
Host smart-5a059386-969a-4592-b1b7-dc21658b3fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101120398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1101120398
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3177675684
Short name T36
Test name
Test status
Simulation time 4824998210 ps
CPU time 12.48 seconds
Started Jun 29 04:41:01 PM PDT 24
Finished Jun 29 04:41:14 PM PDT 24
Peak memory 211320 kb
Host smart-d6b34102-a5cc-4dea-a64f-a9106a87f14d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177675684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3177675684
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2447609185
Short name T193
Test name
Test status
Simulation time 1298122713 ps
CPU time 15.24 seconds
Started Jun 29 04:41:02 PM PDT 24
Finished Jun 29 04:41:18 PM PDT 24
Peak memory 212924 kb
Host smart-4d9925b7-e2e8-4410-9bb8-0222df6f5619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447609185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2447609185
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3844822677
Short name T350
Test name
Test status
Simulation time 8229273250 ps
CPU time 35.91 seconds
Started Jun 29 04:41:03 PM PDT 24
Finished Jun 29 04:41:40 PM PDT 24
Peak memory 216388 kb
Host smart-13471958-1dc6-4301-a90d-149473e7de0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844822677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3844822677
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.165247064
Short name T25
Test name
Test status
Simulation time 3610038827 ps
CPU time 9.97 seconds
Started Jun 29 04:41:13 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 211212 kb
Host smart-436487f3-1e2a-434e-9a29-1a4c13fe9738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165247064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.165247064
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.565067901
Short name T343
Test name
Test status
Simulation time 31273331722 ps
CPU time 307.27 seconds
Started Jun 29 04:41:09 PM PDT 24
Finished Jun 29 04:46:17 PM PDT 24
Peak memory 233648 kb
Host smart-38d567af-fe5d-44bc-8a49-c2435f1997c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565067901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.565067901
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.334000052
Short name T186
Test name
Test status
Simulation time 6506390268 ps
CPU time 15.82 seconds
Started Jun 29 04:41:09 PM PDT 24
Finished Jun 29 04:41:25 PM PDT 24
Peak memory 212188 kb
Host smart-4bb3ecc2-2cc0-4e14-abe5-e6ed87f9a4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334000052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.334000052
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.888343673
Short name T299
Test name
Test status
Simulation time 3266488062 ps
CPU time 15.09 seconds
Started Jun 29 04:41:13 PM PDT 24
Finished Jun 29 04:41:28 PM PDT 24
Peak memory 211396 kb
Host smart-806666c9-83c2-4d50-8a88-a1afa6ba44b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888343673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.888343673
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.932518638
Short name T287
Test name
Test status
Simulation time 3448980244 ps
CPU time 28.83 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 04:41:41 PM PDT 24
Peak memory 212704 kb
Host smart-b5452e88-f732-4ef6-9764-a4354e898cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932518638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.932518638
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.680726557
Short name T301
Test name
Test status
Simulation time 4171740319 ps
CPU time 50.43 seconds
Started Jun 29 04:41:11 PM PDT 24
Finished Jun 29 04:42:03 PM PDT 24
Peak memory 215912 kb
Host smart-7bff8e96-a720-4f68-9dab-9283b6fda926
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680726557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.680726557
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4258582727
Short name T159
Test name
Test status
Simulation time 1397587477 ps
CPU time 12.47 seconds
Started Jun 29 04:41:10 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 211288 kb
Host smart-9be4b9d6-226b-4f09-9c82-57c679f4847d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258582727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4258582727
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2160824751
Short name T231
Test name
Test status
Simulation time 67079122570 ps
CPU time 203.66 seconds
Started Jun 29 04:41:13 PM PDT 24
Finished Jun 29 04:44:37 PM PDT 24
Peak memory 234816 kb
Host smart-89c0c79b-7fad-4faf-9cd0-5ff64cf9a0dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160824751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2160824751
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2381670602
Short name T182
Test name
Test status
Simulation time 340180093 ps
CPU time 11.71 seconds
Started Jun 29 04:41:11 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 211876 kb
Host smart-503a1c9c-3f65-4c34-bd36-62a9c46eaca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381670602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2381670602
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3396059547
Short name T329
Test name
Test status
Simulation time 602054502 ps
CPU time 5.52 seconds
Started Jun 29 04:41:16 PM PDT 24
Finished Jun 29 04:41:22 PM PDT 24
Peak memory 211336 kb
Host smart-b6e1630f-bf83-4382-8e77-dc03377a30c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396059547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3396059547
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3373432882
Short name T199
Test name
Test status
Simulation time 2271930820 ps
CPU time 10.44 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 214128 kb
Host smart-ef5715d9-b1d1-463f-ae21-5751204230f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373432882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3373432882
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1803994480
Short name T155
Test name
Test status
Simulation time 1118871601 ps
CPU time 21.18 seconds
Started Jun 29 04:41:11 PM PDT 24
Finished Jun 29 04:41:32 PM PDT 24
Peak memory 216376 kb
Host smart-a7ea7ed5-e102-42b6-a660-4c81a02b28bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803994480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1803994480
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3219758517
Short name T148
Test name
Test status
Simulation time 3183640560 ps
CPU time 13.84 seconds
Started Jun 29 04:41:08 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 211284 kb
Host smart-3a07b2f7-2241-4653-b7bc-b9b70016d36d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219758517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3219758517
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4230862617
Short name T254
Test name
Test status
Simulation time 54214347102 ps
CPU time 280.73 seconds
Started Jun 29 04:41:13 PM PDT 24
Finished Jun 29 04:45:54 PM PDT 24
Peak memory 212580 kb
Host smart-886f2341-f7c8-4d0d-a1d1-06a31133b1d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230862617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.4230862617
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1196861012
Short name T281
Test name
Test status
Simulation time 2774568591 ps
CPU time 24.16 seconds
Started Jun 29 04:41:09 PM PDT 24
Finished Jun 29 04:41:34 PM PDT 24
Peak memory 212296 kb
Host smart-c89b1744-dbfb-44b3-be33-e16dcca2e39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196861012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1196861012
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1168900062
Short name T171
Test name
Test status
Simulation time 432907483 ps
CPU time 8.28 seconds
Started Jun 29 04:41:09 PM PDT 24
Finished Jun 29 04:41:18 PM PDT 24
Peak memory 211300 kb
Host smart-ec39b188-4709-4cda-9c29-8e2a5122d1ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168900062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1168900062
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3664723550
Short name T53
Test name
Test status
Simulation time 4123206463 ps
CPU time 22.12 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 04:41:35 PM PDT 24
Peak memory 213708 kb
Host smart-8baeda4b-b1d3-4cc8-8b5f-147673843875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664723550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3664723550
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3957275905
Short name T77
Test name
Test status
Simulation time 1143719217 ps
CPU time 15.14 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 04:41:28 PM PDT 24
Peak memory 211308 kb
Host smart-8f6d5307-8da5-4cc6-b715-a244b02ca982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957275905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3957275905
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1392907005
Short name T333
Test name
Test status
Simulation time 788581167 ps
CPU time 9.51 seconds
Started Jun 29 04:41:10 PM PDT 24
Finished Jun 29 04:41:20 PM PDT 24
Peak memory 211216 kb
Host smart-8278de60-6c15-444b-92db-d4f46d543593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392907005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1392907005
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1404873725
Short name T220
Test name
Test status
Simulation time 32330523782 ps
CPU time 297.8 seconds
Started Jun 29 04:41:13 PM PDT 24
Finished Jun 29 04:46:11 PM PDT 24
Peak memory 212596 kb
Host smart-6cdeee69-ea5e-4149-aaea-ef51210d3f95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404873725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1404873725
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3914937321
Short name T153
Test name
Test status
Simulation time 10928531707 ps
CPU time 23.75 seconds
Started Jun 29 04:41:09 PM PDT 24
Finished Jun 29 04:41:33 PM PDT 24
Peak memory 212156 kb
Host smart-07598e36-c057-4b4e-833b-e7373cfa26d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914937321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3914937321
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4170615747
Short name T99
Test name
Test status
Simulation time 120117712 ps
CPU time 5.45 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 04:41:18 PM PDT 24
Peak memory 211340 kb
Host smart-9fd64303-0039-4f2c-a79a-5d1cc4896918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170615747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4170615747
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.385799569
Short name T226
Test name
Test status
Simulation time 3531146851 ps
CPU time 31.94 seconds
Started Jun 29 04:41:09 PM PDT 24
Finished Jun 29 04:41:41 PM PDT 24
Peak memory 213404 kb
Host smart-e5c1fce6-7e77-4d5f-aa59-62ffc85b5632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385799569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.385799569
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1075664057
Short name T136
Test name
Test status
Simulation time 1607492453 ps
CPU time 22.46 seconds
Started Jun 29 04:41:15 PM PDT 24
Finished Jun 29 04:41:38 PM PDT 24
Peak memory 213564 kb
Host smart-83a700c6-972b-4725-8f71-af531faacb17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075664057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1075664057
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1696027418
Short name T166
Test name
Test status
Simulation time 2324165622 ps
CPU time 13.33 seconds
Started Jun 29 04:41:09 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 211344 kb
Host smart-4c4b8f9a-9a68-4e16-bf6b-ab31b9af082f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696027418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1696027418
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.235681458
Short name T296
Test name
Test status
Simulation time 43852119849 ps
CPU time 245.75 seconds
Started Jun 29 04:41:10 PM PDT 24
Finished Jun 29 04:45:16 PM PDT 24
Peak memory 237756 kb
Host smart-d09b6ff5-c15e-46d1-bbca-e4fe2ca87666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235681458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.235681458
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3055407698
Short name T124
Test name
Test status
Simulation time 4213197653 ps
CPU time 32.08 seconds
Started Jun 29 04:41:17 PM PDT 24
Finished Jun 29 04:41:49 PM PDT 24
Peak memory 212108 kb
Host smart-f73dc57f-a629-447f-9aae-a0fdf64cdb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055407698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3055407698
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1941465973
Short name T235
Test name
Test status
Simulation time 815332840 ps
CPU time 10.55 seconds
Started Jun 29 04:41:11 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 211336 kb
Host smart-fa286675-5d93-40bc-bf65-a1f2c29f49d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941465973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1941465973
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3223551769
Short name T256
Test name
Test status
Simulation time 12325468888 ps
CPU time 30.4 seconds
Started Jun 29 04:41:10 PM PDT 24
Finished Jun 29 04:41:41 PM PDT 24
Peak memory 214032 kb
Host smart-75a34bfd-ba79-4a2d-868d-a6982784850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223551769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3223551769
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.857316824
Short name T257
Test name
Test status
Simulation time 1723664896 ps
CPU time 25.8 seconds
Started Jun 29 04:41:11 PM PDT 24
Finished Jun 29 04:41:37 PM PDT 24
Peak memory 215424 kb
Host smart-6338a7a3-30d9-428b-af4f-6282c2c2d251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857316824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.857316824
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3020734670
Short name T134
Test name
Test status
Simulation time 346270731 ps
CPU time 4.27 seconds
Started Jun 29 04:41:15 PM PDT 24
Finished Jun 29 04:41:20 PM PDT 24
Peak memory 211288 kb
Host smart-7ef492b5-ff51-4054-b7b8-1e3c117fcc71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020734670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3020734670
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2188060641
Short name T45
Test name
Test status
Simulation time 17450221528 ps
CPU time 139.8 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 04:43:33 PM PDT 24
Peak memory 237792 kb
Host smart-c531b81a-fc0c-4e1b-ab0c-2cbda4736e06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188060641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2188060641
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1276789788
Short name T339
Test name
Test status
Simulation time 1934101231 ps
CPU time 21.22 seconds
Started Jun 29 04:41:11 PM PDT 24
Finished Jun 29 04:41:32 PM PDT 24
Peak memory 211952 kb
Host smart-926c13ec-aa9d-48a7-a182-1f800aa8b11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276789788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1276789788
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2453214037
Short name T9
Test name
Test status
Simulation time 32993234095 ps
CPU time 15.14 seconds
Started Jun 29 04:41:08 PM PDT 24
Finished Jun 29 04:41:23 PM PDT 24
Peak memory 211368 kb
Host smart-112deaab-b383-4af8-9712-51d10c99a706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453214037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2453214037
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3060581902
Short name T6
Test name
Test status
Simulation time 5554087205 ps
CPU time 28.13 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 04:41:41 PM PDT 24
Peak memory 214352 kb
Host smart-09517bd4-57c8-42b5-b011-215a5c29a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060581902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3060581902
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1530552575
Short name T315
Test name
Test status
Simulation time 1624581413 ps
CPU time 16.94 seconds
Started Jun 29 04:41:10 PM PDT 24
Finished Jun 29 04:41:28 PM PDT 24
Peak memory 211648 kb
Host smart-b6b841ca-d9b8-42e6-ab35-04dfc4d33f37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530552575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1530552575
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.577926236
Short name T13
Test name
Test status
Simulation time 105827243693 ps
CPU time 5838.37 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 06:18:31 PM PDT 24
Peak memory 230100 kb
Host smart-3c6e4fb7-9987-4f9e-b6f5-e83669163d71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577926236 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.577926236
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2504921989
Short name T352
Test name
Test status
Simulation time 852425091 ps
CPU time 9.34 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 04:41:22 PM PDT 24
Peak memory 211236 kb
Host smart-79556bc2-a109-493b-b0fd-49afdd3dbc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504921989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2504921989
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1555847181
Short name T40
Test name
Test status
Simulation time 268508565913 ps
CPU time 225.14 seconds
Started Jun 29 04:41:10 PM PDT 24
Finished Jun 29 04:44:56 PM PDT 24
Peak memory 234156 kb
Host smart-6028442b-fc31-48ad-a751-18ccc1ee33a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555847181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1555847181
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3331501619
Short name T250
Test name
Test status
Simulation time 28701628738 ps
CPU time 27.78 seconds
Started Jun 29 04:41:16 PM PDT 24
Finished Jun 29 04:41:45 PM PDT 24
Peak memory 212232 kb
Host smart-fb936c71-887f-47a9-86a6-b65d48851ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331501619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3331501619
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3167966644
Short name T263
Test name
Test status
Simulation time 660489465 ps
CPU time 5.7 seconds
Started Jun 29 04:41:11 PM PDT 24
Finished Jun 29 04:41:17 PM PDT 24
Peak memory 211340 kb
Host smart-0ec51a72-c934-49f1-ab41-48af82063ccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167966644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3167966644
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2306108062
Short name T8
Test name
Test status
Simulation time 15510826646 ps
CPU time 36.32 seconds
Started Jun 29 04:41:18 PM PDT 24
Finished Jun 29 04:41:54 PM PDT 24
Peak memory 214200 kb
Host smart-600e4463-7bce-490c-82ce-bf2f8e8d02d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306108062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2306108062
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.150174513
Short name T354
Test name
Test status
Simulation time 1086927336 ps
CPU time 31.76 seconds
Started Jun 29 04:41:12 PM PDT 24
Finished Jun 29 04:41:44 PM PDT 24
Peak memory 215676 kb
Host smart-c2bbffb8-2ec4-4dc8-85c8-6320846e5b40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150174513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.150174513
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1662826678
Short name T211
Test name
Test status
Simulation time 2154988696 ps
CPU time 16.65 seconds
Started Jun 29 04:41:18 PM PDT 24
Finished Jun 29 04:41:35 PM PDT 24
Peak memory 211288 kb
Host smart-3d81c46e-8777-4692-bef9-582b73ed1265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662826678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1662826678
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3160487624
Short name T19
Test name
Test status
Simulation time 7884571161 ps
CPU time 95.26 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:42:55 PM PDT 24
Peak memory 236828 kb
Host smart-8facf94e-9785-48e2-b145-28a5a5d8c5e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160487624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3160487624
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2720670314
Short name T218
Test name
Test status
Simulation time 428317073 ps
CPU time 9.39 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:41:29 PM PDT 24
Peak memory 212048 kb
Host smart-3c02d660-43d8-4eff-bfe5-94509e12dc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720670314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2720670314
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1496111268
Short name T183
Test name
Test status
Simulation time 1901768599 ps
CPU time 15.98 seconds
Started Jun 29 04:41:17 PM PDT 24
Finished Jun 29 04:41:34 PM PDT 24
Peak memory 211340 kb
Host smart-1ece7470-9626-4e56-ac91-99cc74404794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496111268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1496111268
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.404563302
Short name T198
Test name
Test status
Simulation time 284324424 ps
CPU time 11.17 seconds
Started Jun 29 04:41:15 PM PDT 24
Finished Jun 29 04:41:27 PM PDT 24
Peak memory 212156 kb
Host smart-fe4ef0e3-2ad1-4634-86a9-f525ddb285b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404563302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.404563302
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.276075627
Short name T175
Test name
Test status
Simulation time 4649516041 ps
CPU time 44.13 seconds
Started Jun 29 04:41:19 PM PDT 24
Finished Jun 29 04:42:03 PM PDT 24
Peak memory 219356 kb
Host smart-a56717c3-93c5-417a-ae6c-05c67b69aca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276075627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.276075627
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2443081271
Short name T139
Test name
Test status
Simulation time 1024395686 ps
CPU time 10.32 seconds
Started Jun 29 04:39:58 PM PDT 24
Finished Jun 29 04:40:09 PM PDT 24
Peak memory 211220 kb
Host smart-26af25c8-6a03-4a04-b155-a7ba7fedc23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443081271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2443081271
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2640497111
Short name T230
Test name
Test status
Simulation time 50521193758 ps
CPU time 492.05 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:48:08 PM PDT 24
Peak memory 237752 kb
Host smart-49ef7d76-4629-4b70-a037-7eecd9236ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640497111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2640497111
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3353743686
Short name T246
Test name
Test status
Simulation time 22037740893 ps
CPU time 32.78 seconds
Started Jun 29 04:39:53 PM PDT 24
Finished Jun 29 04:40:26 PM PDT 24
Peak memory 212380 kb
Host smart-2f16e2fc-fcb7-491a-bf44-04628886876d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353743686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3353743686
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.584514375
Short name T212
Test name
Test status
Simulation time 388999753 ps
CPU time 5.41 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:40:01 PM PDT 24
Peak memory 211248 kb
Host smart-3c518724-cf8f-47f5-9e6b-2aba39f650dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584514375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.584514375
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1741467519
Short name T265
Test name
Test status
Simulation time 1862925565 ps
CPU time 13.84 seconds
Started Jun 29 04:39:53 PM PDT 24
Finished Jun 29 04:40:09 PM PDT 24
Peak memory 213880 kb
Host smart-f0a1513d-1524-4c90-ad26-a354dd97024f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741467519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1741467519
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2990042460
Short name T132
Test name
Test status
Simulation time 879742664 ps
CPU time 13 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:40:09 PM PDT 24
Peak memory 213612 kb
Host smart-ab8e4aa7-2dd2-4b3b-adb3-a9b1a44a2055
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990042460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2990042460
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2924507451
Short name T274
Test name
Test status
Simulation time 1830442651 ps
CPU time 9.85 seconds
Started Jun 29 04:39:59 PM PDT 24
Finished Jun 29 04:40:09 PM PDT 24
Peak memory 211288 kb
Host smart-4d343b6d-55be-4fa8-a569-2ce09b947c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924507451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2924507451
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3897328150
Short name T50
Test name
Test status
Simulation time 170231672 ps
CPU time 9.62 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:40:05 PM PDT 24
Peak memory 211908 kb
Host smart-e2b46193-4f42-40d3-a376-5528908fe869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897328150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3897328150
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2590378648
Short name T346
Test name
Test status
Simulation time 1225165628 ps
CPU time 12.78 seconds
Started Jun 29 04:39:53 PM PDT 24
Finished Jun 29 04:40:06 PM PDT 24
Peak memory 211332 kb
Host smart-13f32dfa-1e17-482d-b433-8bdf32e5bcd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590378648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2590378648
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2180985428
Short name T282
Test name
Test status
Simulation time 3503755960 ps
CPU time 28.71 seconds
Started Jun 29 04:39:59 PM PDT 24
Finished Jun 29 04:40:28 PM PDT 24
Peak memory 213432 kb
Host smart-3bb01f0d-7405-4ff4-abf0-3700bd6b388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180985428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2180985428
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1648233008
Short name T224
Test name
Test status
Simulation time 657353558 ps
CPU time 11.94 seconds
Started Jun 29 04:39:56 PM PDT 24
Finished Jun 29 04:40:09 PM PDT 24
Peak memory 211272 kb
Host smart-722f590e-9b64-4e42-b06a-52326bee1476
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648233008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1648233008
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4116887419
Short name T56
Test name
Test status
Simulation time 211722290465 ps
CPU time 3986.3 seconds
Started Jun 29 04:39:55 PM PDT 24
Finished Jun 29 05:46:23 PM PDT 24
Peak memory 246720 kb
Host smart-a51c651a-5956-4449-8296-245cdb17bcad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116887419 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.4116887419
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1522457817
Short name T126
Test name
Test status
Simulation time 1754926829 ps
CPU time 9.69 seconds
Started Jun 29 04:39:59 PM PDT 24
Finished Jun 29 04:40:09 PM PDT 24
Peak memory 211288 kb
Host smart-1655b60c-600b-4e75-b554-55c55977f4bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522457817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1522457817
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.940036944
Short name T206
Test name
Test status
Simulation time 70524407749 ps
CPU time 371.07 seconds
Started Jun 29 04:39:53 PM PDT 24
Finished Jun 29 04:46:06 PM PDT 24
Peak memory 237724 kb
Host smart-11dd2dd3-e83a-4c44-a2df-10c3ac95ba9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940036944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.940036944
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3379739400
Short name T49
Test name
Test status
Simulation time 168664526 ps
CPU time 9.48 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:40:05 PM PDT 24
Peak memory 211896 kb
Host smart-88ad33e9-4b29-4375-ab84-351467bfefc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379739400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3379739400
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1177400581
Short name T219
Test name
Test status
Simulation time 15209152453 ps
CPU time 14.46 seconds
Started Jun 29 04:39:55 PM PDT 24
Finished Jun 29 04:40:11 PM PDT 24
Peak memory 211396 kb
Host smart-f889a5cd-fb3e-4067-ac0c-0f3cb816a3e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177400581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1177400581
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3004463930
Short name T247
Test name
Test status
Simulation time 3319484775 ps
CPU time 27.75 seconds
Started Jun 29 04:39:56 PM PDT 24
Finished Jun 29 04:40:25 PM PDT 24
Peak memory 213248 kb
Host smart-146e5b5e-143b-4623-8fdf-29f562e129c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004463930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3004463930
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3610955500
Short name T164
Test name
Test status
Simulation time 3805618801 ps
CPU time 16.04 seconds
Started Jun 29 04:39:54 PM PDT 24
Finished Jun 29 04:40:12 PM PDT 24
Peak memory 214360 kb
Host smart-f6065845-3994-4e32-b32d-a2bda81a06e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610955500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3610955500
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3945033293
Short name T55
Test name
Test status
Simulation time 7566020006 ps
CPU time 1809.54 seconds
Started Jun 29 04:39:56 PM PDT 24
Finished Jun 29 05:10:07 PM PDT 24
Peak memory 221908 kb
Host smart-40a3ee60-e0ee-4cb1-842d-c302f0c40fdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945033293 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3945033293
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.949984429
Short name T154
Test name
Test status
Simulation time 1946524365 ps
CPU time 14.81 seconds
Started Jun 29 04:40:05 PM PDT 24
Finished Jun 29 04:40:20 PM PDT 24
Peak memory 211288 kb
Host smart-4122ceb8-a568-4a2d-bdb2-b49bc924d913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949984429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.949984429
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3448931181
Short name T255
Test name
Test status
Simulation time 1517547041 ps
CPU time 81.16 seconds
Started Jun 29 04:39:59 PM PDT 24
Finished Jun 29 04:41:20 PM PDT 24
Peak memory 212520 kb
Host smart-97e4a841-edc2-41de-a6dd-a355473a288f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448931181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3448931181
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1022046349
Short name T225
Test name
Test status
Simulation time 5281636516 ps
CPU time 31.06 seconds
Started Jun 29 04:39:56 PM PDT 24
Finished Jun 29 04:40:28 PM PDT 24
Peak memory 212180 kb
Host smart-d7975856-3f5a-4fa7-b90c-bc63e19702a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022046349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1022046349
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1922184
Short name T37
Test name
Test status
Simulation time 5505372307 ps
CPU time 12.96 seconds
Started Jun 29 04:39:55 PM PDT 24
Finished Jun 29 04:40:09 PM PDT 24
Peak memory 211392 kb
Host smart-68d983f0-dac6-4c9a-9879-4a50176cbef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1922184
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.743016773
Short name T160
Test name
Test status
Simulation time 3109399049 ps
CPU time 16.48 seconds
Started Jun 29 04:39:57 PM PDT 24
Finished Jun 29 04:40:14 PM PDT 24
Peak memory 213380 kb
Host smart-d6403f8b-f28f-4179-82a2-bbc8add2a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743016773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.743016773
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3791896511
Short name T93
Test name
Test status
Simulation time 1627935901 ps
CPU time 37.8 seconds
Started Jun 29 04:39:55 PM PDT 24
Finished Jun 29 04:40:34 PM PDT 24
Peak memory 214740 kb
Host smart-3db704c2-f57d-47da-a05f-15df6bc6e7c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791896511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3791896511
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2237033565
Short name T272
Test name
Test status
Simulation time 35871797684 ps
CPU time 2633.91 seconds
Started Jun 29 04:39:53 PM PDT 24
Finished Jun 29 05:23:48 PM PDT 24
Peak memory 235728 kb
Host smart-018a2b36-bbac-4a61-843d-84f9a101213a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237033565 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2237033565
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2260557665
Short name T200
Test name
Test status
Simulation time 2687922283 ps
CPU time 11.89 seconds
Started Jun 29 04:40:01 PM PDT 24
Finished Jun 29 04:40:14 PM PDT 24
Peak memory 211276 kb
Host smart-2241d331-1112-45d6-a7ec-174326f39a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260557665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2260557665
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1307671101
Short name T222
Test name
Test status
Simulation time 14858375834 ps
CPU time 137.51 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:42:21 PM PDT 24
Peak memory 238032 kb
Host smart-7999d327-1756-45c1-b79e-159d20f40008
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307671101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1307671101
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2546590750
Short name T147
Test name
Test status
Simulation time 5939108801 ps
CPU time 13.21 seconds
Started Jun 29 04:40:06 PM PDT 24
Finished Jun 29 04:40:20 PM PDT 24
Peak memory 211396 kb
Host smart-0bbb358e-f269-4301-a02f-9543f393afa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546590750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2546590750
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4230823623
Short name T10
Test name
Test status
Simulation time 6579199952 ps
CPU time 32.8 seconds
Started Jun 29 04:40:03 PM PDT 24
Finished Jun 29 04:40:37 PM PDT 24
Peak memory 214188 kb
Host smart-c23cb50e-69b7-4008-994a-2ee759dbbae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230823623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4230823623
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.919198387
Short name T177
Test name
Test status
Simulation time 211398213 ps
CPU time 12.85 seconds
Started Jun 29 04:40:04 PM PDT 24
Finished Jun 29 04:40:18 PM PDT 24
Peak memory 213476 kb
Host smart-dad90efc-e003-47cc-846f-103ea46dfe57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919198387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.919198387
Directory /workspace/9.rom_ctrl_stress_all/latest
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