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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.38 96.89 92.13 97.67 100.00 98.62 97.30 99.07


Total test records in report: 465
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T297 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2102935188 Jun 30 04:50:19 PM PDT 24 Jun 30 04:50:46 PM PDT 24 6364745382 ps
T298 /workspace/coverage/default/29.rom_ctrl_smoke.540268212 Jun 30 04:50:45 PM PDT 24 Jun 30 04:50:56 PM PDT 24 188946291 ps
T299 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.591056647 Jun 30 04:50:19 PM PDT 24 Jun 30 04:50:30 PM PDT 24 3449865814 ps
T300 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1929468252 Jun 30 04:50:45 PM PDT 24 Jun 30 04:50:51 PM PDT 24 100059715 ps
T301 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2430702312 Jun 30 04:50:14 PM PDT 24 Jun 30 04:50:23 PM PDT 24 2385600880 ps
T302 /workspace/coverage/default/41.rom_ctrl_stress_all.2504001941 Jun 30 04:51:07 PM PDT 24 Jun 30 04:51:53 PM PDT 24 15452428486 ps
T303 /workspace/coverage/default/5.rom_ctrl_stress_all.1975110343 Jun 30 04:50:08 PM PDT 24 Jun 30 04:50:53 PM PDT 24 18216622165 ps
T304 /workspace/coverage/default/40.rom_ctrl_stress_all.1213231312 Jun 30 04:51:08 PM PDT 24 Jun 30 04:51:25 PM PDT 24 6935666135 ps
T305 /workspace/coverage/default/23.rom_ctrl_smoke.3715644215 Jun 30 04:50:31 PM PDT 24 Jun 30 04:50:56 PM PDT 24 7361393664 ps
T306 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2893801032 Jun 30 04:50:57 PM PDT 24 Jun 30 04:53:10 PM PDT 24 44083834001 ps
T307 /workspace/coverage/default/25.rom_ctrl_stress_all.2798791161 Jun 30 04:50:38 PM PDT 24 Jun 30 04:50:59 PM PDT 24 10918752356 ps
T308 /workspace/coverage/default/14.rom_ctrl_stress_all.1209457638 Jun 30 04:50:20 PM PDT 24 Jun 30 04:50:37 PM PDT 24 611444163 ps
T309 /workspace/coverage/default/3.rom_ctrl_smoke.1524745820 Jun 30 04:50:05 PM PDT 24 Jun 30 04:50:31 PM PDT 24 13427496457 ps
T310 /workspace/coverage/default/38.rom_ctrl_smoke.2120527447 Jun 30 04:51:00 PM PDT 24 Jun 30 04:51:37 PM PDT 24 7313168645 ps
T311 /workspace/coverage/default/19.rom_ctrl_stress_all.1033155560 Jun 30 04:50:25 PM PDT 24 Jun 30 04:50:47 PM PDT 24 380177998 ps
T312 /workspace/coverage/default/7.rom_ctrl_smoke.4132987473 Jun 30 04:50:12 PM PDT 24 Jun 30 04:50:34 PM PDT 24 2230395588 ps
T313 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.17017147 Jun 30 04:51:18 PM PDT 24 Jun 30 04:51:31 PM PDT 24 2289089107 ps
T30 /workspace/coverage/default/4.rom_ctrl_sec_cm.3776926614 Jun 30 04:50:08 PM PDT 24 Jun 30 04:51:50 PM PDT 24 655690915 ps
T314 /workspace/coverage/default/42.rom_ctrl_smoke.2706285973 Jun 30 04:51:12 PM PDT 24 Jun 30 04:51:50 PM PDT 24 14082334869 ps
T315 /workspace/coverage/default/19.rom_ctrl_smoke.3577793105 Jun 30 04:50:26 PM PDT 24 Jun 30 04:50:43 PM PDT 24 2205837642 ps
T316 /workspace/coverage/default/32.rom_ctrl_alert_test.1062915137 Jun 30 04:50:57 PM PDT 24 Jun 30 04:51:02 PM PDT 24 87500852 ps
T317 /workspace/coverage/default/22.rom_ctrl_stress_all.3295208075 Jun 30 04:50:34 PM PDT 24 Jun 30 04:51:08 PM PDT 24 10015860399 ps
T318 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.210599127 Jun 30 04:50:19 PM PDT 24 Jun 30 04:52:05 PM PDT 24 13156431358 ps
T319 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2956804906 Jun 30 04:51:11 PM PDT 24 Jun 30 04:51:21 PM PDT 24 663901187 ps
T320 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2955413773 Jun 30 04:50:37 PM PDT 24 Jun 30 04:50:47 PM PDT 24 477722966 ps
T321 /workspace/coverage/default/21.rom_ctrl_alert_test.1928988282 Jun 30 04:50:31 PM PDT 24 Jun 30 04:50:38 PM PDT 24 254636470 ps
T322 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.99238704 Jun 30 04:50:12 PM PDT 24 Jun 30 04:52:23 PM PDT 24 8708455900 ps
T323 /workspace/coverage/default/34.rom_ctrl_alert_test.2569287933 Jun 30 04:50:59 PM PDT 24 Jun 30 04:51:04 PM PDT 24 1185138096 ps
T324 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2486535142 Jun 30 04:50:55 PM PDT 24 Jun 30 04:51:12 PM PDT 24 3792654192 ps
T325 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1279157070 Jun 30 04:51:00 PM PDT 24 Jun 30 04:55:30 PM PDT 24 48761456874 ps
T326 /workspace/coverage/default/5.rom_ctrl_alert_test.2997401773 Jun 30 04:50:08 PM PDT 24 Jun 30 04:50:13 PM PDT 24 85408485 ps
T327 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1863468378 Jun 30 04:50:12 PM PDT 24 Jun 30 04:50:20 PM PDT 24 2217977499 ps
T328 /workspace/coverage/default/27.rom_ctrl_alert_test.2038189478 Jun 30 04:50:38 PM PDT 24 Jun 30 04:50:53 PM PDT 24 2685393500 ps
T329 /workspace/coverage/default/29.rom_ctrl_stress_all.1999846709 Jun 30 04:50:44 PM PDT 24 Jun 30 04:51:23 PM PDT 24 15848236138 ps
T330 /workspace/coverage/default/11.rom_ctrl_alert_test.3395291425 Jun 30 04:50:10 PM PDT 24 Jun 30 04:50:25 PM PDT 24 7170743720 ps
T331 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.253738529 Jun 30 04:50:26 PM PDT 24 Jun 30 04:54:54 PM PDT 24 84054553878 ps
T332 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1537003412 Jun 30 04:50:13 PM PDT 24 Jun 30 04:52:58 PM PDT 24 10328594032 ps
T333 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4228617382 Jun 30 04:50:15 PM PDT 24 Jun 30 04:50:21 PM PDT 24 378645772 ps
T334 /workspace/coverage/default/3.rom_ctrl_stress_all.3599381641 Jun 30 04:50:05 PM PDT 24 Jun 30 04:52:20 PM PDT 24 68411690531 ps
T335 /workspace/coverage/default/28.rom_ctrl_stress_all.1415535310 Jun 30 04:50:46 PM PDT 24 Jun 30 04:50:59 PM PDT 24 1397150034 ps
T336 /workspace/coverage/default/2.rom_ctrl_alert_test.3724670902 Jun 30 04:50:06 PM PDT 24 Jun 30 04:50:13 PM PDT 24 338546893 ps
T337 /workspace/coverage/default/32.rom_ctrl_smoke.3202201129 Jun 30 04:50:56 PM PDT 24 Jun 30 04:51:24 PM PDT 24 37170049672 ps
T338 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1980880724 Jun 30 04:50:38 PM PDT 24 Jun 30 04:51:05 PM PDT 24 6009122637 ps
T339 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.864042805 Jun 30 04:50:56 PM PDT 24 Jun 30 04:51:24 PM PDT 24 37566872500 ps
T340 /workspace/coverage/default/36.rom_ctrl_stress_all.257781189 Jun 30 04:51:00 PM PDT 24 Jun 30 04:51:21 PM PDT 24 1427203911 ps
T341 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3457551745 Jun 30 04:50:47 PM PDT 24 Jun 30 04:54:19 PM PDT 24 24382139815 ps
T342 /workspace/coverage/default/41.rom_ctrl_alert_test.3932571070 Jun 30 04:51:09 PM PDT 24 Jun 30 04:51:18 PM PDT 24 5614142914 ps
T343 /workspace/coverage/default/18.rom_ctrl_stress_all.4107027929 Jun 30 04:50:24 PM PDT 24 Jun 30 04:51:17 PM PDT 24 22457302163 ps
T344 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2011578740 Jun 30 04:50:24 PM PDT 24 Jun 30 04:52:54 PM PDT 24 29018942480 ps
T345 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.74807888 Jun 30 04:51:08 PM PDT 24 Jun 30 04:51:15 PM PDT 24 370325909 ps
T346 /workspace/coverage/default/43.rom_ctrl_alert_test.3936961044 Jun 30 04:51:10 PM PDT 24 Jun 30 04:51:25 PM PDT 24 1840312322 ps
T347 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.533326053 Jun 30 04:50:04 PM PDT 24 Jun 30 04:51:44 PM PDT 24 5538233994 ps
T348 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1720830057 Jun 30 04:50:13 PM PDT 24 Jun 30 04:50:31 PM PDT 24 1290861580 ps
T349 /workspace/coverage/default/30.rom_ctrl_stress_all.309106706 Jun 30 04:50:45 PM PDT 24 Jun 30 04:51:00 PM PDT 24 1129622401 ps
T31 /workspace/coverage/default/0.rom_ctrl_sec_cm.2876040128 Jun 30 04:50:06 PM PDT 24 Jun 30 04:51:57 PM PDT 24 2172714058 ps
T350 /workspace/coverage/default/3.rom_ctrl_alert_test.2681233573 Jun 30 04:50:06 PM PDT 24 Jun 30 04:50:21 PM PDT 24 1650281055 ps
T351 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2944345791 Jun 30 04:50:35 PM PDT 24 Jun 30 04:50:53 PM PDT 24 19005903805 ps
T352 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3614108039 Jun 30 04:50:59 PM PDT 24 Jun 30 05:16:45 PM PDT 24 19291731951 ps
T353 /workspace/coverage/default/24.rom_ctrl_alert_test.3372304392 Jun 30 04:50:38 PM PDT 24 Jun 30 04:50:43 PM PDT 24 89746305 ps
T354 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2845483094 Jun 30 04:51:08 PM PDT 24 Jun 30 04:52:31 PM PDT 24 3542376626 ps
T355 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.987989072 Jun 30 04:50:26 PM PDT 24 Jun 30 05:11:31 PM PDT 24 147534261638 ps
T356 /workspace/coverage/default/30.rom_ctrl_smoke.2887981137 Jun 30 04:50:46 PM PDT 24 Jun 30 04:51:14 PM PDT 24 5599003601 ps
T357 /workspace/coverage/default/46.rom_ctrl_alert_test.1188251504 Jun 30 04:51:13 PM PDT 24 Jun 30 04:51:24 PM PDT 24 3635728682 ps
T358 /workspace/coverage/default/35.rom_ctrl_stress_all.3224872041 Jun 30 04:51:00 PM PDT 24 Jun 30 04:51:29 PM PDT 24 4848682206 ps
T359 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3400434938 Jun 30 04:51:14 PM PDT 24 Jun 30 04:53:09 PM PDT 24 3140229779 ps
T360 /workspace/coverage/default/21.rom_ctrl_smoke.3978729190 Jun 30 04:50:32 PM PDT 24 Jun 30 04:51:05 PM PDT 24 16042806142 ps
T361 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.849873241 Jun 30 04:50:39 PM PDT 24 Jun 30 04:51:07 PM PDT 24 6536935756 ps
T362 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3319834974 Jun 30 04:51:16 PM PDT 24 Jun 30 04:51:42 PM PDT 24 2663398797 ps
T363 /workspace/coverage/default/6.rom_ctrl_alert_test.1578465019 Jun 30 04:50:17 PM PDT 24 Jun 30 04:50:29 PM PDT 24 1174803740 ps
T364 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1468029356 Jun 30 04:50:55 PM PDT 24 Jun 30 04:51:01 PM PDT 24 540540264 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3218450081 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:59 PM PDT 24 3107426130 ps
T67 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.402698324 Jun 30 04:49:57 PM PDT 24 Jun 30 04:50:16 PM PDT 24 8445229681 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3747335183 Jun 30 04:49:41 PM PDT 24 Jun 30 04:49:58 PM PDT 24 1530030138 ps
T63 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1804034064 Jun 30 04:50:04 PM PDT 24 Jun 30 04:51:19 PM PDT 24 6420363292 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.805350620 Jun 30 04:49:32 PM PDT 24 Jun 30 04:49:36 PM PDT 24 168759237 ps
T72 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1749438433 Jun 30 04:49:32 PM PDT 24 Jun 30 04:49:51 PM PDT 24 7270037739 ps
T102 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.856156323 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:55 PM PDT 24 1284301067 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2993940721 Jun 30 04:50:03 PM PDT 24 Jun 30 04:50:09 PM PDT 24 85542701 ps
T366 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1588911556 Jun 30 04:49:53 PM PDT 24 Jun 30 04:50:07 PM PDT 24 3289931082 ps
T73 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3803886963 Jun 30 04:49:46 PM PDT 24 Jun 30 04:50:42 PM PDT 24 32869431381 ps
T74 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1494682218 Jun 30 04:50:04 PM PDT 24 Jun 30 04:50:22 PM PDT 24 2114095391 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.539764534 Jun 30 04:49:41 PM PDT 24 Jun 30 04:49:52 PM PDT 24 3498505980 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3966772443 Jun 30 04:49:33 PM PDT 24 Jun 30 04:49:51 PM PDT 24 1781491441 ps
T369 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2957434077 Jun 30 04:49:56 PM PDT 24 Jun 30 04:50:03 PM PDT 24 202128430 ps
T75 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3391309893 Jun 30 04:49:58 PM PDT 24 Jun 30 04:51:09 PM PDT 24 40705165808 ps
T76 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2374037122 Jun 30 04:49:34 PM PDT 24 Jun 30 04:50:37 PM PDT 24 29941006517 ps
T77 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2154645601 Jun 30 04:50:03 PM PDT 24 Jun 30 04:50:48 PM PDT 24 9418440742 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2928361822 Jun 30 04:49:33 PM PDT 24 Jun 30 04:50:48 PM PDT 24 2760229634 ps
T65 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.560680459 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:33 PM PDT 24 1120732916 ps
T78 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.400591373 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:11 PM PDT 24 5127599082 ps
T370 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2289819869 Jun 30 04:49:56 PM PDT 24 Jun 30 04:50:13 PM PDT 24 1855240775 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.104107899 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:59 PM PDT 24 2734231829 ps
T372 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2834275258 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:49 PM PDT 24 127874512 ps
T79 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3513767938 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:09 PM PDT 24 3676757455 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.268034317 Jun 30 04:49:32 PM PDT 24 Jun 30 04:50:44 PM PDT 24 4893060303 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2132114660 Jun 30 04:49:45 PM PDT 24 Jun 30 04:50:00 PM PDT 24 3297004922 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1919929379 Jun 30 04:49:41 PM PDT 24 Jun 30 04:49:49 PM PDT 24 523087235 ps
T374 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.488205183 Jun 30 04:50:05 PM PDT 24 Jun 30 04:50:46 PM PDT 24 3126866646 ps
T375 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1631627615 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:54 PM PDT 24 2786949265 ps
T376 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2597416962 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:56 PM PDT 24 1601586052 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1124697958 Jun 30 04:49:43 PM PDT 24 Jun 30 04:50:32 PM PDT 24 20468278909 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2901951851 Jun 30 04:49:43 PM PDT 24 Jun 30 04:50:35 PM PDT 24 5826443296 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1736851766 Jun 30 04:49:47 PM PDT 24 Jun 30 04:50:00 PM PDT 24 2453418359 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.864871047 Jun 30 04:50:04 PM PDT 24 Jun 30 04:51:12 PM PDT 24 6881848166 ps
T89 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.628043685 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:49 PM PDT 24 540577842 ps
T378 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1616206357 Jun 30 04:49:47 PM PDT 24 Jun 30 04:49:58 PM PDT 24 291480707 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.569684365 Jun 30 04:49:33 PM PDT 24 Jun 30 04:50:32 PM PDT 24 5831293337 ps
T379 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1599498631 Jun 30 04:49:47 PM PDT 24 Jun 30 04:49:53 PM PDT 24 120672381 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1383778381 Jun 30 04:49:43 PM PDT 24 Jun 30 04:49:54 PM PDT 24 4093115812 ps
T381 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2210416377 Jun 30 04:50:03 PM PDT 24 Jun 30 04:50:11 PM PDT 24 306675202 ps
T382 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.491597957 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:08 PM PDT 24 991713530 ps
T383 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2348614891 Jun 30 04:49:47 PM PDT 24 Jun 30 04:50:02 PM PDT 24 1036979333 ps
T91 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.471750811 Jun 30 04:49:56 PM PDT 24 Jun 30 04:51:01 PM PDT 24 6464225302 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3529652862 Jun 30 04:49:39 PM PDT 24 Jun 30 04:50:16 PM PDT 24 152799476 ps
T385 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2334308533 Jun 30 04:49:53 PM PDT 24 Jun 30 04:50:10 PM PDT 24 2112415530 ps
T386 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3079601967 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:45 PM PDT 24 436810592 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3887042604 Jun 30 04:49:41 PM PDT 24 Jun 30 04:49:49 PM PDT 24 167981210 ps
T99 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.547025085 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:01 PM PDT 24 332804902 ps
T116 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1091275889 Jun 30 04:49:40 PM PDT 24 Jun 30 04:50:17 PM PDT 24 163072917 ps
T100 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.835990193 Jun 30 04:49:45 PM PDT 24 Jun 30 04:49:58 PM PDT 24 3288051520 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.789480023 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:51 PM PDT 24 1767995833 ps
T96 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.456335747 Jun 30 04:49:56 PM PDT 24 Jun 30 04:50:26 PM PDT 24 8992683560 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4161308899 Jun 30 04:49:30 PM PDT 24 Jun 30 04:49:37 PM PDT 24 332318358 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.195093823 Jun 30 04:49:32 PM PDT 24 Jun 30 04:49:46 PM PDT 24 1638759816 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2039897590 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:56 PM PDT 24 1783491375 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.496750536 Jun 30 04:49:49 PM PDT 24 Jun 30 04:50:47 PM PDT 24 78641835264 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1662099022 Jun 30 04:49:41 PM PDT 24 Jun 30 04:49:48 PM PDT 24 309001067 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2005157203 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:56 PM PDT 24 4116095572 ps
T394 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4101184902 Jun 30 04:49:45 PM PDT 24 Jun 30 04:49:51 PM PDT 24 1082662203 ps
T109 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1147051549 Jun 30 04:49:49 PM PDT 24 Jun 30 04:51:03 PM PDT 24 11246600368 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3616288394 Jun 30 04:49:43 PM PDT 24 Jun 30 04:49:54 PM PDT 24 2664673186 ps
T101 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3138091820 Jun 30 04:49:56 PM PDT 24 Jun 30 04:50:07 PM PDT 24 1805170458 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.880018427 Jun 30 04:49:41 PM PDT 24 Jun 30 04:49:56 PM PDT 24 4882436338 ps
T397 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2315357855 Jun 30 04:50:03 PM PDT 24 Jun 30 04:50:15 PM PDT 24 1496509928 ps
T398 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.641038290 Jun 30 04:49:54 PM PDT 24 Jun 30 04:50:11 PM PDT 24 8108019986 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2678373458 Jun 30 04:49:33 PM PDT 24 Jun 30 04:49:47 PM PDT 24 3030097758 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2820025820 Jun 30 04:49:32 PM PDT 24 Jun 30 04:49:44 PM PDT 24 4548637720 ps
T92 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2727267340 Jun 30 04:49:34 PM PDT 24 Jun 30 04:49:44 PM PDT 24 797025704 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.684595644 Jun 30 04:49:35 PM PDT 24 Jun 30 04:49:51 PM PDT 24 3634842559 ps
T97 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2776028942 Jun 30 04:50:04 PM PDT 24 Jun 30 04:51:38 PM PDT 24 80656456658 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4074223434 Jun 30 04:49:43 PM PDT 24 Jun 30 04:49:49 PM PDT 24 865343726 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4005019414 Jun 30 04:49:31 PM PDT 24 Jun 30 04:49:39 PM PDT 24 192698040 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2410325707 Jun 30 04:49:51 PM PDT 24 Jun 30 04:51:09 PM PDT 24 9904776990 ps
T404 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.92869062 Jun 30 04:49:50 PM PDT 24 Jun 30 04:50:07 PM PDT 24 4310455578 ps
T405 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.441643982 Jun 30 04:49:58 PM PDT 24 Jun 30 04:50:08 PM PDT 24 4987670790 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1494795096 Jun 30 04:49:44 PM PDT 24 Jun 30 04:50:55 PM PDT 24 296557384 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2602633345 Jun 30 04:49:34 PM PDT 24 Jun 30 04:49:43 PM PDT 24 631924687 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3738315872 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:56 PM PDT 24 1940935012 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3096603695 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:12 PM PDT 24 4034545866 ps
T106 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1088780855 Jun 30 04:49:57 PM PDT 24 Jun 30 04:51:12 PM PDT 24 3551668875 ps
T409 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2908225714 Jun 30 04:49:54 PM PDT 24 Jun 30 04:50:09 PM PDT 24 14102941958 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1938546274 Jun 30 04:49:32 PM PDT 24 Jun 30 04:49:36 PM PDT 24 98126673 ps
T411 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3592605585 Jun 30 04:50:05 PM PDT 24 Jun 30 04:50:19 PM PDT 24 2409099077 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3955066665 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:57 PM PDT 24 1905192882 ps
T413 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2186913866 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:54 PM PDT 24 4790117279 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2419386442 Jun 30 04:49:48 PM PDT 24 Jun 30 04:49:57 PM PDT 24 3275079548 ps
T107 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1777609764 Jun 30 04:49:56 PM PDT 24 Jun 30 04:51:09 PM PDT 24 301234475 ps
T113 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1975993782 Jun 30 04:49:47 PM PDT 24 Jun 30 04:50:57 PM PDT 24 290585548 ps
T415 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2419300346 Jun 30 04:49:51 PM PDT 24 Jun 30 04:50:02 PM PDT 24 2075576264 ps
T416 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4131737924 Jun 30 04:49:31 PM PDT 24 Jun 30 04:49:41 PM PDT 24 7151324889 ps
T417 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3647166527 Jun 30 04:49:50 PM PDT 24 Jun 30 04:50:02 PM PDT 24 2835844190 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2278002450 Jun 30 04:49:39 PM PDT 24 Jun 30 04:49:44 PM PDT 24 333134432 ps
T419 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3523412967 Jun 30 04:49:42 PM PDT 24 Jun 30 04:50:01 PM PDT 24 1332075444 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2918191405 Jun 30 04:49:32 PM PDT 24 Jun 30 04:49:41 PM PDT 24 2247943511 ps
T421 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2845602710 Jun 30 04:49:57 PM PDT 24 Jun 30 04:50:13 PM PDT 24 1641664208 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1370589613 Jun 30 04:49:32 PM PDT 24 Jun 30 04:49:40 PM PDT 24 883358147 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2673510000 Jun 30 04:49:41 PM PDT 24 Jun 30 04:49:54 PM PDT 24 20469602759 ps
T424 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3059907270 Jun 30 04:50:03 PM PDT 24 Jun 30 04:50:18 PM PDT 24 6925464674 ps
T425 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1734534225 Jun 30 04:50:04 PM PDT 24 Jun 30 04:50:19 PM PDT 24 1429498836 ps
T426 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.457386234 Jun 30 04:49:49 PM PDT 24 Jun 30 04:50:34 PM PDT 24 6899162834 ps
T95 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1186537261 Jun 30 04:49:33 PM PDT 24 Jun 30 04:50:36 PM PDT 24 8306385128 ps
T427 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1417370329 Jun 30 04:49:47 PM PDT 24 Jun 30 04:49:52 PM PDT 24 88243808 ps
T428 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4195316033 Jun 30 04:50:06 PM PDT 24 Jun 30 04:50:18 PM PDT 24 1364052813 ps
T112 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.525640340 Jun 30 04:49:41 PM PDT 24 Jun 30 04:50:23 PM PDT 24 2028332949 ps
T429 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1712088215 Jun 30 04:49:58 PM PDT 24 Jun 30 04:50:30 PM PDT 24 7983811247 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4233916153 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:23 PM PDT 24 2864152794 ps
T114 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.488108977 Jun 30 04:49:45 PM PDT 24 Jun 30 04:50:22 PM PDT 24 157916482 ps
T430 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1561444033 Jun 30 04:49:47 PM PDT 24 Jun 30 04:50:02 PM PDT 24 7618007500 ps
T431 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3865779343 Jun 30 04:49:51 PM PDT 24 Jun 30 04:50:30 PM PDT 24 6349147970 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.890537137 Jun 30 04:49:45 PM PDT 24 Jun 30 04:50:01 PM PDT 24 1425099598 ps
T433 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3196219137 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:14 PM PDT 24 7981156101 ps
T434 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.891709385 Jun 30 04:49:57 PM PDT 24 Jun 30 04:50:03 PM PDT 24 99411103 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.960990800 Jun 30 04:49:57 PM PDT 24 Jun 30 04:50:02 PM PDT 24 174815420 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3586316602 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:53 PM PDT 24 4625184696 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1754068429 Jun 30 04:50:04 PM PDT 24 Jun 30 04:50:19 PM PDT 24 1433725599 ps
T438 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.336087051 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:57 PM PDT 24 19716932201 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.514104152 Jun 30 04:49:57 PM PDT 24 Jun 30 04:50:15 PM PDT 24 10304851758 ps
T440 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1387197389 Jun 30 04:50:06 PM PDT 24 Jun 30 04:50:26 PM PDT 24 8380281923 ps
T115 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3552341380 Jun 30 04:49:41 PM PDT 24 Jun 30 04:50:26 PM PDT 24 1570582891 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1263235526 Jun 30 04:50:05 PM PDT 24 Jun 30 04:50:21 PM PDT 24 9123042905 ps
T442 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1625239465 Jun 30 04:50:06 PM PDT 24 Jun 30 04:50:14 PM PDT 24 269654457 ps
T443 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1234061730 Jun 30 04:49:48 PM PDT 24 Jun 30 04:50:03 PM PDT 24 7336338790 ps
T444 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.175813400 Jun 30 04:49:47 PM PDT 24 Jun 30 04:50:05 PM PDT 24 4033500601 ps
T445 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2817235590 Jun 30 04:50:04 PM PDT 24 Jun 30 04:51:21 PM PDT 24 1575067252 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.676108353 Jun 30 04:49:39 PM PDT 24 Jun 30 04:49:55 PM PDT 24 1979406216 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1132147512 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:50 PM PDT 24 2389287911 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.233641691 Jun 30 04:49:33 PM PDT 24 Jun 30 04:49:45 PM PDT 24 3978970716 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3629644100 Jun 30 04:49:40 PM PDT 24 Jun 30 04:49:51 PM PDT 24 1273331285 ps
T450 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.624782450 Jun 30 04:49:49 PM PDT 24 Jun 30 04:50:09 PM PDT 24 380938322 ps
T108 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1267903051 Jun 30 04:49:56 PM PDT 24 Jun 30 04:51:10 PM PDT 24 5610784589 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2126744045 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:55 PM PDT 24 2459734514 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1818893320 Jun 30 04:49:41 PM PDT 24 Jun 30 04:50:01 PM PDT 24 1514205729 ps
T453 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1693607719 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:03 PM PDT 24 296925645 ps
T454 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1908932837 Jun 30 04:49:57 PM PDT 24 Jun 30 04:50:03 PM PDT 24 174830133 ps
T455 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2826982456 Jun 30 04:49:46 PM PDT 24 Jun 30 04:51:13 PM PDT 24 65756905474 ps
T456 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.143811891 Jun 30 04:49:51 PM PDT 24 Jun 30 04:50:05 PM PDT 24 5940511231 ps
T457 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1457003920 Jun 30 04:49:34 PM PDT 24 Jun 30 04:49:45 PM PDT 24 499420085 ps
T458 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1131241004 Jun 30 04:49:56 PM PDT 24 Jun 30 04:50:01 PM PDT 24 87212328 ps
T459 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1477748676 Jun 30 04:49:47 PM PDT 24 Jun 30 04:50:03 PM PDT 24 5652821681 ps
T460 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3718541653 Jun 30 04:49:32 PM PDT 24 Jun 30 04:49:46 PM PDT 24 7902559388 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3631607228 Jun 30 04:49:42 PM PDT 24 Jun 30 04:49:59 PM PDT 24 7410877324 ps
T462 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2263527707 Jun 30 04:49:55 PM PDT 24 Jun 30 04:50:01 PM PDT 24 348118726 ps
T463 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3850565144 Jun 30 04:49:56 PM PDT 24 Jun 30 04:51:06 PM PDT 24 1615160692 ps
T464 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1571607328 Jun 30 04:49:34 PM PDT 24 Jun 30 04:49:48 PM PDT 24 24525214179 ps
T465 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3449549673 Jun 30 04:49:57 PM PDT 24 Jun 30 04:50:09 PM PDT 24 1228817291 ps

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.1577520556
Short name T1
Test name
Test status
Simulation time 240544370377 ps
CPU time 5148.68 seconds
Started Jun 30 04:50:46 PM PDT 24
Finished Jun 30 06:16:36 PM PDT 24
Peak memory 235808 kb
Host smart-4ba278a9-3fd3-4510-b9de-7e574388d41e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577520556 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.1577520556
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1923918168
Short name T41
Test name
Test status
Simulation time 38594235618 ps
CPU time 398.51 seconds
Started Jun 30 04:50:11 PM PDT 24
Finished Jun 30 04:56:50 PM PDT 24
Peak memory 225128 kb
Host smart-562067ec-347a-4092-a87c-91fa15b0d807
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923918168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1923918168
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2574535830
Short name T6
Test name
Test status
Simulation time 253581628 ps
CPU time 11.72 seconds
Started Jun 30 04:50:13 PM PDT 24
Finished Jun 30 04:50:25 PM PDT 24
Peak memory 212416 kb
Host smart-f5d8b2f8-1b72-4fc6-9ecd-0d32d6ca55ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574535830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2574535830
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1804034064
Short name T63
Test name
Test status
Simulation time 6420363292 ps
CPU time 73.92 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:51:19 PM PDT 24
Peak memory 218836 kb
Host smart-8a14f9a3-b015-41ca-896d-12f245bfe100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804034064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1804034064
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1285695092
Short name T9
Test name
Test status
Simulation time 310937150 ps
CPU time 18.92 seconds
Started Jun 30 04:51:13 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 215904 kb
Host smart-66731f15-d570-4f21-a868-2fbcbf550cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285695092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1285695092
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.299673289
Short name T24
Test name
Test status
Simulation time 12187691376 ps
CPU time 107.98 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:51:55 PM PDT 24
Peak memory 238340 kb
Host smart-bf3d8344-3e25-40a9-8220-61a584bef123
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299673289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.299673289
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1124697958
Short name T86
Test name
Test status
Simulation time 20468278909 ps
CPU time 48.18 seconds
Started Jun 30 04:49:43 PM PDT 24
Finished Jun 30 04:50:32 PM PDT 24
Peak memory 210636 kb
Host smart-a759b36a-a775-425a-bf32-0072b8ae4626
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124697958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1124697958
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1267903051
Short name T108
Test name
Test status
Simulation time 5610784589 ps
CPU time 73.33 seconds
Started Jun 30 04:49:56 PM PDT 24
Finished Jun 30 04:51:10 PM PDT 24
Peak memory 218936 kb
Host smart-b26d77bf-4875-4474-9ec3-ab49def09b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267903051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1267903051
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4158480578
Short name T35
Test name
Test status
Simulation time 28104063784 ps
CPU time 13.31 seconds
Started Jun 30 04:50:07 PM PDT 24
Finished Jun 30 04:50:21 PM PDT 24
Peak memory 211380 kb
Host smart-20fe4c40-b060-4c1e-a89b-2e2cc9676696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158480578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4158480578
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3431763652
Short name T119
Test name
Test status
Simulation time 22398309277 ps
CPU time 106.58 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:51:53 PM PDT 24
Peak memory 219308 kb
Host smart-b74b51dc-0685-44ad-909a-20fff88f2afc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431763652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3431763652
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2374037122
Short name T76
Test name
Test status
Simulation time 29941006517 ps
CPU time 62.32 seconds
Started Jun 30 04:49:34 PM PDT 24
Finished Jun 30 04:50:37 PM PDT 24
Peak memory 210976 kb
Host smart-0fbb172a-6fdf-4e56-86af-429edc7a2ead
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374037122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2374037122
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2791146364
Short name T12
Test name
Test status
Simulation time 27523030491 ps
CPU time 83.21 seconds
Started Jun 30 04:50:58 PM PDT 24
Finished Jun 30 04:52:22 PM PDT 24
Peak memory 217284 kb
Host smart-03f17ed9-9060-48aa-bd94-d628241d6cf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791146364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2791146364
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2192454731
Short name T29
Test name
Test status
Simulation time 9735397540 ps
CPU time 34.88 seconds
Started Jun 30 04:51:15 PM PDT 24
Finished Jun 30 04:51:51 PM PDT 24
Peak memory 212212 kb
Host smart-7cc7fe21-c29c-4b3d-8456-83e3a371eadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192454731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2192454731
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3608246854
Short name T57
Test name
Test status
Simulation time 7870044207 ps
CPU time 21.06 seconds
Started Jun 30 04:50:46 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 212156 kb
Host smart-52aa4ee6-bcbd-4db8-8e4e-e85f45b14b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608246854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3608246854
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.268034317
Short name T105
Test name
Test status
Simulation time 4893060303 ps
CPU time 71.96 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:50:44 PM PDT 24
Peak memory 211576 kb
Host smart-8fa58d19-73f9-45b3-b65e-7d5ab09baedd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268034317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.268034317
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.612400775
Short name T207
Test name
Test status
Simulation time 73215219868 ps
CPU time 345.81 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:56:26 PM PDT 24
Peak memory 228472 kb
Host smart-9cd71b10-1892-4647-960e-40975e919510
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612400775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.612400775
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2928361822
Short name T64
Test name
Test status
Simulation time 2760229634 ps
CPU time 74.57 seconds
Started Jun 30 04:49:33 PM PDT 24
Finished Jun 30 04:50:48 PM PDT 24
Peak memory 218956 kb
Host smart-8ccbe10d-abba-45c3-864d-87c5318016ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928361822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2928361822
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2653117020
Short name T16
Test name
Test status
Simulation time 195263746581 ps
CPU time 1940.39 seconds
Started Jun 30 04:51:16 PM PDT 24
Finished Jun 30 05:23:37 PM PDT 24
Peak memory 236516 kb
Host smart-9e682ca5-ca37-4942-8b8b-2628fa930edc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653117020 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2653117020
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2834842467
Short name T157
Test name
Test status
Simulation time 353357765 ps
CPU time 10.54 seconds
Started Jun 30 04:50:15 PM PDT 24
Finished Jun 30 04:50:26 PM PDT 24
Peak memory 213964 kb
Host smart-0c8380da-3584-4eaa-af92-d980783f26ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834842467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2834842467
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4161308899
Short name T389
Test name
Test status
Simulation time 332318358 ps
CPU time 6.45 seconds
Started Jun 30 04:49:30 PM PDT 24
Finished Jun 30 04:49:37 PM PDT 24
Peak memory 217844 kb
Host smart-a0e5c65d-80e3-4301-a4c9-98ba62cc1a05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161308899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4161308899
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1370589613
Short name T422
Test name
Test status
Simulation time 883358147 ps
CPU time 6.75 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:40 PM PDT 24
Peak memory 210592 kb
Host smart-2f6d0873-2456-47fb-9d76-4d1cf2075adb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370589613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1370589613
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1749438433
Short name T72
Test name
Test status
Simulation time 7270037739 ps
CPU time 18.06 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:51 PM PDT 24
Peak memory 218520 kb
Host smart-dace58d5-bc89-40a9-a7fa-77c507d525da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749438433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1749438433
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.233641691
Short name T448
Test name
Test status
Simulation time 3978970716 ps
CPU time 11.6 seconds
Started Jun 30 04:49:33 PM PDT 24
Finished Jun 30 04:49:45 PM PDT 24
Peak memory 218996 kb
Host smart-62294869-73fa-4be9-93d0-b03c2a91a672
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233641691 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.233641691
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2602633345
Short name T406
Test name
Test status
Simulation time 631924687 ps
CPU time 8.48 seconds
Started Jun 30 04:49:34 PM PDT 24
Finished Jun 30 04:49:43 PM PDT 24
Peak memory 210632 kb
Host smart-d1c96705-76b6-4dc8-a343-2599fe1c17cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602633345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2602633345
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2678373458
Short name T399
Test name
Test status
Simulation time 3030097758 ps
CPU time 13.71 seconds
Started Jun 30 04:49:33 PM PDT 24
Finished Jun 30 04:49:47 PM PDT 24
Peak memory 210484 kb
Host smart-d4d34eac-a9e7-48e2-b1c8-ec73bd288860
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678373458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2678373458
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.805350620
Short name T365
Test name
Test status
Simulation time 168759237 ps
CPU time 4.22 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:36 PM PDT 24
Peak memory 210424 kb
Host smart-c92eaad8-878f-45f8-b38c-f61394f02afa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805350620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
805350620
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4131737924
Short name T416
Test name
Test status
Simulation time 7151324889 ps
CPU time 10.03 seconds
Started Jun 30 04:49:31 PM PDT 24
Finished Jun 30 04:49:41 PM PDT 24
Peak memory 211004 kb
Host smart-d49f6f0b-de22-4376-9ec9-b6df1b1d3e6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131737924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4131737924
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3718541653
Short name T460
Test name
Test status
Simulation time 7902559388 ps
CPU time 13.13 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:46 PM PDT 24
Peak memory 218992 kb
Host smart-65af4c2c-1995-4bfb-afe1-ec44271fbd84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718541653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3718541653
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2727267340
Short name T92
Test name
Test status
Simulation time 797025704 ps
CPU time 9.43 seconds
Started Jun 30 04:49:34 PM PDT 24
Finished Jun 30 04:49:44 PM PDT 24
Peak memory 218152 kb
Host smart-e39247a1-5a6d-46f9-bc21-6f1afebe8cc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727267340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2727267340
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2820025820
Short name T400
Test name
Test status
Simulation time 4548637720 ps
CPU time 11.66 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:44 PM PDT 24
Peak memory 210636 kb
Host smart-e907cabe-72ec-4afb-b603-caadc8a258a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820025820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2820025820
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1457003920
Short name T457
Test name
Test status
Simulation time 499420085 ps
CPU time 10.55 seconds
Started Jun 30 04:49:34 PM PDT 24
Finished Jun 30 04:49:45 PM PDT 24
Peak memory 218596 kb
Host smart-03307877-3bd2-411b-8830-889f00744663
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457003920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1457003920
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2918191405
Short name T420
Test name
Test status
Simulation time 2247943511 ps
CPU time 8.37 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:41 PM PDT 24
Peak memory 219024 kb
Host smart-6adca5f7-2a61-438d-b0e7-e9e14869dc9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918191405 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2918191405
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1571607328
Short name T464
Test name
Test status
Simulation time 24525214179 ps
CPU time 13.47 seconds
Started Jun 30 04:49:34 PM PDT 24
Finished Jun 30 04:49:48 PM PDT 24
Peak memory 217764 kb
Host smart-4e24c7f8-76fc-4de6-a421-ac9ac2706693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571607328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1571607328
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.195093823
Short name T390
Test name
Test status
Simulation time 1638759816 ps
CPU time 13.25 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:46 PM PDT 24
Peak memory 210560 kb
Host smart-eb004955-a373-476b-bd8f-1f2b5d2fe3e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195093823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.195093823
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.684595644
Short name T401
Test name
Test status
Simulation time 3634842559 ps
CPU time 15.16 seconds
Started Jun 30 04:49:35 PM PDT 24
Finished Jun 30 04:49:51 PM PDT 24
Peak memory 210596 kb
Host smart-e5a13fa0-0e67-4d1c-bdfd-6db944646fae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684595644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
684595644
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.569684365
Short name T90
Test name
Test status
Simulation time 5831293337 ps
CPU time 58.79 seconds
Started Jun 30 04:49:33 PM PDT 24
Finished Jun 30 04:50:32 PM PDT 24
Peak memory 218828 kb
Host smart-ce787b08-16d9-4b5b-86bb-45023151246e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569684365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.569684365
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1938546274
Short name T410
Test name
Test status
Simulation time 98126673 ps
CPU time 4.4 seconds
Started Jun 30 04:49:32 PM PDT 24
Finished Jun 30 04:49:36 PM PDT 24
Peak memory 218856 kb
Host smart-63f40f87-a649-48c2-a1ee-ee58b8bb550b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938546274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1938546274
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3966772443
Short name T368
Test name
Test status
Simulation time 1781491441 ps
CPU time 16.46 seconds
Started Jun 30 04:49:33 PM PDT 24
Finished Jun 30 04:49:51 PM PDT 24
Peak memory 218944 kb
Host smart-a743a517-9f17-4a0e-a888-75524be9e337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966772443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3966772443
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4101184902
Short name T394
Test name
Test status
Simulation time 1082662203 ps
CPU time 5.84 seconds
Started Jun 30 04:49:45 PM PDT 24
Finished Jun 30 04:49:51 PM PDT 24
Peak memory 212348 kb
Host smart-8064746a-fdb5-43e2-baae-a140e8aa2839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101184902 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4101184902
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1234061730
Short name T443
Test name
Test status
Simulation time 7336338790 ps
CPU time 14.9 seconds
Started Jun 30 04:49:48 PM PDT 24
Finished Jun 30 04:50:03 PM PDT 24
Peak memory 218684 kb
Host smart-c7410674-e6c4-4876-aed4-51ff142fa684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234061730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1234061730
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2826982456
Short name T455
Test name
Test status
Simulation time 65756905474 ps
CPU time 85.56 seconds
Started Jun 30 04:49:46 PM PDT 24
Finished Jun 30 04:51:13 PM PDT 24
Peak memory 210684 kb
Host smart-5d2e2f21-2c38-4639-921f-0e0aab077cc0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826982456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2826982456
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.175813400
Short name T444
Test name
Test status
Simulation time 4033500601 ps
CPU time 17.02 seconds
Started Jun 30 04:49:47 PM PDT 24
Finished Jun 30 04:50:05 PM PDT 24
Peak memory 210664 kb
Host smart-8d8e83dc-5362-4516-b399-8fa960b3375e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175813400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.175813400
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2348614891
Short name T383
Test name
Test status
Simulation time 1036979333 ps
CPU time 14.56 seconds
Started Jun 30 04:49:47 PM PDT 24
Finished Jun 30 04:50:02 PM PDT 24
Peak memory 218940 kb
Host smart-7108e9ac-4bc8-41df-8f22-cfeca87ed812
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348614891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2348614891
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.457386234
Short name T426
Test name
Test status
Simulation time 6899162834 ps
CPU time 44.37 seconds
Started Jun 30 04:49:49 PM PDT 24
Finished Jun 30 04:50:34 PM PDT 24
Peak memory 218924 kb
Host smart-c8ec0b04-0528-436a-88b0-ee987325ef21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457386234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.457386234
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3449549673
Short name T465
Test name
Test status
Simulation time 1228817291 ps
CPU time 11.19 seconds
Started Jun 30 04:49:57 PM PDT 24
Finished Jun 30 04:50:09 PM PDT 24
Peak memory 218872 kb
Host smart-16993c7b-7c53-4ad8-a796-444f932cda72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449549673 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3449549673
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.441643982
Short name T405
Test name
Test status
Simulation time 4987670790 ps
CPU time 9.85 seconds
Started Jun 30 04:49:58 PM PDT 24
Finished Jun 30 04:50:08 PM PDT 24
Peak memory 218724 kb
Host smart-b54d51ba-72d9-4a7c-ab65-01e84b528846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441643982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.441643982
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3865779343
Short name T431
Test name
Test status
Simulation time 6349147970 ps
CPU time 38.22 seconds
Started Jun 30 04:49:51 PM PDT 24
Finished Jun 30 04:50:30 PM PDT 24
Peak memory 211624 kb
Host smart-7b11b465-8a71-4048-a9e9-8fd7969810e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865779343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3865779343
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.400591373
Short name T78
Test name
Test status
Simulation time 5127599082 ps
CPU time 14.88 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:11 PM PDT 24
Peak memory 210824 kb
Host smart-3ba91bd1-5e19-4f7a-934c-34b8ecabc3f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400591373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.400591373
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1588911556
Short name T366
Test name
Test status
Simulation time 3289931082 ps
CPU time 13.56 seconds
Started Jun 30 04:49:53 PM PDT 24
Finished Jun 30 04:50:07 PM PDT 24
Peak memory 219012 kb
Host smart-1075046a-8750-4ae9-b3a4-fe9570070175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588911556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1588911556
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1147051549
Short name T109
Test name
Test status
Simulation time 11246600368 ps
CPU time 73.86 seconds
Started Jun 30 04:49:49 PM PDT 24
Finished Jun 30 04:51:03 PM PDT 24
Peak memory 218928 kb
Host smart-d67551cc-a2fd-47a4-b119-eb6f97a5fa59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147051549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1147051549
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2334308533
Short name T385
Test name
Test status
Simulation time 2112415530 ps
CPU time 16.81 seconds
Started Jun 30 04:49:53 PM PDT 24
Finished Jun 30 04:50:10 PM PDT 24
Peak memory 218956 kb
Host smart-ab8be536-263d-4765-a63e-3a546c454a86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334308533 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2334308533
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1908932837
Short name T454
Test name
Test status
Simulation time 174830133 ps
CPU time 4.23 seconds
Started Jun 30 04:49:57 PM PDT 24
Finished Jun 30 04:50:03 PM PDT 24
Peak memory 217400 kb
Host smart-a073c441-8a55-4572-be67-2496c595dc41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908932837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1908932837
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.456335747
Short name T96
Test name
Test status
Simulation time 8992683560 ps
CPU time 28.04 seconds
Started Jun 30 04:49:56 PM PDT 24
Finished Jun 30 04:50:26 PM PDT 24
Peak memory 210660 kb
Host smart-820f32da-99d0-4d65-a26f-cffbfa678824
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456335747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.456335747
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.402698324
Short name T67
Test name
Test status
Simulation time 8445229681 ps
CPU time 17.46 seconds
Started Jun 30 04:49:57 PM PDT 24
Finished Jun 30 04:50:16 PM PDT 24
Peak memory 210716 kb
Host smart-c493b9b6-b4f5-4910-bc16-9b57dcb636b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402698324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.402698324
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2845602710
Short name T421
Test name
Test status
Simulation time 1641664208 ps
CPU time 14.9 seconds
Started Jun 30 04:49:57 PM PDT 24
Finished Jun 30 04:50:13 PM PDT 24
Peak memory 218932 kb
Host smart-354dcf88-439b-447a-9106-18afc5b396be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845602710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2845602710
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.560680459
Short name T65
Test name
Test status
Simulation time 1120732916 ps
CPU time 36.3 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:33 PM PDT 24
Peak memory 210804 kb
Host smart-85d90fd1-9a29-4183-b279-3ac905c1701c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560680459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.560680459
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2289819869
Short name T370
Test name
Test status
Simulation time 1855240775 ps
CPU time 15.32 seconds
Started Jun 30 04:49:56 PM PDT 24
Finished Jun 30 04:50:13 PM PDT 24
Peak memory 218860 kb
Host smart-7b4b4f29-ca53-442e-801e-5cf0c2fb6667
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289819869 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2289819869
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2908225714
Short name T409
Test name
Test status
Simulation time 14102941958 ps
CPU time 13.61 seconds
Started Jun 30 04:49:54 PM PDT 24
Finished Jun 30 04:50:09 PM PDT 24
Peak memory 218680 kb
Host smart-c2caa238-d2a4-4d7b-8a80-f10896090f45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908225714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2908225714
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.471750811
Short name T91
Test name
Test status
Simulation time 6464225302 ps
CPU time 63.31 seconds
Started Jun 30 04:49:56 PM PDT 24
Finished Jun 30 04:51:01 PM PDT 24
Peak memory 210664 kb
Host smart-46d8f83a-b360-4aa8-bd55-686386d6a1c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471750811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.471750811
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1131241004
Short name T458
Test name
Test status
Simulation time 87212328 ps
CPU time 4.39 seconds
Started Jun 30 04:49:56 PM PDT 24
Finished Jun 30 04:50:01 PM PDT 24
Peak memory 218188 kb
Host smart-8808d670-d838-420e-82bd-437892c6a8c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131241004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1131241004
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.491597957
Short name T382
Test name
Test status
Simulation time 991713530 ps
CPU time 12.36 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:08 PM PDT 24
Peak memory 218828 kb
Host smart-98a67f1b-c3cc-4355-924e-9cdfc8dfc418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491597957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.491597957
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3096603695
Short name T408
Test name
Test status
Simulation time 4034545866 ps
CPU time 15.59 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:12 PM PDT 24
Peak memory 219012 kb
Host smart-56cd47ec-f4ce-47fb-8bcf-4588423a009a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096603695 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3096603695
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.960990800
Short name T435
Test name
Test status
Simulation time 174815420 ps
CPU time 4.3 seconds
Started Jun 30 04:49:57 PM PDT 24
Finished Jun 30 04:50:02 PM PDT 24
Peak memory 217908 kb
Host smart-4cb89360-463c-4ce5-aeb0-9700fe2f998c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960990800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.960990800
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1712088215
Short name T429
Test name
Test status
Simulation time 7983811247 ps
CPU time 31.3 seconds
Started Jun 30 04:49:58 PM PDT 24
Finished Jun 30 04:50:30 PM PDT 24
Peak memory 210724 kb
Host smart-f926d84a-cd9c-4aee-9e8e-fa717788a048
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712088215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1712088215
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.547025085
Short name T99
Test name
Test status
Simulation time 332804902 ps
CPU time 4.27 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:01 PM PDT 24
Peak memory 210764 kb
Host smart-6756fd03-f4e1-4492-9341-c667e5634981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547025085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.547025085
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.514104152
Short name T439
Test name
Test status
Simulation time 10304851758 ps
CPU time 16.59 seconds
Started Jun 30 04:49:57 PM PDT 24
Finished Jun 30 04:50:15 PM PDT 24
Peak memory 218868 kb
Host smart-b4b46ddd-9fa2-4241-8704-27e12f4e6b16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514104152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.514104152
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1777609764
Short name T107
Test name
Test status
Simulation time 301234475 ps
CPU time 71.79 seconds
Started Jun 30 04:49:56 PM PDT 24
Finished Jun 30 04:51:09 PM PDT 24
Peak memory 218892 kb
Host smart-9602bbf8-107f-41ca-8d8f-1ff610ae9218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777609764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1777609764
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.891709385
Short name T434
Test name
Test status
Simulation time 99411103 ps
CPU time 5.49 seconds
Started Jun 30 04:49:57 PM PDT 24
Finished Jun 30 04:50:03 PM PDT 24
Peak memory 218996 kb
Host smart-611bf1a3-ab32-433e-a81c-e5f4c93c6290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891709385 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.891709385
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2263527707
Short name T462
Test name
Test status
Simulation time 348118726 ps
CPU time 4.23 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:01 PM PDT 24
Peak memory 217648 kb
Host smart-280529b9-0124-47ef-988b-4308c419ca50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263527707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2263527707
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3391309893
Short name T75
Test name
Test status
Simulation time 40705165808 ps
CPU time 70.58 seconds
Started Jun 30 04:49:58 PM PDT 24
Finished Jun 30 04:51:09 PM PDT 24
Peak memory 210656 kb
Host smart-db5ae165-ba56-4a98-bfb0-c3ef9376022e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391309893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3391309893
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3513767938
Short name T79
Test name
Test status
Simulation time 3676757455 ps
CPU time 12.6 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:09 PM PDT 24
Peak memory 210852 kb
Host smart-93f7e23a-c37a-44d0-92a5-8f85cda05fae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513767938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3513767938
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3196219137
Short name T433
Test name
Test status
Simulation time 7981156101 ps
CPU time 17.69 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:14 PM PDT 24
Peak memory 218868 kb
Host smart-43a56b4e-25a8-4fa8-85fa-ae3b200820a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196219137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3196219137
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3850565144
Short name T463
Test name
Test status
Simulation time 1615160692 ps
CPU time 68.66 seconds
Started Jun 30 04:49:56 PM PDT 24
Finished Jun 30 04:51:06 PM PDT 24
Peak memory 212496 kb
Host smart-f1527350-1982-4307-a338-dc1a81c6a4e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850565144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3850565144
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2957434077
Short name T369
Test name
Test status
Simulation time 202128430 ps
CPU time 5.15 seconds
Started Jun 30 04:49:56 PM PDT 24
Finished Jun 30 04:50:03 PM PDT 24
Peak memory 218932 kb
Host smart-b46d8244-2d69-4628-8d82-a41adafd6616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957434077 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2957434077
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1693607719
Short name T453
Test name
Test status
Simulation time 296925645 ps
CPU time 6.32 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:03 PM PDT 24
Peak memory 217556 kb
Host smart-956fb5bf-0cae-4b8a-8c18-835b13bfc878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693607719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1693607719
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.4233916153
Short name T93
Test name
Test status
Simulation time 2864152794 ps
CPU time 27.66 seconds
Started Jun 30 04:49:55 PM PDT 24
Finished Jun 30 04:50:23 PM PDT 24
Peak memory 210700 kb
Host smart-dd7770df-daf1-48d9-9bb6-824b21e5ca67
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233916153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.4233916153
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3138091820
Short name T101
Test name
Test status
Simulation time 1805170458 ps
CPU time 9.62 seconds
Started Jun 30 04:49:56 PM PDT 24
Finished Jun 30 04:50:07 PM PDT 24
Peak memory 218848 kb
Host smart-5152e810-aaa0-43bb-8c7d-8e75cfb82a9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138091820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3138091820
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.641038290
Short name T398
Test name
Test status
Simulation time 8108019986 ps
CPU time 15.62 seconds
Started Jun 30 04:49:54 PM PDT 24
Finished Jun 30 04:50:11 PM PDT 24
Peak memory 218976 kb
Host smart-aaddd25c-da5c-46b6-9546-147b95b0790b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641038290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.641038290
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1088780855
Short name T106
Test name
Test status
Simulation time 3551668875 ps
CPU time 73.4 seconds
Started Jun 30 04:49:57 PM PDT 24
Finished Jun 30 04:51:12 PM PDT 24
Peak memory 212224 kb
Host smart-31d0be56-4ab1-4f54-87be-080aa2576865
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088780855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1088780855
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1734534225
Short name T425
Test name
Test status
Simulation time 1429498836 ps
CPU time 13.6 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:50:19 PM PDT 24
Peak memory 216936 kb
Host smart-d6e526af-eeb8-49e5-affe-64c7be590187
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734534225 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1734534225
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2993940721
Short name T103
Test name
Test status
Simulation time 85542701 ps
CPU time 4.18 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:50:09 PM PDT 24
Peak memory 210508 kb
Host smart-3d1541fd-5f02-4a96-b0bc-c128fcf5a080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993940721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2993940721
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2776028942
Short name T97
Test name
Test status
Simulation time 80656456658 ps
CPU time 92.71 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:51:38 PM PDT 24
Peak memory 210728 kb
Host smart-108a94d7-a3e6-46f5-a126-a3dbc0f771f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776028942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2776028942
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1494682218
Short name T74
Test name
Test status
Simulation time 2114095391 ps
CPU time 17.16 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:50:22 PM PDT 24
Peak memory 210696 kb
Host smart-0ef8bb12-af7c-4ad1-a302-adeede4c7e94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494682218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1494682218
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4195316033
Short name T428
Test name
Test status
Simulation time 1364052813 ps
CPU time 10.99 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:50:18 PM PDT 24
Peak memory 218840 kb
Host smart-47385d1e-33d1-4173-bd60-0fb23f002f32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195316033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4195316033
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1625239465
Short name T442
Test name
Test status
Simulation time 269654457 ps
CPU time 6.34 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:50:14 PM PDT 24
Peak memory 218868 kb
Host smart-1ff25998-a48c-40e7-9801-8519957834b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625239465 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1625239465
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1263235526
Short name T441
Test name
Test status
Simulation time 9123042905 ps
CPU time 14.85 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:21 PM PDT 24
Peak memory 218904 kb
Host smart-ca9c108c-ab74-4c4e-97f4-a1182d36a9c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263235526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1263235526
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2154645601
Short name T77
Test name
Test status
Simulation time 9418440742 ps
CPU time 43.3 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:50:48 PM PDT 24
Peak memory 210756 kb
Host smart-e39e497c-a398-4dc7-a65c-e30ecabd33eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154645601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2154645601
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3592605585
Short name T411
Test name
Test status
Simulation time 2409099077 ps
CPU time 12.53 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:19 PM PDT 24
Peak memory 210800 kb
Host smart-c7061b47-fce3-4b59-b189-f11e5582da54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592605585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3592605585
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3059907270
Short name T424
Test name
Test status
Simulation time 6925464674 ps
CPU time 14.59 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:50:18 PM PDT 24
Peak memory 218900 kb
Host smart-f55e3c64-43d1-447f-b0c2-43cebb53fb57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059907270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3059907270
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2817235590
Short name T445
Test name
Test status
Simulation time 1575067252 ps
CPU time 75.56 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 212180 kb
Host smart-07d85142-d76e-44b0-a99e-9f3c4e063304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817235590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2817235590
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2210416377
Short name T381
Test name
Test status
Simulation time 306675202 ps
CPU time 6.68 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:50:11 PM PDT 24
Peak memory 218864 kb
Host smart-a37b5b55-88c1-4c91-a1fc-76eca947d697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210416377 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2210416377
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2315357855
Short name T397
Test name
Test status
Simulation time 1496509928 ps
CPU time 10.34 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:50:15 PM PDT 24
Peak memory 217704 kb
Host smart-5364895b-08d7-4236-b2bb-c447090e3acd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315357855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2315357855
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.864871047
Short name T88
Test name
Test status
Simulation time 6881848166 ps
CPU time 66.85 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:51:12 PM PDT 24
Peak memory 211772 kb
Host smart-5b72c680-24de-425b-bed2-f136f9fa3384
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864871047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.864871047
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1754068429
Short name T437
Test name
Test status
Simulation time 1433725599 ps
CPU time 13.98 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:50:19 PM PDT 24
Peak memory 210636 kb
Host smart-bf1214aa-0772-4b05-9fda-a0c12af7d67a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754068429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1754068429
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1387197389
Short name T440
Test name
Test status
Simulation time 8380281923 ps
CPU time 19 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:50:26 PM PDT 24
Peak memory 219008 kb
Host smart-79fb6179-34eb-4e04-82f7-569f0da707af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387197389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1387197389
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.488205183
Short name T374
Test name
Test status
Simulation time 3126866646 ps
CPU time 39.95 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:46 PM PDT 24
Peak memory 218924 kb
Host smart-af5ed7e8-18ca-4a6c-9411-b0445b6e9070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488205183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.488205183
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1383778381
Short name T380
Test name
Test status
Simulation time 4093115812 ps
CPU time 10.38 seconds
Started Jun 30 04:49:43 PM PDT 24
Finished Jun 30 04:49:54 PM PDT 24
Peak memory 209844 kb
Host smart-249192fb-950f-4ce8-a73c-f1c365d0d324
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383778381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1383778381
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.856156323
Short name T102
Test name
Test status
Simulation time 1284301067 ps
CPU time 12.05 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:55 PM PDT 24
Peak memory 210588 kb
Host smart-05ee11bc-cb87-4d38-86d0-e845e228159e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856156323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.856156323
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3747335183
Short name T68
Test name
Test status
Simulation time 1530030138 ps
CPU time 16.67 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:49:58 PM PDT 24
Peak memory 210568 kb
Host smart-fbe8971a-06c6-4af5-b931-6d1c58c77bfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747335183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3747335183
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1662099022
Short name T392
Test name
Test status
Simulation time 309001067 ps
CPU time 6.46 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:49:48 PM PDT 24
Peak memory 218788 kb
Host smart-1a894165-24de-48a9-9424-2063bfcf70fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662099022 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1662099022
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3586316602
Short name T436
Test name
Test status
Simulation time 4625184696 ps
CPU time 11.35 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:53 PM PDT 24
Peak memory 217968 kb
Host smart-7de325ff-022a-483d-a7c1-b44c13691c9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586316602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3586316602
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4074223434
Short name T402
Test name
Test status
Simulation time 865343726 ps
CPU time 5.56 seconds
Started Jun 30 04:49:43 PM PDT 24
Finished Jun 30 04:49:49 PM PDT 24
Peak memory 210432 kb
Host smart-06ff209c-6ea3-4dbd-8d17-21e443cac403
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074223434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4074223434
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3738315872
Short name T407
Test name
Test status
Simulation time 1940935012 ps
CPU time 15.03 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:56 PM PDT 24
Peak memory 210560 kb
Host smart-93956cc5-4d5a-47ff-84cb-9e2347486d04
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738315872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3738315872
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1186537261
Short name T95
Test name
Test status
Simulation time 8306385128 ps
CPU time 62.34 seconds
Started Jun 30 04:49:33 PM PDT 24
Finished Jun 30 04:50:36 PM PDT 24
Peak memory 210636 kb
Host smart-fa6d0c73-1832-431f-a075-5372272cb1f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186537261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1186537261
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2278002450
Short name T418
Test name
Test status
Simulation time 333134432 ps
CPU time 4.17 seconds
Started Jun 30 04:49:39 PM PDT 24
Finished Jun 30 04:49:44 PM PDT 24
Peak memory 218020 kb
Host smart-2bd15b2f-22af-4128-873a-02be9f1d392f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278002450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2278002450
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4005019414
Short name T403
Test name
Test status
Simulation time 192698040 ps
CPU time 8.03 seconds
Started Jun 30 04:49:31 PM PDT 24
Finished Jun 30 04:49:39 PM PDT 24
Peak memory 218804 kb
Host smart-58f68c8d-1ce9-4371-bb4a-f874ffb4a8e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005019414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4005019414
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3529652862
Short name T384
Test name
Test status
Simulation time 152799476 ps
CPU time 36.94 seconds
Started Jun 30 04:49:39 PM PDT 24
Finished Jun 30 04:50:16 PM PDT 24
Peak memory 211188 kb
Host smart-796d769a-49af-4b6e-bda0-1f1db872c35b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529652862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3529652862
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.628043685
Short name T89
Test name
Test status
Simulation time 540577842 ps
CPU time 7.75 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:49 PM PDT 24
Peak memory 217304 kb
Host smart-341360b8-3ed6-4b78-94eb-17553d87a616
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628043685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.628043685
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2005157203
Short name T393
Test name
Test status
Simulation time 4116095572 ps
CPU time 15.69 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:56 PM PDT 24
Peak memory 210624 kb
Host smart-4af81692-b1c0-4cb5-9387-ebf921660ceb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005157203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2005157203
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3218450081
Short name T66
Test name
Test status
Simulation time 3107426130 ps
CPU time 18.97 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:59 PM PDT 24
Peak memory 211032 kb
Host smart-3cf9d57e-979f-4015-971a-26e10b7fc73a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218450081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3218450081
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.789480023
Short name T388
Test name
Test status
Simulation time 1767995833 ps
CPU time 9.39 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:51 PM PDT 24
Peak memory 218912 kb
Host smart-acb760d3-cefb-4f98-b05c-bf20fd35bb10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789480023 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.789480023
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2673510000
Short name T423
Test name
Test status
Simulation time 20469602759 ps
CPU time 11.88 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:49:54 PM PDT 24
Peak memory 218832 kb
Host smart-a378a055-bc3d-49ee-a575-9defcecb86fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673510000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2673510000
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.676108353
Short name T446
Test name
Test status
Simulation time 1979406216 ps
CPU time 15.08 seconds
Started Jun 30 04:49:39 PM PDT 24
Finished Jun 30 04:49:55 PM PDT 24
Peak memory 210460 kb
Host smart-3d60b80b-f83f-464a-8e47-b675100b6137
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676108353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.676108353
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3629644100
Short name T449
Test name
Test status
Simulation time 1273331285 ps
CPU time 11.07 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:51 PM PDT 24
Peak memory 210456 kb
Host smart-573f29d8-f76c-4cd4-8ff7-e0e05acd6afa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629644100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3629644100
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2132114660
Short name T98
Test name
Test status
Simulation time 3297004922 ps
CPU time 13.89 seconds
Started Jun 30 04:49:45 PM PDT 24
Finished Jun 30 04:50:00 PM PDT 24
Peak memory 218648 kb
Host smart-88d7ca67-6285-465f-a406-4d446fcaa149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132114660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2132114660
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.890537137
Short name T432
Test name
Test status
Simulation time 1425099598 ps
CPU time 15.45 seconds
Started Jun 30 04:49:45 PM PDT 24
Finished Jun 30 04:50:01 PM PDT 24
Peak memory 218580 kb
Host smart-d42539bc-932f-47a5-a528-aa10f8dd566f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890537137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.890537137
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1494795096
Short name T110
Test name
Test status
Simulation time 296557384 ps
CPU time 70.83 seconds
Started Jun 30 04:49:44 PM PDT 24
Finished Jun 30 04:50:55 PM PDT 24
Peak memory 212080 kb
Host smart-bc09de86-693c-4c43-8853-e2cd9a79438a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494795096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1494795096
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3079601967
Short name T386
Test name
Test status
Simulation time 436810592 ps
CPU time 4.38 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:45 PM PDT 24
Peak memory 217872 kb
Host smart-7ac87726-3076-4808-b0b7-6e73deef176f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079601967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3079601967
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3631607228
Short name T461
Test name
Test status
Simulation time 7410877324 ps
CPU time 16.06 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:59 PM PDT 24
Peak memory 210752 kb
Host smart-12fb3ab6-1066-4581-b919-1737d0c37a4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631607228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3631607228
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3955066665
Short name T412
Test name
Test status
Simulation time 1905192882 ps
CPU time 14.08 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:57 PM PDT 24
Peak memory 210704 kb
Host smart-7150476b-06d6-4687-b8ef-a534cfc1c419
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955066665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3955066665
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1919929379
Short name T373
Test name
Test status
Simulation time 523087235 ps
CPU time 7.71 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:49:49 PM PDT 24
Peak memory 218768 kb
Host smart-baddc08c-7732-4c51-8d32-38c662d8b0c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919929379 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1919929379
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2039897590
Short name T391
Test name
Test status
Simulation time 1783491375 ps
CPU time 13.52 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:56 PM PDT 24
Peak memory 210632 kb
Host smart-bfc1a12a-d7f4-4a81-92af-5f605c056d8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039897590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2039897590
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1132147512
Short name T447
Test name
Test status
Simulation time 2389287911 ps
CPU time 7.22 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:50 PM PDT 24
Peak memory 210576 kb
Host smart-9a8ed731-f67a-434c-8553-4f11a582c178
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132147512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1132147512
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3616288394
Short name T395
Test name
Test status
Simulation time 2664673186 ps
CPU time 10.59 seconds
Started Jun 30 04:49:43 PM PDT 24
Finished Jun 30 04:49:54 PM PDT 24
Peak memory 209808 kb
Host smart-0b8208ac-092e-4c9b-8770-09f4835ce01d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616288394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3616288394
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1818893320
Short name T452
Test name
Test status
Simulation time 1514205729 ps
CPU time 19.1 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:50:01 PM PDT 24
Peak memory 210596 kb
Host smart-e72e7baf-f730-4a35-a39c-60012701732f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818893320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1818893320
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2126744045
Short name T451
Test name
Test status
Simulation time 2459734514 ps
CPU time 11.61 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:55 PM PDT 24
Peak memory 210784 kb
Host smart-631173d8-2ad7-4046-89a5-075e6be96422
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126744045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2126744045
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.104107899
Short name T371
Test name
Test status
Simulation time 2734231829 ps
CPU time 17.58 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:59 PM PDT 24
Peak memory 219272 kb
Host smart-1ee48326-6a1b-4d5c-8299-73daad4c4177
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104107899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.104107899
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.525640340
Short name T112
Test name
Test status
Simulation time 2028332949 ps
CPU time 41.3 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:50:23 PM PDT 24
Peak memory 218896 kb
Host smart-ca99c466-b2eb-4156-aca8-9af70b196658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525640340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.525640340
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2597416962
Short name T376
Test name
Test status
Simulation time 1601586052 ps
CPU time 13.38 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:56 PM PDT 24
Peak memory 218816 kb
Host smart-fbc3f83d-8d5b-41f6-8c14-53d20f9f789e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597416962 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2597416962
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1631627615
Short name T375
Test name
Test status
Simulation time 2786949265 ps
CPU time 12.74 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:49:54 PM PDT 24
Peak memory 210652 kb
Host smart-3717ffee-d56c-493f-8721-da1ea3988a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631627615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1631627615
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2901951851
Short name T87
Test name
Test status
Simulation time 5826443296 ps
CPU time 50.96 seconds
Started Jun 30 04:49:43 PM PDT 24
Finished Jun 30 04:50:35 PM PDT 24
Peak memory 210704 kb
Host smart-cec949a7-9e37-49ef-9f3b-ef38cb703e49
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901951851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2901951851
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.336087051
Short name T438
Test name
Test status
Simulation time 19716932201 ps
CPU time 14.53 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:57 PM PDT 24
Peak memory 210808 kb
Host smart-bc35e0bc-db14-420d-a1b7-f7a1e4ad9357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336087051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.336087051
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3887042604
Short name T387
Test name
Test status
Simulation time 167981210 ps
CPU time 7.02 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:49:49 PM PDT 24
Peak memory 218940 kb
Host smart-80037bfd-3292-4401-a18d-29facee30f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887042604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3887042604
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3552341380
Short name T115
Test name
Test status
Simulation time 1570582891 ps
CPU time 44.12 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:50:26 PM PDT 24
Peak memory 212152 kb
Host smart-cc73983e-1b11-4bb6-addf-a52fdde19703
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552341380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3552341380
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.539764534
Short name T367
Test name
Test status
Simulation time 3498505980 ps
CPU time 10.2 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:49:52 PM PDT 24
Peak memory 219020 kb
Host smart-482621be-690c-453e-ab2e-5b3f8b37f91e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539764534 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.539764534
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.880018427
Short name T396
Test name
Test status
Simulation time 4882436338 ps
CPU time 14.28 seconds
Started Jun 30 04:49:41 PM PDT 24
Finished Jun 30 04:49:56 PM PDT 24
Peak memory 210656 kb
Host smart-1e2664da-af34-4dc0-8325-3047fbf5d848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880018427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.880018427
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3523412967
Short name T419
Test name
Test status
Simulation time 1332075444 ps
CPU time 18.6 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:50:01 PM PDT 24
Peak memory 210596 kb
Host smart-b6b01ba3-d450-446e-beb9-8092b3007d24
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523412967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3523412967
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2186913866
Short name T413
Test name
Test status
Simulation time 4790117279 ps
CPU time 11.53 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:54 PM PDT 24
Peak memory 210936 kb
Host smart-75490208-aa79-40ed-be59-c509857f81d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186913866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2186913866
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2834275258
Short name T372
Test name
Test status
Simulation time 127874512 ps
CPU time 6.53 seconds
Started Jun 30 04:49:42 PM PDT 24
Finished Jun 30 04:49:49 PM PDT 24
Peak memory 218948 kb
Host smart-6dde09fb-2234-4902-b316-d51dedeb2818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834275258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2834275258
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1091275889
Short name T116
Test name
Test status
Simulation time 163072917 ps
CPU time 36.42 seconds
Started Jun 30 04:49:40 PM PDT 24
Finished Jun 30 04:50:17 PM PDT 24
Peak memory 210780 kb
Host smart-64bf005e-2116-490c-9453-3d39db79948f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091275889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1091275889
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1599498631
Short name T379
Test name
Test status
Simulation time 120672381 ps
CPU time 5.21 seconds
Started Jun 30 04:49:47 PM PDT 24
Finished Jun 30 04:49:53 PM PDT 24
Peak memory 214236 kb
Host smart-998c868a-e531-4a0e-8227-73cd17bd5f95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599498631 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1599498631
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1561444033
Short name T430
Test name
Test status
Simulation time 7618007500 ps
CPU time 15.15 seconds
Started Jun 30 04:49:47 PM PDT 24
Finished Jun 30 04:50:02 PM PDT 24
Peak memory 218792 kb
Host smart-22a8ae0d-a1ab-4c55-895a-7c3d32d20e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561444033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1561444033
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3803886963
Short name T73
Test name
Test status
Simulation time 32869431381 ps
CPU time 55.8 seconds
Started Jun 30 04:49:46 PM PDT 24
Finished Jun 30 04:50:42 PM PDT 24
Peak memory 210648 kb
Host smart-cc128c33-778b-4d3f-bdc1-5781a6276cd2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803886963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3803886963
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3647166527
Short name T417
Test name
Test status
Simulation time 2835844190 ps
CPU time 12.11 seconds
Started Jun 30 04:49:50 PM PDT 24
Finished Jun 30 04:50:02 PM PDT 24
Peak memory 210824 kb
Host smart-6c42c70b-6ccc-4f81-9546-03dc5acfc7e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647166527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3647166527
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1477748676
Short name T459
Test name
Test status
Simulation time 5652821681 ps
CPU time 15.98 seconds
Started Jun 30 04:49:47 PM PDT 24
Finished Jun 30 04:50:03 PM PDT 24
Peak memory 219012 kb
Host smart-7c4ca9c5-0190-4714-93a9-960b36885db4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477748676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1477748676
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1975993782
Short name T113
Test name
Test status
Simulation time 290585548 ps
CPU time 69.51 seconds
Started Jun 30 04:49:47 PM PDT 24
Finished Jun 30 04:50:57 PM PDT 24
Peak memory 218796 kb
Host smart-d04993b3-6f9b-4450-842d-fe86fec2807e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975993782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1975993782
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2419386442
Short name T414
Test name
Test status
Simulation time 3275079548 ps
CPU time 9.03 seconds
Started Jun 30 04:49:48 PM PDT 24
Finished Jun 30 04:49:57 PM PDT 24
Peak memory 212916 kb
Host smart-2faec1e1-8ab5-4591-8933-fe039a82d0a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419386442 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2419386442
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1417370329
Short name T427
Test name
Test status
Simulation time 88243808 ps
CPU time 4.24 seconds
Started Jun 30 04:49:47 PM PDT 24
Finished Jun 30 04:49:52 PM PDT 24
Peak memory 210676 kb
Host smart-fc001f62-7772-47c7-8e78-862bf18409c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417370329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1417370329
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.496750536
Short name T94
Test name
Test status
Simulation time 78641835264 ps
CPU time 57.12 seconds
Started Jun 30 04:49:49 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 210756 kb
Host smart-b84b94d2-70d3-4f01-b88a-8137ac42aa58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496750536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.496750536
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.835990193
Short name T100
Test name
Test status
Simulation time 3288051520 ps
CPU time 13.53 seconds
Started Jun 30 04:49:45 PM PDT 24
Finished Jun 30 04:49:58 PM PDT 24
Peak memory 218860 kb
Host smart-ceaef1b3-bef9-47ad-b1b3-973d69cbf378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835990193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.835990193
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1616206357
Short name T378
Test name
Test status
Simulation time 291480707 ps
CPU time 10.53 seconds
Started Jun 30 04:49:47 PM PDT 24
Finished Jun 30 04:49:58 PM PDT 24
Peak memory 218900 kb
Host smart-8acd196b-3304-4e05-aa23-0c05142f110b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616206357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1616206357
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2410325707
Short name T111
Test name
Test status
Simulation time 9904776990 ps
CPU time 77.77 seconds
Started Jun 30 04:49:51 PM PDT 24
Finished Jun 30 04:51:09 PM PDT 24
Peak memory 212488 kb
Host smart-5ccf4123-6307-453f-8aac-8d1b0a5ac0c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410325707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2410325707
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2419300346
Short name T415
Test name
Test status
Simulation time 2075576264 ps
CPU time 10.47 seconds
Started Jun 30 04:49:51 PM PDT 24
Finished Jun 30 04:50:02 PM PDT 24
Peak memory 218792 kb
Host smart-1faa6b8d-30ab-4fa4-8790-36819e50ba3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419300346 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2419300346
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.143811891
Short name T456
Test name
Test status
Simulation time 5940511231 ps
CPU time 13.78 seconds
Started Jun 30 04:49:51 PM PDT 24
Finished Jun 30 04:50:05 PM PDT 24
Peak memory 210764 kb
Host smart-9b1bf811-9b57-413c-af9e-4f1d8366760a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143811891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.143811891
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.624782450
Short name T450
Test name
Test status
Simulation time 380938322 ps
CPU time 18.83 seconds
Started Jun 30 04:49:49 PM PDT 24
Finished Jun 30 04:50:09 PM PDT 24
Peak memory 210604 kb
Host smart-cf1fc6b4-87ac-4574-84fb-6c3cbd2321e6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624782450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.624782450
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.92869062
Short name T404
Test name
Test status
Simulation time 4310455578 ps
CPU time 16.53 seconds
Started Jun 30 04:49:50 PM PDT 24
Finished Jun 30 04:50:07 PM PDT 24
Peak memory 210760 kb
Host smart-cea85706-c952-4074-910b-dce1d04b3865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92869062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctr
l_same_csr_outstanding.92869062
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1736851766
Short name T377
Test name
Test status
Simulation time 2453418359 ps
CPU time 13.11 seconds
Started Jun 30 04:49:47 PM PDT 24
Finished Jun 30 04:50:00 PM PDT 24
Peak memory 218996 kb
Host smart-3c44bc55-9e7d-47cd-82c5-7b784ae8d430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736851766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1736851766
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.488108977
Short name T114
Test name
Test status
Simulation time 157916482 ps
CPU time 35.89 seconds
Started Jun 30 04:49:45 PM PDT 24
Finished Jun 30 04:50:22 PM PDT 24
Peak memory 218740 kb
Host smart-9ee2bcd7-1701-40b6-9881-57ee871fc896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488108977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.488108977
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1038752968
Short name T240
Test name
Test status
Simulation time 5132476424 ps
CPU time 11.88 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:50:19 PM PDT 24
Peak memory 211376 kb
Host smart-e20d3f75-f7c3-4f0d-aa39-5130eaa28853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038752968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1038752968
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1733019868
Short name T177
Test name
Test status
Simulation time 1751820306 ps
CPU time 58.98 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:51:05 PM PDT 24
Peak memory 236068 kb
Host smart-35987869-2662-44ac-8de2-8e395f9263a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733019868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1733019868
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4151294453
Short name T248
Test name
Test status
Simulation time 2543855692 ps
CPU time 24.89 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:31 PM PDT 24
Peak memory 211952 kb
Host smart-a1c8466c-f269-407c-9eaa-9bf15b62b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151294453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4151294453
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2814192816
Short name T4
Test name
Test status
Simulation time 199179453 ps
CPU time 5.62 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:50:10 PM PDT 24
Peak memory 211288 kb
Host smart-3e60a231-51fd-41ee-aa4e-f0c7ed40d33e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814192816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2814192816
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2876040128
Short name T31
Test name
Test status
Simulation time 2172714058 ps
CPU time 109.61 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 235996 kb
Host smart-d8c93119-d1be-4d25-bd40-3a12bbaf44e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876040128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2876040128
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2146397633
Short name T84
Test name
Test status
Simulation time 3686655681 ps
CPU time 39.41 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:50:45 PM PDT 24
Peak memory 213804 kb
Host smart-d2d25571-723b-4e49-9546-a9f3621ac07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146397633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2146397633
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2954025452
Short name T45
Test name
Test status
Simulation time 27646708296 ps
CPU time 284.65 seconds
Started Jun 30 04:50:07 PM PDT 24
Finished Jun 30 04:54:53 PM PDT 24
Peak memory 234376 kb
Host smart-c0601565-549a-4716-9fa2-49efe59383fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954025452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2954025452
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2038692380
Short name T233
Test name
Test status
Simulation time 2222523159 ps
CPU time 14.03 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:20 PM PDT 24
Peak memory 211868 kb
Host smart-0b8f7d56-4291-469d-9846-c764c586f369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038692380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2038692380
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2860012258
Short name T231
Test name
Test status
Simulation time 8077448027 ps
CPU time 17.56 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:24 PM PDT 24
Peak memory 211416 kb
Host smart-13848fe6-028e-433d-8362-8806a751b83f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2860012258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2860012258
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3392628838
Short name T180
Test name
Test status
Simulation time 191803048 ps
CPU time 10.42 seconds
Started Jun 30 04:50:08 PM PDT 24
Finished Jun 30 04:50:19 PM PDT 24
Peak memory 213520 kb
Host smart-8a4f2dff-1722-4f8c-86da-1b57b1b2e756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392628838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3392628838
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1726230591
Short name T236
Test name
Test status
Simulation time 2089636828 ps
CPU time 40.28 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 215120 kb
Host smart-dd31b1f1-0cfc-486b-9a1e-2ba1f3f9669d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726230591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1726230591
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1567767916
Short name T274
Test name
Test status
Simulation time 6295558896 ps
CPU time 13.43 seconds
Started Jun 30 04:50:16 PM PDT 24
Finished Jun 30 04:50:30 PM PDT 24
Peak memory 211360 kb
Host smart-26ea2198-81f5-42f6-8acc-2693b9e86e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567767916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1567767916
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1693436925
Short name T117
Test name
Test status
Simulation time 11461116274 ps
CPU time 117.02 seconds
Started Jun 30 04:50:16 PM PDT 24
Finished Jun 30 04:52:14 PM PDT 24
Peak memory 236748 kb
Host smart-596ac083-5e2e-473d-9c41-1da16bda6b8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693436925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1693436925
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3303446557
Short name T279
Test name
Test status
Simulation time 1037286523 ps
CPU time 9.66 seconds
Started Jun 30 04:50:12 PM PDT 24
Finished Jun 30 04:50:22 PM PDT 24
Peak memory 212184 kb
Host smart-27951114-c20a-45ac-b0c7-344105be5197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303446557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3303446557
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.970989680
Short name T122
Test name
Test status
Simulation time 1531983821 ps
CPU time 14.17 seconds
Started Jun 30 04:50:14 PM PDT 24
Finished Jun 30 04:50:28 PM PDT 24
Peak memory 211280 kb
Host smart-20d35f4f-96a9-4d09-acf0-2d4be1c66b77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970989680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.970989680
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3820047416
Short name T81
Test name
Test status
Simulation time 498189083 ps
CPU time 10.67 seconds
Started Jun 30 04:50:12 PM PDT 24
Finished Jun 30 04:50:23 PM PDT 24
Peak memory 213924 kb
Host smart-fdaf1213-5aae-4d5d-8d4d-0a37a1c7038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820047416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3820047416
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.363821148
Short name T135
Test name
Test status
Simulation time 32942168580 ps
CPU time 78.45 seconds
Started Jun 30 04:50:11 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 219400 kb
Host smart-50de3c9f-36a7-445a-b1a9-6ab70ade9afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363821148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.363821148
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3395291425
Short name T330
Test name
Test status
Simulation time 7170743720 ps
CPU time 15.11 seconds
Started Jun 30 04:50:10 PM PDT 24
Finished Jun 30 04:50:25 PM PDT 24
Peak memory 211304 kb
Host smart-6519d12a-f3c6-409f-b8dc-9ca7f577c2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395291425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3395291425
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.99238704
Short name T322
Test name
Test status
Simulation time 8708455900 ps
CPU time 131.09 seconds
Started Jun 30 04:50:12 PM PDT 24
Finished Jun 30 04:52:23 PM PDT 24
Peak memory 212076 kb
Host smart-a4374cf9-f217-4af0-af55-d1b6fc4c9564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99238704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_co
rrupt_sig_fatal_chk.99238704
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1720830057
Short name T348
Test name
Test status
Simulation time 1290861580 ps
CPU time 17.09 seconds
Started Jun 30 04:50:13 PM PDT 24
Finished Jun 30 04:50:31 PM PDT 24
Peak memory 212088 kb
Host smart-89cb5210-3c5c-4171-a69e-2c0a842e9b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720830057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1720830057
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2627310749
Short name T40
Test name
Test status
Simulation time 160359285 ps
CPU time 5.41 seconds
Started Jun 30 04:50:15 PM PDT 24
Finished Jun 30 04:50:20 PM PDT 24
Peak memory 211276 kb
Host smart-5907778f-7cd7-4e58-b51b-65adef3fffbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627310749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2627310749
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.16268919
Short name T83
Test name
Test status
Simulation time 1545158284 ps
CPU time 21.6 seconds
Started Jun 30 04:50:15 PM PDT 24
Finished Jun 30 04:50:37 PM PDT 24
Peak memory 213596 kb
Host smart-0f4c5ba4-a34d-41b4-987e-ac5c2f645cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16268919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.16268919
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3695596497
Short name T272
Test name
Test status
Simulation time 43751570295 ps
CPU time 30.8 seconds
Started Jun 30 04:50:11 PM PDT 24
Finished Jun 30 04:50:43 PM PDT 24
Peak memory 214140 kb
Host smart-2978846b-68c6-4d7d-b584-b51e503c9871
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695596497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3695596497
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3622995049
Short name T211
Test name
Test status
Simulation time 171902206 ps
CPU time 4.13 seconds
Started Jun 30 04:50:17 PM PDT 24
Finished Jun 30 04:50:22 PM PDT 24
Peak memory 211292 kb
Host smart-d509d13f-235a-4e53-8f14-c2cfa009f594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622995049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3622995049
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1537003412
Short name T332
Test name
Test status
Simulation time 10328594032 ps
CPU time 164.07 seconds
Started Jun 30 04:50:13 PM PDT 24
Finished Jun 30 04:52:58 PM PDT 24
Peak memory 225504 kb
Host smart-8013ba01-dec9-4bdc-914f-9d65050f3534
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537003412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1537003412
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4228617382
Short name T333
Test name
Test status
Simulation time 378645772 ps
CPU time 5.21 seconds
Started Jun 30 04:50:15 PM PDT 24
Finished Jun 30 04:50:21 PM PDT 24
Peak memory 211292 kb
Host smart-3ce045db-bf41-4855-bbe7-fe4d034b15d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228617382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4228617382
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3927055538
Short name T269
Test name
Test status
Simulation time 1186560701 ps
CPU time 16.67 seconds
Started Jun 30 04:50:14 PM PDT 24
Finished Jun 30 04:50:31 PM PDT 24
Peak memory 212068 kb
Host smart-ad8ca811-fea2-4b73-ad9b-b73a50d7ca21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927055538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3927055538
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.426440735
Short name T169
Test name
Test status
Simulation time 85474491 ps
CPU time 4.22 seconds
Started Jun 30 04:50:16 PM PDT 24
Finished Jun 30 04:50:21 PM PDT 24
Peak memory 211176 kb
Host smart-26a7e77c-6f0b-4522-ae62-c50537b0ccb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426440735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.426440735
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.659712467
Short name T241
Test name
Test status
Simulation time 4400332996 ps
CPU time 93.89 seconds
Started Jun 30 04:50:20 PM PDT 24
Finished Jun 30 04:51:54 PM PDT 24
Peak memory 225608 kb
Host smart-a5434f6e-b34e-40ad-9c0a-f2168826c8f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659712467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.659712467
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1538430556
Short name T179
Test name
Test status
Simulation time 4173550325 ps
CPU time 33.74 seconds
Started Jun 30 04:50:18 PM PDT 24
Finished Jun 30 04:50:52 PM PDT 24
Peak memory 211788 kb
Host smart-ae3dc710-7741-4919-a8aa-0f3852edb01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538430556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1538430556
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.591056647
Short name T299
Test name
Test status
Simulation time 3449865814 ps
CPU time 10.37 seconds
Started Jun 30 04:50:19 PM PDT 24
Finished Jun 30 04:50:30 PM PDT 24
Peak memory 211428 kb
Host smart-4b8d443d-6353-400c-a9ff-ea6fb7db521d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591056647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.591056647
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1985998521
Short name T268
Test name
Test status
Simulation time 2332719757 ps
CPU time 22.84 seconds
Started Jun 30 04:50:19 PM PDT 24
Finished Jun 30 04:50:42 PM PDT 24
Peak memory 212068 kb
Host smart-d9e1c57a-45ae-4560-a9ea-03125327d9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985998521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1985998521
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.200988706
Short name T166
Test name
Test status
Simulation time 1418190923 ps
CPU time 23.63 seconds
Started Jun 30 04:50:17 PM PDT 24
Finished Jun 30 04:50:41 PM PDT 24
Peak memory 216316 kb
Host smart-57eac072-ad5d-4647-9ac3-d88fa71c50f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200988706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.200988706
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.916360796
Short name T69
Test name
Test status
Simulation time 171160521 ps
CPU time 4.15 seconds
Started Jun 30 04:50:20 PM PDT 24
Finished Jun 30 04:50:25 PM PDT 24
Peak memory 211212 kb
Host smart-19e55c7a-1c0c-4b86-bffc-415d82218a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916360796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.916360796
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1404621975
Short name T242
Test name
Test status
Simulation time 303712827349 ps
CPU time 402.34 seconds
Started Jun 30 04:50:18 PM PDT 24
Finished Jun 30 04:57:01 PM PDT 24
Peak memory 228588 kb
Host smart-c11a60e7-a39a-48b6-9020-6414edc6b5c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404621975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1404621975
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2102935188
Short name T297
Test name
Test status
Simulation time 6364745382 ps
CPU time 26.38 seconds
Started Jun 30 04:50:19 PM PDT 24
Finished Jun 30 04:50:46 PM PDT 24
Peak memory 212464 kb
Host smart-5a301e57-5d6d-481d-b60c-a6e277a05468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102935188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2102935188
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.671521107
Short name T132
Test name
Test status
Simulation time 442849014 ps
CPU time 8.34 seconds
Started Jun 30 04:50:19 PM PDT 24
Finished Jun 30 04:50:28 PM PDT 24
Peak memory 211304 kb
Host smart-af566a03-a1d7-48e6-918f-56d0ecb20c37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671521107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.671521107
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2182816528
Short name T165
Test name
Test status
Simulation time 10371590857 ps
CPU time 24.07 seconds
Started Jun 30 04:50:19 PM PDT 24
Finished Jun 30 04:50:44 PM PDT 24
Peak memory 214240 kb
Host smart-2eea7a46-2155-4b3b-9f73-cbed9d7e6df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182816528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2182816528
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1209457638
Short name T308
Test name
Test status
Simulation time 611444163 ps
CPU time 16.69 seconds
Started Jun 30 04:50:20 PM PDT 24
Finished Jun 30 04:50:37 PM PDT 24
Peak memory 213724 kb
Host smart-82cfa5c9-66cf-4113-b5cd-8397ad0f06b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209457638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1209457638
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1390760315
Short name T71
Test name
Test status
Simulation time 1900757678 ps
CPU time 13.78 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:50:39 PM PDT 24
Peak memory 211288 kb
Host smart-4c95d98e-0a41-4206-9d49-4c78f9f928aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390760315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1390760315
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.210599127
Short name T318
Test name
Test status
Simulation time 13156431358 ps
CPU time 105.37 seconds
Started Jun 30 04:50:19 PM PDT 24
Finished Jun 30 04:52:05 PM PDT 24
Peak memory 212160 kb
Host smart-256c7c1c-9bd6-4c19-a578-e97868cea194
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210599127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.210599127
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.296974650
Short name T54
Test name
Test status
Simulation time 347900108 ps
CPU time 9.31 seconds
Started Jun 30 04:50:26 PM PDT 24
Finished Jun 30 04:50:36 PM PDT 24
Peak memory 212016 kb
Host smart-36c2d442-88c8-41ac-a133-fd0ed94e611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296974650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.296974650
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.919348926
Short name T162
Test name
Test status
Simulation time 2167460226 ps
CPU time 8.55 seconds
Started Jun 30 04:50:19 PM PDT 24
Finished Jun 30 04:50:28 PM PDT 24
Peak memory 211348 kb
Host smart-64038f2e-15d2-48c8-9d4d-0d2fdc7de2a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919348926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.919348926
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.787367627
Short name T213
Test name
Test status
Simulation time 3380074379 ps
CPU time 33.4 seconds
Started Jun 30 04:50:18 PM PDT 24
Finished Jun 30 04:50:52 PM PDT 24
Peak memory 213844 kb
Host smart-cbcf5709-2d46-4f47-94a5-04f22e0fef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787367627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.787367627
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.540567364
Short name T164
Test name
Test status
Simulation time 439945758 ps
CPU time 25.26 seconds
Started Jun 30 04:50:18 PM PDT 24
Finished Jun 30 04:50:44 PM PDT 24
Peak memory 216140 kb
Host smart-1d7ae0ce-18b5-47c3-975c-b34b1cf4a650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540567364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.540567364
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2519108163
Short name T13
Test name
Test status
Simulation time 22584546659 ps
CPU time 665.61 seconds
Started Jun 30 04:50:23 PM PDT 24
Finished Jun 30 05:01:29 PM PDT 24
Peak memory 232632 kb
Host smart-e37e2028-48b8-4741-8e06-f6b0d320b166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519108163 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2519108163
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2622548171
Short name T70
Test name
Test status
Simulation time 212995557 ps
CPU time 6 seconds
Started Jun 30 04:50:26 PM PDT 24
Finished Jun 30 04:50:33 PM PDT 24
Peak memory 211252 kb
Host smart-7196cac1-493e-46cb-ab93-8a01c3558ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622548171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2622548171
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4126882581
Short name T175
Test name
Test status
Simulation time 66115407698 ps
CPU time 188.7 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:53:35 PM PDT 24
Peak memory 238912 kb
Host smart-44b2c671-3a66-4934-a6d9-e660e998a91d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126882581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4126882581
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1155874643
Short name T291
Test name
Test status
Simulation time 341321388 ps
CPU time 9.3 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:50:35 PM PDT 24
Peak memory 212116 kb
Host smart-d6fe81ed-299e-454e-8f9f-67947fe86a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155874643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1155874643
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3061820848
Short name T187
Test name
Test status
Simulation time 2265023939 ps
CPU time 11.49 seconds
Started Jun 30 04:50:24 PM PDT 24
Finished Jun 30 04:50:35 PM PDT 24
Peak memory 211320 kb
Host smart-35a05791-0e8f-4e16-8018-9df51a793c13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061820848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3061820848
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.191026182
Short name T217
Test name
Test status
Simulation time 3059608379 ps
CPU time 27.93 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:50:54 PM PDT 24
Peak memory 213712 kb
Host smart-12980f41-a555-4be5-a621-2fcc4a87bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191026182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.191026182
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2297897389
Short name T275
Test name
Test status
Simulation time 2853607621 ps
CPU time 19.84 seconds
Started Jun 30 04:50:27 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 213928 kb
Host smart-b51a0e23-387b-4ff4-826f-a78d3d0173fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297897389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2297897389
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.107441284
Short name T148
Test name
Test status
Simulation time 3350996948 ps
CPU time 13.96 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:50:39 PM PDT 24
Peak memory 211308 kb
Host smart-1c20d3a5-161d-4e65-835c-6ac064f74620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107441284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.107441284
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.253738529
Short name T331
Test name
Test status
Simulation time 84054553878 ps
CPU time 267.05 seconds
Started Jun 30 04:50:26 PM PDT 24
Finished Jun 30 04:54:54 PM PDT 24
Peak memory 237832 kb
Host smart-e9671cd9-7446-44f9-80be-3440f6bdf4ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253738529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.253738529
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2874919954
Short name T243
Test name
Test status
Simulation time 2418611727 ps
CPU time 23.69 seconds
Started Jun 30 04:50:26 PM PDT 24
Finished Jun 30 04:50:50 PM PDT 24
Peak memory 211976 kb
Host smart-adb12816-6909-4b3e-b9b4-250ef432165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874919954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2874919954
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2461758180
Short name T206
Test name
Test status
Simulation time 309704639 ps
CPU time 5.72 seconds
Started Jun 30 04:50:26 PM PDT 24
Finished Jun 30 04:50:32 PM PDT 24
Peak memory 211368 kb
Host smart-c2e7111f-d3d5-4c3f-b94b-a07448240420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461758180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2461758180
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.284793215
Short name T145
Test name
Test status
Simulation time 3650166725 ps
CPU time 32.53 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:50:59 PM PDT 24
Peak memory 213544 kb
Host smart-d526100f-c780-48d7-8f21-2b240936a44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284793215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.284793215
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1972998839
Short name T3
Test name
Test status
Simulation time 8951627526 ps
CPU time 81.5 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:51:47 PM PDT 24
Peak memory 216944 kb
Host smart-c16341d2-86a4-4eca-bb7c-c41a34a62e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972998839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1972998839
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1713862827
Short name T34
Test name
Test status
Simulation time 546435328 ps
CPU time 7.18 seconds
Started Jun 30 04:50:24 PM PDT 24
Finished Jun 30 04:50:32 PM PDT 24
Peak memory 211292 kb
Host smart-efef8db0-7988-4190-a2ae-0b683699d4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713862827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1713862827
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2455698928
Short name T150
Test name
Test status
Simulation time 20919163886 ps
CPU time 204.39 seconds
Started Jun 30 04:50:24 PM PDT 24
Finished Jun 30 04:53:49 PM PDT 24
Peak memory 237868 kb
Host smart-578e8847-90c5-4fb4-808c-9713f4f68cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455698928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2455698928
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3070887203
Short name T5
Test name
Test status
Simulation time 7937250602 ps
CPU time 32.37 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:50:58 PM PDT 24
Peak memory 212204 kb
Host smart-bb523314-db6b-46a2-881e-de61d5c1e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070887203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3070887203
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2972425908
Short name T282
Test name
Test status
Simulation time 1504328592 ps
CPU time 7.36 seconds
Started Jun 30 04:50:26 PM PDT 24
Finished Jun 30 04:50:34 PM PDT 24
Peak memory 211588 kb
Host smart-6abe1bf8-e809-434f-a0ed-7542c4c89e71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2972425908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2972425908
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1682019985
Short name T296
Test name
Test status
Simulation time 1296273497 ps
CPU time 19.15 seconds
Started Jun 30 04:50:24 PM PDT 24
Finished Jun 30 04:50:43 PM PDT 24
Peak memory 213648 kb
Host smart-f4b2de1d-467b-4954-8ecf-303159354799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682019985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1682019985
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4107027929
Short name T343
Test name
Test status
Simulation time 22457302163 ps
CPU time 52.03 seconds
Started Jun 30 04:50:24 PM PDT 24
Finished Jun 30 04:51:17 PM PDT 24
Peak memory 215748 kb
Host smart-dd035409-7ee2-45f1-acd1-1d9f885a1fef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107027929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4107027929
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.987989072
Short name T355
Test name
Test status
Simulation time 147534261638 ps
CPU time 1264.68 seconds
Started Jun 30 04:50:26 PM PDT 24
Finished Jun 30 05:11:31 PM PDT 24
Peak memory 235808 kb
Host smart-f2c20af4-002e-41fb-a289-cd05ccd7672c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987989072 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.987989072
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3589808158
Short name T212
Test name
Test status
Simulation time 6879861513 ps
CPU time 11.29 seconds
Started Jun 30 04:50:33 PM PDT 24
Finished Jun 30 04:50:45 PM PDT 24
Peak memory 211296 kb
Host smart-7f8f7f34-2fa6-4ed6-bc0d-b5c0c665b316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589808158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3589808158
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2011578740
Short name T344
Test name
Test status
Simulation time 29018942480 ps
CPU time 148.55 seconds
Started Jun 30 04:50:24 PM PDT 24
Finished Jun 30 04:52:54 PM PDT 24
Peak memory 212508 kb
Host smart-253e21d9-6791-4bb0-8036-c9448620d75e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011578740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2011578740
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.417244962
Short name T55
Test name
Test status
Simulation time 6831166719 ps
CPU time 29.51 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:50:55 PM PDT 24
Peak memory 212552 kb
Host smart-a7591e8d-5a50-416d-a6ed-6139353c3abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417244962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.417244962
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.487473801
Short name T208
Test name
Test status
Simulation time 3462615305 ps
CPU time 15.05 seconds
Started Jun 30 04:50:26 PM PDT 24
Finished Jun 30 04:50:41 PM PDT 24
Peak memory 211428 kb
Host smart-37d41ee0-ce7d-4a77-9171-beff56c0d53c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487473801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.487473801
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3577793105
Short name T315
Test name
Test status
Simulation time 2205837642 ps
CPU time 16.72 seconds
Started Jun 30 04:50:26 PM PDT 24
Finished Jun 30 04:50:43 PM PDT 24
Peak memory 213496 kb
Host smart-d0a1bfe5-e318-48ef-a5c0-7331659dbb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577793105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3577793105
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1033155560
Short name T311
Test name
Test status
Simulation time 380177998 ps
CPU time 21.14 seconds
Started Jun 30 04:50:25 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 214516 kb
Host smart-48690240-09be-4058-93ed-d39082aa4526
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033155560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1033155560
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1775636119
Short name T60
Test name
Test status
Simulation time 204699720491 ps
CPU time 2100.23 seconds
Started Jun 30 04:50:30 PM PDT 24
Finished Jun 30 05:25:31 PM PDT 24
Peak memory 236220 kb
Host smart-632c3c4f-2f43-4dbf-bfac-aa6f01b38255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775636119 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1775636119
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3724670902
Short name T336
Test name
Test status
Simulation time 338546893 ps
CPU time 5.79 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:50:13 PM PDT 24
Peak memory 211292 kb
Host smart-6b27d5da-7c87-4af3-a6c0-978c06a53d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724670902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3724670902
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.533326053
Short name T347
Test name
Test status
Simulation time 5538233994 ps
CPU time 98.18 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:51:44 PM PDT 24
Peak memory 237800 kb
Host smart-6a389934-cace-442c-befe-6efcc9a3751d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533326053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.533326053
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2317516426
Short name T10
Test name
Test status
Simulation time 5530813430 ps
CPU time 33.9 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:50:40 PM PDT 24
Peak memory 212228 kb
Host smart-43e4c788-a543-4830-8f6d-e2b42c6e91ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317516426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2317516426
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3899830903
Short name T131
Test name
Test status
Simulation time 1642405496 ps
CPU time 12.75 seconds
Started Jun 30 04:50:07 PM PDT 24
Finished Jun 30 04:50:21 PM PDT 24
Peak memory 211288 kb
Host smart-622f27c7-62ca-450c-a3a5-42c8b5f43dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3899830903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3899830903
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2534029786
Short name T25
Test name
Test status
Simulation time 770224275 ps
CPU time 51.32 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:58 PM PDT 24
Peak memory 236776 kb
Host smart-54c35ed1-baa5-4c1b-8a12-7a988a503026
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534029786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2534029786
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.29671627
Short name T259
Test name
Test status
Simulation time 4587255589 ps
CPU time 27.51 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:50:31 PM PDT 24
Peak memory 213520 kb
Host smart-47e4fa01-4fe5-4f1f-af1f-3d238db55520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29671627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.29671627
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3727514046
Short name T171
Test name
Test status
Simulation time 4019886412 ps
CPU time 36.59 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:50:41 PM PDT 24
Peak memory 216276 kb
Host smart-8c09c1bb-fb32-46bc-a32a-8b774ea2f7df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727514046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3727514046
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.146372883
Short name T61
Test name
Test status
Simulation time 86473768738 ps
CPU time 787.43 seconds
Started Jun 30 04:50:07 PM PDT 24
Finished Jun 30 05:03:15 PM PDT 24
Peak memory 235712 kb
Host smart-21297de9-0f51-43d8-acf8-ac64628d36f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146372883 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.146372883
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1945682602
Short name T56
Test name
Test status
Simulation time 628617589 ps
CPU time 8.32 seconds
Started Jun 30 04:50:34 PM PDT 24
Finished Jun 30 04:50:43 PM PDT 24
Peak memory 211248 kb
Host smart-b6cd65db-7a05-4060-84b4-3b6b00630346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945682602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1945682602
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.729927625
Short name T118
Test name
Test status
Simulation time 99256895269 ps
CPU time 271.13 seconds
Started Jun 30 04:50:31 PM PDT 24
Finished Jun 30 04:55:03 PM PDT 24
Peak memory 212588 kb
Host smart-b657ccee-6f18-4add-865b-2c313eba3094
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729927625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.729927625
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2944345791
Short name T351
Test name
Test status
Simulation time 19005903805 ps
CPU time 17.14 seconds
Started Jun 30 04:50:35 PM PDT 24
Finished Jun 30 04:50:53 PM PDT 24
Peak memory 212244 kb
Host smart-8183f355-9826-4646-a809-ed4a2c53317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944345791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2944345791
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1990580813
Short name T120
Test name
Test status
Simulation time 98093201 ps
CPU time 5.69 seconds
Started Jun 30 04:50:30 PM PDT 24
Finished Jun 30 04:50:37 PM PDT 24
Peak memory 211368 kb
Host smart-25544dae-d579-40f5-b22e-e54df6257740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990580813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1990580813
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1050071678
Short name T178
Test name
Test status
Simulation time 12009104640 ps
CPU time 25.48 seconds
Started Jun 30 04:50:31 PM PDT 24
Finished Jun 30 04:50:57 PM PDT 24
Peak memory 214152 kb
Host smart-5dad0883-a566-4c59-a818-f3025e67af0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050071678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1050071678
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3751407689
Short name T190
Test name
Test status
Simulation time 382022349 ps
CPU time 16.22 seconds
Started Jun 30 04:50:33 PM PDT 24
Finished Jun 30 04:50:50 PM PDT 24
Peak memory 213392 kb
Host smart-ec5e4b5f-5889-40a3-821a-87e8d0b52dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751407689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3751407689
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1928988282
Short name T321
Test name
Test status
Simulation time 254636470 ps
CPU time 6.16 seconds
Started Jun 30 04:50:31 PM PDT 24
Finished Jun 30 04:50:38 PM PDT 24
Peak memory 211252 kb
Host smart-3c6e494c-37e8-4d4a-aa80-961a8a5cb4c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928988282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1928988282
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3320952423
Short name T271
Test name
Test status
Simulation time 93606221711 ps
CPU time 248.06 seconds
Started Jun 30 04:50:31 PM PDT 24
Finished Jun 30 04:54:40 PM PDT 24
Peak memory 237444 kb
Host smart-cccfd5d2-46b4-402d-a725-c70a18f7cbe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320952423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3320952423
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1304494541
Short name T227
Test name
Test status
Simulation time 7866487685 ps
CPU time 32.02 seconds
Started Jun 30 04:50:34 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 212296 kb
Host smart-dc26de03-9d66-46ed-8c17-e0481e2220c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304494541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1304494541
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3324392182
Short name T127
Test name
Test status
Simulation time 13178649375 ps
CPU time 12.98 seconds
Started Jun 30 04:50:33 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 211392 kb
Host smart-6056978e-cc2b-4241-b1fe-987f9aeedbb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324392182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3324392182
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3978729190
Short name T360
Test name
Test status
Simulation time 16042806142 ps
CPU time 32.69 seconds
Started Jun 30 04:50:32 PM PDT 24
Finished Jun 30 04:51:05 PM PDT 24
Peak memory 214260 kb
Host smart-38254ecc-9514-44d3-a5ee-dba42a03fcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978729190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3978729190
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.4124071394
Short name T200
Test name
Test status
Simulation time 1388674165 ps
CPU time 15.21 seconds
Started Jun 30 04:50:34 PM PDT 24
Finished Jun 30 04:50:50 PM PDT 24
Peak memory 214052 kb
Host smart-69ae74fe-b189-43bf-83af-626eab4505a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124071394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.4124071394
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.520547856
Short name T226
Test name
Test status
Simulation time 462135649 ps
CPU time 4.4 seconds
Started Jun 30 04:50:35 PM PDT 24
Finished Jun 30 04:50:40 PM PDT 24
Peak memory 211276 kb
Host smart-9d995259-6164-4f75-b6d7-c99721bf6c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520547856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.520547856
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3757312570
Short name T33
Test name
Test status
Simulation time 20223014825 ps
CPU time 135.79 seconds
Started Jun 30 04:50:32 PM PDT 24
Finished Jun 30 04:52:48 PM PDT 24
Peak memory 225684 kb
Host smart-7c6eeb71-f4c8-4946-b93a-a2f466ac1543
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757312570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3757312570
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.400422537
Short name T124
Test name
Test status
Simulation time 1638012984 ps
CPU time 19.38 seconds
Started Jun 30 04:50:35 PM PDT 24
Finished Jun 30 04:50:55 PM PDT 24
Peak memory 212960 kb
Host smart-96907663-209f-4741-89d7-4d6dc4377059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400422537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.400422537
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.466518745
Short name T11
Test name
Test status
Simulation time 1122689870 ps
CPU time 11.31 seconds
Started Jun 30 04:50:35 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 211272 kb
Host smart-5bb3734b-0651-474b-9de4-9f6c20828be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466518745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.466518745
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1516210752
Short name T151
Test name
Test status
Simulation time 22179815226 ps
CPU time 23.73 seconds
Started Jun 30 04:50:34 PM PDT 24
Finished Jun 30 04:50:58 PM PDT 24
Peak memory 213744 kb
Host smart-3bc7aa48-6c3a-4cbd-89e3-d0e3371900fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516210752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1516210752
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3295208075
Short name T317
Test name
Test status
Simulation time 10015860399 ps
CPU time 33.65 seconds
Started Jun 30 04:50:34 PM PDT 24
Finished Jun 30 04:51:08 PM PDT 24
Peak memory 214464 kb
Host smart-590a1798-74dc-4bc1-8a07-23d08939ba44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295208075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3295208075
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2966847969
Short name T176
Test name
Test status
Simulation time 221347348 ps
CPU time 5.78 seconds
Started Jun 30 04:50:32 PM PDT 24
Finished Jun 30 04:50:39 PM PDT 24
Peak memory 211244 kb
Host smart-d8c175ce-0a9f-42e7-81fe-ac2eb06bc4dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966847969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2966847969
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1221991676
Short name T44
Test name
Test status
Simulation time 30725379710 ps
CPU time 369.7 seconds
Started Jun 30 04:50:34 PM PDT 24
Finished Jun 30 04:56:44 PM PDT 24
Peak memory 238064 kb
Host smart-6841bbee-64cd-496a-a8a4-d283e0b47b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221991676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1221991676
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.439596920
Short name T37
Test name
Test status
Simulation time 335139828 ps
CPU time 9.33 seconds
Started Jun 30 04:50:33 PM PDT 24
Finished Jun 30 04:50:43 PM PDT 24
Peak memory 211880 kb
Host smart-08480cdc-d686-4a0a-a7de-de335393485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439596920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.439596920
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3599597495
Short name T197
Test name
Test status
Simulation time 1063855826 ps
CPU time 8.06 seconds
Started Jun 30 04:50:35 PM PDT 24
Finished Jun 30 04:50:44 PM PDT 24
Peak memory 211336 kb
Host smart-b75785ff-fdf0-4154-bac0-0d5e114d86d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599597495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3599597495
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3715644215
Short name T305
Test name
Test status
Simulation time 7361393664 ps
CPU time 24.61 seconds
Started Jun 30 04:50:31 PM PDT 24
Finished Jun 30 04:50:56 PM PDT 24
Peak memory 214920 kb
Host smart-6bb00bf6-1deb-4600-80c7-dc5af44023b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715644215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3715644215
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.875613553
Short name T228
Test name
Test status
Simulation time 596174052 ps
CPU time 16.7 seconds
Started Jun 30 04:50:35 PM PDT 24
Finished Jun 30 04:50:52 PM PDT 24
Peak memory 214608 kb
Host smart-5f9bb2b5-be3e-4517-9ae6-87d7a08b501c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875613553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.875613553
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3372304392
Short name T353
Test name
Test status
Simulation time 89746305 ps
CPU time 4.24 seconds
Started Jun 30 04:50:38 PM PDT 24
Finished Jun 30 04:50:43 PM PDT 24
Peak memory 211248 kb
Host smart-0ff99d16-2ebc-4b0c-9e63-58a04b638e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372304392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3372304392
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3615619322
Short name T286
Test name
Test status
Simulation time 3909176475 ps
CPU time 126.24 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:52:46 PM PDT 24
Peak memory 237772 kb
Host smart-ca86f61b-7251-47f9-a83c-5ecf15dd46f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615619322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3615619322
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2955413773
Short name T320
Test name
Test status
Simulation time 477722966 ps
CPU time 9.69 seconds
Started Jun 30 04:50:37 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 212184 kb
Host smart-2a6e1439-2f82-4a74-9a50-7f05d8c14536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955413773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2955413773
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1970638129
Short name T18
Test name
Test status
Simulation time 2436676515 ps
CPU time 12.75 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:50:53 PM PDT 24
Peak memory 211324 kb
Host smart-6ed008bf-8cc6-4913-bc84-d0b4f7bbf357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970638129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1970638129
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.366458275
Short name T172
Test name
Test status
Simulation time 12784022654 ps
CPU time 36.19 seconds
Started Jun 30 04:50:33 PM PDT 24
Finished Jun 30 04:51:09 PM PDT 24
Peak memory 213972 kb
Host smart-17c7a68b-a427-4f22-8889-25890d962eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366458275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.366458275
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3711361413
Short name T237
Test name
Test status
Simulation time 509783439 ps
CPU time 11.8 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:50:52 PM PDT 24
Peak memory 214796 kb
Host smart-107b3378-2491-4ca3-9b15-71774b6cdd1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711361413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3711361413
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3397732837
Short name T264
Test name
Test status
Simulation time 6079713251 ps
CPU time 12.99 seconds
Started Jun 30 04:50:38 PM PDT 24
Finished Jun 30 04:50:51 PM PDT 24
Peak memory 211364 kb
Host smart-26a86fbb-fba9-45fc-bdf1-8c062151e959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397732837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3397732837
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.293175268
Short name T270
Test name
Test status
Simulation time 2572448696 ps
CPU time 24.62 seconds
Started Jun 30 04:50:38 PM PDT 24
Finished Jun 30 04:51:04 PM PDT 24
Peak memory 211948 kb
Host smart-ac126b93-eba9-4251-ba80-080c3ec8a3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293175268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.293175268
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2355469251
Short name T50
Test name
Test status
Simulation time 2084251323 ps
CPU time 8.39 seconds
Started Jun 30 04:50:38 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 211064 kb
Host smart-438c20dd-1a46-4fa8-970a-a0e99bbc38ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355469251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2355469251
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3040622973
Short name T220
Test name
Test status
Simulation time 2490853680 ps
CPU time 27.25 seconds
Started Jun 30 04:50:36 PM PDT 24
Finished Jun 30 04:51:04 PM PDT 24
Peak memory 212188 kb
Host smart-8150bf1e-ddaf-443b-817e-9379c29bccff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040622973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3040622973
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2798791161
Short name T307
Test name
Test status
Simulation time 10918752356 ps
CPU time 20.26 seconds
Started Jun 30 04:50:38 PM PDT 24
Finished Jun 30 04:50:59 PM PDT 24
Peak memory 212180 kb
Host smart-785e9608-c339-4c97-8f2b-ffe9b5f40e40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798791161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2798791161
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3888456946
Short name T146
Test name
Test status
Simulation time 86455655 ps
CPU time 4.32 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:50:44 PM PDT 24
Peak memory 211220 kb
Host smart-9fb115e9-4316-429a-b2ac-16418df76be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888456946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3888456946
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3869367290
Short name T184
Test name
Test status
Simulation time 26260324400 ps
CPU time 143.73 seconds
Started Jun 30 04:50:40 PM PDT 24
Finished Jun 30 04:53:04 PM PDT 24
Peak memory 212628 kb
Host smart-ac90cfca-8291-462e-b32e-26f560af5bd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869367290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3869367290
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.849873241
Short name T361
Test name
Test status
Simulation time 6536935756 ps
CPU time 26.79 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 212596 kb
Host smart-43e65145-cf6c-49bd-9287-49593ed767bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849873241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.849873241
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3313489023
Short name T267
Test name
Test status
Simulation time 2341977000 ps
CPU time 7.4 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:50:47 PM PDT 24
Peak memory 211416 kb
Host smart-3c4b29d8-a2f8-4928-a0a7-9ab704dbc707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3313489023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3313489023
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.691999951
Short name T36
Test name
Test status
Simulation time 3633233844 ps
CPU time 33.75 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:51:14 PM PDT 24
Peak memory 213420 kb
Host smart-2b6685da-32af-4d9c-a671-1a03cab46057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691999951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.691999951
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.862732693
Short name T196
Test name
Test status
Simulation time 11331553003 ps
CPU time 41.77 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:51:22 PM PDT 24
Peak memory 216628 kb
Host smart-90e8d907-6a3e-4e26-8435-2c297adfcf93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862732693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.862732693
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.4071928685
Short name T59
Test name
Test status
Simulation time 42949161284 ps
CPU time 7073.26 seconds
Started Jun 30 04:50:40 PM PDT 24
Finished Jun 30 06:48:35 PM PDT 24
Peak memory 228044 kb
Host smart-9c48efc2-91eb-4539-8c47-f33fc134e5f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071928685 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.4071928685
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2038189478
Short name T328
Test name
Test status
Simulation time 2685393500 ps
CPU time 13.84 seconds
Started Jun 30 04:50:38 PM PDT 24
Finished Jun 30 04:50:53 PM PDT 24
Peak memory 211316 kb
Host smart-46450a48-d4e2-4973-9633-17e9f8bb6ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038189478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2038189478
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.674593806
Short name T210
Test name
Test status
Simulation time 147164850620 ps
CPU time 378.81 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:56:59 PM PDT 24
Peak memory 237392 kb
Host smart-8931f6be-1de0-4876-b92b-f8369f2554e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674593806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.674593806
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1980880724
Short name T338
Test name
Test status
Simulation time 6009122637 ps
CPU time 26.25 seconds
Started Jun 30 04:50:38 PM PDT 24
Finished Jun 30 04:51:05 PM PDT 24
Peak memory 212172 kb
Host smart-9f06557a-6654-4fb7-b2e0-04caf9631616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980880724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1980880724
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3888257798
Short name T19
Test name
Test status
Simulation time 1818216142 ps
CPU time 10.85 seconds
Started Jun 30 04:50:40 PM PDT 24
Finished Jun 30 04:50:52 PM PDT 24
Peak memory 211340 kb
Host smart-ef9738f8-e6e5-4056-a85f-263e46ad649c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888257798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3888257798
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2452447132
Short name T2
Test name
Test status
Simulation time 1887470375 ps
CPU time 23.67 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:51:03 PM PDT 24
Peak memory 213108 kb
Host smart-a975e420-9dc8-4365-bc80-f795a14283ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452447132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2452447132
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3423669521
Short name T192
Test name
Test status
Simulation time 3980568667 ps
CPU time 31.77 seconds
Started Jun 30 04:50:39 PM PDT 24
Finished Jun 30 04:51:12 PM PDT 24
Peak memory 214748 kb
Host smart-bc07daf0-41fb-4175-946a-3c485761ff67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423669521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3423669521
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2899675753
Short name T251
Test name
Test status
Simulation time 421211500 ps
CPU time 7.38 seconds
Started Jun 30 04:50:46 PM PDT 24
Finished Jun 30 04:50:55 PM PDT 24
Peak memory 211312 kb
Host smart-6bed2c36-3ef4-4313-b8dd-bb20f32c4cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899675753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2899675753
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4253858485
Short name T51
Test name
Test status
Simulation time 14645719933 ps
CPU time 175.75 seconds
Started Jun 30 04:50:45 PM PDT 24
Finished Jun 30 04:53:42 PM PDT 24
Peak memory 233772 kb
Host smart-3af6c35c-c767-46e1-804d-5ca92d19cd4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253858485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4253858485
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1901016486
Short name T174
Test name
Test status
Simulation time 1700368096 ps
CPU time 15.21 seconds
Started Jun 30 04:50:46 PM PDT 24
Finished Jun 30 04:51:02 PM PDT 24
Peak memory 211336 kb
Host smart-f2d8c9d7-7917-4e3d-995d-a8c88e833fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901016486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1901016486
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1469852663
Short name T263
Test name
Test status
Simulation time 57556725577 ps
CPU time 40.45 seconds
Started Jun 30 04:50:45 PM PDT 24
Finished Jun 30 04:51:26 PM PDT 24
Peak memory 213848 kb
Host smart-aeaa9da8-906c-41b1-9784-17d8e222207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469852663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1469852663
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1415535310
Short name T335
Test name
Test status
Simulation time 1397150034 ps
CPU time 12.28 seconds
Started Jun 30 04:50:46 PM PDT 24
Finished Jun 30 04:50:59 PM PDT 24
Peak memory 211208 kb
Host smart-0cf8610e-988c-42c4-b45e-e43daa58fd23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415535310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1415535310
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3451540395
Short name T27
Test name
Test status
Simulation time 16275459730 ps
CPU time 9.49 seconds
Started Jun 30 04:50:45 PM PDT 24
Finished Jun 30 04:50:55 PM PDT 24
Peak memory 211380 kb
Host smart-72ecb20b-a67b-48d5-a960-f1290a552a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451540395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3451540395
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3457551745
Short name T341
Test name
Test status
Simulation time 24382139815 ps
CPU time 211.5 seconds
Started Jun 30 04:50:47 PM PDT 24
Finished Jun 30 04:54:19 PM PDT 24
Peak memory 212696 kb
Host smart-dbbf4015-c8fb-4556-a673-18b5825623f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457551745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3457551745
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3633909666
Short name T238
Test name
Test status
Simulation time 10900827425 ps
CPU time 19.56 seconds
Started Jun 30 04:50:45 PM PDT 24
Finished Jun 30 04:51:05 PM PDT 24
Peak memory 212264 kb
Host smart-be56ee9a-2672-4762-a6ca-d5d8459b7e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633909666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3633909666
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1929468252
Short name T300
Test name
Test status
Simulation time 100059715 ps
CPU time 5.56 seconds
Started Jun 30 04:50:45 PM PDT 24
Finished Jun 30 04:50:51 PM PDT 24
Peak memory 211336 kb
Host smart-183020a4-9b89-40ea-8745-b4376e1f1b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929468252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1929468252
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.540268212
Short name T298
Test name
Test status
Simulation time 188946291 ps
CPU time 10.44 seconds
Started Jun 30 04:50:45 PM PDT 24
Finished Jun 30 04:50:56 PM PDT 24
Peak memory 213548 kb
Host smart-e2827626-a88f-4376-bce6-c30b165edf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540268212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.540268212
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1999846709
Short name T329
Test name
Test status
Simulation time 15848236138 ps
CPU time 39.15 seconds
Started Jun 30 04:50:44 PM PDT 24
Finished Jun 30 04:51:23 PM PDT 24
Peak memory 215052 kb
Host smart-c68127e7-37fd-4768-ab94-95fd2bc6955c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999846709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1999846709
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2681233573
Short name T350
Test name
Test status
Simulation time 1650281055 ps
CPU time 14.04 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:50:21 PM PDT 24
Peak memory 211252 kb
Host smart-482eeaeb-d7ab-4e90-8be5-f5cd60e2bc16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681233573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2681233573
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1100048979
Short name T222
Test name
Test status
Simulation time 187177442590 ps
CPU time 199.39 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:53:25 PM PDT 24
Peak memory 237756 kb
Host smart-d1c564e8-347f-4a19-9997-29e0a7127d5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100048979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1100048979
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1787530799
Short name T133
Test name
Test status
Simulation time 2760740280 ps
CPU time 25.81 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:32 PM PDT 24
Peak memory 211940 kb
Host smart-c8aee02d-11e3-413f-944b-eb9bd34f8317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787530799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1787530799
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1021209330
Short name T104
Test name
Test status
Simulation time 4324125405 ps
CPU time 10.45 seconds
Started Jun 30 04:50:07 PM PDT 24
Finished Jun 30 04:50:19 PM PDT 24
Peak memory 211348 kb
Host smart-ecf77ce1-cc23-41e7-9f61-d1337f16d1ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021209330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1021209330
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.518367272
Short name T26
Test name
Test status
Simulation time 2342948936 ps
CPU time 65.26 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:51:09 PM PDT 24
Peak memory 233616 kb
Host smart-9dc9ed4d-e27a-45dd-9369-22b1e9325c55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518367272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.518367272
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1524745820
Short name T309
Test name
Test status
Simulation time 13427496457 ps
CPU time 25.07 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:50:31 PM PDT 24
Peak memory 213908 kb
Host smart-24bb4429-e240-4172-b484-ec6be90da406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524745820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1524745820
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3599381641
Short name T334
Test name
Test status
Simulation time 68411690531 ps
CPU time 134.02 seconds
Started Jun 30 04:50:05 PM PDT 24
Finished Jun 30 04:52:20 PM PDT 24
Peak memory 219348 kb
Host smart-a527bc9c-59d1-41a6-9034-bec7479f798d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599381641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3599381641
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3487104313
Short name T265
Test name
Test status
Simulation time 488666665 ps
CPU time 4.25 seconds
Started Jun 30 04:50:48 PM PDT 24
Finished Jun 30 04:50:52 PM PDT 24
Peak memory 211264 kb
Host smart-62ba0e92-2e00-4334-b8ea-da8d837562f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487104313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3487104313
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2613659864
Short name T293
Test name
Test status
Simulation time 2758755018 ps
CPU time 92.1 seconds
Started Jun 30 04:50:47 PM PDT 24
Finished Jun 30 04:52:20 PM PDT 24
Peak memory 234840 kb
Host smart-4723a257-3f53-4740-bc41-473844bbf329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613659864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2613659864
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2047006607
Short name T144
Test name
Test status
Simulation time 334240321 ps
CPU time 9.41 seconds
Started Jun 30 04:50:47 PM PDT 24
Finished Jun 30 04:50:57 PM PDT 24
Peak memory 211872 kb
Host smart-471bc93e-65df-43b6-a5bf-934c5bf618a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047006607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2047006607
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2782471034
Short name T224
Test name
Test status
Simulation time 2234908853 ps
CPU time 11.44 seconds
Started Jun 30 04:50:47 PM PDT 24
Finished Jun 30 04:50:59 PM PDT 24
Peak memory 211352 kb
Host smart-c3f081fd-1b89-40ce-bfa9-1451cea4613a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782471034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2782471034
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2887981137
Short name T356
Test name
Test status
Simulation time 5599003601 ps
CPU time 26.97 seconds
Started Jun 30 04:50:46 PM PDT 24
Finished Jun 30 04:51:14 PM PDT 24
Peak memory 212944 kb
Host smart-a17ec69b-c223-45ff-8236-2492fbad4073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887981137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2887981137
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.309106706
Short name T349
Test name
Test status
Simulation time 1129622401 ps
CPU time 13.96 seconds
Started Jun 30 04:50:45 PM PDT 24
Finished Jun 30 04:51:00 PM PDT 24
Peak memory 211316 kb
Host smart-bc525d7b-64e6-4bba-afef-9a9b940f7b24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309106706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.309106706
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3549387164
Short name T258
Test name
Test status
Simulation time 66179126661 ps
CPU time 813.63 seconds
Started Jun 30 04:50:47 PM PDT 24
Finished Jun 30 05:04:21 PM PDT 24
Peak memory 227628 kb
Host smart-c35a0761-560c-4758-b2b1-3ea645c6abc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549387164 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3549387164
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.845506073
Short name T147
Test name
Test status
Simulation time 622725701 ps
CPU time 8 seconds
Started Jun 30 04:50:56 PM PDT 24
Finished Jun 30 04:51:04 PM PDT 24
Peak memory 211248 kb
Host smart-014dac91-3e6b-45ae-b155-5c2c682212bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845506073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.845506073
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.787571219
Short name T198
Test name
Test status
Simulation time 6963922772 ps
CPU time 122.42 seconds
Started Jun 30 04:50:46 PM PDT 24
Finished Jun 30 04:52:49 PM PDT 24
Peak memory 235040 kb
Host smart-39ed9832-97f4-429a-a595-1ad5509ef846
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787571219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.787571219
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1593707051
Short name T189
Test name
Test status
Simulation time 3542229599 ps
CPU time 30.72 seconds
Started Jun 30 04:50:50 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 211924 kb
Host smart-0e6a126a-4d1e-48d3-bd13-0e28b8e0534b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593707051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1593707051
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3693249117
Short name T161
Test name
Test status
Simulation time 6615236464 ps
CPU time 14.92 seconds
Started Jun 30 04:50:45 PM PDT 24
Finished Jun 30 04:51:01 PM PDT 24
Peak memory 211432 kb
Host smart-01f64ab6-0a62-49a3-abb2-d8df4f3744c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693249117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3693249117
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2711870730
Short name T140
Test name
Test status
Simulation time 1810131902 ps
CPU time 20.99 seconds
Started Jun 30 04:50:46 PM PDT 24
Finished Jun 30 04:51:08 PM PDT 24
Peak memory 213412 kb
Host smart-2423ddb6-93d5-498a-afde-633eaf7c3599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711870730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2711870730
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1579323348
Short name T139
Test name
Test status
Simulation time 392062877 ps
CPU time 9.88 seconds
Started Jun 30 04:50:45 PM PDT 24
Finished Jun 30 04:50:55 PM PDT 24
Peak memory 211140 kb
Host smart-b41645de-d546-405a-a3af-842a5f00ad77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579323348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1579323348
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1062915137
Short name T316
Test name
Test status
Simulation time 87500852 ps
CPU time 4.39 seconds
Started Jun 30 04:50:57 PM PDT 24
Finished Jun 30 04:51:02 PM PDT 24
Peak memory 211236 kb
Host smart-f78180e7-c2d1-45f3-8c2b-13bc5f7a7b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062915137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1062915137
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1731663476
Short name T232
Test name
Test status
Simulation time 147856964852 ps
CPU time 334.02 seconds
Started Jun 30 04:50:56 PM PDT 24
Finished Jun 30 04:56:31 PM PDT 24
Peak memory 228160 kb
Host smart-8ea45f7e-4108-4a76-9add-77ff9a65e577
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731663476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1731663476
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3872977580
Short name T295
Test name
Test status
Simulation time 16708787833 ps
CPU time 33.88 seconds
Started Jun 30 04:50:55 PM PDT 24
Finished Jun 30 04:51:29 PM PDT 24
Peak memory 212156 kb
Host smart-e7fd5da1-1793-4338-999d-ad5c6b66240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872977580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3872977580
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1468029356
Short name T364
Test name
Test status
Simulation time 540540264 ps
CPU time 5.32 seconds
Started Jun 30 04:50:55 PM PDT 24
Finished Jun 30 04:51:01 PM PDT 24
Peak memory 211364 kb
Host smart-0e76bdc9-7e78-45ae-a88e-1a5aaa8d8ce5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468029356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1468029356
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3202201129
Short name T337
Test name
Test status
Simulation time 37170049672 ps
CPU time 27.1 seconds
Started Jun 30 04:50:56 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 213604 kb
Host smart-0c699c5b-40eb-4917-9e64-2efe73c0d788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202201129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3202201129
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3737223642
Short name T292
Test name
Test status
Simulation time 2712882652 ps
CPU time 10 seconds
Started Jun 30 04:50:55 PM PDT 24
Finished Jun 30 04:51:06 PM PDT 24
Peak memory 211368 kb
Host smart-34f8ea74-e881-4d94-ba7e-b8b95cb163b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737223642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3737223642
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2322203273
Short name T202
Test name
Test status
Simulation time 1210716656 ps
CPU time 6.24 seconds
Started Jun 30 04:50:55 PM PDT 24
Finished Jun 30 04:51:02 PM PDT 24
Peak memory 211236 kb
Host smart-cea36875-00b4-4dc5-935a-5db62f6ec125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322203273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2322203273
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2191862857
Short name T43
Test name
Test status
Simulation time 5683773603 ps
CPU time 85.95 seconds
Started Jun 30 04:50:55 PM PDT 24
Finished Jun 30 04:52:21 PM PDT 24
Peak memory 237640 kb
Host smart-ede763ad-d803-4d6e-b9f7-ff705bcff651
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191862857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2191862857
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.472214391
Short name T261
Test name
Test status
Simulation time 4003269303 ps
CPU time 33.22 seconds
Started Jun 30 04:50:54 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 211976 kb
Host smart-869c45d4-fd25-41a4-aaf2-3a6b579b337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472214391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.472214391
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2486535142
Short name T324
Test name
Test status
Simulation time 3792654192 ps
CPU time 16.1 seconds
Started Jun 30 04:50:55 PM PDT 24
Finished Jun 30 04:51:12 PM PDT 24
Peak memory 211376 kb
Host smart-ecc77a34-f686-41eb-9ca0-b07d983a0145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486535142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2486535142
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.261566228
Short name T134
Test name
Test status
Simulation time 8772886342 ps
CPU time 34.42 seconds
Started Jun 30 04:50:56 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 213872 kb
Host smart-b85ba188-85bd-4a4b-9cc6-95111643519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261566228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.261566228
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1653122959
Short name T276
Test name
Test status
Simulation time 14616689414 ps
CPU time 42.22 seconds
Started Jun 30 04:50:55 PM PDT 24
Finished Jun 30 04:51:38 PM PDT 24
Peak memory 219372 kb
Host smart-0ca45f26-a1c9-4c90-98f3-051b86e5ca71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653122959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1653122959
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2569287933
Short name T323
Test name
Test status
Simulation time 1185138096 ps
CPU time 4.3 seconds
Started Jun 30 04:50:59 PM PDT 24
Finished Jun 30 04:51:04 PM PDT 24
Peak memory 211324 kb
Host smart-42fa9999-d8c6-4d31-b22f-a16f72451753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569287933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2569287933
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3516373129
Short name T284
Test name
Test status
Simulation time 5202159905 ps
CPU time 88.92 seconds
Started Jun 30 04:50:54 PM PDT 24
Finished Jun 30 04:52:23 PM PDT 24
Peak memory 237328 kb
Host smart-b5e36ab5-5764-46f2-a512-9d6bf46df8c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516373129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3516373129
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.864042805
Short name T339
Test name
Test status
Simulation time 37566872500 ps
CPU time 27.06 seconds
Started Jun 30 04:50:56 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 212092 kb
Host smart-aed74e30-ec55-4393-a58c-13bbe1a768a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864042805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.864042805
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4182108971
Short name T239
Test name
Test status
Simulation time 1339050980 ps
CPU time 12.77 seconds
Started Jun 30 04:50:54 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 211300 kb
Host smart-f546971a-d647-4fc3-b917-2738affb0575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182108971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4182108971
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1182398983
Short name T218
Test name
Test status
Simulation time 8218580865 ps
CPU time 33.79 seconds
Started Jun 30 04:50:55 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 214120 kb
Host smart-d5a0cb3c-0a0a-4f25-941a-192cb3118ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182398983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1182398983
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2736453403
Short name T216
Test name
Test status
Simulation time 2237005029 ps
CPU time 23.68 seconds
Started Jun 30 04:50:54 PM PDT 24
Finished Jun 30 04:51:18 PM PDT 24
Peak memory 214824 kb
Host smart-012f5e66-5256-4266-bcf9-8f9769a5c660
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736453403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2736453403
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2038122697
Short name T294
Test name
Test status
Simulation time 688820650 ps
CPU time 5.5 seconds
Started Jun 30 04:51:02 PM PDT 24
Finished Jun 30 04:51:08 PM PDT 24
Peak memory 211316 kb
Host smart-e8905916-76f4-45e1-afec-11931f4ecbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038122697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2038122697
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1279157070
Short name T325
Test name
Test status
Simulation time 48761456874 ps
CPU time 270.35 seconds
Started Jun 30 04:51:00 PM PDT 24
Finished Jun 30 04:55:30 PM PDT 24
Peak memory 234888 kb
Host smart-ac6b1e72-e5fc-4794-9f91-7323c6a73c29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279157070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1279157070
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3583614743
Short name T158
Test name
Test status
Simulation time 22915634141 ps
CPU time 28.15 seconds
Started Jun 30 04:51:01 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 212236 kb
Host smart-f4a39091-8bb4-4b6f-8291-e3ed676adeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583614743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3583614743
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3126836813
Short name T194
Test name
Test status
Simulation time 561553559 ps
CPU time 8.53 seconds
Started Jun 30 04:50:58 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 211300 kb
Host smart-adef9cd3-84cf-4eea-a58b-4e5f2704ffbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126836813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3126836813
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.937393456
Short name T256
Test name
Test status
Simulation time 5543800992 ps
CPU time 21.07 seconds
Started Jun 30 04:50:58 PM PDT 24
Finished Jun 30 04:51:20 PM PDT 24
Peak memory 213968 kb
Host smart-087ce775-b71c-4a0f-9c4c-ee95fc1e3914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937393456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.937393456
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3224872041
Short name T358
Test name
Test status
Simulation time 4848682206 ps
CPU time 28.76 seconds
Started Jun 30 04:51:00 PM PDT 24
Finished Jun 30 04:51:29 PM PDT 24
Peak memory 216980 kb
Host smart-5f7d7418-3c17-4b84-80af-da5bdecdb8df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224872041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3224872041
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3861394076
Short name T167
Test name
Test status
Simulation time 3431089610 ps
CPU time 9.72 seconds
Started Jun 30 04:50:57 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 211364 kb
Host smart-3fdfc923-4df5-4556-9616-f4dca752715c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861394076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3861394076
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2893801032
Short name T306
Test name
Test status
Simulation time 44083834001 ps
CPU time 132.87 seconds
Started Jun 30 04:50:57 PM PDT 24
Finished Jun 30 04:53:10 PM PDT 24
Peak memory 237840 kb
Host smart-18c55779-b10d-494b-a419-0063ee5958d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893801032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2893801032
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.410095038
Short name T160
Test name
Test status
Simulation time 4719959225 ps
CPU time 24.14 seconds
Started Jun 30 04:50:58 PM PDT 24
Finished Jun 30 04:51:23 PM PDT 24
Peak memory 212484 kb
Host smart-de0647bb-ff36-4555-ba41-01390d0c6e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410095038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.410095038
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2424592165
Short name T244
Test name
Test status
Simulation time 547608641 ps
CPU time 9.26 seconds
Started Jun 30 04:50:59 PM PDT 24
Finished Jun 30 04:51:09 PM PDT 24
Peak memory 211368 kb
Host smart-efe46ccc-ed8f-44f1-8843-4a9760b14617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424592165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2424592165
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.623091495
Short name T123
Test name
Test status
Simulation time 354294908 ps
CPU time 9.81 seconds
Started Jun 30 04:51:01 PM PDT 24
Finished Jun 30 04:51:12 PM PDT 24
Peak memory 212524 kb
Host smart-6045cac1-4921-40a7-9047-807922a0dd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623091495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.623091495
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.257781189
Short name T340
Test name
Test status
Simulation time 1427203911 ps
CPU time 20.17 seconds
Started Jun 30 04:51:00 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 214400 kb
Host smart-a329032d-8640-40ac-9d46-01164b8a6e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257781189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.257781189
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1087530921
Short name T15
Test name
Test status
Simulation time 58847488482 ps
CPU time 2110.28 seconds
Started Jun 30 04:50:59 PM PDT 24
Finished Jun 30 05:26:10 PM PDT 24
Peak memory 237424 kb
Host smart-09e4c501-1e89-44f8-8cf2-2ffe07a61e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087530921 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1087530921
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4161548804
Short name T260
Test name
Test status
Simulation time 2067904219 ps
CPU time 16.08 seconds
Started Jun 30 04:50:59 PM PDT 24
Finished Jun 30 04:51:16 PM PDT 24
Peak memory 211292 kb
Host smart-5e9c5b00-6e4e-4689-b9ee-4ec7da055dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161548804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4161548804
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1441640598
Short name T266
Test name
Test status
Simulation time 144464210486 ps
CPU time 175.87 seconds
Started Jun 30 04:51:03 PM PDT 24
Finished Jun 30 04:54:00 PM PDT 24
Peak memory 236744 kb
Host smart-b2ca74c9-3c4d-4cd6-bf7f-46200acd793d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441640598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1441640598
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3552406425
Short name T136
Test name
Test status
Simulation time 253843025 ps
CPU time 9.63 seconds
Started Jun 30 04:51:00 PM PDT 24
Finished Jun 30 04:51:10 PM PDT 24
Peak memory 211912 kb
Host smart-fc9cf6cd-7b14-45b7-901a-0a3f71944f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552406425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3552406425
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4257820302
Short name T47
Test name
Test status
Simulation time 1356674660 ps
CPU time 7.69 seconds
Started Jun 30 04:51:03 PM PDT 24
Finished Jun 30 04:51:11 PM PDT 24
Peak memory 211372 kb
Host smart-7a6f369a-7e3b-46bf-88ae-5da80dc2c064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257820302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4257820302
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3051151533
Short name T80
Test name
Test status
Simulation time 4905418693 ps
CPU time 26.25 seconds
Started Jun 30 04:51:01 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 212472 kb
Host smart-06e9f940-1814-4d48-bf76-e8c1927f8d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051151533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3051151533
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.899135573
Short name T249
Test name
Test status
Simulation time 380809190 ps
CPU time 6.77 seconds
Started Jun 30 04:50:59 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 211148 kb
Host smart-33e11799-949d-4f61-bee3-ef7bc44474e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899135573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.899135573
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3614108039
Short name T352
Test name
Test status
Simulation time 19291731951 ps
CPU time 1545.73 seconds
Started Jun 30 04:50:59 PM PDT 24
Finished Jun 30 05:16:45 PM PDT 24
Peak memory 228076 kb
Host smart-e709ed44-9c3d-4262-9066-b9a6fa375b77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614108039 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3614108039
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.915327011
Short name T199
Test name
Test status
Simulation time 501416160 ps
CPU time 7.47 seconds
Started Jun 30 04:50:59 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 211312 kb
Host smart-46d03ea0-6a18-4f01-ac52-44d13f4cf396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915327011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.915327011
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4220758346
Short name T154
Test name
Test status
Simulation time 233600732463 ps
CPU time 522.19 seconds
Started Jun 30 04:51:00 PM PDT 24
Finished Jun 30 04:59:43 PM PDT 24
Peak memory 212528 kb
Host smart-2a9833c0-77bd-401d-89e8-9a233b7c866f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220758346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4220758346
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1776944193
Short name T142
Test name
Test status
Simulation time 3372744604 ps
CPU time 30.04 seconds
Started Jun 30 04:51:01 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 211972 kb
Host smart-050a1508-eba4-40ef-a20f-c58976a0dd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776944193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1776944193
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.692830749
Short name T257
Test name
Test status
Simulation time 97910250 ps
CPU time 5.45 seconds
Started Jun 30 04:51:02 PM PDT 24
Finished Jun 30 04:51:08 PM PDT 24
Peak memory 211296 kb
Host smart-7bb1ab54-31ca-4e19-8369-26ba8bd2d256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692830749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.692830749
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2120527447
Short name T310
Test name
Test status
Simulation time 7313168645 ps
CPU time 36.29 seconds
Started Jun 30 04:51:00 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 213500 kb
Host smart-2458ce08-89d6-409b-ad8b-3bc1c2a49575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120527447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2120527447
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2776633795
Short name T128
Test name
Test status
Simulation time 3408853773 ps
CPU time 43.56 seconds
Started Jun 30 04:51:03 PM PDT 24
Finished Jun 30 04:51:47 PM PDT 24
Peak memory 216472 kb
Host smart-a03cc807-daa1-402c-9973-a789f9c8e9db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776633795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2776633795
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3695733171
Short name T8
Test name
Test status
Simulation time 321503236 ps
CPU time 4.33 seconds
Started Jun 30 04:51:01 PM PDT 24
Finished Jun 30 04:51:06 PM PDT 24
Peak memory 211316 kb
Host smart-32f13979-4ae6-40b5-a907-45178f20ba03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695733171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3695733171
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.644658161
Short name T42
Test name
Test status
Simulation time 67857379950 ps
CPU time 341.08 seconds
Started Jun 30 04:50:59 PM PDT 24
Finished Jun 30 04:56:41 PM PDT 24
Peak memory 212564 kb
Host smart-b2262bd9-2992-4a8b-b5b5-8cd233cf28cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644658161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.644658161
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.762498813
Short name T141
Test name
Test status
Simulation time 5430747370 ps
CPU time 22.17 seconds
Started Jun 30 04:51:01 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 212172 kb
Host smart-10e62f39-632d-46bd-852d-38d4fee8f38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762498813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.762498813
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.191577926
Short name T7
Test name
Test status
Simulation time 188636158 ps
CPU time 5.86 seconds
Started Jun 30 04:51:02 PM PDT 24
Finished Jun 30 04:51:08 PM PDT 24
Peak memory 211296 kb
Host smart-98988886-82ed-4952-b3ec-6ec10c2ddb76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=191577926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.191577926
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1046625210
Short name T201
Test name
Test status
Simulation time 664675849 ps
CPU time 14.63 seconds
Started Jun 30 04:51:02 PM PDT 24
Finished Jun 30 04:51:17 PM PDT 24
Peak memory 211812 kb
Host smart-b8d0cdf0-8780-4df6-bcea-b29b60d41862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046625210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1046625210
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3336153872
Short name T28
Test name
Test status
Simulation time 951538122 ps
CPU time 10.1 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:50:16 PM PDT 24
Peak memory 211224 kb
Host smart-7ced03a8-41ee-4c68-9015-8456ca7705d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336153872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3336153872
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1709727475
Short name T288
Test name
Test status
Simulation time 30218912951 ps
CPU time 280.24 seconds
Started Jun 30 04:50:08 PM PDT 24
Finished Jun 30 04:54:49 PM PDT 24
Peak memory 233716 kb
Host smart-283502e0-2209-49bf-840c-7679e8c20b81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709727475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1709727475
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.292793946
Short name T125
Test name
Test status
Simulation time 25168016942 ps
CPU time 32.4 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:50:36 PM PDT 24
Peak memory 212516 kb
Host smart-2f44fe16-3b03-4915-a5c6-23a5726eb9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292793946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.292793946
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.44907038
Short name T203
Test name
Test status
Simulation time 21840645416 ps
CPU time 16.04 seconds
Started Jun 30 04:50:03 PM PDT 24
Finished Jun 30 04:50:20 PM PDT 24
Peak memory 211372 kb
Host smart-5288cbd4-506f-4a3d-b219-b18db145bf66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44907038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.44907038
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3776926614
Short name T30
Test name
Test status
Simulation time 655690915 ps
CPU time 101.61 seconds
Started Jun 30 04:50:08 PM PDT 24
Finished Jun 30 04:51:50 PM PDT 24
Peak memory 236744 kb
Host smart-43383283-03a6-4905-bce2-ddfd0a554ec3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776926614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3776926614
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1652616002
Short name T159
Test name
Test status
Simulation time 33796465112 ps
CPU time 35.98 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:50:43 PM PDT 24
Peak memory 214916 kb
Host smart-43128f6f-d588-4d13-a301-71896896e9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652616002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1652616002
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2854650469
Short name T82
Test name
Test status
Simulation time 9977250920 ps
CPU time 60.32 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:51:07 PM PDT 24
Peak memory 216952 kb
Host smart-317007e2-0978-414d-b906-98ad29d93397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854650469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2854650469
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2383405607
Short name T183
Test name
Test status
Simulation time 3295193072 ps
CPU time 16.15 seconds
Started Jun 30 04:51:07 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 211352 kb
Host smart-58b637e8-0d33-4971-b0b7-7dc24f8aeec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383405607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2383405607
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2989361133
Short name T149
Test name
Test status
Simulation time 74464940473 ps
CPU time 175.19 seconds
Started Jun 30 04:51:09 PM PDT 24
Finished Jun 30 04:54:05 PM PDT 24
Peak memory 224972 kb
Host smart-784cf422-524a-447c-b245-d9d46a831696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989361133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2989361133
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1440520315
Short name T53
Test name
Test status
Simulation time 8537173604 ps
CPU time 34.09 seconds
Started Jun 30 04:51:07 PM PDT 24
Finished Jun 30 04:51:43 PM PDT 24
Peak memory 212724 kb
Host smart-eb3e5f3b-a052-4eeb-90d3-94a957d28a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440520315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1440520315
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3593349305
Short name T205
Test name
Test status
Simulation time 2023429600 ps
CPU time 16.64 seconds
Started Jun 30 04:51:07 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 211368 kb
Host smart-04cbc2d0-611a-4213-aa97-5d6ea86b87d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593349305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3593349305
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.505767994
Short name T153
Test name
Test status
Simulation time 2667379509 ps
CPU time 24.88 seconds
Started Jun 30 04:51:07 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 213452 kb
Host smart-083f0e18-de44-4880-aa55-4bd43c1b56ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505767994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.505767994
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1213231312
Short name T304
Test name
Test status
Simulation time 6935666135 ps
CPU time 15.86 seconds
Started Jun 30 04:51:08 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 215576 kb
Host smart-39a466bc-8077-42d6-ab9e-126ec4b6b1e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213231312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1213231312
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3932571070
Short name T342
Test name
Test status
Simulation time 5614142914 ps
CPU time 8.5 seconds
Started Jun 30 04:51:09 PM PDT 24
Finished Jun 30 04:51:18 PM PDT 24
Peak memory 211352 kb
Host smart-bf05b288-6cc2-434e-be41-a65d22c69a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932571070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3932571070
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2584604677
Short name T185
Test name
Test status
Simulation time 23824973047 ps
CPU time 147.8 seconds
Started Jun 30 04:51:10 PM PDT 24
Finished Jun 30 04:53:38 PM PDT 24
Peak memory 237780 kb
Host smart-ab01aa1a-67a6-4a4f-b37d-8f92a32ac7c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584604677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2584604677
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1897884704
Short name T32
Test name
Test status
Simulation time 14773576341 ps
CPU time 33.16 seconds
Started Jun 30 04:51:12 PM PDT 24
Finished Jun 30 04:51:46 PM PDT 24
Peak memory 212440 kb
Host smart-d5432ae6-c6a7-4484-a345-b99af6f96174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897884704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1897884704
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.74807888
Short name T345
Test name
Test status
Simulation time 370325909 ps
CPU time 5.35 seconds
Started Jun 30 04:51:08 PM PDT 24
Finished Jun 30 04:51:15 PM PDT 24
Peak memory 211364 kb
Host smart-f973b01e-4bf7-4f39-9a4b-dc610333df17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74807888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.74807888
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2357035412
Short name T204
Test name
Test status
Simulation time 743697153 ps
CPU time 9.91 seconds
Started Jun 30 04:51:07 PM PDT 24
Finished Jun 30 04:51:18 PM PDT 24
Peak memory 213512 kb
Host smart-bcda34f6-53a3-4b6a-936f-33508c70fd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357035412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2357035412
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2504001941
Short name T302
Test name
Test status
Simulation time 15452428486 ps
CPU time 45.18 seconds
Started Jun 30 04:51:07 PM PDT 24
Finished Jun 30 04:51:53 PM PDT 24
Peak memory 219324 kb
Host smart-c34aa25e-ef1a-46a5-8707-09680e51f19c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504001941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2504001941
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3084993209
Short name T287
Test name
Test status
Simulation time 6594796936 ps
CPU time 11.29 seconds
Started Jun 30 04:51:08 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 211312 kb
Host smart-1689ca39-17d6-465b-92b1-f0b7ff0c9530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084993209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3084993209
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4283260090
Short name T46
Test name
Test status
Simulation time 228923237619 ps
CPU time 582.58 seconds
Started Jun 30 04:51:09 PM PDT 24
Finished Jun 30 05:00:53 PM PDT 24
Peak memory 233788 kb
Host smart-82aba579-3790-45c0-b5d6-50efb484d0fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283260090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4283260090
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1823994236
Short name T290
Test name
Test status
Simulation time 2972298324 ps
CPU time 26.51 seconds
Started Jun 30 04:51:08 PM PDT 24
Finished Jun 30 04:51:36 PM PDT 24
Peak memory 211768 kb
Host smart-688913a0-bbc3-4a9b-a01f-4f13ae830dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823994236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1823994236
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.618543946
Short name T219
Test name
Test status
Simulation time 264754806 ps
CPU time 7.5 seconds
Started Jun 30 04:51:08 PM PDT 24
Finished Jun 30 04:51:17 PM PDT 24
Peak memory 211336 kb
Host smart-e48aca1e-717c-4b0e-bfa8-086a2be45d5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618543946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.618543946
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2706285973
Short name T314
Test name
Test status
Simulation time 14082334869 ps
CPU time 37.23 seconds
Started Jun 30 04:51:12 PM PDT 24
Finished Jun 30 04:51:50 PM PDT 24
Peak memory 214940 kb
Host smart-f5931323-3bd6-4c81-9b3a-94db681e2b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706285973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2706285973
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3310011017
Short name T255
Test name
Test status
Simulation time 774252341 ps
CPU time 13.6 seconds
Started Jun 30 04:51:08 PM PDT 24
Finished Jun 30 04:51:23 PM PDT 24
Peak memory 214348 kb
Host smart-079aa652-4252-47df-93ac-ebb65a061a02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310011017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3310011017
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3936961044
Short name T346
Test name
Test status
Simulation time 1840312322 ps
CPU time 14.81 seconds
Started Jun 30 04:51:10 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 211308 kb
Host smart-8c6777d7-0e39-4f9a-831d-d67954370ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936961044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3936961044
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2845483094
Short name T354
Test name
Test status
Simulation time 3542376626 ps
CPU time 81.88 seconds
Started Jun 30 04:51:08 PM PDT 24
Finished Jun 30 04:52:31 PM PDT 24
Peak memory 236588 kb
Host smart-81126fb7-d1b4-491a-842d-572a179debf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845483094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2845483094
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2956804906
Short name T319
Test name
Test status
Simulation time 663901187 ps
CPU time 9.36 seconds
Started Jun 30 04:51:11 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 212040 kb
Host smart-79d4d58e-b1e7-46b5-b8e8-88d0c9888db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956804906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2956804906
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3333151530
Short name T221
Test name
Test status
Simulation time 102736164 ps
CPU time 5.9 seconds
Started Jun 30 04:51:07 PM PDT 24
Finished Jun 30 04:51:15 PM PDT 24
Peak memory 211380 kb
Host smart-2b95d71d-d2ed-4ea6-847a-6d15e063e6dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333151530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3333151530
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.65874135
Short name T289
Test name
Test status
Simulation time 958521244 ps
CPU time 15.68 seconds
Started Jun 30 04:51:07 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 213080 kb
Host smart-3ff3ffd1-20c7-4250-a9a2-95cfb76e331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65874135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.65874135
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1293801097
Short name T170
Test name
Test status
Simulation time 1616130760 ps
CPU time 24.11 seconds
Started Jun 30 04:51:07 PM PDT 24
Finished Jun 30 04:51:33 PM PDT 24
Peak memory 215180 kb
Host smart-7ef1e7d7-f038-4f64-a271-c3b2ccc1be29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293801097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1293801097
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.422765388
Short name T38
Test name
Test status
Simulation time 191259861 ps
CPU time 4.4 seconds
Started Jun 30 04:51:15 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 211288 kb
Host smart-c1a44e8a-f126-43a3-87b6-282254131fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422765388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.422765388
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2825430335
Short name T223
Test name
Test status
Simulation time 27862989496 ps
CPU time 169.43 seconds
Started Jun 30 04:51:16 PM PDT 24
Finished Jun 30 04:54:07 PM PDT 24
Peak memory 234728 kb
Host smart-b6f55c4d-b882-4617-85ca-477fe74a7f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825430335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2825430335
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.500026512
Short name T195
Test name
Test status
Simulation time 426811187 ps
CPU time 12.46 seconds
Started Jun 30 04:51:15 PM PDT 24
Finished Jun 30 04:51:29 PM PDT 24
Peak memory 211808 kb
Host smart-7e036745-5587-4990-bde6-298a1e47abca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500026512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.500026512
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.393420989
Short name T285
Test name
Test status
Simulation time 368044078 ps
CPU time 6.66 seconds
Started Jun 30 04:51:16 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 211256 kb
Host smart-29cc27fc-a339-4e99-92f0-04e990fe85cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393420989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.393420989
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4191571672
Short name T85
Test name
Test status
Simulation time 2991961071 ps
CPU time 29.36 seconds
Started Jun 30 04:51:15 PM PDT 24
Finished Jun 30 04:51:45 PM PDT 24
Peak memory 213636 kb
Host smart-eb74d219-2d9d-4d01-9ba0-0d7f767e1fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191571672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4191571672
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2327044664
Short name T278
Test name
Test status
Simulation time 332716074 ps
CPU time 4.19 seconds
Started Jun 30 04:51:18 PM PDT 24
Finished Jun 30 04:51:22 PM PDT 24
Peak memory 211244 kb
Host smart-65f2320a-5a2c-49cb-baa3-3e5f943a7f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327044664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2327044664
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.964638245
Short name T23
Test name
Test status
Simulation time 15421385325 ps
CPU time 255.72 seconds
Started Jun 30 04:51:14 PM PDT 24
Finished Jun 30 04:55:31 PM PDT 24
Peak memory 237728 kb
Host smart-b4ac6d9a-9c09-4c52-88d5-4ec18dca65c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964638245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.964638245
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3319834974
Short name T362
Test name
Test status
Simulation time 2663398797 ps
CPU time 25.25 seconds
Started Jun 30 04:51:16 PM PDT 24
Finished Jun 30 04:51:42 PM PDT 24
Peak memory 212004 kb
Host smart-33dfc2d4-1b66-4a46-8b9e-206a7a33f1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319834974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3319834974
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4247086368
Short name T52
Test name
Test status
Simulation time 561169979 ps
CPU time 8.42 seconds
Started Jun 30 04:51:14 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 211332 kb
Host smart-5beaf7f9-40c0-4e67-8473-cb762d3b60a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247086368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4247086368
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3558474878
Short name T235
Test name
Test status
Simulation time 1044811480 ps
CPU time 16.15 seconds
Started Jun 30 04:51:19 PM PDT 24
Finished Jun 30 04:51:36 PM PDT 24
Peak memory 212784 kb
Host smart-470801a3-ed41-4df7-a3b8-001408353ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558474878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3558474878
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3193631810
Short name T283
Test name
Test status
Simulation time 686829523 ps
CPU time 9.8 seconds
Started Jun 30 04:51:14 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 213824 kb
Host smart-45145a68-a507-4e6d-94f2-06c61f9cbeca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193631810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3193631810
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1188251504
Short name T357
Test name
Test status
Simulation time 3635728682 ps
CPU time 10.11 seconds
Started Jun 30 04:51:13 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 211348 kb
Host smart-ab8c55ec-6f2f-4e34-b718-7b8b19b79706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188251504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1188251504
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.440737032
Short name T273
Test name
Test status
Simulation time 17742276008 ps
CPU time 201.3 seconds
Started Jun 30 04:51:16 PM PDT 24
Finished Jun 30 04:54:38 PM PDT 24
Peak memory 213172 kb
Host smart-227ebe69-c1b8-483c-bb7a-3bba9ac67987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440737032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.440737032
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3879757934
Short name T253
Test name
Test status
Simulation time 500256956 ps
CPU time 12.99 seconds
Started Jun 30 04:51:15 PM PDT 24
Finished Jun 30 04:51:29 PM PDT 24
Peak memory 213688 kb
Host smart-14e0928e-c0cd-47d9-a7fd-41f5bf100a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879757934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3879757934
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4246391738
Short name T163
Test name
Test status
Simulation time 2307391656 ps
CPU time 7.52 seconds
Started Jun 30 04:51:16 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 211396 kb
Host smart-723bcdc4-7920-4774-ab35-93b20e5b9f7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246391738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4246391738
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1624190205
Short name T280
Test name
Test status
Simulation time 2157325595 ps
CPU time 16.57 seconds
Started Jun 30 04:51:17 PM PDT 24
Finished Jun 30 04:51:34 PM PDT 24
Peak memory 213524 kb
Host smart-019e65fd-5468-455f-ba09-76d5d5e4cb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624190205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1624190205
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2957193399
Short name T156
Test name
Test status
Simulation time 4455050305 ps
CPU time 48.52 seconds
Started Jun 30 04:51:15 PM PDT 24
Finished Jun 30 04:52:05 PM PDT 24
Peak memory 217664 kb
Host smart-a3c3826e-7d93-4103-bc4b-a087e7cb58d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957193399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2957193399
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1442787297
Short name T62
Test name
Test status
Simulation time 13342595389 ps
CPU time 757.94 seconds
Started Jun 30 04:51:19 PM PDT 24
Finished Jun 30 05:03:58 PM PDT 24
Peak memory 223232 kb
Host smart-4c68fa66-1829-44c0-af94-8360023170da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442787297 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1442787297
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1521382684
Short name T193
Test name
Test status
Simulation time 3747858306 ps
CPU time 14.09 seconds
Started Jun 30 04:51:14 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 211348 kb
Host smart-3738017c-3039-4d38-8920-1700a49d021b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521382684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1521382684
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3400434938
Short name T359
Test name
Test status
Simulation time 3140229779 ps
CPU time 113.15 seconds
Started Jun 30 04:51:14 PM PDT 24
Finished Jun 30 04:53:09 PM PDT 24
Peak memory 236888 kb
Host smart-8b4cef03-1df5-4154-8fd8-3c92577e459d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400434938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3400434938
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2287954008
Short name T138
Test name
Test status
Simulation time 2766405579 ps
CPU time 13.82 seconds
Started Jun 30 04:51:14 PM PDT 24
Finished Jun 30 04:51:29 PM PDT 24
Peak memory 211900 kb
Host smart-756857bf-973c-41ba-bcd6-c80b4e65cbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287954008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2287954008
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.17017147
Short name T313
Test name
Test status
Simulation time 2289089107 ps
CPU time 11.83 seconds
Started Jun 30 04:51:18 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 211348 kb
Host smart-bebf301c-dc3d-47c5-a4e1-723be4a44ccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17017147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.17017147
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.740213509
Short name T48
Test name
Test status
Simulation time 13049435531 ps
CPU time 25.8 seconds
Started Jun 30 04:51:17 PM PDT 24
Finished Jun 30 04:51:44 PM PDT 24
Peak memory 213828 kb
Host smart-14a326b3-0b7e-4298-8371-eea5f0d31ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740213509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.740213509
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.922476770
Short name T181
Test name
Test status
Simulation time 13842709670 ps
CPU time 65.28 seconds
Started Jun 30 04:51:16 PM PDT 24
Finished Jun 30 04:52:23 PM PDT 24
Peak memory 216900 kb
Host smart-59986765-3eb4-442b-a048-bfcf81e0c1ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922476770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.922476770
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2177196179
Short name T186
Test name
Test status
Simulation time 664622053 ps
CPU time 5.46 seconds
Started Jun 30 04:51:21 PM PDT 24
Finished Jun 30 04:51:27 PM PDT 24
Peak memory 211300 kb
Host smart-f7f78efd-30af-4059-b4e6-bbf955a00adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177196179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2177196179
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1765349293
Short name T246
Test name
Test status
Simulation time 20193264263 ps
CPU time 269.23 seconds
Started Jun 30 04:51:14 PM PDT 24
Finished Jun 30 04:55:45 PM PDT 24
Peak memory 228592 kb
Host smart-3c8c7e07-ad9d-4b1e-9515-48fa890ab5f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765349293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1765349293
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3395970518
Short name T225
Test name
Test status
Simulation time 3857161389 ps
CPU time 10.97 seconds
Started Jun 30 04:51:13 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 211432 kb
Host smart-f31a6b2c-2aad-4721-8af2-90aa1243b364
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395970518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3395970518
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3595798432
Short name T39
Test name
Test status
Simulation time 15136321085 ps
CPU time 36 seconds
Started Jun 30 04:51:17 PM PDT 24
Finished Jun 30 04:51:54 PM PDT 24
Peak memory 213868 kb
Host smart-c9b9b915-406a-4893-9b31-e86ce11af2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595798432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3595798432
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.264964713
Short name T245
Test name
Test status
Simulation time 1362014718 ps
CPU time 16.02 seconds
Started Jun 30 04:51:16 PM PDT 24
Finished Jun 30 04:51:33 PM PDT 24
Peak memory 211236 kb
Host smart-96cf1df6-792c-4378-9236-96dc039d28e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264964713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.264964713
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3747426668
Short name T58
Test name
Test status
Simulation time 17946657106 ps
CPU time 658.45 seconds
Started Jun 30 04:51:19 PM PDT 24
Finished Jun 30 05:02:19 PM PDT 24
Peak memory 234200 kb
Host smart-11336181-da3b-4455-a7b5-7e9fdbc43b21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747426668 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3747426668
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3018533604
Short name T209
Test name
Test status
Simulation time 485559380 ps
CPU time 7.28 seconds
Started Jun 30 04:51:15 PM PDT 24
Finished Jun 30 04:51:23 PM PDT 24
Peak memory 211320 kb
Host smart-7b969864-b4d4-44ed-8157-304e4fa3e4a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018533604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3018533604
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2455853358
Short name T155
Test name
Test status
Simulation time 20339482355 ps
CPU time 223.5 seconds
Started Jun 30 04:51:15 PM PDT 24
Finished Jun 30 04:55:00 PM PDT 24
Peak memory 228548 kb
Host smart-5d3011f1-2bab-448a-93fc-4896653e5410
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455853358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2455853358
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.990272087
Short name T173
Test name
Test status
Simulation time 3148832763 ps
CPU time 27.9 seconds
Started Jun 30 04:51:19 PM PDT 24
Finished Jun 30 04:51:47 PM PDT 24
Peak memory 211808 kb
Host smart-db2f52d2-58f7-45f7-b65d-beca6828ef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990272087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.990272087
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1661456260
Short name T121
Test name
Test status
Simulation time 3288338700 ps
CPU time 9.95 seconds
Started Jun 30 04:51:14 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 211384 kb
Host smart-86d314ad-0151-4770-b1a6-d57653411d55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661456260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1661456260
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2535402972
Short name T137
Test name
Test status
Simulation time 1758190916 ps
CPU time 15.99 seconds
Started Jun 30 04:51:15 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 213720 kb
Host smart-082ebe5d-e5e8-4a90-9eae-33884eb3d5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535402972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2535402972
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1143632872
Short name T215
Test name
Test status
Simulation time 1960666058 ps
CPU time 36.6 seconds
Started Jun 30 04:51:18 PM PDT 24
Finished Jun 30 04:51:55 PM PDT 24
Peak memory 214248 kb
Host smart-117f7e74-a683-4bd7-9eb8-79edaf912792
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143632872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1143632872
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2417171500
Short name T277
Test name
Test status
Simulation time 69366343972 ps
CPU time 3325.81 seconds
Started Jun 30 04:51:16 PM PDT 24
Finished Jun 30 05:46:44 PM PDT 24
Peak memory 235752 kb
Host smart-be3ea271-b87b-4c90-9bda-5710126aadc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417171500 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2417171500
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2997401773
Short name T326
Test name
Test status
Simulation time 85408485 ps
CPU time 4.31 seconds
Started Jun 30 04:50:08 PM PDT 24
Finished Jun 30 04:50:13 PM PDT 24
Peak memory 211316 kb
Host smart-b28b5cad-30f1-4e1a-9210-19752b09b7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997401773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2997401773
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.512760040
Short name T247
Test name
Test status
Simulation time 86285650079 ps
CPU time 414.03 seconds
Started Jun 30 04:50:06 PM PDT 24
Finished Jun 30 04:57:01 PM PDT 24
Peak memory 225216 kb
Host smart-09f7795a-b8b3-48c7-9887-7f84e9c19e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512760040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.512760040
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2865771401
Short name T130
Test name
Test status
Simulation time 12105743300 ps
CPU time 26.9 seconds
Started Jun 30 04:50:08 PM PDT 24
Finished Jun 30 04:50:36 PM PDT 24
Peak memory 212392 kb
Host smart-aab4478f-6045-474b-96cb-625781f2fc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865771401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2865771401
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2267418933
Short name T126
Test name
Test status
Simulation time 3758114942 ps
CPU time 15 seconds
Started Jun 30 04:50:07 PM PDT 24
Finished Jun 30 04:50:23 PM PDT 24
Peak memory 211344 kb
Host smart-a5c187e4-f625-468f-9f4b-f88f6e06c201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267418933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2267418933
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2740054889
Short name T234
Test name
Test status
Simulation time 3108136696 ps
CPU time 27.95 seconds
Started Jun 30 04:50:07 PM PDT 24
Finished Jun 30 04:50:36 PM PDT 24
Peak memory 211816 kb
Host smart-4475a53b-00aa-48e8-8f8d-d027e4c16d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740054889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2740054889
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1975110343
Short name T303
Test name
Test status
Simulation time 18216622165 ps
CPU time 44.64 seconds
Started Jun 30 04:50:08 PM PDT 24
Finished Jun 30 04:50:53 PM PDT 24
Peak memory 216824 kb
Host smart-c58e15fd-bbba-4d2c-80a9-1cf1ed1495f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975110343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1975110343
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1578465019
Short name T363
Test name
Test status
Simulation time 1174803740 ps
CPU time 11.24 seconds
Started Jun 30 04:50:17 PM PDT 24
Finished Jun 30 04:50:29 PM PDT 24
Peak memory 211256 kb
Host smart-18ceb684-e3e6-41fb-88a5-362ab362733b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578465019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1578465019
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3358439289
Short name T254
Test name
Test status
Simulation time 4896634982 ps
CPU time 110.94 seconds
Started Jun 30 04:50:13 PM PDT 24
Finished Jun 30 04:52:04 PM PDT 24
Peak memory 224552 kb
Host smart-6e894c11-70c9-449b-8cec-30b7099df61b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358439289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3358439289
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3233225045
Short name T152
Test name
Test status
Simulation time 3641671372 ps
CPU time 15.48 seconds
Started Jun 30 04:50:14 PM PDT 24
Finished Jun 30 04:50:30 PM PDT 24
Peak memory 211428 kb
Host smart-b290f876-e9fd-4a66-a4ef-e677ae857ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233225045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3233225045
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2113699023
Short name T252
Test name
Test status
Simulation time 1666094966 ps
CPU time 10.62 seconds
Started Jun 30 04:50:12 PM PDT 24
Finished Jun 30 04:50:23 PM PDT 24
Peak memory 211264 kb
Host smart-8018a0b9-e2fe-46b5-87de-f217d9d3e84e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113699023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2113699023
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.4175714275
Short name T188
Test name
Test status
Simulation time 8365750787 ps
CPU time 43.37 seconds
Started Jun 30 04:50:04 PM PDT 24
Finished Jun 30 04:50:49 PM PDT 24
Peak memory 213108 kb
Host smart-56abbfa1-43df-4e6e-87d2-29f15a8be1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175714275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.4175714275
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.657507615
Short name T230
Test name
Test status
Simulation time 23852644687 ps
CPU time 31.46 seconds
Started Jun 30 04:50:07 PM PDT 24
Finished Jun 30 04:50:39 PM PDT 24
Peak memory 214276 kb
Host smart-0fd21a71-b50c-4860-a082-bb32b0cd30e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657507615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.657507615
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3092568581
Short name T262
Test name
Test status
Simulation time 4959950525 ps
CPU time 11.76 seconds
Started Jun 30 04:50:13 PM PDT 24
Finished Jun 30 04:50:25 PM PDT 24
Peak memory 211304 kb
Host smart-17ffcdb2-9c68-4af9-8770-eab05f1622eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092568581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3092568581
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1705193942
Short name T22
Test name
Test status
Simulation time 13455600548 ps
CPU time 130.08 seconds
Started Jun 30 04:50:10 PM PDT 24
Finished Jun 30 04:52:21 PM PDT 24
Peak memory 236788 kb
Host smart-a724886b-56c7-4694-baae-e2f106dadef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705193942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1705193942
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.648619408
Short name T191
Test name
Test status
Simulation time 19376201614 ps
CPU time 34.18 seconds
Started Jun 30 04:50:16 PM PDT 24
Finished Jun 30 04:50:51 PM PDT 24
Peak memory 212224 kb
Host smart-de746706-cec1-4490-a869-0f7317c7595c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648619408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.648619408
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2430702312
Short name T301
Test name
Test status
Simulation time 2385600880 ps
CPU time 8.72 seconds
Started Jun 30 04:50:14 PM PDT 24
Finished Jun 30 04:50:23 PM PDT 24
Peak memory 211340 kb
Host smart-8ac2300d-52f7-45ab-a164-c31cfa693a87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430702312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2430702312
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4132987473
Short name T312
Test name
Test status
Simulation time 2230395588 ps
CPU time 21.88 seconds
Started Jun 30 04:50:12 PM PDT 24
Finished Jun 30 04:50:34 PM PDT 24
Peak memory 212760 kb
Host smart-1de11bf7-432c-46a9-ac34-cbd0d743cc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132987473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4132987473
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2089717686
Short name T182
Test name
Test status
Simulation time 17326333529 ps
CPU time 55.42 seconds
Started Jun 30 04:50:13 PM PDT 24
Finished Jun 30 04:51:09 PM PDT 24
Peak memory 219396 kb
Host smart-0596c048-5767-4957-9088-078d58f70c7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089717686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2089717686
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3877101761
Short name T214
Test name
Test status
Simulation time 2165323484 ps
CPU time 13.19 seconds
Started Jun 30 04:50:15 PM PDT 24
Finished Jun 30 04:50:28 PM PDT 24
Peak memory 211288 kb
Host smart-28d511cd-b619-4135-9af5-d748efbbcb35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877101761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3877101761
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1548892266
Short name T21
Test name
Test status
Simulation time 74804693480 ps
CPU time 205.11 seconds
Started Jun 30 04:50:12 PM PDT 24
Finished Jun 30 04:53:38 PM PDT 24
Peak memory 233536 kb
Host smart-5114804f-4a5b-4e71-9992-30b25e4c7e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548892266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1548892266
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2116756040
Short name T49
Test name
Test status
Simulation time 3387165072 ps
CPU time 27.67 seconds
Started Jun 30 04:50:15 PM PDT 24
Finished Jun 30 04:50:44 PM PDT 24
Peak memory 212024 kb
Host smart-3c162e5e-b18b-4ed0-9070-36e978657bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116756040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2116756040
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1863468378
Short name T327
Test name
Test status
Simulation time 2217977499 ps
CPU time 7.71 seconds
Started Jun 30 04:50:12 PM PDT 24
Finished Jun 30 04:50:20 PM PDT 24
Peak memory 211344 kb
Host smart-edf7aef2-1939-474a-a031-7ca6261125e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863468378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1863468378
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.246984296
Short name T168
Test name
Test status
Simulation time 5547509034 ps
CPU time 25.39 seconds
Started Jun 30 04:50:17 PM PDT 24
Finished Jun 30 04:50:42 PM PDT 24
Peak memory 213064 kb
Host smart-7d24261f-5144-4ad9-9f73-079d5102c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246984296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.246984296
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1446294429
Short name T17
Test name
Test status
Simulation time 14699784358 ps
CPU time 30.81 seconds
Started Jun 30 04:50:12 PM PDT 24
Finished Jun 30 04:50:44 PM PDT 24
Peak memory 216180 kb
Host smart-b070b525-3f10-453b-8fd1-2a173b4f16d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446294429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1446294429
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.57873178
Short name T281
Test name
Test status
Simulation time 86208484792 ps
CPU time 5766.64 seconds
Started Jun 30 04:50:15 PM PDT 24
Finished Jun 30 06:26:22 PM PDT 24
Peak memory 235680 kb
Host smart-6566cd5a-eb09-448d-8020-0576cb584ce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57873178 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.57873178
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1283483887
Short name T229
Test name
Test status
Simulation time 367128503 ps
CPU time 6.65 seconds
Started Jun 30 04:50:18 PM PDT 24
Finished Jun 30 04:50:24 PM PDT 24
Peak memory 211192 kb
Host smart-e230edfb-d3ca-4f50-8b86-d5ffed6a7e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283483887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1283483887
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1601669649
Short name T129
Test name
Test status
Simulation time 17582455554 ps
CPU time 34.34 seconds
Started Jun 30 04:50:11 PM PDT 24
Finished Jun 30 04:50:45 PM PDT 24
Peak memory 211360 kb
Host smart-6c3132a2-1e35-409d-aa1a-a3415b66650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601669649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1601669649
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4009430621
Short name T20
Test name
Test status
Simulation time 175957104 ps
CPU time 6.6 seconds
Started Jun 30 04:50:16 PM PDT 24
Finished Jun 30 04:50:23 PM PDT 24
Peak memory 211288 kb
Host smart-74a709b4-5aad-4f3b-a8da-7c1d707d9860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4009430621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4009430621
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2948803658
Short name T250
Test name
Test status
Simulation time 8317982532 ps
CPU time 15.95 seconds
Started Jun 30 04:50:17 PM PDT 24
Finished Jun 30 04:50:33 PM PDT 24
Peak memory 214116 kb
Host smart-22517f5f-067e-43fa-abf4-ce60c9db89ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948803658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2948803658
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.240743135
Short name T143
Test name
Test status
Simulation time 1729864824 ps
CPU time 18.2 seconds
Started Jun 30 04:50:17 PM PDT 24
Finished Jun 30 04:50:35 PM PDT 24
Peak memory 211220 kb
Host smart-588dcd72-f8a7-42f1-9185-f8238b99bc3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240743135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.240743135
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.614034935
Short name T14
Test name
Test status
Simulation time 92198617348 ps
CPU time 3778.04 seconds
Started Jun 30 04:50:15 PM PDT 24
Finished Jun 30 05:53:14 PM PDT 24
Peak memory 254080 kb
Host smart-4085e3bd-0fd2-4dfe-b13d-dc03d11526f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614034935 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.614034935
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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