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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.32 96.89 92.42 97.67 100.00 98.62 97.30 98.37


Total test records in report: 462
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T298 /workspace/coverage/default/15.rom_ctrl_alert_test.4290219544 Jul 01 11:04:27 AM PDT 24 Jul 01 11:04:43 AM PDT 24 6869928640 ps
T299 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2218054739 Jul 01 11:04:17 AM PDT 24 Jul 01 11:08:14 AM PDT 24 15692809750 ps
T300 /workspace/coverage/default/29.rom_ctrl_stress_all.1859196343 Jul 01 11:04:42 AM PDT 24 Jul 01 11:04:59 AM PDT 24 343310794 ps
T301 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3200578771 Jul 01 11:04:29 AM PDT 24 Jul 01 11:04:50 AM PDT 24 12328992632 ps
T302 /workspace/coverage/default/32.rom_ctrl_alert_test.1443088508 Jul 01 11:04:43 AM PDT 24 Jul 01 11:04:53 AM PDT 24 825727223 ps
T303 /workspace/coverage/default/22.rom_ctrl_smoke.3990533402 Jul 01 11:04:28 AM PDT 24 Jul 01 11:05:04 AM PDT 24 4228938058 ps
T304 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2148889284 Jul 01 11:04:43 AM PDT 24 Jul 01 11:04:57 AM PDT 24 4585160060 ps
T305 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2639313606 Jul 01 11:04:42 AM PDT 24 Jul 01 11:08:28 AM PDT 24 93783577594 ps
T306 /workspace/coverage/default/28.rom_ctrl_smoke.2521709769 Jul 01 11:04:30 AM PDT 24 Jul 01 11:04:41 AM PDT 24 2007250833 ps
T307 /workspace/coverage/default/1.rom_ctrl_alert_test.2452303314 Jul 01 11:03:51 AM PDT 24 Jul 01 11:04:08 AM PDT 24 4014428363 ps
T308 /workspace/coverage/default/25.rom_ctrl_smoke.3909748404 Jul 01 11:04:25 AM PDT 24 Jul 01 11:04:36 AM PDT 24 191862572 ps
T309 /workspace/coverage/default/8.rom_ctrl_smoke.3461410589 Jul 01 11:04:09 AM PDT 24 Jul 01 11:04:20 AM PDT 24 191519857 ps
T310 /workspace/coverage/default/43.rom_ctrl_alert_test.262809575 Jul 01 11:05:13 AM PDT 24 Jul 01 11:05:18 AM PDT 24 86653135 ps
T311 /workspace/coverage/default/25.rom_ctrl_alert_test.3948293040 Jul 01 11:04:28 AM PDT 24 Jul 01 11:04:44 AM PDT 24 1741030815 ps
T312 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2953383725 Jul 01 11:04:41 AM PDT 24 Jul 01 11:04:57 AM PDT 24 11518112260 ps
T313 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1216119206 Jul 01 11:04:13 AM PDT 24 Jul 01 11:06:01 AM PDT 24 2650721870 ps
T314 /workspace/coverage/default/29.rom_ctrl_alert_test.2406338138 Jul 01 11:04:41 AM PDT 24 Jul 01 11:04:51 AM PDT 24 1849895877 ps
T315 /workspace/coverage/default/42.rom_ctrl_alert_test.3981488795 Jul 01 11:05:03 AM PDT 24 Jul 01 11:05:14 AM PDT 24 2734117169 ps
T316 /workspace/coverage/default/41.rom_ctrl_smoke.3286421229 Jul 01 11:04:56 AM PDT 24 Jul 01 11:05:15 AM PDT 24 1345177052 ps
T317 /workspace/coverage/default/31.rom_ctrl_stress_all.345864723 Jul 01 11:04:37 AM PDT 24 Jul 01 11:05:44 AM PDT 24 27452085542 ps
T318 /workspace/coverage/default/26.rom_ctrl_stress_all.3096444468 Jul 01 11:04:34 AM PDT 24 Jul 01 11:04:52 AM PDT 24 301733657 ps
T319 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2039775247 Jul 01 11:04:41 AM PDT 24 Jul 01 11:04:51 AM PDT 24 175879181 ps
T320 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4293279617 Jul 01 11:04:32 AM PDT 24 Jul 01 11:11:14 AM PDT 24 171654993659 ps
T321 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2982784159 Jul 01 11:03:51 AM PDT 24 Jul 01 11:04:06 AM PDT 24 2450598122 ps
T322 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1531302524 Jul 01 11:04:01 AM PDT 24 Jul 01 11:04:16 AM PDT 24 1230763069 ps
T323 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1647688342 Jul 01 11:04:46 AM PDT 24 Jul 01 11:07:12 AM PDT 24 4438032362 ps
T324 /workspace/coverage/default/49.rom_ctrl_smoke.1352780299 Jul 01 11:05:10 AM PDT 24 Jul 01 11:05:40 AM PDT 24 6123818045 ps
T325 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2234892738 Jul 01 11:05:12 AM PDT 24 Jul 01 11:56:28 AM PDT 24 340014721814 ps
T326 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3965514403 Jul 01 11:04:54 AM PDT 24 Jul 01 11:05:09 AM PDT 24 1571686368 ps
T327 /workspace/coverage/default/39.rom_ctrl_alert_test.1083252205 Jul 01 11:04:54 AM PDT 24 Jul 01 11:05:03 AM PDT 24 6115353469 ps
T328 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3462650305 Jul 01 11:05:09 AM PDT 24 Jul 01 11:11:12 AM PDT 24 38572529177 ps
T329 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3702640807 Jul 01 11:05:09 AM PDT 24 Jul 01 11:07:29 AM PDT 24 51904298699 ps
T330 /workspace/coverage/default/19.rom_ctrl_alert_test.3491428838 Jul 01 11:04:24 AM PDT 24 Jul 01 11:04:30 AM PDT 24 167694914 ps
T331 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2185319698 Jul 01 11:05:17 AM PDT 24 Jul 01 11:07:44 AM PDT 24 89286768978 ps
T332 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1611623101 Jul 01 11:04:52 AM PDT 24 Jul 01 11:05:21 AM PDT 24 25427528957 ps
T333 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1170648880 Jul 01 11:04:21 AM PDT 24 Jul 01 11:10:29 AM PDT 24 35469807164 ps
T334 /workspace/coverage/default/5.rom_ctrl_alert_test.1862952415 Jul 01 11:04:12 AM PDT 24 Jul 01 11:04:23 AM PDT 24 1886111333 ps
T335 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3571899923 Jul 01 11:04:41 AM PDT 24 Jul 01 11:05:11 AM PDT 24 3520149293 ps
T336 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4038979118 Jul 01 11:04:21 AM PDT 24 Jul 01 11:06:21 AM PDT 24 11277166842 ps
T337 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1081394194 Jul 01 11:04:25 AM PDT 24 Jul 01 11:04:46 AM PDT 24 7183039889 ps
T338 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.836382862 Jul 01 11:05:11 AM PDT 24 Jul 01 11:05:24 AM PDT 24 4792701190 ps
T339 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3805420780 Jul 01 11:04:36 AM PDT 24 Jul 01 11:04:46 AM PDT 24 341127023 ps
T340 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3729584857 Jul 01 11:04:41 AM PDT 24 Jul 01 11:34:01 AM PDT 24 47268957779 ps
T341 /workspace/coverage/default/40.rom_ctrl_smoke.2700500078 Jul 01 11:04:52 AM PDT 24 Jul 01 11:05:15 AM PDT 24 8185944380 ps
T342 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.903735125 Jul 01 11:04:39 AM PDT 24 Jul 01 11:04:45 AM PDT 24 95999893 ps
T343 /workspace/coverage/default/38.rom_ctrl_smoke.1242533122 Jul 01 11:04:51 AM PDT 24 Jul 01 11:05:20 AM PDT 24 10439834979 ps
T344 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.760012666 Jul 01 11:04:47 AM PDT 24 Jul 01 11:05:03 AM PDT 24 1803790766 ps
T24 /workspace/coverage/default/4.rom_ctrl_sec_cm.634267700 Jul 01 11:03:58 AM PDT 24 Jul 01 11:05:46 AM PDT 24 7222992465 ps
T345 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2850710701 Jul 01 11:04:22 AM PDT 24 Jul 01 11:04:39 AM PDT 24 1956914542 ps
T346 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1583165443 Jul 01 11:04:24 AM PDT 24 Jul 01 11:06:40 AM PDT 24 8674231044 ps
T347 /workspace/coverage/default/35.rom_ctrl_alert_test.3593780511 Jul 01 11:04:55 AM PDT 24 Jul 01 11:05:04 AM PDT 24 1229504852 ps
T348 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.794021137 Jul 01 11:04:23 AM PDT 24 Jul 01 11:04:29 AM PDT 24 97879525 ps
T349 /workspace/coverage/default/3.rom_ctrl_stress_all.1095481552 Jul 01 11:04:13 AM PDT 24 Jul 01 11:04:44 AM PDT 24 14493715033 ps
T350 /workspace/coverage/default/30.rom_ctrl_stress_all.3621062500 Jul 01 11:04:35 AM PDT 24 Jul 01 11:05:41 AM PDT 24 23812896692 ps
T351 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2843008580 Jul 01 11:04:37 AM PDT 24 Jul 01 11:04:49 AM PDT 24 1134657802 ps
T352 /workspace/coverage/default/1.rom_ctrl_stress_all.382892859 Jul 01 11:03:52 AM PDT 24 Jul 01 11:04:23 AM PDT 24 1916915606 ps
T353 /workspace/coverage/default/6.rom_ctrl_stress_all.1818842330 Jul 01 11:04:02 AM PDT 24 Jul 01 11:04:24 AM PDT 24 2436795931 ps
T354 /workspace/coverage/default/24.rom_ctrl_alert_test.1945515179 Jul 01 11:04:27 AM PDT 24 Jul 01 11:04:41 AM PDT 24 5908040716 ps
T355 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.786617316 Jul 01 11:04:55 AM PDT 24 Jul 01 11:05:23 AM PDT 24 20088477572 ps
T356 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2798673209 Jul 01 11:04:35 AM PDT 24 Jul 01 11:41:20 AM PDT 24 232571133900 ps
T357 /workspace/coverage/default/16.rom_ctrl_alert_test.3080959623 Jul 01 11:04:21 AM PDT 24 Jul 01 11:04:35 AM PDT 24 1729701111 ps
T358 /workspace/coverage/default/16.rom_ctrl_smoke.2714784078 Jul 01 11:04:24 AM PDT 24 Jul 01 11:04:37 AM PDT 24 1388676735 ps
T359 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4044739372 Jul 01 11:04:21 AM PDT 24 Jul 01 11:24:12 AM PDT 24 29995537767 ps
T360 /workspace/coverage/default/36.rom_ctrl_alert_test.3084421570 Jul 01 11:04:46 AM PDT 24 Jul 01 11:05:00 AM PDT 24 1398582708 ps
T361 /workspace/coverage/default/43.rom_ctrl_stress_all.941806201 Jul 01 11:05:07 AM PDT 24 Jul 01 11:05:21 AM PDT 24 817747309 ps
T362 /workspace/coverage/default/12.rom_ctrl_stress_all.533584470 Jul 01 11:04:15 AM PDT 24 Jul 01 11:04:32 AM PDT 24 340896303 ps
T363 /workspace/coverage/default/47.rom_ctrl_stress_all.4248013094 Jul 01 11:05:12 AM PDT 24 Jul 01 11:05:50 AM PDT 24 41544757443 ps
T364 /workspace/coverage/default/28.rom_ctrl_alert_test.3266729940 Jul 01 11:04:36 AM PDT 24 Jul 01 11:04:53 AM PDT 24 3750284107 ps
T53 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3676626046 Jul 01 10:44:20 AM PDT 24 Jul 01 10:45:24 AM PDT 24 32849497750 ps
T54 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1407424875 Jul 01 10:43:48 AM PDT 24 Jul 01 10:44:08 AM PDT 24 726868083 ps
T55 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.939607132 Jul 01 10:44:00 AM PDT 24 Jul 01 10:44:16 AM PDT 24 1510482569 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3956450937 Jul 01 10:44:26 AM PDT 24 Jul 01 10:44:47 AM PDT 24 1834274775 ps
T86 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2534324894 Jul 01 10:44:03 AM PDT 24 Jul 01 10:44:11 AM PDT 24 1060182691 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2502771768 Jul 01 10:43:52 AM PDT 24 Jul 01 10:44:01 AM PDT 24 1146509330 ps
T82 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2907678434 Jul 01 10:44:15 AM PDT 24 Jul 01 10:44:27 AM PDT 24 5395484801 ps
T367 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3228365780 Jul 01 10:43:59 AM PDT 24 Jul 01 10:44:09 AM PDT 24 330259790 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3327734907 Jul 01 10:43:53 AM PDT 24 Jul 01 10:44:06 AM PDT 24 5290059870 ps
T369 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1148635574 Jul 01 10:44:03 AM PDT 24 Jul 01 10:44:11 AM PDT 24 1155865051 ps
T87 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2430655592 Jul 01 10:43:52 AM PDT 24 Jul 01 10:44:12 AM PDT 24 32563191407 ps
T61 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1570954655 Jul 01 10:44:30 AM PDT 24 Jul 01 10:45:17 AM PDT 24 10596491277 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4084161529 Jul 01 10:44:20 AM PDT 24 Jul 01 10:44:47 AM PDT 24 1768946088 ps
T62 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.392514483 Jul 01 10:44:16 AM PDT 24 Jul 01 10:45:40 AM PDT 24 34740098154 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.143405322 Jul 01 10:43:49 AM PDT 24 Jul 01 10:44:07 AM PDT 24 9376723094 ps
T50 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3186673955 Jul 01 10:44:18 AM PDT 24 Jul 01 10:45:35 AM PDT 24 2056916821 ps
T51 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1615955249 Jul 01 10:43:50 AM PDT 24 Jul 01 10:44:31 AM PDT 24 1035641893 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.457334651 Jul 01 10:43:48 AM PDT 24 Jul 01 10:44:00 AM PDT 24 8215712184 ps
T83 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.437068212 Jul 01 10:43:54 AM PDT 24 Jul 01 10:44:13 AM PDT 24 7493453848 ps
T89 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.793458641 Jul 01 10:44:04 AM PDT 24 Jul 01 10:44:50 AM PDT 24 4810055052 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1322110602 Jul 01 10:43:47 AM PDT 24 Jul 01 10:43:57 AM PDT 24 1152358983 ps
T52 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.484992907 Jul 01 10:43:58 AM PDT 24 Jul 01 10:45:16 AM PDT 24 2602371360 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1197316185 Jul 01 10:44:30 AM PDT 24 Jul 01 10:44:38 AM PDT 24 2376864289 ps
T91 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1170042866 Jul 01 10:43:59 AM PDT 24 Jul 01 10:45:13 AM PDT 24 286335916 ps
T373 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1700176206 Jul 01 10:44:08 AM PDT 24 Jul 01 10:44:17 AM PDT 24 552480336 ps
T63 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2962910917 Jul 01 10:44:03 AM PDT 24 Jul 01 10:44:17 AM PDT 24 4655992466 ps
T96 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3520833784 Jul 01 10:43:53 AM PDT 24 Jul 01 10:44:37 AM PDT 24 8017881711 ps
T64 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4067292220 Jul 01 10:43:58 AM PDT 24 Jul 01 10:44:06 AM PDT 24 87317841 ps
T65 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.830633883 Jul 01 10:44:08 AM PDT 24 Jul 01 10:44:23 AM PDT 24 5131506742 ps
T85 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2057820203 Jul 01 10:44:04 AM PDT 24 Jul 01 10:44:15 AM PDT 24 1031840892 ps
T374 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4100048941 Jul 01 10:43:57 AM PDT 24 Jul 01 10:44:08 AM PDT 24 454588040 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2999463315 Jul 01 10:44:14 AM PDT 24 Jul 01 10:44:27 AM PDT 24 6440049802 ps
T376 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.83295645 Jul 01 10:44:27 AM PDT 24 Jul 01 10:44:44 AM PDT 24 7588831775 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1825813223 Jul 01 10:44:16 AM PDT 24 Jul 01 10:44:31 AM PDT 24 7331397582 ps
T66 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1204805514 Jul 01 10:44:06 AM PDT 24 Jul 01 10:44:11 AM PDT 24 85821677 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.825797294 Jul 01 10:43:50 AM PDT 24 Jul 01 10:44:06 AM PDT 24 1895509680 ps
T379 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1650871076 Jul 01 10:43:58 AM PDT 24 Jul 01 10:44:06 AM PDT 24 90811754 ps
T103 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.122328090 Jul 01 10:44:27 AM PDT 24 Jul 01 10:45:09 AM PDT 24 1075570205 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.385910770 Jul 01 10:44:11 AM PDT 24 Jul 01 10:44:24 AM PDT 24 5860838901 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.930862785 Jul 01 10:43:46 AM PDT 24 Jul 01 10:43:57 AM PDT 24 1113985091 ps
T381 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3231672924 Jul 01 10:44:01 AM PDT 24 Jul 01 10:44:08 AM PDT 24 105104126 ps
T382 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1504999205 Jul 01 10:44:08 AM PDT 24 Jul 01 10:44:53 AM PDT 24 1422366697 ps
T68 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2577600926 Jul 01 10:44:05 AM PDT 24 Jul 01 10:44:16 AM PDT 24 4927754391 ps
T383 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.773827122 Jul 01 10:44:11 AM PDT 24 Jul 01 10:44:19 AM PDT 24 2178440758 ps
T73 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.589971399 Jul 01 10:44:31 AM PDT 24 Jul 01 10:45:47 AM PDT 24 32485039771 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2284527937 Jul 01 10:44:02 AM PDT 24 Jul 01 10:44:16 AM PDT 24 6576041418 ps
T385 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3245815270 Jul 01 10:43:44 AM PDT 24 Jul 01 10:44:22 AM PDT 24 2053420557 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3326790131 Jul 01 10:44:37 AM PDT 24 Jul 01 10:44:49 AM PDT 24 4398188429 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1532323706 Jul 01 10:44:05 AM PDT 24 Jul 01 10:44:23 AM PDT 24 2029274300 ps
T97 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.356830014 Jul 01 10:43:53 AM PDT 24 Jul 01 10:44:39 AM PDT 24 2866937103 ps
T388 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3405193531 Jul 01 10:44:03 AM PDT 24 Jul 01 10:44:16 AM PDT 24 3520178781 ps
T389 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2426689663 Jul 01 10:44:59 AM PDT 24 Jul 01 10:45:31 AM PDT 24 4948115445 ps
T390 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3815841816 Jul 01 10:44:28 AM PDT 24 Jul 01 10:44:39 AM PDT 24 501076766 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2107045184 Jul 01 10:44:18 AM PDT 24 Jul 01 10:45:05 AM PDT 24 20527479024 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1852557471 Jul 01 10:43:50 AM PDT 24 Jul 01 10:43:55 AM PDT 24 85661285 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.508308801 Jul 01 10:43:58 AM PDT 24 Jul 01 10:44:13 AM PDT 24 4311040071 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1969361045 Jul 01 10:44:59 AM PDT 24 Jul 01 10:45:18 AM PDT 24 8589702574 ps
T90 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1287662387 Jul 01 10:43:57 AM PDT 24 Jul 01 10:44:20 AM PDT 24 971811871 ps
T394 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3591581432 Jul 01 10:44:23 AM PDT 24 Jul 01 10:44:34 AM PDT 24 1247736990 ps
T395 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1924152109 Jul 01 10:44:05 AM PDT 24 Jul 01 10:44:15 AM PDT 24 1573047732 ps
T396 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2105956340 Jul 01 10:45:33 AM PDT 24 Jul 01 10:45:49 AM PDT 24 6851312500 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.552372577 Jul 01 10:43:49 AM PDT 24 Jul 01 10:43:57 AM PDT 24 1484318378 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2238786972 Jul 01 10:44:13 AM PDT 24 Jul 01 10:44:29 AM PDT 24 1430541920 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1863891054 Jul 01 10:44:19 AM PDT 24 Jul 01 10:44:40 AM PDT 24 8523124296 ps
T400 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3210982963 Jul 01 10:43:58 AM PDT 24 Jul 01 10:44:08 AM PDT 24 1598779897 ps
T401 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2408498886 Jul 01 10:44:00 AM PDT 24 Jul 01 10:44:38 AM PDT 24 2642034336 ps
T402 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1454561289 Jul 01 10:44:07 AM PDT 24 Jul 01 10:44:14 AM PDT 24 196272061 ps
T403 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.262449808 Jul 01 10:44:03 AM PDT 24 Jul 01 10:44:16 AM PDT 24 6488324055 ps
T100 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.179230918 Jul 01 10:43:54 AM PDT 24 Jul 01 10:45:06 AM PDT 24 501353814 ps
T404 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1294071654 Jul 01 10:43:57 AM PDT 24 Jul 01 10:44:14 AM PDT 24 9140970539 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1528948000 Jul 01 10:43:57 AM PDT 24 Jul 01 10:44:09 AM PDT 24 584312641 ps
T74 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.542644313 Jul 01 10:44:21 AM PDT 24 Jul 01 10:45:36 AM PDT 24 7877670940 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1258702101 Jul 01 10:43:57 AM PDT 24 Jul 01 10:45:23 AM PDT 24 44746006558 ps
T407 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.819354888 Jul 01 10:44:00 AM PDT 24 Jul 01 10:44:08 AM PDT 24 375759742 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2080785827 Jul 01 10:43:56 AM PDT 24 Jul 01 10:44:05 AM PDT 24 89829795 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1552963300 Jul 01 10:44:05 AM PDT 24 Jul 01 10:44:10 AM PDT 24 270006581 ps
T410 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3573538582 Jul 01 10:43:57 AM PDT 24 Jul 01 10:44:17 AM PDT 24 4829347219 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2968623415 Jul 01 10:43:58 AM PDT 24 Jul 01 10:44:11 AM PDT 24 6311462426 ps
T412 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1955865353 Jul 01 10:43:48 AM PDT 24 Jul 01 10:43:54 AM PDT 24 107000350 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1774867400 Jul 01 10:44:11 AM PDT 24 Jul 01 10:44:28 AM PDT 24 1958371984 ps
T414 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.444457946 Jul 01 10:43:55 AM PDT 24 Jul 01 10:44:18 AM PDT 24 372157398 ps
T415 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2001218229 Jul 01 10:44:32 AM PDT 24 Jul 01 10:45:12 AM PDT 24 346877848 ps
T416 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3074081280 Jul 01 10:44:18 AM PDT 24 Jul 01 10:45:59 AM PDT 24 45705014133 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.251120645 Jul 01 10:43:55 AM PDT 24 Jul 01 10:44:06 AM PDT 24 541541134 ps
T418 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2013823039 Jul 01 10:44:19 AM PDT 24 Jul 01 10:44:32 AM PDT 24 2621138781 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1689333736 Jul 01 10:43:52 AM PDT 24 Jul 01 10:44:07 AM PDT 24 1576049752 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2207991518 Jul 01 10:44:12 AM PDT 24 Jul 01 10:44:26 AM PDT 24 1281138000 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2602931278 Jul 01 10:43:52 AM PDT 24 Jul 01 10:43:59 AM PDT 24 334044365 ps
T421 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2831549147 Jul 01 10:44:04 AM PDT 24 Jul 01 10:44:16 AM PDT 24 6198128373 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.514415224 Jul 01 10:43:58 AM PDT 24 Jul 01 10:44:15 AM PDT 24 2753202897 ps
T423 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1932324541 Jul 01 10:44:07 AM PDT 24 Jul 01 10:44:16 AM PDT 24 139892445 ps
T76 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2492558215 Jul 01 10:43:58 AM PDT 24 Jul 01 10:44:42 AM PDT 24 47606348705 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2805685791 Jul 01 10:43:44 AM PDT 24 Jul 01 10:43:53 AM PDT 24 5726657897 ps
T93 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2756547015 Jul 01 10:44:00 AM PDT 24 Jul 01 10:44:38 AM PDT 24 704727027 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2160410476 Jul 01 10:43:55 AM PDT 24 Jul 01 10:44:42 AM PDT 24 4807663259 ps
T425 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.494471730 Jul 01 10:44:56 AM PDT 24 Jul 01 10:45:40 AM PDT 24 17850650968 ps
T426 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1346826075 Jul 01 10:44:05 AM PDT 24 Jul 01 10:44:18 AM PDT 24 2354802982 ps
T101 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.546460221 Jul 01 10:44:08 AM PDT 24 Jul 01 10:44:49 AM PDT 24 2568169827 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.473881115 Jul 01 10:44:01 AM PDT 24 Jul 01 10:44:18 AM PDT 24 21640412594 ps
T428 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4186914816 Jul 01 10:43:51 AM PDT 24 Jul 01 10:44:06 AM PDT 24 6341958901 ps
T429 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2692656939 Jul 01 10:44:06 AM PDT 24 Jul 01 10:44:22 AM PDT 24 37553741303 ps
T430 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3743886298 Jul 01 10:44:59 AM PDT 24 Jul 01 10:45:04 AM PDT 24 417144024 ps
T431 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3601679027 Jul 01 10:45:21 AM PDT 24 Jul 01 10:45:32 AM PDT 24 1841852105 ps
T432 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3185134367 Jul 01 10:44:02 AM PDT 24 Jul 01 10:44:07 AM PDT 24 87584177 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1078872732 Jul 01 10:43:51 AM PDT 24 Jul 01 10:44:08 AM PDT 24 1561560018 ps
T434 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1948758438 Jul 01 10:43:50 AM PDT 24 Jul 01 10:43:56 AM PDT 24 302045879 ps
T77 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3487216267 Jul 01 10:44:25 AM PDT 24 Jul 01 10:45:31 AM PDT 24 6070098644 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.314423743 Jul 01 10:43:59 AM PDT 24 Jul 01 10:44:41 AM PDT 24 293298456 ps
T435 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.130844849 Jul 01 10:44:12 AM PDT 24 Jul 01 10:45:07 AM PDT 24 6130136169 ps
T436 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3560986593 Jul 01 10:44:07 AM PDT 24 Jul 01 10:44:16 AM PDT 24 656943638 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2078579553 Jul 01 10:43:57 AM PDT 24 Jul 01 10:45:00 AM PDT 24 29455386976 ps
T438 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3729922547 Jul 01 10:44:14 AM PDT 24 Jul 01 10:44:29 AM PDT 24 5322597156 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2278630714 Jul 01 10:43:54 AM PDT 24 Jul 01 10:44:04 AM PDT 24 168160112 ps
T440 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1012978506 Jul 01 10:44:30 AM PDT 24 Jul 01 10:44:34 AM PDT 24 85685041 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3742655835 Jul 01 10:43:58 AM PDT 24 Jul 01 10:44:17 AM PDT 24 1780675902 ps
T78 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1357179891 Jul 01 10:44:04 AM PDT 24 Jul 01 10:44:16 AM PDT 24 6062215037 ps
T79 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.445129965 Jul 01 10:44:09 AM PDT 24 Jul 01 10:44:14 AM PDT 24 333293060 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2750242787 Jul 01 10:43:51 AM PDT 24 Jul 01 10:44:02 AM PDT 24 1225413345 ps
T442 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2476389213 Jul 01 10:44:59 AM PDT 24 Jul 01 10:45:10 AM PDT 24 1073816792 ps
T443 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3260437711 Jul 01 10:44:08 AM PDT 24 Jul 01 10:44:19 AM PDT 24 3100672488 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3029840264 Jul 01 10:44:15 AM PDT 24 Jul 01 10:44:24 AM PDT 24 676746790 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1217522859 Jul 01 10:44:07 AM PDT 24 Jul 01 10:44:22 AM PDT 24 6717576084 ps
T81 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1113832279 Jul 01 10:44:17 AM PDT 24 Jul 01 10:44:30 AM PDT 24 2204999396 ps
T446 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2046848462 Jul 01 10:44:21 AM PDT 24 Jul 01 10:44:32 AM PDT 24 3975777829 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1912289262 Jul 01 10:43:57 AM PDT 24 Jul 01 10:44:08 AM PDT 24 92006820 ps
T448 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.253089110 Jul 01 10:43:55 AM PDT 24 Jul 01 10:44:10 AM PDT 24 727239732 ps
T449 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.232334280 Jul 01 10:44:28 AM PDT 24 Jul 01 10:44:46 AM PDT 24 7016533527 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2177148434 Jul 01 10:43:47 AM PDT 24 Jul 01 10:44:04 AM PDT 24 4879275842 ps
T451 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.247241657 Jul 01 10:43:57 AM PDT 24 Jul 01 10:44:07 AM PDT 24 334305396 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1710349961 Jul 01 10:43:52 AM PDT 24 Jul 01 10:44:04 AM PDT 24 22020343418 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3469805429 Jul 01 10:44:12 AM PDT 24 Jul 01 10:44:23 AM PDT 24 2206191135 ps
T454 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4024637591 Jul 01 10:43:55 AM PDT 24 Jul 01 10:44:10 AM PDT 24 1354633136 ps
T95 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3478440722 Jul 01 10:43:57 AM PDT 24 Jul 01 10:45:20 AM PDT 24 9128544817 ps
T102 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1846004823 Jul 01 10:44:21 AM PDT 24 Jul 01 10:45:05 AM PDT 24 1418865366 ps
T455 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.101608547 Jul 01 10:44:30 AM PDT 24 Jul 01 10:45:31 AM PDT 24 66300933055 ps
T456 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4201875290 Jul 01 10:43:58 AM PDT 24 Jul 01 10:44:34 AM PDT 24 5261778593 ps
T457 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3458667673 Jul 01 10:44:08 AM PDT 24 Jul 01 10:44:15 AM PDT 24 427452794 ps
T98 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2791915352 Jul 01 10:43:56 AM PDT 24 Jul 01 10:44:44 AM PDT 24 15175094691 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1209005709 Jul 01 10:43:54 AM PDT 24 Jul 01 10:44:04 AM PDT 24 593951847 ps
T459 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3845442315 Jul 01 10:43:54 AM PDT 24 Jul 01 10:44:03 AM PDT 24 2498732148 ps
T99 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1500926834 Jul 01 10:43:53 AM PDT 24 Jul 01 10:44:33 AM PDT 24 172027676 ps
T460 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.459860894 Jul 01 10:44:26 AM PDT 24 Jul 01 10:44:36 AM PDT 24 568047545 ps
T461 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.91295964 Jul 01 10:43:51 AM PDT 24 Jul 01 10:44:05 AM PDT 24 6407085397 ps
T462 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3711642507 Jul 01 10:44:35 AM PDT 24 Jul 01 10:44:42 AM PDT 24 349576293 ps

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3449693362
Short name T4
Test name
Test status
Simulation time 45514112026 ps
CPU time 209.23 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:07:59 AM PDT 24
Peak memory 213664 kb
Host smart-d52fd862-3492-4bf2-8c04-3569bd0e1093
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449693362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3449693362
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.540588094
Short name T19
Test name
Test status
Simulation time 47575353565 ps
CPU time 967.42 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:20:37 AM PDT 24
Peak memory 230624 kb
Host smart-eff86b81-9a31-404b-af78-91eee8d65590
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540588094 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.540588094
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2870015869
Short name T231
Test name
Test status
Simulation time 17535973058 ps
CPU time 240.51 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:08:30 AM PDT 24
Peak memory 233828 kb
Host smart-1e511de8-2530-439d-854a-55a3d72ae1ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870015869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2870015869
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2207376041
Short name T11
Test name
Test status
Simulation time 2140883382 ps
CPU time 13.98 seconds
Started Jul 01 11:04:07 AM PDT 24
Finished Jul 01 11:04:22 AM PDT 24
Peak memory 213572 kb
Host smart-fa5f286b-7459-436c-a279-514ea4d926b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207376041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2207376041
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.484992907
Short name T52
Test name
Test status
Simulation time 2602371360 ps
CPU time 74.96 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:45:16 AM PDT 24
Peak memory 212084 kb
Host smart-995841bc-90ed-4832-943c-f7e2db34361f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484992907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.484992907
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3679543739
Short name T15
Test name
Test status
Simulation time 222018601 ps
CPU time 51.83 seconds
Started Jul 01 11:03:49 AM PDT 24
Finished Jul 01 11:04:43 AM PDT 24
Peak memory 236924 kb
Host smart-72519f0f-845d-4c7a-9367-bddf3d7727a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679543739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3679543739
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1570954655
Short name T61
Test name
Test status
Simulation time 10596491277 ps
CPU time 47.55 seconds
Started Jul 01 10:44:30 AM PDT 24
Finished Jul 01 10:45:17 AM PDT 24
Peak memory 210796 kb
Host smart-65ce28e7-a50a-4470-bbfa-9ee480048cdf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570954655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1570954655
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1523113988
Short name T130
Test name
Test status
Simulation time 5249943355 ps
CPU time 55.4 seconds
Started Jul 01 11:05:18 AM PDT 24
Finished Jul 01 11:06:14 AM PDT 24
Peak memory 216664 kb
Host smart-ea498cc0-26f2-474e-8132-5ca3f17142d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523113988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1523113988
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3304217305
Short name T10
Test name
Test status
Simulation time 22702242482 ps
CPU time 33.31 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:05:05 AM PDT 24
Peak memory 212296 kb
Host smart-108a03f7-0388-44dc-9b83-9b22c7f90b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304217305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3304217305
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2190929002
Short name T37
Test name
Test status
Simulation time 82973383920 ps
CPU time 3107.74 seconds
Started Jul 01 11:04:32 AM PDT 24
Finished Jul 01 11:56:21 AM PDT 24
Peak memory 244764 kb
Host smart-1ce2e7f0-a899-4af4-a629-7c0e7174e053
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190929002 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2190929002
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2160410476
Short name T94
Test name
Test status
Simulation time 4807663259 ps
CPU time 42.68 seconds
Started Jul 01 10:43:55 AM PDT 24
Finished Jul 01 10:44:42 AM PDT 24
Peak memory 211240 kb
Host smart-3cfd3584-090d-4a19-9885-77b533f38a14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160410476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2160410476
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.185335360
Short name T56
Test name
Test status
Simulation time 2222409819 ps
CPU time 10.74 seconds
Started Jul 01 11:03:49 AM PDT 24
Finished Jul 01 11:04:00 AM PDT 24
Peak memory 211604 kb
Host smart-53ecd67a-7f4a-4328-a736-4b2a4f196c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185335360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.185335360
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.589971399
Short name T73
Test name
Test status
Simulation time 32485039771 ps
CPU time 75.5 seconds
Started Jul 01 10:44:31 AM PDT 24
Finished Jul 01 10:45:47 AM PDT 24
Peak memory 217760 kb
Host smart-791a6192-53d5-4c4c-baef-d24b3305ca2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589971399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.589971399
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1155301592
Short name T29
Test name
Test status
Simulation time 10670080536 ps
CPU time 178.25 seconds
Started Jul 01 11:04:35 AM PDT 24
Finished Jul 01 11:07:34 AM PDT 24
Peak memory 238460 kb
Host smart-cff91a75-73ee-4a26-88cd-9e59bc91b926
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155301592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1155301592
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1883064446
Short name T222
Test name
Test status
Simulation time 177041752 ps
CPU time 9.65 seconds
Started Jul 01 11:03:49 AM PDT 24
Finished Jul 01 11:04:01 AM PDT 24
Peak memory 211984 kb
Host smart-b081c599-76f7-484d-a661-bdcf7540dbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883064446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1883064446
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1500926834
Short name T99
Test name
Test status
Simulation time 172027676 ps
CPU time 38.18 seconds
Started Jul 01 10:43:53 AM PDT 24
Finished Jul 01 10:44:33 AM PDT 24
Peak memory 212020 kb
Host smart-8b73dad0-124b-4d42-940f-670fb5a433a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500926834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1500926834
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2756547015
Short name T93
Test name
Test status
Simulation time 704727027 ps
CPU time 36.22 seconds
Started Jul 01 10:44:00 AM PDT 24
Finished Jul 01 10:44:38 AM PDT 24
Peak memory 218928 kb
Host smart-87025952-efaa-4c4d-bc4e-42e8f77e31bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756547015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2756547015
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2982903434
Short name T36
Test name
Test status
Simulation time 142811743838 ps
CPU time 1354.13 seconds
Started Jul 01 11:04:42 AM PDT 24
Finished Jul 01 11:27:17 AM PDT 24
Peak memory 235852 kb
Host smart-972e321d-8c53-4d47-9bb3-c322a44addd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982903434 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2982903434
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1555199550
Short name T210
Test name
Test status
Simulation time 1070923095 ps
CPU time 65.52 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:05:35 AM PDT 24
Peak memory 228032 kb
Host smart-8f686f3f-b5bf-41d9-8f73-a6a260674da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555199550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1555199550
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1774867400
Short name T413
Test name
Test status
Simulation time 1958371984 ps
CPU time 15.92 seconds
Started Jul 01 10:44:11 AM PDT 24
Finished Jul 01 10:44:28 AM PDT 24
Peak memory 218328 kb
Host smart-c910501d-2aa1-4509-b638-cd005a9315ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774867400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1774867400
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3228365780
Short name T367
Test name
Test status
Simulation time 330259790 ps
CPU time 6.58 seconds
Started Jul 01 10:43:59 AM PDT 24
Finished Jul 01 10:44:09 AM PDT 24
Peak memory 210568 kb
Host smart-3759722a-ef8e-4160-a7ff-e976c60d6f28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228365780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3228365780
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1912289262
Short name T447
Test name
Test status
Simulation time 92006820 ps
CPU time 7.31 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:44:08 AM PDT 24
Peak memory 210632 kb
Host smart-f2649963-140c-4631-ad13-71d3bcf063e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912289262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1912289262
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2805685791
Short name T424
Test name
Test status
Simulation time 5726657897 ps
CPU time 8.85 seconds
Started Jul 01 10:43:44 AM PDT 24
Finished Jul 01 10:43:53 AM PDT 24
Peak memory 219028 kb
Host smart-558fb704-783e-4616-8104-1affa1526ab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805685791 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2805685791
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.457334651
Short name T88
Test name
Test status
Simulation time 8215712184 ps
CPU time 11.54 seconds
Started Jul 01 10:43:48 AM PDT 24
Finished Jul 01 10:44:00 AM PDT 24
Peak memory 210760 kb
Host smart-bc828408-416c-4c15-ba60-d3a5f4002d83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457334651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.457334651
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3185134367
Short name T432
Test name
Test status
Simulation time 87584177 ps
CPU time 4.11 seconds
Started Jul 01 10:44:02 AM PDT 24
Finished Jul 01 10:44:07 AM PDT 24
Peak memory 210388 kb
Host smart-f488db56-f32c-46b9-9e8a-6001c2b93d2f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185134367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3185134367
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3327734907
Short name T368
Test name
Test status
Simulation time 5290059870 ps
CPU time 11.83 seconds
Started Jul 01 10:43:53 AM PDT 24
Finished Jul 01 10:44:06 AM PDT 24
Peak memory 210628 kb
Host smart-fb612d50-7713-4de7-b79f-3812afa34b5a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327734907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3327734907
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2078579553
Short name T437
Test name
Test status
Simulation time 29455386976 ps
CPU time 59.67 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:45:00 AM PDT 24
Peak memory 210688 kb
Host smart-2fb549d4-e357-4636-b05c-52dbbf3870f2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078579553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2078579553
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2907678434
Short name T82
Test name
Test status
Simulation time 5395484801 ps
CPU time 11.92 seconds
Started Jul 01 10:44:15 AM PDT 24
Finished Jul 01 10:44:27 AM PDT 24
Peak memory 218824 kb
Host smart-6ab0eb28-4e3f-4aab-ad5c-879920b70473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907678434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2907678434
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1322110602
Short name T372
Test name
Test status
Simulation time 1152358983 ps
CPU time 10.07 seconds
Started Jul 01 10:43:47 AM PDT 24
Finished Jul 01 10:43:57 AM PDT 24
Peak memory 218892 kb
Host smart-73684461-c3ae-47cc-8033-d5f5b39b9919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322110602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1322110602
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3520833784
Short name T96
Test name
Test status
Simulation time 8017881711 ps
CPU time 42.51 seconds
Started Jul 01 10:43:53 AM PDT 24
Finished Jul 01 10:44:37 AM PDT 24
Peak memory 218996 kb
Host smart-cb6747ff-0e55-44e6-a5c0-9ebd4b0baca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520833784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3520833784
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2177148434
Short name T450
Test name
Test status
Simulation time 4879275842 ps
CPU time 15.88 seconds
Started Jul 01 10:43:47 AM PDT 24
Finished Jul 01 10:44:04 AM PDT 24
Peak memory 218844 kb
Host smart-c480988f-d354-4127-9860-e98f5de8be1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177148434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2177148434
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1209005709
Short name T458
Test name
Test status
Simulation time 593951847 ps
CPU time 7.9 seconds
Started Jul 01 10:43:54 AM PDT 24
Finished Jul 01 10:44:04 AM PDT 24
Peak memory 210728 kb
Host smart-f490bf3a-a315-4bf0-9d47-818210cc89f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209005709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1209005709
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.514415224
Short name T422
Test name
Test status
Simulation time 2753202897 ps
CPU time 13.52 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:44:15 AM PDT 24
Peak memory 210696 kb
Host smart-8544d0dd-5f01-407c-b433-5354f23ba5ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514415224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.514415224
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.143405322
Short name T371
Test name
Test status
Simulation time 9376723094 ps
CPU time 17.45 seconds
Started Jul 01 10:43:49 AM PDT 24
Finished Jul 01 10:44:07 AM PDT 24
Peak memory 218948 kb
Host smart-0209f4ef-b789-47dd-86ea-55172dca553e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143405322 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.143405322
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1948758438
Short name T434
Test name
Test status
Simulation time 302045879 ps
CPU time 6.11 seconds
Started Jul 01 10:43:50 AM PDT 24
Finished Jul 01 10:43:56 AM PDT 24
Peak memory 217604 kb
Host smart-5cebfa0e-4410-45bc-97fc-a29c4563f017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948758438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1948758438
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1217522859
Short name T445
Test name
Test status
Simulation time 6717576084 ps
CPU time 13.88 seconds
Started Jul 01 10:44:07 AM PDT 24
Finished Jul 01 10:44:22 AM PDT 24
Peak memory 210532 kb
Host smart-d871a83c-58d3-46a4-bc1e-7974b4aef622
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217522859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1217522859
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.930862785
Short name T380
Test name
Test status
Simulation time 1113985091 ps
CPU time 10.8 seconds
Started Jul 01 10:43:46 AM PDT 24
Finished Jul 01 10:43:57 AM PDT 24
Peak memory 210428 kb
Host smart-37d9f188-50d2-4b9d-9b01-501e228c1e51
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930862785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
930862785
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1407424875
Short name T54
Test name
Test status
Simulation time 726868083 ps
CPU time 19.4 seconds
Started Jul 01 10:43:48 AM PDT 24
Finished Jul 01 10:44:08 AM PDT 24
Peak memory 210708 kb
Host smart-fa5428c3-6045-4e98-943e-1517d86e2706
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407424875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1407424875
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1852557471
Short name T391
Test name
Test status
Simulation time 85661285 ps
CPU time 4.36 seconds
Started Jul 01 10:43:50 AM PDT 24
Finished Jul 01 10:43:55 AM PDT 24
Peak memory 210592 kb
Host smart-37b5fab7-7443-4f84-9513-e5ecc4ff6fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852557471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1852557471
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.253089110
Short name T448
Test name
Test status
Simulation time 727239732 ps
CPU time 11.89 seconds
Started Jul 01 10:43:55 AM PDT 24
Finished Jul 01 10:44:10 AM PDT 24
Peak memory 218888 kb
Host smart-3fc6fbc7-7736-4f3a-8388-3408f3103c90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253089110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.253089110
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3245815270
Short name T385
Test name
Test status
Simulation time 2053420557 ps
CPU time 38.02 seconds
Started Jul 01 10:43:44 AM PDT 24
Finished Jul 01 10:44:22 AM PDT 24
Peak memory 218908 kb
Host smart-572a7e29-93c8-46b3-b151-6ee99e77b89a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245815270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3245815270
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1454561289
Short name T402
Test name
Test status
Simulation time 196272061 ps
CPU time 5.54 seconds
Started Jul 01 10:44:07 AM PDT 24
Finished Jul 01 10:44:14 AM PDT 24
Peak memory 219012 kb
Host smart-c8cc5640-6050-4ba5-a986-8221ab12a87f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454561289 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1454561289
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.247241657
Short name T451
Test name
Test status
Simulation time 334305396 ps
CPU time 6.57 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:44:07 AM PDT 24
Peak memory 210724 kb
Host smart-4b000a85-0ab1-4665-8237-8397cafdfea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247241657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.247241657
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.793458641
Short name T89
Test name
Test status
Simulation time 4810055052 ps
CPU time 45.98 seconds
Started Jul 01 10:44:04 AM PDT 24
Finished Jul 01 10:44:50 AM PDT 24
Peak memory 210792 kb
Host smart-8cbf2b0f-533a-47b0-9a02-83a1a8e60a3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793458641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.793458641
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.830633883
Short name T65
Test name
Test status
Simulation time 5131506742 ps
CPU time 13.55 seconds
Started Jul 01 10:44:08 AM PDT 24
Finished Jul 01 10:44:23 AM PDT 24
Peak memory 218312 kb
Host smart-72765cc2-50da-4636-bb24-7c62f044b694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830633883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.830633883
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1969361045
Short name T393
Test name
Test status
Simulation time 8589702574 ps
CPU time 18.49 seconds
Started Jul 01 10:44:59 AM PDT 24
Finished Jul 01 10:45:18 AM PDT 24
Peak memory 216992 kb
Host smart-26577bea-820f-40dc-94f7-a6db5825254a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969361045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1969361045
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1846004823
Short name T102
Test name
Test status
Simulation time 1418865366 ps
CPU time 43.1 seconds
Started Jul 01 10:44:21 AM PDT 24
Finished Jul 01 10:45:05 AM PDT 24
Peak memory 218936 kb
Host smart-db04cf12-530a-474f-803c-de1cc7b40cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846004823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1846004823
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.773827122
Short name T383
Test name
Test status
Simulation time 2178440758 ps
CPU time 7.88 seconds
Started Jul 01 10:44:11 AM PDT 24
Finished Jul 01 10:44:19 AM PDT 24
Peak memory 218864 kb
Host smart-cc1dbde6-2b26-4c5f-a4f6-84c511247da9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773827122 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.773827122
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1204805514
Short name T66
Test name
Test status
Simulation time 85821677 ps
CPU time 4.1 seconds
Started Jul 01 10:44:06 AM PDT 24
Finished Jul 01 10:44:11 AM PDT 24
Peak memory 210700 kb
Host smart-c60b2932-1eac-429a-88f6-1aae81826b56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204805514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1204805514
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.444457946
Short name T414
Test name
Test status
Simulation time 372157398 ps
CPU time 19.17 seconds
Started Jul 01 10:43:55 AM PDT 24
Finished Jul 01 10:44:18 AM PDT 24
Peak memory 210668 kb
Host smart-bac90e36-3b6e-453c-9d30-d31f194b1411
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444457946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.444457946
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2013823039
Short name T418
Test name
Test status
Simulation time 2621138781 ps
CPU time 12.34 seconds
Started Jul 01 10:44:19 AM PDT 24
Finished Jul 01 10:44:32 AM PDT 24
Peak memory 218880 kb
Host smart-3432006d-bc10-4ce5-b9e2-38acdf0361b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013823039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2013823039
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4084161529
Short name T370
Test name
Test status
Simulation time 1768946088 ps
CPU time 16.39 seconds
Started Jul 01 10:44:20 AM PDT 24
Finished Jul 01 10:44:47 AM PDT 24
Peak memory 218804 kb
Host smart-2bf02829-9dbd-4049-8223-2afc9b619452
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084161529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4084161529
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1170042866
Short name T91
Test name
Test status
Simulation time 286335916 ps
CPU time 71.15 seconds
Started Jul 01 10:43:59 AM PDT 24
Finished Jul 01 10:45:13 AM PDT 24
Peak memory 211420 kb
Host smart-3941d869-1251-48a1-a211-e44f9ba2e276
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170042866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1170042866
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4024637591
Short name T454
Test name
Test status
Simulation time 1354633136 ps
CPU time 12.25 seconds
Started Jul 01 10:43:55 AM PDT 24
Finished Jul 01 10:44:10 AM PDT 24
Peak memory 219024 kb
Host smart-f8d74ec8-e14b-4836-addb-58e42a76dd96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024637591 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4024637591
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2534324894
Short name T86
Test name
Test status
Simulation time 1060182691 ps
CPU time 7.73 seconds
Started Jul 01 10:44:03 AM PDT 24
Finished Jul 01 10:44:11 AM PDT 24
Peak memory 217500 kb
Host smart-852a7b05-bce9-45fb-bb7c-0e86f86832a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534324894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2534324894
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3845442315
Short name T459
Test name
Test status
Simulation time 2498732148 ps
CPU time 7.3 seconds
Started Jul 01 10:43:54 AM PDT 24
Finished Jul 01 10:44:03 AM PDT 24
Peak memory 218276 kb
Host smart-dd4f1629-67e3-4c89-a7ca-8d391b61886f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845442315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3845442315
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1863891054
Short name T399
Test name
Test status
Simulation time 8523124296 ps
CPU time 20.16 seconds
Started Jul 01 10:44:19 AM PDT 24
Finished Jul 01 10:44:40 AM PDT 24
Peak memory 218904 kb
Host smart-05776f28-f296-47f2-8a36-646a3bd1c09b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863891054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1863891054
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1615955249
Short name T51
Test name
Test status
Simulation time 1035641893 ps
CPU time 39.72 seconds
Started Jul 01 10:43:50 AM PDT 24
Finished Jul 01 10:44:31 AM PDT 24
Peak memory 218872 kb
Host smart-74c6c31d-80a1-42db-bcdd-ebf7058047eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615955249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1615955249
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2476389213
Short name T442
Test name
Test status
Simulation time 1073816792 ps
CPU time 10.23 seconds
Started Jul 01 10:44:59 AM PDT 24
Finished Jul 01 10:45:10 AM PDT 24
Peak memory 217044 kb
Host smart-143784dc-9d35-474f-9d72-d571cc330a3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476389213 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2476389213
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2692656939
Short name T429
Test name
Test status
Simulation time 37553741303 ps
CPU time 15.52 seconds
Started Jul 01 10:44:06 AM PDT 24
Finished Jul 01 10:44:22 AM PDT 24
Peak memory 218908 kb
Host smart-b661c168-6194-4cd7-855a-e6d81ca23883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692656939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2692656939
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2408498886
Short name T401
Test name
Test status
Simulation time 2642034336 ps
CPU time 35.4 seconds
Started Jul 01 10:44:00 AM PDT 24
Finished Jul 01 10:44:38 AM PDT 24
Peak memory 210756 kb
Host smart-47a798d6-4651-4071-a0d4-02f700789517
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408498886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2408498886
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3743886298
Short name T430
Test name
Test status
Simulation time 417144024 ps
CPU time 4.06 seconds
Started Jul 01 10:44:59 AM PDT 24
Finished Jul 01 10:45:04 AM PDT 24
Peak memory 216320 kb
Host smart-e69a3cfd-eeb0-4b7a-81fc-aeeb412423e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743886298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3743886298
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2238786972
Short name T398
Test name
Test status
Simulation time 1430541920 ps
CPU time 14.92 seconds
Started Jul 01 10:44:13 AM PDT 24
Finished Jul 01 10:44:29 AM PDT 24
Peak memory 218960 kb
Host smart-6a4f5c0d-b7c6-4d8c-905c-4ef1af28eae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238786972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2238786972
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2046848462
Short name T446
Test name
Test status
Simulation time 3975777829 ps
CPU time 9.73 seconds
Started Jul 01 10:44:21 AM PDT 24
Finished Jul 01 10:44:32 AM PDT 24
Peak memory 219088 kb
Host smart-6ace9099-d076-4d35-9a73-2ed0879b7931
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046848462 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2046848462
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3601679027
Short name T431
Test name
Test status
Simulation time 1841852105 ps
CPU time 10.36 seconds
Started Jul 01 10:45:21 AM PDT 24
Finished Jul 01 10:45:32 AM PDT 24
Peak memory 210524 kb
Host smart-f8096d21-b522-4c84-a62c-849614b9a90e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601679027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3601679027
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2426689663
Short name T389
Test name
Test status
Simulation time 4948115445 ps
CPU time 31.55 seconds
Started Jul 01 10:44:59 AM PDT 24
Finished Jul 01 10:45:31 AM PDT 24
Peak memory 210156 kb
Host smart-cc72a85d-eb5a-43a7-8e22-5b1c1aa4afd5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426689663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2426689663
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3458667673
Short name T457
Test name
Test status
Simulation time 427452794 ps
CPU time 5.84 seconds
Started Jul 01 10:44:08 AM PDT 24
Finished Jul 01 10:44:15 AM PDT 24
Peak memory 210772 kb
Host smart-8393a27c-9437-44a9-845e-53a060762c84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458667673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3458667673
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2105956340
Short name T396
Test name
Test status
Simulation time 6851312500 ps
CPU time 16.57 seconds
Started Jul 01 10:45:33 AM PDT 24
Finished Jul 01 10:45:49 AM PDT 24
Peak memory 218828 kb
Host smart-1408dd90-27c0-4fb4-9438-a1297933990f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105956340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2105956340
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.356830014
Short name T97
Test name
Test status
Simulation time 2866937103 ps
CPU time 43.43 seconds
Started Jul 01 10:43:53 AM PDT 24
Finished Jul 01 10:44:39 AM PDT 24
Peak memory 219008 kb
Host smart-4c208117-e65b-448d-8b58-84865c33ee71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356830014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.356830014
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.83295645
Short name T376
Test name
Test status
Simulation time 7588831775 ps
CPU time 14.39 seconds
Started Jul 01 10:44:27 AM PDT 24
Finished Jul 01 10:44:44 AM PDT 24
Peak memory 218832 kb
Host smart-3b670277-5029-458f-8c1e-7eca14e782b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83295645 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.83295645
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1650871076
Short name T379
Test name
Test status
Simulation time 90811754 ps
CPU time 4.3 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:44:06 AM PDT 24
Peak memory 210696 kb
Host smart-5600e474-cae6-4daf-a469-c45aa0c6d9df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650871076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1650871076
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4201875290
Short name T456
Test name
Test status
Simulation time 5261778593 ps
CPU time 32.29 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:44:34 AM PDT 24
Peak memory 218912 kb
Host smart-8358b6ad-4c32-4f12-9707-cbee426e9fc7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201875290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4201875290
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1932324541
Short name T423
Test name
Test status
Simulation time 139892445 ps
CPU time 6.91 seconds
Started Jul 01 10:44:07 AM PDT 24
Finished Jul 01 10:44:16 AM PDT 24
Peak memory 218128 kb
Host smart-fced6158-ef1e-46b8-ad4a-72b4f29f4a3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932324541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1932324541
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.473881115
Short name T427
Test name
Test status
Simulation time 21640412594 ps
CPU time 15.44 seconds
Started Jul 01 10:44:01 AM PDT 24
Finished Jul 01 10:44:18 AM PDT 24
Peak memory 219024 kb
Host smart-365f78d2-86a2-4774-a9b6-0f748e6bbad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473881115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.473881115
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2001218229
Short name T415
Test name
Test status
Simulation time 346877848 ps
CPU time 40.09 seconds
Started Jul 01 10:44:32 AM PDT 24
Finished Jul 01 10:45:12 AM PDT 24
Peak memory 218804 kb
Host smart-c2eec36b-3055-4d39-bc05-3fd61b2f2175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001218229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2001218229
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1689333736
Short name T419
Test name
Test status
Simulation time 1576049752 ps
CPU time 13.88 seconds
Started Jul 01 10:43:52 AM PDT 24
Finished Jul 01 10:44:07 AM PDT 24
Peak memory 219016 kb
Host smart-332f3a44-7184-4738-86fc-924a84e12500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689333736 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1689333736
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3560986593
Short name T436
Test name
Test status
Simulation time 656943638 ps
CPU time 7.96 seconds
Started Jul 01 10:44:07 AM PDT 24
Finished Jul 01 10:44:16 AM PDT 24
Peak memory 217684 kb
Host smart-2c7a4731-7061-413a-a35f-5e8ea9e529e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560986593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3560986593
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3676626046
Short name T53
Test name
Test status
Simulation time 32849497750 ps
CPU time 62.99 seconds
Started Jul 01 10:44:20 AM PDT 24
Finished Jul 01 10:45:24 AM PDT 24
Peak memory 210764 kb
Host smart-ecd9364b-fbb1-4ab6-9a67-86764075e663
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676626046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3676626046
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1197316185
Short name T84
Test name
Test status
Simulation time 2376864289 ps
CPU time 8.09 seconds
Started Jul 01 10:44:30 AM PDT 24
Finished Jul 01 10:44:38 AM PDT 24
Peak memory 218404 kb
Host smart-ee481aa4-9af7-4577-822d-d4de1b397e7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197316185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1197316185
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2831549147
Short name T421
Test name
Test status
Simulation time 6198128373 ps
CPU time 11.88 seconds
Started Jul 01 10:44:04 AM PDT 24
Finished Jul 01 10:44:16 AM PDT 24
Peak memory 219096 kb
Host smart-7b65de0b-d321-4f7e-a65d-6a4b1b6387de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831549147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2831549147
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.314423743
Short name T104
Test name
Test status
Simulation time 293298456 ps
CPU time 39.04 seconds
Started Jul 01 10:43:59 AM PDT 24
Finished Jul 01 10:44:41 AM PDT 24
Peak memory 211128 kb
Host smart-19835c7c-fc0f-4fef-a0bf-c20aae1fb0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314423743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.314423743
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1924152109
Short name T395
Test name
Test status
Simulation time 1573047732 ps
CPU time 9.79 seconds
Started Jul 01 10:44:05 AM PDT 24
Finished Jul 01 10:44:15 AM PDT 24
Peak memory 219000 kb
Host smart-c9172adc-a710-4999-9c5f-83af2a87d817
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924152109 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1924152109
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1700176206
Short name T373
Test name
Test status
Simulation time 552480336 ps
CPU time 7.77 seconds
Started Jul 01 10:44:08 AM PDT 24
Finished Jul 01 10:44:17 AM PDT 24
Peak memory 210608 kb
Host smart-6f0b2714-ddf7-4b9e-a5fd-f6e49d1dd50f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700176206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1700176206
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2492558215
Short name T76
Test name
Test status
Simulation time 47606348705 ps
CPU time 40.64 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:44:42 AM PDT 24
Peak memory 210680 kb
Host smart-1e95880d-8d3f-4b5f-97be-655eb86732e4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492558215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2492558215
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.385910770
Short name T67
Test name
Test status
Simulation time 5860838901 ps
CPU time 13.05 seconds
Started Jul 01 10:44:11 AM PDT 24
Finished Jul 01 10:44:24 AM PDT 24
Peak memory 218956 kb
Host smart-dd9579bc-cc41-4939-8337-695641c3cd45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385910770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.385910770
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3815841816
Short name T390
Test name
Test status
Simulation time 501076766 ps
CPU time 10.48 seconds
Started Jul 01 10:44:28 AM PDT 24
Finished Jul 01 10:44:39 AM PDT 24
Peak memory 218940 kb
Host smart-713012a3-5bba-4158-9563-66c893230fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815841816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3815841816
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.179230918
Short name T100
Test name
Test status
Simulation time 501353814 ps
CPU time 70.15 seconds
Started Jul 01 10:43:54 AM PDT 24
Finished Jul 01 10:45:06 AM PDT 24
Peak memory 218908 kb
Host smart-56ff7cb1-8230-4a6d-9c66-10b1b6a3ddd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179230918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.179230918
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3711642507
Short name T462
Test name
Test status
Simulation time 349576293 ps
CPU time 4.95 seconds
Started Jul 01 10:44:35 AM PDT 24
Finished Jul 01 10:44:42 AM PDT 24
Peak memory 218860 kb
Host smart-652d3ea1-b890-4795-91d4-790d861d4512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711642507 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3711642507
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2577600926
Short name T68
Test name
Test status
Simulation time 4927754391 ps
CPU time 11.3 seconds
Started Jul 01 10:44:05 AM PDT 24
Finished Jul 01 10:44:16 AM PDT 24
Peak memory 210612 kb
Host smart-c6077a9c-6a2a-4378-b8e5-b40b640fc27a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577600926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2577600926
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3487216267
Short name T77
Test name
Test status
Simulation time 6070098644 ps
CPU time 60.28 seconds
Started Jul 01 10:44:25 AM PDT 24
Finished Jul 01 10:45:31 AM PDT 24
Peak memory 210760 kb
Host smart-d284d173-2aa6-4f76-b153-652148195183
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487216267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3487216267
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3729922547
Short name T438
Test name
Test status
Simulation time 5322597156 ps
CPU time 14.31 seconds
Started Jul 01 10:44:14 AM PDT 24
Finished Jul 01 10:44:29 AM PDT 24
Peak memory 218884 kb
Host smart-2c106480-cd83-4064-ab65-9e819a241da9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729922547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3729922547
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3956450937
Short name T365
Test name
Test status
Simulation time 1834274775 ps
CPU time 19.5 seconds
Started Jul 01 10:44:26 AM PDT 24
Finished Jul 01 10:44:47 AM PDT 24
Peak memory 218892 kb
Host smart-fc84b662-6be4-4e7d-b418-6499ace32301
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956450937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3956450937
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.122328090
Short name T103
Test name
Test status
Simulation time 1075570205 ps
CPU time 41.48 seconds
Started Jul 01 10:44:27 AM PDT 24
Finished Jul 01 10:45:09 AM PDT 24
Peak memory 211992 kb
Host smart-2bd62544-5a56-4acd-9153-482c4fcdb0c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122328090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.122328090
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3591581432
Short name T394
Test name
Test status
Simulation time 1247736990 ps
CPU time 11.08 seconds
Started Jul 01 10:44:23 AM PDT 24
Finished Jul 01 10:44:34 AM PDT 24
Peak memory 219012 kb
Host smart-77eacacc-09c4-4e85-8bed-b358f9af41e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591581432 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3591581432
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1113832279
Short name T81
Test name
Test status
Simulation time 2204999396 ps
CPU time 12.93 seconds
Started Jul 01 10:44:17 AM PDT 24
Finished Jul 01 10:44:30 AM PDT 24
Peak memory 218444 kb
Host smart-a495b044-c5a6-4223-80a9-1b604652dc5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113832279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1113832279
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.101608547
Short name T455
Test name
Test status
Simulation time 66300933055 ps
CPU time 61.05 seconds
Started Jul 01 10:44:30 AM PDT 24
Finished Jul 01 10:45:31 AM PDT 24
Peak memory 210716 kb
Host smart-a9df3794-579b-4465-8bff-42fca5fa34d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101608547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.101608547
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3326790131
Short name T386
Test name
Test status
Simulation time 4398188429 ps
CPU time 10.88 seconds
Started Jul 01 10:44:37 AM PDT 24
Finished Jul 01 10:44:49 AM PDT 24
Peak memory 210776 kb
Host smart-ddea8fb1-0f63-4eaf-a371-c368c1070be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326790131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3326790131
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.232334280
Short name T449
Test name
Test status
Simulation time 7016533527 ps
CPU time 17.37 seconds
Started Jul 01 10:44:28 AM PDT 24
Finished Jul 01 10:44:46 AM PDT 24
Peak memory 218968 kb
Host smart-be2221ca-256c-480d-b346-2b9279567fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232334280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.232334280
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.546460221
Short name T101
Test name
Test status
Simulation time 2568169827 ps
CPU time 39.61 seconds
Started Jul 01 10:44:08 AM PDT 24
Finished Jul 01 10:44:49 AM PDT 24
Peak memory 218972 kb
Host smart-9ec267bc-fe54-4b24-b119-35abe9cc6aff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546460221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.546460221
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2750242787
Short name T80
Test name
Test status
Simulation time 1225413345 ps
CPU time 10.82 seconds
Started Jul 01 10:43:51 AM PDT 24
Finished Jul 01 10:44:02 AM PDT 24
Peak memory 210720 kb
Host smart-d20206e0-aee5-48ad-b8c6-d6a7ecc185cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750242787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2750242787
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.251120645
Short name T417
Test name
Test status
Simulation time 541541134 ps
CPU time 7.77 seconds
Started Jul 01 10:43:55 AM PDT 24
Finished Jul 01 10:44:06 AM PDT 24
Peak memory 217552 kb
Host smart-e63e8637-8a6c-4f90-bc76-1349625f2685
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251120645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.251120645
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1078872732
Short name T433
Test name
Test status
Simulation time 1561560018 ps
CPU time 16.22 seconds
Started Jul 01 10:43:51 AM PDT 24
Finished Jul 01 10:44:08 AM PDT 24
Peak memory 210692 kb
Host smart-144bc406-99f4-4e69-9e8c-e117a0eb1549
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078872732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1078872732
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4100048941
Short name T374
Test name
Test status
Simulation time 454588040 ps
CPU time 6.81 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:44:08 AM PDT 24
Peak memory 218840 kb
Host smart-d3f1b764-8d18-4437-8631-5210462abf16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100048941 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4100048941
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2284527937
Short name T384
Test name
Test status
Simulation time 6576041418 ps
CPU time 13.18 seconds
Started Jul 01 10:44:02 AM PDT 24
Finished Jul 01 10:44:16 AM PDT 24
Peak memory 217692 kb
Host smart-e1b393a6-995d-4151-9a93-26e0e7fabb3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284527937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2284527937
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2602931278
Short name T420
Test name
Test status
Simulation time 334044365 ps
CPU time 5.99 seconds
Started Jul 01 10:43:52 AM PDT 24
Finished Jul 01 10:43:59 AM PDT 24
Peak memory 210592 kb
Host smart-15460b0e-3bd6-4534-91e3-be80000e8ec3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602931278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2602931278
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2502771768
Short name T366
Test name
Test status
Simulation time 1146509330 ps
CPU time 7.99 seconds
Started Jul 01 10:43:52 AM PDT 24
Finished Jul 01 10:44:01 AM PDT 24
Peak memory 210592 kb
Host smart-41b33d32-0ada-4657-a8be-1829f94d34cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502771768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2502771768
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1258702101
Short name T406
Test name
Test status
Simulation time 44746006558 ps
CPU time 82.53 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:45:23 AM PDT 24
Peak memory 210772 kb
Host smart-577caedc-96a2-4a8a-94d7-8b767182d7aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258702101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1258702101
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2968623415
Short name T411
Test name
Test status
Simulation time 6311462426 ps
CPU time 9.12 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:44:11 AM PDT 24
Peak memory 210824 kb
Host smart-808b502e-bf95-42d3-8b6e-a0890541a88b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968623415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2968623415
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.508308801
Short name T392
Test name
Test status
Simulation time 4311040071 ps
CPU time 11.42 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:44:13 AM PDT 24
Peak memory 218996 kb
Host smart-39fb352f-e142-4a87-9ab4-165832a7c09c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508308801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.508308801
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2791915352
Short name T98
Test name
Test status
Simulation time 15175094691 ps
CPU time 45.01 seconds
Started Jul 01 10:43:56 AM PDT 24
Finished Jul 01 10:44:44 AM PDT 24
Peak memory 212372 kb
Host smart-a82d1ef9-fc86-46bd-9ce1-2d70b37d4fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791915352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2791915352
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2430655592
Short name T87
Test name
Test status
Simulation time 32563191407 ps
CPU time 18.14 seconds
Started Jul 01 10:43:52 AM PDT 24
Finished Jul 01 10:44:12 AM PDT 24
Peak memory 210728 kb
Host smart-b7e8c84d-cff6-4061-bcd4-fa7e2d8266c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430655592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2430655592
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.825797294
Short name T378
Test name
Test status
Simulation time 1895509680 ps
CPU time 15.25 seconds
Started Jul 01 10:43:50 AM PDT 24
Finished Jul 01 10:44:06 AM PDT 24
Peak memory 210676 kb
Host smart-ea735d79-2f44-4a63-935d-ad5eb832439b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825797294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.825797294
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2207991518
Short name T75
Test name
Test status
Simulation time 1281138000 ps
CPU time 12.72 seconds
Started Jul 01 10:44:12 AM PDT 24
Finished Jul 01 10:44:26 AM PDT 24
Peak memory 210636 kb
Host smart-73c30489-5585-41d4-9d01-924ec96ae11e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207991518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2207991518
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3742655835
Short name T441
Test name
Test status
Simulation time 1780675902 ps
CPU time 15.02 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:44:17 AM PDT 24
Peak memory 218980 kb
Host smart-c9dbe264-6ca2-44ed-9566-8f5ae654fbc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742655835 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3742655835
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2080785827
Short name T408
Test name
Test status
Simulation time 89829795 ps
CPU time 4.31 seconds
Started Jul 01 10:43:56 AM PDT 24
Finished Jul 01 10:44:05 AM PDT 24
Peak memory 210616 kb
Host smart-9c53ca9d-0216-4e2c-ae8c-cd0b2680d341
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080785827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2080785827
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.552372577
Short name T397
Test name
Test status
Simulation time 1484318378 ps
CPU time 7.72 seconds
Started Jul 01 10:43:49 AM PDT 24
Finished Jul 01 10:43:57 AM PDT 24
Peak memory 210532 kb
Host smart-9a7d2153-3ae0-4c29-bdb3-81e980ff9255
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552372577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.552372577
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1710349961
Short name T452
Test name
Test status
Simulation time 22020343418 ps
CPU time 11.24 seconds
Started Jul 01 10:43:52 AM PDT 24
Finished Jul 01 10:44:04 AM PDT 24
Peak memory 210580 kb
Host smart-f646e3d1-9f5f-403a-9848-f33acedeaac4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710349961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1710349961
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.494471730
Short name T425
Test name
Test status
Simulation time 17850650968 ps
CPU time 43.01 seconds
Started Jul 01 10:44:56 AM PDT 24
Finished Jul 01 10:45:40 AM PDT 24
Peak memory 210764 kb
Host smart-efc82b21-fad5-45d6-850b-07a996f9b3da
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494471730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.494471730
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2057820203
Short name T85
Test name
Test status
Simulation time 1031840892 ps
CPU time 10.13 seconds
Started Jul 01 10:44:04 AM PDT 24
Finished Jul 01 10:44:15 AM PDT 24
Peak memory 210536 kb
Host smart-37897a93-46c2-4632-a788-ce1481a7c6f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057820203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2057820203
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1528948000
Short name T405
Test name
Test status
Simulation time 584312641 ps
CPU time 8.02 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:44:09 AM PDT 24
Peak memory 218892 kb
Host smart-2d1e8bda-ffd3-40cc-a28c-0407c1b409bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528948000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1528948000
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1357179891
Short name T78
Test name
Test status
Simulation time 6062215037 ps
CPU time 11.98 seconds
Started Jul 01 10:44:04 AM PDT 24
Finished Jul 01 10:44:16 AM PDT 24
Peak memory 218848 kb
Host smart-9ebce475-c63b-4f26-9678-4a22d4242168
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357179891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1357179891
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1148635574
Short name T369
Test name
Test status
Simulation time 1155865051 ps
CPU time 6.8 seconds
Started Jul 01 10:44:03 AM PDT 24
Finished Jul 01 10:44:11 AM PDT 24
Peak memory 217516 kb
Host smart-fb05c3ed-6a92-4e9e-98e9-b48ed0ce8e88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148635574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1148635574
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.939607132
Short name T55
Test name
Test status
Simulation time 1510482569 ps
CPU time 14.16 seconds
Started Jul 01 10:44:00 AM PDT 24
Finished Jul 01 10:44:16 AM PDT 24
Peak memory 218512 kb
Host smart-95ee4f02-e8ec-473f-9f5a-602f227e0f5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939607132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.939607132
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3469805429
Short name T453
Test name
Test status
Simulation time 2206191135 ps
CPU time 10.35 seconds
Started Jul 01 10:44:12 AM PDT 24
Finished Jul 01 10:44:23 AM PDT 24
Peak memory 218948 kb
Host smart-8db8fd36-c958-49dc-beb8-20d8eb0af692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469805429 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3469805429
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3029840264
Short name T444
Test name
Test status
Simulation time 676746790 ps
CPU time 8.22 seconds
Started Jul 01 10:44:15 AM PDT 24
Finished Jul 01 10:44:24 AM PDT 24
Peak memory 210720 kb
Host smart-116e615f-f88b-47ba-81b0-04eb4213b713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029840264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3029840264
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2999463315
Short name T375
Test name
Test status
Simulation time 6440049802 ps
CPU time 13.09 seconds
Started Jul 01 10:44:14 AM PDT 24
Finished Jul 01 10:44:27 AM PDT 24
Peak memory 210516 kb
Host smart-018050e9-21cf-4974-9766-c73d46fd9813
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999463315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2999463315
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1552963300
Short name T409
Test name
Test status
Simulation time 270006581 ps
CPU time 4.25 seconds
Started Jul 01 10:44:05 AM PDT 24
Finished Jul 01 10:44:10 AM PDT 24
Peak memory 210476 kb
Host smart-cdd31a7c-4f0f-40b6-ad4f-4dcc11dc6c7c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552963300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1552963300
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.130844849
Short name T435
Test name
Test status
Simulation time 6130136169 ps
CPU time 54.43 seconds
Started Jul 01 10:44:12 AM PDT 24
Finished Jul 01 10:45:07 AM PDT 24
Peak memory 210732 kb
Host smart-fe3acb0e-aa35-4180-9509-08b69a7940d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130844849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.130844849
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.437068212
Short name T83
Test name
Test status
Simulation time 7493453848 ps
CPU time 16.87 seconds
Started Jul 01 10:43:54 AM PDT 24
Finished Jul 01 10:44:13 AM PDT 24
Peak memory 211040 kb
Host smart-906d983b-aba4-4154-a115-b29932ca6236
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437068212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.437068212
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2278630714
Short name T439
Test name
Test status
Simulation time 168160112 ps
CPU time 6.42 seconds
Started Jul 01 10:43:54 AM PDT 24
Finished Jul 01 10:44:04 AM PDT 24
Peak memory 218900 kb
Host smart-3b3fe7da-416a-4013-b3bf-718f6d7c69dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278630714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2278630714
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2107045184
Short name T92
Test name
Test status
Simulation time 20527479024 ps
CPU time 46.37 seconds
Started Jul 01 10:44:18 AM PDT 24
Finished Jul 01 10:45:05 AM PDT 24
Peak memory 218936 kb
Host smart-3937b355-37b3-49f8-a301-d9eff4f4b13b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107045184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2107045184
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3260437711
Short name T443
Test name
Test status
Simulation time 3100672488 ps
CPU time 9.54 seconds
Started Jul 01 10:44:08 AM PDT 24
Finished Jul 01 10:44:19 AM PDT 24
Peak memory 219012 kb
Host smart-d692df03-7378-47a8-89c5-9b738ea85f1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260437711 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3260437711
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.91295964
Short name T461
Test name
Test status
Simulation time 6407085397 ps
CPU time 13.3 seconds
Started Jul 01 10:43:51 AM PDT 24
Finished Jul 01 10:44:05 AM PDT 24
Peak memory 210764 kb
Host smart-29c5990a-b1f6-4ece-b681-e5bca3121875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91295964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.91295964
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.392514483
Short name T62
Test name
Test status
Simulation time 34740098154 ps
CPU time 83 seconds
Started Jul 01 10:44:16 AM PDT 24
Finished Jul 01 10:45:40 AM PDT 24
Peak memory 210680 kb
Host smart-5622161c-b3f7-40f7-9119-6cc6f4f8da2b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392514483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.392514483
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1012978506
Short name T440
Test name
Test status
Simulation time 85685041 ps
CPU time 4.39 seconds
Started Jul 01 10:44:30 AM PDT 24
Finished Jul 01 10:44:34 AM PDT 24
Peak memory 210648 kb
Host smart-8e370e91-d3e2-45c9-b09e-3fa203a0206a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012978506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1012978506
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1532323706
Short name T387
Test name
Test status
Simulation time 2029274300 ps
CPU time 17.84 seconds
Started Jul 01 10:44:05 AM PDT 24
Finished Jul 01 10:44:23 AM PDT 24
Peak memory 218964 kb
Host smart-3ef0871f-9b49-4ca5-9250-cab3a7716543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532323706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1532323706
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3231672924
Short name T381
Test name
Test status
Simulation time 105104126 ps
CPU time 5.41 seconds
Started Jul 01 10:44:01 AM PDT 24
Finished Jul 01 10:44:08 AM PDT 24
Peak memory 215932 kb
Host smart-a958b3be-7a1e-44a2-8aaf-da16bd006ea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231672924 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3231672924
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.445129965
Short name T79
Test name
Test status
Simulation time 333293060 ps
CPU time 4.04 seconds
Started Jul 01 10:44:09 AM PDT 24
Finished Jul 01 10:44:14 AM PDT 24
Peak memory 210704 kb
Host smart-5c87468b-6e02-4112-80ad-4ff537e370e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445129965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.445129965
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.542644313
Short name T74
Test name
Test status
Simulation time 7877670940 ps
CPU time 74.02 seconds
Started Jul 01 10:44:21 AM PDT 24
Finished Jul 01 10:45:36 AM PDT 24
Peak memory 217880 kb
Host smart-ec635bb4-397e-4240-ab01-ad39d6197fd7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542644313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.542644313
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2962910917
Short name T63
Test name
Test status
Simulation time 4655992466 ps
CPU time 12.9 seconds
Started Jul 01 10:44:03 AM PDT 24
Finished Jul 01 10:44:17 AM PDT 24
Peak memory 211184 kb
Host smart-e7758415-0e82-450a-bc9b-53b267788a54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962910917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2962910917
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1955865353
Short name T412
Test name
Test status
Simulation time 107000350 ps
CPU time 5.24 seconds
Started Jul 01 10:43:48 AM PDT 24
Finished Jul 01 10:43:54 AM PDT 24
Peak memory 218968 kb
Host smart-e64dc11a-126f-4de6-a4cf-9fa7d40ca97c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955865353 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1955865353
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3210982963
Short name T400
Test name
Test status
Simulation time 1598779897 ps
CPU time 6.77 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:44:08 AM PDT 24
Peak memory 217948 kb
Host smart-6f050cd2-9b1c-4555-9172-f17b9c1bed4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210982963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3210982963
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1287662387
Short name T90
Test name
Test status
Simulation time 971811871 ps
CPU time 19.03 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:44:20 AM PDT 24
Peak memory 210736 kb
Host smart-0b6f621e-b115-4993-9d01-b342166580a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287662387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1287662387
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.819354888
Short name T407
Test name
Test status
Simulation time 375759742 ps
CPU time 6.12 seconds
Started Jul 01 10:44:00 AM PDT 24
Finished Jul 01 10:44:08 AM PDT 24
Peak memory 210624 kb
Host smart-5d8869cc-b66b-4816-8608-3ad588725216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819354888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.819354888
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3405193531
Short name T388
Test name
Test status
Simulation time 3520178781 ps
CPU time 12.08 seconds
Started Jul 01 10:44:03 AM PDT 24
Finished Jul 01 10:44:16 AM PDT 24
Peak memory 218912 kb
Host smart-be16df34-810e-4288-981f-5d0d071989a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405193531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3405193531
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3478440722
Short name T95
Test name
Test status
Simulation time 9128544817 ps
CPU time 79.27 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:45:20 AM PDT 24
Peak memory 219136 kb
Host smart-62d7a27a-d4f6-43da-9298-58a9a6a91714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478440722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3478440722
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1294071654
Short name T404
Test name
Test status
Simulation time 9140970539 ps
CPU time 13.46 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:44:14 AM PDT 24
Peak memory 219080 kb
Host smart-b920f290-1854-4147-87f6-3525cbd9b7e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294071654 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1294071654
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.262449808
Short name T403
Test name
Test status
Simulation time 6488324055 ps
CPU time 12.48 seconds
Started Jul 01 10:44:03 AM PDT 24
Finished Jul 01 10:44:16 AM PDT 24
Peak memory 210764 kb
Host smart-a0dea792-7fcd-4f9b-962e-9fe76c992574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262449808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.262449808
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3074081280
Short name T416
Test name
Test status
Simulation time 45705014133 ps
CPU time 100.46 seconds
Started Jul 01 10:44:18 AM PDT 24
Finished Jul 01 10:45:59 AM PDT 24
Peak memory 210792 kb
Host smart-030624b5-1bb1-4425-ad3a-32aa60c1aa92
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074081280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3074081280
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4067292220
Short name T64
Test name
Test status
Simulation time 87317841 ps
CPU time 4.41 seconds
Started Jul 01 10:43:58 AM PDT 24
Finished Jul 01 10:44:06 AM PDT 24
Peak memory 210744 kb
Host smart-d73e1184-630b-4e2d-8af7-91afaff6239c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067292220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4067292220
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3573538582
Short name T410
Test name
Test status
Simulation time 4829347219 ps
CPU time 15.89 seconds
Started Jul 01 10:43:57 AM PDT 24
Finished Jul 01 10:44:17 AM PDT 24
Peak memory 219024 kb
Host smart-65aac067-3923-4b3f-9d04-1e0050fe2152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573538582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3573538582
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1504999205
Short name T382
Test name
Test status
Simulation time 1422366697 ps
CPU time 43.76 seconds
Started Jul 01 10:44:08 AM PDT 24
Finished Jul 01 10:44:53 AM PDT 24
Peak memory 218960 kb
Host smart-97d7df15-bf46-4d54-9298-2daaf6d7eb49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504999205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1504999205
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1346826075
Short name T426
Test name
Test status
Simulation time 2354802982 ps
CPU time 11.47 seconds
Started Jul 01 10:44:05 AM PDT 24
Finished Jul 01 10:44:18 AM PDT 24
Peak memory 219076 kb
Host smart-512fd3ca-33f4-4983-aec4-0cb102509693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346826075 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1346826075
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1825813223
Short name T377
Test name
Test status
Simulation time 7331397582 ps
CPU time 15.01 seconds
Started Jul 01 10:44:16 AM PDT 24
Finished Jul 01 10:44:31 AM PDT 24
Peak memory 218908 kb
Host smart-250619e3-b4e1-433c-a149-326717eb7865
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825813223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1825813223
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4186914816
Short name T428
Test name
Test status
Simulation time 6341958901 ps
CPU time 14.23 seconds
Started Jul 01 10:43:51 AM PDT 24
Finished Jul 01 10:44:06 AM PDT 24
Peak memory 210808 kb
Host smart-b1f419fc-6fc5-4004-b268-a9df1f52615d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186914816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4186914816
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.459860894
Short name T460
Test name
Test status
Simulation time 568047545 ps
CPU time 9.12 seconds
Started Jul 01 10:44:26 AM PDT 24
Finished Jul 01 10:44:36 AM PDT 24
Peak memory 218852 kb
Host smart-65271c72-c4fd-46f6-a9d6-0fdc48cb606e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459860894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.459860894
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3186673955
Short name T50
Test name
Test status
Simulation time 2056916821 ps
CPU time 76.03 seconds
Started Jul 01 10:44:18 AM PDT 24
Finished Jul 01 10:45:35 AM PDT 24
Peak memory 218936 kb
Host smart-170029a0-47f4-4ef9-94ac-01870da01754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186673955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3186673955
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2604713314
Short name T256
Test name
Test status
Simulation time 105882476808 ps
CPU time 286.96 seconds
Started Jul 01 11:03:51 AM PDT 24
Finished Jul 01 11:08:40 AM PDT 24
Peak memory 234972 kb
Host smart-29063cbb-fd79-4b67-94fc-3bd8642983e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604713314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2604713314
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2982784159
Short name T321
Test name
Test status
Simulation time 2450598122 ps
CPU time 12.64 seconds
Started Jul 01 11:03:51 AM PDT 24
Finished Jul 01 11:04:06 AM PDT 24
Peak memory 211592 kb
Host smart-c558c29b-f732-4154-a25c-af0a99f44825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982784159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2982784159
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4126937354
Short name T111
Test name
Test status
Simulation time 190174182 ps
CPU time 10.3 seconds
Started Jul 01 11:03:51 AM PDT 24
Finished Jul 01 11:04:03 AM PDT 24
Peak memory 212980 kb
Host smart-a7a774e5-7194-49f7-af54-c66a50629621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126937354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4126937354
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.798640768
Short name T225
Test name
Test status
Simulation time 194418844 ps
CPU time 6.84 seconds
Started Jul 01 11:03:50 AM PDT 24
Finished Jul 01 11:03:59 AM PDT 24
Peak memory 211248 kb
Host smart-cda71463-6601-433d-afb8-15b4d955eb7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798640768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.798640768
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2452303314
Short name T307
Test name
Test status
Simulation time 4014428363 ps
CPU time 15.21 seconds
Started Jul 01 11:03:51 AM PDT 24
Finished Jul 01 11:04:08 AM PDT 24
Peak memory 211432 kb
Host smart-1e078d6e-530f-4317-b6d2-47f8ba9023da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452303314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2452303314
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.631286257
Short name T164
Test name
Test status
Simulation time 1008027062 ps
CPU time 58.59 seconds
Started Jul 01 11:03:50 AM PDT 24
Finished Jul 01 11:04:51 AM PDT 24
Peak memory 227228 kb
Host smart-41b75fd0-c941-44c3-b391-7f19fdf42e4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631286257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.631286257
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.146038574
Short name T284
Test name
Test status
Simulation time 2942548837 ps
CPU time 19.91 seconds
Started Jul 01 11:04:13 AM PDT 24
Finished Jul 01 11:04:33 AM PDT 24
Peak memory 211896 kb
Host smart-74e2e3f6-c6e9-491f-9d70-88c728bd8eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146038574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.146038574
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2425176107
Short name T190
Test name
Test status
Simulation time 1043096650 ps
CPU time 11.26 seconds
Started Jul 01 11:03:50 AM PDT 24
Finished Jul 01 11:04:03 AM PDT 24
Peak memory 211380 kb
Host smart-865d4e4d-939d-4a9e-9ea3-61e187e0c801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425176107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2425176107
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3903517140
Short name T23
Test name
Test status
Simulation time 1590281643 ps
CPU time 106.82 seconds
Started Jul 01 11:04:12 AM PDT 24
Finished Jul 01 11:06:00 AM PDT 24
Peak memory 235528 kb
Host smart-f941ae56-fa39-430d-bab3-3cc5492682cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903517140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3903517140
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1425399831
Short name T69
Test name
Test status
Simulation time 5500830295 ps
CPU time 26.43 seconds
Started Jul 01 11:03:49 AM PDT 24
Finished Jul 01 11:04:17 AM PDT 24
Peak memory 213636 kb
Host smart-27ac2383-1ca4-4570-a77f-02276990b6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425399831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1425399831
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.382892859
Short name T352
Test name
Test status
Simulation time 1916915606 ps
CPU time 30.18 seconds
Started Jul 01 11:03:52 AM PDT 24
Finished Jul 01 11:04:23 AM PDT 24
Peak memory 215196 kb
Host smart-c10451f1-2b30-49ac-bdb1-d4897da17e82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382892859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.382892859
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2819711717
Short name T207
Test name
Test status
Simulation time 1539018488 ps
CPU time 6.47 seconds
Started Jul 01 11:04:26 AM PDT 24
Finished Jul 01 11:04:33 AM PDT 24
Peak memory 211312 kb
Host smart-3e814d32-490a-4165-baf8-1f1d8cfbbda1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819711717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2819711717
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3442609266
Short name T105
Test name
Test status
Simulation time 283375776115 ps
CPU time 300.55 seconds
Started Jul 01 11:04:09 AM PDT 24
Finished Jul 01 11:09:11 AM PDT 24
Peak memory 237864 kb
Host smart-6317bb45-859a-425c-b095-7f5bd1322e7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442609266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3442609266
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1588355179
Short name T228
Test name
Test status
Simulation time 2245538109 ps
CPU time 22.44 seconds
Started Jul 01 11:04:16 AM PDT 24
Finished Jul 01 11:04:39 AM PDT 24
Peak memory 211988 kb
Host smart-e8e1d924-a542-4056-aec0-4a1a95e1e609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588355179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1588355179
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3871309925
Short name T208
Test name
Test status
Simulation time 2946369588 ps
CPU time 9.93 seconds
Started Jul 01 11:04:22 AM PDT 24
Finished Jul 01 11:04:32 AM PDT 24
Peak memory 211452 kb
Host smart-97d1a249-033a-4257-9cfc-1f8e143ea2ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871309925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3871309925
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3738914156
Short name T279
Test name
Test status
Simulation time 11334999095 ps
CPU time 33.88 seconds
Started Jul 01 11:04:08 AM PDT 24
Finished Jul 01 11:04:42 AM PDT 24
Peak memory 213960 kb
Host smart-26ba880b-be9e-40f7-b9ad-8dadd0327dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738914156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3738914156
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4220863152
Short name T9
Test name
Test status
Simulation time 10725734397 ps
CPU time 15.22 seconds
Started Jul 01 11:04:09 AM PDT 24
Finished Jul 01 11:04:24 AM PDT 24
Peak memory 212648 kb
Host smart-448704dc-5e52-4755-9cf9-115e3cfa7ac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220863152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4220863152
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3139111953
Short name T213
Test name
Test status
Simulation time 1037270156 ps
CPU time 10.62 seconds
Started Jul 01 11:04:14 AM PDT 24
Finished Jul 01 11:04:25 AM PDT 24
Peak memory 211344 kb
Host smart-ded531a9-7e9e-45a6-9598-5579c1dd2ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139111953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3139111953
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1216119206
Short name T313
Test name
Test status
Simulation time 2650721870 ps
CPU time 106.74 seconds
Started Jul 01 11:04:13 AM PDT 24
Finished Jul 01 11:06:01 AM PDT 24
Peak memory 225048 kb
Host smart-4807eeb3-a197-4261-b52e-68d9cc419ad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216119206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1216119206
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.673182484
Short name T3
Test name
Test status
Simulation time 1801465093 ps
CPU time 20.68 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:04:50 AM PDT 24
Peak memory 211960 kb
Host smart-81a4da69-bbfe-4595-9c08-42fe59b3fffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673182484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.673182484
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2809135045
Short name T144
Test name
Test status
Simulation time 1829881214 ps
CPU time 5.3 seconds
Started Jul 01 11:04:27 AM PDT 24
Finished Jul 01 11:04:34 AM PDT 24
Peak memory 211408 kb
Host smart-0decc48d-1c76-4c5d-ac9b-80fc71cb4ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809135045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2809135045
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.481001258
Short name T172
Test name
Test status
Simulation time 6500521860 ps
CPU time 32.66 seconds
Started Jul 01 11:04:26 AM PDT 24
Finished Jul 01 11:04:59 AM PDT 24
Peak memory 212600 kb
Host smart-971a542c-fb7d-4f97-8c12-9cc4deb8552a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481001258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.481001258
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1416168219
Short name T189
Test name
Test status
Simulation time 17059498731 ps
CPU time 57.06 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:05:26 AM PDT 24
Peak memory 215984 kb
Host smart-63f294d3-d16e-429d-90f0-b077665ccd66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416168219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1416168219
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3136955809
Short name T232
Test name
Test status
Simulation time 1560228958 ps
CPU time 13.65 seconds
Started Jul 01 11:04:12 AM PDT 24
Finished Jul 01 11:04:26 AM PDT 24
Peak memory 211344 kb
Host smart-4ab14f3d-3178-4f41-852e-9cecf20732b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136955809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3136955809
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2640695210
Short name T155
Test name
Test status
Simulation time 14228908714 ps
CPU time 28 seconds
Started Jul 01 11:04:19 AM PDT 24
Finished Jul 01 11:04:48 AM PDT 24
Peak memory 212292 kb
Host smart-018fe777-b0d0-4091-b8cd-89ab274667de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640695210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2640695210
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.172378327
Short name T238
Test name
Test status
Simulation time 4034106128 ps
CPU time 16.37 seconds
Started Jul 01 11:04:14 AM PDT 24
Finished Jul 01 11:04:31 AM PDT 24
Peak memory 211424 kb
Host smart-eeb9be9f-542d-4266-9ebd-e3380407deea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172378327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.172378327
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3831359950
Short name T169
Test name
Test status
Simulation time 4041215217 ps
CPU time 40.52 seconds
Started Jul 01 11:04:27 AM PDT 24
Finished Jul 01 11:05:08 AM PDT 24
Peak memory 214088 kb
Host smart-b613a9c1-f3ef-4625-9b67-e5d3b6e78de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831359950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3831359950
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.533584470
Short name T362
Test name
Test status
Simulation time 340896303 ps
CPU time 16.78 seconds
Started Jul 01 11:04:15 AM PDT 24
Finished Jul 01 11:04:32 AM PDT 24
Peak memory 215080 kb
Host smart-f5d34f10-8339-410d-a2f5-6fdc8e0a8fb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533584470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.533584470
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.670129430
Short name T217
Test name
Test status
Simulation time 1942372634 ps
CPU time 11.15 seconds
Started Jul 01 11:04:16 AM PDT 24
Finished Jul 01 11:04:27 AM PDT 24
Peak memory 211364 kb
Host smart-e65db9e1-7e17-4f71-8afe-f07d9ab829e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670129430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.670129430
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1682182030
Short name T125
Test name
Test status
Simulation time 1483140830 ps
CPU time 18.2 seconds
Started Jul 01 11:04:14 AM PDT 24
Finished Jul 01 11:04:33 AM PDT 24
Peak memory 212064 kb
Host smart-40f74f35-da21-4a90-a21c-07349d65c72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682182030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1682182030
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1728802288
Short name T266
Test name
Test status
Simulation time 7113485193 ps
CPU time 14.53 seconds
Started Jul 01 11:04:14 AM PDT 24
Finished Jul 01 11:04:29 AM PDT 24
Peak memory 211496 kb
Host smart-31663f30-11f1-4d24-9327-1c5206d075df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728802288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1728802288
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2801438824
Short name T70
Test name
Test status
Simulation time 4221062221 ps
CPU time 24.06 seconds
Started Jul 01 11:04:12 AM PDT 24
Finished Jul 01 11:04:37 AM PDT 24
Peak memory 213720 kb
Host smart-fb9153dd-280a-47f3-b3c4-66eb79c4a45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801438824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2801438824
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.512347517
Short name T278
Test name
Test status
Simulation time 4910556316 ps
CPU time 47.56 seconds
Started Jul 01 11:04:13 AM PDT 24
Finished Jul 01 11:05:02 AM PDT 24
Peak memory 217228 kb
Host smart-c68c1c32-d2eb-42c9-8ecf-8f61cae9feae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512347517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.512347517
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3518658804
Short name T177
Test name
Test status
Simulation time 309904790 ps
CPU time 4.33 seconds
Started Jul 01 11:04:29 AM PDT 24
Finished Jul 01 11:04:34 AM PDT 24
Peak memory 211344 kb
Host smart-66f7b335-84f7-4819-b84e-fb42204403f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518658804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3518658804
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3281033603
Short name T26
Test name
Test status
Simulation time 103214884297 ps
CPU time 193.54 seconds
Started Jul 01 11:04:22 AM PDT 24
Finished Jul 01 11:07:36 AM PDT 24
Peak memory 224828 kb
Host smart-389c044f-d99a-4961-8c4c-1e030dcefb69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281033603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3281033603
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3214898443
Short name T247
Test name
Test status
Simulation time 3666901567 ps
CPU time 30.77 seconds
Started Jul 01 11:04:26 AM PDT 24
Finished Jul 01 11:04:58 AM PDT 24
Peak memory 211460 kb
Host smart-960fafa8-f155-4b47-8bb8-dc2265135f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214898443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3214898443
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2850710701
Short name T345
Test name
Test status
Simulation time 1956914542 ps
CPU time 15.76 seconds
Started Jul 01 11:04:22 AM PDT 24
Finished Jul 01 11:04:39 AM PDT 24
Peak memory 211376 kb
Host smart-b45eabb9-702a-4ff0-8955-0c1bd6014a45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850710701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2850710701
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2009703901
Short name T7
Test name
Test status
Simulation time 1311764210 ps
CPU time 11.69 seconds
Started Jul 01 11:04:27 AM PDT 24
Finished Jul 01 11:04:40 AM PDT 24
Peak memory 213808 kb
Host smart-74d26cf0-2c11-4c6b-9e0a-c0b5c854a485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009703901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2009703901
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3392770164
Short name T181
Test name
Test status
Simulation time 6408563692 ps
CPU time 35.22 seconds
Started Jul 01 11:04:13 AM PDT 24
Finished Jul 01 11:04:49 AM PDT 24
Peak memory 214836 kb
Host smart-22bf091d-bce1-4371-8cf0-4d8b734ce689
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392770164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3392770164
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.4290219544
Short name T298
Test name
Test status
Simulation time 6869928640 ps
CPU time 14.38 seconds
Started Jul 01 11:04:27 AM PDT 24
Finished Jul 01 11:04:43 AM PDT 24
Peak memory 211384 kb
Host smart-d253da68-9fa1-4e0e-b281-8b910040b9eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290219544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.4290219544
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1305349150
Short name T201
Test name
Test status
Simulation time 30925740947 ps
CPU time 137.96 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:06:49 AM PDT 24
Peak memory 212656 kb
Host smart-2e287a98-2d7e-4b2c-bf0c-c279f09cc2c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305349150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1305349150
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2157441130
Short name T30
Test name
Test status
Simulation time 175534950 ps
CPU time 9.39 seconds
Started Jul 01 11:04:29 AM PDT 24
Finished Jul 01 11:04:40 AM PDT 24
Peak memory 211964 kb
Host smart-abf9aac9-8de2-4c81-ba2a-a24df149c286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157441130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2157441130
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3397490072
Short name T230
Test name
Test status
Simulation time 9344146218 ps
CPU time 17.66 seconds
Started Jul 01 11:04:26 AM PDT 24
Finished Jul 01 11:04:44 AM PDT 24
Peak memory 211448 kb
Host smart-c6d9eac9-2e0d-441d-ba51-7cbc4d5611dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397490072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3397490072
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3600628550
Short name T212
Test name
Test status
Simulation time 944246894 ps
CPU time 16.71 seconds
Started Jul 01 11:04:21 AM PDT 24
Finished Jul 01 11:04:39 AM PDT 24
Peak memory 213316 kb
Host smart-fea1ab85-b89c-4ab2-8f1c-302a8c771e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600628550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3600628550
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.503570404
Short name T224
Test name
Test status
Simulation time 640049254 ps
CPU time 13.11 seconds
Started Jul 01 11:04:20 AM PDT 24
Finished Jul 01 11:04:34 AM PDT 24
Peak memory 211420 kb
Host smart-8f4f4b3e-f0bb-4adc-b574-5d8391867ca2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503570404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.503570404
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3080959623
Short name T357
Test name
Test status
Simulation time 1729701111 ps
CPU time 13.99 seconds
Started Jul 01 11:04:21 AM PDT 24
Finished Jul 01 11:04:35 AM PDT 24
Peak memory 211344 kb
Host smart-38f656c6-e112-4835-8e80-82d4d2cd32cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080959623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3080959623
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2367598826
Short name T290
Test name
Test status
Simulation time 15995874604 ps
CPU time 93.04 seconds
Started Jul 01 11:04:27 AM PDT 24
Finished Jul 01 11:06:01 AM PDT 24
Peak memory 237524 kb
Host smart-6c7e0d40-cd7d-49cc-860c-8d7ca97fa8fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367598826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2367598826
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3551999139
Short name T1
Test name
Test status
Simulation time 1177737727 ps
CPU time 11.91 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:04:43 AM PDT 24
Peak memory 211396 kb
Host smart-b6d73be1-efd2-413f-92be-9e20f6579c3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551999139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3551999139
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2714784078
Short name T358
Test name
Test status
Simulation time 1388676735 ps
CPU time 12.17 seconds
Started Jul 01 11:04:24 AM PDT 24
Finished Jul 01 11:04:37 AM PDT 24
Peak memory 213884 kb
Host smart-bc017b58-15fc-45a7-b89a-5033883b4aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714784078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2714784078
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1240756725
Short name T239
Test name
Test status
Simulation time 49557925501 ps
CPU time 97.07 seconds
Started Jul 01 11:04:25 AM PDT 24
Finished Jul 01 11:06:03 AM PDT 24
Peak memory 219408 kb
Host smart-efd39e12-515c-4d02-a27d-0416b94143c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240756725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1240756725
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.4044739372
Short name T359
Test name
Test status
Simulation time 29995537767 ps
CPU time 1190.26 seconds
Started Jul 01 11:04:21 AM PDT 24
Finished Jul 01 11:24:12 AM PDT 24
Peak memory 235936 kb
Host smart-7fb5cd5d-bf08-47a5-8aed-0c719c50e033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044739372 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.4044739372
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1863850595
Short name T240
Test name
Test status
Simulation time 1741633660 ps
CPU time 13.94 seconds
Started Jul 01 11:04:40 AM PDT 24
Finished Jul 01 11:04:54 AM PDT 24
Peak memory 211348 kb
Host smart-1bc3457c-8bb9-4aa6-9ed8-b370216ef081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863850595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1863850595
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.962206742
Short name T31
Test name
Test status
Simulation time 6015691070 ps
CPU time 180.48 seconds
Started Jul 01 11:04:19 AM PDT 24
Finished Jul 01 11:07:21 AM PDT 24
Peak memory 235244 kb
Host smart-f6e553e7-63a5-45ac-9d02-bf1b5138f3ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962206742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.962206742
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2344843954
Short name T107
Test name
Test status
Simulation time 1583339350 ps
CPU time 14.19 seconds
Started Jul 01 11:04:21 AM PDT 24
Finished Jul 01 11:04:36 AM PDT 24
Peak memory 211296 kb
Host smart-ef21a771-ee21-424f-9f53-c2a1bdbd59af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2344843954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2344843954
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1097751996
Short name T139
Test name
Test status
Simulation time 3105843979 ps
CPU time 19.03 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:04:48 AM PDT 24
Peak memory 213380 kb
Host smart-e16b02f4-ca4d-4366-9e07-24ab024940ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097751996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1097751996
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3350401445
Short name T137
Test name
Test status
Simulation time 36947303299 ps
CPU time 101.94 seconds
Started Jul 01 11:04:26 AM PDT 24
Finished Jul 01 11:06:09 AM PDT 24
Peak memory 219412 kb
Host smart-f9a6a839-9ee9-4d60-9433-7da363e63ba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350401445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3350401445
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.374544273
Short name T127
Test name
Test status
Simulation time 1380858057 ps
CPU time 12.53 seconds
Started Jul 01 11:04:24 AM PDT 24
Finished Jul 01 11:04:38 AM PDT 24
Peak memory 211368 kb
Host smart-89b27a8b-65cb-4ff7-8d39-b7efc67af68a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374544273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.374544273
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4038979118
Short name T336
Test name
Test status
Simulation time 11277166842 ps
CPU time 119.33 seconds
Started Jul 01 11:04:21 AM PDT 24
Finished Jul 01 11:06:21 AM PDT 24
Peak memory 225028 kb
Host smart-7b8d1ac2-e9ab-4f91-8ff1-764d014f0cbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038979118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4038979118
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1081394194
Short name T337
Test name
Test status
Simulation time 7183039889 ps
CPU time 20.23 seconds
Started Jul 01 11:04:25 AM PDT 24
Finished Jul 01 11:04:46 AM PDT 24
Peak memory 211524 kb
Host smart-bbfe188c-b7c2-449b-9a18-e2a4d135324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081394194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1081394194
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.400916017
Short name T108
Test name
Test status
Simulation time 301253424 ps
CPU time 7.89 seconds
Started Jul 01 11:04:18 AM PDT 24
Finished Jul 01 11:04:27 AM PDT 24
Peak memory 211392 kb
Host smart-4c475ee2-30bd-48a9-a927-65ba4701b7cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400916017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.400916017
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2016373672
Short name T25
Test name
Test status
Simulation time 192441871 ps
CPU time 9.9 seconds
Started Jul 01 11:04:26 AM PDT 24
Finished Jul 01 11:04:37 AM PDT 24
Peak memory 213188 kb
Host smart-fefa836c-c6d8-4c24-b869-ad376a3c5835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016373672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2016373672
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1702293778
Short name T131
Test name
Test status
Simulation time 83233716184 ps
CPU time 51.61 seconds
Started Jul 01 11:04:24 AM PDT 24
Finished Jul 01 11:05:16 AM PDT 24
Peak memory 216988 kb
Host smart-a5987106-ad56-4a8d-a06a-c42877a0c66b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702293778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1702293778
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3088685804
Short name T20
Test name
Test status
Simulation time 108483112385 ps
CPU time 2353.08 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:43:45 AM PDT 24
Peak memory 232120 kb
Host smart-ca2aef14-7543-4eed-97a5-ec8fc12efa75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088685804 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3088685804
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3491428838
Short name T330
Test name
Test status
Simulation time 167694914 ps
CPU time 5.51 seconds
Started Jul 01 11:04:24 AM PDT 24
Finished Jul 01 11:04:30 AM PDT 24
Peak memory 211368 kb
Host smart-7f518f55-a7e7-45ac-9df6-ae55d1d2d622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491428838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3491428838
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1170648880
Short name T333
Test name
Test status
Simulation time 35469807164 ps
CPU time 367.17 seconds
Started Jul 01 11:04:21 AM PDT 24
Finished Jul 01 11:10:29 AM PDT 24
Peak memory 237736 kb
Host smart-826811f5-0fea-44b5-abba-9604edaa2f0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170648880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1170648880
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3489011085
Short name T49
Test name
Test status
Simulation time 1197576049 ps
CPU time 16.9 seconds
Started Jul 01 11:04:25 AM PDT 24
Finished Jul 01 11:04:43 AM PDT 24
Peak memory 212008 kb
Host smart-29fb583a-941c-4713-8613-1f0dbecb9197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489011085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3489011085
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.511943214
Short name T286
Test name
Test status
Simulation time 3044946981 ps
CPU time 13.23 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:04:44 AM PDT 24
Peak memory 211472 kb
Host smart-dbeb016e-c5fb-4849-be48-b96812b3351c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=511943214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.511943214
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.438420349
Short name T159
Test name
Test status
Simulation time 2656568299 ps
CPU time 24.6 seconds
Started Jul 01 11:04:27 AM PDT 24
Finished Jul 01 11:04:52 AM PDT 24
Peak memory 213392 kb
Host smart-aa9da6c5-f796-40e8-bc0e-c97282a174b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438420349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.438420349
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3251007828
Short name T274
Test name
Test status
Simulation time 23859506022 ps
CPU time 22.33 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:04:52 AM PDT 24
Peak memory 216500 kb
Host smart-d9a9c20c-6907-44a5-ad3c-c36305c57bc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251007828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3251007828
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2508096339
Short name T251
Test name
Test status
Simulation time 5585744569 ps
CPU time 10.9 seconds
Started Jul 01 11:04:04 AM PDT 24
Finished Jul 01 11:04:15 AM PDT 24
Peak memory 211408 kb
Host smart-47c6bf91-4631-4b65-b160-3b6f46dd5884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508096339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2508096339
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3227347104
Short name T206
Test name
Test status
Simulation time 140292537097 ps
CPU time 301.16 seconds
Started Jul 01 11:03:50 AM PDT 24
Finished Jul 01 11:08:52 AM PDT 24
Peak memory 237876 kb
Host smart-cee2f3ee-9b8e-4f2f-a2c1-c4546f15ceac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227347104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3227347104
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3933390280
Short name T166
Test name
Test status
Simulation time 348175285 ps
CPU time 9.51 seconds
Started Jul 01 11:03:49 AM PDT 24
Finished Jul 01 11:04:00 AM PDT 24
Peak memory 211892 kb
Host smart-1f01b1e5-a0e5-4994-9922-412c67ecc0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933390280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3933390280
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2510327308
Short name T204
Test name
Test status
Simulation time 687812996 ps
CPU time 6.15 seconds
Started Jul 01 11:03:55 AM PDT 24
Finished Jul 01 11:04:02 AM PDT 24
Peak memory 211356 kb
Host smart-21d10f85-cdcb-4160-a7dd-7edffd4d5d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510327308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2510327308
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3354562718
Short name T14
Test name
Test status
Simulation time 1669815636 ps
CPU time 102.44 seconds
Started Jul 01 11:03:50 AM PDT 24
Finished Jul 01 11:05:34 AM PDT 24
Peak memory 236016 kb
Host smart-08eda614-ab91-4b98-906e-aa5ba9cc62b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354562718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3354562718
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1000992172
Short name T291
Test name
Test status
Simulation time 1267688254 ps
CPU time 19.31 seconds
Started Jul 01 11:03:51 AM PDT 24
Finished Jul 01 11:04:12 AM PDT 24
Peak memory 213620 kb
Host smart-1d83fdb4-a677-4457-8e67-1cf6b16e64f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000992172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1000992172
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4020661608
Short name T287
Test name
Test status
Simulation time 189256171 ps
CPU time 8.22 seconds
Started Jul 01 11:04:04 AM PDT 24
Finished Jul 01 11:04:12 AM PDT 24
Peak memory 211220 kb
Host smart-7d767327-7785-4324-a079-11a2571504ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020661608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4020661608
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2885872622
Short name T146
Test name
Test status
Simulation time 4601033406 ps
CPU time 11.16 seconds
Started Jul 01 11:04:32 AM PDT 24
Finished Jul 01 11:04:44 AM PDT 24
Peak memory 211408 kb
Host smart-6e838fba-0430-401a-8cbc-5929d0308d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885872622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2885872622
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2701194027
Short name T242
Test name
Test status
Simulation time 5515608591 ps
CPU time 79.5 seconds
Started Jul 01 11:04:35 AM PDT 24
Finished Jul 01 11:05:55 AM PDT 24
Peak memory 237920 kb
Host smart-d2f63156-a638-4693-ac46-0b34d3e37557
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701194027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2701194027
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2369007729
Short name T122
Test name
Test status
Simulation time 6565365052 ps
CPU time 19.9 seconds
Started Jul 01 11:04:33 AM PDT 24
Finished Jul 01 11:04:54 AM PDT 24
Peak memory 212360 kb
Host smart-0541ba42-a1f0-4e42-8171-5a60e8e6f950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369007729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2369007729
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3977056655
Short name T175
Test name
Test status
Simulation time 993652097 ps
CPU time 10.65 seconds
Started Jul 01 11:04:26 AM PDT 24
Finished Jul 01 11:04:38 AM PDT 24
Peak memory 211384 kb
Host smart-22861e26-08d6-4aba-8bff-e317b8db26a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977056655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3977056655
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2402977796
Short name T249
Test name
Test status
Simulation time 4606310830 ps
CPU time 32.83 seconds
Started Jul 01 11:04:22 AM PDT 24
Finished Jul 01 11:04:55 AM PDT 24
Peak memory 214448 kb
Host smart-2ee17353-3821-4188-aa8a-fca95ef64415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402977796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2402977796
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2801321210
Short name T157
Test name
Test status
Simulation time 25246463299 ps
CPU time 56.25 seconds
Started Jul 01 11:04:29 AM PDT 24
Finished Jul 01 11:05:27 AM PDT 24
Peak memory 214464 kb
Host smart-37a99226-64c0-4892-9b13-15b9f1a6eb7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801321210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2801321210
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1293827254
Short name T226
Test name
Test status
Simulation time 89303759 ps
CPU time 4.43 seconds
Started Jul 01 11:04:33 AM PDT 24
Finished Jul 01 11:04:38 AM PDT 24
Peak memory 211308 kb
Host smart-b4984d4b-59be-467b-ae2c-bf4ea2ed4401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293827254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1293827254
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2878857477
Short name T124
Test name
Test status
Simulation time 24966082373 ps
CPU time 92.54 seconds
Started Jul 01 11:04:31 AM PDT 24
Finished Jul 01 11:06:04 AM PDT 24
Peak memory 236996 kb
Host smart-ac9806da-bfca-479e-98d5-a51c61efc0ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878857477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2878857477
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.701671658
Short name T123
Test name
Test status
Simulation time 3029534060 ps
CPU time 26.87 seconds
Started Jul 01 11:04:32 AM PDT 24
Finished Jul 01 11:04:59 AM PDT 24
Peak memory 212000 kb
Host smart-2d9396ec-295b-4dc8-9df6-f56cee2cb42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701671658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.701671658
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2237183307
Short name T135
Test name
Test status
Simulation time 436346361 ps
CPU time 5.77 seconds
Started Jul 01 11:04:40 AM PDT 24
Finished Jul 01 11:04:46 AM PDT 24
Peak memory 211420 kb
Host smart-058cccd1-c7a1-4490-8ac8-73fe3ace3739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237183307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2237183307
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3871361476
Short name T112
Test name
Test status
Simulation time 2527506192 ps
CPU time 9.77 seconds
Started Jul 01 11:04:36 AM PDT 24
Finished Jul 01 11:04:46 AM PDT 24
Peak memory 213480 kb
Host smart-d652e196-8b68-4a66-b924-7ca01d838003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871361476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3871361476
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3314949339
Short name T235
Test name
Test status
Simulation time 847319559 ps
CPU time 16.28 seconds
Started Jul 01 11:04:26 AM PDT 24
Finished Jul 01 11:04:43 AM PDT 24
Peak memory 214440 kb
Host smart-835b305d-6e94-4373-872e-608eb408ffb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314949339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3314949339
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1273927435
Short name T59
Test name
Test status
Simulation time 89304601 ps
CPU time 4.44 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:04:36 AM PDT 24
Peak memory 211372 kb
Host smart-1b294411-a2f9-4c0d-a62d-4b2a66f1ce77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273927435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1273927435
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4239800375
Short name T167
Test name
Test status
Simulation time 2139231747 ps
CPU time 131.99 seconds
Started Jul 01 11:04:33 AM PDT 24
Finished Jul 01 11:06:46 AM PDT 24
Peak memory 237856 kb
Host smart-7d8d8b05-67d2-42f5-a734-04fbffd4b4cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239800375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4239800375
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2631861678
Short name T250
Test name
Test status
Simulation time 2759646472 ps
CPU time 25.29 seconds
Started Jul 01 11:04:24 AM PDT 24
Finished Jul 01 11:04:50 AM PDT 24
Peak memory 211536 kb
Host smart-61f16d94-4dc8-4e91-9fd4-1092f0478068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631861678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2631861678
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2843008580
Short name T351
Test name
Test status
Simulation time 1134657802 ps
CPU time 12.16 seconds
Started Jul 01 11:04:37 AM PDT 24
Finished Jul 01 11:04:49 AM PDT 24
Peak memory 211412 kb
Host smart-b5a28bc7-28b1-49b6-a665-83db63331a08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843008580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2843008580
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3990533402
Short name T303
Test name
Test status
Simulation time 4228938058 ps
CPU time 34.48 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:05:04 AM PDT 24
Peak memory 213392 kb
Host smart-c61bf202-7ea2-4f34-99c3-488b44053831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990533402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3990533402
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.570182428
Short name T13
Test name
Test status
Simulation time 3808892943 ps
CPU time 40.24 seconds
Started Jul 01 11:04:25 AM PDT 24
Finished Jul 01 11:05:06 AM PDT 24
Peak memory 215792 kb
Host smart-c132d9e6-ef2e-47da-ae3e-ff90c3bf8381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570182428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.570182428
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4176752301
Short name T17
Test name
Test status
Simulation time 1691860448 ps
CPU time 14.14 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:04:43 AM PDT 24
Peak memory 211360 kb
Host smart-77f3eb58-6a29-4d80-8898-903d3ae0f81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176752301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4176752301
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4194163202
Short name T241
Test name
Test status
Simulation time 7889817104 ps
CPU time 21.3 seconds
Started Jul 01 11:04:35 AM PDT 24
Finished Jul 01 11:04:57 AM PDT 24
Peak memory 214604 kb
Host smart-dc8c0d99-5a95-4d7e-ac93-df673ccf1fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194163202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4194163202
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.727700096
Short name T128
Test name
Test status
Simulation time 824158654 ps
CPU time 5.26 seconds
Started Jul 01 11:04:34 AM PDT 24
Finished Jul 01 11:04:40 AM PDT 24
Peak memory 211380 kb
Host smart-fbbc3102-6cdd-4771-b577-5bf463834fc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727700096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.727700096
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3130113597
Short name T2
Test name
Test status
Simulation time 13356326607 ps
CPU time 32.6 seconds
Started Jul 01 11:04:34 AM PDT 24
Finished Jul 01 11:05:07 AM PDT 24
Peak memory 214000 kb
Host smart-7fed7aa0-035f-4974-92b0-e7d8f8aa3289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130113597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3130113597
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3644168849
Short name T48
Test name
Test status
Simulation time 12953906057 ps
CPU time 38.18 seconds
Started Jul 01 11:04:27 AM PDT 24
Finished Jul 01 11:05:06 AM PDT 24
Peak memory 217088 kb
Host smart-65adba74-ceee-47e8-a58c-bc082326b9cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644168849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3644168849
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2571634068
Short name T21
Test name
Test status
Simulation time 15253161060 ps
CPU time 4228.56 seconds
Started Jul 01 11:04:24 AM PDT 24
Finished Jul 01 12:14:54 PM PDT 24
Peak memory 224140 kb
Host smart-9d270442-cb9f-4bea-9c03-bdebec2880eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571634068 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2571634068
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1945515179
Short name T354
Test name
Test status
Simulation time 5908040716 ps
CPU time 13.23 seconds
Started Jul 01 11:04:27 AM PDT 24
Finished Jul 01 11:04:41 AM PDT 24
Peak memory 211404 kb
Host smart-5f855071-f174-455d-a415-16ac0e7194b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945515179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1945515179
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3810513866
Short name T191
Test name
Test status
Simulation time 17552622683 ps
CPU time 276.59 seconds
Started Jul 01 11:04:27 AM PDT 24
Finished Jul 01 11:09:04 AM PDT 24
Peak memory 225352 kb
Host smart-b0f35232-152a-46d9-9f6f-888e009c9d1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810513866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3810513866
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3805420780
Short name T339
Test name
Test status
Simulation time 341127023 ps
CPU time 9.2 seconds
Started Jul 01 11:04:36 AM PDT 24
Finished Jul 01 11:04:46 AM PDT 24
Peak memory 211892 kb
Host smart-bae5d141-7ab7-4740-b724-e74deac8b9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805420780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3805420780
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2112036954
Short name T194
Test name
Test status
Simulation time 1626254119 ps
CPU time 14.97 seconds
Started Jul 01 11:04:40 AM PDT 24
Finished Jul 01 11:04:56 AM PDT 24
Peak memory 211424 kb
Host smart-d5d0523f-0ed3-4725-91f0-9573f9529989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112036954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2112036954
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2517386899
Short name T271
Test name
Test status
Simulation time 5807705402 ps
CPU time 34.54 seconds
Started Jul 01 11:04:31 AM PDT 24
Finished Jul 01 11:05:07 AM PDT 24
Peak memory 214576 kb
Host smart-e1bf5256-9545-4ac6-8403-919460617b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517386899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2517386899
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3223914559
Short name T163
Test name
Test status
Simulation time 16343138161 ps
CPU time 54.43 seconds
Started Jul 01 11:04:35 AM PDT 24
Finished Jul 01 11:05:30 AM PDT 24
Peak memory 217160 kb
Host smart-359a03c9-35c0-4b19-9eda-f42154588c08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223914559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3223914559
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3729584857
Short name T340
Test name
Test status
Simulation time 47268957779 ps
CPU time 1759.21 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:34:01 AM PDT 24
Peak memory 230992 kb
Host smart-f39d4e55-da6b-4d8b-b62d-e183018c8689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729584857 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3729584857
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3948293040
Short name T311
Test name
Test status
Simulation time 1741030815 ps
CPU time 14.36 seconds
Started Jul 01 11:04:28 AM PDT 24
Finished Jul 01 11:04:44 AM PDT 24
Peak memory 211348 kb
Host smart-018c4926-aae9-4c28-9411-c7adad1c0323
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948293040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3948293040
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4293279617
Short name T320
Test name
Test status
Simulation time 171654993659 ps
CPU time 402.13 seconds
Started Jul 01 11:04:32 AM PDT 24
Finished Jul 01 11:11:14 AM PDT 24
Peak memory 236756 kb
Host smart-9ef010fd-8e21-45a7-92b9-d8c207e9a15d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293279617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4293279617
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2026178105
Short name T22
Test name
Test status
Simulation time 1032201087 ps
CPU time 13.48 seconds
Started Jul 01 11:04:37 AM PDT 24
Finished Jul 01 11:04:51 AM PDT 24
Peak memory 211860 kb
Host smart-5842418f-9a86-4538-86c1-74122d853cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026178105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2026178105
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.56597560
Short name T295
Test name
Test status
Simulation time 609171528 ps
CPU time 9.11 seconds
Started Jul 01 11:04:39 AM PDT 24
Finished Jul 01 11:04:49 AM PDT 24
Peak memory 211424 kb
Host smart-5eb83b95-ccc9-45bc-9360-edb7705b38fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56597560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.56597560
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3909748404
Short name T308
Test name
Test status
Simulation time 191862572 ps
CPU time 10.44 seconds
Started Jul 01 11:04:25 AM PDT 24
Finished Jul 01 11:04:36 AM PDT 24
Peak memory 213088 kb
Host smart-5d7f6d5c-47a0-4714-a2c8-f44ec736c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909748404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3909748404
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1174325715
Short name T187
Test name
Test status
Simulation time 851415026 ps
CPU time 15.7 seconds
Started Jul 01 11:04:24 AM PDT 24
Finished Jul 01 11:04:41 AM PDT 24
Peak memory 214068 kb
Host smart-1057080c-a69d-403d-9570-3f57b7dcd510
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174325715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1174325715
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2577102551
Short name T148
Test name
Test status
Simulation time 174981775 ps
CPU time 4.31 seconds
Started Jul 01 11:04:38 AM PDT 24
Finished Jul 01 11:04:42 AM PDT 24
Peak memory 211300 kb
Host smart-cf7ee591-54f2-4dfb-a44f-86954dac5420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577102551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2577102551
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3051429500
Short name T5
Test name
Test status
Simulation time 60981067565 ps
CPU time 134.04 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:06:45 AM PDT 24
Peak memory 236828 kb
Host smart-e2c5bdc9-1714-4d21-9f83-c089a59d79d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051429500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3051429500
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1505780290
Short name T110
Test name
Test status
Simulation time 36231124658 ps
CPU time 25.7 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:04:57 AM PDT 24
Peak memory 214720 kb
Host smart-c76400fa-ac5f-4dc2-b6b1-60c694756803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505780290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1505780290
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1810626205
Short name T261
Test name
Test status
Simulation time 2375098537 ps
CPU time 8.95 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:04:40 AM PDT 24
Peak memory 211448 kb
Host smart-3126f2aa-a531-496d-a7d6-86bf64670460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1810626205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1810626205
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1946773300
Short name T218
Test name
Test status
Simulation time 4167523147 ps
CPU time 33.82 seconds
Started Jul 01 11:04:37 AM PDT 24
Finished Jul 01 11:05:12 AM PDT 24
Peak memory 213448 kb
Host smart-f7cf73be-29c9-437b-be56-4d260e076f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946773300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1946773300
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3096444468
Short name T318
Test name
Test status
Simulation time 301733657 ps
CPU time 17.63 seconds
Started Jul 01 11:04:34 AM PDT 24
Finished Jul 01 11:04:52 AM PDT 24
Peak memory 213152 kb
Host smart-3a05e946-a819-4e42-8009-583cf1e568b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096444468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3096444468
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1479435083
Short name T134
Test name
Test status
Simulation time 85589949 ps
CPU time 4.32 seconds
Started Jul 01 11:04:33 AM PDT 24
Finished Jul 01 11:04:38 AM PDT 24
Peak memory 211172 kb
Host smart-0c3a34f6-ddfc-402a-b3c8-f4237719a2a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479435083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1479435083
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3963087763
Short name T229
Test name
Test status
Simulation time 4680452724 ps
CPU time 150.6 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:07:02 AM PDT 24
Peak memory 237820 kb
Host smart-227bef36-778c-48f3-af9e-8fc9e9dd24c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963087763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3963087763
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3200578771
Short name T301
Test name
Test status
Simulation time 12328992632 ps
CPU time 19.76 seconds
Started Jul 01 11:04:29 AM PDT 24
Finished Jul 01 11:04:50 AM PDT 24
Peak memory 212304 kb
Host smart-da215a26-f4ab-4cde-89fc-c2fa02c1c02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200578771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3200578771
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2303637107
Short name T221
Test name
Test status
Simulation time 11682444150 ps
CPU time 9.38 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:04:40 AM PDT 24
Peak memory 211464 kb
Host smart-90b3635d-f25d-4545-891d-41022d2868ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2303637107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2303637107
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3678858513
Short name T168
Test name
Test status
Simulation time 1020692171 ps
CPU time 14.6 seconds
Started Jul 01 11:04:31 AM PDT 24
Finished Jul 01 11:04:46 AM PDT 24
Peak memory 212752 kb
Host smart-43191af7-1a93-408c-aca7-965d06e0ab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678858513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3678858513
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.913894576
Short name T270
Test name
Test status
Simulation time 14239046766 ps
CPU time 75.79 seconds
Started Jul 01 11:04:38 AM PDT 24
Finished Jul 01 11:05:55 AM PDT 24
Peak memory 217016 kb
Host smart-dee537a2-e0bb-4bf8-9b0d-a9812136c164
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913894576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.913894576
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3266729940
Short name T364
Test name
Test status
Simulation time 3750284107 ps
CPU time 16.76 seconds
Started Jul 01 11:04:36 AM PDT 24
Finished Jul 01 11:04:53 AM PDT 24
Peak memory 211404 kb
Host smart-2451a7a0-5365-47cb-9cb4-08d63693cc41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266729940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3266729940
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1312599860
Short name T151
Test name
Test status
Simulation time 3176764050 ps
CPU time 27.49 seconds
Started Jul 01 11:04:35 AM PDT 24
Finished Jul 01 11:05:02 AM PDT 24
Peak memory 212044 kb
Host smart-3f7714f5-2e30-40db-94eb-a3614a007164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312599860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1312599860
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.903735125
Short name T342
Test name
Test status
Simulation time 95999893 ps
CPU time 5.5 seconds
Started Jul 01 11:04:39 AM PDT 24
Finished Jul 01 11:04:45 AM PDT 24
Peak memory 211400 kb
Host smart-75265448-82d0-4e3e-ba41-6acf72d271d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903735125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.903735125
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2521709769
Short name T306
Test name
Test status
Simulation time 2007250833 ps
CPU time 10.17 seconds
Started Jul 01 11:04:30 AM PDT 24
Finished Jul 01 11:04:41 AM PDT 24
Peak memory 213928 kb
Host smart-2df7b1a2-d20c-4559-a564-43f3ba3b1053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521709769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2521709769
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1647048141
Short name T140
Test name
Test status
Simulation time 2128050324 ps
CPU time 39.52 seconds
Started Jul 01 11:04:38 AM PDT 24
Finished Jul 01 11:05:18 AM PDT 24
Peak memory 215768 kb
Host smart-bece5e2b-d35a-4767-9410-36265f7468e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647048141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1647048141
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2406338138
Short name T314
Test name
Test status
Simulation time 1849895877 ps
CPU time 8.45 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:04:51 AM PDT 24
Peak memory 211352 kb
Host smart-81f5d02c-619c-4110-b4dd-317a5aee0aec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406338138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2406338138
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2263220396
Short name T267
Test name
Test status
Simulation time 62902998329 ps
CPU time 510.38 seconds
Started Jul 01 11:04:43 AM PDT 24
Finished Jul 01 11:13:14 AM PDT 24
Peak memory 236836 kb
Host smart-4d602f82-a420-4a9c-afda-10c4c116a2f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263220396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2263220396
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3786845564
Short name T193
Test name
Test status
Simulation time 1026595418 ps
CPU time 15.29 seconds
Started Jul 01 11:04:36 AM PDT 24
Finished Jul 01 11:04:52 AM PDT 24
Peak memory 212576 kb
Host smart-ae263fa4-f9f9-4c43-a2f5-3bc0c2a06aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786845564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3786845564
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2953383725
Short name T312
Test name
Test status
Simulation time 11518112260 ps
CPU time 15.2 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:04:57 AM PDT 24
Peak memory 211436 kb
Host smart-c850fce2-d722-4223-a976-48b02f6267c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953383725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2953383725
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1325749981
Short name T202
Test name
Test status
Simulation time 3335882936 ps
CPU time 26.08 seconds
Started Jul 01 11:04:38 AM PDT 24
Finished Jul 01 11:05:04 AM PDT 24
Peak memory 213736 kb
Host smart-090db650-dc97-4b3e-aa25-df6a1b87e3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325749981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1325749981
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1859196343
Short name T300
Test name
Test status
Simulation time 343310794 ps
CPU time 15.98 seconds
Started Jul 01 11:04:42 AM PDT 24
Finished Jul 01 11:04:59 AM PDT 24
Peak memory 214884 kb
Host smart-b450e467-edf5-454e-937b-bdc11e6373bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859196343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1859196343
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.314766366
Short name T45
Test name
Test status
Simulation time 27657464926 ps
CPU time 1096.15 seconds
Started Jul 01 11:04:37 AM PDT 24
Finished Jul 01 11:22:53 AM PDT 24
Peak memory 235852 kb
Host smart-c7a5c583-1e91-41ff-9481-01bc8cebf975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314766366 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.314766366
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3829386951
Short name T119
Test name
Test status
Simulation time 4371104076 ps
CPU time 16.98 seconds
Started Jul 01 11:03:57 AM PDT 24
Finished Jul 01 11:04:14 AM PDT 24
Peak memory 211380 kb
Host smart-c315f023-f955-4b9f-9651-ac21d14e1d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829386951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3829386951
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1892374670
Short name T176
Test name
Test status
Simulation time 16666786165 ps
CPU time 137.08 seconds
Started Jul 01 11:03:56 AM PDT 24
Finished Jul 01 11:06:14 AM PDT 24
Peak memory 236844 kb
Host smart-6ad0c53c-bf2b-4966-ba7a-98c250685dca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892374670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1892374670
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1880744636
Short name T234
Test name
Test status
Simulation time 13434452635 ps
CPU time 25.81 seconds
Started Jul 01 11:04:21 AM PDT 24
Finished Jul 01 11:04:48 AM PDT 24
Peak memory 212384 kb
Host smart-11735e72-76da-470d-a2ba-37ad0a7fa076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880744636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1880744636
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.720478428
Short name T223
Test name
Test status
Simulation time 1008755962 ps
CPU time 5.67 seconds
Started Jul 01 11:03:55 AM PDT 24
Finished Jul 01 11:04:02 AM PDT 24
Peak memory 211432 kb
Host smart-89aad4f4-e53c-4528-bbb7-12706031013c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=720478428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.720478428
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.233088501
Short name T16
Test name
Test status
Simulation time 5021356127 ps
CPU time 106.89 seconds
Started Jul 01 11:03:56 AM PDT 24
Finished Jul 01 11:05:44 AM PDT 24
Peak memory 238328 kb
Host smart-a0009908-8285-4adb-aa6b-dc37ff6f4982
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233088501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.233088501
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.636191642
Short name T196
Test name
Test status
Simulation time 3507470040 ps
CPU time 34.52 seconds
Started Jul 01 11:04:11 AM PDT 24
Finished Jul 01 11:04:45 AM PDT 24
Peak memory 213280 kb
Host smart-579c60df-c66a-416b-bee3-3ae709f175be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636191642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.636191642
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1095481552
Short name T349
Test name
Test status
Simulation time 14493715033 ps
CPU time 30.33 seconds
Started Jul 01 11:04:13 AM PDT 24
Finished Jul 01 11:04:44 AM PDT 24
Peak memory 214956 kb
Host smart-8293b923-5f20-44f9-bb06-9afb60fbd632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095481552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1095481552
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1334785915
Short name T296
Test name
Test status
Simulation time 253821086 ps
CPU time 4.37 seconds
Started Jul 01 11:04:38 AM PDT 24
Finished Jul 01 11:04:43 AM PDT 24
Peak memory 211236 kb
Host smart-507b786f-d8d4-4cb1-945e-c6125c32c89d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334785915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1334785915
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1300716139
Short name T220
Test name
Test status
Simulation time 1747172890 ps
CPU time 112.09 seconds
Started Jul 01 11:04:39 AM PDT 24
Finished Jul 01 11:06:32 AM PDT 24
Peak memory 228492 kb
Host smart-0ba8db2f-7a24-4923-bba8-394260700d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300716139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1300716139
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3840173247
Short name T47
Test name
Test status
Simulation time 1544449449 ps
CPU time 14.21 seconds
Started Jul 01 11:04:40 AM PDT 24
Finished Jul 01 11:04:55 AM PDT 24
Peak memory 211988 kb
Host smart-7ac0e709-4647-42b5-985c-e14d565ce6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840173247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3840173247
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.735904649
Short name T114
Test name
Test status
Simulation time 692927764 ps
CPU time 8.93 seconds
Started Jul 01 11:04:43 AM PDT 24
Finished Jul 01 11:04:52 AM PDT 24
Peak memory 211052 kb
Host smart-e887baec-978a-4a93-ae17-9580f519d101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735904649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.735904649
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2448206807
Short name T258
Test name
Test status
Simulation time 4434297610 ps
CPU time 34.5 seconds
Started Jul 01 11:04:40 AM PDT 24
Finished Jul 01 11:05:15 AM PDT 24
Peak memory 213432 kb
Host smart-08340071-9dde-4e01-adc4-65bcdc950426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448206807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2448206807
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3621062500
Short name T350
Test name
Test status
Simulation time 23812896692 ps
CPU time 65.81 seconds
Started Jul 01 11:04:35 AM PDT 24
Finished Jul 01 11:05:41 AM PDT 24
Peak memory 217784 kb
Host smart-a356151a-febf-488b-b94c-2c35ace719f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621062500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3621062500
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2400605081
Short name T46
Test name
Test status
Simulation time 113331197519 ps
CPU time 4299.22 seconds
Started Jul 01 11:04:39 AM PDT 24
Finished Jul 01 12:16:19 PM PDT 24
Peak memory 247424 kb
Host smart-58faa516-a00c-4a94-9b5f-ffe95bbdb15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400605081 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2400605081
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1141696034
Short name T136
Test name
Test status
Simulation time 8702136360 ps
CPU time 16.67 seconds
Started Jul 01 11:04:40 AM PDT 24
Finished Jul 01 11:04:57 AM PDT 24
Peak memory 211420 kb
Host smart-14ecd45e-d796-4ecd-88e1-5139747c5611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141696034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1141696034
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1472587937
Short name T147
Test name
Test status
Simulation time 184681081195 ps
CPU time 173.3 seconds
Started Jul 01 11:04:43 AM PDT 24
Finished Jul 01 11:07:37 AM PDT 24
Peak memory 237884 kb
Host smart-43e0544e-a8e2-4fac-a026-04ba4331baa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472587937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1472587937
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3571899923
Short name T335
Test name
Test status
Simulation time 3520149293 ps
CPU time 29.62 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:05:11 AM PDT 24
Peak memory 211980 kb
Host smart-9842240d-856e-40aa-aa10-8d26cf08c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571899923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3571899923
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2835993698
Short name T118
Test name
Test status
Simulation time 1132989637 ps
CPU time 8.76 seconds
Started Jul 01 11:04:37 AM PDT 24
Finished Jul 01 11:04:46 AM PDT 24
Peak memory 211440 kb
Host smart-df73d690-c874-4baf-868b-19fb284d08b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835993698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2835993698
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2352031081
Short name T179
Test name
Test status
Simulation time 1096614870 ps
CPU time 17.16 seconds
Started Jul 01 11:04:42 AM PDT 24
Finished Jul 01 11:04:59 AM PDT 24
Peak memory 211392 kb
Host smart-cd64b8f3-eb5f-4b0b-b2b3-c6b7dbe67689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352031081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2352031081
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.345864723
Short name T317
Test name
Test status
Simulation time 27452085542 ps
CPU time 66.3 seconds
Started Jul 01 11:04:37 AM PDT 24
Finished Jul 01 11:05:44 AM PDT 24
Peak memory 219380 kb
Host smart-ec1a3c18-d072-4e6d-8f99-f45cbfd5b43a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345864723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.345864723
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2798673209
Short name T356
Test name
Test status
Simulation time 232571133900 ps
CPU time 2203.81 seconds
Started Jul 01 11:04:35 AM PDT 24
Finished Jul 01 11:41:20 AM PDT 24
Peak memory 238100 kb
Host smart-783ba58c-09a2-443d-b9c4-9d6a04d92106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798673209 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2798673209
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1443088508
Short name T302
Test name
Test status
Simulation time 825727223 ps
CPU time 9.2 seconds
Started Jul 01 11:04:43 AM PDT 24
Finished Jul 01 11:04:53 AM PDT 24
Peak memory 211396 kb
Host smart-4eab522c-4183-4815-a430-10cb55c5b946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443088508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1443088508
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2639313606
Short name T305
Test name
Test status
Simulation time 93783577594 ps
CPU time 225.46 seconds
Started Jul 01 11:04:42 AM PDT 24
Finished Jul 01 11:08:28 AM PDT 24
Peak memory 235200 kb
Host smart-054d885d-8496-4e1b-8fbe-6949129d1031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639313606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2639313606
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2039775247
Short name T319
Test name
Test status
Simulation time 175879181 ps
CPU time 9.43 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:04:51 AM PDT 24
Peak memory 212132 kb
Host smart-da0c9dfe-4cd3-453c-b289-caaee1f49687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039775247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2039775247
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2148889284
Short name T304
Test name
Test status
Simulation time 4585160060 ps
CPU time 12.85 seconds
Started Jul 01 11:04:43 AM PDT 24
Finished Jul 01 11:04:57 AM PDT 24
Peak memory 211456 kb
Host smart-bea53d29-fa29-4283-8a3c-7b17480e89b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148889284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2148889284
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4199809292
Short name T233
Test name
Test status
Simulation time 16137749977 ps
CPU time 32.87 seconds
Started Jul 01 11:04:40 AM PDT 24
Finished Jul 01 11:05:14 AM PDT 24
Peak memory 214488 kb
Host smart-0d350a73-7018-4145-8b6f-5d37c8fa0a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199809292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4199809292
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3515826602
Short name T27
Test name
Test status
Simulation time 42365166429 ps
CPU time 30.62 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:05:12 AM PDT 24
Peak memory 214740 kb
Host smart-6330d0a7-4b7b-4290-86ca-9b6d2a12064b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515826602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3515826602
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3750924641
Short name T275
Test name
Test status
Simulation time 692776761 ps
CPU time 4.17 seconds
Started Jul 01 11:04:42 AM PDT 24
Finished Jul 01 11:04:47 AM PDT 24
Peak memory 211328 kb
Host smart-77c6e4fb-8306-4df8-baa0-b229e751cfd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750924641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3750924641
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1992455604
Short name T243
Test name
Test status
Simulation time 5086328538 ps
CPU time 119.24 seconds
Started Jul 01 11:04:43 AM PDT 24
Finished Jul 01 11:06:43 AM PDT 24
Peak memory 228556 kb
Host smart-b882ae20-a398-4975-8dc9-d879f585c574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992455604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1992455604
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1368052639
Short name T288
Test name
Test status
Simulation time 724497086 ps
CPU time 9.37 seconds
Started Jul 01 11:04:40 AM PDT 24
Finished Jul 01 11:04:50 AM PDT 24
Peak memory 212412 kb
Host smart-58325996-1d4c-4162-af78-fc5bbf1abc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368052639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1368052639
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2661138099
Short name T216
Test name
Test status
Simulation time 4166699906 ps
CPU time 17.07 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:04:59 AM PDT 24
Peak memory 211472 kb
Host smart-9b31f6c2-b83e-4c71-a2b8-9d6acf6c75bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661138099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2661138099
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.922815241
Short name T158
Test name
Test status
Simulation time 4633705479 ps
CPU time 18.11 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:05:00 AM PDT 24
Peak memory 213864 kb
Host smart-4ad4baf4-950f-4f02-9759-7948a3688f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922815241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.922815241
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2345417339
Short name T143
Test name
Test status
Simulation time 2319900981 ps
CPU time 26.62 seconds
Started Jul 01 11:04:42 AM PDT 24
Finished Jul 01 11:05:09 AM PDT 24
Peak memory 215364 kb
Host smart-71fb0080-18b4-485e-80b9-6881c7e84508
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345417339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2345417339
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3959060869
Short name T276
Test name
Test status
Simulation time 89070379 ps
CPU time 4.12 seconds
Started Jul 01 11:04:43 AM PDT 24
Finished Jul 01 11:04:48 AM PDT 24
Peak memory 211044 kb
Host smart-7d5ab247-e18c-4b71-8673-05b0e9bebb59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959060869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3959060869
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3898549577
Short name T145
Test name
Test status
Simulation time 26545518021 ps
CPU time 138.97 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:07:00 AM PDT 24
Peak memory 233956 kb
Host smart-d8ac80d4-70c2-428a-9308-15b5baf0bfe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898549577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3898549577
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3557096025
Short name T162
Test name
Test status
Simulation time 19502745640 ps
CPU time 34.02 seconds
Started Jul 01 11:04:42 AM PDT 24
Finished Jul 01 11:05:17 AM PDT 24
Peak memory 212184 kb
Host smart-167a37d1-a15e-48b8-8be7-be7ff2ea1c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557096025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3557096025
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2530700736
Short name T138
Test name
Test status
Simulation time 1958064036 ps
CPU time 16.31 seconds
Started Jul 01 11:04:42 AM PDT 24
Finished Jul 01 11:04:59 AM PDT 24
Peak memory 211388 kb
Host smart-756b0a58-74fb-41de-8b53-d61d0e6ef8ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530700736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2530700736
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2460599214
Short name T152
Test name
Test status
Simulation time 755982385 ps
CPU time 10.6 seconds
Started Jul 01 11:04:41 AM PDT 24
Finished Jul 01 11:04:52 AM PDT 24
Peak memory 214076 kb
Host smart-7fddf4f6-85d2-4b41-9b1b-6fb031f2b579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460599214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2460599214
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3877846888
Short name T297
Test name
Test status
Simulation time 378282307 ps
CPU time 20.73 seconds
Started Jul 01 11:04:42 AM PDT 24
Finished Jul 01 11:05:03 AM PDT 24
Peak memory 213944 kb
Host smart-6b27c1f0-0cd3-445c-a3a6-4bd2958dbabd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877846888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3877846888
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3593780511
Short name T347
Test name
Test status
Simulation time 1229504852 ps
CPU time 8.72 seconds
Started Jul 01 11:04:55 AM PDT 24
Finished Jul 01 11:05:04 AM PDT 24
Peak memory 211236 kb
Host smart-b03bdd60-f780-4fc1-a8d5-b7c28a66ee6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593780511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3593780511
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1647688342
Short name T323
Test name
Test status
Simulation time 4438032362 ps
CPU time 145.13 seconds
Started Jul 01 11:04:46 AM PDT 24
Finished Jul 01 11:07:12 AM PDT 24
Peak memory 213572 kb
Host smart-526def9a-22f5-434c-846a-e966f56c147c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647688342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1647688342
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3084706739
Short name T109
Test name
Test status
Simulation time 39022416647 ps
CPU time 30.86 seconds
Started Jul 01 11:04:45 AM PDT 24
Finished Jul 01 11:05:16 AM PDT 24
Peak memory 212292 kb
Host smart-2e25fc9c-3a84-4dba-80e9-520368b3e381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084706739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3084706739
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.760012666
Short name T344
Test name
Test status
Simulation time 1803790766 ps
CPU time 15.2 seconds
Started Jul 01 11:04:47 AM PDT 24
Finished Jul 01 11:05:03 AM PDT 24
Peak memory 211396 kb
Host smart-1663ee83-d72f-4205-a5ec-89b181bb366c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=760012666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.760012666
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.314916380
Short name T71
Test name
Test status
Simulation time 184266040 ps
CPU time 10.1 seconds
Started Jul 01 11:04:46 AM PDT 24
Finished Jul 01 11:04:57 AM PDT 24
Peak memory 212868 kb
Host smart-1585c480-b6c8-4eb1-ab32-14be711e1836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314916380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.314916380
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1895061282
Short name T260
Test name
Test status
Simulation time 35015824882 ps
CPU time 83.64 seconds
Started Jul 01 11:04:49 AM PDT 24
Finished Jul 01 11:06:13 AM PDT 24
Peak memory 219412 kb
Host smart-435ac1b3-e4f6-4f91-872a-f6c65333a0a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895061282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1895061282
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3084421570
Short name T360
Test name
Test status
Simulation time 1398582708 ps
CPU time 12.6 seconds
Started Jul 01 11:04:46 AM PDT 24
Finished Jul 01 11:05:00 AM PDT 24
Peak memory 211372 kb
Host smart-3711f1dd-93c3-48a5-b933-f4868a6f1770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084421570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3084421570
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2012916980
Short name T203
Test name
Test status
Simulation time 131624205237 ps
CPU time 311.2 seconds
Started Jul 01 11:04:46 AM PDT 24
Finished Jul 01 11:09:58 AM PDT 24
Peak memory 236816 kb
Host smart-aff30dc1-f2c3-49d9-b00c-b95932aeb7a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012916980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2012916980
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.484584003
Short name T264
Test name
Test status
Simulation time 4286197050 ps
CPU time 36.52 seconds
Started Jul 01 11:04:44 AM PDT 24
Finished Jul 01 11:05:21 AM PDT 24
Peak memory 211892 kb
Host smart-18d2b1f1-ba09-47ac-a3f3-3b2c27bb0e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484584003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.484584003
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2093389527
Short name T268
Test name
Test status
Simulation time 187003600 ps
CPU time 5.52 seconds
Started Jul 01 11:04:47 AM PDT 24
Finished Jul 01 11:04:53 AM PDT 24
Peak memory 211408 kb
Host smart-8cec5a7c-80f5-4606-9136-da7a6a564f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093389527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2093389527
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1182664657
Short name T280
Test name
Test status
Simulation time 2018106281 ps
CPU time 13.03 seconds
Started Jul 01 11:04:44 AM PDT 24
Finished Jul 01 11:04:58 AM PDT 24
Peak memory 213160 kb
Host smart-4e6b25be-d6bf-43c4-8880-96d9615db9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182664657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1182664657
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.278711924
Short name T263
Test name
Test status
Simulation time 9909695646 ps
CPU time 108.2 seconds
Started Jul 01 11:04:46 AM PDT 24
Finished Jul 01 11:06:35 AM PDT 24
Peak memory 219436 kb
Host smart-44ff9b1f-3c3a-48a0-8e52-2314a29dcb2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278711924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.278711924
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.538321586
Short name T227
Test name
Test status
Simulation time 1001178527 ps
CPU time 10.45 seconds
Started Jul 01 11:04:54 AM PDT 24
Finished Jul 01 11:05:05 AM PDT 24
Peak memory 211300 kb
Host smart-69938d9f-8ceb-4e54-965b-c56a037f2ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538321586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.538321586
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1215373792
Short name T42
Test name
Test status
Simulation time 9790702815 ps
CPU time 165.08 seconds
Started Jul 01 11:04:47 AM PDT 24
Finished Jul 01 11:07:33 AM PDT 24
Peak memory 225380 kb
Host smart-5d954be3-6286-4de6-8ee2-ca9a33e7911f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215373792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1215373792
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.786617316
Short name T355
Test name
Test status
Simulation time 20088477572 ps
CPU time 26.91 seconds
Started Jul 01 11:04:55 AM PDT 24
Finished Jul 01 11:05:23 AM PDT 24
Peak memory 212108 kb
Host smart-8763d74c-ac0a-4b36-a43d-a5a106dea981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786617316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.786617316
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1598156734
Short name T255
Test name
Test status
Simulation time 195056000 ps
CPU time 5.85 seconds
Started Jul 01 11:04:48 AM PDT 24
Finished Jul 01 11:04:54 AM PDT 24
Peak memory 211396 kb
Host smart-e868cc76-74a3-4460-ba49-4b35f8d8d72e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1598156734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1598156734
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.884649610
Short name T192
Test name
Test status
Simulation time 371803870 ps
CPU time 10.43 seconds
Started Jul 01 11:04:55 AM PDT 24
Finished Jul 01 11:05:06 AM PDT 24
Peak memory 213024 kb
Host smart-4a52e46f-49d3-4e33-8645-b544746f5620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884649610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.884649610
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1605994756
Short name T150
Test name
Test status
Simulation time 940669097 ps
CPU time 30.86 seconds
Started Jul 01 11:04:47 AM PDT 24
Finished Jul 01 11:05:19 AM PDT 24
Peak memory 216488 kb
Host smart-5ec8e32a-8e02-46a0-81d0-6b349112bbcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605994756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1605994756
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.228383721
Short name T57
Test name
Test status
Simulation time 9028233761 ps
CPU time 16.92 seconds
Started Jul 01 11:04:51 AM PDT 24
Finished Jul 01 11:05:08 AM PDT 24
Peak memory 211428 kb
Host smart-090f3c1e-9840-4643-9062-5ac938967960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228383721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.228383721
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1464702046
Short name T32
Test name
Test status
Simulation time 30783683309 ps
CPU time 359.3 seconds
Started Jul 01 11:04:52 AM PDT 24
Finished Jul 01 11:10:52 AM PDT 24
Peak memory 236832 kb
Host smart-8601fb47-2590-4ec1-8487-677ad33b1c67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464702046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1464702046
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1611623101
Short name T332
Test name
Test status
Simulation time 25427528957 ps
CPU time 28.22 seconds
Started Jul 01 11:04:52 AM PDT 24
Finished Jul 01 11:05:21 AM PDT 24
Peak memory 212220 kb
Host smart-7f44bd7d-c627-4e9a-890e-03c42c0d3b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611623101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1611623101
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2927557814
Short name T281
Test name
Test status
Simulation time 3831074463 ps
CPU time 15.38 seconds
Started Jul 01 11:04:52 AM PDT 24
Finished Jul 01 11:05:08 AM PDT 24
Peak memory 211484 kb
Host smart-9a20237a-b569-432c-ad17-f9d105429a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927557814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2927557814
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1242533122
Short name T343
Test name
Test status
Simulation time 10439834979 ps
CPU time 28.12 seconds
Started Jul 01 11:04:51 AM PDT 24
Finished Jul 01 11:05:20 AM PDT 24
Peak memory 212424 kb
Host smart-1234ed10-cc04-432d-9fcf-0fde6774d1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242533122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1242533122
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3635666041
Short name T205
Test name
Test status
Simulation time 179193709 ps
CPU time 10.36 seconds
Started Jul 01 11:04:50 AM PDT 24
Finished Jul 01 11:05:01 AM PDT 24
Peak memory 214240 kb
Host smart-6352782f-ff33-4558-b483-82f10a5a5bc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635666041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3635666041
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1083252205
Short name T327
Test name
Test status
Simulation time 6115353469 ps
CPU time 7.94 seconds
Started Jul 01 11:04:54 AM PDT 24
Finished Jul 01 11:05:03 AM PDT 24
Peak memory 211404 kb
Host smart-d37cf398-cadf-4420-8a9c-4b1c3bec875f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083252205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1083252205
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3782722420
Short name T269
Test name
Test status
Simulation time 51969147782 ps
CPU time 169.54 seconds
Started Jul 01 11:04:51 AM PDT 24
Finished Jul 01 11:07:41 AM PDT 24
Peak memory 236084 kb
Host smart-31f70cb1-27de-4928-baa1-51f8fc13911c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782722420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3782722420
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3716187581
Short name T39
Test name
Test status
Simulation time 725239452 ps
CPU time 9.37 seconds
Started Jul 01 11:04:52 AM PDT 24
Finished Jul 01 11:05:02 AM PDT 24
Peak memory 212328 kb
Host smart-52443afb-6676-41b4-b092-013e1524ce78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716187581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3716187581
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3965514403
Short name T326
Test name
Test status
Simulation time 1571686368 ps
CPU time 14.35 seconds
Started Jul 01 11:04:54 AM PDT 24
Finished Jul 01 11:05:09 AM PDT 24
Peak memory 211396 kb
Host smart-972dbaf9-e8e4-4403-98ea-ffba01e2b1bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965514403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3965514403
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2764100285
Short name T214
Test name
Test status
Simulation time 727687960 ps
CPU time 10.27 seconds
Started Jul 01 11:04:52 AM PDT 24
Finished Jul 01 11:05:03 AM PDT 24
Peak memory 213692 kb
Host smart-bb634c77-3d14-4415-a077-701a0e15e617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764100285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2764100285
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3796366373
Short name T215
Test name
Test status
Simulation time 7236924764 ps
CPU time 36.24 seconds
Started Jul 01 11:04:52 AM PDT 24
Finished Jul 01 11:05:30 AM PDT 24
Peak memory 213588 kb
Host smart-49f4a4f9-33f7-4b77-9dda-27220b8a30a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796366373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3796366373
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3928075228
Short name T185
Test name
Test status
Simulation time 332915857 ps
CPU time 4.39 seconds
Started Jul 01 11:04:02 AM PDT 24
Finished Jul 01 11:04:06 AM PDT 24
Peak memory 211316 kb
Host smart-8cf7d7e7-13b3-4c22-a3a4-d4aef5e65d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928075228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3928075228
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1851145686
Short name T34
Test name
Test status
Simulation time 69342610033 ps
CPU time 332.51 seconds
Started Jul 01 11:03:56 AM PDT 24
Finished Jul 01 11:09:28 AM PDT 24
Peak memory 238100 kb
Host smart-839528f5-7720-4739-ae34-b40a1abe599d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851145686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1851145686
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3748665135
Short name T186
Test name
Test status
Simulation time 694567356 ps
CPU time 9.53 seconds
Started Jul 01 11:03:55 AM PDT 24
Finished Jul 01 11:04:05 AM PDT 24
Peak memory 212008 kb
Host smart-5eac3a40-dfe3-4c39-a63a-b45834467e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748665135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3748665135
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.927743506
Short name T160
Test name
Test status
Simulation time 740119147 ps
CPU time 10.09 seconds
Started Jul 01 11:04:12 AM PDT 24
Finished Jul 01 11:04:22 AM PDT 24
Peak memory 211416 kb
Host smart-4dd11943-c7ba-4c3d-868a-daf30a8a3ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927743506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.927743506
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.634267700
Short name T24
Test name
Test status
Simulation time 7222992465 ps
CPU time 107.1 seconds
Started Jul 01 11:03:58 AM PDT 24
Finished Jul 01 11:05:46 AM PDT 24
Peak memory 236612 kb
Host smart-e123a4c4-7382-424b-a5fb-f1c8f5ebf80d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634267700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.634267700
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3494194715
Short name T273
Test name
Test status
Simulation time 14854027920 ps
CPU time 34.38 seconds
Started Jul 01 11:03:58 AM PDT 24
Finished Jul 01 11:04:33 AM PDT 24
Peak memory 213600 kb
Host smart-3ff6ac6e-c190-4ba3-9a24-f3b26fc89608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494194715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3494194715
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2095341063
Short name T180
Test name
Test status
Simulation time 12956555234 ps
CPU time 39.37 seconds
Started Jul 01 11:04:09 AM PDT 24
Finished Jul 01 11:04:49 AM PDT 24
Peak memory 214444 kb
Host smart-50874a4a-d2c8-470f-b5a5-951ef98a89e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095341063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2095341063
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3402317932
Short name T262
Test name
Test status
Simulation time 171654593 ps
CPU time 4.33 seconds
Started Jul 01 11:04:56 AM PDT 24
Finished Jul 01 11:05:01 AM PDT 24
Peak memory 211300 kb
Host smart-bfb4172e-96f1-4d08-8cc7-c3dbdf50d5fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402317932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3402317932
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3462650305
Short name T328
Test name
Test status
Simulation time 38572529177 ps
CPU time 362.19 seconds
Started Jul 01 11:05:09 AM PDT 24
Finished Jul 01 11:11:12 AM PDT 24
Peak memory 239112 kb
Host smart-4f1490c8-2de0-4021-9b99-b633fe13f13e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462650305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3462650305
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1306614308
Short name T182
Test name
Test status
Simulation time 692792348 ps
CPU time 9.38 seconds
Started Jul 01 11:04:58 AM PDT 24
Finished Jul 01 11:05:07 AM PDT 24
Peak memory 212048 kb
Host smart-e122a41d-c1e1-42eb-a0c9-731be3254d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306614308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1306614308
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.83027213
Short name T195
Test name
Test status
Simulation time 2958024895 ps
CPU time 13.23 seconds
Started Jul 01 11:04:55 AM PDT 24
Finished Jul 01 11:05:09 AM PDT 24
Peak memory 211356 kb
Host smart-49685115-1ff4-4011-9b2e-3cb17ac670e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83027213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.83027213
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2700500078
Short name T341
Test name
Test status
Simulation time 8185944380 ps
CPU time 21.47 seconds
Started Jul 01 11:04:52 AM PDT 24
Finished Jul 01 11:05:15 AM PDT 24
Peak memory 214228 kb
Host smart-810790c0-5522-4e15-bd28-1164f31b38fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700500078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2700500078
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2382418766
Short name T153
Test name
Test status
Simulation time 28341537142 ps
CPU time 24.87 seconds
Started Jul 01 11:04:57 AM PDT 24
Finished Jul 01 11:05:22 AM PDT 24
Peak memory 215016 kb
Host smart-916e1e51-1c84-46f3-b143-94de918a9813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382418766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2382418766
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1505466264
Short name T141
Test name
Test status
Simulation time 6532013401 ps
CPU time 14.88 seconds
Started Jul 01 11:05:01 AM PDT 24
Finished Jul 01 11:05:17 AM PDT 24
Peak memory 211412 kb
Host smart-39232d57-00f7-49c2-9cc8-6e830e0f7c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505466264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1505466264
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3103174126
Short name T126
Test name
Test status
Simulation time 8254243009 ps
CPU time 175.1 seconds
Started Jul 01 11:04:57 AM PDT 24
Finished Jul 01 11:07:52 AM PDT 24
Peak memory 237888 kb
Host smart-40ac9904-257a-4bd4-9323-9cd58e2dc07a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103174126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3103174126
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3883791386
Short name T113
Test name
Test status
Simulation time 579464576 ps
CPU time 14 seconds
Started Jul 01 11:04:55 AM PDT 24
Finished Jul 01 11:05:10 AM PDT 24
Peak memory 211924 kb
Host smart-70cb9a95-49da-4895-b2f9-0fb639df00af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883791386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3883791386
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.468709755
Short name T245
Test name
Test status
Simulation time 134675726 ps
CPU time 6.17 seconds
Started Jul 01 11:05:12 AM PDT 24
Finished Jul 01 11:05:18 AM PDT 24
Peak memory 211420 kb
Host smart-a1090ef4-ecf8-4c01-9efd-0b0ebb0bd26a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468709755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.468709755
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3286421229
Short name T316
Test name
Test status
Simulation time 1345177052 ps
CPU time 18.43 seconds
Started Jul 01 11:04:56 AM PDT 24
Finished Jul 01 11:05:15 AM PDT 24
Peak memory 213580 kb
Host smart-dbeecb5e-3be5-4776-bb4f-86c556960d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286421229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3286421229
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.550654416
Short name T265
Test name
Test status
Simulation time 56454324879 ps
CPU time 29.39 seconds
Started Jul 01 11:04:57 AM PDT 24
Finished Jul 01 11:05:26 AM PDT 24
Peak memory 214316 kb
Host smart-8242df9c-25f5-4b18-8f83-8e870f46d6ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550654416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.550654416
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3981488795
Short name T315
Test name
Test status
Simulation time 2734117169 ps
CPU time 10.57 seconds
Started Jul 01 11:05:03 AM PDT 24
Finished Jul 01 11:05:14 AM PDT 24
Peak memory 211316 kb
Host smart-b4912189-772f-4bc6-b0c5-fe6123d2003f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981488795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3981488795
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1457083600
Short name T106
Test name
Test status
Simulation time 63249072675 ps
CPU time 204.68 seconds
Started Jul 01 11:04:59 AM PDT 24
Finished Jul 01 11:08:24 AM PDT 24
Peak memory 213672 kb
Host smart-65e5dc95-3a85-47bb-81ef-fc85141c0e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457083600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1457083600
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.555046084
Short name T38
Test name
Test status
Simulation time 638052212 ps
CPU time 9.61 seconds
Started Jul 01 11:04:56 AM PDT 24
Finished Jul 01 11:05:06 AM PDT 24
Peak memory 212036 kb
Host smart-13b1e2a6-46e0-453d-b3d1-314ebd80e9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555046084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.555046084
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1563416565
Short name T174
Test name
Test status
Simulation time 659446677 ps
CPU time 9.66 seconds
Started Jul 01 11:05:03 AM PDT 24
Finished Jul 01 11:05:13 AM PDT 24
Peak memory 211400 kb
Host smart-50bcc5e3-d8d8-4811-9c53-5f3b8a09c951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563416565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1563416565
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2415564653
Short name T142
Test name
Test status
Simulation time 10837596744 ps
CPU time 33.58 seconds
Started Jul 01 11:05:00 AM PDT 24
Finished Jul 01 11:05:34 AM PDT 24
Peak memory 213800 kb
Host smart-b00f83a2-70d9-4118-8f8a-6f90fda9b192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415564653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2415564653
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.163829921
Short name T183
Test name
Test status
Simulation time 6252488502 ps
CPU time 55.84 seconds
Started Jul 01 11:05:02 AM PDT 24
Finished Jul 01 11:05:58 AM PDT 24
Peak memory 216408 kb
Host smart-03ca79a9-d40d-4aae-a7d1-5fafd7d8d357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163829921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.163829921
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1608813593
Short name T35
Test name
Test status
Simulation time 54831535304 ps
CPU time 2205.82 seconds
Started Jul 01 11:04:56 AM PDT 24
Finished Jul 01 11:41:42 AM PDT 24
Peak memory 235500 kb
Host smart-90d03da6-10aa-48cf-8264-754b65f4268e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608813593 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1608813593
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.262809575
Short name T310
Test name
Test status
Simulation time 86653135 ps
CPU time 4.37 seconds
Started Jul 01 11:05:13 AM PDT 24
Finished Jul 01 11:05:18 AM PDT 24
Peak memory 211372 kb
Host smart-fc7b0359-9c67-439f-811b-416c38e4a00c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262809575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.262809575
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1983815118
Short name T12
Test name
Test status
Simulation time 23083671532 ps
CPU time 213.28 seconds
Started Jul 01 11:05:00 AM PDT 24
Finished Jul 01 11:08:33 AM PDT 24
Peak memory 212592 kb
Host smart-0830aaaf-f75e-4143-8a51-db61950bf33f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983815118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1983815118
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1891415250
Short name T253
Test name
Test status
Simulation time 2916891955 ps
CPU time 25.31 seconds
Started Jul 01 11:05:02 AM PDT 24
Finished Jul 01 11:05:28 AM PDT 24
Peak memory 211480 kb
Host smart-9997437e-73be-4e43-9474-0d86dbb3626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891415250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1891415250
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1478343056
Short name T197
Test name
Test status
Simulation time 4891066719 ps
CPU time 12.53 seconds
Started Jul 01 11:05:01 AM PDT 24
Finished Jul 01 11:05:14 AM PDT 24
Peak memory 211452 kb
Host smart-5d630ba6-75ff-4ac6-9a09-f08809cd0785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478343056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1478343056
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.857366059
Short name T244
Test name
Test status
Simulation time 498551227 ps
CPU time 10.51 seconds
Started Jul 01 11:05:01 AM PDT 24
Finished Jul 01 11:05:12 AM PDT 24
Peak memory 213100 kb
Host smart-e2dd4816-bdac-4f9a-af90-5b31f7ebad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857366059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.857366059
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.941806201
Short name T361
Test name
Test status
Simulation time 817747309 ps
CPU time 13.62 seconds
Started Jul 01 11:05:07 AM PDT 24
Finished Jul 01 11:05:21 AM PDT 24
Peak memory 214268 kb
Host smart-159318f0-7543-48e2-a1f4-9c00d5bb289d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941806201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.941806201
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2737657093
Short name T117
Test name
Test status
Simulation time 2888616382 ps
CPU time 12.66 seconds
Started Jul 01 11:05:15 AM PDT 24
Finished Jul 01 11:05:28 AM PDT 24
Peak memory 211412 kb
Host smart-79081873-2dfb-40b2-8694-ca6c4cf4b54e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737657093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2737657093
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.562306841
Short name T41
Test name
Test status
Simulation time 1323640662 ps
CPU time 84.72 seconds
Started Jul 01 11:05:05 AM PDT 24
Finished Jul 01 11:06:31 AM PDT 24
Peak memory 232732 kb
Host smart-b653cea6-cce1-411b-83af-1c6d24593a9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562306841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.562306841
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1748074744
Short name T129
Test name
Test status
Simulation time 14546834244 ps
CPU time 20.92 seconds
Started Jul 01 11:05:05 AM PDT 24
Finished Jul 01 11:05:26 AM PDT 24
Peak memory 212416 kb
Host smart-162bcb0d-4fda-49d7-af60-e9a43a8b2110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748074744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1748074744
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.836382862
Short name T338
Test name
Test status
Simulation time 4792701190 ps
CPU time 12.46 seconds
Started Jul 01 11:05:11 AM PDT 24
Finished Jul 01 11:05:24 AM PDT 24
Peak memory 211468 kb
Host smart-71e8a991-f989-43ea-997f-0e733ec1bd91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836382862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.836382862
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1775967472
Short name T257
Test name
Test status
Simulation time 5942919642 ps
CPU time 35.34 seconds
Started Jul 01 11:05:03 AM PDT 24
Finished Jul 01 11:05:39 AM PDT 24
Peak memory 214152 kb
Host smart-9073d8ff-c7a1-4a2f-b36e-a9eb109b8c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775967472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1775967472
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.430352874
Short name T120
Test name
Test status
Simulation time 4174840007 ps
CPU time 16.23 seconds
Started Jul 01 11:05:13 AM PDT 24
Finished Jul 01 11:05:30 AM PDT 24
Peak memory 211472 kb
Host smart-67e0c775-4820-4a95-b95b-7b94044cffc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430352874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.430352874
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2228617292
Short name T43
Test name
Test status
Simulation time 281995209124 ps
CPU time 1671.8 seconds
Started Jul 01 11:05:06 AM PDT 24
Finished Jul 01 11:32:58 AM PDT 24
Peak memory 236164 kb
Host smart-5b745760-d84a-4d97-b8cb-fc924cedd447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228617292 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2228617292
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1280906544
Short name T18
Test name
Test status
Simulation time 7613839566 ps
CPU time 16.09 seconds
Started Jul 01 11:05:04 AM PDT 24
Finished Jul 01 11:05:21 AM PDT 24
Peak memory 211404 kb
Host smart-7dca515e-acec-4656-b5c9-f6f974bcdfbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280906544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1280906544
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1132416447
Short name T33
Test name
Test status
Simulation time 201196394595 ps
CPU time 239.56 seconds
Started Jul 01 11:05:07 AM PDT 24
Finished Jul 01 11:09:07 AM PDT 24
Peak memory 237920 kb
Host smart-4e77131f-d609-4364-9a10-e89dd13b0cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132416447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1132416447
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1924257781
Short name T272
Test name
Test status
Simulation time 9467301365 ps
CPU time 21.49 seconds
Started Jul 01 11:05:08 AM PDT 24
Finished Jul 01 11:05:30 AM PDT 24
Peak memory 212224 kb
Host smart-7c84c5fc-660b-4b20-8a87-cd6ecd39a9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924257781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1924257781
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3394994662
Short name T28
Test name
Test status
Simulation time 6347305847 ps
CPU time 9.75 seconds
Started Jul 01 11:05:11 AM PDT 24
Finished Jul 01 11:05:22 AM PDT 24
Peak memory 211348 kb
Host smart-00a7d3c7-072f-4f82-90e3-105ab86360ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394994662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3394994662
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4139375576
Short name T293
Test name
Test status
Simulation time 1503674516 ps
CPU time 21.26 seconds
Started Jul 01 11:05:07 AM PDT 24
Finished Jul 01 11:05:28 AM PDT 24
Peak memory 213216 kb
Host smart-cd0c910e-43d2-4a54-ba24-2c19f940aff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139375576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4139375576
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2234892738
Short name T325
Test name
Test status
Simulation time 340014721814 ps
CPU time 3075.28 seconds
Started Jul 01 11:05:12 AM PDT 24
Finished Jul 01 11:56:28 AM PDT 24
Peak memory 244088 kb
Host smart-93371510-73d1-4cfb-a601-46cad36bff07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234892738 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2234892738
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2647121832
Short name T58
Test name
Test status
Simulation time 5273787612 ps
CPU time 12.19 seconds
Started Jul 01 11:05:06 AM PDT 24
Finished Jul 01 11:05:19 AM PDT 24
Peak memory 211388 kb
Host smart-0bda3c30-5859-45e0-91ea-e574a7b31c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647121832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2647121832
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2185319698
Short name T331
Test name
Test status
Simulation time 89286768978 ps
CPU time 145.89 seconds
Started Jul 01 11:05:17 AM PDT 24
Finished Jul 01 11:07:44 AM PDT 24
Peak memory 228628 kb
Host smart-75d5e9ba-eb13-48fb-b76a-1f97bf4e0bc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185319698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2185319698
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4109637759
Short name T173
Test name
Test status
Simulation time 168546744 ps
CPU time 9.7 seconds
Started Jul 01 11:05:21 AM PDT 24
Finished Jul 01 11:05:31 AM PDT 24
Peak memory 211840 kb
Host smart-616f026a-f201-41aa-aaf5-c4cea5f404b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109637759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4109637759
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3843547970
Short name T292
Test name
Test status
Simulation time 1944250684 ps
CPU time 11.22 seconds
Started Jul 01 11:05:05 AM PDT 24
Finished Jul 01 11:05:17 AM PDT 24
Peak memory 211420 kb
Host smart-e0110e15-0e2b-4fcb-9d77-0d0cbf650fe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843547970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3843547970
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3843209257
Short name T149
Test name
Test status
Simulation time 1124741536 ps
CPU time 9.95 seconds
Started Jul 01 11:05:08 AM PDT 24
Finished Jul 01 11:05:19 AM PDT 24
Peak memory 213340 kb
Host smart-1f7d812a-e9e2-4b6e-acdf-98e9439690f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843209257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3843209257
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.690244888
Short name T72
Test name
Test status
Simulation time 659686616 ps
CPU time 9.23 seconds
Started Jul 01 11:05:06 AM PDT 24
Finished Jul 01 11:05:16 AM PDT 24
Peak memory 211408 kb
Host smart-8cbe6346-e011-465a-b562-455dab409775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690244888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.690244888
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2002652511
Short name T156
Test name
Test status
Simulation time 8383576826 ps
CPU time 16.65 seconds
Started Jul 01 11:05:13 AM PDT 24
Finished Jul 01 11:05:30 AM PDT 24
Peak memory 211456 kb
Host smart-ba3e586b-c337-4eb6-af92-16ff8b6ab646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002652511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2002652511
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2909197148
Short name T237
Test name
Test status
Simulation time 172166807193 ps
CPU time 381.09 seconds
Started Jul 01 11:05:08 AM PDT 24
Finished Jul 01 11:11:30 AM PDT 24
Peak memory 236532 kb
Host smart-1b6bc083-a3a7-4daa-ae06-b8731e8cff1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909197148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2909197148
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2478691849
Short name T248
Test name
Test status
Simulation time 2459213094 ps
CPU time 24.38 seconds
Started Jul 01 11:05:14 AM PDT 24
Finished Jul 01 11:05:38 AM PDT 24
Peak memory 212044 kb
Host smart-285695af-941c-4aba-b91c-1af57280c588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478691849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2478691849
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.543056615
Short name T283
Test name
Test status
Simulation time 15273091113 ps
CPU time 17.48 seconds
Started Jul 01 11:05:07 AM PDT 24
Finished Jul 01 11:05:25 AM PDT 24
Peak memory 211464 kb
Host smart-faaecea4-8c78-4be7-b82f-3f7b7805dea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543056615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.543056615
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3835291782
Short name T60
Test name
Test status
Simulation time 1536231375 ps
CPU time 18.93 seconds
Started Jul 01 11:05:13 AM PDT 24
Finished Jul 01 11:05:32 AM PDT 24
Peak memory 213348 kb
Host smart-517d1112-c873-456b-b6ea-797600c33e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835291782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3835291782
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4248013094
Short name T363
Test name
Test status
Simulation time 41544757443 ps
CPU time 37.68 seconds
Started Jul 01 11:05:12 AM PDT 24
Finished Jul 01 11:05:50 AM PDT 24
Peak memory 216072 kb
Host smart-5b12d6dc-66d5-41fd-8e07-fba9e9e8374a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248013094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4248013094
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.926624658
Short name T44
Test name
Test status
Simulation time 101592491024 ps
CPU time 4727.48 seconds
Started Jul 01 11:05:13 AM PDT 24
Finished Jul 01 12:24:01 PM PDT 24
Peak memory 235868 kb
Host smart-79f52d9f-5b83-4595-a3b7-982225f860c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926624658 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.926624658
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4240446802
Short name T184
Test name
Test status
Simulation time 175349210 ps
CPU time 4.17 seconds
Started Jul 01 11:05:10 AM PDT 24
Finished Jul 01 11:05:15 AM PDT 24
Peak memory 211244 kb
Host smart-efd9dfe4-a1a2-4329-8c76-fdb129665b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240446802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4240446802
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3702640807
Short name T329
Test name
Test status
Simulation time 51904298699 ps
CPU time 140.25 seconds
Started Jul 01 11:05:09 AM PDT 24
Finished Jul 01 11:07:29 AM PDT 24
Peak memory 236976 kb
Host smart-b04fcb8f-1572-49b6-b046-db8c5c2c3124
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702640807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3702640807
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4294950724
Short name T188
Test name
Test status
Simulation time 1312792975 ps
CPU time 10.76 seconds
Started Jul 01 11:05:11 AM PDT 24
Finished Jul 01 11:05:23 AM PDT 24
Peak memory 211960 kb
Host smart-cfa5734b-7a14-4199-ba76-42bfeed21fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294950724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4294950724
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.833565057
Short name T289
Test name
Test status
Simulation time 8510066357 ps
CPU time 17.47 seconds
Started Jul 01 11:05:17 AM PDT 24
Finished Jul 01 11:05:34 AM PDT 24
Peak memory 211568 kb
Host smart-bf6f003f-088f-42d2-ad13-adfdc9a1f8b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833565057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.833565057
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.4099132369
Short name T170
Test name
Test status
Simulation time 3882300321 ps
CPU time 30.56 seconds
Started Jul 01 11:05:13 AM PDT 24
Finished Jul 01 11:05:44 AM PDT 24
Peak memory 213164 kb
Host smart-57a3fd96-b4a1-4e02-b657-ce0e22a5e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099132369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.4099132369
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.834145041
Short name T132
Test name
Test status
Simulation time 51864847441 ps
CPU time 54.49 seconds
Started Jul 01 11:05:11 AM PDT 24
Finished Jul 01 11:06:06 AM PDT 24
Peak memory 215452 kb
Host smart-c88d6972-ace5-4866-857a-2a79b2f2887e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834145041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.834145041
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2815415123
Short name T259
Test name
Test status
Simulation time 1756167318 ps
CPU time 9.7 seconds
Started Jul 01 11:05:10 AM PDT 24
Finished Jul 01 11:05:20 AM PDT 24
Peak memory 211252 kb
Host smart-30019442-4c99-4f45-9925-7a24418954c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815415123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2815415123
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.381802980
Short name T40
Test name
Test status
Simulation time 19031042721 ps
CPU time 248.16 seconds
Started Jul 01 11:05:21 AM PDT 24
Finished Jul 01 11:09:30 AM PDT 24
Peak memory 234008 kb
Host smart-afbc7be1-e842-4737-bb7f-11f99731e0c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381802980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.381802980
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4029540417
Short name T285
Test name
Test status
Simulation time 4333821638 ps
CPU time 22.42 seconds
Started Jul 01 11:05:25 AM PDT 24
Finished Jul 01 11:05:48 AM PDT 24
Peak memory 212228 kb
Host smart-77cf58a3-3136-43f9-b469-e5507cb4c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029540417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4029540417
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3609896469
Short name T116
Test name
Test status
Simulation time 7895763704 ps
CPU time 16.27 seconds
Started Jul 01 11:05:24 AM PDT 24
Finished Jul 01 11:05:41 AM PDT 24
Peak memory 211476 kb
Host smart-8c4f66df-6701-4f0c-a5e9-557b3c2fa1ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609896469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3609896469
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1352780299
Short name T324
Test name
Test status
Simulation time 6123818045 ps
CPU time 30.18 seconds
Started Jul 01 11:05:10 AM PDT 24
Finished Jul 01 11:05:40 AM PDT 24
Peak memory 213800 kb
Host smart-3e1c7cee-97d7-4d88-8cad-1822db7cadfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352780299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1352780299
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.297155250
Short name T211
Test name
Test status
Simulation time 104680670 ps
CPU time 10.51 seconds
Started Jul 01 11:05:11 AM PDT 24
Finished Jul 01 11:05:22 AM PDT 24
Peak memory 211288 kb
Host smart-065f0db8-bfab-46bc-8c21-e42145c3569e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297155250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.297155250
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1862952415
Short name T334
Test name
Test status
Simulation time 1886111333 ps
CPU time 10.43 seconds
Started Jul 01 11:04:12 AM PDT 24
Finished Jul 01 11:04:23 AM PDT 24
Peak memory 211360 kb
Host smart-9fd6e1e6-6bce-4770-a111-e43e929e86bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862952415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1862952415
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1346582075
Short name T282
Test name
Test status
Simulation time 28702487333 ps
CPU time 293.26 seconds
Started Jul 01 11:04:04 AM PDT 24
Finished Jul 01 11:08:57 AM PDT 24
Peak memory 237996 kb
Host smart-e2e7a776-272e-4c07-9d33-160f29a6314d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346582075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1346582075
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.275167072
Short name T246
Test name
Test status
Simulation time 341162778 ps
CPU time 10 seconds
Started Jul 01 11:04:16 AM PDT 24
Finished Jul 01 11:04:26 AM PDT 24
Peak memory 212036 kb
Host smart-75ce2296-cb29-4e2f-9a77-f5d993b690bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275167072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.275167072
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.794021137
Short name T348
Test name
Test status
Simulation time 97879525 ps
CPU time 5.48 seconds
Started Jul 01 11:04:23 AM PDT 24
Finished Jul 01 11:04:29 AM PDT 24
Peak memory 211416 kb
Host smart-d8e254a8-2e8e-46f7-9f5e-45f83afe9c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794021137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.794021137
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1614533037
Short name T165
Test name
Test status
Simulation time 1758148020 ps
CPU time 12.03 seconds
Started Jul 01 11:04:07 AM PDT 24
Finished Jul 01 11:04:20 AM PDT 24
Peak memory 213472 kb
Host smart-ffac99af-43ca-4cd4-8e7d-9ba7888bca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614533037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1614533037
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1170652149
Short name T209
Test name
Test status
Simulation time 25361990072 ps
CPU time 57.19 seconds
Started Jul 01 11:04:02 AM PDT 24
Finished Jul 01 11:04:59 AM PDT 24
Peak memory 219408 kb
Host smart-08842fd7-cd4b-46e0-ab3b-128fd17ba827
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170652149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1170652149
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1251110673
Short name T6
Test name
Test status
Simulation time 2128077049 ps
CPU time 16.42 seconds
Started Jul 01 11:04:03 AM PDT 24
Finished Jul 01 11:04:19 AM PDT 24
Peak memory 211356 kb
Host smart-2fcd9512-6698-40c9-a215-ff002141fc17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251110673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1251110673
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2218054739
Short name T299
Test name
Test status
Simulation time 15692809750 ps
CPU time 236.39 seconds
Started Jul 01 11:04:17 AM PDT 24
Finished Jul 01 11:08:14 AM PDT 24
Peak memory 237920 kb
Host smart-03e77565-f063-4748-8a86-ef82701d915a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218054739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2218054739
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1531302524
Short name T322
Test name
Test status
Simulation time 1230763069 ps
CPU time 15.17 seconds
Started Jul 01 11:04:01 AM PDT 24
Finished Jul 01 11:04:16 AM PDT 24
Peak memory 212900 kb
Host smart-c449f594-51fc-4b09-adc0-48a460325025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531302524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1531302524
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1667942098
Short name T121
Test name
Test status
Simulation time 821688675 ps
CPU time 10.34 seconds
Started Jul 01 11:04:04 AM PDT 24
Finished Jul 01 11:04:14 AM PDT 24
Peak memory 211372 kb
Host smart-b6065715-08c8-42d0-8c4c-9fb3200cbea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667942098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1667942098
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1551537020
Short name T199
Test name
Test status
Simulation time 1482594452 ps
CPU time 18.55 seconds
Started Jul 01 11:04:13 AM PDT 24
Finished Jul 01 11:04:32 AM PDT 24
Peak memory 211844 kb
Host smart-3996d8e3-6235-4208-b981-e6f321ad1f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551537020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1551537020
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1818842330
Short name T353
Test name
Test status
Simulation time 2436795931 ps
CPU time 21.75 seconds
Started Jul 01 11:04:02 AM PDT 24
Finished Jul 01 11:04:24 AM PDT 24
Peak memory 213820 kb
Host smart-9da69bdb-c34f-48a5-b3f0-317efc67da4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818842330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1818842330
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.121451973
Short name T154
Test name
Test status
Simulation time 6260565787 ps
CPU time 14.31 seconds
Started Jul 01 11:04:29 AM PDT 24
Finished Jul 01 11:04:45 AM PDT 24
Peak memory 211400 kb
Host smart-4ac10bf5-0109-481c-b0de-cf01a9f0d771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121451973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.121451973
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3821208635
Short name T200
Test name
Test status
Simulation time 94265184942 ps
CPU time 437.74 seconds
Started Jul 01 11:04:22 AM PDT 24
Finished Jul 01 11:11:40 AM PDT 24
Peak memory 212952 kb
Host smart-dddb3f18-b915-4e42-bd65-203c932e4923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821208635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3821208635
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3889948911
Short name T161
Test name
Test status
Simulation time 1929898166 ps
CPU time 13.56 seconds
Started Jul 01 11:04:06 AM PDT 24
Finished Jul 01 11:04:20 AM PDT 24
Peak memory 212072 kb
Host smart-f83d95af-e35b-4518-9d2b-2f36f36c7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889948911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3889948911
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.236201797
Short name T277
Test name
Test status
Simulation time 376794543 ps
CPU time 5.41 seconds
Started Jul 01 11:04:07 AM PDT 24
Finished Jul 01 11:04:13 AM PDT 24
Peak memory 211388 kb
Host smart-323e3cbc-caf5-4d70-a31f-1a21810366c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236201797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.236201797
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3328954436
Short name T252
Test name
Test status
Simulation time 43705010631 ps
CPU time 57.7 seconds
Started Jul 01 11:04:01 AM PDT 24
Finished Jul 01 11:04:59 AM PDT 24
Peak memory 219388 kb
Host smart-cb924e7e-4fd4-4cf5-9ceb-fa320e4bfc15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328954436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3328954436
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2251670187
Short name T198
Test name
Test status
Simulation time 5392661916 ps
CPU time 12.49 seconds
Started Jul 01 11:04:26 AM PDT 24
Finished Jul 01 11:04:40 AM PDT 24
Peak memory 211408 kb
Host smart-510d415f-1440-4004-910e-b36934573e8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251670187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2251670187
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.336310377
Short name T236
Test name
Test status
Simulation time 12019669755 ps
CPU time 88.4 seconds
Started Jul 01 11:04:08 AM PDT 24
Finished Jul 01 11:05:37 AM PDT 24
Peak memory 228036 kb
Host smart-3dbb0956-4552-409f-82f7-bda58a5f02b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336310377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.336310377
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.19540037
Short name T171
Test name
Test status
Simulation time 2724665341 ps
CPU time 25.72 seconds
Started Jul 01 11:04:06 AM PDT 24
Finished Jul 01 11:04:32 AM PDT 24
Peak memory 212740 kb
Host smart-0851b946-9206-41bf-afea-8e0241c13224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19540037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.19540037
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.775202554
Short name T8
Test name
Test status
Simulation time 16088301632 ps
CPU time 15.53 seconds
Started Jul 01 11:04:15 AM PDT 24
Finished Jul 01 11:04:31 AM PDT 24
Peak memory 211440 kb
Host smart-3105ac4e-55eb-471d-ad79-731fb798f341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775202554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.775202554
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3461410589
Short name T309
Test name
Test status
Simulation time 191519857 ps
CPU time 10.45 seconds
Started Jul 01 11:04:09 AM PDT 24
Finished Jul 01 11:04:20 AM PDT 24
Peak memory 213800 kb
Host smart-3a7009d5-7683-49f1-ad1b-74da464f1ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461410589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3461410589
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3946845907
Short name T294
Test name
Test status
Simulation time 1975391698 ps
CPU time 26.36 seconds
Started Jul 01 11:04:23 AM PDT 24
Finished Jul 01 11:04:51 AM PDT 24
Peak memory 216772 kb
Host smart-641d5a69-8ee7-4db8-85f3-7074c8767487
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946845907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3946845907
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1524772697
Short name T133
Test name
Test status
Simulation time 469621546 ps
CPU time 7.24 seconds
Started Jul 01 11:04:07 AM PDT 24
Finished Jul 01 11:04:15 AM PDT 24
Peak memory 211368 kb
Host smart-fe9b591e-f2dc-473c-89e0-9be9ea24961d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524772697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1524772697
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1583165443
Short name T346
Test name
Test status
Simulation time 8674231044 ps
CPU time 135.15 seconds
Started Jul 01 11:04:24 AM PDT 24
Finished Jul 01 11:06:40 AM PDT 24
Peak memory 228656 kb
Host smart-72b26461-478d-4de2-94de-8a5dbb9e6b3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583165443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1583165443
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4166453440
Short name T254
Test name
Test status
Simulation time 15069407004 ps
CPU time 24.09 seconds
Started Jul 01 11:04:08 AM PDT 24
Finished Jul 01 11:04:33 AM PDT 24
Peak memory 212372 kb
Host smart-bb816308-4512-465c-843f-8f7f58a94a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166453440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4166453440
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4277551187
Short name T178
Test name
Test status
Simulation time 1564524903 ps
CPU time 9.95 seconds
Started Jul 01 11:04:23 AM PDT 24
Finished Jul 01 11:04:34 AM PDT 24
Peak memory 211348 kb
Host smart-6444de8b-e9f5-4b15-b235-467a3faea8f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277551187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4277551187
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3092831878
Short name T115
Test name
Test status
Simulation time 508644270 ps
CPU time 14.16 seconds
Started Jul 01 11:04:17 AM PDT 24
Finished Jul 01 11:04:32 AM PDT 24
Peak memory 213520 kb
Host smart-992c3da9-37b3-4b4a-80f1-ee3a72c67673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092831878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3092831878
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3699320602
Short name T219
Test name
Test status
Simulation time 1882867286 ps
CPU time 22.16 seconds
Started Jul 01 11:04:09 AM PDT 24
Finished Jul 01 11:04:31 AM PDT 24
Peak memory 211412 kb
Host smart-0bc332e1-737c-4915-b75d-ae2c082fa4cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699320602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3699320602
Directory /workspace/9.rom_ctrl_stress_all/latest
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