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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.35 96.89 92.42 97.67 100.00 98.62 97.45 98.37


Total test records in report: 467
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T99 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1167401929 Jul 01 04:32:01 PM PDT 24 Jul 01 04:32:17 PM PDT 24 1160493681 ps
T100 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.856339980 Jul 01 04:32:13 PM PDT 24 Jul 01 04:45:31 PM PDT 24 20557126995 ps
T101 /workspace/coverage/default/3.rom_ctrl_smoke.820464378 Jul 01 04:31:54 PM PDT 24 Jul 01 04:32:15 PM PDT 24 360837039 ps
T102 /workspace/coverage/default/38.rom_ctrl_smoke.99208539 Jul 01 04:32:23 PM PDT 24 Jul 01 04:32:49 PM PDT 24 644187701 ps
T103 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2854469765 Jul 01 04:31:52 PM PDT 24 Jul 01 04:35:32 PM PDT 24 8446551985 ps
T104 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2652543469 Jul 01 04:32:15 PM PDT 24 Jul 01 04:35:04 PM PDT 24 18906943751 ps
T105 /workspace/coverage/default/38.rom_ctrl_alert_test.2582482023 Jul 01 04:32:26 PM PDT 24 Jul 01 04:32:56 PM PDT 24 18517229135 ps
T311 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4065162809 Jul 01 04:32:18 PM PDT 24 Jul 01 04:32:46 PM PDT 24 1164271150 ps
T312 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3485318776 Jul 01 04:31:55 PM PDT 24 Jul 01 04:37:19 PM PDT 24 45608655237 ps
T41 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2560057816 Jul 01 04:31:52 PM PDT 24 Jul 01 05:09:13 PM PDT 24 67176320231 ps
T313 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2648590426 Jul 01 04:31:59 PM PDT 24 Jul 01 04:32:18 PM PDT 24 347603743 ps
T314 /workspace/coverage/default/2.rom_ctrl_stress_all.3950056210 Jul 01 04:31:35 PM PDT 24 Jul 01 04:32:08 PM PDT 24 1589447530 ps
T315 /workspace/coverage/default/9.rom_ctrl_smoke.2676060816 Jul 01 04:31:52 PM PDT 24 Jul 01 04:32:29 PM PDT 24 6023982465 ps
T316 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.808032530 Jul 01 04:32:17 PM PDT 24 Jul 01 04:32:42 PM PDT 24 2123222104 ps
T317 /workspace/coverage/default/16.rom_ctrl_stress_all.553052563 Jul 01 04:32:00 PM PDT 24 Jul 01 04:32:46 PM PDT 24 9090322771 ps
T318 /workspace/coverage/default/19.rom_ctrl_alert_test.3932939627 Jul 01 04:32:19 PM PDT 24 Jul 01 04:32:43 PM PDT 24 599851294 ps
T319 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1330264076 Jul 01 04:32:23 PM PDT 24 Jul 01 04:32:59 PM PDT 24 7014786869 ps
T320 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3160204593 Jul 01 04:32:23 PM PDT 24 Jul 01 04:40:38 PM PDT 24 196469006521 ps
T321 /workspace/coverage/default/26.rom_ctrl_smoke.448913091 Jul 01 04:32:10 PM PDT 24 Jul 01 04:32:51 PM PDT 24 64207160313 ps
T18 /workspace/coverage/default/3.rom_ctrl_sec_cm.2881335403 Jul 01 04:31:54 PM PDT 24 Jul 01 04:33:03 PM PDT 24 2705136767 ps
T322 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4204781142 Jul 01 04:31:54 PM PDT 24 Jul 01 04:32:10 PM PDT 24 375686033 ps
T323 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2937363740 Jul 01 04:31:50 PM PDT 24 Jul 01 04:32:10 PM PDT 24 1278779166 ps
T324 /workspace/coverage/default/30.rom_ctrl_smoke.213420334 Jul 01 04:32:14 PM PDT 24 Jul 01 04:32:33 PM PDT 24 187217467 ps
T25 /workspace/coverage/default/0.rom_ctrl_sec_cm.2189838564 Jul 01 04:31:46 PM PDT 24 Jul 01 04:33:38 PM PDT 24 256559794 ps
T325 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3301178107 Jul 01 04:32:48 PM PDT 24 Jul 01 04:33:22 PM PDT 24 2882141182 ps
T326 /workspace/coverage/default/24.rom_ctrl_alert_test.374072455 Jul 01 04:32:11 PM PDT 24 Jul 01 04:32:32 PM PDT 24 27047391012 ps
T327 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.175707081 Jul 01 04:32:20 PM PDT 24 Jul 01 04:32:45 PM PDT 24 6355276324 ps
T328 /workspace/coverage/default/10.rom_ctrl_alert_test.921140582 Jul 01 04:32:01 PM PDT 24 Jul 01 04:32:20 PM PDT 24 874860217 ps
T329 /workspace/coverage/default/47.rom_ctrl_stress_all.4138406760 Jul 01 04:32:25 PM PDT 24 Jul 01 04:32:54 PM PDT 24 390223153 ps
T330 /workspace/coverage/default/49.rom_ctrl_alert_test.1819779555 Jul 01 04:32:42 PM PDT 24 Jul 01 04:33:00 PM PDT 24 89004964 ps
T331 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.603087423 Jul 01 04:32:14 PM PDT 24 Jul 01 04:32:37 PM PDT 24 4998026687 ps
T332 /workspace/coverage/default/34.rom_ctrl_stress_all.2366168269 Jul 01 04:32:26 PM PDT 24 Jul 01 04:33:45 PM PDT 24 12158255535 ps
T333 /workspace/coverage/default/17.rom_ctrl_stress_all.3536728659 Jul 01 04:32:04 PM PDT 24 Jul 01 04:32:23 PM PDT 24 593779220 ps
T334 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3390821116 Jul 01 04:31:37 PM PDT 24 Jul 01 04:36:11 PM PDT 24 132920957950 ps
T335 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.722285633 Jul 01 04:31:45 PM PDT 24 Jul 01 04:37:15 PM PDT 24 87744867477 ps
T336 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2274641416 Jul 01 04:32:28 PM PDT 24 Jul 01 04:33:00 PM PDT 24 6646593307 ps
T115 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.303479500 Jul 01 04:32:26 PM PDT 24 Jul 01 05:21:54 PM PDT 24 869493134931 ps
T337 /workspace/coverage/default/21.rom_ctrl_alert_test.1245861135 Jul 01 04:32:02 PM PDT 24 Jul 01 04:32:17 PM PDT 24 686687109 ps
T338 /workspace/coverage/default/22.rom_ctrl_stress_all.1396133245 Jul 01 04:32:03 PM PDT 24 Jul 01 04:32:28 PM PDT 24 4148306098 ps
T339 /workspace/coverage/default/2.rom_ctrl_smoke.1031020715 Jul 01 04:31:38 PM PDT 24 Jul 01 04:32:07 PM PDT 24 1331165619 ps
T340 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3344974254 Jul 01 04:32:07 PM PDT 24 Jul 01 04:32:27 PM PDT 24 1506705354 ps
T26 /workspace/coverage/default/1.rom_ctrl_sec_cm.4151563307 Jul 01 04:31:37 PM PDT 24 Jul 01 04:32:51 PM PDT 24 1796611218 ps
T341 /workspace/coverage/default/6.rom_ctrl_smoke.2191398796 Jul 01 04:31:48 PM PDT 24 Jul 01 04:32:21 PM PDT 24 6582164528 ps
T342 /workspace/coverage/default/17.rom_ctrl_alert_test.44974461 Jul 01 04:32:04 PM PDT 24 Jul 01 04:32:17 PM PDT 24 417191949 ps
T343 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3851407082 Jul 01 04:32:22 PM PDT 24 Jul 01 04:32:58 PM PDT 24 6901034716 ps
T344 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1650039095 Jul 01 04:32:27 PM PDT 24 Jul 01 04:34:35 PM PDT 24 4043362852 ps
T345 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2334234065 Jul 01 04:32:13 PM PDT 24 Jul 01 04:32:33 PM PDT 24 2629800244 ps
T346 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2170996739 Jul 01 04:31:37 PM PDT 24 Jul 01 04:32:04 PM PDT 24 7749822814 ps
T347 /workspace/coverage/default/2.rom_ctrl_alert_test.211789837 Jul 01 04:31:54 PM PDT 24 Jul 01 04:32:12 PM PDT 24 524547422 ps
T348 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3069576886 Jul 01 04:32:17 PM PDT 24 Jul 01 04:33:01 PM PDT 24 3841780385 ps
T349 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2086353674 Jul 01 04:32:23 PM PDT 24 Jul 01 04:33:11 PM PDT 24 13296766018 ps
T350 /workspace/coverage/default/5.rom_ctrl_smoke.4056299508 Jul 01 04:31:56 PM PDT 24 Jul 01 04:32:23 PM PDT 24 9174927230 ps
T351 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.958963278 Jul 01 04:32:16 PM PDT 24 Jul 01 04:32:44 PM PDT 24 2691321470 ps
T352 /workspace/coverage/default/31.rom_ctrl_alert_test.19045941 Jul 01 04:32:24 PM PDT 24 Jul 01 04:32:54 PM PDT 24 9335604474 ps
T353 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2604615108 Jul 01 04:32:16 PM PDT 24 Jul 01 04:32:38 PM PDT 24 266008037 ps
T354 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2172919360 Jul 01 04:32:17 PM PDT 24 Jul 01 04:38:02 PM PDT 24 34494947171 ps
T355 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.783473656 Jul 01 04:32:00 PM PDT 24 Jul 01 04:32:24 PM PDT 24 1777713688 ps
T356 /workspace/coverage/default/12.rom_ctrl_stress_all.744612968 Jul 01 04:32:06 PM PDT 24 Jul 01 04:32:24 PM PDT 24 716245997 ps
T357 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4146423284 Jul 01 04:31:59 PM PDT 24 Jul 01 04:36:12 PM PDT 24 20690705395 ps
T358 /workspace/coverage/default/34.rom_ctrl_alert_test.4175340648 Jul 01 04:32:10 PM PDT 24 Jul 01 04:32:30 PM PDT 24 1287179298 ps
T359 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2185330684 Jul 01 04:32:04 PM PDT 24 Jul 01 04:32:26 PM PDT 24 519335902 ps
T360 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2081949298 Jul 01 04:32:20 PM PDT 24 Jul 01 04:32:46 PM PDT 24 3512394174 ps
T361 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1389175732 Jul 01 04:32:23 PM PDT 24 Jul 01 04:32:47 PM PDT 24 313479139 ps
T362 /workspace/coverage/default/7.rom_ctrl_smoke.1305510995 Jul 01 04:31:50 PM PDT 24 Jul 01 04:32:11 PM PDT 24 192324445 ps
T363 /workspace/coverage/default/40.rom_ctrl_alert_test.460642251 Jul 01 04:32:19 PM PDT 24 Jul 01 04:32:39 PM PDT 24 168217041 ps
T364 /workspace/coverage/default/7.rom_ctrl_alert_test.2581332927 Jul 01 04:32:01 PM PDT 24 Jul 01 04:32:27 PM PDT 24 2154787074 ps
T365 /workspace/coverage/default/32.rom_ctrl_stress_all.3763216139 Jul 01 04:32:21 PM PDT 24 Jul 01 04:33:10 PM PDT 24 5277912035 ps
T366 /workspace/coverage/default/47.rom_ctrl_smoke.1324044431 Jul 01 04:32:29 PM PDT 24 Jul 01 04:32:57 PM PDT 24 2236495062 ps
T367 /workspace/coverage/default/14.rom_ctrl_stress_all.777179641 Jul 01 04:32:01 PM PDT 24 Jul 01 04:33:16 PM PDT 24 14141503369 ps
T368 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1892279527 Jul 01 04:32:21 PM PDT 24 Jul 01 04:32:51 PM PDT 24 695927284 ps
T369 /workspace/coverage/default/4.rom_ctrl_stress_all.1914103055 Jul 01 04:31:56 PM PDT 24 Jul 01 04:32:29 PM PDT 24 4522140851 ps
T370 /workspace/coverage/default/20.rom_ctrl_smoke.4246709867 Jul 01 04:32:18 PM PDT 24 Jul 01 04:32:55 PM PDT 24 2502850241 ps
T59 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2810338685 Jul 01 04:27:54 PM PDT 24 Jul 01 04:28:15 PM PDT 24 5604834677 ps
T60 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3178613895 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:19 PM PDT 24 975727018 ps
T56 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1756145092 Jul 01 04:27:43 PM PDT 24 Jul 01 04:28:39 PM PDT 24 1948541763 ps
T371 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.601941208 Jul 01 04:27:53 PM PDT 24 Jul 01 04:28:13 PM PDT 24 1279353102 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.119596816 Jul 01 04:27:45 PM PDT 24 Jul 01 04:28:07 PM PDT 24 1350110107 ps
T70 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3568395052 Jul 01 04:27:49 PM PDT 24 Jul 01 04:28:46 PM PDT 24 23341926437 ps
T106 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2310833941 Jul 01 04:27:50 PM PDT 24 Jul 01 04:28:08 PM PDT 24 4768374780 ps
T111 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3998378385 Jul 01 04:27:50 PM PDT 24 Jul 01 04:28:52 PM PDT 24 34853375001 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4091388983 Jul 01 04:27:34 PM PDT 24 Jul 01 04:27:50 PM PDT 24 520944477 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.111712639 Jul 01 04:27:32 PM PDT 24 Jul 01 04:27:59 PM PDT 24 3296045757 ps
T107 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2733996462 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:16 PM PDT 24 2417461415 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1276463023 Jul 01 04:27:41 PM PDT 24 Jul 01 04:28:06 PM PDT 24 2062658503 ps
T375 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3121188861 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:17 PM PDT 24 6582042114 ps
T57 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.236966948 Jul 01 04:27:37 PM PDT 24 Jul 01 04:28:37 PM PDT 24 7128535831 ps
T58 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2167650724 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:53 PM PDT 24 3626017244 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3898921130 Jul 01 04:27:56 PM PDT 24 Jul 01 04:28:11 PM PDT 24 992603560 ps
T116 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2429768412 Jul 01 04:27:56 PM PDT 24 Jul 01 04:29:15 PM PDT 24 1023038839 ps
T71 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.919861837 Jul 01 04:27:47 PM PDT 24 Jul 01 04:28:03 PM PDT 24 682578050 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2002772610 Jul 01 04:27:33 PM PDT 24 Jul 01 04:27:55 PM PDT 24 7929040744 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2727889909 Jul 01 04:27:33 PM PDT 24 Jul 01 04:27:55 PM PDT 24 1369816021 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2798460833 Jul 01 04:27:53 PM PDT 24 Jul 01 04:28:06 PM PDT 24 1426388702 ps
T379 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4000654219 Jul 01 04:27:58 PM PDT 24 Jul 01 04:28:16 PM PDT 24 4599033750 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2621955703 Jul 01 04:27:56 PM PDT 24 Jul 01 04:28:10 PM PDT 24 846514190 ps
T108 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.64945073 Jul 01 04:27:51 PM PDT 24 Jul 01 04:28:29 PM PDT 24 4171397996 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1861372312 Jul 01 04:27:37 PM PDT 24 Jul 01 04:28:05 PM PDT 24 8375628590 ps
T382 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1907909319 Jul 01 04:27:43 PM PDT 24 Jul 01 04:28:00 PM PDT 24 2345951965 ps
T73 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3400781406 Jul 01 04:27:42 PM PDT 24 Jul 01 04:28:56 PM PDT 24 12131139039 ps
T109 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1785110065 Jul 01 04:27:49 PM PDT 24 Jul 01 04:28:02 PM PDT 24 882896122 ps
T117 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4237295325 Jul 01 04:27:40 PM PDT 24 Jul 01 04:29:02 PM PDT 24 451237749 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3254955864 Jul 01 04:27:39 PM PDT 24 Jul 01 04:27:59 PM PDT 24 970286652 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3648292459 Jul 01 04:27:45 PM PDT 24 Jul 01 04:28:09 PM PDT 24 4917112146 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3907805104 Jul 01 04:27:51 PM PDT 24 Jul 01 04:28:07 PM PDT 24 1955698768 ps
T74 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1234499815 Jul 01 04:27:48 PM PDT 24 Jul 01 04:28:26 PM PDT 24 8322058313 ps
T75 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1489092483 Jul 01 04:27:45 PM PDT 24 Jul 01 04:28:07 PM PDT 24 2552887684 ps
T386 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3743527411 Jul 01 04:27:43 PM PDT 24 Jul 01 04:28:08 PM PDT 24 5095281566 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.861430954 Jul 01 04:28:06 PM PDT 24 Jul 01 04:28:19 PM PDT 24 86563493 ps
T76 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3512938247 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:14 PM PDT 24 347331447 ps
T113 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1370984916 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:32 PM PDT 24 2255314771 ps
T119 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1193065931 Jul 01 04:27:50 PM PDT 24 Jul 01 04:29:08 PM PDT 24 1173425044 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3652236502 Jul 01 04:27:46 PM PDT 24 Jul 01 04:27:59 PM PDT 24 85730270 ps
T77 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1263117504 Jul 01 04:27:41 PM PDT 24 Jul 01 04:28:06 PM PDT 24 2076246405 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2206343016 Jul 01 04:27:51 PM PDT 24 Jul 01 04:28:44 PM PDT 24 13148239417 ps
T388 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3362449717 Jul 01 04:27:49 PM PDT 24 Jul 01 04:28:09 PM PDT 24 19234131812 ps
T120 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.976556159 Jul 01 04:27:58 PM PDT 24 Jul 01 04:29:22 PM PDT 24 8157477511 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1661912226 Jul 01 04:27:44 PM PDT 24 Jul 01 04:28:10 PM PDT 24 8555909779 ps
T390 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1393887275 Jul 01 04:27:49 PM PDT 24 Jul 01 04:28:03 PM PDT 24 1709029743 ps
T391 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1469328973 Jul 01 04:27:40 PM PDT 24 Jul 01 04:27:57 PM PDT 24 1716346353 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.434207255 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:18 PM PDT 24 389815685 ps
T393 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2918797994 Jul 01 04:27:59 PM PDT 24 Jul 01 04:28:15 PM PDT 24 596924319 ps
T394 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2372438428 Jul 01 04:27:56 PM PDT 24 Jul 01 04:28:16 PM PDT 24 1661030670 ps
T395 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3895781072 Jul 01 04:27:59 PM PDT 24 Jul 01 04:28:20 PM PDT 24 5624479386 ps
T396 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4231929193 Jul 01 04:27:40 PM PDT 24 Jul 01 04:28:02 PM PDT 24 5249663496 ps
T397 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3596189555 Jul 01 04:27:54 PM PDT 24 Jul 01 04:28:14 PM PDT 24 1835612895 ps
T398 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2861720086 Jul 01 04:27:59 PM PDT 24 Jul 01 04:28:25 PM PDT 24 16411595429 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.616140267 Jul 01 04:27:54 PM PDT 24 Jul 01 04:28:09 PM PDT 24 1737793698 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3023184286 Jul 01 04:27:58 PM PDT 24 Jul 01 04:28:24 PM PDT 24 12303780719 ps
T401 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1966526665 Jul 01 04:27:54 PM PDT 24 Jul 01 04:28:15 PM PDT 24 8149775145 ps
T121 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.706015512 Jul 01 04:27:55 PM PDT 24 Jul 01 04:28:42 PM PDT 24 1144137425 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1308174177 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:16 PM PDT 24 5446343440 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4222042428 Jul 01 04:27:37 PM PDT 24 Jul 01 04:27:58 PM PDT 24 2160423566 ps
T404 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1038620977 Jul 01 04:28:07 PM PDT 24 Jul 01 04:28:28 PM PDT 24 1126420395 ps
T123 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2162015261 Jul 01 04:27:50 PM PDT 24 Jul 01 04:29:11 PM PDT 24 3651388098 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3614831912 Jul 01 04:27:40 PM PDT 24 Jul 01 04:27:59 PM PDT 24 1307102211 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1591088175 Jul 01 04:27:56 PM PDT 24 Jul 01 04:28:09 PM PDT 24 85617873 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.489033541 Jul 01 04:27:42 PM PDT 24 Jul 01 04:28:06 PM PDT 24 2431882049 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3045812433 Jul 01 04:27:43 PM PDT 24 Jul 01 04:28:10 PM PDT 24 3643333366 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3472614198 Jul 01 04:27:50 PM PDT 24 Jul 01 04:28:17 PM PDT 24 658481634 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2293437326 Jul 01 04:27:37 PM PDT 24 Jul 01 04:28:01 PM PDT 24 4092917830 ps
T410 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1745990249 Jul 01 04:27:48 PM PDT 24 Jul 01 04:28:06 PM PDT 24 1009933454 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2374684915 Jul 01 04:27:34 PM PDT 24 Jul 01 04:27:49 PM PDT 24 89187543 ps
T85 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4061378150 Jul 01 04:28:00 PM PDT 24 Jul 01 04:29:03 PM PDT 24 12660632755 ps
T124 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2176807744 Jul 01 04:27:35 PM PDT 24 Jul 01 04:28:26 PM PDT 24 1418539306 ps
T86 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3649216460 Jul 01 04:27:46 PM PDT 24 Jul 01 04:28:54 PM PDT 24 22810635535 ps
T125 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4290665597 Jul 01 04:27:38 PM PDT 24 Jul 01 04:28:27 PM PDT 24 155835168 ps
T412 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2734964578 Jul 01 04:27:50 PM PDT 24 Jul 01 04:28:01 PM PDT 24 334374690 ps
T114 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2335639223 Jul 01 04:27:56 PM PDT 24 Jul 01 04:29:02 PM PDT 24 7466758526 ps
T87 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.645982518 Jul 01 04:27:58 PM PDT 24 Jul 01 04:28:34 PM PDT 24 1512970137 ps
T118 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1020469522 Jul 01 04:27:59 PM PDT 24 Jul 01 04:29:16 PM PDT 24 1038421450 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3804450852 Jul 01 04:27:59 PM PDT 24 Jul 01 04:28:33 PM PDT 24 1182098831 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2868989998 Jul 01 04:27:49 PM PDT 24 Jul 01 04:28:44 PM PDT 24 3519585987 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2602542830 Jul 01 04:27:46 PM PDT 24 Jul 01 04:28:09 PM PDT 24 2168787821 ps
T414 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1929958437 Jul 01 04:27:53 PM PDT 24 Jul 01 04:28:11 PM PDT 24 6163548514 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2590584882 Jul 01 04:27:51 PM PDT 24 Jul 01 04:28:02 PM PDT 24 638811012 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2463498462 Jul 01 04:27:48 PM PDT 24 Jul 01 04:28:34 PM PDT 24 3643362600 ps
T416 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.355204612 Jul 01 04:27:54 PM PDT 24 Jul 01 04:28:08 PM PDT 24 1888638666 ps
T417 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1139105696 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:14 PM PDT 24 1909058926 ps
T418 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2330197303 Jul 01 04:27:46 PM PDT 24 Jul 01 04:28:34 PM PDT 24 911646942 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.30080068 Jul 01 04:27:37 PM PDT 24 Jul 01 04:27:53 PM PDT 24 1719632773 ps
T420 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1659504590 Jul 01 04:27:57 PM PDT 24 Jul 01 04:29:21 PM PDT 24 7345272578 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3653059451 Jul 01 04:28:09 PM PDT 24 Jul 01 04:28:23 PM PDT 24 318267327 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4113982717 Jul 01 04:27:43 PM PDT 24 Jul 01 04:28:06 PM PDT 24 1857843371 ps
T126 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3556394573 Jul 01 04:28:00 PM PDT 24 Jul 01 04:29:25 PM PDT 24 3252606007 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.819804365 Jul 01 04:27:45 PM PDT 24 Jul 01 04:28:09 PM PDT 24 7792773520 ps
T424 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4122461095 Jul 01 04:27:44 PM PDT 24 Jul 01 04:28:04 PM PDT 24 1152720716 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3751475612 Jul 01 04:27:42 PM PDT 24 Jul 01 04:27:56 PM PDT 24 88329328 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3840910145 Jul 01 04:27:38 PM PDT 24 Jul 01 04:28:07 PM PDT 24 1933729197 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3861146585 Jul 01 04:27:45 PM PDT 24 Jul 01 04:27:59 PM PDT 24 389097452 ps
T427 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3012651382 Jul 01 04:27:52 PM PDT 24 Jul 01 04:28:05 PM PDT 24 636605189 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1088270416 Jul 01 04:27:42 PM PDT 24 Jul 01 04:28:00 PM PDT 24 1609867414 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2394479501 Jul 01 04:27:40 PM PDT 24 Jul 01 04:28:01 PM PDT 24 4147473974 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3833788875 Jul 01 04:27:38 PM PDT 24 Jul 01 04:28:00 PM PDT 24 1148734760 ps
T122 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1167755175 Jul 01 04:27:49 PM PDT 24 Jul 01 04:29:10 PM PDT 24 1159725967 ps
T430 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3058549454 Jul 01 04:27:46 PM PDT 24 Jul 01 04:28:15 PM PDT 24 2092141431 ps
T431 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1011340302 Jul 01 04:27:52 PM PDT 24 Jul 01 04:28:03 PM PDT 24 188752691 ps
T127 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.463325489 Jul 01 04:27:57 PM PDT 24 Jul 01 04:29:22 PM PDT 24 11033998555 ps
T432 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1432306335 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:21 PM PDT 24 1429231428 ps
T433 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.401119723 Jul 01 04:27:55 PM PDT 24 Jul 01 04:28:13 PM PDT 24 5255022337 ps
T434 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3216657802 Jul 01 04:27:59 PM PDT 24 Jul 01 04:28:26 PM PDT 24 3487609043 ps
T435 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.735320085 Jul 01 04:27:47 PM PDT 24 Jul 01 04:28:52 PM PDT 24 63644054149 ps
T436 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1216914006 Jul 01 04:27:58 PM PDT 24 Jul 01 04:29:21 PM PDT 24 1802576680 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1255949127 Jul 01 04:27:46 PM PDT 24 Jul 01 04:28:05 PM PDT 24 6046549387 ps
T437 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1870131259 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:20 PM PDT 24 2157873582 ps
T438 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.385429836 Jul 01 04:27:45 PM PDT 24 Jul 01 04:27:58 PM PDT 24 88398894 ps
T439 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2624249210 Jul 01 04:27:58 PM PDT 24 Jul 01 04:28:12 PM PDT 24 89005487 ps
T440 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.891342999 Jul 01 04:28:01 PM PDT 24 Jul 01 04:29:13 PM PDT 24 6181398926 ps
T441 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1759249199 Jul 01 04:27:48 PM PDT 24 Jul 01 04:28:03 PM PDT 24 1079614754 ps
T442 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2428855671 Jul 01 04:27:59 PM PDT 24 Jul 01 04:28:20 PM PDT 24 1805313498 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4054179726 Jul 01 04:27:52 PM PDT 24 Jul 01 04:28:02 PM PDT 24 334160621 ps
T444 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2724175219 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:18 PM PDT 24 1525467544 ps
T445 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4181196239 Jul 01 04:27:50 PM PDT 24 Jul 01 04:28:13 PM PDT 24 1869678356 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1996685077 Jul 01 04:28:03 PM PDT 24 Jul 01 04:28:17 PM PDT 24 88828890 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3879683698 Jul 01 04:27:50 PM PDT 24 Jul 01 04:28:09 PM PDT 24 5078963983 ps
T448 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3194275727 Jul 01 04:27:45 PM PDT 24 Jul 01 04:28:11 PM PDT 24 2147602020 ps
T449 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.955991459 Jul 01 04:27:49 PM PDT 24 Jul 01 04:28:12 PM PDT 24 14065033956 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1905608865 Jul 01 04:27:47 PM PDT 24 Jul 01 04:28:07 PM PDT 24 1293142682 ps
T451 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2595073548 Jul 01 04:27:40 PM PDT 24 Jul 01 04:29:11 PM PDT 24 2466785014 ps
T452 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1686542524 Jul 01 04:28:02 PM PDT 24 Jul 01 04:28:25 PM PDT 24 6929652584 ps
T453 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1283743761 Jul 01 04:27:56 PM PDT 24 Jul 01 04:28:17 PM PDT 24 5282359013 ps
T454 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1877037968 Jul 01 04:27:50 PM PDT 24 Jul 01 04:28:15 PM PDT 24 1514827611 ps
T94 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2765537636 Jul 01 04:27:53 PM PDT 24 Jul 01 04:28:03 PM PDT 24 347485749 ps
T455 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.441967792 Jul 01 04:27:56 PM PDT 24 Jul 01 04:28:17 PM PDT 24 7785187682 ps
T128 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1232577672 Jul 01 04:27:51 PM PDT 24 Jul 01 04:28:36 PM PDT 24 609946445 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1445323772 Jul 01 04:27:34 PM PDT 24 Jul 01 04:27:55 PM PDT 24 19593892404 ps
T457 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.304583849 Jul 01 04:27:50 PM PDT 24 Jul 01 04:28:03 PM PDT 24 331153625 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3858183294 Jul 01 04:27:34 PM PDT 24 Jul 01 04:28:00 PM PDT 24 5591935398 ps
T459 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.115131993 Jul 01 04:27:42 PM PDT 24 Jul 01 04:27:56 PM PDT 24 89841479 ps
T460 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2424842406 Jul 01 04:27:43 PM PDT 24 Jul 01 04:28:00 PM PDT 24 583291539 ps
T95 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2592182941 Jul 01 04:27:35 PM PDT 24 Jul 01 04:28:51 PM PDT 24 50283541540 ps
T461 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2716746534 Jul 01 04:27:50 PM PDT 24 Jul 01 04:28:38 PM PDT 24 19966516362 ps
T462 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1569293072 Jul 01 04:27:45 PM PDT 24 Jul 01 04:27:58 PM PDT 24 518886105 ps
T463 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2369408597 Jul 01 04:27:46 PM PDT 24 Jul 01 04:28:02 PM PDT 24 499642912 ps
T464 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2581483732 Jul 01 04:27:57 PM PDT 24 Jul 01 04:28:08 PM PDT 24 346707850 ps
T465 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3984571669 Jul 01 04:27:48 PM PDT 24 Jul 01 04:28:03 PM PDT 24 2819953604 ps
T466 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3808946959 Jul 01 04:28:00 PM PDT 24 Jul 01 04:28:52 PM PDT 24 9252117967 ps
T467 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1294247994 Jul 01 04:28:01 PM PDT 24 Jul 01 04:28:25 PM PDT 24 1838393094 ps

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.514956940
Short name T7
Test name
Test status
Simulation time 9175190747 ps
CPU time 347.66 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:38:16 PM PDT 24
Peak memory 222992 kb
Host smart-0427077c-6c8c-4673-888f-82442bd87d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514956940 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.514956940
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3744677535
Short name T12
Test name
Test status
Simulation time 9059452002 ps
CPU time 119.5 seconds
Started Jul 01 04:32:02 PM PDT 24
Finished Jul 01 04:34:11 PM PDT 24
Peak memory 236816 kb
Host smart-e6cc61d4-09f0-4cf0-898a-71736fc565b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744677535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3744677535
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2161865051
Short name T46
Test name
Test status
Simulation time 14209124204 ps
CPU time 161.88 seconds
Started Jul 01 04:32:07 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 237760 kb
Host smart-b3a2a4de-05ca-4212-b6bf-3300ac21ec75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161865051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2161865051
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4237295325
Short name T117
Test name
Test status
Simulation time 451237749 ps
CPU time 72.35 seconds
Started Jul 01 04:27:40 PM PDT 24
Finished Jul 01 04:29:02 PM PDT 24
Peak memory 218988 kb
Host smart-07f8e169-e903-42b6-9377-557635902250
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237295325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4237295325
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1549200669
Short name T22
Test name
Test status
Simulation time 45645112740 ps
CPU time 97.87 seconds
Started Jul 01 04:32:21 PM PDT 24
Finished Jul 01 04:34:15 PM PDT 24
Peak memory 219400 kb
Host smart-47be68c0-bb44-4769-b7e4-e84b98ec5a1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549200669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1549200669
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3889258721
Short name T16
Test name
Test status
Simulation time 376882107 ps
CPU time 53.49 seconds
Started Jul 01 04:31:50 PM PDT 24
Finished Jul 01 04:32:54 PM PDT 24
Peak memory 236248 kb
Host smart-d83d4572-4a58-4106-9616-72ea5e35e0e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889258721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3889258721
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2206343016
Short name T78
Test name
Test status
Simulation time 13148239417 ps
CPU time 46.67 seconds
Started Jul 01 04:27:51 PM PDT 24
Finished Jul 01 04:28:44 PM PDT 24
Peak memory 210840 kb
Host smart-e9c68c3c-5094-4908-9fd1-6c458e123d66
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206343016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2206343016
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1167755175
Short name T122
Test name
Test status
Simulation time 1159725967 ps
CPU time 73.91 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:29:10 PM PDT 24
Peak memory 218760 kb
Host smart-cf625761-90ca-4d5a-9b32-0819341cd2ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167755175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1167755175
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2261331311
Short name T24
Test name
Test status
Simulation time 201643113841 ps
CPU time 3929.05 seconds
Started Jul 01 04:32:44 PM PDT 24
Finished Jul 01 05:38:26 PM PDT 24
Peak memory 243888 kb
Host smart-a52cac27-c527-469a-a5b3-af9d96a969ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261331311 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2261331311
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3135911532
Short name T19
Test name
Test status
Simulation time 1341705075 ps
CPU time 12.33 seconds
Started Jul 01 04:31:58 PM PDT 24
Finished Jul 01 04:32:20 PM PDT 24
Peak memory 211452 kb
Host smart-83e2fffc-eecf-4898-8269-0da86e951910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135911532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3135911532
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4005407267
Short name T42
Test name
Test status
Simulation time 264622685361 ps
CPU time 2397.97 seconds
Started Jul 01 04:32:20 PM PDT 24
Finished Jul 01 05:12:34 PM PDT 24
Peak memory 237424 kb
Host smart-f115fb86-4ba8-453f-b1cb-9c11ac69f6e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005407267 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.4005407267
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1015015532
Short name T45
Test name
Test status
Simulation time 175334666 ps
CPU time 9.69 seconds
Started Jul 01 04:32:18 PM PDT 24
Finished Jul 01 04:32:41 PM PDT 24
Peak memory 212456 kb
Host smart-cdfa22f4-73f5-4dcd-8839-e13222016439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015015532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1015015532
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1491405164
Short name T33
Test name
Test status
Simulation time 827320164 ps
CPU time 12.2 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:32:15 PM PDT 24
Peak memory 211960 kb
Host smart-ee840888-9a8f-4f60-b28f-38468bd139fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491405164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1491405164
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2310833941
Short name T106
Test name
Test status
Simulation time 4768374780 ps
CPU time 11.04 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:28:08 PM PDT 24
Peak memory 218856 kb
Host smart-299dff2f-15f6-4806-a7da-e10f63bfe813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310833941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2310833941
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2082665193
Short name T40
Test name
Test status
Simulation time 8994406025 ps
CPU time 49.09 seconds
Started Jul 01 04:32:03 PM PDT 24
Finished Jul 01 04:33:01 PM PDT 24
Peak memory 217420 kb
Host smart-5e1d9ee7-9487-43d7-a1c2-75d558b4f453
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082665193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2082665193
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2522336988
Short name T37
Test name
Test status
Simulation time 136856795409 ps
CPU time 348.01 seconds
Started Jul 01 04:31:51 PM PDT 24
Finished Jul 01 04:37:50 PM PDT 24
Peak memory 228716 kb
Host smart-f9ee4636-3a69-49fc-9ade-e627433dbeb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522336988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2522336988
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.463325489
Short name T127
Test name
Test status
Simulation time 11033998555 ps
CPU time 78.43 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:29:22 PM PDT 24
Peak memory 218972 kb
Host smart-33b904dc-4da1-4556-9093-0ff72d66e84c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463325489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.463325489
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1020469522
Short name T118
Test name
Test status
Simulation time 1038421450 ps
CPU time 69.59 seconds
Started Jul 01 04:27:59 PM PDT 24
Finished Jul 01 04:29:16 PM PDT 24
Peak memory 218968 kb
Host smart-68e74dd5-6b03-4f8c-9bc2-26d1ef4e28f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020469522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1020469522
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1232577672
Short name T128
Test name
Test status
Simulation time 609946445 ps
CPU time 38.8 seconds
Started Jul 01 04:27:51 PM PDT 24
Finished Jul 01 04:28:36 PM PDT 24
Peak memory 212120 kb
Host smart-f6644b7f-14bf-4553-a43f-f97bd4b17bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232577672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1232577672
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.683764562
Short name T96
Test name
Test status
Simulation time 799296195 ps
CPU time 9.81 seconds
Started Jul 01 04:32:19 PM PDT 24
Finished Jul 01 04:32:45 PM PDT 24
Peak memory 211356 kb
Host smart-eafea82f-b25c-4b60-b14b-248d82e57db9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683764562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.683764562
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2560057816
Short name T41
Test name
Test status
Simulation time 67176320231 ps
CPU time 2230.04 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 05:09:13 PM PDT 24
Peak memory 235820 kb
Host smart-a23d606f-7d52-4a26-b924-79b3b1e5dd0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560057816 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2560057816
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1308174177
Short name T402
Test name
Test status
Simulation time 5446343440 ps
CPU time 12.38 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 218632 kb
Host smart-fe4c248c-d08c-4695-8746-53402a79eda5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308174177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1308174177
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3254955864
Short name T383
Test name
Test status
Simulation time 970286652 ps
CPU time 10.08 seconds
Started Jul 01 04:27:39 PM PDT 24
Finished Jul 01 04:27:59 PM PDT 24
Peak memory 217544 kb
Host smart-a1c4e1ea-2048-4ebc-b2c6-f1008a8ab201
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254955864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3254955864
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.119596816
Short name T69
Test name
Test status
Simulation time 1350110107 ps
CPU time 13.55 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:28:07 PM PDT 24
Peak memory 218080 kb
Host smart-7d49c440-3412-4f6e-b824-83b7f96146fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119596816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.119596816
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3472614198
Short name T408
Test name
Test status
Simulation time 658481634 ps
CPU time 8.52 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:28:17 PM PDT 24
Peak memory 218880 kb
Host smart-d82d6e11-b028-4bfc-8829-4e52eb41abc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472614198 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3472614198
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.489033541
Short name T84
Test name
Test status
Simulation time 2431882049 ps
CPU time 14.78 seconds
Started Jul 01 04:27:42 PM PDT 24
Finished Jul 01 04:28:06 PM PDT 24
Peak memory 210568 kb
Host smart-550d0eaa-574e-4193-949d-efdd181ecebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489033541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.489033541
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1276463023
Short name T374
Test name
Test status
Simulation time 2062658503 ps
CPU time 15.25 seconds
Started Jul 01 04:27:41 PM PDT 24
Finished Jul 01 04:28:06 PM PDT 24
Peak memory 210468 kb
Host smart-ebf56784-a5e7-4cfd-960d-568f003cac81
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276463023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1276463023
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2727889909
Short name T378
Test name
Test status
Simulation time 1369816021 ps
CPU time 12.22 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:27:55 PM PDT 24
Peak memory 210460 kb
Host smart-bc065b19-6a6b-4235-b940-715587cf8303
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727889909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2727889909
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2463498462
Short name T89
Test name
Test status
Simulation time 3643362600 ps
CPU time 38.69 seconds
Started Jul 01 04:27:48 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 210836 kb
Host smart-41c22bb3-9a94-4605-96a4-047387d279f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463498462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2463498462
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1785110065
Short name T109
Test name
Test status
Simulation time 882896122 ps
CPU time 6.17 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:28:02 PM PDT 24
Peak memory 217924 kb
Host smart-bcb6cc00-bf81-4928-bae3-2f41b411c71c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785110065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1785110065
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3858183294
Short name T458
Test name
Test status
Simulation time 5591935398 ps
CPU time 15.37 seconds
Started Jul 01 04:27:34 PM PDT 24
Finished Jul 01 04:28:00 PM PDT 24
Peak memory 218900 kb
Host smart-0c43b4f3-5476-4990-bcc2-e7533f13cb69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858183294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3858183294
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1088270416
Short name T91
Test name
Test status
Simulation time 1609867414 ps
CPU time 9 seconds
Started Jul 01 04:27:42 PM PDT 24
Finished Jul 01 04:28:00 PM PDT 24
Peak memory 210596 kb
Host smart-0b5858e6-8846-4cd2-b534-31d406c0290d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088270416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1088270416
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4054179726
Short name T443
Test name
Test status
Simulation time 334160621 ps
CPU time 4.34 seconds
Started Jul 01 04:27:52 PM PDT 24
Finished Jul 01 04:28:02 PM PDT 24
Peak memory 210524 kb
Host smart-37d2dc3b-8c2b-4531-ad50-557057a5eaec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054179726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4054179726
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1861372312
Short name T381
Test name
Test status
Simulation time 8375628590 ps
CPU time 16.92 seconds
Started Jul 01 04:27:37 PM PDT 24
Finished Jul 01 04:28:05 PM PDT 24
Peak memory 218712 kb
Host smart-9bcaf795-c956-41f8-893a-3b4abe0de4de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861372312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1861372312
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2394479501
Short name T428
Test name
Test status
Simulation time 4147473974 ps
CPU time 10.86 seconds
Started Jul 01 04:27:40 PM PDT 24
Finished Jul 01 04:28:01 PM PDT 24
Peak memory 218864 kb
Host smart-c6dd5cd7-ac0c-47f3-b4c5-f0fa7514d3f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394479501 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2394479501
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.30080068
Short name T419
Test name
Test status
Simulation time 1719632773 ps
CPU time 5.67 seconds
Started Jul 01 04:27:37 PM PDT 24
Finished Jul 01 04:27:53 PM PDT 24
Peak memory 217416 kb
Host smart-7256ada9-5dc4-4573-90ce-22d06a474ad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30080068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.30080068
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4091388983
Short name T372
Test name
Test status
Simulation time 520944477 ps
CPU time 5.26 seconds
Started Jul 01 04:27:34 PM PDT 24
Finished Jul 01 04:27:50 PM PDT 24
Peak memory 210772 kb
Host smart-393ed7ce-98b1-48af-ba77-aaae2135ce38
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091388983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4091388983
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3751475612
Short name T425
Test name
Test status
Simulation time 88329328 ps
CPU time 4.28 seconds
Started Jul 01 04:27:42 PM PDT 24
Finished Jul 01 04:27:56 PM PDT 24
Peak memory 210460 kb
Host smart-082e290a-1faa-4280-b209-3d2f762a2d28
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751475612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3751475612
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3400781406
Short name T73
Test name
Test status
Simulation time 12131139039 ps
CPU time 63.86 seconds
Started Jul 01 04:27:42 PM PDT 24
Finished Jul 01 04:28:56 PM PDT 24
Peak memory 210656 kb
Host smart-3b67bfc9-763b-47ae-b853-d4a789ea1bf4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400781406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3400781406
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4122461095
Short name T424
Test name
Test status
Simulation time 1152720716 ps
CPU time 10.92 seconds
Started Jul 01 04:27:44 PM PDT 24
Finished Jul 01 04:28:04 PM PDT 24
Peak memory 210660 kb
Host smart-b7033acb-1c5e-4572-97a4-e05cccc1e3be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122461095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4122461095
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3833788875
Short name T429
Test name
Test status
Simulation time 1148734760 ps
CPU time 12.35 seconds
Started Jul 01 04:27:38 PM PDT 24
Finished Jul 01 04:28:00 PM PDT 24
Peak memory 218832 kb
Host smart-bab00fed-5584-4d9a-a822-7be31ecfed73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833788875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3833788875
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4290665597
Short name T125
Test name
Test status
Simulation time 155835168 ps
CPU time 38.55 seconds
Started Jul 01 04:27:38 PM PDT 24
Finished Jul 01 04:28:27 PM PDT 24
Peak memory 211928 kb
Host smart-d77bf574-990d-469c-87ce-f96194fa6086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290665597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4290665597
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2861720086
Short name T398
Test name
Test status
Simulation time 16411595429 ps
CPU time 17.15 seconds
Started Jul 01 04:27:59 PM PDT 24
Finished Jul 01 04:28:25 PM PDT 24
Peak memory 218952 kb
Host smart-0eefb63d-820b-46a6-93c6-f7e59f263d18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861720086 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2861720086
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1569293072
Short name T462
Test name
Test status
Simulation time 518886105 ps
CPU time 4.13 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:27:58 PM PDT 24
Peak memory 217712 kb
Host smart-ebd0d591-a125-4392-99d9-e1e62614200a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569293072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1569293072
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.645982518
Short name T87
Test name
Test status
Simulation time 1512970137 ps
CPU time 28.75 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 210592 kb
Host smart-3cc84f55-4ab3-4658-a6fd-9c9664c8abe7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645982518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.645982518
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3512938247
Short name T76
Test name
Test status
Simulation time 347331447 ps
CPU time 4.37 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 217960 kb
Host smart-66754a40-7aaf-45d1-86ae-98c681f91c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512938247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3512938247
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1283743761
Short name T453
Test name
Test status
Simulation time 5282359013 ps
CPU time 14.74 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:28:17 PM PDT 24
Peak memory 218840 kb
Host smart-d492101c-61e7-44bd-bdaf-73779c52eca4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283743761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1283743761
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2330197303
Short name T418
Test name
Test status
Simulation time 911646942 ps
CPU time 40.39 seconds
Started Jul 01 04:27:46 PM PDT 24
Finished Jul 01 04:28:34 PM PDT 24
Peak memory 212276 kb
Host smart-d469c788-d5b2-438f-a27c-b6b424e3b50a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330197303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2330197303
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2372438428
Short name T394
Test name
Test status
Simulation time 1661030670 ps
CPU time 13.31 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 218796 kb
Host smart-b211a3dd-ea16-41b5-a5db-bb58a1a9b7c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372438428 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2372438428
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3984571669
Short name T465
Test name
Test status
Simulation time 2819953604 ps
CPU time 7.64 seconds
Started Jul 01 04:27:48 PM PDT 24
Finished Jul 01 04:28:03 PM PDT 24
Peak memory 217736 kb
Host smart-25758f9b-7dd1-46c1-8bf5-9582cacb6263
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984571669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3984571669
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2716746534
Short name T461
Test name
Test status
Simulation time 19966516362 ps
CPU time 41.84 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:28:38 PM PDT 24
Peak memory 210888 kb
Host smart-ff002d2c-da02-4ea0-97cd-3cd7437a25d0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716746534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2716746534
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2918797994
Short name T393
Test name
Test status
Simulation time 596924319 ps
CPU time 7.78 seconds
Started Jul 01 04:27:59 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 217628 kb
Host smart-a307f071-6a4f-4520-8a5a-ed7932e79277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918797994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2918797994
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2428855671
Short name T442
Test name
Test status
Simulation time 1805313498 ps
CPU time 13.27 seconds
Started Jul 01 04:27:59 PM PDT 24
Finished Jul 01 04:28:20 PM PDT 24
Peak memory 218840 kb
Host smart-a9cac8f2-3eb6-40d4-9de2-1765a4302ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428855671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2428855671
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1193065931
Short name T119
Test name
Test status
Simulation time 1173425044 ps
CPU time 70.77 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:29:08 PM PDT 24
Peak memory 211812 kb
Host smart-92ab1988-b385-4cdb-85c6-93132d39a077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193065931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1193065931
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1393887275
Short name T390
Test name
Test status
Simulation time 1709029743 ps
CPU time 7.53 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:28:03 PM PDT 24
Peak memory 218888 kb
Host smart-32af8d03-b31d-4f0a-beef-9c253770c6fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393887275 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1393887275
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1255949127
Short name T93
Test name
Test status
Simulation time 6046549387 ps
CPU time 11.17 seconds
Started Jul 01 04:27:46 PM PDT 24
Finished Jul 01 04:28:05 PM PDT 24
Peak memory 210844 kb
Host smart-22c05c59-0aea-46c7-b22e-0c10c30707ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255949127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1255949127
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3012651382
Short name T427
Test name
Test status
Simulation time 636605189 ps
CPU time 6.6 seconds
Started Jul 01 04:27:52 PM PDT 24
Finished Jul 01 04:28:05 PM PDT 24
Peak memory 218708 kb
Host smart-d0ae72d7-7c93-4f36-ba43-9c97f10a8c11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012651382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3012651382
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1216914006
Short name T436
Test name
Test status
Simulation time 1802576680 ps
CPU time 76.17 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:29:21 PM PDT 24
Peak memory 218800 kb
Host smart-4ecc8ed3-57a9-4ca6-b5f8-326e4dcd6e67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216914006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1216914006
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.401119723
Short name T433
Test name
Test status
Simulation time 5255022337 ps
CPU time 11.8 seconds
Started Jul 01 04:27:55 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 218876 kb
Host smart-d319fe4a-b67a-49d7-baf3-541a44f7b181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401119723 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.401119723
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.861430954
Short name T387
Test name
Test status
Simulation time 86563493 ps
CPU time 4.24 seconds
Started Jul 01 04:28:06 PM PDT 24
Finished Jul 01 04:28:19 PM PDT 24
Peak memory 210592 kb
Host smart-1777333e-735a-4c2d-a43d-9bb4fa96d828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861430954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.861430954
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1234499815
Short name T74
Test name
Test status
Simulation time 8322058313 ps
CPU time 31.38 seconds
Started Jul 01 04:27:48 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 210664 kb
Host smart-c7831a26-4f14-44d6-a41f-33a7bb0648b5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234499815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1234499815
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1759249199
Short name T441
Test name
Test status
Simulation time 1079614754 ps
CPU time 7.85 seconds
Started Jul 01 04:27:48 PM PDT 24
Finished Jul 01 04:28:03 PM PDT 24
Peak memory 217984 kb
Host smart-f89bd1b0-600c-426a-b7cc-69705c8cee29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759249199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1759249199
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1591088175
Short name T406
Test name
Test status
Simulation time 85617873 ps
CPU time 6.21 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:28:09 PM PDT 24
Peak memory 218908 kb
Host smart-84afe376-086a-4b2a-aa6c-d4e17067840d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591088175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1591088175
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3121188861
Short name T375
Test name
Test status
Simulation time 6582042114 ps
CPU time 13.54 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:17 PM PDT 24
Peak memory 218936 kb
Host smart-56faf525-b979-4319-b459-7b2caeaba2ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121188861 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3121188861
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1870131259
Short name T437
Test name
Test status
Simulation time 2157873582 ps
CPU time 15.92 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:20 PM PDT 24
Peak memory 210580 kb
Host smart-cec6ae9e-774f-465d-92ca-d993e10b9df5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870131259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1870131259
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2335639223
Short name T114
Test name
Test status
Simulation time 7466758526 ps
CPU time 59.13 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:29:02 PM PDT 24
Peak memory 217692 kb
Host smart-938544e4-dde3-4086-a721-95c73b08b81b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335639223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2335639223
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1432306335
Short name T432
Test name
Test status
Simulation time 1429231428 ps
CPU time 11.95 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:21 PM PDT 24
Peak memory 218932 kb
Host smart-eb4f79ab-cb3e-4abd-aa61-f4dbd9833f86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432306335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1432306335
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3648292459
Short name T384
Test name
Test status
Simulation time 4917112146 ps
CPU time 15.58 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:28:09 PM PDT 24
Peak memory 219136 kb
Host smart-738c66ea-2a77-4273-a0a1-befea62eeced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648292459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3648292459
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.976556159
Short name T120
Test name
Test status
Simulation time 8157477511 ps
CPU time 76.45 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:29:22 PM PDT 24
Peak memory 218864 kb
Host smart-deb89709-fbc1-47f7-a731-653da48e23b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976556159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.976556159
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3653059451
Short name T421
Test name
Test status
Simulation time 318267327 ps
CPU time 4.95 seconds
Started Jul 01 04:28:09 PM PDT 24
Finished Jul 01 04:28:23 PM PDT 24
Peak memory 218996 kb
Host smart-a0e65814-750a-4e50-87e1-cc35c43bd549
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653059451 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3653059451
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1745990249
Short name T410
Test name
Test status
Simulation time 1009933454 ps
CPU time 10.55 seconds
Started Jul 01 04:27:48 PM PDT 24
Finished Jul 01 04:28:06 PM PDT 24
Peak memory 210592 kb
Host smart-bdca9b4a-fde5-4925-be71-2bb9789732d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745990249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1745990249
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4061378150
Short name T85
Test name
Test status
Simulation time 12660632755 ps
CPU time 53.76 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 210600 kb
Host smart-43e7c3a6-3a65-4a13-80c6-566affe38505
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061378150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4061378150
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2734964578
Short name T412
Test name
Test status
Simulation time 334374690 ps
CPU time 4.25 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:28:01 PM PDT 24
Peak memory 210340 kb
Host smart-1995d338-95fb-4128-a71c-efe1a10f7ebe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734964578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2734964578
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4000654219
Short name T379
Test name
Test status
Simulation time 4599033750 ps
CPU time 10.78 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 218908 kb
Host smart-7d7a8309-ef06-42af-ac49-128b86bb4ae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000654219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4000654219
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2162015261
Short name T123
Test name
Test status
Simulation time 3651388098 ps
CPU time 74.1 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:29:11 PM PDT 24
Peak memory 211416 kb
Host smart-2d655cc5-d0a9-44c4-91d1-7df6c3f135f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162015261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2162015261
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1038620977
Short name T404
Test name
Test status
Simulation time 1126420395 ps
CPU time 11 seconds
Started Jul 01 04:28:07 PM PDT 24
Finished Jul 01 04:28:28 PM PDT 24
Peak memory 218776 kb
Host smart-f9d95bd2-78e1-4193-8416-53bdd37de04d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038620977 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1038620977
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2724175219
Short name T444
Test name
Test status
Simulation time 1525467544 ps
CPU time 12.4 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:18 PM PDT 24
Peak memory 218632 kb
Host smart-bdcb5965-18bf-47a7-bb9f-5ccbb28aa477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724175219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2724175219
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3998378385
Short name T111
Test name
Test status
Simulation time 34853375001 ps
CPU time 55.52 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:28:52 PM PDT 24
Peak memory 210664 kb
Host smart-14f68d79-de7e-4643-9ee5-72817fec92be
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998378385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3998378385
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1966526665
Short name T401
Test name
Test status
Simulation time 8149775145 ps
CPU time 15.55 seconds
Started Jul 01 04:27:54 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 218844 kb
Host smart-616ea9bc-5652-4f1a-8bac-02958e2d89bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966526665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1966526665
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3023184286
Short name T400
Test name
Test status
Simulation time 12303780719 ps
CPU time 17.58 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:28:24 PM PDT 24
Peak memory 218884 kb
Host smart-7fb91924-e1d2-4352-85cf-10217942e336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023184286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3023184286
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1659504590
Short name T420
Test name
Test status
Simulation time 7345272578 ps
CPU time 76.87 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:29:21 PM PDT 24
Peak memory 212336 kb
Host smart-01caf6e0-642b-4fef-8bf9-5f5178769955
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659504590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1659504590
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1011340302
Short name T431
Test name
Test status
Simulation time 188752691 ps
CPU time 4.8 seconds
Started Jul 01 04:27:52 PM PDT 24
Finished Jul 01 04:28:03 PM PDT 24
Peak memory 218884 kb
Host smart-5f776eeb-5656-4df4-8606-7369adbbce1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011340302 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1011340302
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3178613895
Short name T60
Test name
Test status
Simulation time 975727018 ps
CPU time 10.06 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:19 PM PDT 24
Peak memory 218728 kb
Host smart-383f02a2-1eb2-411c-b7a5-e189e70bc5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178613895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3178613895
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2868989998
Short name T92
Test name
Test status
Simulation time 3519585987 ps
CPU time 47.8 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:28:44 PM PDT 24
Peak memory 210660 kb
Host smart-32c7271c-a75c-4592-af3c-755f59fe5a2c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868989998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2868989998
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1139105696
Short name T417
Test name
Test status
Simulation time 1909058926 ps
CPU time 9.41 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 218984 kb
Host smart-360dae6f-e52f-4b0d-a5c7-d982c7d3736f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139105696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1139105696
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.601941208
Short name T371
Test name
Test status
Simulation time 1279353102 ps
CPU time 13.8 seconds
Started Jul 01 04:27:53 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 218828 kb
Host smart-6aa1c34c-7892-4464-a859-2cbbc75e0921
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601941208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.601941208
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2167650724
Short name T58
Test name
Test status
Simulation time 3626017244 ps
CPU time 44.37 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:53 PM PDT 24
Peak memory 218824 kb
Host smart-78caf967-d74e-4f2b-a000-4831354fcb13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167650724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2167650724
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.441967792
Short name T455
Test name
Test status
Simulation time 7785187682 ps
CPU time 15.15 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:28:17 PM PDT 24
Peak memory 218868 kb
Host smart-d123d3a5-47f8-4f2a-90aa-c630d6b9bb12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441967792 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.441967792
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.955991459
Short name T449
Test name
Test status
Simulation time 14065033956 ps
CPU time 15.82 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 218948 kb
Host smart-2b01d4bb-9d9a-4eee-9cb7-8394c0f75215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955991459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.955991459
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3808946959
Short name T466
Test name
Test status
Simulation time 9252117967 ps
CPU time 43.67 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:52 PM PDT 24
Peak memory 210660 kb
Host smart-4009e08a-fd26-41ce-8bb9-15cca52fa09b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808946959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3808946959
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3596189555
Short name T397
Test name
Test status
Simulation time 1835612895 ps
CPU time 14.06 seconds
Started Jul 01 04:27:54 PM PDT 24
Finished Jul 01 04:28:14 PM PDT 24
Peak memory 218784 kb
Host smart-07b135a1-f64c-4e79-8408-142768cb3553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596189555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3596189555
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2624249210
Short name T439
Test name
Test status
Simulation time 89005487 ps
CPU time 6.31 seconds
Started Jul 01 04:27:58 PM PDT 24
Finished Jul 01 04:28:12 PM PDT 24
Peak memory 218848 kb
Host smart-0151f502-fbec-44ad-bd1d-9575389604fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624249210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2624249210
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3556394573
Short name T126
Test name
Test status
Simulation time 3252606007 ps
CPU time 76.41 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:29:25 PM PDT 24
Peak memory 211244 kb
Host smart-0b875e45-bc3b-45dd-a690-640cc9963ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556394573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3556394573
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3895781072
Short name T395
Test name
Test status
Simulation time 5624479386 ps
CPU time 13.12 seconds
Started Jul 01 04:27:59 PM PDT 24
Finished Jul 01 04:28:20 PM PDT 24
Peak memory 219192 kb
Host smart-b3f7604a-d51a-489a-9b93-097e8f767907
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895781072 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3895781072
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2765537636
Short name T94
Test name
Test status
Simulation time 347485749 ps
CPU time 4.2 seconds
Started Jul 01 04:27:53 PM PDT 24
Finished Jul 01 04:28:03 PM PDT 24
Peak memory 210536 kb
Host smart-1fe2e452-269f-441a-91ae-a1bfd0c1dfe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765537636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2765537636
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3804450852
Short name T88
Test name
Test status
Simulation time 1182098831 ps
CPU time 25.54 seconds
Started Jul 01 04:27:59 PM PDT 24
Finished Jul 01 04:28:33 PM PDT 24
Peak memory 210560 kb
Host smart-0a3ee9fb-4a04-43a4-8569-ee553dc81a1e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804450852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3804450852
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2733996462
Short name T107
Test name
Test status
Simulation time 2417461415 ps
CPU time 11.26 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:16 PM PDT 24
Peak memory 210716 kb
Host smart-122ac2d9-ce31-46c3-8718-fb4a5c0c8dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733996462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2733996462
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.434207255
Short name T392
Test name
Test status
Simulation time 389815685 ps
CPU time 8.85 seconds
Started Jul 01 04:28:00 PM PDT 24
Finished Jul 01 04:28:18 PM PDT 24
Peak memory 218816 kb
Host smart-ba6546c8-0ff3-4720-887d-b205f32afe2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434207255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.434207255
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1263117504
Short name T77
Test name
Test status
Simulation time 2076246405 ps
CPU time 15.29 seconds
Started Jul 01 04:27:41 PM PDT 24
Finished Jul 01 04:28:06 PM PDT 24
Peak memory 210528 kb
Host smart-6d0cca97-2c67-4935-b0ac-46aef1d831f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263117504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1263117504
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1905608865
Short name T450
Test name
Test status
Simulation time 1293142682 ps
CPU time 12.44 seconds
Started Jul 01 04:27:47 PM PDT 24
Finished Jul 01 04:28:07 PM PDT 24
Peak memory 218636 kb
Host smart-6e58df7e-7d54-4d06-aceb-1f8a70e263a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905608865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1905608865
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3840910145
Short name T90
Test name
Test status
Simulation time 1933729197 ps
CPU time 18.99 seconds
Started Jul 01 04:27:38 PM PDT 24
Finished Jul 01 04:28:07 PM PDT 24
Peak memory 210892 kb
Host smart-ebce00dd-8516-4f62-a411-16466cc15ad3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840910145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3840910145
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3614831912
Short name T405
Test name
Test status
Simulation time 1307102211 ps
CPU time 9.08 seconds
Started Jul 01 04:27:40 PM PDT 24
Finished Jul 01 04:27:59 PM PDT 24
Peak memory 214200 kb
Host smart-ebb02419-8219-4196-ae35-de13bf112598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614831912 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3614831912
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2374684915
Short name T411
Test name
Test status
Simulation time 89187543 ps
CPU time 4.18 seconds
Started Jul 01 04:27:34 PM PDT 24
Finished Jul 01 04:27:49 PM PDT 24
Peak memory 217664 kb
Host smart-29923869-b4e7-4994-8587-69271d3d8e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374684915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2374684915
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4113982717
Short name T422
Test name
Test status
Simulation time 1857843371 ps
CPU time 14.36 seconds
Started Jul 01 04:27:43 PM PDT 24
Finished Jul 01 04:28:06 PM PDT 24
Peak memory 210728 kb
Host smart-202535ba-233d-40bf-bd10-f28c226ee2f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113982717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4113982717
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4231929193
Short name T396
Test name
Test status
Simulation time 5249663496 ps
CPU time 12.39 seconds
Started Jul 01 04:27:40 PM PDT 24
Finished Jul 01 04:28:02 PM PDT 24
Peak memory 210376 kb
Host smart-f41cd49d-c088-4988-b8c0-f7d7460ee7c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231929193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4231929193
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.64945073
Short name T108
Test name
Test status
Simulation time 4171397996 ps
CPU time 31.48 seconds
Started Jul 01 04:27:51 PM PDT 24
Finished Jul 01 04:28:29 PM PDT 24
Peak memory 210676 kb
Host smart-b160d85e-0bf7-43a0-8cab-bfb8ca15b202
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64945073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.64945073
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2602542830
Short name T413
Test name
Test status
Simulation time 2168787821 ps
CPU time 14.94 seconds
Started Jul 01 04:27:46 PM PDT 24
Finished Jul 01 04:28:09 PM PDT 24
Peak memory 210716 kb
Host smart-f4a1b7ed-d6ee-4bcb-ab20-198576c94328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602542830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2602542830
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.111712639
Short name T373
Test name
Test status
Simulation time 3296045757 ps
CPU time 16.82 seconds
Started Jul 01 04:27:32 PM PDT 24
Finished Jul 01 04:27:59 PM PDT 24
Peak memory 218896 kb
Host smart-f64c7b5a-2b20-4f05-9496-108ad4f3ce76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111712639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.111712639
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.236966948
Short name T57
Test name
Test status
Simulation time 7128535831 ps
CPU time 48.8 seconds
Started Jul 01 04:27:37 PM PDT 24
Finished Jul 01 04:28:37 PM PDT 24
Peak memory 212348 kb
Host smart-e3f446f5-e4a5-4aab-b420-94e7018daff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236966948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.236966948
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.819804365
Short name T423
Test name
Test status
Simulation time 7792773520 ps
CPU time 15.33 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:28:09 PM PDT 24
Peak memory 210616 kb
Host smart-55881396-535e-43bb-868a-6ea3ec9e62b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819804365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.819804365
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1661912226
Short name T389
Test name
Test status
Simulation time 8555909779 ps
CPU time 17 seconds
Started Jul 01 04:27:44 PM PDT 24
Finished Jul 01 04:28:10 PM PDT 24
Peak memory 218760 kb
Host smart-6aae2399-50e1-4ddb-bed0-13aa915bdc34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661912226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1661912226
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3045812433
Short name T407
Test name
Test status
Simulation time 3643333366 ps
CPU time 17.87 seconds
Started Jul 01 04:27:43 PM PDT 24
Finished Jul 01 04:28:10 PM PDT 24
Peak memory 210608 kb
Host smart-c7767e80-7972-4606-8a93-0b94478b33df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045812433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3045812433
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3879683698
Short name T447
Test name
Test status
Simulation time 5078963983 ps
CPU time 12.24 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:28:09 PM PDT 24
Peak memory 219016 kb
Host smart-71205e1a-ee7f-4f06-ab59-bc931ef08fda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879683698 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3879683698
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1445323772
Short name T456
Test name
Test status
Simulation time 19593892404 ps
CPU time 10.94 seconds
Started Jul 01 04:27:34 PM PDT 24
Finished Jul 01 04:27:55 PM PDT 24
Peak memory 218836 kb
Host smart-67c401b9-97b1-44b2-95e9-8e408ce2bd2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445323772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1445323772
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3907805104
Short name T385
Test name
Test status
Simulation time 1955698768 ps
CPU time 9.64 seconds
Started Jul 01 04:27:51 PM PDT 24
Finished Jul 01 04:28:07 PM PDT 24
Peak memory 210500 kb
Host smart-3c7a6d77-fc60-4309-b5e8-6fede2672997
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907805104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3907805104
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1294247994
Short name T467
Test name
Test status
Simulation time 1838393094 ps
CPU time 14.33 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:28:25 PM PDT 24
Peak memory 210464 kb
Host smart-566dde6f-0e8a-484a-8e26-e949f271a570
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294247994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1294247994
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1370984916
Short name T113
Test name
Test status
Simulation time 2255314771 ps
CPU time 27.31 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:32 PM PDT 24
Peak memory 210744 kb
Host smart-c322f8b4-4d3e-42d2-8de0-baf022b4c0e3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370984916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1370984916
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3652236502
Short name T110
Test name
Test status
Simulation time 85730270 ps
CPU time 4.34 seconds
Started Jul 01 04:27:46 PM PDT 24
Finished Jul 01 04:27:59 PM PDT 24
Peak memory 218096 kb
Host smart-921aeb0f-b344-43ac-8d23-2b67a301ae85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652236502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3652236502
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2293437326
Short name T409
Test name
Test status
Simulation time 4092917830 ps
CPU time 13.76 seconds
Started Jul 01 04:27:37 PM PDT 24
Finished Jul 01 04:28:01 PM PDT 24
Peak memory 218892 kb
Host smart-1382d0a4-4258-435b-ab36-17bdf57e89b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293437326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2293437326
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.706015512
Short name T121
Test name
Test status
Simulation time 1144137425 ps
CPU time 41.14 seconds
Started Jul 01 04:27:55 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 218796 kb
Host smart-bf177fa1-8294-4aab-982a-48f6ece71656
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706015512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.706015512
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2798460833
Short name T72
Test name
Test status
Simulation time 1426388702 ps
CPU time 6.93 seconds
Started Jul 01 04:27:53 PM PDT 24
Finished Jul 01 04:28:06 PM PDT 24
Peak memory 210732 kb
Host smart-b0751035-9016-4378-9ec2-f5c52766d9ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798460833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2798460833
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1996685077
Short name T446
Test name
Test status
Simulation time 88828890 ps
CPU time 4.8 seconds
Started Jul 01 04:28:03 PM PDT 24
Finished Jul 01 04:28:17 PM PDT 24
Peak memory 210956 kb
Host smart-d4484342-1a00-48e9-8322-22d88a77a931
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996685077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1996685077
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.304583849
Short name T457
Test name
Test status
Simulation time 331153625 ps
CPU time 5.73 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:28:03 PM PDT 24
Peak memory 210524 kb
Host smart-0d861620-086d-43cf-ba88-1b9fa03635a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304583849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.304583849
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3861146585
Short name T426
Test name
Test status
Simulation time 389097452 ps
CPU time 4.96 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:27:59 PM PDT 24
Peak memory 218788 kb
Host smart-9dcdddfa-1aa6-46fc-917d-ba0ee7e53f1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861146585 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3861146585
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.616140267
Short name T399
Test name
Test status
Simulation time 1737793698 ps
CPU time 9.3 seconds
Started Jul 01 04:27:54 PM PDT 24
Finished Jul 01 04:28:09 PM PDT 24
Peak memory 218312 kb
Host smart-ee43ee91-1b7c-4b91-a408-321e4a5a36fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616140267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.616140267
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2590584882
Short name T415
Test name
Test status
Simulation time 638811012 ps
CPU time 4.41 seconds
Started Jul 01 04:27:51 PM PDT 24
Finished Jul 01 04:28:02 PM PDT 24
Peak memory 210528 kb
Host smart-15eb48b9-b9d4-4487-9384-60781b485dfd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590584882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2590584882
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2002772610
Short name T377
Test name
Test status
Simulation time 7929040744 ps
CPU time 11.16 seconds
Started Jul 01 04:27:33 PM PDT 24
Finished Jul 01 04:27:55 PM PDT 24
Peak memory 210448 kb
Host smart-36f113e5-986b-4383-9276-520a3da25ead
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002772610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2002772610
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2592182941
Short name T95
Test name
Test status
Simulation time 50283541540 ps
CPU time 64.56 seconds
Started Jul 01 04:27:35 PM PDT 24
Finished Jul 01 04:28:51 PM PDT 24
Peak memory 210900 kb
Host smart-cf576a68-0074-4e5f-9283-bab7fcb91c8e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592182941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2592182941
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2424842406
Short name T460
Test name
Test status
Simulation time 583291539 ps
CPU time 7.9 seconds
Started Jul 01 04:27:43 PM PDT 24
Finished Jul 01 04:28:00 PM PDT 24
Peak memory 218108 kb
Host smart-1d338c55-ba62-4595-936c-cf87eeb30f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424842406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2424842406
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4222042428
Short name T403
Test name
Test status
Simulation time 2160423566 ps
CPU time 9.94 seconds
Started Jul 01 04:27:37 PM PDT 24
Finished Jul 01 04:27:58 PM PDT 24
Peak memory 218876 kb
Host smart-fc250079-84e3-4c5f-9b44-11dbec4f88eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222042428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4222042428
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3362449717
Short name T388
Test name
Test status
Simulation time 19234131812 ps
CPU time 12.45 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:28:09 PM PDT 24
Peak memory 219100 kb
Host smart-aa4cb863-fc99-41b6-89e5-5cdf75155d17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362449717 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3362449717
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.115131993
Short name T459
Test name
Test status
Simulation time 89841479 ps
CPU time 4.2 seconds
Started Jul 01 04:27:42 PM PDT 24
Finished Jul 01 04:27:56 PM PDT 24
Peak memory 210596 kb
Host smart-8d88dbe6-3ba3-4666-b969-e7ac748552b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115131993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.115131993
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3568395052
Short name T70
Test name
Test status
Simulation time 23341926437 ps
CPU time 49.82 seconds
Started Jul 01 04:27:49 PM PDT 24
Finished Jul 01 04:28:46 PM PDT 24
Peak memory 210912 kb
Host smart-44e0788f-2842-40e1-88f7-0a0f34f08a41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568395052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3568395052
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2810338685
Short name T59
Test name
Test status
Simulation time 5604834677 ps
CPU time 14.82 seconds
Started Jul 01 04:27:54 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 210836 kb
Host smart-aea0d69d-bb18-4d96-9b40-994e4569382c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810338685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2810338685
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3058549454
Short name T430
Test name
Test status
Simulation time 2092141431 ps
CPU time 20.74 seconds
Started Jul 01 04:27:46 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 219020 kb
Host smart-3f88908a-e99b-431b-9a82-19ef49713637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058549454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3058549454
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1756145092
Short name T56
Test name
Test status
Simulation time 1948541763 ps
CPU time 46.52 seconds
Started Jul 01 04:27:43 PM PDT 24
Finished Jul 01 04:28:39 PM PDT 24
Peak memory 212192 kb
Host smart-27bd8db3-9dbf-44de-97af-e0e3275a2668
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756145092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1756145092
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1907909319
Short name T382
Test name
Test status
Simulation time 2345951965 ps
CPU time 7.84 seconds
Started Jul 01 04:27:43 PM PDT 24
Finished Jul 01 04:28:00 PM PDT 24
Peak memory 218916 kb
Host smart-f803e23f-dacd-46ea-9494-8e8549110209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907909319 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1907909319
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4181196239
Short name T445
Test name
Test status
Simulation time 1869678356 ps
CPU time 15.58 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:28:13 PM PDT 24
Peak memory 210588 kb
Host smart-06fd0ff5-4ee4-4321-ab66-e2c59d66734f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181196239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4181196239
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.735320085
Short name T435
Test name
Test status
Simulation time 63644054149 ps
CPU time 56.83 seconds
Started Jul 01 04:27:47 PM PDT 24
Finished Jul 01 04:28:52 PM PDT 24
Peak memory 210856 kb
Host smart-b3e23a5b-902a-4b0f-b75b-bf5f129a9aa2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735320085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.735320085
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1929958437
Short name T414
Test name
Test status
Simulation time 6163548514 ps
CPU time 12.27 seconds
Started Jul 01 04:27:53 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 210824 kb
Host smart-14e85617-9ad7-4f5d-81a4-f672d2af7777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929958437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1929958437
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2621955703
Short name T380
Test name
Test status
Simulation time 846514190 ps
CPU time 7.27 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:28:10 PM PDT 24
Peak memory 219080 kb
Host smart-c0efbf71-9221-42ce-9635-f50e51109178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621955703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2621955703
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2176807744
Short name T124
Test name
Test status
Simulation time 1418539306 ps
CPU time 40.25 seconds
Started Jul 01 04:27:35 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 212056 kb
Host smart-2f7a0b93-cf79-4334-8730-51bfaff98c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176807744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2176807744
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2369408597
Short name T463
Test name
Test status
Simulation time 499642912 ps
CPU time 7.67 seconds
Started Jul 01 04:27:46 PM PDT 24
Finished Jul 01 04:28:02 PM PDT 24
Peak memory 218940 kb
Host smart-3413bad9-48ac-426e-84db-74cbabaa63be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369408597 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2369408597
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.919861837
Short name T71
Test name
Test status
Simulation time 682578050 ps
CPU time 8.19 seconds
Started Jul 01 04:27:47 PM PDT 24
Finished Jul 01 04:28:03 PM PDT 24
Peak memory 217580 kb
Host smart-7bcf5529-795f-4605-8b17-3845bfdaf982
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919861837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.919861837
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3649216460
Short name T86
Test name
Test status
Simulation time 22810635535 ps
CPU time 59.27 seconds
Started Jul 01 04:27:46 PM PDT 24
Finished Jul 01 04:28:54 PM PDT 24
Peak memory 210664 kb
Host smart-b94721a0-1d29-48ba-821f-e026a4fd1e11
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649216460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3649216460
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1489092483
Short name T75
Test name
Test status
Simulation time 2552887684 ps
CPU time 13.21 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:28:07 PM PDT 24
Peak memory 210720 kb
Host smart-bb3c2589-ee8a-4238-9d94-da7ad1ddeec9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489092483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1489092483
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3898921130
Short name T376
Test name
Test status
Simulation time 992603560 ps
CPU time 7.89 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 218892 kb
Host smart-a84e6067-1e09-4c2a-96c3-465b173e837b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898921130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3898921130
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2595073548
Short name T451
Test name
Test status
Simulation time 2466785014 ps
CPU time 80.71 seconds
Started Jul 01 04:27:40 PM PDT 24
Finished Jul 01 04:29:11 PM PDT 24
Peak memory 218860 kb
Host smart-53e455a0-c6fc-43ac-a81a-05cb810ca64a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595073548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2595073548
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1469328973
Short name T391
Test name
Test status
Simulation time 1716346353 ps
CPU time 7.5 seconds
Started Jul 01 04:27:40 PM PDT 24
Finished Jul 01 04:27:57 PM PDT 24
Peak memory 218888 kb
Host smart-fb2287c7-0e08-453b-89ad-88be4f994d48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469328973 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1469328973
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2581483732
Short name T464
Test name
Test status
Simulation time 346707850 ps
CPU time 4.21 seconds
Started Jul 01 04:27:57 PM PDT 24
Finished Jul 01 04:28:08 PM PDT 24
Peak memory 218096 kb
Host smart-6686ecd9-1b7e-42ab-beb9-f8ad89ed9c30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581483732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2581483732
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1877037968
Short name T454
Test name
Test status
Simulation time 1514827611 ps
CPU time 18.05 seconds
Started Jul 01 04:27:50 PM PDT 24
Finished Jul 01 04:28:15 PM PDT 24
Peak memory 210600 kb
Host smart-a6e447e8-c07e-4265-83b9-92e1ac513c33
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877037968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1877037968
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.385429836
Short name T438
Test name
Test status
Simulation time 88398894 ps
CPU time 4.22 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:27:58 PM PDT 24
Peak memory 218156 kb
Host smart-64779636-452e-460c-9f8c-949a62b1f8b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385429836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.385429836
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3743527411
Short name T386
Test name
Test status
Simulation time 5095281566 ps
CPU time 15.1 seconds
Started Jul 01 04:27:43 PM PDT 24
Finished Jul 01 04:28:08 PM PDT 24
Peak memory 218860 kb
Host smart-cbda4818-1e13-4907-9c29-57e8db721c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743527411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3743527411
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2429768412
Short name T116
Test name
Test status
Simulation time 1023038839 ps
CPU time 72.39 seconds
Started Jul 01 04:27:56 PM PDT 24
Finished Jul 01 04:29:15 PM PDT 24
Peak memory 212388 kb
Host smart-3d7a36bd-e1cb-4ba2-8e4e-51679b2fc189
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429768412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2429768412
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3194275727
Short name T448
Test name
Test status
Simulation time 2147602020 ps
CPU time 17.06 seconds
Started Jul 01 04:27:45 PM PDT 24
Finished Jul 01 04:28:11 PM PDT 24
Peak memory 218952 kb
Host smart-9b7a61f9-02c8-40f4-a781-09cd0c0c5066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194275727 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3194275727
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1686542524
Short name T452
Test name
Test status
Simulation time 6929652584 ps
CPU time 13.82 seconds
Started Jul 01 04:28:02 PM PDT 24
Finished Jul 01 04:28:25 PM PDT 24
Peak memory 219124 kb
Host smart-26dc42a3-2779-4072-8e14-a8cc40662c51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686542524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1686542524
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.891342999
Short name T440
Test name
Test status
Simulation time 6181398926 ps
CPU time 63.18 seconds
Started Jul 01 04:28:01 PM PDT 24
Finished Jul 01 04:29:13 PM PDT 24
Peak memory 210624 kb
Host smart-6503da5b-d76d-4a86-8327-f74edba1fc36
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891342999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.891342999
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.355204612
Short name T416
Test name
Test status
Simulation time 1888638666 ps
CPU time 7.44 seconds
Started Jul 01 04:27:54 PM PDT 24
Finished Jul 01 04:28:08 PM PDT 24
Peak memory 218396 kb
Host smart-b7c529cb-7055-4c06-9711-9029c164a666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355204612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.355204612
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3216657802
Short name T434
Test name
Test status
Simulation time 3487609043 ps
CPU time 18.16 seconds
Started Jul 01 04:27:59 PM PDT 24
Finished Jul 01 04:28:26 PM PDT 24
Peak memory 218892 kb
Host smart-4e16618b-f32b-441b-8b29-bcfd7d605fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216657802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3216657802
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1105168941
Short name T27
Test name
Test status
Simulation time 3838921037 ps
CPU time 10.35 seconds
Started Jul 01 04:31:41 PM PDT 24
Finished Jul 01 04:32:03 PM PDT 24
Peak memory 211320 kb
Host smart-4f3795e6-6574-4df3-9a44-d8464f2d49e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105168941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1105168941
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2763340967
Short name T176
Test name
Test status
Simulation time 6822052730 ps
CPU time 97.76 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:33:42 PM PDT 24
Peak memory 237772 kb
Host smart-e7278068-dc04-425f-909e-948e289df159
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763340967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2763340967
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.197189283
Short name T203
Test name
Test status
Simulation time 2678826977 ps
CPU time 18.23 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:32:27 PM PDT 24
Peak memory 212004 kb
Host smart-19ee1ded-0ef6-4dc8-8219-200bcdf2a7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197189283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.197189283
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2170996739
Short name T346
Test name
Test status
Simulation time 7749822814 ps
CPU time 16.01 seconds
Started Jul 01 04:31:37 PM PDT 24
Finished Jul 01 04:32:04 PM PDT 24
Peak memory 211332 kb
Host smart-ff762e07-d44a-49ba-863f-5e48c25324f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170996739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2170996739
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2189838564
Short name T25
Test name
Test status
Simulation time 256559794 ps
CPU time 100.8 seconds
Started Jul 01 04:31:46 PM PDT 24
Finished Jul 01 04:33:38 PM PDT 24
Peak memory 236440 kb
Host smart-6df5fd43-c527-4bfc-90b0-e71add46f7d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189838564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2189838564
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2397828286
Short name T152
Test name
Test status
Simulation time 4744262766 ps
CPU time 33.27 seconds
Started Jul 01 04:31:36 PM PDT 24
Finished Jul 01 04:32:21 PM PDT 24
Peak memory 213536 kb
Host smart-a96257aa-4373-4dac-848c-41df5083d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397828286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2397828286
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4284680386
Short name T276
Test name
Test status
Simulation time 619812703 ps
CPU time 17.65 seconds
Started Jul 01 04:31:39 PM PDT 24
Finished Jul 01 04:32:09 PM PDT 24
Peak memory 215288 kb
Host smart-56f459e0-2863-4c54-85dc-c003582b85ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284680386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4284680386
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3427213665
Short name T221
Test name
Test status
Simulation time 1604931898 ps
CPU time 12.34 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:32:16 PM PDT 24
Peak memory 211332 kb
Host smart-4312dc2e-8600-4802-aa02-3866c74195dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427213665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3427213665
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2854469765
Short name T103
Test name
Test status
Simulation time 8446551985 ps
CPU time 210.55 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:35:32 PM PDT 24
Peak memory 212772 kb
Host smart-31a1eae7-654b-4d8d-b7f6-6867117ba2af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854469765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2854469765
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1210319708
Short name T228
Test name
Test status
Simulation time 2607979146 ps
CPU time 24.93 seconds
Started Jul 01 04:31:42 PM PDT 24
Finished Jul 01 04:32:18 PM PDT 24
Peak memory 212124 kb
Host smart-4b207d3e-34ab-4729-9bcb-75e871356a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210319708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1210319708
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2399193252
Short name T66
Test name
Test status
Simulation time 5573440512 ps
CPU time 14 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:32:16 PM PDT 24
Peak memory 211436 kb
Host smart-52574418-4a72-4703-a108-65c1b41478c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399193252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2399193252
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4151563307
Short name T26
Test name
Test status
Simulation time 1796611218 ps
CPU time 61.75 seconds
Started Jul 01 04:31:37 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 236712 kb
Host smart-9f627dd1-5f87-4c42-9750-2745eba92d1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151563307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4151563307
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.605379893
Short name T256
Test name
Test status
Simulation time 7217575163 ps
CPU time 22.17 seconds
Started Jul 01 04:31:46 PM PDT 24
Finished Jul 01 04:32:20 PM PDT 24
Peak memory 213640 kb
Host smart-4c6b4a03-75f8-43d7-b647-37740e9d5743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605379893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.605379893
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3490592168
Short name T279
Test name
Test status
Simulation time 1370249887 ps
CPU time 15.35 seconds
Started Jul 01 04:31:51 PM PDT 24
Finished Jul 01 04:32:17 PM PDT 24
Peak memory 214424 kb
Host smart-81167c6b-cf25-42cd-9d9a-fe66becb5b7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490592168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3490592168
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4042579791
Short name T55
Test name
Test status
Simulation time 299898331238 ps
CPU time 861.96 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:46:09 PM PDT 24
Peak memory 229408 kb
Host smart-70059b69-64b5-44f5-ab44-5b053e3c3fe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042579791 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.4042579791
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.921140582
Short name T328
Test name
Test status
Simulation time 874860217 ps
CPU time 9.57 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:20 PM PDT 24
Peak memory 211260 kb
Host smart-ae1cfba0-70a4-4ac5-af17-d6fb82cd47d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921140582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.921140582
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3455834582
Short name T277
Test name
Test status
Simulation time 58197352917 ps
CPU time 184.72 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:35:13 PM PDT 24
Peak memory 237944 kb
Host smart-33fceb93-9447-408b-b7bd-28a5491d5042
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455834582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3455834582
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3687162540
Short name T282
Test name
Test status
Simulation time 3729264113 ps
CPU time 31.76 seconds
Started Jul 01 04:31:58 PM PDT 24
Finished Jul 01 04:32:40 PM PDT 24
Peak memory 211888 kb
Host smart-417d664e-d859-4d6f-8d6b-c43eae85f775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687162540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3687162540
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.783473656
Short name T355
Test name
Test status
Simulation time 1777713688 ps
CPU time 14.88 seconds
Started Jul 01 04:32:00 PM PDT 24
Finished Jul 01 04:32:24 PM PDT 24
Peak memory 211380 kb
Host smart-8d0793fa-8ce3-4a8e-8a9f-0b38fc70ed22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783473656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.783473656
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3609208493
Short name T231
Test name
Test status
Simulation time 2396382925 ps
CPU time 25.88 seconds
Started Jul 01 04:31:57 PM PDT 24
Finished Jul 01 04:32:33 PM PDT 24
Peak memory 213740 kb
Host smart-54343b28-02b1-4e36-b107-47714cdd1df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609208493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3609208493
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2284175
Short name T68
Test name
Test status
Simulation time 16023734401 ps
CPU time 34.75 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:32:41 PM PDT 24
Peak memory 214236 kb
Host smart-88057700-b835-4222-be8c-cd00f76c1117
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.rom_ctrl_stress_all.2284175
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.690818212
Short name T209
Test name
Test status
Simulation time 3967104630 ps
CPU time 13.52 seconds
Started Jul 01 04:32:02 PM PDT 24
Finished Jul 01 04:32:25 PM PDT 24
Peak memory 211320 kb
Host smart-403b3131-27e9-473b-abe3-227fc0f7582b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690818212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.690818212
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2185330684
Short name T359
Test name
Test status
Simulation time 519335902 ps
CPU time 13.02 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:32:26 PM PDT 24
Peak memory 212164 kb
Host smart-9c8e9ccf-5f68-4bbe-8a8b-e823efb7e611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185330684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2185330684
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3739683596
Short name T214
Test name
Test status
Simulation time 366310630 ps
CPU time 5.31 seconds
Started Jul 01 04:32:10 PM PDT 24
Finished Jul 01 04:32:23 PM PDT 24
Peak memory 211376 kb
Host smart-0932418f-3458-4bf6-a6d9-64c617cd96f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739683596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3739683596
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3162935950
Short name T310
Test name
Test status
Simulation time 2483526855 ps
CPU time 9.96 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:20 PM PDT 24
Peak memory 213948 kb
Host smart-696a1485-f084-4048-bd05-1423100d9de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162935950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3162935950
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.204813725
Short name T246
Test name
Test status
Simulation time 4218252786 ps
CPU time 42.99 seconds
Started Jul 01 04:32:13 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 214060 kb
Host smart-748a60e9-bf10-404e-9e91-319e606a5ec1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204813725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.204813725
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.600348365
Short name T139
Test name
Test status
Simulation time 501035643 ps
CPU time 5.53 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:16 PM PDT 24
Peak memory 211228 kb
Host smart-fc10a881-0308-44bd-a187-de0eedff7bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600348365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.600348365
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1055125938
Short name T261
Test name
Test status
Simulation time 789410614647 ps
CPU time 477.25 seconds
Started Jul 01 04:31:58 PM PDT 24
Finished Jul 01 04:40:06 PM PDT 24
Peak memory 237184 kb
Host smart-02fca9d9-1c51-4736-81b5-d340d5506cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055125938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1055125938
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1966882640
Short name T263
Test name
Test status
Simulation time 177526761 ps
CPU time 9.4 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:19 PM PDT 24
Peak memory 211864 kb
Host smart-05b9d9cd-8193-458e-8b2b-65f2e0ae2469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966882640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1966882640
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3811846733
Short name T213
Test name
Test status
Simulation time 3606845936 ps
CPU time 13.74 seconds
Started Jul 01 04:32:03 PM PDT 24
Finished Jul 01 04:32:25 PM PDT 24
Peak memory 211536 kb
Host smart-96e86261-16b9-4ac7-87b5-a1647a3556d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811846733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3811846733
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.690902429
Short name T201
Test name
Test status
Simulation time 4631117003 ps
CPU time 14.99 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:32:44 PM PDT 24
Peak memory 211420 kb
Host smart-762df832-c142-411e-a5c9-887f5c5ef0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690902429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.690902429
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.744612968
Short name T356
Test name
Test status
Simulation time 716245997 ps
CPU time 9.3 seconds
Started Jul 01 04:32:06 PM PDT 24
Finished Jul 01 04:32:24 PM PDT 24
Peak memory 211248 kb
Host smart-403f68a3-8e6e-4507-b62e-cd4456998aae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744612968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.744612968
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1017738196
Short name T271
Test name
Test status
Simulation time 6389364689 ps
CPU time 14.44 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:32:38 PM PDT 24
Peak memory 211264 kb
Host smart-29ba9dc2-84af-43fc-9e42-79d42953e8bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017738196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1017738196
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3241586388
Short name T227
Test name
Test status
Simulation time 18237096691 ps
CPU time 236.14 seconds
Started Jul 01 04:32:06 PM PDT 24
Finished Jul 01 04:36:10 PM PDT 24
Peak memory 234928 kb
Host smart-4901fe08-f08b-416c-9a3d-07d5b960523d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241586388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3241586388
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1931510937
Short name T259
Test name
Test status
Simulation time 349055045 ps
CPU time 9.16 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:32:14 PM PDT 24
Peak memory 212020 kb
Host smart-ea7adcb3-7162-4739-bd2c-d86d222c4902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931510937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1931510937
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3288644003
Short name T294
Test name
Test status
Simulation time 383000812 ps
CPU time 5.57 seconds
Started Jul 01 04:32:02 PM PDT 24
Finished Jul 01 04:32:17 PM PDT 24
Peak memory 211304 kb
Host smart-6123717d-0f59-4da2-b496-53adc5b9be4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288644003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3288644003
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2071887311
Short name T166
Test name
Test status
Simulation time 22997913514 ps
CPU time 28.79 seconds
Started Jul 01 04:31:55 PM PDT 24
Finished Jul 01 04:32:35 PM PDT 24
Peak memory 213932 kb
Host smart-59ba3449-3a1a-4b2a-9b76-9b67c659e20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071887311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2071887311
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3443036146
Short name T216
Test name
Test status
Simulation time 2920483567 ps
CPU time 33.2 seconds
Started Jul 01 04:32:05 PM PDT 24
Finished Jul 01 04:32:46 PM PDT 24
Peak memory 217324 kb
Host smart-6b00cba6-600b-4a3c-b6bd-27afe3ada6f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443036146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3443036146
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3611774962
Short name T258
Test name
Test status
Simulation time 31417753066 ps
CPU time 2655.08 seconds
Started Jul 01 04:32:08 PM PDT 24
Finished Jul 01 05:16:32 PM PDT 24
Peak memory 232792 kb
Host smart-a60234d1-6cde-44d2-89f5-0dc049de815e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611774962 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3611774962
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.727014537
Short name T264
Test name
Test status
Simulation time 3850828384 ps
CPU time 15.22 seconds
Started Jul 01 04:32:03 PM PDT 24
Finished Jul 01 04:32:27 PM PDT 24
Peak memory 211392 kb
Host smart-b272853b-e45f-4277-8276-4e5dc05047d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727014537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.727014537
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3133026611
Short name T297
Test name
Test status
Simulation time 9816203279 ps
CPU time 159.55 seconds
Started Jul 01 04:32:10 PM PDT 24
Finished Jul 01 04:34:59 PM PDT 24
Peak memory 236800 kb
Host smart-a932ec62-25cc-4356-828e-3d111f1ca47c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133026611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3133026611
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2836789743
Short name T308
Test name
Test status
Simulation time 7986542837 ps
CPU time 31.54 seconds
Started Jul 01 04:31:55 PM PDT 24
Finished Jul 01 04:32:37 PM PDT 24
Peak memory 212504 kb
Host smart-1b14438e-b108-4649-8395-60442192cbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836789743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2836789743
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1687059228
Short name T5
Test name
Test status
Simulation time 99055991 ps
CPU time 5.18 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:32:11 PM PDT 24
Peak memory 211260 kb
Host smart-43148cd0-4f90-4c52-afcc-17eb854b890f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687059228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1687059228
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.836515043
Short name T229
Test name
Test status
Simulation time 20691881018 ps
CPU time 20.21 seconds
Started Jul 01 04:32:02 PM PDT 24
Finished Jul 01 04:32:31 PM PDT 24
Peak memory 213252 kb
Host smart-87ad16a6-36fa-4703-b9b6-c375c42a4490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836515043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.836515043
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.777179641
Short name T367
Test name
Test status
Simulation time 14141503369 ps
CPU time 65.86 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:33:16 PM PDT 24
Peak memory 217516 kb
Host smart-de419616-bab7-43e0-8b21-589320bc829a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777179641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.777179641
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4146423284
Short name T357
Test name
Test status
Simulation time 20690705395 ps
CPU time 243.4 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:36:12 PM PDT 24
Peak memory 236796 kb
Host smart-e3f39e35-69a5-4804-86f7-ca5d08ab7dc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146423284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4146423284
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2334234065
Short name T345
Test name
Test status
Simulation time 2629800244 ps
CPU time 10.81 seconds
Started Jul 01 04:32:13 PM PDT 24
Finished Jul 01 04:32:33 PM PDT 24
Peak memory 211476 kb
Host smart-53d46361-743b-48c3-bb0f-4c215dde7216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334234065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2334234065
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2145687680
Short name T196
Test name
Test status
Simulation time 39482259666 ps
CPU time 22.16 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:32 PM PDT 24
Peak memory 213944 kb
Host smart-72e4b6a0-33ca-4adc-b79c-457d29bd36f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145687680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2145687680
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3538730562
Short name T169
Test name
Test status
Simulation time 213380863 ps
CPU time 10.03 seconds
Started Jul 01 04:32:06 PM PDT 24
Finished Jul 01 04:32:24 PM PDT 24
Peak memory 211228 kb
Host smart-ad91bf66-0626-46d0-b71a-5ffde05367fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538730562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3538730562
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.434511680
Short name T62
Test name
Test status
Simulation time 8755484126 ps
CPU time 15.53 seconds
Started Jul 01 04:32:21 PM PDT 24
Finished Jul 01 04:32:52 PM PDT 24
Peak memory 211388 kb
Host smart-7c497a31-ef29-463b-a94c-a0d98136f14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434511680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.434511680
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2652543469
Short name T104
Test name
Test status
Simulation time 18906943751 ps
CPU time 158.31 seconds
Started Jul 01 04:32:15 PM PDT 24
Finished Jul 01 04:35:04 PM PDT 24
Peak memory 212832 kb
Host smart-6939b1ee-1258-4691-8a12-d1ef66ba0608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652543469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2652543469
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1375764965
Short name T150
Test name
Test status
Simulation time 3022969748 ps
CPU time 27.32 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:33:08 PM PDT 24
Peak memory 212740 kb
Host smart-acc6d920-d609-45af-8018-70555319a2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375764965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1375764965
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.964686636
Short name T302
Test name
Test status
Simulation time 705965227 ps
CPU time 9.47 seconds
Started Jul 01 04:32:13 PM PDT 24
Finished Jul 01 04:32:32 PM PDT 24
Peak memory 211508 kb
Host smart-6f2f5329-e890-4dd4-847a-a6610c1ebc95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964686636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.964686636
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3166764268
Short name T156
Test name
Test status
Simulation time 7890963433 ps
CPU time 36.41 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:32:43 PM PDT 24
Peak memory 212600 kb
Host smart-38b1e32b-b105-48f6-bd64-53f1a78fb58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166764268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3166764268
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.553052563
Short name T317
Test name
Test status
Simulation time 9090322771 ps
CPU time 37.48 seconds
Started Jul 01 04:32:00 PM PDT 24
Finished Jul 01 04:32:46 PM PDT 24
Peak memory 217236 kb
Host smart-8b23bb0e-0a71-4d6d-8935-cd947e24f586
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553052563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.553052563
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.44974461
Short name T342
Test name
Test status
Simulation time 417191949 ps
CPU time 4.38 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:32:17 PM PDT 24
Peak memory 211452 kb
Host smart-005cd49e-54e1-456a-b5d0-a846b942df5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44974461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.44974461
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4116986612
Short name T289
Test name
Test status
Simulation time 119951024994 ps
CPU time 292.99 seconds
Started Jul 01 04:32:09 PM PDT 24
Finished Jul 01 04:37:11 PM PDT 24
Peak memory 234764 kb
Host smart-e24ee003-e76d-4036-bb54-552d2c1f48f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116986612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4116986612
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3700760269
Short name T222
Test name
Test status
Simulation time 6481891523 ps
CPU time 19.05 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:32:45 PM PDT 24
Peak memory 211520 kb
Host smart-549673ba-753b-4e2d-a34c-89634007192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700760269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3700760269
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.228172373
Short name T171
Test name
Test status
Simulation time 3100155037 ps
CPU time 14.09 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:32:43 PM PDT 24
Peak memory 211476 kb
Host smart-a4f595f1-61af-4d6a-9c2a-31c9890b142e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228172373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.228172373
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1270448854
Short name T32
Test name
Test status
Simulation time 957664587 ps
CPU time 15.54 seconds
Started Jul 01 04:32:17 PM PDT 24
Finished Jul 01 04:32:45 PM PDT 24
Peak memory 213372 kb
Host smart-60c37246-8ade-4644-a12c-7499d7c50c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270448854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1270448854
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3536728659
Short name T333
Test name
Test status
Simulation time 593779220 ps
CPU time 10.26 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:32:23 PM PDT 24
Peak memory 210928 kb
Host smart-c4898509-41e9-42b2-8fb5-d673c4e5423e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536728659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3536728659
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.648731645
Short name T304
Test name
Test status
Simulation time 6598538483 ps
CPU time 13.95 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:24 PM PDT 24
Peak memory 211388 kb
Host smart-f108afd8-edf6-4549-92ec-62f38c9008e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648731645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.648731645
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2172919360
Short name T354
Test name
Test status
Simulation time 34494947171 ps
CPU time 331.66 seconds
Started Jul 01 04:32:17 PM PDT 24
Finished Jul 01 04:38:02 PM PDT 24
Peak memory 234868 kb
Host smart-e9bd423d-5260-408c-bf48-8ffd0e6a88c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172919360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2172919360
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.793060848
Short name T183
Test name
Test status
Simulation time 11346605803 ps
CPU time 25.45 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 212220 kb
Host smart-8dc8242c-95d0-4a18-b86e-017f54b1fc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793060848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.793060848
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4171042359
Short name T266
Test name
Test status
Simulation time 4167790567 ps
CPU time 10.54 seconds
Started Jul 01 04:32:12 PM PDT 24
Finished Jul 01 04:32:32 PM PDT 24
Peak memory 211344 kb
Host smart-7a088d79-40db-4c1a-ad66-fdc25c818188
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171042359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4171042359
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4257078076
Short name T232
Test name
Test status
Simulation time 14874070816 ps
CPU time 22.36 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:32:31 PM PDT 24
Peak memory 212940 kb
Host smart-31a6aaa2-5b5b-4df8-89b0-d399624d86ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257078076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4257078076
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1519384898
Short name T30
Test name
Test status
Simulation time 5523388725 ps
CPU time 34.1 seconds
Started Jul 01 04:32:12 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 217320 kb
Host smart-86a64fe1-433d-45f3-9a74-fcd7cbc0081d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519384898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1519384898
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3932939627
Short name T318
Test name
Test status
Simulation time 599851294 ps
CPU time 8.07 seconds
Started Jul 01 04:32:19 PM PDT 24
Finished Jul 01 04:32:43 PM PDT 24
Peak memory 211268 kb
Host smart-7895b988-dc31-427f-80e7-be808a176e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932939627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3932939627
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.710701676
Short name T269
Test name
Test status
Simulation time 3075269040 ps
CPU time 14.3 seconds
Started Jul 01 04:32:10 PM PDT 24
Finished Jul 01 04:32:33 PM PDT 24
Peak memory 212008 kb
Host smart-59e2cfa3-1ad5-4677-93fb-981b591adc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710701676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.710701676
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.568354907
Short name T177
Test name
Test status
Simulation time 373752760 ps
CPU time 5.46 seconds
Started Jul 01 04:32:10 PM PDT 24
Finished Jul 01 04:32:24 PM PDT 24
Peak memory 211376 kb
Host smart-3d6a17e7-d685-45eb-a3b1-df1d9043f89a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568354907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.568354907
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.749230029
Short name T157
Test name
Test status
Simulation time 3214588187 ps
CPU time 28.36 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 213420 kb
Host smart-b0bd21d2-8b2a-4c74-a221-deb7a2d96dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749230029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.749230029
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.211789837
Short name T347
Test name
Test status
Simulation time 524547422 ps
CPU time 7.67 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:32:12 PM PDT 24
Peak memory 211420 kb
Host smart-4e84d213-0ffc-44c9-a89f-e0d1ac3cc48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211789837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.211789837
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3390821116
Short name T334
Test name
Test status
Simulation time 132920957950 ps
CPU time 262.11 seconds
Started Jul 01 04:31:37 PM PDT 24
Finished Jul 01 04:36:11 PM PDT 24
Peak memory 213532 kb
Host smart-b2436dc2-34de-4ec7-8cdb-353e062c7335
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390821116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3390821116
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4190576076
Short name T197
Test name
Test status
Simulation time 261609016 ps
CPU time 11.01 seconds
Started Jul 01 04:31:51 PM PDT 24
Finished Jul 01 04:32:13 PM PDT 24
Peak memory 211844 kb
Host smart-b58efda0-cda7-4d88-96f0-f40aa9849d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190576076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4190576076
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.639752585
Short name T200
Test name
Test status
Simulation time 1276828573 ps
CPU time 12.4 seconds
Started Jul 01 04:31:49 PM PDT 24
Finished Jul 01 04:32:13 PM PDT 24
Peak memory 211296 kb
Host smart-7344c578-f353-4c14-8dd7-46d1fb76ff4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639752585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.639752585
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3799343027
Short name T17
Test name
Test status
Simulation time 10784167653 ps
CPU time 106.9 seconds
Started Jul 01 04:31:57 PM PDT 24
Finished Jul 01 04:33:54 PM PDT 24
Peak memory 236988 kb
Host smart-ff4f5c63-42c2-4944-93a1-b930bfe1ea34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799343027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3799343027
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1031020715
Short name T339
Test name
Test status
Simulation time 1331165619 ps
CPU time 17.63 seconds
Started Jul 01 04:31:38 PM PDT 24
Finished Jul 01 04:32:07 PM PDT 24
Peak memory 211632 kb
Host smart-71882e78-4b10-47df-a026-838d54507256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031020715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1031020715
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3950056210
Short name T314
Test name
Test status
Simulation time 1589447530 ps
CPU time 20.29 seconds
Started Jul 01 04:31:35 PM PDT 24
Finished Jul 01 04:32:08 PM PDT 24
Peak memory 216352 kb
Host smart-159b9f76-9248-4eab-b53f-53414f5fe514
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950056210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3950056210
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1340577350
Short name T138
Test name
Test status
Simulation time 2959042119 ps
CPU time 14.94 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:32:28 PM PDT 24
Peak memory 211216 kb
Host smart-193a2489-5675-49e1-8878-ae5ccf7e2184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340577350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1340577350
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4275293757
Short name T274
Test name
Test status
Simulation time 57888568332 ps
CPU time 173.7 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:35:04 PM PDT 24
Peak memory 237872 kb
Host smart-c5869c3b-c0d0-4ee1-bf03-25a518f40098
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275293757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4275293757
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3907124271
Short name T295
Test name
Test status
Simulation time 8580507017 ps
CPU time 21.17 seconds
Started Jul 01 04:32:02 PM PDT 24
Finished Jul 01 04:32:32 PM PDT 24
Peak memory 212500 kb
Host smart-a5002469-e78f-4642-8c9e-5817c8a51a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907124271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3907124271
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2398677675
Short name T235
Test name
Test status
Simulation time 99342207 ps
CPU time 5.53 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:16 PM PDT 24
Peak memory 211376 kb
Host smart-30dad418-c931-4602-b093-fcda5648e5a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398677675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2398677675
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4246709867
Short name T370
Test name
Test status
Simulation time 2502850241 ps
CPU time 23.95 seconds
Started Jul 01 04:32:18 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 213672 kb
Host smart-6212a059-4d83-4de5-8b2d-4b2b6b2ebc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246709867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4246709867
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.155768768
Short name T67
Test name
Test status
Simulation time 221281994 ps
CPU time 7.58 seconds
Started Jul 01 04:32:09 PM PDT 24
Finished Jul 01 04:32:24 PM PDT 24
Peak memory 211312 kb
Host smart-ee50c219-f3ff-40f8-8fbf-cc6a2ac58463
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155768768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.155768768
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1245861135
Short name T337
Test name
Test status
Simulation time 686687109 ps
CPU time 6.25 seconds
Started Jul 01 04:32:02 PM PDT 24
Finished Jul 01 04:32:17 PM PDT 24
Peak memory 211228 kb
Host smart-a99ad65e-82df-4aeb-93e5-00e531cba8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245861135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1245861135
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1252900134
Short name T36
Test name
Test status
Simulation time 62847130559 ps
CPU time 270.11 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:36:36 PM PDT 24
Peak memory 237816 kb
Host smart-a1e2a255-9c30-492e-869a-434c161f860e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252900134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1252900134
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3851407082
Short name T343
Test name
Test status
Simulation time 6901034716 ps
CPU time 19.96 seconds
Started Jul 01 04:32:22 PM PDT 24
Finished Jul 01 04:32:58 PM PDT 24
Peak memory 211512 kb
Host smart-6556898d-a95a-4356-ab24-f86322292d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851407082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3851407082
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2995234188
Short name T147
Test name
Test status
Simulation time 2198840886 ps
CPU time 15.81 seconds
Started Jul 01 04:32:18 PM PDT 24
Finished Jul 01 04:32:47 PM PDT 24
Peak memory 211440 kb
Host smart-d5762d42-6706-4000-b93e-a1be92e11642
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995234188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2995234188
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3713195635
Short name T219
Test name
Test status
Simulation time 3337977172 ps
CPU time 15.23 seconds
Started Jul 01 04:32:00 PM PDT 24
Finished Jul 01 04:32:25 PM PDT 24
Peak memory 213612 kb
Host smart-6578a89f-178e-4232-bcd3-35674545c1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713195635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3713195635
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1095279920
Short name T220
Test name
Test status
Simulation time 1110316198 ps
CPU time 18.51 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:32:47 PM PDT 24
Peak memory 214160 kb
Host smart-c924aebb-ae42-4afb-8c2e-2b04c25feb91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095279920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1095279920
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2713313744
Short name T51
Test name
Test status
Simulation time 43620231135 ps
CPU time 1810.78 seconds
Started Jul 01 04:32:09 PM PDT 24
Finished Jul 01 05:02:28 PM PDT 24
Peak memory 237792 kb
Host smart-d52d02d0-a9ee-45a9-ad31-ad21dd82d68f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713313744 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2713313744
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2618778538
Short name T63
Test name
Test status
Simulation time 1941858501 ps
CPU time 11.6 seconds
Started Jul 01 04:32:17 PM PDT 24
Finished Jul 01 04:32:42 PM PDT 24
Peak memory 211228 kb
Host smart-86d9ce86-5422-45bb-9934-5130f590e943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618778538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2618778538
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.438227657
Short name T49
Test name
Test status
Simulation time 116780659307 ps
CPU time 169.63 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 233684 kb
Host smart-edf048ae-f1ae-4448-aacc-4538f713c4ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438227657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.438227657
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2871078739
Short name T194
Test name
Test status
Simulation time 10741922152 ps
CPU time 23.55 seconds
Started Jul 01 04:32:08 PM PDT 24
Finished Jul 01 04:32:40 PM PDT 24
Peak memory 212924 kb
Host smart-30f5757f-be7b-4fb7-9d35-b85583fa2058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871078739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2871078739
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2233200992
Short name T225
Test name
Test status
Simulation time 2557632140 ps
CPU time 8.95 seconds
Started Jul 01 04:32:21 PM PDT 24
Finished Jul 01 04:32:45 PM PDT 24
Peak memory 211444 kb
Host smart-cc66eea2-d5e4-4ed4-9916-d5f48d740378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233200992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2233200992
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3015316608
Short name T207
Test name
Test status
Simulation time 2946261902 ps
CPU time 20.23 seconds
Started Jul 01 04:32:06 PM PDT 24
Finished Jul 01 04:32:35 PM PDT 24
Peak memory 211768 kb
Host smart-9669605c-300e-459e-8315-4bd0d997fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015316608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3015316608
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1396133245
Short name T338
Test name
Test status
Simulation time 4148306098 ps
CPU time 16.85 seconds
Started Jul 01 04:32:03 PM PDT 24
Finished Jul 01 04:32:28 PM PDT 24
Peak memory 212060 kb
Host smart-39000d23-d575-4740-a237-9518a7dce344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396133245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1396133245
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1529681980
Short name T178
Test name
Test status
Simulation time 2045363222 ps
CPU time 16.57 seconds
Started Jul 01 04:32:09 PM PDT 24
Finished Jul 01 04:32:33 PM PDT 24
Peak memory 211268 kb
Host smart-ee53b267-e46f-47cc-9ce6-f3817af92a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529681980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1529681980
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4001817728
Short name T39
Test name
Test status
Simulation time 13833730716 ps
CPU time 169.57 seconds
Started Jul 01 04:32:12 PM PDT 24
Finished Jul 01 04:35:11 PM PDT 24
Peak memory 233884 kb
Host smart-133ef1e5-21a1-4aa9-af14-168bb84b09f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001817728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4001817728
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1892279527
Short name T368
Test name
Test status
Simulation time 695927284 ps
CPU time 14.25 seconds
Started Jul 01 04:32:21 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 212092 kb
Host smart-84146ff7-8055-4d2a-8d04-aaf5a3f90de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892279527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1892279527
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2081949298
Short name T360
Test name
Test status
Simulation time 3512394174 ps
CPU time 10.29 seconds
Started Jul 01 04:32:20 PM PDT 24
Finished Jul 01 04:32:46 PM PDT 24
Peak memory 211308 kb
Host smart-8cd36813-0948-4655-b819-f28c9583ac9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081949298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2081949298
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3882048239
Short name T154
Test name
Test status
Simulation time 374910658 ps
CPU time 10.04 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:32:32 PM PDT 24
Peak memory 213668 kb
Host smart-6f81f1e0-fb58-4651-8357-0e9601aa4530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882048239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3882048239
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1735356713
Short name T83
Test name
Test status
Simulation time 5111747780 ps
CPU time 49.1 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 213320 kb
Host smart-ede5942b-a361-493a-b9e5-3e3cbcd35e24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735356713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1735356713
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.374072455
Short name T326
Test name
Test status
Simulation time 27047391012 ps
CPU time 12.73 seconds
Started Jul 01 04:32:11 PM PDT 24
Finished Jul 01 04:32:32 PM PDT 24
Peak memory 211392 kb
Host smart-6802172a-7669-426d-9f6e-9cea6d905bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374072455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.374072455
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2712915134
Short name T254
Test name
Test status
Simulation time 10630198992 ps
CPU time 181.54 seconds
Started Jul 01 04:32:03 PM PDT 24
Finished Jul 01 04:35:14 PM PDT 24
Peak memory 212552 kb
Host smart-de8297a2-9b55-4fca-ba56-252623567d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712915134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2712915134
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1724585940
Short name T224
Test name
Test status
Simulation time 1331341694 ps
CPU time 12.65 seconds
Started Jul 01 04:32:20 PM PDT 24
Finished Jul 01 04:32:49 PM PDT 24
Peak memory 211376 kb
Host smart-48404470-1953-4e3e-b965-fe091401e9e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724585940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1724585940
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3149114386
Short name T206
Test name
Test status
Simulation time 1976029838 ps
CPU time 23.37 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:32:36 PM PDT 24
Peak memory 213428 kb
Host smart-eea16836-dd70-4d57-adaa-7d6fa7ef1102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149114386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3149114386
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2616098333
Short name T11
Test name
Test status
Simulation time 572897697 ps
CPU time 34.7 seconds
Started Jul 01 04:32:11 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 215392 kb
Host smart-df7962be-ea34-4441-be9c-4ea058b7df06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616098333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2616098333
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3506661854
Short name T185
Test name
Test status
Simulation time 307576471 ps
CPU time 6.32 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:32:47 PM PDT 24
Peak memory 211244 kb
Host smart-0400e46c-2825-4054-a9ba-4bb5000779b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506661854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3506661854
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2905624053
Short name T215
Test name
Test status
Simulation time 83308295087 ps
CPU time 227.49 seconds
Started Jul 01 04:32:17 PM PDT 24
Finished Jul 01 04:36:17 PM PDT 24
Peak memory 213116 kb
Host smart-9826b647-a4df-42fa-b483-6db4ad5c6534
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905624053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2905624053
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3173569443
Short name T255
Test name
Test status
Simulation time 13704108249 ps
CPU time 29.57 seconds
Started Jul 01 04:32:13 PM PDT 24
Finished Jul 01 04:32:52 PM PDT 24
Peak memory 211416 kb
Host smart-5cf4d446-8624-46e4-80cd-7ef3963985ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173569443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3173569443
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3431747210
Short name T251
Test name
Test status
Simulation time 2517449494 ps
CPU time 12.95 seconds
Started Jul 01 04:32:17 PM PDT 24
Finished Jul 01 04:32:43 PM PDT 24
Peak memory 211436 kb
Host smart-5958351f-0cab-4b60-9e97-47ac4f4b6087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431747210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3431747210
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3011451479
Short name T188
Test name
Test status
Simulation time 8911695128 ps
CPU time 23.83 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:32:37 PM PDT 24
Peak memory 213876 kb
Host smart-22b5f40d-6896-4f23-a15f-69cca1b6d442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011451479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3011451479
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.507906418
Short name T153
Test name
Test status
Simulation time 10677215895 ps
CPU time 99.91 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 219308 kb
Host smart-56a81179-fc58-4a27-89e7-af5218245b61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507906418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.507906418
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.856339980
Short name T100
Test name
Test status
Simulation time 20557126995 ps
CPU time 789.08 seconds
Started Jul 01 04:32:13 PM PDT 24
Finished Jul 01 04:45:31 PM PDT 24
Peak memory 235544 kb
Host smart-948e261e-ede8-4cd3-a8c3-dade4edff796
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856339980 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.856339980
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4019999494
Short name T270
Test name
Test status
Simulation time 1439831242 ps
CPU time 13.2 seconds
Started Jul 01 04:32:03 PM PDT 24
Finished Jul 01 04:32:25 PM PDT 24
Peak memory 211236 kb
Host smart-15d1008a-9819-4071-a2ca-c9c2da9c2ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019999494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4019999494
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.853809962
Short name T292
Test name
Test status
Simulation time 7357156256 ps
CPU time 70.28 seconds
Started Jul 01 04:32:05 PM PDT 24
Finished Jul 01 04:33:24 PM PDT 24
Peak memory 227692 kb
Host smart-86979617-338c-4730-be55-0685571eb292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853809962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.853809962
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2086353674
Short name T349
Test name
Test status
Simulation time 13296766018 ps
CPU time 31.88 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:33:11 PM PDT 24
Peak memory 212316 kb
Host smart-f53e16a9-ebfd-4465-a40b-e899558a3bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086353674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2086353674
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2585996105
Short name T208
Test name
Test status
Simulation time 2417291982 ps
CPU time 12.33 seconds
Started Jul 01 04:32:08 PM PDT 24
Finished Jul 01 04:32:28 PM PDT 24
Peak memory 211332 kb
Host smart-62e527f0-cdda-4105-9eed-86035f67f488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585996105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2585996105
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.448913091
Short name T321
Test name
Test status
Simulation time 64207160313 ps
CPU time 32.9 seconds
Started Jul 01 04:32:10 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 213792 kb
Host smart-0663a64c-a689-4268-9d1d-b3a21d9e0221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448913091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.448913091
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.758643999
Short name T230
Test name
Test status
Simulation time 3048326807 ps
CPU time 67.51 seconds
Started Jul 01 04:32:18 PM PDT 24
Finished Jul 01 04:33:39 PM PDT 24
Peak memory 218804 kb
Host smart-d48b139c-6790-4fad-b3df-eb5e2840de84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758643999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.758643999
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.970659662
Short name T130
Test name
Test status
Simulation time 7340796468 ps
CPU time 14.61 seconds
Started Jul 01 04:32:15 PM PDT 24
Finished Jul 01 04:32:40 PM PDT 24
Peak memory 211456 kb
Host smart-128b55a2-5850-4191-8e54-62f2051ac50f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970659662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.970659662
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1786076262
Short name T28
Test name
Test status
Simulation time 61393130430 ps
CPU time 412.37 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:39:06 PM PDT 24
Peak memory 213360 kb
Host smart-47b19520-b392-499e-9a37-1fa27d313c1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786076262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1786076262
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3344974254
Short name T340
Test name
Test status
Simulation time 1506705354 ps
CPU time 11.82 seconds
Started Jul 01 04:32:07 PM PDT 24
Finished Jul 01 04:32:27 PM PDT 24
Peak memory 211920 kb
Host smart-3bf1060d-9e59-4506-bf49-1749dfb3ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344974254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3344974254
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.381855884
Short name T35
Test name
Test status
Simulation time 2713565475 ps
CPU time 21.17 seconds
Started Jul 01 04:32:10 PM PDT 24
Finished Jul 01 04:32:39 PM PDT 24
Peak memory 213812 kb
Host smart-91e02a5b-6a96-4b3f-8070-8ef13cc15cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381855884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.381855884
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2312357318
Short name T80
Test name
Test status
Simulation time 2673823294 ps
CPU time 38.8 seconds
Started Jul 01 04:32:19 PM PDT 24
Finished Jul 01 04:33:14 PM PDT 24
Peak memory 214376 kb
Host smart-a8351826-c51b-49d4-afff-aec5ba72a330
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312357318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2312357318
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2286047663
Short name T167
Test name
Test status
Simulation time 1519633957 ps
CPU time 12.4 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:32:40 PM PDT 24
Peak memory 211200 kb
Host smart-d225192b-c3b5-40f9-87ba-687992c1232e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286047663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2286047663
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1098339010
Short name T305
Test name
Test status
Simulation time 36179658169 ps
CPU time 347.44 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:38:28 PM PDT 24
Peak memory 225400 kb
Host smart-7899ce73-75b6-4cab-ac78-4edcec3fbde1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098339010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1098339010
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.919167341
Short name T205
Test name
Test status
Simulation time 914515885 ps
CPU time 15.27 seconds
Started Jul 01 04:32:21 PM PDT 24
Finished Jul 01 04:32:52 PM PDT 24
Peak memory 211332 kb
Host smart-bcccb6ca-489c-4827-82b4-64b6465fcbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919167341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.919167341
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.175707081
Short name T327
Test name
Test status
Simulation time 6355276324 ps
CPU time 9.8 seconds
Started Jul 01 04:32:20 PM PDT 24
Finished Jul 01 04:32:45 PM PDT 24
Peak memory 211428 kb
Host smart-e6b72a5e-5136-4f6a-983e-30ed77a59d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175707081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.175707081
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.4252203708
Short name T284
Test name
Test status
Simulation time 3187248644 ps
CPU time 15.55 seconds
Started Jul 01 04:32:07 PM PDT 24
Finished Jul 01 04:32:31 PM PDT 24
Peak memory 213316 kb
Host smart-01d4f1c8-7862-46bd-b16b-78ebc855dd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252203708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.4252203708
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.660001599
Short name T143
Test name
Test status
Simulation time 2730669202 ps
CPU time 34.73 seconds
Started Jul 01 04:32:09 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 215884 kb
Host smart-8dd377da-0453-42aa-96b8-29fd29dd9026
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660001599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.660001599
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3096719068
Short name T134
Test name
Test status
Simulation time 89250076 ps
CPU time 4.31 seconds
Started Jul 01 04:32:15 PM PDT 24
Finished Jul 01 04:32:30 PM PDT 24
Peak memory 211220 kb
Host smart-ef938f05-6052-468f-a245-c986931a6d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096719068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3096719068
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1760995442
Short name T280
Test name
Test status
Simulation time 10858221248 ps
CPU time 166.51 seconds
Started Jul 01 04:32:15 PM PDT 24
Finished Jul 01 04:35:12 PM PDT 24
Peak memory 235760 kb
Host smart-6854c959-1f00-445d-9964-35045c6d4b68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760995442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1760995442
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2604615108
Short name T353
Test name
Test status
Simulation time 266008037 ps
CPU time 9.23 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:32:38 PM PDT 24
Peak memory 212088 kb
Host smart-ff44cdd8-b0b5-40bb-bf67-4f3ae2e7af83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604615108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2604615108
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.603087423
Short name T331
Test name
Test status
Simulation time 4998026687 ps
CPU time 12.49 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:32:37 PM PDT 24
Peak memory 211496 kb
Host smart-1c3d00f6-e4ae-43db-8cd9-280df65be40c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603087423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.603087423
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.423861597
Short name T243
Test name
Test status
Simulation time 38085374266 ps
CPU time 31.05 seconds
Started Jul 01 04:32:11 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 214256 kb
Host smart-206d4d31-99cf-47a5-b293-c1fe090e86ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423861597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.423861597
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.752719413
Short name T286
Test name
Test status
Simulation time 3756585741 ps
CPU time 22.66 seconds
Started Jul 01 04:32:08 PM PDT 24
Finished Jul 01 04:32:39 PM PDT 24
Peak memory 215672 kb
Host smart-9316cf62-a747-4e4e-8651-bd7952032b11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752719413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.752719413
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.829117203
Short name T64
Test name
Test status
Simulation time 1523696694 ps
CPU time 13.23 seconds
Started Jul 01 04:31:47 PM PDT 24
Finished Jul 01 04:32:12 PM PDT 24
Peak memory 211360 kb
Host smart-2fa32fe6-32d2-40e5-9a94-dd252f0d13cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829117203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.829117203
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.48693536
Short name T252
Test name
Test status
Simulation time 43078984051 ps
CPU time 411.86 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:38:58 PM PDT 24
Peak memory 228568 kb
Host smart-939fc232-ad41-48c4-ba60-36afdb0d1d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48693536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_cor
rupt_sig_fatal_chk.48693536
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1390739907
Short name T306
Test name
Test status
Simulation time 43724107033 ps
CPU time 32.99 seconds
Started Jul 01 04:31:47 PM PDT 24
Finished Jul 01 04:32:31 PM PDT 24
Peak memory 212216 kb
Host smart-96053c9d-2953-4c2d-94b7-b0a7f7b907e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390739907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1390739907
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3907974059
Short name T172
Test name
Test status
Simulation time 644015988 ps
CPU time 9.58 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:32:18 PM PDT 24
Peak memory 211528 kb
Host smart-16112495-ed7f-4171-bd79-9f973477ae25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907974059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3907974059
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2881335403
Short name T18
Test name
Test status
Simulation time 2705136767 ps
CPU time 57.87 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:33:03 PM PDT 24
Peak memory 236828 kb
Host smart-84d7022f-1f6b-4186-933e-4c6a8ebfc348
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881335403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2881335403
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.820464378
Short name T101
Test name
Test status
Simulation time 360837039 ps
CPU time 9.86 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:32:15 PM PDT 24
Peak memory 213748 kb
Host smart-bc280599-1a41-4378-b8de-05fb4b4bbfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820464378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.820464378
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1765634418
Short name T191
Test name
Test status
Simulation time 11597229105 ps
CPU time 31.59 seconds
Started Jul 01 04:31:50 PM PDT 24
Finished Jul 01 04:32:33 PM PDT 24
Peak memory 215568 kb
Host smart-a0afe0e1-b209-4d4d-a1e3-93fe3fa86b0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765634418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1765634418
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1795896233
Short name T195
Test name
Test status
Simulation time 2051719601 ps
CPU time 16.08 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 211368 kb
Host smart-c314bbba-3854-44dd-b4b1-1a2c96a97fcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795896233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1795896233
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2422717514
Short name T1
Test name
Test status
Simulation time 3771882343 ps
CPU time 131.28 seconds
Started Jul 01 04:32:22 PM PDT 24
Finished Jul 01 04:34:49 PM PDT 24
Peak memory 213196 kb
Host smart-284b96ea-5cb5-486c-91f2-3f0aaba361fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422717514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2422717514
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3069576886
Short name T348
Test name
Test status
Simulation time 3841780385 ps
CPU time 31.01 seconds
Started Jul 01 04:32:17 PM PDT 24
Finished Jul 01 04:33:01 PM PDT 24
Peak memory 211964 kb
Host smart-eff21b84-4989-4567-9984-68bd0faa4c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069576886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3069576886
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1879432598
Short name T272
Test name
Test status
Simulation time 1199613365 ps
CPU time 12.44 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:32:37 PM PDT 24
Peak memory 211316 kb
Host smart-01ecd5a2-c1fc-42df-8b6f-40b239bc0d5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879432598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1879432598
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.213420334
Short name T324
Test name
Test status
Simulation time 187217467 ps
CPU time 10.39 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:32:33 PM PDT 24
Peak memory 214144 kb
Host smart-3291ac3c-6d51-48c1-aac3-44a8a88403e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213420334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.213420334
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1248024126
Short name T162
Test name
Test status
Simulation time 8588042956 ps
CPU time 15.08 seconds
Started Jul 01 04:32:15 PM PDT 24
Finished Jul 01 04:32:41 PM PDT 24
Peak memory 212836 kb
Host smart-59a0c279-d807-4315-b098-6c52982987df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248024126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1248024126
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.19045941
Short name T352
Test name
Test status
Simulation time 9335604474 ps
CPU time 12.7 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:32:54 PM PDT 24
Peak memory 211248 kb
Host smart-d4e3be99-7117-46e5-9f02-62ec6ff265ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19045941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.19045941
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2570885622
Short name T268
Test name
Test status
Simulation time 77299594070 ps
CPU time 151.57 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:34:54 PM PDT 24
Peak memory 228652 kb
Host smart-584fd08f-ae77-42c7-bc56-60f5a42cb309
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570885622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2570885622
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2826796914
Short name T182
Test name
Test status
Simulation time 8565825940 ps
CPU time 22.42 seconds
Started Jul 01 04:32:12 PM PDT 24
Finished Jul 01 04:32:43 PM PDT 24
Peak memory 212124 kb
Host smart-0ec2f823-a6c0-472f-b217-3404a3ec92a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826796914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2826796914
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1038722617
Short name T137
Test name
Test status
Simulation time 1273150114 ps
CPU time 12.72 seconds
Started Jul 01 04:32:25 PM PDT 24
Finished Jul 01 04:32:54 PM PDT 24
Peak memory 211196 kb
Host smart-679268bf-0191-4a70-ab68-ecbcbe4a0235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038722617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1038722617
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.343502185
Short name T184
Test name
Test status
Simulation time 6517743065 ps
CPU time 32.84 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:32:58 PM PDT 24
Peak memory 214324 kb
Host smart-e436b906-130a-46e2-beeb-28e0f858cc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343502185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.343502185
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1635856052
Short name T47
Test name
Test status
Simulation time 6690380399 ps
CPU time 55.84 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:33:21 PM PDT 24
Peak memory 216820 kb
Host smart-239d35b5-de78-4701-b58d-609c626559ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635856052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1635856052
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1689168217
Short name T2
Test name
Test status
Simulation time 1185443868 ps
CPU time 10.91 seconds
Started Jul 01 04:32:15 PM PDT 24
Finished Jul 01 04:32:37 PM PDT 24
Peak memory 211232 kb
Host smart-349d3cd1-0cd8-41a0-9f64-a5c5f033514e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689168217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1689168217
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2134402992
Short name T217
Test name
Test status
Simulation time 4965870025 ps
CPU time 108.69 seconds
Started Jul 01 04:32:15 PM PDT 24
Finished Jul 01 04:34:14 PM PDT 24
Peak memory 236780 kb
Host smart-65cc4eed-363c-4baa-a9d6-adbe2b6756ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134402992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2134402992
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3265865765
Short name T9
Test name
Test status
Simulation time 10492719295 ps
CPU time 24.92 seconds
Started Jul 01 04:32:18 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 212328 kb
Host smart-19840e3e-8c10-42f6-97d7-8c1dbedb4f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265865765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3265865765
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2305672142
Short name T198
Test name
Test status
Simulation time 8610448680 ps
CPU time 15.86 seconds
Started Jul 01 04:32:22 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 211336 kb
Host smart-8658a5d2-7ab6-4c14-b98b-c6cacba6f7df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305672142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2305672142
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1820084138
Short name T179
Test name
Test status
Simulation time 747614093 ps
CPU time 10.38 seconds
Started Jul 01 04:32:22 PM PDT 24
Finished Jul 01 04:32:48 PM PDT 24
Peak memory 213492 kb
Host smart-d01a6aa3-876d-42bd-b914-d8d02cbaed7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820084138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1820084138
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3763216139
Short name T365
Test name
Test status
Simulation time 5277912035 ps
CPU time 32.93 seconds
Started Jul 01 04:32:21 PM PDT 24
Finished Jul 01 04:33:10 PM PDT 24
Peak memory 216616 kb
Host smart-a4bce246-51c0-4b78-bc86-2e83da6d45c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763216139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3763216139
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.851845307
Short name T54
Test name
Test status
Simulation time 49731324000 ps
CPU time 1864.96 seconds
Started Jul 01 04:32:22 PM PDT 24
Finished Jul 01 05:03:43 PM PDT 24
Peak memory 235840 kb
Host smart-f78e5992-e8af-4d45-9b6f-05c7ed7fffc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851845307 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.851845307
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4205220716
Short name T236
Test name
Test status
Simulation time 4994333381 ps
CPU time 11.76 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 211360 kb
Host smart-8acfcb67-de99-4211-b057-fba9b9ecf780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205220716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4205220716
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2012071940
Short name T159
Test name
Test status
Simulation time 1540778456 ps
CPU time 100.53 seconds
Started Jul 01 04:32:19 PM PDT 24
Finished Jul 01 04:34:14 PM PDT 24
Peak memory 237660 kb
Host smart-f5407f27-2a5c-4d60-a84a-4723062769a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012071940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2012071940
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.694032153
Short name T146
Test name
Test status
Simulation time 692466842 ps
CPU time 9.4 seconds
Started Jul 01 04:32:11 PM PDT 24
Finished Jul 01 04:32:30 PM PDT 24
Peak memory 211956 kb
Host smart-9ae51f1b-b1df-4d38-b1cf-90f897e9df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694032153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.694032153
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2908880702
Short name T187
Test name
Test status
Simulation time 1785344375 ps
CPU time 15.93 seconds
Started Jul 01 04:32:08 PM PDT 24
Finished Jul 01 04:32:32 PM PDT 24
Peak memory 211376 kb
Host smart-08b8d461-3c59-43c6-b017-a72467c0da52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908880702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2908880702
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.274328671
Short name T140
Test name
Test status
Simulation time 10012049339 ps
CPU time 23.49 seconds
Started Jul 01 04:32:18 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 214496 kb
Host smart-9f8f1784-096e-499f-832a-63d6906437b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274328671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.274328671
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2740556747
Short name T285
Test name
Test status
Simulation time 10351891281 ps
CPU time 53.19 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:33:33 PM PDT 24
Peak memory 219348 kb
Host smart-2d03b3af-c451-4813-b762-54027b2aa91d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740556747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2740556747
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4175340648
Short name T358
Test name
Test status
Simulation time 1287179298 ps
CPU time 11.64 seconds
Started Jul 01 04:32:10 PM PDT 24
Finished Jul 01 04:32:30 PM PDT 24
Peak memory 211256 kb
Host smart-dd4952ea-69c2-4c9d-a07a-714ed793a50c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175340648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4175340648
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3489759646
Short name T249
Test name
Test status
Simulation time 472246721730 ps
CPU time 317.52 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:37:40 PM PDT 24
Peak memory 232900 kb
Host smart-549c1691-f592-43e6-8115-7813e1ce5cd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489759646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3489759646
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4079444381
Short name T283
Test name
Test status
Simulation time 693431942 ps
CPU time 9.34 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:32:49 PM PDT 24
Peak memory 211984 kb
Host smart-987e8a6e-b375-4cff-9380-7016ffe54553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079444381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4079444381
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1330264076
Short name T319
Test name
Test status
Simulation time 7014786869 ps
CPU time 14.79 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 211368 kb
Host smart-34026f35-5f82-4051-9c9d-142d2c442167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330264076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1330264076
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4285236658
Short name T244
Test name
Test status
Simulation time 740474847 ps
CPU time 9.93 seconds
Started Jul 01 04:32:20 PM PDT 24
Finished Jul 01 04:32:46 PM PDT 24
Peak memory 213300 kb
Host smart-c6763164-33dc-4e97-8bad-56c3a93b451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285236658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4285236658
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2366168269
Short name T332
Test name
Test status
Simulation time 12158255535 ps
CPU time 62.34 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:33:45 PM PDT 24
Peak memory 217008 kb
Host smart-ccca90b4-cff4-45c5-b05b-e217f55e1d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366168269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2366168269
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3942074261
Short name T257
Test name
Test status
Simulation time 173368708630 ps
CPU time 3957.34 seconds
Started Jul 01 04:32:15 PM PDT 24
Finished Jul 01 05:38:23 PM PDT 24
Peak memory 235764 kb
Host smart-0cc22d02-a13e-4355-bfb1-13afb778b038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942074261 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3942074261
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3041639867
Short name T97
Test name
Test status
Simulation time 6175230721 ps
CPU time 13.51 seconds
Started Jul 01 04:32:18 PM PDT 24
Finished Jul 01 04:32:47 PM PDT 24
Peak memory 211392 kb
Host smart-6766cc5c-58c5-4696-86ad-d70ad58df0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041639867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3041639867
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2024760308
Short name T31
Test name
Test status
Simulation time 11447753093 ps
CPU time 114.88 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 211520 kb
Host smart-70565f72-c8b8-4c17-9281-bbec13ba89e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024760308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2024760308
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.674234686
Short name T173
Test name
Test status
Simulation time 4267259074 ps
CPU time 22.17 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:33:01 PM PDT 24
Peak memory 211800 kb
Host smart-22969859-c2a7-41c1-bbe2-ace2bcdb8167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674234686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.674234686
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2095871250
Short name T148
Test name
Test status
Simulation time 10458474618 ps
CPU time 13.07 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 211248 kb
Host smart-4fee5099-3e16-47cd-83bb-7c5cab6ae340
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095871250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2095871250
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.544263805
Short name T192
Test name
Test status
Simulation time 17512012867 ps
CPU time 37.03 seconds
Started Jul 01 04:32:22 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 213860 kb
Host smart-79e6205f-a4d4-4c72-a1af-55a4a6000210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544263805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.544263805
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.821463857
Short name T291
Test name
Test status
Simulation time 11621377574 ps
CPU time 52.2 seconds
Started Jul 01 04:32:11 PM PDT 24
Finished Jul 01 04:33:13 PM PDT 24
Peak memory 219476 kb
Host smart-46d57c1b-b022-4b62-b90f-23faff8a6958
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821463857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.821463857
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3162445216
Short name T234
Test name
Test status
Simulation time 1237878306 ps
CPU time 11.39 seconds
Started Jul 01 04:32:17 PM PDT 24
Finished Jul 01 04:32:41 PM PDT 24
Peak memory 211228 kb
Host smart-f83538a9-88de-481d-b8a3-00d610b454d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162445216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3162445216
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3254121357
Short name T10
Test name
Test status
Simulation time 8868510998 ps
CPU time 58.66 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:33:22 PM PDT 24
Peak memory 232856 kb
Host smart-cce7e1db-2bd2-4008-bbc9-c1e3d2863de2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254121357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3254121357
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1278227183
Short name T164
Test name
Test status
Simulation time 14984019553 ps
CPU time 30.84 seconds
Started Jul 01 04:32:21 PM PDT 24
Finished Jul 01 04:33:08 PM PDT 24
Peak memory 212256 kb
Host smart-5eaca25d-52e6-406d-b215-f435e0871ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278227183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1278227183
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1389175732
Short name T361
Test name
Test status
Simulation time 313479139 ps
CPU time 7.57 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:32:47 PM PDT 24
Peak memory 211376 kb
Host smart-845b50b4-11c3-4c68-afaf-1375254db08a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389175732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1389175732
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1368241901
Short name T190
Test name
Test status
Simulation time 2108241642 ps
CPU time 13.57 seconds
Started Jul 01 04:32:25 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 212020 kb
Host smart-79fa3a11-8c24-47be-8511-46ba04af04c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368241901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1368241901
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3840416075
Short name T165
Test name
Test status
Simulation time 11637829137 ps
CPU time 55.33 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:33:19 PM PDT 24
Peak memory 214132 kb
Host smart-1eda161c-c49b-4189-ab70-754d5d973160
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840416075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3840416075
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3113936965
Short name T50
Test name
Test status
Simulation time 555736273254 ps
CPU time 4017.43 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 05:39:40 PM PDT 24
Peak memory 252312 kb
Host smart-aa78382a-0572-4c39-b48a-809cb4b23c23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113936965 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.3113936965
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2240554004
Short name T142
Test name
Test status
Simulation time 1341703532 ps
CPU time 8.9 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:32:50 PM PDT 24
Peak memory 211260 kb
Host smart-2ad1b1fd-2578-4000-851c-d1ee4fc20d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240554004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2240554004
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3132375224
Short name T262
Test name
Test status
Simulation time 25877065256 ps
CPU time 246.72 seconds
Started Jul 01 04:32:29 PM PDT 24
Finished Jul 01 04:36:53 PM PDT 24
Peak memory 237820 kb
Host smart-4ef6651e-28a9-4dc5-8728-3545d183da74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132375224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3132375224
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.958963278
Short name T351
Test name
Test status
Simulation time 2691321470 ps
CPU time 17.38 seconds
Started Jul 01 04:32:16 PM PDT 24
Finished Jul 01 04:32:44 PM PDT 24
Peak memory 212120 kb
Host smart-929077a9-11ca-44f9-aed0-fb0afc5ee36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958963278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.958963278
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.340598775
Short name T151
Test name
Test status
Simulation time 1708789278 ps
CPU time 14.07 seconds
Started Jul 01 04:32:21 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 211288 kb
Host smart-10082fef-b8cd-4120-b66e-285f892e81c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340598775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.340598775
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3953060203
Short name T144
Test name
Test status
Simulation time 1715529826 ps
CPU time 10.29 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:32:35 PM PDT 24
Peak memory 213136 kb
Host smart-e62ba5f2-8c49-4789-92e0-eea9e69a4ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953060203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3953060203
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4124164293
Short name T8
Test name
Test status
Simulation time 4659306985 ps
CPU time 48.59 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:33:32 PM PDT 24
Peak memory 219288 kb
Host smart-2c7af333-4421-416a-812a-4a3d49563478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124164293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4124164293
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.303479500
Short name T115
Test name
Test status
Simulation time 869493134931 ps
CPU time 2951.37 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 05:21:54 PM PDT 24
Peak memory 245960 kb
Host smart-7f0a349f-5fa9-46f2-98fd-49943e077da0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303479500 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.303479500
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2582482023
Short name T105
Test name
Test status
Simulation time 18517229135 ps
CPU time 13.52 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 211244 kb
Host smart-844d3a9e-8c1b-4799-86dc-8004741912de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582482023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2582482023
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2594471273
Short name T149
Test name
Test status
Simulation time 18074318491 ps
CPU time 199.18 seconds
Started Jul 01 04:32:49 PM PDT 24
Finished Jul 01 04:36:20 PM PDT 24
Peak memory 212492 kb
Host smart-3e8394ee-6e82-49aa-95ad-81399728954f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594471273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2594471273
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1248201609
Short name T43
Test name
Test status
Simulation time 1844571118 ps
CPU time 9.54 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:32:50 PM PDT 24
Peak memory 212332 kb
Host smart-b1b36ff0-c79f-4475-9d85-56c574ad424e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248201609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1248201609
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1702684105
Short name T273
Test name
Test status
Simulation time 2059373431 ps
CPU time 11.21 seconds
Started Jul 01 04:32:34 PM PDT 24
Finished Jul 01 04:33:01 PM PDT 24
Peak memory 211284 kb
Host smart-01f2f0f3-ac07-434e-8f79-8ce47304ca0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1702684105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1702684105
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.99208539
Short name T102
Test name
Test status
Simulation time 644187701 ps
CPU time 9.84 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:32:49 PM PDT 24
Peak memory 212804 kb
Host smart-8611e525-8035-4580-b390-b69fc6fb5882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99208539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.99208539
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1632008832
Short name T163
Test name
Test status
Simulation time 49170530052 ps
CPU time 32.6 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:33:14 PM PDT 24
Peak memory 215356 kb
Host smart-36a8a7e6-c65f-47fe-ab92-5262aec45b9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632008832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1632008832
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1096330447
Short name T189
Test name
Test status
Simulation time 689774003 ps
CPU time 4.29 seconds
Started Jul 01 04:32:22 PM PDT 24
Finished Jul 01 04:32:42 PM PDT 24
Peak memory 211332 kb
Host smart-b3f4b02c-0d73-44f0-b5a7-03a69c25f6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096330447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1096330447
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.226574062
Short name T199
Test name
Test status
Simulation time 38233029401 ps
CPU time 151.37 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:35:15 PM PDT 24
Peak memory 239668 kb
Host smart-a168a027-77f0-43ef-8abd-8bc4674f0aa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226574062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.226574062
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3301178107
Short name T325
Test name
Test status
Simulation time 2882141182 ps
CPU time 22.9 seconds
Started Jul 01 04:32:48 PM PDT 24
Finished Jul 01 04:33:22 PM PDT 24
Peak memory 211844 kb
Host smart-a2dbac73-f9a6-4e9e-ba05-e1d137237562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301178107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3301178107
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3853697332
Short name T275
Test name
Test status
Simulation time 1784429151 ps
CPU time 13.86 seconds
Started Jul 01 04:32:34 PM PDT 24
Finished Jul 01 04:33:03 PM PDT 24
Peak memory 211248 kb
Host smart-4a0a0a52-0763-4dba-98eb-444a7c78af39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853697332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3853697332
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1570730542
Short name T145
Test name
Test status
Simulation time 4127961738 ps
CPU time 26.44 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 213832 kb
Host smart-59c2f23d-f196-492d-b6b3-ccaa68fe15b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570730542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1570730542
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3990550422
Short name T14
Test name
Test status
Simulation time 55042669106 ps
CPU time 81.32 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:34:01 PM PDT 24
Peak memory 219420 kb
Host smart-04905f09-b77e-4171-a2e7-d23f961ec569
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990550422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3990550422
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3475566940
Short name T290
Test name
Test status
Simulation time 204655873 ps
CPU time 4.37 seconds
Started Jul 01 04:31:57 PM PDT 24
Finished Jul 01 04:32:11 PM PDT 24
Peak memory 211372 kb
Host smart-162d6009-99f8-4c75-9e8c-6cb2840fa082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475566940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3475566940
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1785588663
Short name T98
Test name
Test status
Simulation time 1314308994 ps
CPU time 85.23 seconds
Started Jul 01 04:32:08 PM PDT 24
Finished Jul 01 04:33:41 PM PDT 24
Peak memory 237708 kb
Host smart-b7d3c4ff-ed03-417a-9fc0-63cdcbbc4cdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785588663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1785588663
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1056483860
Short name T44
Test name
Test status
Simulation time 665340446 ps
CPU time 9.37 seconds
Started Jul 01 04:31:53 PM PDT 24
Finished Jul 01 04:32:13 PM PDT 24
Peak memory 211852 kb
Host smart-c5289ca9-5bae-40ba-8bad-9d681694bc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056483860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1056483860
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1167401929
Short name T99
Test name
Test status
Simulation time 1160493681 ps
CPU time 7.18 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:17 PM PDT 24
Peak memory 211260 kb
Host smart-7f5f573a-a5ef-40cc-a5e5-9470d8d6f719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167401929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1167401929
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.329628899
Short name T265
Test name
Test status
Simulation time 9233965141 ps
CPU time 19.75 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:32:24 PM PDT 24
Peak memory 214260 kb
Host smart-a3b49f03-d8e9-47cb-abfe-409106847488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329628899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.329628899
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1914103055
Short name T369
Test name
Test status
Simulation time 4522140851 ps
CPU time 23.01 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:32:29 PM PDT 24
Peak memory 217564 kb
Host smart-8da2533a-3a04-4100-893a-344466d6cc43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914103055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1914103055
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.460642251
Short name T363
Test name
Test status
Simulation time 168217041 ps
CPU time 4.31 seconds
Started Jul 01 04:32:19 PM PDT 24
Finished Jul 01 04:32:39 PM PDT 24
Peak memory 211336 kb
Host smart-1b76b93b-bd64-4a03-bc48-3b46912b759b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460642251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.460642251
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3160204593
Short name T320
Test name
Test status
Simulation time 196469006521 ps
CPU time 478.13 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:40:38 PM PDT 24
Peak memory 234812 kb
Host smart-dc64b7f1-c34d-4c0c-960b-40e84fb8d7dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160204593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3160204593
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2124258901
Short name T132
Test name
Test status
Simulation time 4452386745 ps
CPU time 34.12 seconds
Started Jul 01 04:32:22 PM PDT 24
Finished Jul 01 04:33:11 PM PDT 24
Peak memory 211356 kb
Host smart-a9c84715-d590-4ed1-a1f1-69da66e34b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124258901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2124258901
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4065162809
Short name T311
Test name
Test status
Simulation time 1164271150 ps
CPU time 12.55 seconds
Started Jul 01 04:32:18 PM PDT 24
Finished Jul 01 04:32:46 PM PDT 24
Peak memory 211284 kb
Host smart-a6094aad-f1e0-4d5e-87b6-e1543f920f88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065162809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4065162809
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3167987516
Short name T253
Test name
Test status
Simulation time 1402083927 ps
CPU time 15.16 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:33:01 PM PDT 24
Peak memory 213680 kb
Host smart-fac39ce9-06e3-4007-83b7-bea3e7040223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167987516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3167987516
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.650941906
Short name T298
Test name
Test status
Simulation time 13397965898 ps
CPU time 83.69 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:34:06 PM PDT 24
Peak memory 215540 kb
Host smart-343aae74-325e-43fa-89de-1ec5b5b50516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650941906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.650941906
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.664740349
Short name T23
Test name
Test status
Simulation time 18944712424 ps
CPU time 1828.39 seconds
Started Jul 01 04:32:25 PM PDT 24
Finished Jul 01 05:03:10 PM PDT 24
Peak memory 235584 kb
Host smart-07e0595c-6af8-4853-8daa-1e3c527ece99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664740349 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.664740349
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2812250931
Short name T133
Test name
Test status
Simulation time 89330895 ps
CPU time 4.31 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:32:44 PM PDT 24
Peak memory 211348 kb
Host smart-fd26089e-1f89-4439-8373-44667eebf7ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812250931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2812250931
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3560730089
Short name T260
Test name
Test status
Simulation time 34467044347 ps
CPU time 337.96 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:38:18 PM PDT 24
Peak memory 228660 kb
Host smart-1c9e2cac-1178-438f-853b-19e7b0f09132
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560730089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3560730089
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1122724569
Short name T226
Test name
Test status
Simulation time 11764083280 ps
CPU time 24.88 seconds
Started Jul 01 04:32:25 PM PDT 24
Finished Jul 01 04:33:06 PM PDT 24
Peak memory 212248 kb
Host smart-c607eadc-bdce-43fe-98dd-a7d13440ce08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122724569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1122724569
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.4062603949
Short name T168
Test name
Test status
Simulation time 1900286537 ps
CPU time 8.23 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 211288 kb
Host smart-7d659d29-c24b-46a3-a3f6-c2ab08c8adda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062603949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.4062603949
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.620804947
Short name T79
Test name
Test status
Simulation time 446926864 ps
CPU time 13.52 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 213408 kb
Host smart-9327c254-2269-468a-9960-d3b6430bddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620804947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.620804947
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3430644865
Short name T53
Test name
Test status
Simulation time 120236527541 ps
CPU time 3868.77 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 05:37:12 PM PDT 24
Peak memory 252212 kb
Host smart-af21a7c8-b20c-40c0-8e88-0234069510f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430644865 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3430644865
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.17144681
Short name T193
Test name
Test status
Simulation time 1481383075 ps
CPU time 12.92 seconds
Started Jul 01 04:32:25 PM PDT 24
Finished Jul 01 04:32:54 PM PDT 24
Peak memory 211404 kb
Host smart-28d976a8-91b6-405b-8fc4-cfa7623f4304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17144681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.17144681
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.636959585
Short name T202
Test name
Test status
Simulation time 2351980175 ps
CPU time 48.7 seconds
Started Jul 01 04:32:41 PM PDT 24
Finished Jul 01 04:33:43 PM PDT 24
Peak memory 236588 kb
Host smart-38d06d61-b71e-4f5f-9b20-e0c2cfca2e2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636959585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.636959585
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2705715184
Short name T237
Test name
Test status
Simulation time 3661948003 ps
CPU time 21.23 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:33:07 PM PDT 24
Peak memory 211348 kb
Host smart-3e16e7ea-c7f8-492a-8d91-0fac855148b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705715184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2705715184
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4168890220
Short name T135
Test name
Test status
Simulation time 1274017259 ps
CPU time 12.6 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:32:52 PM PDT 24
Peak memory 211280 kb
Host smart-70f315da-a750-4b6e-a622-7768f0518ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168890220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4168890220
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2804888094
Short name T81
Test name
Test status
Simulation time 13818920604 ps
CPU time 19.83 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:33:04 PM PDT 24
Peak memory 214156 kb
Host smart-882d5214-f7b6-4a7a-9fad-f6c814f02b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804888094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2804888094
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2254465736
Short name T248
Test name
Test status
Simulation time 581804411 ps
CPU time 18.21 seconds
Started Jul 01 04:32:44 PM PDT 24
Finished Jul 01 04:33:15 PM PDT 24
Peak memory 212384 kb
Host smart-0d4ece9f-42be-4610-a707-f8843a8ee592
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254465736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2254465736
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3871443216
Short name T136
Test name
Test status
Simulation time 5849075405 ps
CPU time 13.12 seconds
Started Jul 01 04:32:22 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 211500 kb
Host smart-0cd73833-a6b5-4fe7-b665-fa6dd3c3d22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871443216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3871443216
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.741751691
Short name T218
Test name
Test status
Simulation time 20407811186 ps
CPU time 192.05 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:35:56 PM PDT 24
Peak memory 237868 kb
Host smart-93027428-814a-4872-820f-2e66c0377539
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741751691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.741751691
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4176358481
Short name T6
Test name
Test status
Simulation time 3272726661 ps
CPU time 20.24 seconds
Started Jul 01 04:32:43 PM PDT 24
Finished Jul 01 04:33:16 PM PDT 24
Peak memory 211996 kb
Host smart-6beabba2-99bf-4208-a45d-74601002f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176358481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4176358481
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2473024797
Short name T242
Test name
Test status
Simulation time 8545667158 ps
CPU time 12.72 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:57 PM PDT 24
Peak memory 211436 kb
Host smart-70ecd9fe-3d13-4bc1-9c3d-e9e3d902cc60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473024797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2473024797
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2769697026
Short name T155
Test name
Test status
Simulation time 9817870204 ps
CPU time 25.52 seconds
Started Jul 01 04:32:53 PM PDT 24
Finished Jul 01 04:33:29 PM PDT 24
Peak memory 214140 kb
Host smart-52568dec-725e-464e-ab35-d7184647ec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769697026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2769697026
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2660245857
Short name T180
Test name
Test status
Simulation time 2954980474 ps
CPU time 28.72 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:33:11 PM PDT 24
Peak memory 214272 kb
Host smart-2b7adc12-b638-4f52-977c-735ef7044fe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660245857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2660245857
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1652296900
Short name T210
Test name
Test status
Simulation time 505358110 ps
CPU time 6.01 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:50 PM PDT 24
Peak memory 211332 kb
Host smart-d5cdff90-c76f-45b2-bd09-67f692d2bef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652296900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1652296900
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1650039095
Short name T344
Test name
Test status
Simulation time 4043362852 ps
CPU time 111.19 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:34:35 PM PDT 24
Peak memory 235216 kb
Host smart-c76e9c12-827e-4fa4-b312-c5819696bbeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650039095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1650039095
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1546210226
Short name T170
Test name
Test status
Simulation time 8394225205 ps
CPU time 35.01 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:33:16 PM PDT 24
Peak memory 212384 kb
Host smart-4cb96214-72fd-4c9e-80e1-d3ce2755456c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546210226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1546210226
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2765719418
Short name T211
Test name
Test status
Simulation time 2358953234 ps
CPU time 8.11 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:52 PM PDT 24
Peak memory 211436 kb
Host smart-19a05052-78ac-44f4-b69f-83a528f1d7b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765719418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2765719418
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.881646835
Short name T296
Test name
Test status
Simulation time 638691374 ps
CPU time 9.87 seconds
Started Jul 01 04:32:24 PM PDT 24
Finished Jul 01 04:32:51 PM PDT 24
Peak memory 213404 kb
Host smart-650ee99f-b33b-4ca7-a9e4-95455f58c6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881646835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.881646835
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3515898446
Short name T212
Test name
Test status
Simulation time 7061665550 ps
CPU time 37.04 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:33:22 PM PDT 24
Peak memory 214044 kb
Host smart-3b500df7-71e3-45b4-9cf5-53382891eced
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515898446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3515898446
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3628323332
Short name T223
Test name
Test status
Simulation time 1898297056 ps
CPU time 15.22 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:32:59 PM PDT 24
Peak memory 211332 kb
Host smart-7d989bfa-8105-4aec-b757-764471f3a6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628323332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3628323332
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.815704653
Short name T15
Test name
Test status
Simulation time 26714457256 ps
CPU time 264.37 seconds
Started Jul 01 04:32:25 PM PDT 24
Finished Jul 01 04:37:05 PM PDT 24
Peak memory 234220 kb
Host smart-ad7f643b-70e1-46ae-8201-1fe5a035ca35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815704653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.815704653
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1823992955
Short name T21
Test name
Test status
Simulation time 13088588144 ps
CPU time 29.28 seconds
Started Jul 01 04:32:23 PM PDT 24
Finished Jul 01 04:33:09 PM PDT 24
Peak memory 212252 kb
Host smart-bfe055ca-092f-4f93-b45e-b5609da531c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823992955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1823992955
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.508875869
Short name T241
Test name
Test status
Simulation time 3112157836 ps
CPU time 13.72 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:32:58 PM PDT 24
Peak memory 211252 kb
Host smart-2e25bff2-e030-41e6-a775-9102530cc289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508875869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.508875869
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.4221716692
Short name T233
Test name
Test status
Simulation time 5746692066 ps
CPU time 28.92 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:33:11 PM PDT 24
Peak memory 213576 kb
Host smart-fff11bbc-cd0d-4736-9d4a-73ad013a47c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221716692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4221716692
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2019903492
Short name T250
Test name
Test status
Simulation time 3914895931 ps
CPU time 54.57 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:33:40 PM PDT 24
Peak memory 216644 kb
Host smart-af9ca7ee-b051-46d9-9356-38e87c81e873
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019903492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2019903492
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3811478724
Short name T20
Test name
Test status
Simulation time 2015530836 ps
CPU time 10.96 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:32:55 PM PDT 24
Peak memory 211372 kb
Host smart-9a88434c-2de0-4a2a-a1f0-e854de1111d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811478724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3811478724
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.418115050
Short name T240
Test name
Test status
Simulation time 2117929282 ps
CPU time 126.57 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:34:53 PM PDT 24
Peak memory 225880 kb
Host smart-b4d28b10-6867-49c3-a56b-b386965ca935
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418115050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.418115050
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3310189336
Short name T34
Test name
Test status
Simulation time 3349694801 ps
CPU time 17.51 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:33:03 PM PDT 24
Peak memory 211944 kb
Host smart-07435f11-6153-4123-bd02-571b4130ec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310189336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3310189336
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3969512460
Short name T307
Test name
Test status
Simulation time 3881036692 ps
CPU time 16.31 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 211368 kb
Host smart-edbe1ad6-1b72-486d-adb6-6a823d7a2178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969512460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3969512460
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1328003559
Short name T247
Test name
Test status
Simulation time 4258725840 ps
CPU time 23.48 seconds
Started Jul 01 04:32:43 PM PDT 24
Finished Jul 01 04:33:19 PM PDT 24
Peak memory 212504 kb
Host smart-b049150a-3307-446c-ade9-3a0fde8a9708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328003559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1328003559
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2688835019
Short name T299
Test name
Test status
Simulation time 22683661496 ps
CPU time 88.97 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:34:11 PM PDT 24
Peak memory 219288 kb
Host smart-79430862-9774-4813-a4f0-06648dfd64b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688835019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2688835019
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3811740695
Short name T288
Test name
Test status
Simulation time 249366650 ps
CPU time 6.16 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:32:52 PM PDT 24
Peak memory 210688 kb
Host smart-a59b2436-6c4d-4014-9d6a-e2c2c9025dcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811740695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3811740695
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.566577378
Short name T38
Test name
Test status
Simulation time 15396515307 ps
CPU time 116.7 seconds
Started Jul 01 04:32:26 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 228140 kb
Host smart-e9e4e943-24fa-4e31-bcf6-85961637f964
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566577378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.566577378
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2632366460
Short name T309
Test name
Test status
Simulation time 5835972502 ps
CPU time 19.67 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 212280 kb
Host smart-4a7fa192-e65b-4373-b494-88bf485a2337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632366460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2632366460
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2274641416
Short name T336
Test name
Test status
Simulation time 6646593307 ps
CPU time 13.78 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:33:00 PM PDT 24
Peak memory 211332 kb
Host smart-1d6f0591-fa39-4218-a46c-5264a128396a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2274641416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2274641416
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1324044431
Short name T366
Test name
Test status
Simulation time 2236495062 ps
CPU time 10.13 seconds
Started Jul 01 04:32:29 PM PDT 24
Finished Jul 01 04:32:57 PM PDT 24
Peak memory 213216 kb
Host smart-c553c07d-3212-4ff7-88e0-a7e5547aefb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324044431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1324044431
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4138406760
Short name T329
Test name
Test status
Simulation time 390223153 ps
CPU time 13.46 seconds
Started Jul 01 04:32:25 PM PDT 24
Finished Jul 01 04:32:54 PM PDT 24
Peak memory 214392 kb
Host smart-152ede61-dd74-429d-a368-d69847a24c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138406760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4138406760
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2073750371
Short name T267
Test name
Test status
Simulation time 44826897055 ps
CPU time 799.86 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:46:06 PM PDT 24
Peak memory 235732 kb
Host smart-0cf742d2-f344-4cd6-9c9a-7975415266bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073750371 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2073750371
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4224877975
Short name T61
Test name
Test status
Simulation time 333460454 ps
CPU time 4.15 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:48 PM PDT 24
Peak memory 211260 kb
Host smart-8f2ea04c-69d9-40ab-a258-05df4543e7e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224877975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4224877975
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.873472780
Short name T204
Test name
Test status
Simulation time 38985079260 ps
CPU time 197.92 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:36:03 PM PDT 24
Peak memory 228756 kb
Host smart-62a399f8-b513-49df-aca9-df7fdda11df3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873472780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.873472780
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1859981974
Short name T239
Test name
Test status
Simulation time 3522547132 ps
CPU time 22.94 seconds
Started Jul 01 04:32:46 PM PDT 24
Finished Jul 01 04:33:21 PM PDT 24
Peak memory 211912 kb
Host smart-ee6998a0-8206-49a3-8212-600ae975ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859981974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1859981974
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1591976625
Short name T112
Test name
Test status
Simulation time 895277371 ps
CPU time 6.79 seconds
Started Jul 01 04:32:34 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 211564 kb
Host smart-c939ad1a-f6c9-443a-95e9-c2d809af6529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591976625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1591976625
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2290249127
Short name T287
Test name
Test status
Simulation time 267001488 ps
CPU time 12.09 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:32:56 PM PDT 24
Peak memory 212336 kb
Host smart-aabb27e2-2f68-45ca-9e6c-a58812daf4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290249127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2290249127
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2536274537
Short name T293
Test name
Test status
Simulation time 2605487707 ps
CPU time 38.63 seconds
Started Jul 01 04:32:44 PM PDT 24
Finished Jul 01 04:33:36 PM PDT 24
Peak memory 216280 kb
Host smart-771d06ca-194c-4335-b20c-e166c772d4dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536274537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2536274537
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1819779555
Short name T330
Test name
Test status
Simulation time 89004964 ps
CPU time 4.45 seconds
Started Jul 01 04:32:42 PM PDT 24
Finished Jul 01 04:33:00 PM PDT 24
Peak memory 211436 kb
Host smart-77ac85a2-cbde-40ef-95fd-d8cffdb423c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819779555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1819779555
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1452465363
Short name T158
Test name
Test status
Simulation time 21613238848 ps
CPU time 194.53 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:36:00 PM PDT 24
Peak memory 211496 kb
Host smart-3996a80b-58f5-49d6-b84e-3587af0ae101
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452465363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1452465363
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2057413076
Short name T238
Test name
Test status
Simulation time 3850601347 ps
CPU time 31.85 seconds
Started Jul 01 04:32:27 PM PDT 24
Finished Jul 01 04:33:16 PM PDT 24
Peak memory 212064 kb
Host smart-59a7a0ef-99fb-4a6a-b64f-49eaee367ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057413076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2057413076
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3323684643
Short name T300
Test name
Test status
Simulation time 422776274 ps
CPU time 7.91 seconds
Started Jul 01 04:32:44 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 211180 kb
Host smart-920564c3-f007-43c6-ad07-723164c8153f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323684643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3323684643
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2868306085
Short name T129
Test name
Test status
Simulation time 13082410699 ps
CPU time 27.08 seconds
Started Jul 01 04:32:42 PM PDT 24
Finished Jul 01 04:33:22 PM PDT 24
Peak memory 214232 kb
Host smart-4fb97419-7456-4089-b6cf-85fdd7e9cc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868306085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2868306085
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.182771683
Short name T82
Test name
Test status
Simulation time 223687049 ps
CPU time 15.33 seconds
Started Jul 01 04:32:28 PM PDT 24
Finished Jul 01 04:33:02 PM PDT 24
Peak memory 213576 kb
Host smart-08972b1d-5b9c-4a49-84c0-e6d6f0ddec62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182771683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.182771683
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.895486731
Short name T65
Test name
Test status
Simulation time 555456738 ps
CPU time 7.82 seconds
Started Jul 01 04:31:46 PM PDT 24
Finished Jul 01 04:32:04 PM PDT 24
Peak memory 211332 kb
Host smart-b31d8842-9221-4ff0-a5ae-50bd45c9994f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895486731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.895486731
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1695708786
Short name T48
Test name
Test status
Simulation time 42325870988 ps
CPU time 423.1 seconds
Started Jul 01 04:31:53 PM PDT 24
Finished Jul 01 04:39:07 PM PDT 24
Peak memory 234020 kb
Host smart-7bb28fb3-79fc-4a5a-8486-e4705f658ea5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695708786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1695708786
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1162049821
Short name T131
Test name
Test status
Simulation time 6514523715 ps
CPU time 28.74 seconds
Started Jul 01 04:32:02 PM PDT 24
Finished Jul 01 04:32:40 PM PDT 24
Peak memory 212456 kb
Host smart-7238627d-f946-4057-b985-6fbe1de4b679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162049821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1162049821
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4204781142
Short name T322
Test name
Test status
Simulation time 375686033 ps
CPU time 5.67 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:32:10 PM PDT 24
Peak memory 211376 kb
Host smart-89e4f0fb-12df-4e53-afc2-1fd958995f0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204781142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4204781142
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4056299508
Short name T350
Test name
Test status
Simulation time 9174927230 ps
CPU time 16.92 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:32:23 PM PDT 24
Peak memory 214376 kb
Host smart-c26c6efc-7e8d-499c-b0a7-10e489c9f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056299508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4056299508
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3868590726
Short name T161
Test name
Test status
Simulation time 27454384438 ps
CPU time 40.17 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:32:47 PM PDT 24
Peak memory 216288 kb
Host smart-02b95c7d-80b1-4679-83cf-c45ec6909729
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868590726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3868590726
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.595387372
Short name T175
Test name
Test status
Simulation time 332878721 ps
CPU time 4.27 seconds
Started Jul 01 04:32:05 PM PDT 24
Finished Jul 01 04:32:18 PM PDT 24
Peak memory 211252 kb
Host smart-6a27e02c-d2b7-4ed8-9386-32dffb6c5743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595387372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.595387372
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.722285633
Short name T335
Test name
Test status
Simulation time 87744867477 ps
CPU time 319.18 seconds
Started Jul 01 04:31:45 PM PDT 24
Finished Jul 01 04:37:15 PM PDT 24
Peak memory 212604 kb
Host smart-37e6cfd7-06b1-47dd-8caf-ec32826c8c6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722285633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.722285633
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2937363740
Short name T323
Test name
Test status
Simulation time 1278779166 ps
CPU time 9.39 seconds
Started Jul 01 04:31:50 PM PDT 24
Finished Jul 01 04:32:10 PM PDT 24
Peak memory 211980 kb
Host smart-73e6b703-ae5a-4229-a940-af0e587e512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937363740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2937363740
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.938884481
Short name T245
Test name
Test status
Simulation time 3749705607 ps
CPU time 10.22 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:32:17 PM PDT 24
Peak memory 211320 kb
Host smart-8094a136-0bdc-4a25-9a10-f805a5c6a468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938884481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.938884481
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2191398796
Short name T341
Test name
Test status
Simulation time 6582164528 ps
CPU time 21.46 seconds
Started Jul 01 04:31:48 PM PDT 24
Finished Jul 01 04:32:21 PM PDT 24
Peak memory 214976 kb
Host smart-a1a83a32-b690-48c3-966b-4a692cbe5d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191398796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2191398796
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1118220325
Short name T181
Test name
Test status
Simulation time 10011173349 ps
CPU time 50.6 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:32:53 PM PDT 24
Peak memory 216272 kb
Host smart-86b37e48-e87c-4dda-a793-011082f8d4ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118220325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1118220325
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2581332927
Short name T364
Test name
Test status
Simulation time 2154787074 ps
CPU time 17.53 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:27 PM PDT 24
Peak memory 211420 kb
Host smart-7ba5357b-c397-4872-afa2-57e6bc1a74c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581332927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2581332927
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2261654712
Short name T4
Test name
Test status
Simulation time 39606318620 ps
CPU time 217.73 seconds
Started Jul 01 04:31:54 PM PDT 24
Finished Jul 01 04:35:42 PM PDT 24
Peak memory 237716 kb
Host smart-03bce835-4d56-4ca7-bb93-64cef0e406f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261654712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2261654712
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2466396745
Short name T160
Test name
Test status
Simulation time 3060107960 ps
CPU time 26.03 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:32:35 PM PDT 24
Peak memory 212096 kb
Host smart-d2013028-6320-48a9-a2e1-10fe820c5258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466396745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2466396745
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4275341218
Short name T174
Test name
Test status
Simulation time 191583053 ps
CPU time 5.69 seconds
Started Jul 01 04:31:57 PM PDT 24
Finished Jul 01 04:32:12 PM PDT 24
Peak memory 211272 kb
Host smart-358e3a74-fd84-4986-964d-571a6e9e802e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275341218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4275341218
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1305510995
Short name T362
Test name
Test status
Simulation time 192324445 ps
CPU time 10.39 seconds
Started Jul 01 04:31:50 PM PDT 24
Finished Jul 01 04:32:11 PM PDT 24
Peak memory 213036 kb
Host smart-15c11038-1f28-4ac0-ae73-dd15b477477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305510995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1305510995
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1046797191
Short name T281
Test name
Test status
Simulation time 5916851243 ps
CPU time 58.63 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 04:33:05 PM PDT 24
Peak memory 213636 kb
Host smart-9105fdd9-40bf-40d8-8ec1-32242c9bfbc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046797191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1046797191
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3428336887
Short name T29
Test name
Test status
Simulation time 834426579018 ps
CPU time 3231.68 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 05:25:58 PM PDT 24
Peak memory 252092 kb
Host smart-c04ccc8f-052c-4cee-b98f-9ca59a973fe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428336887 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3428336887
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3451724217
Short name T186
Test name
Test status
Simulation time 167822524 ps
CPU time 4.35 seconds
Started Jul 01 04:31:58 PM PDT 24
Finished Jul 01 04:32:12 PM PDT 24
Peak memory 211228 kb
Host smart-7e27df2b-f9e5-4968-8c57-f237b96c34ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451724217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3451724217
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3485318776
Short name T312
Test name
Test status
Simulation time 45608655237 ps
CPU time 313.39 seconds
Started Jul 01 04:31:55 PM PDT 24
Finished Jul 01 04:37:19 PM PDT 24
Peak memory 233860 kb
Host smart-27c748bd-55fa-48d9-9b75-751cc70c1cfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485318776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3485318776
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2648590426
Short name T313
Test name
Test status
Simulation time 347603743 ps
CPU time 9.14 seconds
Started Jul 01 04:31:59 PM PDT 24
Finished Jul 01 04:32:18 PM PDT 24
Peak memory 211856 kb
Host smart-12ad78ca-4743-4e65-b321-13d415d99f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648590426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2648590426
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.808032530
Short name T316
Test name
Test status
Simulation time 2123222104 ps
CPU time 12.27 seconds
Started Jul 01 04:32:17 PM PDT 24
Finished Jul 01 04:32:42 PM PDT 24
Peak memory 211348 kb
Host smart-d79c2492-a4e3-4f89-858c-c6849cfb25bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808032530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.808032530
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2147477911
Short name T303
Test name
Test status
Simulation time 362707160 ps
CPU time 10 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:32:23 PM PDT 24
Peak memory 213204 kb
Host smart-1f1c127d-6f31-47e7-8be3-d36fd7a6bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147477911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2147477911
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3467591869
Short name T301
Test name
Test status
Simulation time 826561640 ps
CPU time 22.02 seconds
Started Jul 01 04:32:01 PM PDT 24
Finished Jul 01 04:32:32 PM PDT 24
Peak memory 214840 kb
Host smart-2bb5814e-3889-45bc-a7ac-ac0455088d36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467591869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3467591869
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2079368376
Short name T141
Test name
Test status
Simulation time 416205829 ps
CPU time 5.81 seconds
Started Jul 01 04:32:02 PM PDT 24
Finished Jul 01 04:32:17 PM PDT 24
Peak memory 211332 kb
Host smart-51970521-dadd-419d-89d7-ca37236c3298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079368376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2079368376
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1630766483
Short name T3
Test name
Test status
Simulation time 3393961042 ps
CPU time 13.6 seconds
Started Jul 01 04:32:14 PM PDT 24
Finished Jul 01 04:32:36 PM PDT 24
Peak memory 211984 kb
Host smart-43ceb749-ed9a-4309-849b-ca61aeeb099f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630766483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1630766483
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2377344283
Short name T278
Test name
Test status
Simulation time 2389207300 ps
CPU time 16.12 seconds
Started Jul 01 04:32:04 PM PDT 24
Finished Jul 01 04:32:29 PM PDT 24
Peak memory 211656 kb
Host smart-c8a770de-5072-48ff-978e-593ea31eacde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377344283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2377344283
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2676060816
Short name T315
Test name
Test status
Simulation time 6023982465 ps
CPU time 26.5 seconds
Started Jul 01 04:31:52 PM PDT 24
Finished Jul 01 04:32:29 PM PDT 24
Peak memory 213636 kb
Host smart-b5576393-d0fa-4e12-87bc-9bb344f01233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676060816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2676060816
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.686521110
Short name T13
Test name
Test status
Simulation time 1194867146 ps
CPU time 21 seconds
Started Jul 01 04:32:02 PM PDT 24
Finished Jul 01 04:32:32 PM PDT 24
Peak memory 213668 kb
Host smart-113ce015-d37c-4d5b-ae0b-5d8493bd9e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686521110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.686521110
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.348802210
Short name T52
Test name
Test status
Simulation time 106350062121 ps
CPU time 4020.4 seconds
Started Jul 01 04:31:56 PM PDT 24
Finished Jul 01 05:39:07 PM PDT 24
Peak memory 247624 kb
Host smart-feceacb6-71ee-45d3-bb58-7c144e7c75bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348802210 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.348802210
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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